Archived
initial commit
This commit is contained in:
@@ -0,0 +1,40 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_hdmi_tx
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GENERIC_DEPS += ../common/ad_csc.v
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GENERIC_DEPS += ../common/ad_csc_RGB2CrYCb.v
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GENERIC_DEPS += ../common/ad_mem.v
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GENERIC_DEPS += ../common/ad_rst.v
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GENERIC_DEPS += ../common/ad_ss_444to422.v
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GENERIC_DEPS += ../common/up_axi.v
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GENERIC_DEPS += ../common/up_clock_mon.v
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GENERIC_DEPS += ../common/up_hdmi_tx.v
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GENERIC_DEPS += ../common/up_xfer_cntrl.v
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GENERIC_DEPS += ../common/up_xfer_status.v
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GENERIC_DEPS += axi_hdmi_tx.v
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GENERIC_DEPS += axi_hdmi_tx_core.v
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GENERIC_DEPS += axi_hdmi_tx_es.v
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GENERIC_DEPS += axi_hdmi_tx_vdma.v
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XILINX_DEPS += ../xilinx/common/ad_mul.v
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XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
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XILINX_DEPS += axi_hdmi_tx_constr.xdc
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XILINX_DEPS += axi_hdmi_tx_ip.tcl
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INTEL_DEPS += ../../library/scripts/adi_intel_device_info_enc.tcl
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INTEL_DEPS += ../intel/common/ad_mul.v
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INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc
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INTEL_DEPS += ../intel/common/up_rst_constr.sdc
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INTEL_DEPS += ../intel/common/up_xfer_cntrl_constr.sdc
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INTEL_DEPS += ../intel/common/up_xfer_status_constr.sdc
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INTEL_DEPS += axi_hdmi_tx_constr.sdc
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INTEL_DEPS += axi_hdmi_tx_hw.tcl
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include ../scripts/library.mk
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@@ -0,0 +1,3 @@
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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eof:
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@@ -0,0 +1,6 @@
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||||
<?xml version="1.0" encoding="UTF-8"?>
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||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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||||
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||||
<labtools version="1" minor="0"/>
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@@ -0,0 +1,342 @@
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// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
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||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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||||
//
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||||
// OR
|
||||
//
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||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
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||||
// ***************************************************************************
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||||
// ***************************************************************************
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`timescale 1ns/100ps
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module axi_hdmi_tx #(
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parameter ID = 0,
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parameter CR_CB_N = 0,
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parameter FPGA_TECHNOLOGY = 0,
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parameter INTERFACE = "16_BIT",
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parameter OUT_CLK_POLARITY = 0) (
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// hdmi interface
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input hdmi_clk,
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output hdmi_out_clk,
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// 16-bit interface
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output hdmi_16_hsync,
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output hdmi_16_vsync,
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output hdmi_16_data_e,
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output [15:0] hdmi_16_data,
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output [15:0] hdmi_16_es_data,
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// 24-bit interface
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output hdmi_24_hsync,
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output hdmi_24_vsync,
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output hdmi_24_data_e,
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output [23:0] hdmi_24_data,
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// 36-bit interface
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output hdmi_36_hsync,
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output hdmi_36_vsync,
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output hdmi_36_data_e,
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output [35:0] hdmi_36_data,
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// vdma interface
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input vdma_clk,
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input vdma_end_of_frame,
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input vdma_valid,
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input [63:0] vdma_data,
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output vdma_ready,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready);
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/* 0 = Launch on rising edge, 1 = Launch on falling edge */
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localparam EMBEDDED_SYNC = (INTERFACE == "16_BIT_EMBEDDED_SYNC") ? 1 : 0;
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localparam XILINX_7SERIES = 1;
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localparam XILINX_ULTRASCALE = 2;
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localparam INTEL_5SERIES = 101;
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// reset and clocks
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wire up_rstn;
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wire up_clk;
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wire hdmi_rst;
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wire vdma_rst;
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// internal signals
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire up_wack_s;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_rdata_s;
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wire up_rack_s;
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wire hdmi_csc_bypass_s;
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wire hdmi_ss_bypass_s;
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wire [ 1:0] hdmi_srcsel_s;
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wire [23:0] hdmi_const_rgb_s;
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wire [15:0] hdmi_hl_active_s;
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wire [15:0] hdmi_hl_width_s;
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wire [15:0] hdmi_hs_width_s;
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wire [15:0] hdmi_he_max_s;
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wire [15:0] hdmi_he_min_s;
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wire [15:0] hdmi_vf_active_s;
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wire [15:0] hdmi_vf_width_s;
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wire [15:0] hdmi_vs_width_s;
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wire [15:0] hdmi_ve_max_s;
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wire [15:0] hdmi_ve_min_s;
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wire [23:0] hdmi_clip_max_s;
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wire [23:0] hdmi_clip_min_s;
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wire hdmi_fs_toggle_s;
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wire [ 8:0] hdmi_raddr_g_s;
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wire hdmi_tpm_oos_s;
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wire hdmi_status_s;
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wire vdma_wr_s;
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wire [ 8:0] vdma_waddr_s;
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wire [47:0] vdma_wdata_s;
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wire vdma_fs_ret_toggle_s;
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wire [ 8:0] vdma_fs_waddr_s;
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wire vdma_ovf_s;
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wire vdma_unf_s;
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wire vdma_tpm_oos_s;
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// signal name changes
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assign up_rstn = s_axi_aresetn;
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assign up_clk = s_axi_aclk;
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// axi interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
|
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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||||
.up_axi_rdata (s_axi_rdata),
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||||
.up_axi_rready (s_axi_rready),
|
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.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
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||||
.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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// processor interface
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up_hdmi_tx i_up (
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.hdmi_clk (hdmi_clk),
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.hdmi_rst (hdmi_rst),
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||||
.hdmi_csc_bypass (hdmi_csc_bypass_s),
|
||||
.hdmi_ss_bypass (hdmi_ss_bypass_s),
|
||||
.hdmi_srcsel (hdmi_srcsel_s),
|
||||
.hdmi_const_rgb (hdmi_const_rgb_s),
|
||||
.hdmi_hl_active (hdmi_hl_active_s),
|
||||
.hdmi_hl_width (hdmi_hl_width_s),
|
||||
.hdmi_hs_width (hdmi_hs_width_s),
|
||||
.hdmi_he_max (hdmi_he_max_s),
|
||||
.hdmi_he_min (hdmi_he_min_s),
|
||||
.hdmi_vf_active (hdmi_vf_active_s),
|
||||
.hdmi_vf_width (hdmi_vf_width_s),
|
||||
.hdmi_vs_width (hdmi_vs_width_s),
|
||||
.hdmi_ve_max (hdmi_ve_max_s),
|
||||
.hdmi_ve_min (hdmi_ve_min_s),
|
||||
.hdmi_clip_max (hdmi_clip_max_s),
|
||||
.hdmi_clip_min (hdmi_clip_min_s),
|
||||
.hdmi_status (hdmi_status_s),
|
||||
.hdmi_tpm_oos (hdmi_tpm_oos_s),
|
||||
.hdmi_clk_ratio (32'd1),
|
||||
.vdma_clk (vdma_clk),
|
||||
.vdma_rst (vdma_rst),
|
||||
.vdma_ovf (vdma_ovf_s),
|
||||
.vdma_unf (vdma_unf_s),
|
||||
.vdma_tpm_oos (vdma_tpm_oos_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
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.up_rdata (up_rdata_s),
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||||
.up_rack (up_rack_s));
|
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|
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// vdma interface
|
||||
|
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axi_hdmi_tx_vdma i_vdma (
|
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.hdmi_fs_toggle (hdmi_fs_toggle_s),
|
||||
.hdmi_raddr_g (hdmi_raddr_g_s),
|
||||
.vdma_clk (vdma_clk),
|
||||
.vdma_rst (vdma_rst),
|
||||
.vdma_valid (vdma_valid),
|
||||
.vdma_data (vdma_data),
|
||||
.vdma_ready (vdma_ready),
|
||||
.vdma_end_of_frame (vdma_end_of_frame),
|
||||
.vdma_wr (vdma_wr_s),
|
||||
.vdma_waddr (vdma_waddr_s),
|
||||
.vdma_wdata (vdma_wdata_s),
|
||||
.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
|
||||
.vdma_fs_waddr (vdma_fs_waddr_s),
|
||||
.vdma_tpm_oos (vdma_tpm_oos_s),
|
||||
.vdma_ovf (vdma_ovf_s),
|
||||
.vdma_unf (vdma_unf_s));
|
||||
|
||||
// hdmi interface
|
||||
|
||||
axi_hdmi_tx_core #(
|
||||
.CR_CB_N(CR_CB_N),
|
||||
.EMBEDDED_SYNC(EMBEDDED_SYNC))
|
||||
i_tx_core (
|
||||
.hdmi_clk (hdmi_clk),
|
||||
.hdmi_rst (hdmi_rst),
|
||||
.hdmi_16_hsync (hdmi_16_hsync),
|
||||
.hdmi_16_vsync (hdmi_16_vsync),
|
||||
.hdmi_16_data_e (hdmi_16_data_e),
|
||||
.hdmi_16_data (hdmi_16_data),
|
||||
.hdmi_16_es_data (hdmi_16_es_data),
|
||||
.hdmi_24_hsync (hdmi_24_hsync),
|
||||
.hdmi_24_vsync (hdmi_24_vsync),
|
||||
.hdmi_24_data_e (hdmi_24_data_e),
|
||||
.hdmi_24_data (hdmi_24_data),
|
||||
.hdmi_36_hsync (hdmi_36_hsync),
|
||||
.hdmi_36_vsync (hdmi_36_vsync),
|
||||
.hdmi_36_data_e (hdmi_36_data_e),
|
||||
.hdmi_36_data (hdmi_36_data),
|
||||
.hdmi_fs_toggle (hdmi_fs_toggle_s),
|
||||
.hdmi_raddr_g (hdmi_raddr_g_s),
|
||||
.hdmi_tpm_oos (hdmi_tpm_oos_s),
|
||||
.hdmi_status (hdmi_status_s),
|
||||
.vdma_clk (vdma_clk),
|
||||
.vdma_wr (vdma_wr_s),
|
||||
.vdma_waddr (vdma_waddr_s),
|
||||
.vdma_wdata (vdma_wdata_s),
|
||||
.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
|
||||
.vdma_fs_waddr (vdma_fs_waddr_s),
|
||||
.hdmi_csc_bypass (hdmi_csc_bypass_s),
|
||||
.hdmi_ss_bypass (hdmi_ss_bypass_s),
|
||||
.hdmi_srcsel (hdmi_srcsel_s),
|
||||
.hdmi_const_rgb (hdmi_const_rgb_s),
|
||||
.hdmi_hl_active (hdmi_hl_active_s),
|
||||
.hdmi_hl_width (hdmi_hl_width_s),
|
||||
.hdmi_hs_width (hdmi_hs_width_s),
|
||||
.hdmi_he_max (hdmi_he_max_s),
|
||||
.hdmi_he_min (hdmi_he_min_s),
|
||||
.hdmi_vf_active (hdmi_vf_active_s),
|
||||
.hdmi_vf_width (hdmi_vf_width_s),
|
||||
.hdmi_vs_width (hdmi_vs_width_s),
|
||||
.hdmi_ve_max (hdmi_ve_max_s),
|
||||
.hdmi_ve_min (hdmi_ve_min_s),
|
||||
.hdmi_clip_max (hdmi_clip_max_s),
|
||||
.hdmi_clip_min (hdmi_clip_min_s));
|
||||
|
||||
// hdmi output clock
|
||||
|
||||
generate
|
||||
if (FPGA_TECHNOLOGY == XILINX_ULTRASCALE) begin
|
||||
ODDRE1 #(.SRVAL(1'b0)) i_clk_oddr (
|
||||
.SR (1'b0),
|
||||
.D1 (~OUT_CLK_POLARITY),
|
||||
.D2 (OUT_CLK_POLARITY),
|
||||
.C (hdmi_clk),
|
||||
.Q (hdmi_out_clk));
|
||||
end
|
||||
if (FPGA_TECHNOLOGY == INTEL_5SERIES) begin
|
||||
altddio_out #(.WIDTH(1)) i_clk_oddr (
|
||||
.aclr (1'b0),
|
||||
.aset (1'b0),
|
||||
.sclr (1'b0),
|
||||
.sset (1'b0),
|
||||
.oe (1'b1),
|
||||
.outclocken (1'b1),
|
||||
.datain_h (~OUT_CLK_POLARITY),
|
||||
.datain_l (OUT_CLK_POLARITY),
|
||||
.outclock (hdmi_clk),
|
||||
.oe_out (),
|
||||
.dataout (hdmi_out_clk));
|
||||
end
|
||||
if (FPGA_TECHNOLOGY == XILINX_7SERIES) begin
|
||||
ODDR #(.INIT(1'b0)) i_clk_oddr (
|
||||
.R (1'b0),
|
||||
.S (1'b0),
|
||||
.CE (1'b1),
|
||||
.D1 (~OUT_CLK_POLARITY),
|
||||
.D2 (OUT_CLK_POLARITY),
|
||||
.C (hdmi_clk),
|
||||
.Q (hdmi_out_clk));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,512 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
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|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,9 @@
|
||||
|
||||
set_false_path -from [get_registers *hdmi_fs_toggle*] -to [get_registers *vdma_fs_toggle_m1]
|
||||
set_false_path -from [get_registers *hdmi_raddr_g*] -to [get_registers *vdma_raddr_g_m1*]
|
||||
set_false_path -from [get_registers *vdma_fs_ret_toggle*] -to [get_registers *hdmi_fs_ret_toggle_m1]
|
||||
set_false_path -from [get_registers *vdma_fs_waddr*] -to [get_registers *hdmi_fs_waddr*]
|
||||
|
||||
set_false_path -from [get_registers *up_xfer_status:i_vdma_xfer_status|up_xfer_toggle*] -to [get_registers *up_xfer_status:i_vdma_xfer_status|d_xfer_state_m1*]
|
||||
set_false_path -from [get_registers *up_xfer_status:i_vdma_xfer_status|d_xfer_toggle*] -to [get_registers *up_xfer_status:i_vdma_xfer_status|up_xfer_toggle_m1*]
|
||||
set_false_path -from [get_registers *up_xfer_status:i_vdma_xfer_status|d_xfer_data*] -to [get_registers *up_xfer_status:i_vdma_xfer_status|up_data_status*]
|
||||
@@ -0,0 +1,10 @@
|
||||
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *vdma_fs_toggle*}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *vdma_raddr_g*}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *hdmi_fs_ret_toggle*}]
|
||||
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *hdmi_fs_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *vdma_fs_toggle_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *hdmi_raddr_g* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *vdma_raddr_g_m1* && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *vdma_fs_ret_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *hdmi_fs_ret_toggle_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *vdma_fs_waddr* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *hdmi_fs_waddr* && IS_SEQUENTIAL}]
|
||||
|
||||
@@ -0,0 +1,571 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Transmit HDMI, video dma data in, hdmi separate syncs data out.
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_hdmi_tx_core #(
|
||||
|
||||
parameter CR_CB_N = 0,
|
||||
parameter EMBEDDED_SYNC = 0) (
|
||||
|
||||
// hdmi interface
|
||||
|
||||
input hdmi_clk,
|
||||
input hdmi_rst,
|
||||
|
||||
// 16-bit interface
|
||||
|
||||
output reg hdmi_16_hsync,
|
||||
output reg hdmi_16_vsync,
|
||||
output reg hdmi_16_data_e,
|
||||
output reg [15:0] hdmi_16_data,
|
||||
output reg [15:0] hdmi_16_es_data,
|
||||
|
||||
// 24-bit interface
|
||||
|
||||
output reg hdmi_24_hsync,
|
||||
output reg hdmi_24_vsync,
|
||||
output reg hdmi_24_data_e,
|
||||
output reg [23:0] hdmi_24_data,
|
||||
|
||||
// 36-bit interface
|
||||
|
||||
output reg hdmi_36_hsync,
|
||||
output reg hdmi_36_vsync,
|
||||
output reg hdmi_36_data_e,
|
||||
output reg [35:0] hdmi_36_data,
|
||||
|
||||
// control signals
|
||||
|
||||
output reg hdmi_fs_toggle,
|
||||
output reg [ 8:0] hdmi_raddr_g,
|
||||
output reg hdmi_tpm_oos,
|
||||
output reg hdmi_status,
|
||||
|
||||
// vdma interface
|
||||
|
||||
input vdma_clk,
|
||||
input vdma_wr,
|
||||
input [ 8:0] vdma_waddr,
|
||||
input [47:0] vdma_wdata,
|
||||
input vdma_fs_ret_toggle,
|
||||
input [ 8:0] vdma_fs_waddr,
|
||||
|
||||
// processor interface
|
||||
|
||||
input hdmi_csc_bypass,
|
||||
input hdmi_ss_bypass,
|
||||
input [ 1:0] hdmi_srcsel,
|
||||
input [23:0] hdmi_const_rgb,
|
||||
input [15:0] hdmi_hl_active,
|
||||
input [15:0] hdmi_hl_width,
|
||||
input [15:0] hdmi_hs_width,
|
||||
input [15:0] hdmi_he_max,
|
||||
input [15:0] hdmi_he_min,
|
||||
input [15:0] hdmi_vf_active,
|
||||
input [15:0] hdmi_vf_width,
|
||||
input [15:0] hdmi_vs_width,
|
||||
input [15:0] hdmi_ve_max,
|
||||
input [15:0] hdmi_ve_min,
|
||||
input [23:0] hdmi_clip_max,
|
||||
input [23:0] hdmi_clip_min);
|
||||
|
||||
|
||||
// internal registers
|
||||
|
||||
reg hdmi_enable = 'd0;
|
||||
reg [15:0] hdmi_hs_count = 'd0;
|
||||
reg [15:0] hdmi_vs_count = 'd0;
|
||||
reg hdmi_fs = 'd0;
|
||||
reg hdmi_fs_ret_toggle_m1 = 'd0;
|
||||
reg hdmi_fs_ret_toggle_m2 = 'd0;
|
||||
reg hdmi_fs_ret_toggle_m3 = 'd0;
|
||||
reg hdmi_fs_ret = 'd0;
|
||||
reg [ 8:0] hdmi_fs_waddr = 'd0;
|
||||
reg hdmi_hs = 'd0;
|
||||
reg hdmi_vs = 'd0;
|
||||
reg hdmi_hs_de = 'd0;
|
||||
reg hdmi_vs_de = 'd0;
|
||||
reg [ 9:0] hdmi_raddr = 'd0;
|
||||
reg hdmi_hs_d = 'd0;
|
||||
reg hdmi_vs_d = 'd0;
|
||||
reg hdmi_hs_de_d = 'd0;
|
||||
reg hdmi_vs_de_d = 'd0;
|
||||
reg hdmi_de_d = 'd0;
|
||||
reg hdmi_data_sel_d = 'd0;
|
||||
reg hdmi_hs_2d = 'd0;
|
||||
reg hdmi_vs_2d = 'd0;
|
||||
reg hdmi_hs_de_2d = 'd0;
|
||||
reg hdmi_vs_de_2d = 'd0;
|
||||
reg hdmi_de_2d = 'd0;
|
||||
reg hdmi_data_sel_2d = 'd0;
|
||||
reg [47:0] hdmi_data_2d = 'd0;
|
||||
reg [23:0] hdmi_tpm_data = 'd0;
|
||||
reg hdmi_hsync = 'd0;
|
||||
reg hdmi_vsync = 'd0;
|
||||
reg hdmi_hsync_data_e = 'd0;
|
||||
reg hdmi_vsync_data_e = 'd0;
|
||||
reg hdmi_data_e = 'd0;
|
||||
reg [23:0] hdmi_data = 'd0;
|
||||
reg hdmi_24_csc_hsync = 'd0;
|
||||
reg hdmi_24_csc_vsync = 'd0;
|
||||
reg hdmi_24_csc_hsync_data_e = 'd0;
|
||||
reg hdmi_24_csc_vsync_data_e = 'd0;
|
||||
reg hdmi_24_csc_data_e = 'd0;
|
||||
reg [23:0] hdmi_24_csc_data = 'd0;
|
||||
reg hdmi_16_hsync_d = 'd0;
|
||||
reg hdmi_16_vsync_d = 'd0;
|
||||
reg hdmi_16_hsync_data_e_d = 'd0;
|
||||
reg hdmi_16_vsync_data_e_d = 'd0;
|
||||
reg hdmi_16_data_e_d = 'd0;
|
||||
reg [15:0] hdmi_16_data_d = 'd0;
|
||||
reg hdmi_es_hs_de = 'd0;
|
||||
reg hdmi_es_vs_de = 'd0;
|
||||
reg [15:0] hdmi_es_data = 'd0;
|
||||
reg [23:0] hdmi_clip_data = 'd0;
|
||||
reg hdmi_clip_hs_de_d = 'd0;
|
||||
reg hdmi_clip_vs_de_d = 'd0;
|
||||
reg hdmi_clip_hs_d = 'd0;
|
||||
reg hdmi_clip_vs_d = 'd0;
|
||||
reg hdmi_clip_de_d = 'd0;
|
||||
|
||||
// internal wires
|
||||
|
||||
wire [15:0] hdmi_hl_width_s;
|
||||
wire [15:0] hdmi_vf_width_s;
|
||||
wire [15:0] hdmi_he_width_s;
|
||||
wire [15:0] hdmi_ve_width_s;
|
||||
wire hdmi_fs_ret_s;
|
||||
wire hdmi_de_s;
|
||||
wire [47:0] hdmi_rdata_s;
|
||||
wire [23:0] hdmi_data_2d_s;
|
||||
wire hdmi_tpm_mismatch_s;
|
||||
wire [23:0] hdmi_tpg_data_s;
|
||||
wire hdmi_csc_hsync_s;
|
||||
wire hdmi_csc_vsync_s;
|
||||
wire hdmi_csc_hsync_data_e_s;
|
||||
wire hdmi_csc_vsync_data_e_s;
|
||||
wire hdmi_csc_data_e_s;
|
||||
wire [23:0] hdmi_csc_data_s;
|
||||
wire hdmi_ss_hsync_s;
|
||||
wire hdmi_ss_vsync_s;
|
||||
wire hdmi_ss_hsync_data_e_s;
|
||||
wire hdmi_ss_vsync_data_e_s;
|
||||
wire hdmi_ss_data_e_s;
|
||||
wire [15:0] hdmi_ss_data_s;
|
||||
wire [15:0] hdmi_es_data_s;
|
||||
|
||||
// binary to grey conversion
|
||||
|
||||
function [8:0] b2g;
|
||||
input [8:0] b;
|
||||
reg [8:0] g;
|
||||
begin
|
||||
g[8] = b[8];
|
||||
g[7] = b[8] ^ b[7];
|
||||
g[6] = b[7] ^ b[6];
|
||||
g[5] = b[6] ^ b[5];
|
||||
g[4] = b[5] ^ b[4];
|
||||
g[3] = b[4] ^ b[3];
|
||||
g[2] = b[3] ^ b[2];
|
||||
g[1] = b[2] ^ b[1];
|
||||
g[0] = b[1] ^ b[0];
|
||||
b2g = g;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// status and enable
|
||||
|
||||
always @(posedge hdmi_clk) begin
|
||||
if (hdmi_rst == 1'b1) begin
|
||||
hdmi_status <= 1'b0;
|
||||
hdmi_enable <= 1'b0;
|
||||
end else begin
|
||||
hdmi_status <= 1'b1;
|
||||
hdmi_enable <= hdmi_srcsel[1] | hdmi_srcsel[0];
|
||||
end
|
||||
end
|
||||
|
||||
// calculate useful limits
|
||||
|
||||
assign hdmi_hl_width_s = hdmi_hl_width - 1'b1;
|
||||
assign hdmi_vf_width_s = hdmi_vf_width - 1'b1;
|
||||
assign hdmi_he_width_s = hdmi_hl_width - (hdmi_hl_active + 1'b1);
|
||||
assign hdmi_ve_width_s = hdmi_vf_width - (hdmi_vf_active + 1'b1);
|
||||
|
||||
// hdmi counters
|
||||
|
||||
always @(posedge hdmi_clk) begin
|
||||
if (hdmi_hs_count >= hdmi_hl_width_s) begin
|
||||
hdmi_hs_count <= 0;
|
||||
end else begin
|
||||
hdmi_hs_count <= hdmi_hs_count + 1'b1;
|
||||
end
|
||||
if (hdmi_hs_count >= hdmi_hl_width_s) begin
|
||||
if (hdmi_vs_count >= hdmi_vf_width_s) begin
|
||||
hdmi_vs_count <= 0;
|
||||
end else begin
|
||||
hdmi_vs_count <= hdmi_vs_count + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// hdmi start of frame
|
||||
|
||||
always @(posedge hdmi_clk) begin
|
||||
if (hdmi_rst == 1'b1) begin
|
||||
hdmi_fs_toggle <= 1'b0;
|
||||
hdmi_fs <= 1'b0;
|
||||
end else begin
|
||||
if (EMBEDDED_SYNC == 1) begin
|
||||
if ((hdmi_hs_count == 1) && (hdmi_vs_count == hdmi_ve_width_s)) begin
|
||||
hdmi_fs <= hdmi_enable;
|
||||
end else begin
|
||||
hdmi_fs <= 1'b0;
|
||||
end
|
||||
end else begin
|
||||
if ((hdmi_hs_count == 1) && (hdmi_vs_count == hdmi_vs_width)) begin
|
||||
hdmi_fs <= hdmi_enable;
|
||||
end else begin
|
||||
hdmi_fs <= 1'b0;
|
||||
end
|
||||
end
|
||||
if (hdmi_fs == 1'b1) begin
|
||||
hdmi_fs_toggle <= ~hdmi_fs_toggle;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// hdmi sof write address
|
||||
|
||||
assign hdmi_fs_ret_s = hdmi_fs_ret_toggle_m2 ^ hdmi_fs_ret_toggle_m3;
|
||||
|
||||
always @(posedge hdmi_clk or posedge hdmi_rst) begin
|
||||
if (hdmi_rst == 1'b1) begin
|
||||
hdmi_fs_ret_toggle_m1 <= 1'd0;
|
||||
hdmi_fs_ret_toggle_m2 <= 1'd0;
|
||||
hdmi_fs_ret_toggle_m3 <= 1'd0;
|
||||
end else begin
|
||||
hdmi_fs_ret_toggle_m1 <= vdma_fs_ret_toggle;
|
||||
hdmi_fs_ret_toggle_m2 <= hdmi_fs_ret_toggle_m1;
|
||||
hdmi_fs_ret_toggle_m3 <= hdmi_fs_ret_toggle_m2;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge hdmi_clk) begin
|
||||
hdmi_fs_ret <= hdmi_fs_ret_s;
|
||||
hdmi_fs_waddr <= vdma_fs_waddr;
|
||||
end
|
||||
|
||||
// hdmi sync signals
|
||||
|
||||
always @(posedge hdmi_clk) begin
|
||||
if (EMBEDDED_SYNC == 1) begin
|
||||
hdmi_hs <= 1'b0;
|
||||
if (hdmi_hs_count <= hdmi_he_width_s) begin
|
||||
hdmi_hs_de <= 1'b0;
|
||||
end else begin
|
||||
hdmi_hs_de <= hdmi_enable;
|
||||
end
|
||||
if (hdmi_vs_count <= hdmi_ve_width_s) begin
|
||||
hdmi_vs_de <= 1'b0;
|
||||
end else begin
|
||||
hdmi_vs_de <= hdmi_enable;
|
||||
end
|
||||
end else begin
|
||||
if (hdmi_hs_count < hdmi_hs_width) begin
|
||||
hdmi_hs <= hdmi_enable;
|
||||
end else begin
|
||||
hdmi_hs <= 1'b0;
|
||||
end
|
||||
if (hdmi_vs_count < hdmi_vs_width) begin
|
||||
hdmi_vs <= hdmi_enable;
|
||||
end else begin
|
||||
hdmi_vs <= 1'b0;
|
||||
end
|
||||
if ((hdmi_hs_count < hdmi_he_min) || (hdmi_hs_count >= hdmi_he_max)) begin
|
||||
hdmi_hs_de <= 1'b0;
|
||||
end else begin
|
||||
hdmi_hs_de <= hdmi_enable;
|
||||
end
|
||||
if ((hdmi_vs_count < hdmi_ve_min) || (hdmi_vs_count >= hdmi_ve_max)) begin
|
||||
hdmi_vs_de <= 1'b0;
|
||||
end else begin
|
||||
hdmi_vs_de <= hdmi_enable;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// hdmi read data
|
||||
|
||||
assign hdmi_de_s = hdmi_hs_de & hdmi_vs_de;
|
||||
|
||||
always @(posedge hdmi_clk) begin
|
||||
if (hdmi_rst == 1'b1) begin
|
||||
hdmi_raddr <= 10'd0;
|
||||
end else if (hdmi_fs == 1'b1) begin
|
||||
hdmi_raddr <= {hdmi_fs_waddr, 1'b0};
|
||||
end else if (hdmi_de_s == 1'b1) begin
|
||||
hdmi_raddr <= hdmi_raddr + 1'b1;
|
||||
end
|
||||
hdmi_raddr_g <= b2g(hdmi_raddr[9:1]);
|
||||
end
|
||||
|
||||
// control and data pipe line
|
||||
|
||||
always @(posedge hdmi_clk) begin
|
||||
hdmi_hs_d <= hdmi_hs;
|
||||
hdmi_vs_d <= hdmi_vs;
|
||||
hdmi_hs_de_d <= hdmi_hs_de;
|
||||
hdmi_vs_de_d <= hdmi_vs_de;
|
||||
hdmi_de_d <= hdmi_de_s;
|
||||
hdmi_data_sel_d <= hdmi_raddr[0];
|
||||
hdmi_hs_2d <= hdmi_hs_d;
|
||||
hdmi_vs_2d <= hdmi_vs_d;
|
||||
hdmi_hs_de_2d <= hdmi_hs_de_d;
|
||||
hdmi_vs_de_2d <= hdmi_vs_de_d;
|
||||
hdmi_de_2d <= hdmi_de_d;
|
||||
hdmi_data_sel_2d <= hdmi_data_sel_d;
|
||||
hdmi_data_2d <= hdmi_rdata_s;
|
||||
end
|
||||
|
||||
// hdmi data count (may be used to monitor or insert)
|
||||
|
||||
assign hdmi_data_2d_s = (hdmi_data_sel_2d == 1'b1) ? hdmi_data_2d[47:24] : hdmi_data_2d[23:0];
|
||||
assign hdmi_tpm_mismatch_s = (hdmi_data_2d_s == hdmi_tpm_data) ? 1'b0 : hdmi_de_2d;
|
||||
assign hdmi_tpg_data_s = hdmi_tpm_data;
|
||||
|
||||
always @(posedge hdmi_clk) begin
|
||||
if ((hdmi_rst == 1'b1) || (hdmi_fs_ret == 1'b1)) begin
|
||||
hdmi_tpm_data <= 'd0;
|
||||
end else if (hdmi_de_2d == 1'b1) begin
|
||||
hdmi_tpm_data <= hdmi_tpm_data + 1'b1;
|
||||
end
|
||||
hdmi_tpm_oos <= hdmi_tpm_mismatch_s;
|
||||
end
|
||||
|
||||
// hdmi data select
|
||||
|
||||
always @(posedge hdmi_clk) begin
|
||||
hdmi_hsync <= hdmi_hs_2d;
|
||||
hdmi_vsync <= hdmi_vs_2d;
|
||||
hdmi_hsync_data_e <= hdmi_hs_de_2d;
|
||||
hdmi_vsync_data_e <= hdmi_vs_de_2d;
|
||||
hdmi_data_e <= hdmi_de_2d;
|
||||
case (hdmi_srcsel)
|
||||
2'b11: hdmi_data <= hdmi_const_rgb;
|
||||
2'b10: hdmi_data <= hdmi_tpg_data_s;
|
||||
2'b01: hdmi_data <= hdmi_data_2d_s;
|
||||
default: hdmi_data <= 24'd0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// Color space conversion bypass (RGB/YCbCr)
|
||||
|
||||
always @(posedge hdmi_clk) begin
|
||||
if (hdmi_csc_bypass == 1'b1) begin
|
||||
hdmi_24_csc_hsync <= hdmi_hsync;
|
||||
hdmi_24_csc_vsync <= hdmi_vsync;
|
||||
hdmi_24_csc_hsync_data_e <= hdmi_hsync_data_e;
|
||||
hdmi_24_csc_vsync_data_e <= hdmi_vsync_data_e;
|
||||
hdmi_24_csc_data_e <= hdmi_data_e;
|
||||
hdmi_24_csc_data <= hdmi_data;
|
||||
end else begin
|
||||
hdmi_24_csc_hsync <= hdmi_csc_hsync_s;
|
||||
hdmi_24_csc_vsync <= hdmi_csc_vsync_s;
|
||||
hdmi_24_csc_hsync_data_e <= hdmi_csc_hsync_data_e_s;
|
||||
hdmi_24_csc_vsync_data_e <= hdmi_csc_vsync_data_e_s;
|
||||
hdmi_24_csc_data_e <= hdmi_csc_data_e_s;
|
||||
hdmi_24_csc_data <= hdmi_csc_data_s;
|
||||
end
|
||||
end
|
||||
|
||||
// hdmi clipping
|
||||
|
||||
always @(posedge hdmi_clk) begin
|
||||
hdmi_clip_hs_d <= hdmi_24_csc_hsync;
|
||||
hdmi_clip_vs_d <= hdmi_24_csc_vsync;
|
||||
hdmi_clip_hs_de_d <= hdmi_24_csc_hsync_data_e;
|
||||
hdmi_clip_vs_de_d <= hdmi_24_csc_vsync_data_e;
|
||||
hdmi_clip_de_d <= hdmi_24_csc_data_e;
|
||||
|
||||
// Cr (red-diff) / red
|
||||
|
||||
if (hdmi_24_csc_data[23:16] > hdmi_clip_max[23:16]) begin
|
||||
hdmi_clip_data[23:16] <= hdmi_clip_max[23:16];
|
||||
end else if (hdmi_24_csc_data[23:16] < hdmi_clip_min[23:16]) begin
|
||||
hdmi_clip_data[23:16] <= hdmi_clip_min[23:16];
|
||||
end else begin
|
||||
hdmi_clip_data[23:16] <= hdmi_24_csc_data[23:16];
|
||||
end
|
||||
|
||||
// Y (luma) / green
|
||||
|
||||
if (hdmi_24_csc_data[15:8] > hdmi_clip_max[15:8]) begin
|
||||
hdmi_clip_data[15:8] <= hdmi_clip_max[15:8];
|
||||
end else if (hdmi_24_csc_data[15:8] < hdmi_clip_min[15:8]) begin
|
||||
hdmi_clip_data[15:8] <= hdmi_clip_min[15:8];
|
||||
end else begin
|
||||
hdmi_clip_data[15:8] <= hdmi_24_csc_data[15:8];
|
||||
end
|
||||
|
||||
// Cb (blue-diff) / blue
|
||||
|
||||
if (hdmi_24_csc_data[7:0] > hdmi_clip_max[7:0]) begin
|
||||
hdmi_clip_data[7:0] <= hdmi_clip_max[7:0];
|
||||
end else if (hdmi_24_csc_data[7:0] < hdmi_clip_min[7:0]) begin
|
||||
hdmi_clip_data[7:0] <= hdmi_clip_min[7:0];
|
||||
end else begin
|
||||
hdmi_clip_data[7:0] <= hdmi_24_csc_data[7:0];
|
||||
end
|
||||
end
|
||||
|
||||
// hdmi csc 16, 24 and 36 outputs
|
||||
|
||||
always @(posedge hdmi_clk) begin
|
||||
|
||||
hdmi_36_hsync <= hdmi_clip_hs_d;
|
||||
hdmi_36_vsync <= hdmi_clip_vs_d;
|
||||
hdmi_36_data_e <= hdmi_clip_de_d;
|
||||
hdmi_36_data[35:24] <= {hdmi_clip_data[23:16], hdmi_clip_data[23:20]};
|
||||
hdmi_36_data[23:12] <= {hdmi_clip_data[15: 8], hdmi_clip_data[15:12]};
|
||||
hdmi_36_data[11: 0] <= {hdmi_clip_data[ 7: 0], hdmi_clip_data[ 7: 4]};
|
||||
|
||||
hdmi_24_hsync <= hdmi_clip_hs_d;
|
||||
hdmi_24_vsync <= hdmi_clip_vs_d;
|
||||
hdmi_24_data_e <= hdmi_clip_de_d;
|
||||
hdmi_24_data <= hdmi_clip_data;
|
||||
|
||||
hdmi_16_hsync <= hdmi_16_hsync_d;
|
||||
hdmi_16_vsync <= hdmi_16_vsync_d;
|
||||
hdmi_16_data_e <= hdmi_16_data_e_d;
|
||||
hdmi_16_data <= hdmi_16_data_d;
|
||||
hdmi_16_es_data <= hdmi_es_data_s;
|
||||
|
||||
if (hdmi_ss_bypass == 1'b1) begin
|
||||
hdmi_16_hsync_d <= hdmi_clip_hs_d;
|
||||
hdmi_16_vsync_d <= hdmi_clip_vs_d;
|
||||
hdmi_16_hsync_data_e_d <= hdmi_clip_hs_de_d;
|
||||
hdmi_16_vsync_data_e_d <= hdmi_clip_vs_de_d;
|
||||
hdmi_16_data_e_d <= hdmi_clip_de_d;
|
||||
hdmi_16_data_d <= hdmi_clip_data[15:0]; // Ignore the upper 8 bit
|
||||
end else begin
|
||||
hdmi_16_hsync_d <= hdmi_ss_hsync_s;
|
||||
hdmi_16_vsync_d <= hdmi_ss_vsync_s;
|
||||
hdmi_16_hsync_data_e_d <= hdmi_ss_hsync_data_e_s;
|
||||
hdmi_16_vsync_data_e_d <= hdmi_ss_vsync_data_e_s;
|
||||
hdmi_16_data_e_d <= hdmi_ss_data_e_s;
|
||||
hdmi_16_data_d <= hdmi_ss_data_s;
|
||||
end
|
||||
end
|
||||
|
||||
// hdmi embedded sync
|
||||
|
||||
always @(posedge hdmi_clk) begin
|
||||
hdmi_es_hs_de <= hdmi_16_hsync_data_e_d;
|
||||
hdmi_es_vs_de <= hdmi_16_vsync_data_e_d;
|
||||
if (hdmi_16_data_e_d == 1'b0) begin
|
||||
hdmi_es_data[15:8] <= 8'h80;
|
||||
end else begin
|
||||
hdmi_es_data[15:8] <= hdmi_16_data_d[15:8];
|
||||
end
|
||||
if (hdmi_16_data_e_d == 1'b0) begin
|
||||
hdmi_es_data[7:0] <= 8'h80;
|
||||
end else begin
|
||||
hdmi_es_data[7:0] <= hdmi_16_data_d[7:0];
|
||||
end
|
||||
end
|
||||
|
||||
// data memory
|
||||
|
||||
ad_mem #(.DATA_WIDTH(48), .ADDRESS_WIDTH(9)) i_mem (
|
||||
.clka (vdma_clk),
|
||||
.wea (vdma_wr),
|
||||
.addra (vdma_waddr),
|
||||
.dina (vdma_wdata),
|
||||
.clkb (hdmi_clk),
|
||||
.reb (1'b1),
|
||||
.addrb (hdmi_raddr[9:1]),
|
||||
.doutb (hdmi_rdata_s));
|
||||
|
||||
// color space coversion, RGB to CrYCb
|
||||
|
||||
ad_csc_RGB2CrYCb #(.DELAY_DATA_WIDTH(5)) i_csc_RGB2CrYCb (
|
||||
.clk (hdmi_clk),
|
||||
.RGB_sync ({hdmi_hsync,
|
||||
hdmi_vsync,
|
||||
hdmi_hsync_data_e,
|
||||
hdmi_vsync_data_e,
|
||||
hdmi_data_e}),
|
||||
.RGB_data (hdmi_data),
|
||||
.CrYCb_sync ({hdmi_csc_hsync_s,
|
||||
hdmi_csc_vsync_s,
|
||||
hdmi_csc_hsync_data_e_s,
|
||||
hdmi_csc_vsync_data_e_s,
|
||||
hdmi_csc_data_e_s}),
|
||||
.CrYCb_data (hdmi_csc_data_s));
|
||||
|
||||
// sub sampling, 444 to 422
|
||||
|
||||
ad_ss_444to422 #(.DELAY_DATA_WIDTH(5), .CR_CB_N(CR_CB_N)) i_ss_444to422 (
|
||||
.clk (hdmi_clk),
|
||||
.s444_de (hdmi_clip_de_d),
|
||||
.s444_sync ({hdmi_clip_hs_d,
|
||||
hdmi_clip_vs_d,
|
||||
hdmi_clip_hs_de_d,
|
||||
hdmi_clip_vs_de_d,
|
||||
hdmi_clip_de_d}),
|
||||
.s444_data (hdmi_clip_data),
|
||||
.s422_sync ({hdmi_ss_hsync_s,
|
||||
hdmi_ss_vsync_s,
|
||||
hdmi_ss_hsync_data_e_s,
|
||||
hdmi_ss_vsync_data_e_s,
|
||||
hdmi_ss_data_e_s}),
|
||||
.s422_data (hdmi_ss_data_s));
|
||||
|
||||
// embedded sync
|
||||
|
||||
axi_hdmi_tx_es #(.DATA_WIDTH(16)) i_es (
|
||||
.hdmi_clk (hdmi_clk),
|
||||
.hdmi_hs_de (hdmi_es_hs_de),
|
||||
.hdmi_vs_de (hdmi_es_vs_de),
|
||||
.hdmi_data_de (hdmi_es_data),
|
||||
.hdmi_data (hdmi_es_data_s));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,107 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Transmit HDMI, video dma data in, hdmi separate syncs data out.
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_hdmi_tx_es #(
|
||||
|
||||
parameter DATA_WIDTH = 32) (
|
||||
|
||||
// hdmi interface
|
||||
|
||||
input hdmi_clk,
|
||||
input hdmi_hs_de,
|
||||
input hdmi_vs_de,
|
||||
input [(DATA_WIDTH-1):0] hdmi_data_de,
|
||||
output reg [(DATA_WIDTH-1):0] hdmi_data);
|
||||
|
||||
localparam BYTE_WIDTH = DATA_WIDTH/8;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg hdmi_hs_de_d = 'd0;
|
||||
reg [(DATA_WIDTH-1):0] hdmi_data_d = 'd0;
|
||||
reg hdmi_hs_de_2d = 'd0;
|
||||
reg [(DATA_WIDTH-1):0] hdmi_data_2d = 'd0;
|
||||
reg hdmi_hs_de_3d = 'd0;
|
||||
reg [(DATA_WIDTH-1):0] hdmi_data_3d = 'd0;
|
||||
reg hdmi_hs_de_4d = 'd0;
|
||||
reg [(DATA_WIDTH-1):0] hdmi_data_4d = 'd0;
|
||||
reg hdmi_hs_de_5d = 'd0;
|
||||
reg [(DATA_WIDTH-1):0] hdmi_data_5d = 'd0;
|
||||
|
||||
// internal wires
|
||||
|
||||
wire [(DATA_WIDTH-1):0] hdmi_sav_s;
|
||||
wire [(DATA_WIDTH-1):0] hdmi_eav_s;
|
||||
|
||||
// hdmi embedded sync insertion
|
||||
|
||||
assign hdmi_sav_s = (hdmi_vs_de == 1) ? {BYTE_WIDTH{8'h80}} : {BYTE_WIDTH{8'hab}};
|
||||
assign hdmi_eav_s = (hdmi_vs_de == 1) ? {BYTE_WIDTH{8'h9d}} : {BYTE_WIDTH{8'hb6}};
|
||||
|
||||
always @(posedge hdmi_clk) begin
|
||||
hdmi_hs_de_d <= hdmi_hs_de;
|
||||
case ({hdmi_hs_de_4d, hdmi_hs_de_3d, hdmi_hs_de_2d,
|
||||
hdmi_hs_de_d, hdmi_hs_de})
|
||||
5'b11000: hdmi_data_d <= {BYTE_WIDTH{8'h00}};
|
||||
5'b11100: hdmi_data_d <= {BYTE_WIDTH{8'h00}};
|
||||
5'b11110: hdmi_data_d <= {BYTE_WIDTH{8'hff}};
|
||||
5'b10000: hdmi_data_d <= hdmi_eav_s;
|
||||
default: hdmi_data_d <= hdmi_data_de;
|
||||
endcase
|
||||
hdmi_hs_de_2d <= hdmi_hs_de_d;
|
||||
hdmi_data_2d <= hdmi_data_d;
|
||||
hdmi_hs_de_3d <= hdmi_hs_de_2d;
|
||||
hdmi_data_3d <= hdmi_data_2d;
|
||||
hdmi_hs_de_4d <= hdmi_hs_de_3d;
|
||||
hdmi_data_4d <= hdmi_data_3d;
|
||||
hdmi_hs_de_5d <= hdmi_hs_de_4d;
|
||||
hdmi_data_5d <= hdmi_data_4d;
|
||||
case ({hdmi_hs_de_5d, hdmi_hs_de_4d, hdmi_hs_de_3d,
|
||||
hdmi_hs_de_2d, hdmi_hs_de_d})
|
||||
5'b00111: hdmi_data <= {BYTE_WIDTH{8'h00}};
|
||||
5'b00011: hdmi_data <= {BYTE_WIDTH{8'h00}};
|
||||
5'b00001: hdmi_data <= {BYTE_WIDTH{8'hff}};
|
||||
5'b01111: hdmi_data <= hdmi_sav_s;
|
||||
default: hdmi_data <= hdmi_data_5d;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,124 @@
|
||||
|
||||
|
||||
package require qsys
|
||||
package require quartus::device
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source ../scripts/adi_ip_intel.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_intel_device_info_enc.tcl
|
||||
|
||||
set_module_property NAME axi_hdmi_tx
|
||||
set_module_property DESCRIPTION "AXI HDMI Transmit Interface"
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property GROUP "Analog Devices"
|
||||
set_module_property DISPLAY_NAME axi_hdmi_tx
|
||||
set_module_property VALIDATION_CALLBACK info_param_validate
|
||||
set_module_property ELABORATION_CALLBACK add_out_interface
|
||||
|
||||
# files
|
||||
|
||||
ad_ip_files axi_hdmi_tx [list \
|
||||
$ad_hdl_dir/library/common/ad_mem.v \
|
||||
$ad_hdl_dir/library/common/ad_rst.v \
|
||||
$ad_hdl_dir/library/common/ad_csc.v \
|
||||
$ad_hdl_dir/library/common/ad_csc_RGB2CrYCb.v \
|
||||
$ad_hdl_dir/library/common/ad_ss_444to422.v \
|
||||
$ad_hdl_dir/library/common/up_axi.v \
|
||||
$ad_hdl_dir/library/common/up_xfer_cntrl.v \
|
||||
$ad_hdl_dir/library/common/up_xfer_status.v \
|
||||
$ad_hdl_dir/library/common/up_clock_mon.v \
|
||||
$ad_hdl_dir/library/common/up_hdmi_tx.v \
|
||||
$ad_hdl_dir/library/intel/common/ad_mul.v \
|
||||
$ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \
|
||||
$ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \
|
||||
$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
|
||||
$ad_hdl_dir/library/intel/common/up_rst_constr.sdc \
|
||||
axi_hdmi_tx_vdma.v \
|
||||
axi_hdmi_tx_es.v \
|
||||
axi_hdmi_tx_core.v \
|
||||
axi_hdmi_tx.v \
|
||||
axi_hdmi_tx_constr.sdc \
|
||||
]
|
||||
|
||||
# parameters
|
||||
|
||||
add_parameter ID INTEGER 0
|
||||
set_parameter_property ID DEFAULT_VALUE 0
|
||||
set_parameter_property ID DISPLAY_NAME ID
|
||||
set_parameter_property ID UNITS None
|
||||
set_parameter_property ID HDL_PARAMETER true
|
||||
|
||||
add_parameter CR_CB_N INTEGER 0
|
||||
set_parameter_property CR_CB_N DEFAULT_VALUE 0
|
||||
set_parameter_property CR_CB_N DISPLAY_NAME CR_CB_N
|
||||
set_parameter_property CR_CB_N UNITS None
|
||||
set_parameter_property CR_CB_N HDL_PARAMETER true
|
||||
|
||||
add_parameter INTERFACE STRING "16_BIT"
|
||||
set_parameter_property INTERFACE DEFAULT_VALUE "16_BIT"
|
||||
set_parameter_property INTERFACE DISPLAY_NAME INTERFACE
|
||||
set_parameter_property INTERFACE TYPE STRING
|
||||
set_parameter_property INTERFACE ALLOWED_RANGES { "16_BIT" "24_BIT" "36_BIT" "16_BIT_EMBEDDED_SYNC" }
|
||||
set_parameter_property INTERFACE HDL_PARAMETER false
|
||||
|
||||
add_parameter DEVICE STRING ""
|
||||
set_parameter_property DEVICE SYSTEM_INFO {DEVICE}
|
||||
set_parameter_property DEVICE HDL_PARAMETER false
|
||||
set_parameter_property DEVICE VISIBLE false
|
||||
|
||||
adi_add_device_spec_param "FPGA_TECHNOLOGY"
|
||||
|
||||
# axi4 slave
|
||||
|
||||
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
|
||||
|
||||
# hdmi interface
|
||||
|
||||
add_interface hdmi_clock clock end
|
||||
add_interface_port hdmi_clock hdmi_clk clk Input 1
|
||||
|
||||
add_interface hdmi_if conduit end
|
||||
set_interface_property hdmi_if associatedClock hdmi_clock
|
||||
add_interface_port hdmi_if hdmi_out_clk h_clk Output 1
|
||||
|
||||
# streaming dma
|
||||
|
||||
add_interface vdma_clock clock end
|
||||
add_interface_port vdma_clock vdma_clk clk Input 1
|
||||
|
||||
add_interface vdma_if axi4stream end
|
||||
set_interface_property vdma_if associatedClock vdma_clock
|
||||
set_interface_property vdma_if associatedReset s_axi_reset
|
||||
add_interface_port vdma_if vdma_valid tvalid Input 1
|
||||
add_interface_port vdma_if vdma_data tdata Input 64
|
||||
add_interface_port vdma_if vdma_ready tready Output 1
|
||||
add_interface_port vdma_if vdma_end_of_frame tlast Input 1
|
||||
|
||||
proc add_out_interface {} {
|
||||
|
||||
set interface [get_parameter_value INTERFACE]
|
||||
switch $interface {
|
||||
"16_BIT" {
|
||||
add_interface_port hdmi_if hdmi_16_hsync h16_hsync Output 1
|
||||
add_interface_port hdmi_if hdmi_16_vsync h16_vsync Output 1
|
||||
add_interface_port hdmi_if hdmi_16_data_e h16_data_e Output 1
|
||||
add_interface_port hdmi_if hdmi_16_data h16_data Output 16
|
||||
}
|
||||
"24_BIT" {
|
||||
add_interface_port hdmi_if hdmi_24_hsync h24_hsync Output 1
|
||||
add_interface_port hdmi_if hdmi_24_vsync h24_vsync Output 1
|
||||
add_interface_port hdmi_if hdmi_24_data_e h24_data_e Output 1
|
||||
add_interface_port hdmi_if hdmi_24_data h24_data Output 24
|
||||
}
|
||||
"36_BIT" {
|
||||
add_interface_port hdmi_if hdmi_36_hsync h36_hsync Output 1
|
||||
add_interface_port hdmi_if hdmi_36_vsync h36_vsync Output 1
|
||||
add_interface_port hdmi_if hdmi_36_data_e h36_data_e Output 1
|
||||
add_interface_port hdmi_if hdmi_36_data h36_data Output 36
|
||||
}
|
||||
"16_BIT_EMBEDDED_SYNC" {
|
||||
add_interface_port hdmi_if hdmi_16_es_data h16_es_data Output 16
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,77 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_hdmi_tx
|
||||
adi_ip_files axi_hdmi_tx [list \
|
||||
"$ad_hdl_dir/library/common/ad_mem.v" \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/common/ad_csc.v" \
|
||||
"$ad_hdl_dir/library/common/ad_csc_RGB2CrYCb.v" \
|
||||
"$ad_hdl_dir/library/common/ad_ss_444to422.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
"$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
"$ad_hdl_dir/library/common/up_hdmi_tx.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
|
||||
"axi_hdmi_tx_constr.xdc" \
|
||||
"axi_hdmi_tx_vdma.v" \
|
||||
"axi_hdmi_tx_es.v" \
|
||||
"axi_hdmi_tx_core.v" \
|
||||
"axi_hdmi_tx.v" ]
|
||||
|
||||
adi_ip_properties axi_hdmi_tx
|
||||
|
||||
adi_init_bd_tcl
|
||||
adi_ip_bd axi_hdmi_tx "bd/bd.tcl"
|
||||
|
||||
set_property driver_value 0 [ipx::get_ports *hsync* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *vsync* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *data* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *es_data* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property driver_value 0 [ipx::get_ports *vdma_end_of_frame* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *vdma_valid* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *vdma_data* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *vdma_ready* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property value_format string [ipx::get_user_parameters INTERFACE -of_objects [ipx::current_core]]
|
||||
set_property value_format string [ipx::get_hdl_parameters INTERFACE -of_objects [ipx::current_core]]
|
||||
set_property value_validation_list {16_BIT 24_BIT 36_BIT 16_BIT_EMBEDDED_SYNC} \
|
||||
[ipx::get_user_parameters INTERFACE -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "16_BIT"} \
|
||||
[ipx::get_ports *hdmi_16* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "24_BIT"} \
|
||||
[ipx::get_ports *hdmi_24* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "36_BIT"} \
|
||||
[ipx::get_ports *hdmi_36* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "16_BIT_EMBEDDED_SYNC"} \
|
||||
[ipx::get_ports *hdmi_16_es_data* -of_objects [ipx::current_core]]
|
||||
|
||||
adi_add_bus "s_axis" "slave" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
[list {"vdma_ready" "TREADY"} \
|
||||
{"vdma_valid" "TVALID"} \
|
||||
{"vdma_data" "TDATA"} \
|
||||
{"vdma_end_of_frame" "TLAST"} ]
|
||||
|
||||
ipx::infer_bus_interface hdmi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface hdmi_out_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface vdma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
|
||||
ipx::associate_bus_interfaces -busif s_axis -clock vdma_clk [ipx::current_core]
|
||||
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
@@ -0,0 +1,235 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Transmit HDMI, video dma data in, hdmi separate syncs data out.
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_hdmi_tx_vdma (
|
||||
|
||||
// hdmi interface
|
||||
|
||||
input hdmi_fs_toggle,
|
||||
input [ 8:0] hdmi_raddr_g,
|
||||
|
||||
// vdma interface
|
||||
|
||||
input vdma_clk,
|
||||
input vdma_rst,
|
||||
input vdma_end_of_frame,
|
||||
input vdma_valid,
|
||||
input [63:0] vdma_data,
|
||||
output reg vdma_ready,
|
||||
output reg vdma_wr,
|
||||
output reg [ 8:0] vdma_waddr,
|
||||
output reg [47:0] vdma_wdata,
|
||||
output reg vdma_fs_ret_toggle,
|
||||
output reg [ 8:0] vdma_fs_waddr,
|
||||
output reg vdma_tpm_oos,
|
||||
output reg vdma_ovf,
|
||||
output reg vdma_unf);
|
||||
|
||||
localparam BUF_THRESHOLD_LO = 9'd3;
|
||||
localparam BUF_THRESHOLD_HI = 9'd509;
|
||||
localparam RDY_THRESHOLD_LO = 9'd450;
|
||||
localparam RDY_THRESHOLD_HI = 9'd500;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg vdma_fs_toggle_m1 = 1'd0;
|
||||
reg vdma_fs_toggle_m2 = 1'd0;
|
||||
reg vdma_fs_toggle_m3 = 1'd0;
|
||||
reg [22:0] vdma_tpm_data = 23'd0;
|
||||
reg [ 8:0] vdma_raddr_g_m1 = 9'd0;
|
||||
reg [ 8:0] vdma_raddr_g_m2 = 9'd0;
|
||||
reg [ 8:0] vdma_raddr = 9'd0;
|
||||
reg [ 8:0] vdma_addr_diff = 9'd0;
|
||||
reg vdma_almost_full = 1'd0;
|
||||
reg vdma_almost_empty = 1'd0;
|
||||
reg hdmi_fs = 1'd0;
|
||||
reg vdma_fs = 1'd0;
|
||||
reg vdma_end_of_frame_d = 1'd0;
|
||||
reg vdma_active_frame = 1'd0;
|
||||
|
||||
// internal wires
|
||||
|
||||
wire [47:0] vdma_tpm_data_s;
|
||||
wire vdma_tpm_oos_s;
|
||||
wire [ 9:0] vdma_addr_diff_s;
|
||||
wire vdma_ovf_s;
|
||||
wire vdma_unf_s;
|
||||
|
||||
// grey to binary conversion
|
||||
|
||||
function [8:0] g2b;
|
||||
input [8:0] g;
|
||||
reg [8:0] b;
|
||||
begin
|
||||
b[8] = g[8];
|
||||
b[7] = b[8] ^ g[7];
|
||||
b[6] = b[7] ^ g[6];
|
||||
b[5] = b[6] ^ g[5];
|
||||
b[4] = b[5] ^ g[4];
|
||||
b[3] = b[4] ^ g[3];
|
||||
b[2] = b[3] ^ g[2];
|
||||
b[1] = b[2] ^ g[1];
|
||||
b[0] = b[1] ^ g[0];
|
||||
g2b = b;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// hdmi frame sync
|
||||
|
||||
always @(posedge vdma_clk) begin
|
||||
if (vdma_rst == 1'b1) begin
|
||||
vdma_fs_toggle_m1 <= 1'd0;
|
||||
vdma_fs_toggle_m2 <= 1'd0;
|
||||
vdma_fs_toggle_m3 <= 1'd0;
|
||||
end else begin
|
||||
vdma_fs_toggle_m1 <= hdmi_fs_toggle;
|
||||
vdma_fs_toggle_m2 <= vdma_fs_toggle_m1;
|
||||
vdma_fs_toggle_m3 <= vdma_fs_toggle_m2;
|
||||
end
|
||||
hdmi_fs <= vdma_fs_toggle_m2 ^ vdma_fs_toggle_m3;
|
||||
end
|
||||
|
||||
// dma frame sync
|
||||
|
||||
always @(posedge vdma_clk) begin
|
||||
if (vdma_rst == 1'b1) begin
|
||||
vdma_end_of_frame_d <= 1'b0;
|
||||
vdma_fs <= 1'b0;
|
||||
end else begin
|
||||
vdma_end_of_frame_d <= vdma_end_of_frame;
|
||||
vdma_fs <= vdma_end_of_frame_d;
|
||||
end
|
||||
end
|
||||
|
||||
// sync dma and hdmi frames
|
||||
|
||||
always @(posedge vdma_clk) begin
|
||||
if (vdma_rst == 1'b1) begin
|
||||
vdma_fs_ret_toggle = 1'b0;
|
||||
vdma_fs_waddr <= 9'b0;
|
||||
end else begin
|
||||
if (vdma_fs) begin
|
||||
vdma_fs_ret_toggle <= ~vdma_fs_ret_toggle;
|
||||
vdma_fs_waddr <= vdma_waddr ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// accept new frame from dma
|
||||
|
||||
always @(posedge vdma_clk) begin
|
||||
if (vdma_rst == 1'b1) begin
|
||||
vdma_active_frame <= 1'b0;
|
||||
end else begin
|
||||
if ((vdma_active_frame == 1'b1) && (vdma_end_of_frame == 1'b1)) begin
|
||||
vdma_active_frame <= 1'b0;
|
||||
end else if ((vdma_active_frame == 1'b0) && (hdmi_fs == 1'b1)) begin
|
||||
vdma_active_frame <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// vdma write
|
||||
|
||||
always @(posedge vdma_clk) begin
|
||||
vdma_wr <= vdma_valid & vdma_ready;
|
||||
if (vdma_rst == 1'b1) begin
|
||||
vdma_waddr <= 9'd0;
|
||||
end else if (vdma_wr == 1'b1) begin
|
||||
vdma_waddr <= vdma_waddr + 1'b1;
|
||||
end
|
||||
vdma_wdata <= {vdma_data[55:32], vdma_data[23:0]};
|
||||
end
|
||||
|
||||
// test error conditions
|
||||
|
||||
assign vdma_tpm_data_s = {vdma_tpm_data, 1'b1, vdma_tpm_data, 1'b0};
|
||||
assign vdma_tpm_oos_s = (vdma_wdata == vdma_tpm_data_s) ? 1'b0 : vdma_wr;
|
||||
|
||||
always @(posedge vdma_clk) begin
|
||||
if ((vdma_rst == 1'b1) || (vdma_fs == 1'b1)) begin
|
||||
vdma_tpm_data <= 23'd0;
|
||||
vdma_tpm_oos <= 1'd0;
|
||||
end else if (vdma_wr == 1'b1) begin
|
||||
vdma_tpm_data <= vdma_tpm_data + 1'b1;
|
||||
vdma_tpm_oos <= vdma_tpm_oos_s;
|
||||
end
|
||||
end
|
||||
|
||||
// overflow or underflow status
|
||||
|
||||
assign vdma_addr_diff_s = {1'b1, vdma_waddr} - vdma_raddr;
|
||||
assign vdma_ovf_s = (vdma_addr_diff < BUF_THRESHOLD_LO) ? vdma_almost_full : 1'b0;
|
||||
assign vdma_unf_s = (vdma_addr_diff > BUF_THRESHOLD_HI) ? vdma_almost_empty : 1'b0;
|
||||
|
||||
always @(posedge vdma_clk) begin
|
||||
if (vdma_rst == 1'b1) begin
|
||||
vdma_raddr_g_m1 <= 9'd0;
|
||||
vdma_raddr_g_m2 <= 9'd0;
|
||||
end else begin
|
||||
vdma_raddr_g_m1 <= hdmi_raddr_g;
|
||||
vdma_raddr_g_m2 <= vdma_raddr_g_m1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge vdma_clk) begin
|
||||
vdma_raddr <= g2b(vdma_raddr_g_m2);
|
||||
vdma_addr_diff <= vdma_addr_diff_s[8:0];
|
||||
if (vdma_addr_diff >= RDY_THRESHOLD_HI) begin
|
||||
vdma_ready <= 1'b0;
|
||||
end else if (vdma_addr_diff <= RDY_THRESHOLD_LO) begin
|
||||
vdma_ready <= vdma_active_frame;
|
||||
end
|
||||
if (vdma_addr_diff > BUF_THRESHOLD_HI) begin
|
||||
vdma_almost_full <= 1'b1;
|
||||
end else begin
|
||||
vdma_almost_full <= 1'b0;
|
||||
end
|
||||
if (vdma_addr_diff < BUF_THRESHOLD_LO) begin
|
||||
vdma_almost_empty <= 1'b1;
|
||||
end else begin
|
||||
vdma_almost_empty <= 1'b0;
|
||||
end
|
||||
vdma_ovf <= vdma_ovf_s;
|
||||
vdma_unf <= vdma_unf_s;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,44 @@
|
||||
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
bd::mark_propagate_only $ip " \
|
||||
FPGA_TECHNOLOGY"
|
||||
|
||||
adi_auto_assign_device_spec $cellpath
|
||||
}
|
||||
|
||||
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable/overwritable parameters
|
||||
foreach i $auto_set_param_list_overwritable {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,2 @@
|
||||
CLEAN_TARGET += bd
|
||||
CLEAN_TARGET += temporary_case_dependencies.mk
|
||||
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Wed Dec 8 10:23:00 2021
|
||||
# Process ID: 66684
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx
|
||||
# Command line: vivado -mode batch -source axi_hdmi_tx_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_hdmi_tx/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source axi_hdmi_tx_ip.tcl
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,88 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "CR_CB_N" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "INTERFACE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "OUT_CLK_POLARITY" -parent ${Page_0}
|
||||
#Adding Group
|
||||
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CR_CB_N { PARAM_VALUE.CR_CB_N } {
|
||||
# Procedure called to update CR_CB_N when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CR_CB_N { PARAM_VALUE.CR_CB_N } {
|
||||
# Procedure called to validate CR_CB_N
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to validate FPGA_TECHNOLOGY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.INTERFACE { PARAM_VALUE.INTERFACE } {
|
||||
# Procedure called to update INTERFACE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.INTERFACE { PARAM_VALUE.INTERFACE } {
|
||||
# Procedure called to validate INTERFACE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.OUT_CLK_POLARITY { PARAM_VALUE.OUT_CLK_POLARITY } {
|
||||
# Procedure called to update OUT_CLK_POLARITY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.OUT_CLK_POLARITY { PARAM_VALUE.OUT_CLK_POLARITY } {
|
||||
# Procedure called to validate OUT_CLK_POLARITY
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CR_CB_N { MODELPARAM_VALUE.CR_CB_N PARAM_VALUE.CR_CB_N } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CR_CB_N}] ${MODELPARAM_VALUE.CR_CB_N}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.INTERFACE { MODELPARAM_VALUE.INTERFACE PARAM_VALUE.INTERFACE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.INTERFACE}] ${MODELPARAM_VALUE.INTERFACE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.OUT_CLK_POLARITY { MODELPARAM_VALUE.OUT_CLK_POLARITY PARAM_VALUE.OUT_CLK_POLARITY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.OUT_CLK_POLARITY}] ${MODELPARAM_VALUE.OUT_CLK_POLARITY}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user