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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2019 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_pulse_gen_regmap #(
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parameter ID = 0,
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parameter [31:0] CORE_MAGIC = 0,
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parameter [31:0] CORE_VERSION = 0,
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parameter [ 0:0] ASYNC_CLK_EN = 1,
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parameter PULSE_WIDTH = 7,
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parameter PULSE_PERIOD = 10 )(
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// external clock
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input ext_clk,
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// control and status signals
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output clk_out,
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output pulse_gen_resetn,
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output [31:0] pulse_width,
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output [31:0] pulse_period,
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output load_config,
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// processor interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output reg up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output reg [31:0] up_rdata,
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output reg up_rack
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);
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// internal registers
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reg [31:0] up_scratch = 'd0;
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reg [31:0] up_pulse_width = 'd0;
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reg [31:0] up_pulse_period = 'd0;
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reg up_load_config = 1'b0;
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reg up_reset;
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 'd0;
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up_scratch <= 'd0;
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up_pulse_period <= PULSE_PERIOD;
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up_pulse_width <= PULSE_WIDTH;
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up_load_config <= 1'b0;
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up_reset <= 1'b1;
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end else begin
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up_wack <= up_wreq;
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if ((up_wreq == 1'b1) && (up_waddr == 14'h2)) begin
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up_scratch <= up_wdata;
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end
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if ((up_wreq == 1'b1) && (up_waddr == 14'h4)) begin
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up_reset <= up_wdata[0];
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up_load_config <= up_wdata[1];
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end else begin
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up_load_config <= 1'b0;
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end
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if ((up_wreq == 1'b1) && (up_waddr == 14'h5)) begin
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up_pulse_period <= up_wdata;
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end
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if ((up_wreq == 1'b1) && (up_waddr == 14'h6)) begin
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up_pulse_width <= up_wdata;
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end
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end
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end
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_rack <= up_rreq;
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if (up_rreq == 1'b1) begin
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case (up_raddr)
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14'h0: up_rdata <= CORE_VERSION;
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14'h1: up_rdata <= ID;
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14'h2: up_rdata <= up_scratch;
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14'h3: up_rdata <= CORE_MAGIC;
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14'h4: up_rdata <= up_reset;
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14'h5: up_rdata <= up_pulse_period;
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14'h6: up_rdata <= up_pulse_width;
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default: up_rdata <= 0;
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endcase
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end else begin
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up_rdata <= 32'd0;
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end
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end
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end
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generate
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if (ASYNC_CLK_EN) begin : counter_external_clock
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assign clk_out = ext_clk;
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ad_rst i_d_rst_reg (
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.rst_async (up_reset),
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.clk (clk_out),
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.rstn (pulse_gen_resetn),
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.rst ());
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sync_data #(
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.NUM_OF_BITS (32),
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.ASYNC_CLK (1))
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i_pulse_period_sync (
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.in_clk (up_clk),
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.in_data (up_pulse_period),
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.out_clk (clk_out),
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.out_data (pulse_period));
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sync_data #(
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.NUM_OF_BITS (32),
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.ASYNC_CLK (1))
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i_pulse_width_sync (
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.in_clk (up_clk),
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.in_data (up_pulse_width),
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.out_clk (clk_out),
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.out_data (pulse_width));
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sync_event #(
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.NUM_OF_EVENTS (1),
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.ASYNC_CLK (1))
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i_load_config_sync (
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.in_clk (up_clk),
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.in_event (up_load_config),
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.out_clk (clk_out),
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.out_event (load_config));
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end else begin : counter_sys_clock // counter is running on system clk
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assign clk_out = up_clk;
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assign pulse_gen_resetn = ~up_reset;
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assign pulse_period = up_pulse_period;
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assign pulse_width = up_pulse_width;
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assign load_config = up_load_config;
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end
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endgenerate
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endmodule
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