Archived
initial commit
This commit is contained in:
@@ -0,0 +1,20 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_spdif_rx
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GENERIC_DEPS += ../common/axi_ctrlif.vhd
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GENERIC_DEPS += ../common/axi_streaming_dma_rx_fifo.vhd
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GENERIC_DEPS += ../common/dma_fifo.vhd
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GENERIC_DEPS += ../common/pl330_dma_fifo.vhd
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GENERIC_DEPS += axi_spdif_rx.vhd
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GENERIC_DEPS += rx_decode.vhd
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GENERIC_DEPS += rx_package.vhd
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GENERIC_DEPS += rx_phase_det.vhd
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GENERIC_DEPS += rx_status_reg.vhd
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XILINX_DEPS += axi_spdif_rx_ip.tcl
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include ../scripts/library.mk
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@@ -0,0 +1,3 @@
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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eof:
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@@ -0,0 +1,6 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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<labtools version="1" minor="0"/>
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@@ -0,0 +1,433 @@
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-- ***************************************************************************
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-- ***************************************************************************
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-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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--
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-- In this HDL repository, there are many different and unique modules, consisting
|
||||
-- of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
-- developed independently, and may be accompanied by separate and unique license
|
||||
-- terms.
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||||
--
|
||||
-- The user should read each of these license terms, and understand the
|
||||
-- freedoms and responsibilities that he or she has by using this source/core.
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||||
--
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||||
-- This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
-- A PARTICULAR PURPOSE.
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||||
--
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||||
-- Redistribution and use of source or resulting binaries, with or without modification
|
||||
-- of this file, are permitted under one of the following two license terms:
|
||||
--
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||||
-- 1. The GNU General Public License version 2 as published by the
|
||||
-- Free Software Foundation, which can be found in the top level directory
|
||||
-- of this repository (LICENSE_GPL2), and also online at:
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||||
-- <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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||||
--
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||||
-- OR
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||||
--
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||||
-- 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
-- of this repository (LICENSE_ADIBSD), and also on-line at:
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||||
-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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||||
-- This will allow to generate bit files and not release the source code,
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||||
-- as long as it attaches to an ADI device.
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||||
--
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-- ***************************************************************************
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-- ***************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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library work;
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use work.rx_package.all;
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use work.axi_ctrlif;
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use work.axi_streaming_dma_rx_fifo;
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use work.pl330_dma_fifo;
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entity axi_spdif_rx is
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generic
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(
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C_S_AXI_DATA_WIDTH : integer := 32;
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C_S_AXI_ADDR_WIDTH : integer := 32;
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C_DMA_TYPE : integer := 0
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);
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port
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(
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--SPDIF ports
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rx_int_o : out std_logic;
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spdif_rx_i : in std_logic;
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spdif_rx_i_dbg : out std_logic;
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--AXI Lite inter face
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s_axi_aclk : in std_logic;
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s_axi_aresetn : in std_logic;
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s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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s_axi_awvalid : in std_logic;
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s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
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s_axi_wvalid : in std_logic;
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s_axi_bready : in std_logic;
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s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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s_axi_arvalid : in std_logic;
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s_axi_rready : in std_logic;
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s_axi_arready : out std_logic;
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s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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s_axi_rresp : out std_logic_vector(1 downto 0);
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s_axi_rvalid : out std_logic;
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s_axi_wready : out std_logic;
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s_axi_bresp : out std_logic_vector(1 downto 0);
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s_axi_bvalid : out std_logic;
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s_axi_awready : out std_logic;
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s_axi_awprot : in std_logic_vector(2 downto 0);
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s_axi_arprot : in std_logic_vector(2 downto 0);
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--AXI STREAM interface
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m_axis_aclk : in std_logic;
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m_axis_tready : in std_logic;
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m_axis_tdata : out std_logic_vector(31 downto 0);
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m_axis_tlast : out std_logic;
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m_axis_tvalid : out std_logic;
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m_axis_tkeep : out std_logic_vector(3 downto 0);
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--PL330 DMA interface
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dma_req_aclk : in std_logic;
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dma_req_rstn : in std_logic;
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dma_req_davalid : in std_logic;
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dma_req_datype : in std_logic_vector(1 downto 0);
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dma_req_daready : out std_logic;
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dma_req_drvalid : out std_logic;
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dma_req_drtype : out std_logic_vector(1 downto 0);
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dma_req_drlast : out std_logic;
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dma_req_drready : in std_logic
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);
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end entity axi_spdif_rx;
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------------------------------------------------------------------------------
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-- Architecture section
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------------------------------------------------------------------------------
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architecture IMP of axi_spdif_rx is
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signal wr_data : std_logic_vector(31 downto 0);
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signal rd_data : std_logic_vector(31 downto 0);
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signal wr_addr : integer range 0 to 3;
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signal rd_addr : integer range 0 to 3;
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signal wr_stb : std_logic;
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signal rd_ack : std_logic;
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signal version_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal control_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal chstatus_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal sampled_data : std_logic_vector(31 downto 0);
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signal sample_ack : std_logic;
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signal sample_din : std_logic_vector(31 downto 0);
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signal sample_wr : std_logic;
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signal conf_rxen : std_logic;
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signal conf_sample : std_logic;
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signal conf_chas : std_logic;
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signal conf_valid : std_logic;
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signal conf_blken : std_logic;
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signal conf_valen : std_logic;
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signal conf_useren : std_logic;
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signal conf_staten : std_logic;
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signal conf_paren : std_logic;
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signal config_rd : std_logic;
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signal config_wr : std_logic;
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signal conf_mode : std_logic_vector(3 downto 0);
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signal conf_bits : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
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signal conf_dout : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
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signal fifo_data_out : std_logic_vector(31 downto 0);
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signal fifo_data_ack : std_logic;
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signal fifo_reset : std_logic;
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signal tx_fifo_stb : std_logic;
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signal enable : boolean;
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signal lock : std_logic;
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signal rx_data : std_logic;
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signal rx_data_en : std_logic;
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signal rx_block_start : std_logic;
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signal rx_channel_a : std_logic;
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signal rx_error : std_logic;
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signal lock_evt : std_logic;
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signal ud_a_en : std_logic;
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signal ud_b_en : std_logic;
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signal cs_a_en : std_logic;
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signal cs_b_en : std_logic;
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signal rx_frame_start : std_logic;
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signal istat_lsbf : std_logic;
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signal istat_hsbf : std_logic;
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signal istat_paritya : std_logic;
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signal istat_parityb : std_logic;
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signal sbuf_wr_adr : std_logic_vector(C_S_AXI_ADDR_WIDTH - 2 downto 0);
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begin
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-------------------------------------------------------------------------------
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-- Version Register
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-------------------------------------------------------------------------------
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version_reg(31 downto 20) <= (others => '0');
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version_reg(19 downto 16) <= "0001";
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version_reg(15 downto 12) <= (others => '0');
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version_reg(11 downto 5) <= std_logic_vector(to_unsigned(C_S_AXI_ADDR_WIDTH,7));
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version_reg(4) <= '1';
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version_reg(3 downto 0) <= "0001";
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Control Register
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--------------------------------------------------------------------------------
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conf_mode(3 downto 0) <= control_reg(23 downto 20);
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conf_paren <= control_reg(19);
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conf_staten <= control_reg(18);
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conf_useren <= control_reg(17);
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conf_valen <= control_reg(16);
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conf_blken <= control_reg(5);
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conf_valid <= control_reg(4);
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conf_chas <= control_reg(3);
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conf_sample <= control_reg(1);
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conf_rxen <= control_reg(0);
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--------------------------------------------------------------------------------
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fifo_reset <= not conf_sample;
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enable <= conf_sample = '1';
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streaming_dma_gen: if C_DMA_TYPE = 0 generate
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fifo: entity axi_streaming_dma_rx_fifo
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generic map (
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RAM_ADDR_WIDTH => 3,
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FIFO_DWIDTH => 32
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)
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port map (
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clk => s_axi_aclk,
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resetn => s_axi_aresetn,
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fifo_reset => fifo_reset,
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enable => enable,
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period_len => 11,
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m_axis_aclk => m_axis_aclk,
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m_axis_tready => m_axis_tready,
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m_axis_tdata => m_axis_tdata,
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m_axis_tlast => m_axis_tlast,
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m_axis_tvalid => m_axis_tvalid,
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m_axis_tkeep => m_axis_tkeep,
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-- Write port
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in_stb => sample_wr,
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in_ack => sample_ack,
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in_data => sample_din
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);
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end generate;
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no_streaming_dma_gen: if C_DMA_TYPE /= 0 generate
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m_axis_tvalid <= '0';
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m_axis_tlast <= '0';
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m_axis_tkeep <= "0000";
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m_axis_tdata <= (others => '0');
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end generate;
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pl330_dma_gen: if C_DMA_TYPE = 1 generate
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tx_fifo_stb <= '1' when wr_addr = 3 and wr_stb = '1' else '0';
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fifo: entity pl330_dma_fifo
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generic map(
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RAM_ADDR_WIDTH => 3,
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FIFO_DWIDTH => 32,
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FIFO_DIRECTION => 0
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)
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port map (
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clk => s_axi_aclk,
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resetn => s_axi_aresetn,
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fifo_reset => fifo_reset,
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enable => enable,
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in_data => sample_din,
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in_stb => sample_wr,
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out_ack => tx_fifo_stb,
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out_data => sampled_data,
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dclk => dma_req_aclk,
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dresetn => dma_req_rstn,
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davalid => dma_req_davalid,
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daready => dma_req_daready,
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datype => dma_req_datype,
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drvalid => dma_req_drvalid,
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drready => dma_req_drready,
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drtype => dma_req_drtype,
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drlast => dma_req_drlast
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);
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end generate;
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no_pl330_dma_gen: if C_DMA_TYPE /= 1 generate
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dma_req_daready <= '0';
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dma_req_drvalid <= '0';
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dma_req_drtype <= (others => '0');
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dma_req_drlast <= '0';
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end generate;
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--------------------------------------------------------------------------------
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-- Status Register
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--------------------------------------------------------------------------------
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STAT: rx_status_reg
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generic map
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(
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DATA_WIDTH => C_S_AXI_DATA_WIDTH
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)
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port map
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(
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up_clk => s_axi_aclk,
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status_rd => rd_ack,
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lock => lock,
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chas => conf_chas,
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rx_block_start => rx_block_start,
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ch_data => rx_data,
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cs_a_en => cs_a_en,
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cs_b_en => cs_b_en,
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status_dout => chstatus_reg
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);
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Phase decoder
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--------------------------------------------------------------------------------
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PDET: rx_phase_det
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generic map
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(
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AXI_FREQ => 100 -- WishBone frequency in MHz
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)
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port map
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(
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up_clk => s_axi_aclk,
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rxen => conf_rxen,
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spdif => spdif_rx_i,
|
||||
lock => lock,
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||||
lock_evt => lock_evt,
|
||||
rx_data => rx_data,
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rx_data_en => rx_data_en,
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rx_block_start => rx_block_start,
|
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rx_frame_start => rx_frame_start,
|
||||
rx_channel_a => rx_channel_a,
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||||
rx_error => rx_error,
|
||||
ud_a_en => ud_a_en,
|
||||
ud_b_en => ud_b_en,
|
||||
cs_a_en => cs_a_en,
|
||||
cs_b_en => cs_b_en
|
||||
);
|
||||
spdif_rx_i_dbg <= spdif_rx_i;
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Rx Decoder
|
||||
--------------------------------------------------------------------------------
|
||||
FDEC: rx_decode
|
||||
generic map
|
||||
(
|
||||
DATA_WIDTH => C_S_AXI_DATA_WIDTH,
|
||||
ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
|
||||
)
|
||||
port map
|
||||
(
|
||||
up_clk => s_axi_aclk,
|
||||
conf_rxen => conf_rxen,
|
||||
conf_sample => conf_sample,
|
||||
conf_valid => conf_valid,
|
||||
conf_mode => conf_mode,
|
||||
conf_blken => conf_blken,
|
||||
conf_valen => conf_valen,
|
||||
conf_useren => conf_useren,
|
||||
conf_staten => conf_staten,
|
||||
conf_paren => conf_paren,
|
||||
lock => lock,
|
||||
rx_data => rx_data,
|
||||
rx_data_en => rx_data_en,
|
||||
rx_block_start => rx_block_start,
|
||||
rx_frame_start => rx_frame_start,
|
||||
rx_channel_a => rx_channel_a,
|
||||
wr_en => sample_wr,
|
||||
wr_addr => sbuf_wr_adr,
|
||||
wr_data => sample_din,
|
||||
stat_paritya => istat_paritya,
|
||||
stat_parityb => istat_parityb,
|
||||
stat_lsbf => istat_lsbf,
|
||||
stat_hsbf => istat_hsbf
|
||||
);
|
||||
rx_int_o <= sample_wr;
|
||||
|
||||
ctrlif: entity axi_ctrlif
|
||||
generic map (
|
||||
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
|
||||
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
|
||||
C_NUM_REG => 4
|
||||
)
|
||||
port map(
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
|
||||
rd_addr => rd_addr,
|
||||
rd_data => rd_data,
|
||||
rd_ack => rd_ack,
|
||||
rd_stb => '1',
|
||||
|
||||
wr_addr => wr_addr,
|
||||
wr_data => wr_data,
|
||||
wr_ack => '1',
|
||||
wr_stb => wr_stb
|
||||
);
|
||||
|
||||
process (s_axi_aclk)
|
||||
begin
|
||||
if rising_edge(s_axi_aclk) then
|
||||
if s_axi_aresetn = '0' then
|
||||
control_reg <= (others => '0');
|
||||
else
|
||||
if wr_stb = '1' then
|
||||
case wr_addr is
|
||||
when 1 => control_reg <= wr_data;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (rd_addr, version_reg, control_reg, chstatus_reg, sampled_data)
|
||||
begin
|
||||
case rd_addr is
|
||||
when 0 => rd_data <= version_reg;
|
||||
when 1 => rd_data <= control_reg;
|
||||
when 2 => rd_data <= chstatus_reg;
|
||||
when 3 => rd_data <= sampled_data;
|
||||
when others => rd_data <= (others => '0');
|
||||
end case;
|
||||
end process;
|
||||
|
||||
end IMP;
|
||||
@@ -0,0 +1,423 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx/axi_spdif_rx.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="97ed79be0077461c9655956921a035e3"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../common/axi_ctrlif.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/rx_package.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/dma_fifo.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/axi_streaming_dma_rx_fifo.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/pl330_dma_fifo.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/rx_decode.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/rx_phase_det.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/rx_status_reg.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_spdif_rx.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_spdif_rx"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,759 @@
|
||||
|
||||
****** Vivado v2019.1.3 (64-bit)
|
||||
**** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
**** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
source axi_spdif_rx_ip.tcl
|
||||
# source ../scripts/adi_env.tcl
|
||||
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
|
||||
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
|
||||
## if [info exists ::env(ADI_HDL_DIR)] {
|
||||
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
|
||||
## }
|
||||
## if [info exists ::env(ADI_GHDL_DIR)] {
|
||||
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
|
||||
## }
|
||||
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
|
||||
### variable auto_set_param_list
|
||||
### variable auto_set_param_list_overwritable
|
||||
### variable fpga_series_list
|
||||
### variable fpga_family_list
|
||||
### variable speed_grade_list
|
||||
### variable dev_package_list
|
||||
### variable xcvr_type_list
|
||||
### variable fpga_voltage_list
|
||||
### set auto_set_param_list { \
|
||||
### DEV_PACKAGE \
|
||||
### SPEED_GRADE \
|
||||
### FPGA_FAMILY \
|
||||
### FPGA_TECHNOLOGY }
|
||||
### set auto_set_param_list_overwritable { \
|
||||
### FPGA_VOLTAGE \
|
||||
### XCVR_TYPE }
|
||||
### set fpga_technology_list { \
|
||||
### { Unknown 0 } \
|
||||
### { 7series 1 } \
|
||||
### { ultrascale 2 } \
|
||||
### { ultrascale+ 3 }}
|
||||
### set fpga_family_list { \
|
||||
### { Unknown 0 } \
|
||||
### { artix 1 } \
|
||||
### { kintex 2 } \
|
||||
### { virtex 3 } \
|
||||
### { zynq 4 }}
|
||||
### set speed_grade_list { \
|
||||
### { Unknown 0 } \
|
||||
### { -1 10 } \
|
||||
### { -1L 11 } \
|
||||
### { -1H 12 } \
|
||||
### { -1HV 13 } \
|
||||
### { -1LV 14 } \
|
||||
### { -2 20 } \
|
||||
### { -2L 21 } \
|
||||
### { -2LV 22 } \
|
||||
### { -3 30 }}
|
||||
### set dev_package_list { \
|
||||
### { Unknown 0 } \
|
||||
### { rf 1 } \
|
||||
### { fl 2 } \
|
||||
### { ff 3 } \
|
||||
### { fb 4 } \
|
||||
### { hc 5 } \
|
||||
### { fh 6 } \
|
||||
### { cs 7 } \
|
||||
### { cp 8 } \
|
||||
### { ft 9 } \
|
||||
### { fg 10 } \
|
||||
### { sb 11 } \
|
||||
### { rb 12 } \
|
||||
### { rs 13 } \
|
||||
### { cl 14 } \
|
||||
### { sf 15 } \
|
||||
### { ba 16 } \
|
||||
### { fa 17 } \
|
||||
### { fs 18 } \
|
||||
### { fi 19 }}
|
||||
### set xcvr_type_list { \
|
||||
### { Unknown 0 } \
|
||||
### { GTPE2_NOT_SUPPORTED 1 } \
|
||||
### { GTXE2 2 } \
|
||||
### { GTHE2_NOT_SUPPORTED 3 } \
|
||||
### { GTZE2_NOT_SUPPORTED 4 } \
|
||||
### { GTHE3 5 } \
|
||||
### { GTYE3_NOT_SUPPORTED 6 } \
|
||||
### { GTRE4_NOT_SUPPORTED 7 } \
|
||||
### { GTHE4 8 } \
|
||||
### { GTYE4 9 } \
|
||||
### { GTME4_NOT_SUPPORTED 10}}
|
||||
### set fpga_voltage_list {0 5000} ;
|
||||
### proc adi_device_spec {cellpath param} {
|
||||
###
|
||||
### set list_pointer [string tolower $param]
|
||||
### set list_pointer [append list_pointer "_list"]
|
||||
###
|
||||
### upvar 1 $list_pointer $list_pointer
|
||||
###
|
||||
### set ip [get_bd_cells $cellpath]
|
||||
### set part [get_property PART [current_project]]
|
||||
###
|
||||
### switch -regexp -- $param {
|
||||
### FPGA_TECHNOLOGY {
|
||||
### switch -regexp -- $part {
|
||||
### ^xc7 {set series_name 7series}
|
||||
### ^xczu {set series_name ultrascale+}
|
||||
### ^xc.u.p {set series_name ultrascale+}
|
||||
### ^xc.u {set series_name ultrascale }
|
||||
### default {
|
||||
### puts "Undefined fpga technology for \"$part\"!"
|
||||
### exit -1
|
||||
### }
|
||||
### }
|
||||
### return "$series_name"
|
||||
### }
|
||||
### FPGA_FAMILY {
|
||||
### set fpga_family [get_property FAMILY $part]
|
||||
### foreach i $fpga_family_list {
|
||||
### regexp ^[lindex $i 0] $fpga_family matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### SPEED_GRADE {
|
||||
### set speed_grade [get_property SPEED $part]
|
||||
### return "$speed_grade"
|
||||
### }
|
||||
### DEV_PACKAGE {
|
||||
### set dev_package [get_property PACKAGE $part]
|
||||
### foreach i $dev_package_list {
|
||||
### regexp ^[lindex $i 0] $dev_package matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### XCVR_TYPE {
|
||||
### set matched ""
|
||||
### set dev_transcivers "none"
|
||||
### foreach x [list_property $part] {
|
||||
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
|
||||
### }
|
||||
### foreach i $xcvr_type_list {
|
||||
### regexp ^[lindex $i 0] $dev_transcivers matched
|
||||
### }
|
||||
### if { $matched eq "" } {
|
||||
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### FPGA_VOLTAGE {
|
||||
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
|
||||
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
|
||||
###
|
||||
### return "$fpga_voltage"
|
||||
### }
|
||||
### default {
|
||||
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
|
||||
### }
|
||||
### }
|
||||
### }
|
||||
## if {![info exists REQUIRED_VIVADO_VERSION]} {
|
||||
## set REQUIRED_VIVADO_VERSION "2019.1"
|
||||
## }
|
||||
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
|
||||
## set IGNORE_VERSION_CHECK 1
|
||||
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
|
||||
## set IGNORE_VERSION_CHECK 0
|
||||
## }
|
||||
## proc adi_ip_ttcl {ip_name ip_constr_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
|
||||
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_sim_ttcl {ip_name ip_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
|
||||
## set f [ipx::add_file $ip_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_bd {ip_name ip_bd_files} {
|
||||
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
|
||||
## if {$proj_filegroup == {}} {
|
||||
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
|
||||
## }
|
||||
##
|
||||
## foreach file $ip_bd_files {
|
||||
## set f [ipx::add_file $file $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type tclSource \
|
||||
## ] $f
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_infer_streaming_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_ip_infer_mm_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
|
||||
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency $port
|
||||
## if {$driver_value != {}} {
|
||||
## set_property DRIVER_VALUE $driver_value $port
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_set_bus_dependency {bus prefix dependency} {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
|
||||
## adi_set_ports_dependency $prefix $dependency 0
|
||||
## }
|
||||
## proc adi_add_port_map {bus phys logic} {
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## }
|
||||
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## adi_add_port_map $bus {*}$port_map
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
|
||||
## for {set i 0} {$i < $num} {incr i} {
|
||||
## set bus_name [format "%s%d" $bus_name_prefix $i]
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## if {$dependency ne ""} {
|
||||
## set bus_dependency [string map [list "{i}" $i] $dependency]
|
||||
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
|
||||
## }
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## lassign $port_map phys logic width width_dep
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
|
||||
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
|
||||
## if {$width_dep ne ""} {
|
||||
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
|
||||
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
|
||||
## set width_dep_r "(($width_dep) * $i)"
|
||||
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
|
||||
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
|
||||
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
|
||||
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
|
||||
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
|
||||
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
|
||||
## set_property display_name $clock_inf_name $clock_inf
|
||||
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
|
||||
## set_property physical_name $clock_signal_name $clock_map
|
||||
##
|
||||
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
|
||||
## set_property value $bus_inf_name $assoc_busif
|
||||
##
|
||||
## if { $reset_signal_name != "" } {
|
||||
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
|
||||
## set_property value $reset_signal_name $assoc_reset
|
||||
##
|
||||
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
|
||||
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
|
||||
## set_property display_name $reset_inf_name $reset_inf
|
||||
## set_property interface_mode $reset_signal_mode $reset_inf
|
||||
## set reset_map [ipx::add_port_map "RST" $reset_inf]
|
||||
## set_property physical_name $reset_signal_name $reset_map
|
||||
##
|
||||
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
|
||||
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
|
||||
## set_property value "ACTIVE_LOW" $reset_polarity
|
||||
## } else {
|
||||
## set_property value "ACTIVE_HIGH" $reset_polarity
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_add_core_dependencies {vlnvs} {
|
||||
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
|
||||
## foreach vlnv $vlnvs {
|
||||
## ipx::add_subcore $vlnv $file_group
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_create {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
## global ad_ghdl_dir
|
||||
## global REQUIRED_VIVADO_VERSION
|
||||
## global IGNORE_VERSION_CHECK
|
||||
##
|
||||
## set VIVADO_VERSION [version -short]
|
||||
## if {$IGNORE_VERSION_CHECK} {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## }
|
||||
## } else {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "ERROR: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
|
||||
## exit 2
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## create_project $ip_name . -force
|
||||
##
|
||||
## ## Load custom message severity definitions
|
||||
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
|
||||
##
|
||||
## set lib_dirs $ad_hdl_dir/library
|
||||
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
|
||||
## lappend lib_dirs $ad_ghdl_dir/library
|
||||
## }
|
||||
##
|
||||
## set_property ip_repo_paths $lib_dirs [current_fileset]
|
||||
## update_ip_catalog
|
||||
## }
|
||||
## proc adi_ip_files {ip_name ip_files} {
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## foreach m_file $ip_files {
|
||||
## if {[file extension $m_file] eq ".xdc"} {
|
||||
## add_files -norecurse -fileset constrs_1 $m_file
|
||||
## } else {
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
|
||||
## }
|
||||
## }
|
||||
## set_property "top" "$ip_name" $proj_fileset
|
||||
## }
|
||||
## proc adi_ip_properties_lite {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
##
|
||||
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
|
||||
##
|
||||
## set_property name $ip_name [ipx::current_core]
|
||||
##
|
||||
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
|
||||
## set_property company_url {http://www.analog.com} [ipx::current_core]
|
||||
##
|
||||
## set i_families ""
|
||||
## foreach i_part [get_parts] {
|
||||
## lappend i_families [get_property FAMILY $i_part]
|
||||
## }
|
||||
## set i_families [lsort -unique $i_families]
|
||||
## set s_families [get_property supported_families [ipx::current_core]]
|
||||
## foreach i_family $i_families {
|
||||
## set s_families "$s_families $i_family Production"
|
||||
## set s_families "$s_families $i_family Beta"
|
||||
## }
|
||||
## set_property supported_families $s_families [ipx::current_core]
|
||||
##
|
||||
## ipx::save_core [ipx::current_core]
|
||||
##
|
||||
## ipx::remove_all_bus_interface [ipx::current_core]
|
||||
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
|
||||
## foreach map $memory_maps {
|
||||
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
|
||||
## }
|
||||
##
|
||||
## ipx::update_checksums [ipx::current_core]
|
||||
## ipx::save_core [ipx::current_core]
|
||||
## }
|
||||
## proc adi_ip_properties {ip_name} {
|
||||
##
|
||||
## adi_ip_properties_lite $ip_name
|
||||
##
|
||||
## ipx::infer_bus_interface {\
|
||||
## s_axi_awvalid \
|
||||
## s_axi_awaddr \
|
||||
## s_axi_awprot \
|
||||
## s_axi_awready \
|
||||
## s_axi_wvalid \
|
||||
## s_axi_wdata \
|
||||
## s_axi_wstrb \
|
||||
## s_axi_wready \
|
||||
## s_axi_bvalid \
|
||||
## s_axi_bresp \
|
||||
##
|
||||
## s_axi_bready \
|
||||
## s_axi_arvalid \
|
||||
## s_axi_araddr \
|
||||
## s_axi_arprot \
|
||||
## s_axi_arready \
|
||||
## s_axi_rvalid \
|
||||
## s_axi_rdata \
|
||||
## s_axi_rresp \
|
||||
## s_axi_rready} \
|
||||
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
|
||||
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
|
||||
##
|
||||
## if {$raddr_width != $waddr_width} {
|
||||
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
|
||||
## set range 65536
|
||||
## } else {
|
||||
## if {$raddr_width >= 16} {
|
||||
## set range 65536
|
||||
## } else {
|
||||
## set range [expr 1 << $raddr_width]
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
## set_property range $range [ipx::get_address_blocks axi_lite \
|
||||
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
|
||||
## ipx::save_core
|
||||
## }
|
||||
## proc adi_init_bd_tcl {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## if { [file exists bd] } {
|
||||
## file delete -force bd
|
||||
## }
|
||||
## file mkdir bd
|
||||
##
|
||||
## set bd_tcl [open "bd/bd.tcl" w]
|
||||
##
|
||||
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
|
||||
## puts $bd_tcl "proc init {cellpath otherInfo} {"
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl ""
|
||||
## set auto_set_param ""
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
|
||||
## puts $bd_tcl $auto_set_param
|
||||
## }
|
||||
##
|
||||
## set auto_set_overwritable_param ""
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_overwritable_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_overwritable_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
|
||||
## puts $bd_tcl $auto_set_overwritable_param
|
||||
## }
|
||||
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
|
||||
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
|
||||
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set parent_dir \"../\""
|
||||
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
|
||||
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
|
||||
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " break"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " append parent_dir \"../\""
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## close $bd_tcl
|
||||
##
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
|
||||
##
|
||||
## set local_mk [open "temporary_case_dependencies.mk" w]
|
||||
## seek $local_mk 0 start
|
||||
## puts $local_mk "CLEAN_TARGET += bd"
|
||||
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
|
||||
## close $local_mk
|
||||
## }
|
||||
## proc adi_add_auto_fpga_spec_params {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_device_spec_param {ip_param} {
|
||||
##
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## set list_pointer [string tolower $ip_param]
|
||||
## set list_pointer [append list_pointer "_list"]
|
||||
##
|
||||
## global $list_pointer
|
||||
##
|
||||
## # set j 1D list from the original list
|
||||
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
|
||||
##
|
||||
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
|
||||
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "range_long" \
|
||||
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
|
||||
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## } else {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "pairs" \
|
||||
## "value_validation_pairs" $j ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## }
|
||||
##
|
||||
## # FPGA info grup
|
||||
## set info_group_name "FPGA info"
|
||||
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
|
||||
## if { [string trim $info_group] eq "" } {
|
||||
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
|
||||
## -parent $page0 -display_name $info_group_name]
|
||||
## }
|
||||
##
|
||||
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
|
||||
## set_property -dict [list "widget" "comboBox" ] $p
|
||||
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
|
||||
## }
|
||||
## proc adi_if_define {name} {
|
||||
##
|
||||
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
|
||||
## ipx::create_bus_definition analog.com interface $name 1.0
|
||||
##
|
||||
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
|
||||
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
|
||||
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
|
||||
##
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## }
|
||||
## proc adi_if_ports {dir width name {type none}} {
|
||||
##
|
||||
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
|
||||
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
|
||||
## set_property master_presence required $m_intf
|
||||
## set_property slave_presence required $m_intf
|
||||
## set_property master_width $width $m_intf
|
||||
## set_property slave_width $width $m_intf
|
||||
##
|
||||
## set m_dir "in"
|
||||
## set s_dir "out"
|
||||
## if {$dir eq "output"} {
|
||||
## set m_dir "out"
|
||||
## set s_dir "in"
|
||||
## }
|
||||
##
|
||||
## set_property master_direction $m_dir $m_intf
|
||||
## set_property slave_direction $s_dir $m_intf
|
||||
##
|
||||
## if {$type ne "none"} {
|
||||
## set_property is_${type} true $m_intf
|
||||
## }
|
||||
##
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## }
|
||||
## proc adi_if_infer_bus {if_name mode name maps} {
|
||||
##
|
||||
## ipx::add_bus_interface $name [ipx::current_core]
|
||||
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
|
||||
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
|
||||
## set_property interface_mode $mode $m_bus_if
|
||||
##
|
||||
## foreach map $maps {
|
||||
## set m_maps [regexp -all -inline {\S+} $map]
|
||||
## lassign $m_maps p_name p_map
|
||||
## ipx::add_port_map $p_name $m_bus_if
|
||||
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
|
||||
## }
|
||||
## }
|
||||
# adi_ip_create axi_spdif_rx
|
||||
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
|
||||
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1343} -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1306} -new_severity WARNING
|
||||
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
|
||||
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
|
||||
## set_msg_config -id {Synth 8-3331} -new_severity INFO
|
||||
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
|
||||
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
|
||||
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
|
||||
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'.)
|
||||
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
|
||||
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
|
||||
# adi_ip_files axi_spdif_rx [list \
|
||||
# "$ad_hdl_dir/library/common/axi_ctrlif.vhd" \
|
||||
# "$ad_hdl_dir/library/common/axi_streaming_dma_rx_fifo.vhd" \
|
||||
# "$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \
|
||||
# "$ad_hdl_dir/library/common/dma_fifo.vhd" \
|
||||
# "rx_phase_det.vhd" \
|
||||
# "rx_package.vhd" \
|
||||
# "rx_decode.vhd" \
|
||||
# "rx_status_reg.vhd" \
|
||||
# "axi_spdif_rx.vhd" ]
|
||||
# adi_ip_properties axi_spdif_rx
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_ctrlif.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_rx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/pl330_dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_ctrlif.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_rx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/pl330_dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'm_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_rstn'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3157] Bus Interface 'dma_req_rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'dma_req_rstn' is not *resetn - please double check the POLARITY setting.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'dma_req_aclk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 's_axi_aclk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
||||
# adi_ip_infer_streaming_interfaces axi_spdif_rx
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rstn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'm_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_rstn'.
|
||||
# adi_add_bus "dma_ack" "slave" \
|
||||
# "xilinx.com:interface:axis_rtl:1.0" \
|
||||
# "xilinx.com:interface:axis:1.0" \
|
||||
# [list {"dma_req_davalid" "TVALID"} \
|
||||
# {"dma_req_daready" "TREADY"} \
|
||||
# {"dma_req_datype" "TUSER"} ]
|
||||
# adi_add_bus "dma_req" "master" \
|
||||
# "xilinx.com:interface:axis_rtl:1.0" \
|
||||
# "xilinx.com:interface:axis:1.0" \
|
||||
# [list {"dma_req_drvalid" "TVALID"} \
|
||||
# {"dma_req_drready" "TREADY"} \
|
||||
# {"dma_req_drtype" "TUSER"} \
|
||||
# {"dma_req_drlast" "TLAST"} ]
|
||||
# adi_add_bus_clock "dma_req_aclk" "dma_req:dma_ack" "dma_req_rstn"
|
||||
# adi_set_bus_dependency "m_axis" "m_axis" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)"
|
||||
# adi_set_bus_dependency "dma_ack" "dma_req_da" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
|
||||
# adi_set_bus_dependency "dma_req" "dma_req_dr" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
|
||||
# adi_set_ports_dependency "dma_req_aclk" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
|
||||
# adi_set_ports_dependency "dma_req_rstn" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
|
||||
# ipx::save_core [ipx::current_core]
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:16:38 2021...
|
||||
@@ -0,0 +1,51 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_spdif_rx
|
||||
adi_ip_files axi_spdif_rx [list \
|
||||
"$ad_hdl_dir/library/common/axi_ctrlif.vhd" \
|
||||
"$ad_hdl_dir/library/common/axi_streaming_dma_rx_fifo.vhd" \
|
||||
"$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \
|
||||
"$ad_hdl_dir/library/common/dma_fifo.vhd" \
|
||||
"rx_phase_det.vhd" \
|
||||
"rx_package.vhd" \
|
||||
"rx_decode.vhd" \
|
||||
"rx_status_reg.vhd" \
|
||||
"axi_spdif_rx.vhd" ]
|
||||
|
||||
adi_ip_properties axi_spdif_rx
|
||||
adi_ip_infer_streaming_interfaces axi_spdif_rx
|
||||
|
||||
adi_add_bus "dma_ack" "slave" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
[list {"dma_req_davalid" "TVALID"} \
|
||||
{"dma_req_daready" "TREADY"} \
|
||||
{"dma_req_datype" "TUSER"} ]
|
||||
adi_add_bus "dma_req" "master" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
[list {"dma_req_drvalid" "TVALID"} \
|
||||
{"dma_req_drready" "TREADY"} \
|
||||
{"dma_req_drtype" "TUSER"} \
|
||||
{"dma_req_drlast" "TLAST"} ]
|
||||
|
||||
# Clock and reset are for both dma_req and dma_ack
|
||||
adi_add_bus_clock "dma_req_aclk" "dma_req:dma_ack" "dma_req_rstn"
|
||||
|
||||
adi_set_bus_dependency "m_axis" "m_axis" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)"
|
||||
|
||||
adi_set_bus_dependency "dma_ack" "dma_req_da" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
|
||||
adi_set_bus_dependency "dma_req" "dma_req_dr" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "dma_req_aclk" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "dma_req_rstn" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,176 @@
|
||||
----------------------------------------------------------------------
|
||||
---- ----
|
||||
---- WISHBONE SPDIF IP Core ----
|
||||
---- ----
|
||||
---- This file is part of the SPDIF project ----
|
||||
---- http://www.opencores.org/cores/spdif_interface/ ----
|
||||
---- ----
|
||||
---- Description ----
|
||||
---- SPDIF receiver channel status capture module ----
|
||||
---- ----
|
||||
---- ----
|
||||
---- To Do: ----
|
||||
---- - ----
|
||||
---- ----
|
||||
---- Author(s): ----
|
||||
---- - Geir Drange, [email protected] ----
|
||||
---- ----
|
||||
----------------------------------------------------------------------
|
||||
---- ----
|
||||
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
|
||||
---- ----
|
||||
---- This source file may be used and distributed without ----
|
||||
---- restriction provided that this copyright statement is not ----
|
||||
---- removed from the file and that any derivative work contains ----
|
||||
---- the original copyright notice and the associated disclaimer. ----
|
||||
---- ----
|
||||
---- This source file is free software; you can redistribute it ----
|
||||
---- and/or modify it under the terms of the GNU Lesser General ----
|
||||
---- Public License as published by the Free Software Foundation; ----
|
||||
---- either version 2.1 of the License, or (at your option) any ----
|
||||
---- later version. ----
|
||||
---- ----
|
||||
---- This source is distributed in the hope that it will be ----
|
||||
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
||||
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
||||
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
||||
---- details. ----
|
||||
---- ----
|
||||
---- You should have received a copy of the GNU Lesser General ----
|
||||
---- Public License along with this source; if not, download it ----
|
||||
---- from http://www.opencores.org/lgpl.shtml ----
|
||||
---- ----
|
||||
----------------------------------------------------------------------
|
||||
--
|
||||
-- CVS Revision History
|
||||
--
|
||||
-- $Log: not supported by cvs2svn $
|
||||
-- Revision 1.4 2004/07/19 16:58:37 gedra
|
||||
-- Fixed bug.
|
||||
--
|
||||
-- Revision 1.3 2004/06/27 16:16:55 gedra
|
||||
-- Signal renaming and bug fix.
|
||||
--
|
||||
-- Revision 1.2 2004/06/26 14:14:47 gedra
|
||||
-- Converted to numeric_std and fixed a few bugs.
|
||||
--
|
||||
-- Revision 1.1 2004/06/05 17:16:46 gedra
|
||||
-- Channel status/user data capture register
|
||||
--
|
||||
--
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use work.rx_package.all;
|
||||
|
||||
entity rx_cap_reg is
|
||||
port (
|
||||
clk: in std_logic; -- clock
|
||||
rst: in std_logic; -- reset
|
||||
--cap_ctrl_wr: in std_logic; -- control register write
|
||||
--cap_ctrl_rd: in std_logic; -- control register read
|
||||
--cap_data_rd: in std_logic; -- data register read
|
||||
cap_reg: in std_logic_vector(31 downto 0);
|
||||
cap_din: in std_logic_vector(31 downto 0); -- write data
|
||||
rx_block_start: in std_logic; -- start of block signal
|
||||
ch_data: in std_logic; -- channel status/user data
|
||||
ud_a_en: in std_logic; -- user data ch. A enable
|
||||
ud_b_en: in std_logic; -- user data ch. B enable
|
||||
cs_a_en: in std_logic; -- channel status ch. A enable
|
||||
cs_b_en: in std_logic; -- channel status ch. B enable
|
||||
cap_dout: out std_logic_vector(31 downto 0); -- read data
|
||||
cap_evt: out std_logic); -- capture event (interrupt)
|
||||
end rx_cap_reg;
|
||||
|
||||
architecture rtl of rx_cap_reg is
|
||||
|
||||
signal cap_ctrl_bits, cap_ctrl_dout: std_logic_vector(31 downto 0);
|
||||
signal cap_reg_1, cap_new : std_logic_vector(31 downto 0);
|
||||
signal bitlen, cap_len : integer range 0 to 63;
|
||||
signal bitpos, cur_pos : integer range 0 to 255;
|
||||
signal chid, cdata, compared : std_logic;
|
||||
signal d_enable : std_logic_vector(3 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- Data bus or'ing
|
||||
cap_dout <= cap_reg_1;-- when cap_data_rd = '1' else cap_ctrl_dout;
|
||||
|
||||
chid <= cap_reg(6);
|
||||
cdata <= cap_reg(7);
|
||||
|
||||
-- capture data register
|
||||
CDAT: process (clk, rst)
|
||||
begin
|
||||
if rst = '1' then
|
||||
cap_reg_1 <= (others => '0'); --
|
||||
cap_new <= (others => '0');
|
||||
cur_pos <= 0;
|
||||
cap_len <= 0;
|
||||
cap_evt <= '0';
|
||||
compared <= '0';
|
||||
bitpos <= 0;
|
||||
bitlen <= 0;
|
||||
else
|
||||
if rising_edge(clk) then
|
||||
bitlen <= to_integer(unsigned(cap_reg(5 downto 0)));
|
||||
bitpos <= to_integer(unsigned(cap_reg(15 downto 8)));
|
||||
if bitlen > 0 then -- bitlen = 0 disables the capture function
|
||||
-- bit counter, 0 to 191
|
||||
if rx_block_start = '1' then
|
||||
cur_pos <= 0;
|
||||
cap_len <= 0;
|
||||
cap_new <= (others => '0');
|
||||
compared <= '0';
|
||||
elsif cs_b_en = '1' then -- ch. status #2 comes last, count then
|
||||
cur_pos <= cur_pos + 1;
|
||||
end if;
|
||||
-- capture bits
|
||||
if cur_pos >= bitpos and cap_len < bitlen then
|
||||
case d_enable is
|
||||
when "0001" => -- user data channel A
|
||||
if cdata = '0' and chid = '0' then
|
||||
cap_new(cap_len) <= ch_data;
|
||||
cap_len <= cap_len + 1;
|
||||
end if;
|
||||
when "0010" => -- user data channel B
|
||||
if cdata = '0' and chid = '1' then
|
||||
cap_new(cap_len) <= ch_data;
|
||||
cap_len <= cap_len + 1;
|
||||
end if;
|
||||
when "0100" => -- channel status ch. A
|
||||
if cdata = '1' and chid = '0' then
|
||||
cap_new(cap_len) <= ch_data;
|
||||
cap_len <= cap_len + 1;
|
||||
end if;
|
||||
when "1000" => -- channel status ch. B
|
||||
if cdata = '1' and chid = '1' then
|
||||
cap_new(cap_len) <= ch_data;
|
||||
cap_len <= cap_len + 1;
|
||||
end if;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
-- if all bits captured, check with previous data
|
||||
if cap_len = bitlen and compared = '0' then
|
||||
compared <= '1';
|
||||
-- event generated if captured bits differ
|
||||
if cap_reg_1 /= cap_new then
|
||||
cap_evt <= '1';
|
||||
end if;
|
||||
cap_reg_1 <= cap_new;
|
||||
else
|
||||
cap_evt <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process CDAT;
|
||||
|
||||
d_enable(0) <= ud_a_en;
|
||||
d_enable(1) <= ud_b_en;
|
||||
d_enable(2) <= cs_a_en;
|
||||
d_enable(3) <= cs_b_en;
|
||||
|
||||
end rtl;
|
||||
@@ -0,0 +1,265 @@
|
||||
----------------------------------------------------------------------
|
||||
---- ----
|
||||
---- WISHBONE SPDIF IP Core ----
|
||||
---- ----
|
||||
---- This file is part of the SPDIF project ----
|
||||
---- http://www.opencores.org/cores/spdif_interface/ ----
|
||||
---- ----
|
||||
---- Description ----
|
||||
---- Sample decoder. Extract sample words and write to sample ----
|
||||
---- buffer. ----
|
||||
---- ----
|
||||
---- ----
|
||||
---- To Do: ----
|
||||
---- - ----
|
||||
---- ----
|
||||
---- Author(s): ----
|
||||
---- - Geir Drange, [email protected] ----
|
||||
---- ----
|
||||
----------------------------------------------------------------------
|
||||
---- ----
|
||||
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
|
||||
---- ----
|
||||
---- This source file may be used and distributed without ----
|
||||
---- restriction provided that this copyright statement is not ----
|
||||
---- removed from the file and that any derivative work contains ----
|
||||
---- the original copyright notice and the associated disclaimer. ----
|
||||
---- ----
|
||||
---- This source file is free software; you can redistribute it ----
|
||||
---- and/or modify it under the terms of the GNU Lesser General ----
|
||||
---- Public License as published by the Free Software Foundation; ----
|
||||
---- either version 2.1 of the License, or (at your option) any ----
|
||||
---- later version. ----
|
||||
---- ----
|
||||
---- This source is distributed in the hope that it will be ----
|
||||
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
||||
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
||||
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
||||
---- details. ----
|
||||
---- ----
|
||||
---- You should have received a copy of the GNU Lesser General ----
|
||||
---- Public License along with this source; if not, download it ----
|
||||
---- from http://www.opencores.org/lgpl.shtml ----
|
||||
---- ----
|
||||
----------------------------------------------------------------------
|
||||
--
|
||||
-- CVS Revision History
|
||||
--
|
||||
-- $Log: not supported by cvs2svn $
|
||||
-- Revision 1.4 2004/07/11 16:19:50 gedra
|
||||
-- Bug-fix.
|
||||
--
|
||||
-- Revision 1.3 2004/06/26 14:14:47 gedra
|
||||
-- Converted to numeric_std and fixed a few bugs.
|
||||
--
|
||||
-- Revision 1.2 2004/06/16 19:04:09 gedra
|
||||
-- Fixed a few bugs.
|
||||
--
|
||||
-- Revision 1.1 2004/06/13 18:07:47 gedra
|
||||
-- Frame decoder and sample extractor
|
||||
--
|
||||
--
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity rx_decode is
|
||||
generic (DATA_WIDTH: integer range 16 to 32;
|
||||
ADDR_WIDTH: integer range 8 to 64);
|
||||
port (
|
||||
up_clk: in std_logic;
|
||||
conf_rxen: in std_logic;
|
||||
conf_sample: in std_logic;
|
||||
conf_valid: in std_logic;
|
||||
conf_mode: in std_logic_vector(3 downto 0);
|
||||
conf_blken: in std_logic;
|
||||
conf_valen: in std_logic;
|
||||
conf_useren: in std_logic;
|
||||
conf_staten: in std_logic;
|
||||
conf_paren: in std_logic;
|
||||
lock: in std_logic;
|
||||
rx_data: in std_logic;
|
||||
rx_data_en: in std_logic;
|
||||
rx_block_start: in std_logic;
|
||||
rx_frame_start: in std_logic;
|
||||
rx_channel_a: in std_logic;
|
||||
wr_en: out std_logic;
|
||||
wr_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0);
|
||||
wr_data: out std_logic_vector(DATA_WIDTH - 1 downto 0);
|
||||
stat_paritya: out std_logic;
|
||||
stat_parityb: out std_logic;
|
||||
stat_lsbf: out std_logic;
|
||||
stat_hsbf: out std_logic);
|
||||
end rx_decode;
|
||||
|
||||
architecture rtl of rx_decode is
|
||||
|
||||
signal adr_cnt : integer range 0 to 2**(ADDR_WIDTH - 1) - 1;
|
||||
type samp_states is (IDLE, CHA_SYNC, GET_SAMP, PAR_CHK);
|
||||
signal sampst : samp_states;
|
||||
signal bit_cnt, par_cnt : integer range 0 to 31;
|
||||
signal samp_start : integer range 0 to 15;
|
||||
signal tmp_data : std_logic_vector(31 downto 0);
|
||||
signal tmp_stat : std_logic_vector(4 downto 0);
|
||||
signal valid, next_is_a, blk_start : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- output data
|
||||
OD32: if DATA_WIDTH = 32 generate
|
||||
--wr_data(31 downto 27) <= tmp_stat;
|
||||
wr_data(31 downto 0) <= tmp_data(31 downto 0);
|
||||
end generate OD32;
|
||||
OD16: if DATA_WIDTH = 16 generate
|
||||
wr_data(15 downto 0) <= tmp_data(15 downto 0);
|
||||
end generate OD16;
|
||||
|
||||
-- State machine extracting audio samples
|
||||
SAEX: process (up_clk, conf_rxen)
|
||||
begin -- process SAEX
|
||||
if conf_rxen = '0' then
|
||||
adr_cnt <= 0;
|
||||
next_is_a <= '1';
|
||||
wr_en <= '0';
|
||||
wr_addr <= (others => '0');
|
||||
tmp_data <= (others => '0');
|
||||
par_cnt <= 0;
|
||||
blk_start <= '0';
|
||||
stat_paritya <= '0';
|
||||
stat_parityb <= '0';
|
||||
stat_lsbf <= '0';
|
||||
stat_hsbf <= '0';
|
||||
valid <= '0';
|
||||
bit_cnt <= 0;
|
||||
sampst <= IDLE;
|
||||
tmp_stat <= (others => '0');
|
||||
elsif rising_edge(up_clk) then
|
||||
--extract and store samples
|
||||
case sampst is
|
||||
when IDLE =>
|
||||
next_is_a <= '1';
|
||||
if lock = '1' and conf_sample = '1' then
|
||||
sampst <= CHA_SYNC;
|
||||
end if;
|
||||
when CHA_SYNC =>
|
||||
wr_addr <= std_logic_vector(to_unsigned(adr_cnt, ADDR_WIDTH - 1));
|
||||
wr_en <= '0';
|
||||
bit_cnt <= 0;
|
||||
valid <= '0';
|
||||
par_cnt <= 0;
|
||||
stat_paritya <= '0';
|
||||
stat_parityb <= '0';
|
||||
stat_lsbf <= '0';
|
||||
stat_hsbf <= '0';
|
||||
--tmp_data(31 downto 0) <= (others => '0');
|
||||
if rx_block_start = '1' and conf_blken = '1' then
|
||||
blk_start <= '1';
|
||||
end if;
|
||||
if rx_frame_start = '1' then --and rx_channel_a = '1' then --next_is_a then
|
||||
next_is_a <= rx_channel_a;
|
||||
if(rx_channel_a = '1') then
|
||||
tmp_data(31 downto 0) <= (others => '0');
|
||||
end if;
|
||||
sampst <= GET_SAMP;
|
||||
end if;
|
||||
when GET_SAMP =>
|
||||
tmp_stat(0) <= blk_start;
|
||||
if rx_data_en = '1' then
|
||||
bit_cnt <= bit_cnt + 1;
|
||||
-- audio part
|
||||
if bit_cnt >= samp_start and bit_cnt <= 23 then
|
||||
if(next_is_a = '1') then
|
||||
tmp_data(bit_cnt - samp_start) <= rx_data;
|
||||
else
|
||||
tmp_data(bit_cnt + 16 - samp_start) <= rx_data;
|
||||
end if;
|
||||
end if;
|
||||
-- status bits
|
||||
case bit_cnt is
|
||||
when 24 => -- validity bit
|
||||
valid <= rx_data;
|
||||
if conf_valen = '1' then
|
||||
tmp_stat(1) <= rx_data;
|
||||
else
|
||||
tmp_stat(1) <= '0';
|
||||
end if;
|
||||
when 25 => -- user data
|
||||
if conf_useren = '1' then
|
||||
tmp_stat(2) <= rx_data;
|
||||
else
|
||||
tmp_stat(2) <= '0';
|
||||
end if;
|
||||
when 26 => -- channel status
|
||||
if conf_staten = '1' then
|
||||
tmp_stat(3) <= rx_data;
|
||||
else
|
||||
tmp_stat(3) <= '0';
|
||||
end if;
|
||||
when 27 => -- parity bit
|
||||
if conf_paren = '1' then
|
||||
tmp_stat(4) <= rx_data;
|
||||
else
|
||||
tmp_stat(4) <= '0';
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
-- parity: count number of 1's
|
||||
if rx_data = '1' then
|
||||
par_cnt <= par_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
if bit_cnt = 28 then
|
||||
sampst <= PAR_CHK;
|
||||
end if;
|
||||
when PAR_CHK =>
|
||||
blk_start <= '0';
|
||||
if (((valid = '0' and conf_valid = '1') or conf_valid = '0') and (next_is_a = '0')) then
|
||||
wr_en <= '1';
|
||||
end if;
|
||||
-- parity check
|
||||
if par_cnt mod 2 /= 0 then
|
||||
if rx_channel_a = '1' then
|
||||
stat_paritya <= '1';
|
||||
else
|
||||
stat_parityb <= '1';
|
||||
end if;
|
||||
end if;
|
||||
-- address counter
|
||||
if adr_cnt < 2**(ADDR_WIDTH - 1) - 1 then
|
||||
adr_cnt <= adr_cnt + 1;
|
||||
else
|
||||
adr_cnt <= 0;
|
||||
stat_hsbf <= '1'; -- signal high buffer full
|
||||
end if;
|
||||
if adr_cnt = 2**(ADDR_WIDTH - 2) - 1 then
|
||||
stat_lsbf <= '1'; -- signal low buffer full
|
||||
end if;
|
||||
sampst <= CHA_SYNC;
|
||||
when others =>
|
||||
sampst <= IDLE;
|
||||
end case;
|
||||
end if;
|
||||
end process SAEX;
|
||||
|
||||
-- determine sample resolution from mode bits in 32bit mode
|
||||
M32: if DATA_WIDTH = 32 generate
|
||||
samp_start <= 8 when conf_mode = "0000" else
|
||||
7 when conf_mode = "0001" else
|
||||
6 when conf_mode = "0010" else
|
||||
5 when conf_mode = "0011" else
|
||||
4 when conf_mode = "0100" else
|
||||
3 when conf_mode = "0101" else
|
||||
2 when conf_mode = "0110" else
|
||||
1 when conf_mode = "0111" else
|
||||
0 when conf_mode = "1000" else
|
||||
8;
|
||||
end generate M32;
|
||||
-- in 16bit mode only 16bit of audio is supported
|
||||
M16: if DATA_WIDTH = 16 generate
|
||||
samp_start <= 8;
|
||||
end generate M16;
|
||||
|
||||
|
||||
end rtl;
|
||||
@@ -0,0 +1,248 @@
|
||||
----------------------------------------------------------------------
|
||||
---- ----
|
||||
---- WISHBONE SPDIF IP Core ----
|
||||
---- ----
|
||||
---- This file is part of the SPDIF project ----
|
||||
---- http://www.opencores.org/cores/spdif_interface/ ----
|
||||
---- ----
|
||||
---- Description ----
|
||||
---- SPDIF receiver component package. ----
|
||||
---- ----
|
||||
---- ----
|
||||
---- To Do: ----
|
||||
---- - ----
|
||||
---- ----
|
||||
---- Author(s): ----
|
||||
---- - Geir Drange, [email protected] ----
|
||||
---- ----
|
||||
----------------------------------------------------------------------
|
||||
---- ----
|
||||
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
|
||||
---- ----
|
||||
---- This source file may be used and distributed without ----
|
||||
---- restriction provided that this copyright statement is not ----
|
||||
---- removed from the file and that any derivative work contains ----
|
||||
---- the original copyright notice and the associated disclaimer. ----
|
||||
---- ----
|
||||
---- This source file is free software; you can redistribute it ----
|
||||
---- and/or modify it under the terms of the GNU Lesser General ----
|
||||
---- Public License as published by the Free Software Foundation; ----
|
||||
---- either version 2.1 of the License, or (at your option) any ----
|
||||
---- later version. ----
|
||||
---- ----
|
||||
---- This source is distributed in the hope that it will be ----
|
||||
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
||||
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
||||
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
||||
---- details. ----
|
||||
---- ----
|
||||
---- You should have received a copy of the GNU Lesser General ----
|
||||
---- Public License along with this source; if not, download it ----
|
||||
---- from http://www.opencores.org/lgpl.shtml ----
|
||||
---- ----
|
||||
----------------------------------------------------------------------
|
||||
--
|
||||
-- CVS Revision History
|
||||
--
|
||||
-- $Log: not supported by cvs2svn $
|
||||
-- Revision 1.8 2004/06/27 16:16:55 gedra
|
||||
-- Signal renaming and bug fix.
|
||||
--
|
||||
-- Revision 1.7 2004/06/26 14:14:47 gedra
|
||||
-- Converted to numeric_std and fixed a few bugs.
|
||||
--
|
||||
-- Revision 1.6 2004/06/23 18:10:17 gedra
|
||||
-- Added Wishbone bus cycle decoder.
|
||||
--
|
||||
-- Revision 1.5 2004/06/16 19:03:45 gedra
|
||||
-- Changed status reg. declaration
|
||||
--
|
||||
-- Revision 1.4 2004/06/13 18:08:09 gedra
|
||||
-- Added frame decoder and sample extractor
|
||||
--
|
||||
-- Revision 1.3 2004/06/10 18:57:36 gedra
|
||||
-- Cleaned up lint warnings.
|
||||
--
|
||||
-- Revision 1.2 2004/06/09 19:24:50 gedra
|
||||
-- Added dual port ram.
|
||||
--
|
||||
-- Revision 1.1 2004/06/07 18:06:00 gedra
|
||||
-- Receiver component declarations.
|
||||
--
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
||||
package rx_package is
|
||||
|
||||
-- type declarations
|
||||
type bus_array is array (0 to 7) of std_logic_vector(31 downto 0);
|
||||
|
||||
-- components
|
||||
component rx_ver_reg
|
||||
generic (DATA_WIDTH: integer := 32;
|
||||
ADDR_WIDTH: integer := 8;
|
||||
CH_ST_CAPTURE: integer := 1);
|
||||
port (
|
||||
ver_rd: in std_logic; -- version register read
|
||||
ver_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0)); -- read data
|
||||
end component;
|
||||
|
||||
component gen_control_reg
|
||||
generic (DATA_WIDTH: integer;
|
||||
-- note that this vector is (0 to xx), reverse order
|
||||
ACTIVE_BIT_MASK: std_logic_vector);
|
||||
port (
|
||||
clk: in std_logic; -- clock
|
||||
rst: in std_logic; -- reset
|
||||
ctrl_wr: in std_logic; -- control register write
|
||||
ctrl_rd: in std_logic; -- control register read
|
||||
ctrl_din: in std_logic_vector(DATA_WIDTH - 1 downto 0);
|
||||
ctrl_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0);
|
||||
ctrl_bits: out std_logic_vector(DATA_WIDTH - 1 downto 0));
|
||||
end component;
|
||||
|
||||
component rx_status_reg
|
||||
generic (DATA_WIDTH: integer := 32);
|
||||
port (
|
||||
up_clk: in std_logic; -- clock
|
||||
status_rd: in std_logic; -- status register read
|
||||
lock: in std_logic; -- signal lock status
|
||||
chas: in std_logic; -- channel A or B select
|
||||
rx_block_start: in std_logic; -- start of block signal
|
||||
ch_data: in std_logic; -- channel status/user data
|
||||
cs_a_en: in std_logic; -- channel status ch. A enable
|
||||
cs_b_en: in std_logic; -- channel status ch. B enable
|
||||
status_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));
|
||||
end component;
|
||||
|
||||
component gen_event_reg
|
||||
generic (DATA_WIDTH: integer := 32);
|
||||
port (
|
||||
clk: in std_logic; -- clock
|
||||
rst: in std_logic; -- reset
|
||||
evt_wr: in std_logic; -- event register write
|
||||
evt_rd: in std_logic; -- event register read
|
||||
evt_din: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data
|
||||
event: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- event vector
|
||||
evt_mask: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- irq mask
|
||||
evt_en: in std_logic; -- irq enable
|
||||
evt_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data
|
||||
evt_irq: out std_logic); -- interrupt request
|
||||
end component;
|
||||
|
||||
component rx_cap_reg
|
||||
port (
|
||||
clk: in std_logic; -- clock
|
||||
rst: in std_logic; -- reset
|
||||
--cap_ctrl_wr: in std_logic; -- control register write
|
||||
--cap_ctrl_rd: in std_logic; -- control register read
|
||||
--cap_data_rd: in std_logic; -- data register read
|
||||
cap_reg: in std_logic_vector(31 downto 0);
|
||||
cap_din: in std_logic_vector(31 downto 0); -- write data
|
||||
rx_block_start: in std_logic; -- start of block signal
|
||||
ch_data: in std_logic; -- channel status/user data
|
||||
ud_a_en: in std_logic; -- user data ch. A enable
|
||||
ud_b_en: in std_logic; -- user data ch. B enable
|
||||
cs_a_en: in std_logic; -- channel status ch. A enable
|
||||
cs_b_en: in std_logic; -- channel status ch. B enable
|
||||
cap_dout: out std_logic_vector(31 downto 0); -- read data
|
||||
cap_evt: out std_logic); -- capture event (interrupt)
|
||||
end component;
|
||||
|
||||
component rx_phase_det
|
||||
generic (AXI_FREQ: natural := 33); -- WishBone frequency in MHz
|
||||
port (
|
||||
up_clk: in std_logic;
|
||||
rxen: in std_logic;
|
||||
spdif: in std_logic;
|
||||
lock: out std_logic;
|
||||
lock_evt: out std_logic; -- lock status change event
|
||||
rx_data: out std_logic;
|
||||
rx_data_en: out std_logic;
|
||||
rx_block_start: out std_logic;
|
||||
rx_frame_start: out std_logic;
|
||||
rx_channel_a: out std_logic;
|
||||
rx_error: out std_logic;
|
||||
ud_a_en: out std_logic; -- user data ch. A enable
|
||||
ud_b_en: out std_logic; -- user data ch. B enable
|
||||
cs_a_en: out std_logic; -- channel status ch. A enable
|
||||
cs_b_en: out std_logic); -- channel status ch. B enable);
|
||||
end component;
|
||||
|
||||
component dpram
|
||||
generic (DATA_WIDTH: positive := 32;
|
||||
RAM_WIDTH: positive := 8);
|
||||
port (
|
||||
clk: in std_logic;
|
||||
rst: in std_logic; -- reset is optional, not used here
|
||||
din: in std_logic_vector(DATA_WIDTH - 1 downto 0);
|
||||
wr_en: in std_logic;
|
||||
rd_en: in std_logic;
|
||||
wr_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0);
|
||||
rd_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0);
|
||||
dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));
|
||||
end component;
|
||||
|
||||
component rx_decode
|
||||
generic (DATA_WIDTH: integer range 16 to 32 := 32;
|
||||
ADDR_WIDTH: integer range 8 to 64 := 8);
|
||||
port (
|
||||
up_clk: in std_logic;
|
||||
conf_rxen: in std_logic;
|
||||
conf_sample: in std_logic;
|
||||
conf_valid: in std_logic;
|
||||
conf_mode: in std_logic_vector(3 downto 0);
|
||||
conf_blken: in std_logic;
|
||||
conf_valen: in std_logic;
|
||||
conf_useren: in std_logic;
|
||||
conf_staten: in std_logic;
|
||||
conf_paren: in std_logic;
|
||||
lock: in std_logic;
|
||||
rx_data: in std_logic;
|
||||
rx_data_en: in std_logic;
|
||||
rx_block_start: in std_logic;
|
||||
rx_frame_start: in std_logic;
|
||||
rx_channel_a: in std_logic;
|
||||
wr_en: out std_logic;
|
||||
wr_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0);
|
||||
wr_data: out std_logic_vector(DATA_WIDTH - 1 downto 0);
|
||||
stat_paritya: out std_logic;
|
||||
stat_parityb: out std_logic;
|
||||
stat_lsbf: out std_logic;
|
||||
stat_hsbf: out std_logic);
|
||||
end component;
|
||||
|
||||
component rx_wb_decoder
|
||||
generic (DATA_WIDTH: integer := 32;
|
||||
ADDR_WIDTH: integer := 8);
|
||||
port (
|
||||
up_clk: in std_logic; -- wishbone clock
|
||||
wb_rst_i: in std_logic; -- reset signal
|
||||
wb_sel_i: in std_logic; -- select input
|
||||
wb_stb_i: in std_logic; -- strobe input
|
||||
wb_we_i: in std_logic; -- write enable
|
||||
wb_cyc_i: in std_logic; -- cycle input
|
||||
wb_bte_i: in std_logic_vector(1 downto 0); -- burts type extension
|
||||
wb_adr_i: in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- address
|
||||
wb_cti_i: in std_logic_vector(2 downto 0); -- cycle type identifier
|
||||
data_out: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus
|
||||
wb_ack_o: out std_logic; -- acknowledge
|
||||
wb_dat_o: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- data out
|
||||
version_rd: out std_logic; -- Version register read
|
||||
config_rd: out std_logic; -- Config register read
|
||||
config_wr: out std_logic; -- Config register write
|
||||
status_rd: out std_logic; -- Status register read
|
||||
intmask_rd: out std_logic; -- Interrupt mask register read
|
||||
intmask_wr: out std_logic; -- Interrupt mask register write
|
||||
intstat_rd: out std_logic; -- Interrupt status register read
|
||||
intstat_wr: out std_logic; -- Interrupt status register read
|
||||
mem_rd: out std_logic; -- Sample memory read
|
||||
mem_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0); -- memory addr.
|
||||
ch_st_cap_rd: out std_logic_vector(7 downto 0); -- Ch. status cap. read
|
||||
ch_st_cap_wr: out std_logic_vector(7 downto 0); -- Ch. status cap. write
|
||||
ch_st_data_rd: out std_logic_vector(7 downto 0)); -- Ch. status data read
|
||||
end component;
|
||||
|
||||
end rx_package;
|
||||
@@ -0,0 +1,398 @@
|
||||
----------------------------------------------------------------------
|
||||
---- ----
|
||||
---- WISHBONE SPDIF IP Core ----
|
||||
---- ----
|
||||
---- This file is part of the SPDIF project ----
|
||||
---- http://www.opencores.org/cores/spdif_interface/ ----
|
||||
---- ----
|
||||
---- Description ----
|
||||
---- Oversampling phase detector. Decodes bi-phase mark encoded ----
|
||||
---- signal. Clock must be at least 8 times higher than bit rate. ----
|
||||
---- The SPDIF bitrate must be minimum 100kHz. ----
|
||||
---- ----
|
||||
---- To Do: ----
|
||||
---- - ----
|
||||
---- ----
|
||||
---- Author(s): ----
|
||||
---- - Geir Drange, [email protected] ----
|
||||
---- ----
|
||||
----------------------------------------------------------------------
|
||||
---- ----
|
||||
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
|
||||
---- ----
|
||||
---- This source file may be used and distributed without ----
|
||||
---- restriction provided that this copyright statement is not ----
|
||||
---- removed from the file and that any derivative work contains ----
|
||||
---- the original copyright notice and the associated disclaimer. ----
|
||||
---- ----
|
||||
---- This source file is free software; you can redistribute it ----
|
||||
---- and/or modify it under the terms of the GNU Lesser General ----
|
||||
---- Public License as published by the Free Software Foundation; ----
|
||||
---- either version 2.1 of the License, or (at your option) any ----
|
||||
---- later version. ----
|
||||
---- ----
|
||||
---- This source is distributed in the hope that it will be ----
|
||||
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
||||
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
||||
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
||||
---- details. ----
|
||||
---- ----
|
||||
---- You should have received a copy of the GNU Lesser General ----
|
||||
---- Public License along with this source; if not, download it ----
|
||||
---- from http://www.opencores.org/lgpl.shtml ----
|
||||
---- ----
|
||||
----------------------------------------------------------------------
|
||||
--
|
||||
-- CVS Revision History
|
||||
--
|
||||
-- $Log: not supported by cvs2svn $
|
||||
-- Revision 1.5 2004/07/19 16:58:37 gedra
|
||||
-- Fixed bug.
|
||||
--
|
||||
-- Revision 1.4 2004/07/12 17:06:41 gedra
|
||||
-- Fixed bug with lock event generation.
|
||||
--
|
||||
-- Revision 1.3 2004/07/11 16:19:50 gedra
|
||||
-- Bug-fix.
|
||||
--
|
||||
-- Revision 1.2 2004/06/13 18:08:50 gedra
|
||||
-- Renamed generic and cleaned some lint's
|
||||
--
|
||||
-- Revision 1.1 2004/06/06 15:43:02 gedra
|
||||
-- Early version of the bi-phase mark decoder.
|
||||
--
|
||||
--
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity rx_phase_det is
|
||||
generic (AXI_FREQ: natural := 100); -- WishBone frequency in MHz
|
||||
port (
|
||||
up_clk: in std_logic; -- wishbone clock
|
||||
rxen: in std_logic; -- phase detector enable
|
||||
spdif: in std_logic; -- SPDIF input signal
|
||||
lock: out std_logic; -- true if locked to spdif input
|
||||
lock_evt: out std_logic; -- lock status change event
|
||||
rx_data: out std_logic; -- recevied data
|
||||
rx_data_en: out std_logic; -- received data enable
|
||||
rx_block_start: out std_logic; -- start-of-block pulse
|
||||
rx_frame_start: out std_logic; -- start-of-frame pulse
|
||||
rx_channel_a: out std_logic; -- 1 if channel A frame is recevied
|
||||
rx_error: out std_logic; -- signal error was detected
|
||||
ud_a_en: out std_logic; -- user data ch. A enable
|
||||
ud_b_en: out std_logic; -- user data ch. B enable
|
||||
cs_a_en: out std_logic; -- channel status ch. A enable
|
||||
cs_b_en: out std_logic); -- channel status ch. B enable);
|
||||
end rx_phase_det;
|
||||
|
||||
architecture rtl of rx_phase_det is
|
||||
|
||||
constant TRANSITIONS : integer := 70;
|
||||
constant FRAMES_FOR_LOCK : integer := 3;
|
||||
signal maxpulse, maxp, mp_cnt: integer range 0 to 16 * AXI_FREQ;
|
||||
signal last_cnt, max_thres : integer range 0 to 16 * AXI_FREQ;
|
||||
signal minpulse, minp, min_thres: integer range 0 to 8 * AXI_FREQ;
|
||||
signal zspdif, spdif_in, zspdif_in, trans, ztrans : std_logic;
|
||||
signal trans_cnt : integer range 0 to TRANSITIONS;
|
||||
signal valid, p_long, p_short: std_logic;
|
||||
type pulse_type is (ZERO, SHORT, MED, LONG);
|
||||
type pulse_array is array (0 to 3) of pulse_type;
|
||||
signal preamble: pulse_array;
|
||||
signal new_pulse, short_idx, ilock: std_logic;
|
||||
type frame_state is (IDLE, HUNT, FRAMESTART, FRAME_RX);
|
||||
signal framerx : frame_state;
|
||||
signal frame_cnt : integer range 0 to FRAMES_FOR_LOCK;
|
||||
signal bit_cnt : integer range 0 to 63;
|
||||
signal pre_cnt : integer range 0 to 7;
|
||||
type preamble_types is (NONE, PRE_X, PRE_Y, PRE_Z);
|
||||
signal new_preamble, last_preamble : preamble_types;
|
||||
signal irx_channel_a, zilock : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- Pulse width analyzer
|
||||
PHDET: process (up_clk, rxen)
|
||||
begin
|
||||
if rxen = '0' then -- reset by configuration register bit
|
||||
maxpulse <= 0;
|
||||
maxp <= 0;
|
||||
mp_cnt <= 0;
|
||||
zspdif <= '0';
|
||||
zspdif_in <= '0';
|
||||
spdif_in <= '0';
|
||||
trans_cnt <= 0;
|
||||
minpulse <= 0;
|
||||
minp <= 8 * AXI_FREQ;
|
||||
last_cnt <= 0;
|
||||
trans <= '0';
|
||||
valid <= '0';
|
||||
preamble <= (ZERO, ZERO, ZERO, ZERO);
|
||||
max_thres <= 0;
|
||||
min_thres <= 0;
|
||||
new_preamble <= NONE;
|
||||
ztrans <= '0';
|
||||
new_pulse <= '0';
|
||||
else
|
||||
if rising_edge(up_clk) then
|
||||
-- sync spdif signal to wishbone clock
|
||||
zspdif <= spdif;
|
||||
spdif_in <= zspdif;
|
||||
-- find the longest pulse, which is the bi-phase violation
|
||||
-- also find the shortest pulse
|
||||
zspdif_in <= spdif_in;
|
||||
if zspdif_in /= spdif_in then -- input transition
|
||||
mp_cnt <= 0;
|
||||
trans <= '1';
|
||||
last_cnt <= mp_cnt;
|
||||
if trans_cnt > 0 then
|
||||
if mp_cnt > maxp then
|
||||
maxp <= mp_cnt;
|
||||
end if;
|
||||
if mp_cnt < minp then
|
||||
minp <= mp_cnt;
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
trans <= '0';
|
||||
if mp_cnt < 16 * AXI_FREQ then
|
||||
mp_cnt <= mp_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
-- transition counting
|
||||
if trans = '1' then
|
||||
if trans_cnt < TRANSITIONS then
|
||||
trans_cnt <= trans_cnt + 1;
|
||||
else
|
||||
-- the max/min pulse length is updated after given # of transitions
|
||||
trans_cnt <= 0;
|
||||
maxpulse <= maxp;
|
||||
maxp <= 0;
|
||||
minpulse <= minp;
|
||||
minp <= 8 * AXI_FREQ;
|
||||
min_thres <= maxp / 2;
|
||||
if maxp < 11 then
|
||||
max_thres <= maxp - 1;
|
||||
else
|
||||
max_thres <= maxp - 3;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
-- detection of valid SPDIF signal
|
||||
if maxpulse > 6 then
|
||||
valid <= '1';
|
||||
else
|
||||
valid <= '0';
|
||||
end if;
|
||||
-- bit decoding
|
||||
if trans = '1' then
|
||||
if (last_cnt < min_thres) and (last_cnt > 0) then
|
||||
p_short <= '1';
|
||||
preamble(0) <= SHORT;
|
||||
else
|
||||
p_short <= '0';
|
||||
end if;
|
||||
if last_cnt >= max_thres then
|
||||
p_long <= '1';
|
||||
preamble(0) <= LONG;
|
||||
else
|
||||
p_long <= '0';
|
||||
end if;
|
||||
if last_cnt = 0 then
|
||||
preamble(0) <= ZERO;
|
||||
end if;
|
||||
if (last_cnt < max_thres) and (last_cnt >= min_thres) then
|
||||
preamble(0) <= MED;
|
||||
end if;
|
||||
preamble(3) <= preamble(2);
|
||||
preamble(2) <= preamble(1);
|
||||
preamble(1) <= preamble(0);
|
||||
end if;
|
||||
-- preamble detection
|
||||
if preamble(3) = LONG and preamble(2) = LONG and preamble(1) = SHORT
|
||||
and preamble(0) = SHORT then
|
||||
new_preamble <= PRE_X;
|
||||
elsif preamble(3) = LONG and preamble(2) = MED and preamble(1) = SHORT
|
||||
and preamble(0) = MED then
|
||||
new_preamble <= PRE_Y;
|
||||
elsif preamble(3) = LONG and preamble(2) = SHORT and preamble(1) = SHORT
|
||||
and preamble(0) = LONG then
|
||||
new_preamble <= PRE_Z;
|
||||
else
|
||||
new_preamble <= NONE;
|
||||
end if;
|
||||
-- delayed transition pulse for the state machine
|
||||
ztrans <= trans;
|
||||
new_pulse <= ztrans;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
lock <= ilock;
|
||||
rx_channel_a <= irx_channel_a;
|
||||
|
||||
-- State machine that hunt for and lock onto sub-frames
|
||||
FRX: process (up_clk, rxen)
|
||||
begin
|
||||
if rxen = '0' then
|
||||
framerx <= IDLE;
|
||||
ilock <= '0';
|
||||
zilock <= '0';
|
||||
rx_data <= '0';
|
||||
rx_data_en <= '0';
|
||||
rx_block_start <= '0';
|
||||
rx_frame_start <= '0';
|
||||
irx_channel_a <= '0';
|
||||
ud_a_en <= '0';
|
||||
ud_b_en <= '0';
|
||||
cs_a_en <= '0';
|
||||
cs_b_en <= '0';
|
||||
rx_error <= '0';
|
||||
lock_evt <= '0';
|
||||
bit_cnt <= 0;
|
||||
pre_cnt <= 0;
|
||||
short_idx <= '0';
|
||||
frame_cnt <= 0;
|
||||
last_preamble <= NONE;
|
||||
elsif rising_edge(up_clk) then
|
||||
zilock <= ilock;
|
||||
if zilock /= ilock then -- generate event for event reg.
|
||||
lock_evt <= '1';
|
||||
else
|
||||
lock_evt <= '0';
|
||||
end if;
|
||||
case framerx is
|
||||
when IDLE => -- wait for recevier to be enabled
|
||||
if valid = '1' then
|
||||
framerx <= HUNT;
|
||||
end if;
|
||||
when HUNT => -- wait for preamble detection
|
||||
frame_cnt <= 0;
|
||||
ilock <= '0';
|
||||
rx_error <= '0';
|
||||
if new_pulse = '1' then
|
||||
if new_preamble /= NONE then
|
||||
framerx <= FRAMESTART;
|
||||
end if;
|
||||
end if;
|
||||
when FRAMESTART => -- reset sub-frame bit counter
|
||||
bit_cnt <= 0;
|
||||
pre_cnt <= 0;
|
||||
if frame_cnt < FRAMES_FOR_LOCK then
|
||||
frame_cnt <= frame_cnt + 1;
|
||||
else
|
||||
ilock <= '1';
|
||||
end if;
|
||||
last_preamble <= new_preamble;
|
||||
short_idx <= '0';
|
||||
rx_frame_start <= '1';
|
||||
rx_block_start <= '0';
|
||||
framerx <= FRAME_RX;
|
||||
when FRAME_RX => -- receive complete sub-frame
|
||||
if new_pulse = '1' then
|
||||
if bit_cnt < 28 then
|
||||
case preamble(0) is
|
||||
when ZERO =>
|
||||
short_idx <= '0';
|
||||
when SHORT =>
|
||||
if short_idx = '0' then
|
||||
short_idx <= '1';
|
||||
else
|
||||
-- two short pulses is a logical '1'
|
||||
bit_cnt <= bit_cnt + 1;
|
||||
short_idx <= '0';
|
||||
rx_data <= '1';
|
||||
rx_data_en <= ilock;
|
||||
-- user data enable for the capture register
|
||||
if bit_cnt = 25 and ilock = '1' then
|
||||
ud_a_en <= irx_channel_a;
|
||||
ud_b_en <= not irx_channel_a;
|
||||
end if;
|
||||
-- channel status enable for the capture register
|
||||
if bit_cnt = 26 and ilock = '1' then
|
||||
cs_a_en <= irx_channel_a;
|
||||
cs_b_en <= not irx_channel_a;
|
||||
end if;
|
||||
end if;
|
||||
when MED =>
|
||||
-- medium pulse is logical '0'
|
||||
bit_cnt <= bit_cnt + 1;
|
||||
rx_data <= '0';
|
||||
rx_data_en <= ilock;
|
||||
short_idx <= '0';
|
||||
-- user data enable for the capture register
|
||||
if bit_cnt = 25 and ilock = '1' then
|
||||
ud_a_en <= irx_channel_a;
|
||||
ud_b_en <= not irx_channel_a;
|
||||
end if;
|
||||
-- channel status enable for the capture register
|
||||
if bit_cnt = 26 and ilock = '1' then
|
||||
cs_a_en <= irx_channel_a;
|
||||
cs_b_en <= not irx_channel_a;
|
||||
end if;
|
||||
when LONG =>
|
||||
short_idx <= '0';
|
||||
when others =>
|
||||
framerx <= HUNT;
|
||||
end case;
|
||||
else
|
||||
-- there should be 4 pulses in preamble
|
||||
if pre_cnt < 7 then
|
||||
pre_cnt <= pre_cnt + 1;
|
||||
else
|
||||
rx_error <= '1';
|
||||
framerx <= HUNT;
|
||||
end if;
|
||||
-- check for correct preamble here
|
||||
if pre_cnt = 3 then
|
||||
case last_preamble is
|
||||
when PRE_X =>
|
||||
if new_preamble = PRE_Y then
|
||||
framerx <= FRAMESTART;
|
||||
irx_channel_a <= '0';
|
||||
else
|
||||
rx_error <= '1';
|
||||
framerx <= HUNT;
|
||||
end if;
|
||||
when PRE_Y =>
|
||||
if new_preamble = PRE_X or new_preamble = PRE_Z then
|
||||
irx_channel_a <= '1';
|
||||
-- start of new block?
|
||||
if new_preamble = PRE_Z then
|
||||
rx_block_start <= '1';
|
||||
end if;
|
||||
framerx <= FRAMESTART;
|
||||
else
|
||||
rx_error <= '1';
|
||||
framerx <= HUNT;
|
||||
end if;
|
||||
when PRE_Z =>
|
||||
if new_preamble = PRE_Y then
|
||||
irx_channel_a <= '0';
|
||||
framerx <= FRAMESTART;
|
||||
else
|
||||
rx_error <= '1';
|
||||
framerx <= HUNT;
|
||||
end if;
|
||||
when others =>
|
||||
rx_error <= '1';
|
||||
framerx <= HUNT;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
rx_data_en <= '0';
|
||||
rx_block_start <= '0';
|
||||
rx_frame_start <= '0';
|
||||
ud_a_en <= '0';
|
||||
ud_b_en <= '0';
|
||||
cs_a_en <= '0';
|
||||
cs_b_en <= '0';
|
||||
end if;
|
||||
when others =>
|
||||
framerx <= IDLE;
|
||||
end case;
|
||||
end if;
|
||||
end process FRX;
|
||||
|
||||
end rtl;
|
||||
@@ -0,0 +1,150 @@
|
||||
----------------------------------------------------------------------
|
||||
---- ----
|
||||
---- WISHBONE SPDIF IP Core ----
|
||||
---- ----
|
||||
---- This file is part of the SPDIF project ----
|
||||
---- http://www.opencores.org/cores/spdif_interface/ ----
|
||||
---- ----
|
||||
---- Description ----
|
||||
---- SPDIF receiver status register ----
|
||||
---- ----
|
||||
---- ----
|
||||
---- To Do: ----
|
||||
---- - ----
|
||||
---- ----
|
||||
---- Author(s): ----
|
||||
---- - Geir Drange, [email protected] ----
|
||||
---- ----
|
||||
----------------------------------------------------------------------
|
||||
---- ----
|
||||
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
|
||||
---- ----
|
||||
---- This source file may be used and distributed without ----
|
||||
---- restriction provided that this copyright statement is not ----
|
||||
---- removed from the file and that any derivative work contains ----
|
||||
---- the original copyright notice and the associated disclaimer. ----
|
||||
---- ----
|
||||
---- This source file is free software; you can redistribute it ----
|
||||
---- and/or modify it under the terms of the GNU Lesser General ----
|
||||
---- Public License as published by the Free Software Foundation; ----
|
||||
---- either version 2.1 of the License, or (at your option) any ----
|
||||
---- later version. ----
|
||||
---- ----
|
||||
---- This source is distributed in the hope that it will be ----
|
||||
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
||||
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
||||
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
||||
---- details. ----
|
||||
---- ----
|
||||
---- You should have received a copy of the GNU Lesser General ----
|
||||
---- Public License along with this source; if not, download it ----
|
||||
---- from http://www.opencores.org/lgpl.shtml ----
|
||||
---- ----
|
||||
----------------------------------------------------------------------
|
||||
--
|
||||
-- CVS Revision History
|
||||
--
|
||||
-- $Log: not supported by cvs2svn $
|
||||
-- Revision 1.4 2004/06/27 16:16:55 gedra
|
||||
-- Signal renaming and bug fix.
|
||||
--
|
||||
-- Revision 1.3 2004/06/26 14:14:47 gedra
|
||||
-- Converted to numeric_std and fixed a few bugs.
|
||||
--
|
||||
-- Revision 1.2 2004/06/16 19:03:10 gedra
|
||||
-- Added channel status decoding.
|
||||
--
|
||||
-- Revision 1.1 2004/06/05 17:17:12 gedra
|
||||
-- Recevier status register
|
||||
--
|
||||
--
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity rx_status_reg is
|
||||
generic (DATA_WIDTH: integer);
|
||||
port (
|
||||
up_clk: in std_logic; -- clock
|
||||
status_rd: in std_logic; -- status register read
|
||||
lock: in std_logic; -- signal lock status
|
||||
chas: in std_logic; -- channel A or B select
|
||||
rx_block_start: in std_logic; -- start of block signal
|
||||
ch_data: in std_logic; -- channel status/user data
|
||||
cs_a_en: in std_logic; -- channel status ch. A enable
|
||||
cs_b_en: in std_logic; -- channel status ch. B enable
|
||||
status_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));
|
||||
end rx_status_reg;
|
||||
|
||||
architecture rtl of rx_status_reg is
|
||||
|
||||
signal status_vector : std_logic_vector(DATA_WIDTH - 1 downto 0);
|
||||
signal cur_pos : integer range 0 to 255;
|
||||
signal pro_mode : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
status_dout <= status_vector when status_rd = '1' else (others => '0');
|
||||
|
||||
D32: if DATA_WIDTH = 32 generate
|
||||
status_vector(31 downto 16) <= (others => '0');
|
||||
end generate D32;
|
||||
|
||||
status_vector(0) <= lock;
|
||||
status_vector(15 downto 7) <= (others => '0');
|
||||
|
||||
-- extract channel status bits to be used
|
||||
CDAT: process (up_clk, lock)
|
||||
begin
|
||||
if lock = '0' then
|
||||
cur_pos <= 0;
|
||||
pro_mode <= '0';
|
||||
status_vector(6 downto 1) <= (others => '0');
|
||||
else
|
||||
if rising_edge(up_clk) then
|
||||
-- bit counter, 0 to 191
|
||||
if rx_block_start = '1' then
|
||||
cur_pos <= 0;
|
||||
elsif cs_b_en = '1' then -- ch. status #2 comes last, count then
|
||||
cur_pos <= cur_pos + 1;
|
||||
end if;
|
||||
-- extract status bits used in status register
|
||||
if (chas = '0' and cs_b_en = '1') or
|
||||
(chas = '1' and cs_a_en = '1') then
|
||||
case cur_pos is
|
||||
when 0 => -- PRO bit
|
||||
status_vector(1) <= ch_data;
|
||||
pro_mode <= ch_data;
|
||||
when 1 => -- AUDIO bit
|
||||
status_vector(2) <= not ch_data;
|
||||
when 2 => -- emphasis/copy bit
|
||||
if pro_mode = '1' then
|
||||
status_vector(5) <= ch_data;
|
||||
else
|
||||
status_vector(6) <= ch_data;
|
||||
end if;
|
||||
when 3 => -- emphasis
|
||||
if pro_mode = '1' then
|
||||
status_vector(4) <= ch_data;
|
||||
else
|
||||
status_vector(5) <= ch_data;
|
||||
end if;
|
||||
when 4 => -- emphasis
|
||||
if pro_mode = '1' then
|
||||
status_vector(3) <= ch_data;
|
||||
else
|
||||
status_vector(4) <= ch_data;
|
||||
end if;
|
||||
when 5 => -- emphasis
|
||||
if pro_mode = '0' then
|
||||
status_vector(3) <= ch_data;
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process CDAT;
|
||||
|
||||
end rtl;
|
||||
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Thu Dec 9 15:16:27 2021
|
||||
# Process ID: 6273
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx
|
||||
# Command line: vivado -mode batch -source axi_spdif_rx_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source axi_spdif_rx_ip.tcl
|
||||
@@ -0,0 +1,764 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Thu Dec 9 15:16:27 2021
|
||||
# Process ID: 6273
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx
|
||||
# Command line: vivado -mode batch -source axi_spdif_rx_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source axi_spdif_rx_ip.tcl
|
||||
# source ../scripts/adi_env.tcl
|
||||
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
|
||||
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
|
||||
## if [info exists ::env(ADI_HDL_DIR)] {
|
||||
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
|
||||
## }
|
||||
## if [info exists ::env(ADI_GHDL_DIR)] {
|
||||
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
|
||||
## }
|
||||
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
|
||||
### variable auto_set_param_list
|
||||
### variable auto_set_param_list_overwritable
|
||||
### variable fpga_series_list
|
||||
### variable fpga_family_list
|
||||
### variable speed_grade_list
|
||||
### variable dev_package_list
|
||||
### variable xcvr_type_list
|
||||
### variable fpga_voltage_list
|
||||
### set auto_set_param_list { \
|
||||
### DEV_PACKAGE \
|
||||
### SPEED_GRADE \
|
||||
### FPGA_FAMILY \
|
||||
### FPGA_TECHNOLOGY }
|
||||
### set auto_set_param_list_overwritable { \
|
||||
### FPGA_VOLTAGE \
|
||||
### XCVR_TYPE }
|
||||
### set fpga_technology_list { \
|
||||
### { Unknown 0 } \
|
||||
### { 7series 1 } \
|
||||
### { ultrascale 2 } \
|
||||
### { ultrascale+ 3 }}
|
||||
### set fpga_family_list { \
|
||||
### { Unknown 0 } \
|
||||
### { artix 1 } \
|
||||
### { kintex 2 } \
|
||||
### { virtex 3 } \
|
||||
### { zynq 4 }}
|
||||
### set speed_grade_list { \
|
||||
### { Unknown 0 } \
|
||||
### { -1 10 } \
|
||||
### { -1L 11 } \
|
||||
### { -1H 12 } \
|
||||
### { -1HV 13 } \
|
||||
### { -1LV 14 } \
|
||||
### { -2 20 } \
|
||||
### { -2L 21 } \
|
||||
### { -2LV 22 } \
|
||||
### { -3 30 }}
|
||||
### set dev_package_list { \
|
||||
### { Unknown 0 } \
|
||||
### { rf 1 } \
|
||||
### { fl 2 } \
|
||||
### { ff 3 } \
|
||||
### { fb 4 } \
|
||||
### { hc 5 } \
|
||||
### { fh 6 } \
|
||||
### { cs 7 } \
|
||||
### { cp 8 } \
|
||||
### { ft 9 } \
|
||||
### { fg 10 } \
|
||||
### { sb 11 } \
|
||||
### { rb 12 } \
|
||||
### { rs 13 } \
|
||||
### { cl 14 } \
|
||||
### { sf 15 } \
|
||||
### { ba 16 } \
|
||||
### { fa 17 } \
|
||||
### { fs 18 } \
|
||||
### { fi 19 }}
|
||||
### set xcvr_type_list { \
|
||||
### { Unknown 0 } \
|
||||
### { GTPE2_NOT_SUPPORTED 1 } \
|
||||
### { GTXE2 2 } \
|
||||
### { GTHE2_NOT_SUPPORTED 3 } \
|
||||
### { GTZE2_NOT_SUPPORTED 4 } \
|
||||
### { GTHE3 5 } \
|
||||
### { GTYE3_NOT_SUPPORTED 6 } \
|
||||
### { GTRE4_NOT_SUPPORTED 7 } \
|
||||
### { GTHE4 8 } \
|
||||
### { GTYE4 9 } \
|
||||
### { GTME4_NOT_SUPPORTED 10}}
|
||||
### set fpga_voltage_list {0 5000} ;
|
||||
### proc adi_device_spec {cellpath param} {
|
||||
###
|
||||
### set list_pointer [string tolower $param]
|
||||
### set list_pointer [append list_pointer "_list"]
|
||||
###
|
||||
### upvar 1 $list_pointer $list_pointer
|
||||
###
|
||||
### set ip [get_bd_cells $cellpath]
|
||||
### set part [get_property PART [current_project]]
|
||||
###
|
||||
### switch -regexp -- $param {
|
||||
### FPGA_TECHNOLOGY {
|
||||
### switch -regexp -- $part {
|
||||
### ^xc7 {set series_name 7series}
|
||||
### ^xczu {set series_name ultrascale+}
|
||||
### ^xc.u.p {set series_name ultrascale+}
|
||||
### ^xc.u {set series_name ultrascale }
|
||||
### default {
|
||||
### puts "Undefined fpga technology for \"$part\"!"
|
||||
### exit -1
|
||||
### }
|
||||
### }
|
||||
### return "$series_name"
|
||||
### }
|
||||
### FPGA_FAMILY {
|
||||
### set fpga_family [get_property FAMILY $part]
|
||||
### foreach i $fpga_family_list {
|
||||
### regexp ^[lindex $i 0] $fpga_family matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### SPEED_GRADE {
|
||||
### set speed_grade [get_property SPEED $part]
|
||||
### return "$speed_grade"
|
||||
### }
|
||||
### DEV_PACKAGE {
|
||||
### set dev_package [get_property PACKAGE $part]
|
||||
### foreach i $dev_package_list {
|
||||
### regexp ^[lindex $i 0] $dev_package matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### XCVR_TYPE {
|
||||
### set matched ""
|
||||
### set dev_transcivers "none"
|
||||
### foreach x [list_property $part] {
|
||||
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
|
||||
### }
|
||||
### foreach i $xcvr_type_list {
|
||||
### regexp ^[lindex $i 0] $dev_transcivers matched
|
||||
### }
|
||||
### if { $matched eq "" } {
|
||||
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### FPGA_VOLTAGE {
|
||||
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
|
||||
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
|
||||
###
|
||||
### return "$fpga_voltage"
|
||||
### }
|
||||
### default {
|
||||
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
|
||||
### }
|
||||
### }
|
||||
### }
|
||||
## if {![info exists REQUIRED_VIVADO_VERSION]} {
|
||||
## set REQUIRED_VIVADO_VERSION "2019.1"
|
||||
## }
|
||||
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
|
||||
## set IGNORE_VERSION_CHECK 1
|
||||
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
|
||||
## set IGNORE_VERSION_CHECK 0
|
||||
## }
|
||||
## proc adi_ip_ttcl {ip_name ip_constr_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
|
||||
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_sim_ttcl {ip_name ip_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
|
||||
## set f [ipx::add_file $ip_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_bd {ip_name ip_bd_files} {
|
||||
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
|
||||
## if {$proj_filegroup == {}} {
|
||||
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
|
||||
## }
|
||||
##
|
||||
## foreach file $ip_bd_files {
|
||||
## set f [ipx::add_file $file $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type tclSource \
|
||||
## ] $f
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_infer_streaming_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_ip_infer_mm_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
|
||||
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency $port
|
||||
## if {$driver_value != {}} {
|
||||
## set_property DRIVER_VALUE $driver_value $port
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_set_bus_dependency {bus prefix dependency} {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
|
||||
## adi_set_ports_dependency $prefix $dependency 0
|
||||
## }
|
||||
## proc adi_add_port_map {bus phys logic} {
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## }
|
||||
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## adi_add_port_map $bus {*}$port_map
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
|
||||
## for {set i 0} {$i < $num} {incr i} {
|
||||
## set bus_name [format "%s%d" $bus_name_prefix $i]
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## if {$dependency ne ""} {
|
||||
## set bus_dependency [string map [list "{i}" $i] $dependency]
|
||||
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
|
||||
## }
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## lassign $port_map phys logic width width_dep
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
|
||||
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
|
||||
## if {$width_dep ne ""} {
|
||||
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
|
||||
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
|
||||
## set width_dep_r "(($width_dep) * $i)"
|
||||
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
|
||||
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
|
||||
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
|
||||
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
|
||||
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
|
||||
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
|
||||
## set_property display_name $clock_inf_name $clock_inf
|
||||
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
|
||||
## set_property physical_name $clock_signal_name $clock_map
|
||||
##
|
||||
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
|
||||
## set_property value $bus_inf_name $assoc_busif
|
||||
##
|
||||
## if { $reset_signal_name != "" } {
|
||||
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
|
||||
## set_property value $reset_signal_name $assoc_reset
|
||||
##
|
||||
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
|
||||
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
|
||||
## set_property display_name $reset_inf_name $reset_inf
|
||||
## set_property interface_mode $reset_signal_mode $reset_inf
|
||||
## set reset_map [ipx::add_port_map "RST" $reset_inf]
|
||||
## set_property physical_name $reset_signal_name $reset_map
|
||||
##
|
||||
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
|
||||
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
|
||||
## set_property value "ACTIVE_LOW" $reset_polarity
|
||||
## } else {
|
||||
## set_property value "ACTIVE_HIGH" $reset_polarity
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_add_core_dependencies {vlnvs} {
|
||||
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
|
||||
## foreach vlnv $vlnvs {
|
||||
## ipx::add_subcore $vlnv $file_group
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_create {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
## global ad_ghdl_dir
|
||||
## global REQUIRED_VIVADO_VERSION
|
||||
## global IGNORE_VERSION_CHECK
|
||||
##
|
||||
## set VIVADO_VERSION [version -short]
|
||||
## if {$IGNORE_VERSION_CHECK} {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## }
|
||||
## } else {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "ERROR: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
|
||||
## exit 2
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## create_project $ip_name . -force
|
||||
##
|
||||
## ## Load custom message severity definitions
|
||||
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
|
||||
##
|
||||
## set lib_dirs $ad_hdl_dir/library
|
||||
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
|
||||
## lappend lib_dirs $ad_ghdl_dir/library
|
||||
## }
|
||||
##
|
||||
## set_property ip_repo_paths $lib_dirs [current_fileset]
|
||||
## update_ip_catalog
|
||||
## }
|
||||
## proc adi_ip_files {ip_name ip_files} {
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## foreach m_file $ip_files {
|
||||
## if {[file extension $m_file] eq ".xdc"} {
|
||||
## add_files -norecurse -fileset constrs_1 $m_file
|
||||
## } else {
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
|
||||
## }
|
||||
## }
|
||||
## set_property "top" "$ip_name" $proj_fileset
|
||||
## }
|
||||
## proc adi_ip_properties_lite {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
##
|
||||
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
|
||||
##
|
||||
## set_property name $ip_name [ipx::current_core]
|
||||
##
|
||||
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
|
||||
## set_property company_url {http://www.analog.com} [ipx::current_core]
|
||||
##
|
||||
## set i_families ""
|
||||
## foreach i_part [get_parts] {
|
||||
## lappend i_families [get_property FAMILY $i_part]
|
||||
## }
|
||||
## set i_families [lsort -unique $i_families]
|
||||
## set s_families [get_property supported_families [ipx::current_core]]
|
||||
## foreach i_family $i_families {
|
||||
## set s_families "$s_families $i_family Production"
|
||||
## set s_families "$s_families $i_family Beta"
|
||||
## }
|
||||
## set_property supported_families $s_families [ipx::current_core]
|
||||
##
|
||||
## ipx::save_core [ipx::current_core]
|
||||
##
|
||||
## ipx::remove_all_bus_interface [ipx::current_core]
|
||||
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
|
||||
## foreach map $memory_maps {
|
||||
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
|
||||
## }
|
||||
##
|
||||
## ipx::update_checksums [ipx::current_core]
|
||||
## ipx::save_core [ipx::current_core]
|
||||
## }
|
||||
## proc adi_ip_properties {ip_name} {
|
||||
##
|
||||
## adi_ip_properties_lite $ip_name
|
||||
##
|
||||
## ipx::infer_bus_interface {\
|
||||
## s_axi_awvalid \
|
||||
## s_axi_awaddr \
|
||||
## s_axi_awprot \
|
||||
## s_axi_awready \
|
||||
## s_axi_wvalid \
|
||||
## s_axi_wdata \
|
||||
## s_axi_wstrb \
|
||||
## s_axi_wready \
|
||||
## s_axi_bvalid \
|
||||
## s_axi_bresp \
|
||||
##
|
||||
## s_axi_bready \
|
||||
## s_axi_arvalid \
|
||||
## s_axi_araddr \
|
||||
## s_axi_arprot \
|
||||
## s_axi_arready \
|
||||
## s_axi_rvalid \
|
||||
## s_axi_rdata \
|
||||
## s_axi_rresp \
|
||||
## s_axi_rready} \
|
||||
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
|
||||
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
|
||||
##
|
||||
## if {$raddr_width != $waddr_width} {
|
||||
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
|
||||
## set range 65536
|
||||
## } else {
|
||||
## if {$raddr_width >= 16} {
|
||||
## set range 65536
|
||||
## } else {
|
||||
## set range [expr 1 << $raddr_width]
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
## set_property range $range [ipx::get_address_blocks axi_lite \
|
||||
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
|
||||
## ipx::save_core
|
||||
## }
|
||||
## proc adi_init_bd_tcl {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## if { [file exists bd] } {
|
||||
## file delete -force bd
|
||||
## }
|
||||
## file mkdir bd
|
||||
##
|
||||
## set bd_tcl [open "bd/bd.tcl" w]
|
||||
##
|
||||
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
|
||||
## puts $bd_tcl "proc init {cellpath otherInfo} {"
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl ""
|
||||
## set auto_set_param ""
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
|
||||
## puts $bd_tcl $auto_set_param
|
||||
## }
|
||||
##
|
||||
## set auto_set_overwritable_param ""
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_overwritable_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_overwritable_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
|
||||
## puts $bd_tcl $auto_set_overwritable_param
|
||||
## }
|
||||
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
|
||||
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
|
||||
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set parent_dir \"../\""
|
||||
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
|
||||
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
|
||||
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " break"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " append parent_dir \"../\""
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## close $bd_tcl
|
||||
##
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
|
||||
##
|
||||
## set local_mk [open "temporary_case_dependencies.mk" w]
|
||||
## seek $local_mk 0 start
|
||||
## puts $local_mk "CLEAN_TARGET += bd"
|
||||
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
|
||||
## close $local_mk
|
||||
## }
|
||||
## proc adi_add_auto_fpga_spec_params {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_device_spec_param {ip_param} {
|
||||
##
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## set list_pointer [string tolower $ip_param]
|
||||
## set list_pointer [append list_pointer "_list"]
|
||||
##
|
||||
## global $list_pointer
|
||||
##
|
||||
## # set j 1D list from the original list
|
||||
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
|
||||
##
|
||||
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
|
||||
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "range_long" \
|
||||
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
|
||||
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## } else {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "pairs" \
|
||||
## "value_validation_pairs" $j ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## }
|
||||
##
|
||||
## # FPGA info grup
|
||||
## set info_group_name "FPGA info"
|
||||
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
|
||||
## if { [string trim $info_group] eq "" } {
|
||||
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
|
||||
## -parent $page0 -display_name $info_group_name]
|
||||
## }
|
||||
##
|
||||
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
|
||||
## set_property -dict [list "widget" "comboBox" ] $p
|
||||
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
|
||||
## }
|
||||
## proc adi_if_define {name} {
|
||||
##
|
||||
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
|
||||
## ipx::create_bus_definition analog.com interface $name 1.0
|
||||
##
|
||||
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
|
||||
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
|
||||
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
|
||||
##
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## }
|
||||
## proc adi_if_ports {dir width name {type none}} {
|
||||
##
|
||||
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
|
||||
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
|
||||
## set_property master_presence required $m_intf
|
||||
## set_property slave_presence required $m_intf
|
||||
## set_property master_width $width $m_intf
|
||||
## set_property slave_width $width $m_intf
|
||||
##
|
||||
## set m_dir "in"
|
||||
## set s_dir "out"
|
||||
## if {$dir eq "output"} {
|
||||
## set m_dir "out"
|
||||
## set s_dir "in"
|
||||
## }
|
||||
##
|
||||
## set_property master_direction $m_dir $m_intf
|
||||
## set_property slave_direction $s_dir $m_intf
|
||||
##
|
||||
## if {$type ne "none"} {
|
||||
## set_property is_${type} true $m_intf
|
||||
## }
|
||||
##
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## }
|
||||
## proc adi_if_infer_bus {if_name mode name maps} {
|
||||
##
|
||||
## ipx::add_bus_interface $name [ipx::current_core]
|
||||
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
|
||||
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
|
||||
## set_property interface_mode $mode $m_bus_if
|
||||
##
|
||||
## foreach map $maps {
|
||||
## set m_maps [regexp -all -inline {\S+} $map]
|
||||
## lassign $m_maps p_name p_map
|
||||
## ipx::add_port_map $p_name $m_bus_if
|
||||
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
|
||||
## }
|
||||
## }
|
||||
# adi_ip_create axi_spdif_rx
|
||||
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
|
||||
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1343} -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1306} -new_severity WARNING
|
||||
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
|
||||
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
|
||||
## set_msg_config -id {Synth 8-3331} -new_severity INFO
|
||||
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
|
||||
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
|
||||
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
|
||||
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'.)
|
||||
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
|
||||
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
|
||||
# adi_ip_files axi_spdif_rx [list \
|
||||
# "$ad_hdl_dir/library/common/axi_ctrlif.vhd" \
|
||||
# "$ad_hdl_dir/library/common/axi_streaming_dma_rx_fifo.vhd" \
|
||||
# "$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \
|
||||
# "$ad_hdl_dir/library/common/dma_fifo.vhd" \
|
||||
# "rx_phase_det.vhd" \
|
||||
# "rx_package.vhd" \
|
||||
# "rx_decode.vhd" \
|
||||
# "rx_status_reg.vhd" \
|
||||
# "axi_spdif_rx.vhd" ]
|
||||
# adi_ip_properties axi_spdif_rx
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_ctrlif.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_rx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/pl330_dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_ctrlif.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_rx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/pl330_dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'm_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_rstn'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3157] Bus Interface 'dma_req_rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'dma_req_rstn' is not *resetn - please double check the POLARITY setting.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'dma_req_aclk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 's_axi_aclk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
||||
# adi_ip_infer_streaming_interfaces axi_spdif_rx
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rstn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'm_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_rstn'.
|
||||
# adi_add_bus "dma_ack" "slave" \
|
||||
# "xilinx.com:interface:axis_rtl:1.0" \
|
||||
# "xilinx.com:interface:axis:1.0" \
|
||||
# [list {"dma_req_davalid" "TVALID"} \
|
||||
# {"dma_req_daready" "TREADY"} \
|
||||
# {"dma_req_datype" "TUSER"} ]
|
||||
# adi_add_bus "dma_req" "master" \
|
||||
# "xilinx.com:interface:axis_rtl:1.0" \
|
||||
# "xilinx.com:interface:axis:1.0" \
|
||||
# [list {"dma_req_drvalid" "TVALID"} \
|
||||
# {"dma_req_drready" "TREADY"} \
|
||||
# {"dma_req_drtype" "TUSER"} \
|
||||
# {"dma_req_drlast" "TLAST"} ]
|
||||
# adi_add_bus_clock "dma_req_aclk" "dma_req:dma_ack" "dma_req_rstn"
|
||||
# adi_set_bus_dependency "m_axis" "m_axis" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)"
|
||||
# adi_set_bus_dependency "dma_ack" "dma_req_da" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
|
||||
# adi_set_bus_dependency "dma_req" "dma_req_dr" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
|
||||
# adi_set_ports_dependency "dma_req_aclk" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
|
||||
# adi_set_ports_dependency "dma_req_rstn" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
|
||||
# ipx::save_core [ipx::current_core]
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:16:38 2021...
|
||||
@@ -0,0 +1,55 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "C_DMA_TYPE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_S_AXI_ADDR_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_S_AXI_DATA_WIDTH" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_DMA_TYPE { PARAM_VALUE.C_DMA_TYPE } {
|
||||
# Procedure called to update C_DMA_TYPE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_DMA_TYPE { PARAM_VALUE.C_DMA_TYPE } {
|
||||
# Procedure called to validate C_DMA_TYPE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to update C_S_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to validate C_S_AXI_ADDR_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
|
||||
# Procedure called to update C_S_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
|
||||
# Procedure called to validate C_S_AXI_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_DMA_TYPE { MODELPARAM_VALUE.C_DMA_TYPE PARAM_VALUE.C_DMA_TYPE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_DMA_TYPE}] ${MODELPARAM_VALUE.C_DMA_TYPE}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user