Archived
initial commit
This commit is contained in:
@@ -0,0 +1,19 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_spdif_tx
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GENERIC_DEPS += ../common/axi_ctrlif.vhd
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GENERIC_DEPS += ../common/axi_streaming_dma_tx_fifo.vhd
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GENERIC_DEPS += ../common/dma_fifo.vhd
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GENERIC_DEPS += ../common/pl330_dma_fifo.vhd
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GENERIC_DEPS += axi_spdif_tx.vhd
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GENERIC_DEPS += tx_encoder.vhd
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GENERIC_DEPS += tx_package.vhd
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XILINX_DEPS += axi_spdif_tx_constr.xdc
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XILINX_DEPS += axi_spdif_tx_ip.tcl
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include ../scripts/library.mk
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@@ -0,0 +1,3 @@
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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eof:
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@@ -0,0 +1,6 @@
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<?xml version="1.0" encoding="UTF-8"?>
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||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
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||||
<!-- -->
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<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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<labtools version="1" minor="0"/>
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@@ -0,0 +1,318 @@
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-- ***************************************************************************
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||||
-- ***************************************************************************
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||||
-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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--
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||||
-- In this HDL repository, there are many different and unique modules, consisting
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||||
-- of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
-- developed independently, and may be accompanied by separate and unique license
|
||||
-- terms.
|
||||
--
|
||||
-- The user should read each of these license terms, and understand the
|
||||
-- freedoms and responsibilities that he or she has by using this source/core.
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||||
--
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||||
-- This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
-- A PARTICULAR PURPOSE.
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||||
--
|
||||
-- Redistribution and use of source or resulting binaries, with or without modification
|
||||
-- of this file, are permitted under one of the following two license terms:
|
||||
--
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||||
-- 1. The GNU General Public License version 2 as published by the
|
||||
-- Free Software Foundation, which can be found in the top level directory
|
||||
-- of this repository (LICENSE_GPL2), and also online at:
|
||||
-- <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
--
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||||
-- OR
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||||
--
|
||||
-- 2. An ADI specific BSD license, which can be found in the top level directory
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||||
-- of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
-- This will allow to generate bit files and not release the source code,
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||||
-- as long as it attaches to an ADI device.
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||||
--
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-- ***************************************************************************
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||||
-- ***************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.tx_package.all;
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use work.axi_ctrlif;
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use work.axi_streaming_dma_tx_fifo;
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use work.pl330_dma_fifo;
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entity axi_spdif_tx is
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generic (
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S_AXI_DATA_WIDTH : integer := 32;
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S_AXI_ADDRESS_WIDTH : integer := 32;
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DEVICE_FAMILY : string := "virtex6";
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DMA_TYPE : integer := 0
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);
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port (
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--SPDIF ports
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spdif_data_clk : in std_logic;
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spdif_tx_o : out std_logic;
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--AXI Lite interface
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s_axi_aclk : in std_logic;
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s_axi_aresetn : in std_logic;
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s_axi_awaddr : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
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s_axi_awprot : in std_logic_vector(2 downto 0);
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s_axi_awvalid : in std_logic;
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s_axi_wdata : in std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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s_axi_wstrb : in std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0);
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s_axi_wvalid : in std_logic;
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s_axi_bready : in std_logic;
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s_axi_araddr : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
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s_axi_arprot : in std_logic_vector(2 downto 0);
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s_axi_arvalid : in std_logic;
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s_axi_rready : in std_logic;
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s_axi_arready : out std_logic;
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s_axi_rdata : out std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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s_axi_rresp : out std_logic_vector(1 downto 0);
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s_axi_rvalid : out std_logic;
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s_axi_wready : out std_logic;
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s_axi_bresp : out std_logic_vector(1 downto 0);
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s_axi_bvalid : out std_logic;
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s_axi_awready : out std_logic;
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--axi streaming interface
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s_axis_aclk : in std_logic;
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s_axis_aresetn : in std_logic;
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s_axis_tready : out std_logic;
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s_axis_tdata : in std_logic_vector(31 downto 0);
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s_axis_tlast : in std_logic;
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s_axis_tvalid : in std_logic;
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--PL330 DMA interface
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dma_req_aclk : in std_logic;
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dma_req_rstn : in std_logic;
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dma_req_davalid : in std_logic;
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dma_req_datype : in std_logic_vector(1 downto 0);
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dma_req_daready : out std_logic;
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dma_req_drvalid : out std_logic;
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dma_req_drtype : out std_logic_vector(1 downto 0);
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dma_req_drlast : out std_logic;
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dma_req_drready : in std_logic
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);
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end entity axi_spdif_tx;
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------------------------------------------------------------------------------
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-- Architecture section
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------------------------------------------------------------------------------
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architecture IMP of axi_spdif_tx is
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------------------------------------------
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-- SPDIF signals
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------------------------------------------
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signal config_reg : std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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signal chstatus_reg : std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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signal chstat_freq : std_logic_vector(1 downto 0);
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signal chstat_gstat, chstat_preem, chstat_copy, chstat_audio : std_logic;
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signal sample_data_ack : std_logic;
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signal sample_data: std_logic_vector(15 downto 0);
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signal conf_mode : std_logic_vector(3 downto 0);
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signal conf_ratio : std_logic_vector(7 downto 0);
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signal conf_tinten, conf_txdata, conf_txen : std_logic;
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signal channel : std_logic;
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signal enable : boolean;
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signal fifo_data_out : std_logic_vector(31 downto 0);
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signal fifo_data_ack : std_logic;
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signal fifo_reset : std_logic;
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signal tx_fifo_stb : std_logic;
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-- Register access
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signal wr_data : std_logic_vector(31 downto 0);
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signal rd_data : std_logic_vector(31 downto 0);
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signal wr_addr : integer range 0 to 3;
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signal rd_addr : integer range 0 to 3;
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signal wr_stb : std_logic;
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signal rd_ack : std_logic;
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begin
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fifo_reset <= not conf_txdata;
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enable <= conf_txdata = '1';
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fifo_data_ack <= channel and sample_data_ack;
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streaming_dma_gen: if DMA_TYPE = 0 generate
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fifo: entity axi_streaming_dma_tx_fifo
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generic map (
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RAM_ADDR_WIDTH => 3,
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FIFO_DWIDTH => 32
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)
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port map (
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clk => s_axi_aclk,
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resetn => s_axi_aresetn,
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fifo_reset => fifo_reset,
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enable => enable,
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s_axis_aclk => s_axis_aclk,
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s_axis_tready => s_axis_tready,
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s_axis_tdata => s_axis_tdata,
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s_axis_tvalid => s_axis_tlast,
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s_axis_tlast => s_axis_tvalid,
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out_ack => fifo_data_ack,
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out_data => fifo_data_out
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);
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end generate;
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no_streaming_dma_gen: if DMA_TYPE /= 0 generate
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s_axis_tready <= '0';
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end generate;
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pl330_dma_gen: if DMA_TYPE = 1 generate
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tx_fifo_stb <= '1' when wr_addr = 3 and wr_stb = '1' else '0';
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fifo: entity pl330_dma_fifo
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generic map(
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RAM_ADDR_WIDTH => 3,
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FIFO_DWIDTH => 32,
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FIFO_DIRECTION => 0
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)
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port map (
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clk => s_axi_aclk,
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resetn => s_axi_aresetn,
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fifo_reset => fifo_reset,
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enable => enable,
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in_data => wr_data,
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in_stb => tx_fifo_stb,
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out_ack => fifo_data_ack,
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out_data => fifo_data_out,
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dclk => dma_req_aclk,
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dresetn => dma_req_rstn,
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davalid => dma_req_davalid,
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daready => dma_req_daready,
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datype => dma_req_datype,
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drvalid => dma_req_drvalid,
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drready => dma_req_drreadY,
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drtype => dma_req_drtype,
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drlast => dma_req_drlast
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);
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end generate;
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no_pl330_dma_gen: if DMA_TYPE /= 1 generate
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dma_req_daready <= '0';
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dma_req_drvalid <= '0';
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dma_req_drtype <= (others => '0');
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dma_req_drlast <= '0';
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end generate;
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sample_data_mux: process (fifo_data_out, channel) is
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begin
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if channel = '0' then
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sample_data <= fifo_data_out(15 downto 0);
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else
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sample_data <= fifo_data_out(31 downto 16);
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end if;
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end process;
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-- Configuration signals update
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conf_mode(3 downto 0) <= config_reg(23 downto 20);
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conf_ratio(7 downto 0) <= config_reg(15 downto 8);
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conf_tinten <= config_reg(2);
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conf_txdata <= config_reg(1);
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conf_txen <= config_reg(0);
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-- Channel status signals update
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chstat_freq(1 downto 0) <= chstatus_reg(7 downto 6);
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chstat_gstat <= chstatus_reg(3);
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chstat_preem <= chstatus_reg(2);
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||||
chstat_copy <= chstatus_reg(1);
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chstat_audio <= chstatus_reg(0);
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||||
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||||
-- Transmit encoder
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||||
TENC: tx_encoder
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||||
generic map (
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||||
DATA_WIDTH => 16
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)
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port map (
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up_clk => s_axi_aclk,
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data_clk => spdif_data_clk, -- data clock
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||||
resetn => s_axi_aresetn, -- resetn
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conf_mode => conf_mode, -- sample format
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conf_ratio => conf_ratio, -- clock divider
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conf_txdata => conf_txdata, -- sample data enable
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conf_txen => conf_txen, -- spdif signal enable
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||||
chstat_freq => chstat_freq, -- sample freq.
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chstat_gstat => chstat_gstat, -- generation status
|
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chstat_preem => chstat_preem, -- preemphasis status
|
||||
chstat_copy => chstat_copy, -- copyright bit
|
||||
chstat_audio => chstat_audio, -- data format
|
||||
sample_data => sample_data, -- audio data
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||||
sample_data_ack => sample_data_ack, -- sample buffer read
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||||
channel => channel, -- which channel should be read
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spdif_tx_o => spdif_tx_o -- SPDIF output signal
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||||
);
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||||
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||||
ctrlif: entity axi_ctrlif
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||||
generic map (
|
||||
C_S_AXI_ADDR_WIDTH => S_AXI_ADDRESS_WIDTH,
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||||
C_S_AXI_DATA_WIDTH => S_AXI_DATA_WIDTH,
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||||
C_NUM_REG => 4
|
||||
)
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||||
port map(
|
||||
s_axi_aclk => s_axi_aclk,
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||||
s_axi_aresetn => s_axi_aresetn,
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s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
|
||||
rd_addr => rd_addr,
|
||||
rd_data => rd_data,
|
||||
rd_ack => rd_ack,
|
||||
rd_stb => '1',
|
||||
|
||||
wr_addr => wr_addr,
|
||||
wr_data => wr_data,
|
||||
wr_ack => '1',
|
||||
wr_stb => wr_stb
|
||||
);
|
||||
|
||||
process (s_axi_aclk)
|
||||
begin
|
||||
if rising_edge(s_axi_aclk) then
|
||||
if s_axi_aresetn = '0' then
|
||||
config_reg <= (others => '0');
|
||||
chstatus_reg <= (others => '0');
|
||||
else
|
||||
if wr_stb = '1' then
|
||||
case wr_addr is
|
||||
when 0 => config_reg <= wr_data;
|
||||
when 1 => chstatus_reg <= wr_data;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (rd_addr, config_reg, chstatus_reg)
|
||||
begin
|
||||
case rd_addr is
|
||||
when 0 => rd_data <= config_reg;
|
||||
when 1 => rd_data <= chstatus_reg;
|
||||
when others => rd_data <= (others => '0');
|
||||
end case;
|
||||
end process;
|
||||
|
||||
end IMP;
|
||||
@@ -0,0 +1,417 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx/axi_spdif_tx.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="b0539486630c482b8b582fd128de539d"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../common/axi_ctrlif.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/tx_package.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/dma_fifo.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/axi_streaming_dma_tx_fifo.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/pl330_dma_fifo.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/tx_encoder.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_spdif_tx.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_spdif_tx"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/axi_spdif_tx_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,11 @@
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -hier cdc_sync_stage1_*_reg] \
|
||||
[get_cells -hier cdc_sync_stage2_*_reg]
|
||||
|
||||
set_false_path \
|
||||
-from [get_cells -hier cdc_sync_stage0_*_reg -filter {PRIMITIVE_SUBGROUP == flop || primitive_subgroup == SDR}] \
|
||||
-to [get_cells -hier cdc_sync_stage1_*_reg -filter {PRIMITIVE_SUBGROUP == flop || primitive_subgroup == SDR}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_cells -hier spdif_out_reg -filter {PRIMITIVE_SUBGROUP == flop || primitive_subgroup == SDR}] \
|
||||
-to [get_cells -hier spdif_tx_o_reg -filter {PRIMITIVE_SUBGROUP == flop || primitive_subgroup == SDR}]
|
||||
@@ -0,0 +1,761 @@
|
||||
|
||||
****** Vivado v2019.1.3 (64-bit)
|
||||
**** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
**** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
source axi_spdif_tx_ip.tcl
|
||||
# source ../scripts/adi_env.tcl
|
||||
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
|
||||
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
|
||||
## if [info exists ::env(ADI_HDL_DIR)] {
|
||||
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
|
||||
## }
|
||||
## if [info exists ::env(ADI_GHDL_DIR)] {
|
||||
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
|
||||
## }
|
||||
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
|
||||
### variable auto_set_param_list
|
||||
### variable auto_set_param_list_overwritable
|
||||
### variable fpga_series_list
|
||||
### variable fpga_family_list
|
||||
### variable speed_grade_list
|
||||
### variable dev_package_list
|
||||
### variable xcvr_type_list
|
||||
### variable fpga_voltage_list
|
||||
### set auto_set_param_list { \
|
||||
### DEV_PACKAGE \
|
||||
### SPEED_GRADE \
|
||||
### FPGA_FAMILY \
|
||||
### FPGA_TECHNOLOGY }
|
||||
### set auto_set_param_list_overwritable { \
|
||||
### FPGA_VOLTAGE \
|
||||
### XCVR_TYPE }
|
||||
### set fpga_technology_list { \
|
||||
### { Unknown 0 } \
|
||||
### { 7series 1 } \
|
||||
### { ultrascale 2 } \
|
||||
### { ultrascale+ 3 }}
|
||||
### set fpga_family_list { \
|
||||
### { Unknown 0 } \
|
||||
### { artix 1 } \
|
||||
### { kintex 2 } \
|
||||
### { virtex 3 } \
|
||||
### { zynq 4 }}
|
||||
### set speed_grade_list { \
|
||||
### { Unknown 0 } \
|
||||
### { -1 10 } \
|
||||
### { -1L 11 } \
|
||||
### { -1H 12 } \
|
||||
### { -1HV 13 } \
|
||||
### { -1LV 14 } \
|
||||
### { -2 20 } \
|
||||
### { -2L 21 } \
|
||||
### { -2LV 22 } \
|
||||
### { -3 30 }}
|
||||
### set dev_package_list { \
|
||||
### { Unknown 0 } \
|
||||
### { rf 1 } \
|
||||
### { fl 2 } \
|
||||
### { ff 3 } \
|
||||
### { fb 4 } \
|
||||
### { hc 5 } \
|
||||
### { fh 6 } \
|
||||
### { cs 7 } \
|
||||
### { cp 8 } \
|
||||
### { ft 9 } \
|
||||
### { fg 10 } \
|
||||
### { sb 11 } \
|
||||
### { rb 12 } \
|
||||
### { rs 13 } \
|
||||
### { cl 14 } \
|
||||
### { sf 15 } \
|
||||
### { ba 16 } \
|
||||
### { fa 17 } \
|
||||
### { fs 18 } \
|
||||
### { fi 19 }}
|
||||
### set xcvr_type_list { \
|
||||
### { Unknown 0 } \
|
||||
### { GTPE2_NOT_SUPPORTED 1 } \
|
||||
### { GTXE2 2 } \
|
||||
### { GTHE2_NOT_SUPPORTED 3 } \
|
||||
### { GTZE2_NOT_SUPPORTED 4 } \
|
||||
### { GTHE3 5 } \
|
||||
### { GTYE3_NOT_SUPPORTED 6 } \
|
||||
### { GTRE4_NOT_SUPPORTED 7 } \
|
||||
### { GTHE4 8 } \
|
||||
### { GTYE4 9 } \
|
||||
### { GTME4_NOT_SUPPORTED 10}}
|
||||
### set fpga_voltage_list {0 5000} ;
|
||||
### proc adi_device_spec {cellpath param} {
|
||||
###
|
||||
### set list_pointer [string tolower $param]
|
||||
### set list_pointer [append list_pointer "_list"]
|
||||
###
|
||||
### upvar 1 $list_pointer $list_pointer
|
||||
###
|
||||
### set ip [get_bd_cells $cellpath]
|
||||
### set part [get_property PART [current_project]]
|
||||
###
|
||||
### switch -regexp -- $param {
|
||||
### FPGA_TECHNOLOGY {
|
||||
### switch -regexp -- $part {
|
||||
### ^xc7 {set series_name 7series}
|
||||
### ^xczu {set series_name ultrascale+}
|
||||
### ^xc.u.p {set series_name ultrascale+}
|
||||
### ^xc.u {set series_name ultrascale }
|
||||
### default {
|
||||
### puts "Undefined fpga technology for \"$part\"!"
|
||||
### exit -1
|
||||
### }
|
||||
### }
|
||||
### return "$series_name"
|
||||
### }
|
||||
### FPGA_FAMILY {
|
||||
### set fpga_family [get_property FAMILY $part]
|
||||
### foreach i $fpga_family_list {
|
||||
### regexp ^[lindex $i 0] $fpga_family matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### SPEED_GRADE {
|
||||
### set speed_grade [get_property SPEED $part]
|
||||
### return "$speed_grade"
|
||||
### }
|
||||
### DEV_PACKAGE {
|
||||
### set dev_package [get_property PACKAGE $part]
|
||||
### foreach i $dev_package_list {
|
||||
### regexp ^[lindex $i 0] $dev_package matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### XCVR_TYPE {
|
||||
### set matched ""
|
||||
### set dev_transcivers "none"
|
||||
### foreach x [list_property $part] {
|
||||
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
|
||||
### }
|
||||
### foreach i $xcvr_type_list {
|
||||
### regexp ^[lindex $i 0] $dev_transcivers matched
|
||||
### }
|
||||
### if { $matched eq "" } {
|
||||
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### FPGA_VOLTAGE {
|
||||
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
|
||||
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
|
||||
###
|
||||
### return "$fpga_voltage"
|
||||
### }
|
||||
### default {
|
||||
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
|
||||
### }
|
||||
### }
|
||||
### }
|
||||
## if {![info exists REQUIRED_VIVADO_VERSION]} {
|
||||
## set REQUIRED_VIVADO_VERSION "2019.1"
|
||||
## }
|
||||
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
|
||||
## set IGNORE_VERSION_CHECK 1
|
||||
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
|
||||
## set IGNORE_VERSION_CHECK 0
|
||||
## }
|
||||
## proc adi_ip_ttcl {ip_name ip_constr_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
|
||||
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_sim_ttcl {ip_name ip_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
|
||||
## set f [ipx::add_file $ip_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_bd {ip_name ip_bd_files} {
|
||||
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
|
||||
## if {$proj_filegroup == {}} {
|
||||
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
|
||||
## }
|
||||
##
|
||||
## foreach file $ip_bd_files {
|
||||
## set f [ipx::add_file $file $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type tclSource \
|
||||
## ] $f
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_infer_streaming_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_ip_infer_mm_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
|
||||
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency $port
|
||||
## if {$driver_value != {}} {
|
||||
## set_property DRIVER_VALUE $driver_value $port
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_set_bus_dependency {bus prefix dependency} {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
|
||||
## adi_set_ports_dependency $prefix $dependency 0
|
||||
## }
|
||||
## proc adi_add_port_map {bus phys logic} {
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## }
|
||||
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## adi_add_port_map $bus {*}$port_map
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
|
||||
## for {set i 0} {$i < $num} {incr i} {
|
||||
## set bus_name [format "%s%d" $bus_name_prefix $i]
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## if {$dependency ne ""} {
|
||||
## set bus_dependency [string map [list "{i}" $i] $dependency]
|
||||
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
|
||||
## }
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## lassign $port_map phys logic width width_dep
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
|
||||
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
|
||||
## if {$width_dep ne ""} {
|
||||
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
|
||||
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
|
||||
## set width_dep_r "(($width_dep) * $i)"
|
||||
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
|
||||
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
|
||||
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
|
||||
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
|
||||
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
|
||||
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
|
||||
## set_property display_name $clock_inf_name $clock_inf
|
||||
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
|
||||
## set_property physical_name $clock_signal_name $clock_map
|
||||
##
|
||||
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
|
||||
## set_property value $bus_inf_name $assoc_busif
|
||||
##
|
||||
## if { $reset_signal_name != "" } {
|
||||
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
|
||||
## set_property value $reset_signal_name $assoc_reset
|
||||
##
|
||||
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
|
||||
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
|
||||
## set_property display_name $reset_inf_name $reset_inf
|
||||
## set_property interface_mode $reset_signal_mode $reset_inf
|
||||
## set reset_map [ipx::add_port_map "RST" $reset_inf]
|
||||
## set_property physical_name $reset_signal_name $reset_map
|
||||
##
|
||||
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
|
||||
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
|
||||
## set_property value "ACTIVE_LOW" $reset_polarity
|
||||
## } else {
|
||||
## set_property value "ACTIVE_HIGH" $reset_polarity
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_add_core_dependencies {vlnvs} {
|
||||
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
|
||||
## foreach vlnv $vlnvs {
|
||||
## ipx::add_subcore $vlnv $file_group
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_create {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
## global ad_ghdl_dir
|
||||
## global REQUIRED_VIVADO_VERSION
|
||||
## global IGNORE_VERSION_CHECK
|
||||
##
|
||||
## set VIVADO_VERSION [version -short]
|
||||
## if {$IGNORE_VERSION_CHECK} {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## }
|
||||
## } else {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "ERROR: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
|
||||
## exit 2
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## create_project $ip_name . -force
|
||||
##
|
||||
## ## Load custom message severity definitions
|
||||
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
|
||||
##
|
||||
## set lib_dirs $ad_hdl_dir/library
|
||||
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
|
||||
## lappend lib_dirs $ad_ghdl_dir/library
|
||||
## }
|
||||
##
|
||||
## set_property ip_repo_paths $lib_dirs [current_fileset]
|
||||
## update_ip_catalog
|
||||
## }
|
||||
## proc adi_ip_files {ip_name ip_files} {
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## foreach m_file $ip_files {
|
||||
## if {[file extension $m_file] eq ".xdc"} {
|
||||
## add_files -norecurse -fileset constrs_1 $m_file
|
||||
## } else {
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
|
||||
## }
|
||||
## }
|
||||
## set_property "top" "$ip_name" $proj_fileset
|
||||
## }
|
||||
## proc adi_ip_properties_lite {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
##
|
||||
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
|
||||
##
|
||||
## set_property name $ip_name [ipx::current_core]
|
||||
##
|
||||
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
|
||||
## set_property company_url {http://www.analog.com} [ipx::current_core]
|
||||
##
|
||||
## set i_families ""
|
||||
## foreach i_part [get_parts] {
|
||||
## lappend i_families [get_property FAMILY $i_part]
|
||||
## }
|
||||
## set i_families [lsort -unique $i_families]
|
||||
## set s_families [get_property supported_families [ipx::current_core]]
|
||||
## foreach i_family $i_families {
|
||||
## set s_families "$s_families $i_family Production"
|
||||
## set s_families "$s_families $i_family Beta"
|
||||
## }
|
||||
## set_property supported_families $s_families [ipx::current_core]
|
||||
##
|
||||
## ipx::save_core [ipx::current_core]
|
||||
##
|
||||
## ipx::remove_all_bus_interface [ipx::current_core]
|
||||
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
|
||||
## foreach map $memory_maps {
|
||||
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
|
||||
## }
|
||||
##
|
||||
## ipx::update_checksums [ipx::current_core]
|
||||
## ipx::save_core [ipx::current_core]
|
||||
## }
|
||||
## proc adi_ip_properties {ip_name} {
|
||||
##
|
||||
## adi_ip_properties_lite $ip_name
|
||||
##
|
||||
## ipx::infer_bus_interface {\
|
||||
## s_axi_awvalid \
|
||||
## s_axi_awaddr \
|
||||
## s_axi_awprot \
|
||||
## s_axi_awready \
|
||||
## s_axi_wvalid \
|
||||
## s_axi_wdata \
|
||||
## s_axi_wstrb \
|
||||
## s_axi_wready \
|
||||
## s_axi_bvalid \
|
||||
## s_axi_bresp \
|
||||
##
|
||||
## s_axi_bready \
|
||||
## s_axi_arvalid \
|
||||
## s_axi_araddr \
|
||||
## s_axi_arprot \
|
||||
## s_axi_arready \
|
||||
## s_axi_rvalid \
|
||||
## s_axi_rdata \
|
||||
## s_axi_rresp \
|
||||
## s_axi_rready} \
|
||||
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
|
||||
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
|
||||
##
|
||||
## if {$raddr_width != $waddr_width} {
|
||||
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
|
||||
## set range 65536
|
||||
## } else {
|
||||
## if {$raddr_width >= 16} {
|
||||
## set range 65536
|
||||
## } else {
|
||||
## set range [expr 1 << $raddr_width]
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
## set_property range $range [ipx::get_address_blocks axi_lite \
|
||||
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
|
||||
## ipx::save_core
|
||||
## }
|
||||
## proc adi_init_bd_tcl {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## if { [file exists bd] } {
|
||||
## file delete -force bd
|
||||
## }
|
||||
## file mkdir bd
|
||||
##
|
||||
## set bd_tcl [open "bd/bd.tcl" w]
|
||||
##
|
||||
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
|
||||
## puts $bd_tcl "proc init {cellpath otherInfo} {"
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl ""
|
||||
## set auto_set_param ""
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
|
||||
## puts $bd_tcl $auto_set_param
|
||||
## }
|
||||
##
|
||||
## set auto_set_overwritable_param ""
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_overwritable_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_overwritable_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
|
||||
## puts $bd_tcl $auto_set_overwritable_param
|
||||
## }
|
||||
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
|
||||
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
|
||||
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set parent_dir \"../\""
|
||||
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
|
||||
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
|
||||
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " break"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " append parent_dir \"../\""
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## close $bd_tcl
|
||||
##
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
|
||||
##
|
||||
## set local_mk [open "temporary_case_dependencies.mk" w]
|
||||
## seek $local_mk 0 start
|
||||
## puts $local_mk "CLEAN_TARGET += bd"
|
||||
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
|
||||
## close $local_mk
|
||||
## }
|
||||
## proc adi_add_auto_fpga_spec_params {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_device_spec_param {ip_param} {
|
||||
##
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## set list_pointer [string tolower $ip_param]
|
||||
## set list_pointer [append list_pointer "_list"]
|
||||
##
|
||||
## global $list_pointer
|
||||
##
|
||||
## # set j 1D list from the original list
|
||||
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
|
||||
##
|
||||
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
|
||||
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "range_long" \
|
||||
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
|
||||
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## } else {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "pairs" \
|
||||
## "value_validation_pairs" $j ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## }
|
||||
##
|
||||
## # FPGA info grup
|
||||
## set info_group_name "FPGA info"
|
||||
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
|
||||
## if { [string trim $info_group] eq "" } {
|
||||
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
|
||||
## -parent $page0 -display_name $info_group_name]
|
||||
## }
|
||||
##
|
||||
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
|
||||
## set_property -dict [list "widget" "comboBox" ] $p
|
||||
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
|
||||
## }
|
||||
## proc adi_if_define {name} {
|
||||
##
|
||||
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
|
||||
## ipx::create_bus_definition analog.com interface $name 1.0
|
||||
##
|
||||
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
|
||||
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
|
||||
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
|
||||
##
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## }
|
||||
## proc adi_if_ports {dir width name {type none}} {
|
||||
##
|
||||
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
|
||||
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
|
||||
## set_property master_presence required $m_intf
|
||||
## set_property slave_presence required $m_intf
|
||||
## set_property master_width $width $m_intf
|
||||
## set_property slave_width $width $m_intf
|
||||
##
|
||||
## set m_dir "in"
|
||||
## set s_dir "out"
|
||||
## if {$dir eq "output"} {
|
||||
## set m_dir "out"
|
||||
## set s_dir "in"
|
||||
## }
|
||||
##
|
||||
## set_property master_direction $m_dir $m_intf
|
||||
## set_property slave_direction $s_dir $m_intf
|
||||
##
|
||||
## if {$type ne "none"} {
|
||||
## set_property is_${type} true $m_intf
|
||||
## }
|
||||
##
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## }
|
||||
## proc adi_if_infer_bus {if_name mode name maps} {
|
||||
##
|
||||
## ipx::add_bus_interface $name [ipx::current_core]
|
||||
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
|
||||
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
|
||||
## set_property interface_mode $mode $m_bus_if
|
||||
##
|
||||
## foreach map $maps {
|
||||
## set m_maps [regexp -all -inline {\S+} $map]
|
||||
## lassign $m_maps p_name p_map
|
||||
## ipx::add_port_map $p_name $m_bus_if
|
||||
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
|
||||
## }
|
||||
## }
|
||||
# adi_ip_create axi_spdif_tx
|
||||
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
|
||||
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1343} -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1306} -new_severity WARNING
|
||||
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
|
||||
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
|
||||
## set_msg_config -id {Synth 8-3331} -new_severity INFO
|
||||
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
|
||||
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
|
||||
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
|
||||
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'.)
|
||||
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
|
||||
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
|
||||
# adi_ip_files axi_spdif_tx [list \
|
||||
# "$ad_hdl_dir/library/common/axi_ctrlif.vhd" \
|
||||
# "$ad_hdl_dir/library/common/axi_streaming_dma_tx_fifo.vhd" \
|
||||
# "$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \
|
||||
# "$ad_hdl_dir/library/common/dma_fifo.vhd" \
|
||||
# "tx_package.vhd" \
|
||||
# "tx_encoder.vhd" \
|
||||
# "axi_spdif_tx.vhd" \
|
||||
# "axi_spdif_tx_constr.xdc" ]
|
||||
# adi_ip_properties axi_spdif_tx
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_ctrlif.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_tx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/pl330_dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_ctrlif.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_tx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/pl330_dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'spdif_clk' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axis'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_rstn'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axis_aresetn'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'spdif_clk': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3157] Bus Interface 'dma_req_rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'dma_req_rstn' is not *resetn - please double check the POLARITY setting.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'dma_req_aclk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
WARNING: [IP_Flow 19-3238] Range of address space is set to a full 4G (Address Block 'reg0' of Memory Map 's_axi'). Consider reducing this by setting the range of the address block to a lower number, or alternatively reduce the number of bits on the address line in your HDL's top level file interface.
|
||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
||||
# adi_ip_infer_streaming_interfaces axi_spdif_tx
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'spdif_data_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rstn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axis'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_rstn'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axis_aresetn'.
|
||||
# adi_add_bus "dma_ack" "slave" \
|
||||
# "xilinx.com:interface:axis_rtl:1.0" \
|
||||
# "xilinx.com:interface:axis:1.0" \
|
||||
# [list {"dma_req_davalid" "TVALID"} \
|
||||
# {"dma_req_daready" "TREADY"} \
|
||||
# {"dma_req_datype" "TUSER"} ]
|
||||
# adi_add_bus "dma_req" "master" \
|
||||
# "xilinx.com:interface:axis_rtl:1.0" \
|
||||
# "xilinx.com:interface:axis:1.0" \
|
||||
# [list {"dma_req_drvalid" "TVALID"} \
|
||||
# {"dma_req_drready" "TREADY"} \
|
||||
# {"dma_req_drtype" "TUSER"} \
|
||||
# {"dma_req_drlast" "TLAST"} ]
|
||||
# adi_add_bus_clock "dma_req_aclk" "dma_req:dma_ack" "dma_req_rstn"
|
||||
# adi_set_bus_dependency "s_axis" "s_axis" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0)"
|
||||
# adi_set_bus_dependency "dma_ack" "dma_req_da" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
|
||||
# adi_set_bus_dependency "dma_req" "dma_req_dr" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
|
||||
# adi_set_ports_dependency "dma_req_aclk" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
|
||||
# adi_set_ports_dependency "dma_req_rstn" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
|
||||
# ipx::save_core [ipx::current_core]
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:23:28 2021...
|
||||
@@ -0,0 +1,50 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_spdif_tx
|
||||
adi_ip_files axi_spdif_tx [list \
|
||||
"$ad_hdl_dir/library/common/axi_ctrlif.vhd" \
|
||||
"$ad_hdl_dir/library/common/axi_streaming_dma_tx_fifo.vhd" \
|
||||
"$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \
|
||||
"$ad_hdl_dir/library/common/dma_fifo.vhd" \
|
||||
"tx_package.vhd" \
|
||||
"tx_encoder.vhd" \
|
||||
"axi_spdif_tx.vhd" \
|
||||
"axi_spdif_tx_constr.xdc" ]
|
||||
|
||||
adi_ip_properties axi_spdif_tx
|
||||
adi_ip_infer_streaming_interfaces axi_spdif_tx
|
||||
|
||||
adi_add_bus "dma_ack" "slave" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
[list {"dma_req_davalid" "TVALID"} \
|
||||
{"dma_req_daready" "TREADY"} \
|
||||
{"dma_req_datype" "TUSER"} ]
|
||||
adi_add_bus "dma_req" "master" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
[list {"dma_req_drvalid" "TVALID"} \
|
||||
{"dma_req_drready" "TREADY"} \
|
||||
{"dma_req_drtype" "TUSER"} \
|
||||
{"dma_req_drlast" "TLAST"} ]
|
||||
|
||||
# Clock and reset are for both dma_req and dma_ack
|
||||
adi_add_bus_clock "dma_req_aclk" "dma_req:dma_ack" "dma_req_rstn"
|
||||
|
||||
adi_set_bus_dependency "s_axis" "s_axis" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0)"
|
||||
|
||||
adi_set_bus_dependency "dma_ack" "dma_req_da" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
|
||||
adi_set_bus_dependency "dma_req" "dma_req_dr" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "dma_req_aclk" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "dma_req_rstn" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,495 @@
|
||||
----------------------------------------------------------------------
|
||||
---- ----
|
||||
---- WISHBONE SPDIF IP Core ----
|
||||
---- ----
|
||||
---- This file is part of the SPDIF project ----
|
||||
---- http://www.opencores.org/cores/spdif_interface/ ----
|
||||
---- ----
|
||||
---- Description ----
|
||||
---- SPDIF transmitter signal encoder. Reads out samples from the ----
|
||||
---- sample buffer, assembles frames and subframes and encodes ----
|
||||
---- serial data as bi-phase mark code. ----
|
||||
---- ----
|
||||
---- To Do: ----
|
||||
---- - ----
|
||||
---- ----
|
||||
---- Author(s): ----
|
||||
---- - Geir Drange, [email protected] ----
|
||||
---- ----
|
||||
----------------------------------------------------------------------
|
||||
---- ----
|
||||
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
|
||||
---- ----
|
||||
---- This source file may be used and distributed without ----
|
||||
---- restriction provided that this copyright statement is not ----
|
||||
---- removed from the file and that any derivative work contains ----
|
||||
---- the original copyright notice and the associated disclaimer. ----
|
||||
---- ----
|
||||
---- This source file is free software; you can redistribute it ----
|
||||
---- and/or modify it under the terms of the GNU Lesser General ----
|
||||
---- Public License as published by the Free Software Foundation; ----
|
||||
---- either version 2.1 of the License, or (at your option) any ----
|
||||
---- later version. ----
|
||||
---- ----
|
||||
---- This source is distributed in the hope that it will be ----
|
||||
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
||||
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
||||
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
||||
---- details. ----
|
||||
---- ----
|
||||
---- You should have received a copy of the GNU Lesser General ----
|
||||
---- Public License along with this source; if not, download it ----
|
||||
---- from http://www.opencores.org/lgpl.shtml ----
|
||||
---- ----
|
||||
----------------------------------------------------------------------
|
||||
--
|
||||
-- CVS Revision History
|
||||
--
|
||||
-- $Log: not supported by cvs2svn $
|
||||
--
|
||||
--
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity tx_encoder is
|
||||
generic (DATA_WIDTH: integer range 16 to 32 := 32);
|
||||
port (
|
||||
up_clk: in std_logic; -- clock
|
||||
data_clk : in std_logic; -- data clock
|
||||
resetn : in std_logic; -- resetn
|
||||
conf_mode: in std_logic_vector(3 downto 0); -- sample format
|
||||
conf_ratio: in std_logic_vector(7 downto 0); -- clock divider
|
||||
conf_txdata: in std_logic; -- sample data enable
|
||||
conf_txen: in std_logic; -- spdif signal enable
|
||||
chstat_freq: in std_logic_vector(1 downto 0); -- sample freq.
|
||||
chstat_gstat: in std_logic; -- generation status
|
||||
chstat_preem: in std_logic; -- preemphasis status
|
||||
chstat_copy: in std_logic; -- copyright bit
|
||||
chstat_audio: in std_logic; -- data format
|
||||
sample_data: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
|
||||
sample_data_ack: out std_logic; -- sample buffer read
|
||||
channel: out std_logic;
|
||||
spdif_tx_o: out std_logic);
|
||||
end tx_encoder;
|
||||
|
||||
architecture rtl of tx_encoder is
|
||||
|
||||
signal spdif_clk_en, spdif_out : std_logic;
|
||||
signal clk_cnt : integer range 0 to 511;
|
||||
type buf_states is (IDLE, READ_CHA, READ_CHB, CHA_RDY, CHB_RDY);
|
||||
signal bufctrl : buf_states;
|
||||
signal cha_samp_ack, chb_samp_ack : std_logic;
|
||||
type frame_states is (IDLE, BLOCK_START, CHANNEL_A, CHANNEL_B);
|
||||
signal framest : frame_states;
|
||||
signal frame_cnt : integer range 0 to 191;
|
||||
signal bit_cnt, par_cnt : integer range 0 to 31;
|
||||
signal inv_preamble, toggle, valid : std_logic;
|
||||
signal def_user_data, def_ch_status : std_logic_vector(191 downto 0);
|
||||
signal active_user_data, active_ch_status : std_logic_vector(191 downto 0);
|
||||
signal audio : std_logic_vector(23 downto 0);
|
||||
signal par_vector : std_logic_vector(26 downto 0);
|
||||
signal send_audio : std_logic;
|
||||
|
||||
signal cdc_sync_stage0_tick_counter : std_logic := '0';
|
||||
signal cdc_sync_stage1_tick_counter : std_logic := '0';
|
||||
signal cdc_sync_stage2_tick_counter : std_logic := '0';
|
||||
signal cdc_sync_stage3_tick_counter : std_logic := '0';
|
||||
signal tick_counter : std_logic;
|
||||
|
||||
constant X_PREAMBLE : std_logic_vector(0 to 7) := "11100010";
|
||||
constant Y_PREAMBLE : std_logic_vector(0 to 7) := "11100100";
|
||||
constant Z_PREAMBLE : std_logic_vector(0 to 7) := "11101000";
|
||||
|
||||
function encode_bit (
|
||||
signal bit_cnt : integer; -- sub-frame bit position
|
||||
signal valid : std_logic; -- validity bit
|
||||
signal frame_cnt : integer; -- frame counter
|
||||
signal par_cnt : integer; -- parity counter
|
||||
signal user_data : std_logic_vector(191 downto 0);
|
||||
signal ch_status : std_logic_vector(191 downto 0);
|
||||
signal audio : std_logic_vector(23 downto 0);
|
||||
signal toggle : std_logic;
|
||||
signal prev_spdif : std_logic) -- prev. value of spdif signal
|
||||
|
||||
return std_logic is
|
||||
variable spdif, next_bit : std_logic;
|
||||
begin
|
||||
if bit_cnt > 3 and bit_cnt < 28 then -- audio part
|
||||
next_bit := audio(bit_cnt - 4);
|
||||
elsif bit_cnt = 28 then -- validity bit
|
||||
next_bit := valid;
|
||||
elsif bit_cnt = 29 then -- user data
|
||||
next_bit := user_data(frame_cnt);
|
||||
elsif bit_cnt = 30 then
|
||||
next_bit := ch_status(frame_cnt); -- channel status
|
||||
elsif bit_cnt = 31 then
|
||||
if par_cnt mod 2 = 1 then
|
||||
next_bit := '1';
|
||||
else
|
||||
next_bit := '0';
|
||||
end if;
|
||||
end if;
|
||||
-- bi-phase mark encoding:
|
||||
if next_bit = '0' then
|
||||
if toggle = '0' then
|
||||
spdif := not prev_spdif;
|
||||
else
|
||||
spdif := prev_spdif;
|
||||
end if;
|
||||
else
|
||||
spdif := not prev_spdif;
|
||||
end if;
|
||||
return(spdif);
|
||||
end encode_bit;
|
||||
|
||||
begin
|
||||
|
||||
-- SPDIF clock enable generation. The clock is a fraction of the data clock,
|
||||
-- determined by the conf_ratio value.
|
||||
DCLK : process (data_clk)
|
||||
begin
|
||||
if rising_edge(data_clk) then
|
||||
cdc_sync_stage0_tick_counter <= not cdc_sync_stage0_tick_counter;
|
||||
end if;
|
||||
end process DCLK;
|
||||
|
||||
process (up_clk) begin
|
||||
if rising_edge(up_clk) then
|
||||
cdc_sync_stage1_tick_counter <= cdc_sync_stage0_tick_counter;
|
||||
cdc_sync_stage2_tick_counter <= cdc_sync_stage1_tick_counter;
|
||||
cdc_sync_stage3_tick_counter <= cdc_sync_stage2_tick_counter;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
tick_counter <= cdc_sync_stage3_tick_counter xor cdc_sync_stage2_tick_counter;
|
||||
|
||||
CGEN: process (up_clk)
|
||||
begin
|
||||
if rising_edge(up_clk) then
|
||||
if resetn = '0' or conf_txen = '0' then
|
||||
clk_cnt <= 0;
|
||||
spdif_clk_en <= '0';
|
||||
else
|
||||
spdif_clk_en <= '0';
|
||||
|
||||
if tick_counter = '1' then
|
||||
if clk_cnt < to_integer(unsigned(conf_ratio)) then
|
||||
clk_cnt <= clk_cnt + 1;
|
||||
else
|
||||
clk_cnt <= 0;
|
||||
spdif_clk_en <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process CGEN;
|
||||
|
||||
SRD: process (up_clk)
|
||||
begin
|
||||
if rising_edge(up_clk) then
|
||||
if resetn = '0' or conf_txdata = '0' then
|
||||
bufctrl <= IDLE;
|
||||
sample_data_ack <= '0';
|
||||
channel <= '0';
|
||||
else
|
||||
case bufctrl is
|
||||
when IDLE =>
|
||||
sample_data_ack <= '0';
|
||||
if conf_txdata = '1' then
|
||||
bufctrl <= READ_CHA;
|
||||
sample_data_ack <='1';
|
||||
end if;
|
||||
when READ_CHA =>
|
||||
channel <= '0';
|
||||
sample_data_ack <= '0';
|
||||
bufctrl <= CHA_RDY;
|
||||
when CHA_RDY =>
|
||||
if cha_samp_ack = '1' then
|
||||
sample_data_ack <= '1';
|
||||
bufctrl <= READ_CHB;
|
||||
end if;
|
||||
when READ_CHB =>
|
||||
channel <= '1';
|
||||
sample_data_ack <= '0';
|
||||
bufctrl <= CHB_RDY;
|
||||
when CHB_RDY =>
|
||||
if chb_samp_ack = '1' then
|
||||
sample_data_ack <= '1';
|
||||
bufctrl <= READ_CHA;
|
||||
end if;
|
||||
when others =>
|
||||
bufctrl <= IDLE;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process SRD;
|
||||
|
||||
TXSYNC: process (data_clk)
|
||||
begin
|
||||
if (rising_edge(data_clk)) then
|
||||
spdif_tx_o <= spdif_out;
|
||||
end if;
|
||||
end process TXSYNC;
|
||||
|
||||
-- State machine that generates sub-frames and blocks
|
||||
|
||||
FRST: process (up_clk)
|
||||
begin
|
||||
if rising_edge(up_clk) then
|
||||
if resetn = '0' or conf_txen = '0' then
|
||||
framest <= IDLE;
|
||||
frame_cnt <= 0;
|
||||
bit_cnt <= 0;
|
||||
spdif_out <= '0';
|
||||
inv_preamble <= '0';
|
||||
toggle <= '0';
|
||||
valid <= '1';
|
||||
send_audio <= '0';
|
||||
cha_samp_ack <= '0';
|
||||
chb_samp_ack <= '0';
|
||||
else
|
||||
if spdif_clk_en = '1' then -- SPDIF clock is twice the bit rate
|
||||
case framest is
|
||||
when IDLE =>
|
||||
bit_cnt <= 0;
|
||||
frame_cnt <= 0;
|
||||
inv_preamble <= '0';
|
||||
toggle <= '0';
|
||||
framest <= BLOCK_START;
|
||||
when BLOCK_START => -- Start of channels status block/Ch. A
|
||||
chb_samp_ack <= '0';
|
||||
toggle <= not toggle; -- Each bit uses two clock enables,
|
||||
if toggle = '1' then -- counted by the toggle bit.
|
||||
if bit_cnt < 31 then
|
||||
bit_cnt <= bit_cnt + 1;
|
||||
else
|
||||
bit_cnt <= 0;
|
||||
if send_audio = '1' then
|
||||
cha_samp_ack <= '1';
|
||||
end if;
|
||||
framest <= CHANNEL_B;
|
||||
end if;
|
||||
end if;
|
||||
-- Block start uses preamble Z.
|
||||
if bit_cnt < 4 then
|
||||
if toggle = '0' then
|
||||
spdif_out <= Z_PREAMBLE(2 * bit_cnt) xor inv_preamble;
|
||||
else
|
||||
spdif_out <= Z_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
|
||||
end if;
|
||||
par_cnt <= 0;
|
||||
elsif bit_cnt > 3 and bit_cnt <= 31 then
|
||||
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
|
||||
par_cnt, active_user_data,
|
||||
active_ch_status,
|
||||
audio, toggle, spdif_out);
|
||||
if bit_cnt = 31 then
|
||||
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
|
||||
par_cnt, active_user_data,
|
||||
active_ch_status,
|
||||
audio, toggle, spdif_out);
|
||||
end if;
|
||||
if toggle = '0' then
|
||||
if bit_cnt > 3 and bit_cnt < 31 and
|
||||
par_vector(bit_cnt - 4) = '1' then
|
||||
par_cnt <= par_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
when CHANNEL_A => -- Sub-frame: channel A.
|
||||
chb_samp_ack <= '0';
|
||||
toggle <= not toggle;
|
||||
if toggle = '1' then
|
||||
if bit_cnt < 31 then
|
||||
bit_cnt <= bit_cnt + 1;
|
||||
else
|
||||
bit_cnt <= 0;
|
||||
if spdif_out = '1' then
|
||||
inv_preamble <= '1';
|
||||
else
|
||||
inv_preamble <= '0';
|
||||
end if;
|
||||
if send_audio = '1' then
|
||||
cha_samp_ack <= '1';
|
||||
end if;
|
||||
framest <= CHANNEL_B;
|
||||
end if;
|
||||
end if;
|
||||
-- Channel A uses preable X.
|
||||
if bit_cnt < 4 then
|
||||
if toggle = '0' then
|
||||
spdif_out <= X_PREAMBLE(2 * bit_cnt) xor inv_preamble;
|
||||
else
|
||||
spdif_out <= X_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
|
||||
end if;
|
||||
par_cnt <= 0;
|
||||
elsif bit_cnt > 3 and bit_cnt <= 31 then
|
||||
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
|
||||
par_cnt, active_user_data,
|
||||
active_ch_status,
|
||||
audio, toggle, spdif_out);
|
||||
if bit_cnt = 31 then
|
||||
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
|
||||
par_cnt, active_user_data,
|
||||
active_ch_status,
|
||||
audio, toggle, spdif_out);
|
||||
end if;
|
||||
if toggle = '0' then
|
||||
if bit_cnt > 3 and bit_cnt < 31 and
|
||||
par_vector(bit_cnt - 4) = '1' then
|
||||
par_cnt <= par_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
when CHANNEL_B => -- Sub-frame: channel B.
|
||||
cha_samp_ack <= '0';
|
||||
toggle <= not toggle;
|
||||
if toggle = '1' then
|
||||
if bit_cnt < 31 then
|
||||
bit_cnt <= bit_cnt + 1;
|
||||
else
|
||||
bit_cnt <= 0;
|
||||
valid <= not conf_txdata;
|
||||
if spdif_out = '1' then
|
||||
inv_preamble <= '1';
|
||||
else
|
||||
inv_preamble <= '0';
|
||||
end if;
|
||||
send_audio <= conf_txdata; -- 1 if audio samples sohuld be sent
|
||||
if send_audio = '1' then
|
||||
chb_samp_ack <= '1';
|
||||
end if;
|
||||
if frame_cnt < 191 then -- One block is 192 frames
|
||||
frame_cnt <= frame_cnt + 1;
|
||||
framest <= CHANNEL_A;
|
||||
else
|
||||
frame_cnt <= 0;
|
||||
framest <= BLOCK_START;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
-- Channel B uses preable Y.
|
||||
if bit_cnt < 4 then
|
||||
if toggle = '0' then
|
||||
spdif_out <= Y_PREAMBLE(2 * bit_cnt) xor inv_preamble;
|
||||
else
|
||||
spdif_out <= Y_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
|
||||
end if;
|
||||
par_cnt <= 0;
|
||||
elsif bit_cnt > 3 and bit_cnt <= 31 then
|
||||
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
|
||||
par_cnt, active_user_data,
|
||||
active_ch_status,
|
||||
audio, toggle, spdif_out);
|
||||
if bit_cnt = 31 then
|
||||
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
|
||||
par_cnt, active_user_data,
|
||||
active_ch_status,
|
||||
audio, toggle, spdif_out);
|
||||
end if;
|
||||
if toggle = '0' then
|
||||
if bit_cnt > 3 and bit_cnt < 31 and
|
||||
par_vector(bit_cnt - 4) = '1' then
|
||||
par_cnt <= par_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
when others =>
|
||||
framest <= IDLE;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process FRST;
|
||||
|
||||
-- Audio data latching
|
||||
DA32: if DATA_WIDTH = 32 generate
|
||||
ALAT: process (up_clk)
|
||||
begin
|
||||
if rising_edge(up_clk) then
|
||||
if send_audio = '0' then
|
||||
audio(23 downto 0) <= (others => '0');
|
||||
else
|
||||
case to_integer(unsigned(conf_mode)) is
|
||||
when 0 => -- 16 bit audio
|
||||
audio(23 downto 8) <= sample_data(15 downto 0);
|
||||
audio(7 downto 0) <= (others => '0');
|
||||
when 1 => -- 17 bit audio
|
||||
audio(23 downto 7) <= sample_data(16 downto 0);
|
||||
audio(6 downto 0) <= (others => '0');
|
||||
when 2 => -- 18 bit audio
|
||||
audio(23 downto 6) <= sample_data(17 downto 0);
|
||||
audio(5 downto 0) <= (others => '0');
|
||||
when 3 => -- 19 bit audio
|
||||
audio(23 downto 5) <= sample_data(18 downto 0);
|
||||
audio(4 downto 0) <= (others => '0');
|
||||
when 4 => -- 20 bit audio
|
||||
audio(23 downto 4) <= sample_data(19 downto 0);
|
||||
audio(3 downto 0) <= (others => '0');
|
||||
when 5 => -- 21 bit audio
|
||||
audio(23 downto 3) <= sample_data(20 downto 0);
|
||||
audio(2 downto 0) <= (others => '0');
|
||||
when 6 => -- 22 bit audio
|
||||
audio(23 downto 2) <= sample_data(21 downto 0);
|
||||
audio(1 downto 0) <= (others => '0');
|
||||
when 7 => -- 23 bit audio
|
||||
audio(23 downto 1) <= sample_data(22 downto 0);
|
||||
audio(0) <= '0';
|
||||
when 8 => -- 24 bit audio
|
||||
audio(23 downto 0) <= sample_data(23 downto 0);
|
||||
when others => -- unsupported modes
|
||||
audio(23 downto 0) <= (others => '0');
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process ALAT;
|
||||
end generate DA32;
|
||||
|
||||
DA16: if DATA_WIDTH = 16 generate
|
||||
ALAT: process (up_clk)
|
||||
begin
|
||||
if rising_edge(up_clk) then
|
||||
if send_audio = '0' then
|
||||
audio(23 downto 0) <= (others => '0');
|
||||
else
|
||||
audio(23 downto 8) <= sample_data(15 downto 0);
|
||||
audio(7 downto 0) <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process ALAT;
|
||||
end generate DA16;
|
||||
|
||||
-- Parity vector. These bits are counted to generate even parity
|
||||
par_vector(23 downto 0) <= audio(23 downto 0);
|
||||
par_vector(24) <= valid;
|
||||
par_vector(25) <= active_user_data(frame_cnt);
|
||||
par_vector(26) <= active_ch_status(frame_cnt);
|
||||
|
||||
-- Channel status and user datat to be used if buffers are disabled.
|
||||
-- User data is then all zero, while channel status bits are taken from
|
||||
-- register TxChStat.
|
||||
def_user_data(191 downto 0) <= (others => '0');
|
||||
def_ch_status(0) <= '0'; -- consumer mode
|
||||
def_ch_status(1) <= chstat_audio; -- audio bit
|
||||
def_ch_status(2) <= chstat_copy; -- copy right
|
||||
def_ch_status(5 downto 3) <= "000" when chstat_preem = '0'
|
||||
else "001"; -- pre-emphasis
|
||||
def_ch_status(7 downto 6) <= "00";
|
||||
def_ch_status(14 downto 8) <= (others => '0');
|
||||
def_ch_status(15) <= chstat_gstat; -- generation status
|
||||
def_ch_status(23 downto 16) <= (others => '0');
|
||||
def_ch_status(27 downto 24) <= "0000" when chstat_freq = "00" else
|
||||
"0010" when chstat_freq = "01" else
|
||||
"0011" when chstat_freq = "10" else
|
||||
"0001";
|
||||
def_ch_status(191 downto 28) <= (others => '0'); --191 28
|
||||
|
||||
-- Generate channel status vector based on configuration register setting.
|
||||
active_ch_status <= def_ch_status;
|
||||
|
||||
-- Generate user data vector based on configuration register setting.
|
||||
active_user_data <= def_user_data;
|
||||
|
||||
end rtl;
|
||||
@@ -0,0 +1,88 @@
|
||||
----------------------------------------------------------------------
|
||||
---- ----
|
||||
---- WISHBONE SPDIF IP Core ----
|
||||
---- ----
|
||||
---- This file is part of the SPDIF project ----
|
||||
---- http://www.opencores.org/cores/spdif_interface/ ----
|
||||
---- ----
|
||||
---- Description ----
|
||||
---- SPDIF transmitter component package. ----
|
||||
---- ----
|
||||
---- ----
|
||||
---- To Do: ----
|
||||
---- - ----
|
||||
---- ----
|
||||
---- Author(s): ----
|
||||
---- - Geir Drange, [email protected] ----
|
||||
---- ----
|
||||
----------------------------------------------------------------------
|
||||
---- ----
|
||||
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
|
||||
---- ----
|
||||
---- This source file may be used and distributed without ----
|
||||
---- restriction provided that this copyright statement is not ----
|
||||
---- removed from the file and that any derivative work contains ----
|
||||
---- the original copyright notice and the associated disclaimer. ----
|
||||
---- ----
|
||||
---- This source file is free software; you can redistribute it ----
|
||||
---- and/or modify it under the terms of the GNU Lesser General ----
|
||||
---- Public License as published by the Free Software Foundation; ----
|
||||
---- either version 2.1 of the License, or (at your option) any ----
|
||||
---- later version. ----
|
||||
---- ----
|
||||
---- This source is distributed in the hope that it will be ----
|
||||
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
||||
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
||||
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
||||
---- details. ----
|
||||
---- ----
|
||||
---- You should have received a copy of the GNU Lesser General ----
|
||||
---- Public License along with this source; if not, download it ----
|
||||
---- from http://www.opencores.org/lgpl.shtml ----
|
||||
---- ----
|
||||
----------------------------------------------------------------------
|
||||
--
|
||||
-- CVS Revision History
|
||||
--
|
||||
-- $Log: not supported by cvs2svn $
|
||||
-- Revision 1.2 2004/07/14 17:58:49 gedra
|
||||
-- Added new components.
|
||||
--
|
||||
-- Revision 1.1 2004/07/13 18:30:25 gedra
|
||||
-- Transmitter component declarations.
|
||||
--
|
||||
--
|
||||
--
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
package tx_package is
|
||||
|
||||
component tx_encoder
|
||||
generic
|
||||
(
|
||||
DATA_WIDTH: integer range 16 to 32 := 32
|
||||
);
|
||||
port
|
||||
(
|
||||
up_clk: in std_logic; -- clock
|
||||
data_clk : in std_logic; -- data clock
|
||||
resetn : in std_logic; -- resetn
|
||||
conf_mode: in std_logic_vector(3 downto 0); -- sample format
|
||||
conf_ratio: in std_logic_vector(7 downto 0); -- clock divider
|
||||
conf_txdata: in std_logic; -- sample data enable
|
||||
conf_txen: in std_logic; -- spdif signal enable
|
||||
chstat_freq: in std_logic_vector(1 downto 0); -- sample freq.
|
||||
chstat_gstat: in std_logic; -- generation status
|
||||
chstat_preem: in std_logic; -- preemphasis status
|
||||
chstat_copy: in std_logic; -- copyright bit
|
||||
chstat_audio: in std_logic; -- data format
|
||||
sample_data: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
|
||||
sample_data_ack : out std_logic; -- sample buffer read
|
||||
channel: out std_logic;
|
||||
spdif_tx_o: out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
end tx_package;
|
||||
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Wed Dec 8 10:23:17 2021
|
||||
# Process ID: 66771
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx
|
||||
# Command line: vivado -mode batch -source axi_spdif_tx_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source axi_spdif_tx_ip.tcl
|
||||
@@ -0,0 +1,766 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Wed Dec 8 10:23:17 2021
|
||||
# Process ID: 66771
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx
|
||||
# Command line: vivado -mode batch -source axi_spdif_tx_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source axi_spdif_tx_ip.tcl
|
||||
# source ../scripts/adi_env.tcl
|
||||
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
|
||||
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
|
||||
## if [info exists ::env(ADI_HDL_DIR)] {
|
||||
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
|
||||
## }
|
||||
## if [info exists ::env(ADI_GHDL_DIR)] {
|
||||
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
|
||||
## }
|
||||
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
|
||||
### variable auto_set_param_list
|
||||
### variable auto_set_param_list_overwritable
|
||||
### variable fpga_series_list
|
||||
### variable fpga_family_list
|
||||
### variable speed_grade_list
|
||||
### variable dev_package_list
|
||||
### variable xcvr_type_list
|
||||
### variable fpga_voltage_list
|
||||
### set auto_set_param_list { \
|
||||
### DEV_PACKAGE \
|
||||
### SPEED_GRADE \
|
||||
### FPGA_FAMILY \
|
||||
### FPGA_TECHNOLOGY }
|
||||
### set auto_set_param_list_overwritable { \
|
||||
### FPGA_VOLTAGE \
|
||||
### XCVR_TYPE }
|
||||
### set fpga_technology_list { \
|
||||
### { Unknown 0 } \
|
||||
### { 7series 1 } \
|
||||
### { ultrascale 2 } \
|
||||
### { ultrascale+ 3 }}
|
||||
### set fpga_family_list { \
|
||||
### { Unknown 0 } \
|
||||
### { artix 1 } \
|
||||
### { kintex 2 } \
|
||||
### { virtex 3 } \
|
||||
### { zynq 4 }}
|
||||
### set speed_grade_list { \
|
||||
### { Unknown 0 } \
|
||||
### { -1 10 } \
|
||||
### { -1L 11 } \
|
||||
### { -1H 12 } \
|
||||
### { -1HV 13 } \
|
||||
### { -1LV 14 } \
|
||||
### { -2 20 } \
|
||||
### { -2L 21 } \
|
||||
### { -2LV 22 } \
|
||||
### { -3 30 }}
|
||||
### set dev_package_list { \
|
||||
### { Unknown 0 } \
|
||||
### { rf 1 } \
|
||||
### { fl 2 } \
|
||||
### { ff 3 } \
|
||||
### { fb 4 } \
|
||||
### { hc 5 } \
|
||||
### { fh 6 } \
|
||||
### { cs 7 } \
|
||||
### { cp 8 } \
|
||||
### { ft 9 } \
|
||||
### { fg 10 } \
|
||||
### { sb 11 } \
|
||||
### { rb 12 } \
|
||||
### { rs 13 } \
|
||||
### { cl 14 } \
|
||||
### { sf 15 } \
|
||||
### { ba 16 } \
|
||||
### { fa 17 } \
|
||||
### { fs 18 } \
|
||||
### { fi 19 }}
|
||||
### set xcvr_type_list { \
|
||||
### { Unknown 0 } \
|
||||
### { GTPE2_NOT_SUPPORTED 1 } \
|
||||
### { GTXE2 2 } \
|
||||
### { GTHE2_NOT_SUPPORTED 3 } \
|
||||
### { GTZE2_NOT_SUPPORTED 4 } \
|
||||
### { GTHE3 5 } \
|
||||
### { GTYE3_NOT_SUPPORTED 6 } \
|
||||
### { GTRE4_NOT_SUPPORTED 7 } \
|
||||
### { GTHE4 8 } \
|
||||
### { GTYE4 9 } \
|
||||
### { GTME4_NOT_SUPPORTED 10}}
|
||||
### set fpga_voltage_list {0 5000} ;
|
||||
### proc adi_device_spec {cellpath param} {
|
||||
###
|
||||
### set list_pointer [string tolower $param]
|
||||
### set list_pointer [append list_pointer "_list"]
|
||||
###
|
||||
### upvar 1 $list_pointer $list_pointer
|
||||
###
|
||||
### set ip [get_bd_cells $cellpath]
|
||||
### set part [get_property PART [current_project]]
|
||||
###
|
||||
### switch -regexp -- $param {
|
||||
### FPGA_TECHNOLOGY {
|
||||
### switch -regexp -- $part {
|
||||
### ^xc7 {set series_name 7series}
|
||||
### ^xczu {set series_name ultrascale+}
|
||||
### ^xc.u.p {set series_name ultrascale+}
|
||||
### ^xc.u {set series_name ultrascale }
|
||||
### default {
|
||||
### puts "Undefined fpga technology for \"$part\"!"
|
||||
### exit -1
|
||||
### }
|
||||
### }
|
||||
### return "$series_name"
|
||||
### }
|
||||
### FPGA_FAMILY {
|
||||
### set fpga_family [get_property FAMILY $part]
|
||||
### foreach i $fpga_family_list {
|
||||
### regexp ^[lindex $i 0] $fpga_family matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### SPEED_GRADE {
|
||||
### set speed_grade [get_property SPEED $part]
|
||||
### return "$speed_grade"
|
||||
### }
|
||||
### DEV_PACKAGE {
|
||||
### set dev_package [get_property PACKAGE $part]
|
||||
### foreach i $dev_package_list {
|
||||
### regexp ^[lindex $i 0] $dev_package matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### XCVR_TYPE {
|
||||
### set matched ""
|
||||
### set dev_transcivers "none"
|
||||
### foreach x [list_property $part] {
|
||||
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
|
||||
### }
|
||||
### foreach i $xcvr_type_list {
|
||||
### regexp ^[lindex $i 0] $dev_transcivers matched
|
||||
### }
|
||||
### if { $matched eq "" } {
|
||||
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### FPGA_VOLTAGE {
|
||||
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
|
||||
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
|
||||
###
|
||||
### return "$fpga_voltage"
|
||||
### }
|
||||
### default {
|
||||
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
|
||||
### }
|
||||
### }
|
||||
### }
|
||||
## if {![info exists REQUIRED_VIVADO_VERSION]} {
|
||||
## set REQUIRED_VIVADO_VERSION "2019.1"
|
||||
## }
|
||||
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
|
||||
## set IGNORE_VERSION_CHECK 1
|
||||
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
|
||||
## set IGNORE_VERSION_CHECK 0
|
||||
## }
|
||||
## proc adi_ip_ttcl {ip_name ip_constr_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
|
||||
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_sim_ttcl {ip_name ip_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
|
||||
## set f [ipx::add_file $ip_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_bd {ip_name ip_bd_files} {
|
||||
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
|
||||
## if {$proj_filegroup == {}} {
|
||||
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
|
||||
## }
|
||||
##
|
||||
## foreach file $ip_bd_files {
|
||||
## set f [ipx::add_file $file $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type tclSource \
|
||||
## ] $f
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_infer_streaming_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_ip_infer_mm_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
|
||||
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency $port
|
||||
## if {$driver_value != {}} {
|
||||
## set_property DRIVER_VALUE $driver_value $port
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_set_bus_dependency {bus prefix dependency} {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
|
||||
## adi_set_ports_dependency $prefix $dependency 0
|
||||
## }
|
||||
## proc adi_add_port_map {bus phys logic} {
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## }
|
||||
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## adi_add_port_map $bus {*}$port_map
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
|
||||
## for {set i 0} {$i < $num} {incr i} {
|
||||
## set bus_name [format "%s%d" $bus_name_prefix $i]
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## if {$dependency ne ""} {
|
||||
## set bus_dependency [string map [list "{i}" $i] $dependency]
|
||||
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
|
||||
## }
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## lassign $port_map phys logic width width_dep
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
|
||||
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
|
||||
## if {$width_dep ne ""} {
|
||||
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
|
||||
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
|
||||
## set width_dep_r "(($width_dep) * $i)"
|
||||
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
|
||||
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
|
||||
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
|
||||
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
|
||||
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
|
||||
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
|
||||
## set_property display_name $clock_inf_name $clock_inf
|
||||
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
|
||||
## set_property physical_name $clock_signal_name $clock_map
|
||||
##
|
||||
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
|
||||
## set_property value $bus_inf_name $assoc_busif
|
||||
##
|
||||
## if { $reset_signal_name != "" } {
|
||||
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
|
||||
## set_property value $reset_signal_name $assoc_reset
|
||||
##
|
||||
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
|
||||
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
|
||||
## set_property display_name $reset_inf_name $reset_inf
|
||||
## set_property interface_mode $reset_signal_mode $reset_inf
|
||||
## set reset_map [ipx::add_port_map "RST" $reset_inf]
|
||||
## set_property physical_name $reset_signal_name $reset_map
|
||||
##
|
||||
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
|
||||
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
|
||||
## set_property value "ACTIVE_LOW" $reset_polarity
|
||||
## } else {
|
||||
## set_property value "ACTIVE_HIGH" $reset_polarity
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_add_core_dependencies {vlnvs} {
|
||||
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
|
||||
## foreach vlnv $vlnvs {
|
||||
## ipx::add_subcore $vlnv $file_group
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_create {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
## global ad_ghdl_dir
|
||||
## global REQUIRED_VIVADO_VERSION
|
||||
## global IGNORE_VERSION_CHECK
|
||||
##
|
||||
## set VIVADO_VERSION [version -short]
|
||||
## if {$IGNORE_VERSION_CHECK} {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## }
|
||||
## } else {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "ERROR: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
|
||||
## exit 2
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## create_project $ip_name . -force
|
||||
##
|
||||
## ## Load custom message severity definitions
|
||||
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
|
||||
##
|
||||
## set lib_dirs $ad_hdl_dir/library
|
||||
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
|
||||
## lappend lib_dirs $ad_ghdl_dir/library
|
||||
## }
|
||||
##
|
||||
## set_property ip_repo_paths $lib_dirs [current_fileset]
|
||||
## update_ip_catalog
|
||||
## }
|
||||
## proc adi_ip_files {ip_name ip_files} {
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## foreach m_file $ip_files {
|
||||
## if {[file extension $m_file] eq ".xdc"} {
|
||||
## add_files -norecurse -fileset constrs_1 $m_file
|
||||
## } else {
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
|
||||
## }
|
||||
## }
|
||||
## set_property "top" "$ip_name" $proj_fileset
|
||||
## }
|
||||
## proc adi_ip_properties_lite {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
##
|
||||
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
|
||||
##
|
||||
## set_property name $ip_name [ipx::current_core]
|
||||
##
|
||||
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
|
||||
## set_property company_url {http://www.analog.com} [ipx::current_core]
|
||||
##
|
||||
## set i_families ""
|
||||
## foreach i_part [get_parts] {
|
||||
## lappend i_families [get_property FAMILY $i_part]
|
||||
## }
|
||||
## set i_families [lsort -unique $i_families]
|
||||
## set s_families [get_property supported_families [ipx::current_core]]
|
||||
## foreach i_family $i_families {
|
||||
## set s_families "$s_families $i_family Production"
|
||||
## set s_families "$s_families $i_family Beta"
|
||||
## }
|
||||
## set_property supported_families $s_families [ipx::current_core]
|
||||
##
|
||||
## ipx::save_core [ipx::current_core]
|
||||
##
|
||||
## ipx::remove_all_bus_interface [ipx::current_core]
|
||||
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
|
||||
## foreach map $memory_maps {
|
||||
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
|
||||
## }
|
||||
##
|
||||
## ipx::update_checksums [ipx::current_core]
|
||||
## ipx::save_core [ipx::current_core]
|
||||
## }
|
||||
## proc adi_ip_properties {ip_name} {
|
||||
##
|
||||
## adi_ip_properties_lite $ip_name
|
||||
##
|
||||
## ipx::infer_bus_interface {\
|
||||
## s_axi_awvalid \
|
||||
## s_axi_awaddr \
|
||||
## s_axi_awprot \
|
||||
## s_axi_awready \
|
||||
## s_axi_wvalid \
|
||||
## s_axi_wdata \
|
||||
## s_axi_wstrb \
|
||||
## s_axi_wready \
|
||||
## s_axi_bvalid \
|
||||
## s_axi_bresp \
|
||||
##
|
||||
## s_axi_bready \
|
||||
## s_axi_arvalid \
|
||||
## s_axi_araddr \
|
||||
## s_axi_arprot \
|
||||
## s_axi_arready \
|
||||
## s_axi_rvalid \
|
||||
## s_axi_rdata \
|
||||
## s_axi_rresp \
|
||||
## s_axi_rready} \
|
||||
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
|
||||
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
|
||||
##
|
||||
## if {$raddr_width != $waddr_width} {
|
||||
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
|
||||
## set range 65536
|
||||
## } else {
|
||||
## if {$raddr_width >= 16} {
|
||||
## set range 65536
|
||||
## } else {
|
||||
## set range [expr 1 << $raddr_width]
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
## set_property range $range [ipx::get_address_blocks axi_lite \
|
||||
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
|
||||
## ipx::save_core
|
||||
## }
|
||||
## proc adi_init_bd_tcl {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## if { [file exists bd] } {
|
||||
## file delete -force bd
|
||||
## }
|
||||
## file mkdir bd
|
||||
##
|
||||
## set bd_tcl [open "bd/bd.tcl" w]
|
||||
##
|
||||
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
|
||||
## puts $bd_tcl "proc init {cellpath otherInfo} {"
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl ""
|
||||
## set auto_set_param ""
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
|
||||
## puts $bd_tcl $auto_set_param
|
||||
## }
|
||||
##
|
||||
## set auto_set_overwritable_param ""
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_overwritable_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_overwritable_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
|
||||
## puts $bd_tcl $auto_set_overwritable_param
|
||||
## }
|
||||
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
|
||||
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
|
||||
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set parent_dir \"../\""
|
||||
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
|
||||
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
|
||||
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " break"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " append parent_dir \"../\""
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## close $bd_tcl
|
||||
##
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
|
||||
##
|
||||
## set local_mk [open "temporary_case_dependencies.mk" w]
|
||||
## seek $local_mk 0 start
|
||||
## puts $local_mk "CLEAN_TARGET += bd"
|
||||
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
|
||||
## close $local_mk
|
||||
## }
|
||||
## proc adi_add_auto_fpga_spec_params {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_device_spec_param {ip_param} {
|
||||
##
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## set list_pointer [string tolower $ip_param]
|
||||
## set list_pointer [append list_pointer "_list"]
|
||||
##
|
||||
## global $list_pointer
|
||||
##
|
||||
## # set j 1D list from the original list
|
||||
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
|
||||
##
|
||||
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
|
||||
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "range_long" \
|
||||
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
|
||||
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## } else {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "pairs" \
|
||||
## "value_validation_pairs" $j ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## }
|
||||
##
|
||||
## # FPGA info grup
|
||||
## set info_group_name "FPGA info"
|
||||
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
|
||||
## if { [string trim $info_group] eq "" } {
|
||||
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
|
||||
## -parent $page0 -display_name $info_group_name]
|
||||
## }
|
||||
##
|
||||
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
|
||||
## set_property -dict [list "widget" "comboBox" ] $p
|
||||
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
|
||||
## }
|
||||
## proc adi_if_define {name} {
|
||||
##
|
||||
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
|
||||
## ipx::create_bus_definition analog.com interface $name 1.0
|
||||
##
|
||||
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
|
||||
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
|
||||
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
|
||||
##
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## }
|
||||
## proc adi_if_ports {dir width name {type none}} {
|
||||
##
|
||||
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
|
||||
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
|
||||
## set_property master_presence required $m_intf
|
||||
## set_property slave_presence required $m_intf
|
||||
## set_property master_width $width $m_intf
|
||||
## set_property slave_width $width $m_intf
|
||||
##
|
||||
## set m_dir "in"
|
||||
## set s_dir "out"
|
||||
## if {$dir eq "output"} {
|
||||
## set m_dir "out"
|
||||
## set s_dir "in"
|
||||
## }
|
||||
##
|
||||
## set_property master_direction $m_dir $m_intf
|
||||
## set_property slave_direction $s_dir $m_intf
|
||||
##
|
||||
## if {$type ne "none"} {
|
||||
## set_property is_${type} true $m_intf
|
||||
## }
|
||||
##
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## }
|
||||
## proc adi_if_infer_bus {if_name mode name maps} {
|
||||
##
|
||||
## ipx::add_bus_interface $name [ipx::current_core]
|
||||
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
|
||||
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
|
||||
## set_property interface_mode $mode $m_bus_if
|
||||
##
|
||||
## foreach map $maps {
|
||||
## set m_maps [regexp -all -inline {\S+} $map]
|
||||
## lassign $m_maps p_name p_map
|
||||
## ipx::add_port_map $p_name $m_bus_if
|
||||
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
|
||||
## }
|
||||
## }
|
||||
# adi_ip_create axi_spdif_tx
|
||||
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
|
||||
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1343} -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1306} -new_severity WARNING
|
||||
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
|
||||
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
|
||||
## set_msg_config -id {Synth 8-3331} -new_severity INFO
|
||||
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
|
||||
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
|
||||
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
|
||||
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'.)
|
||||
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
|
||||
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
|
||||
# adi_ip_files axi_spdif_tx [list \
|
||||
# "$ad_hdl_dir/library/common/axi_ctrlif.vhd" \
|
||||
# "$ad_hdl_dir/library/common/axi_streaming_dma_tx_fifo.vhd" \
|
||||
# "$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \
|
||||
# "$ad_hdl_dir/library/common/dma_fifo.vhd" \
|
||||
# "tx_package.vhd" \
|
||||
# "tx_encoder.vhd" \
|
||||
# "axi_spdif_tx.vhd" \
|
||||
# "axi_spdif_tx_constr.xdc" ]
|
||||
# adi_ip_properties axi_spdif_tx
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_ctrlif.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_tx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/pl330_dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_ctrlif.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/axi_streaming_dma_tx_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/pl330_dma_fifo.vhd' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_spdif_tx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'spdif_clk' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axis'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_rstn'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axis_aresetn'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'spdif_clk': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3157] Bus Interface 'dma_req_rstn': Bus parameter POLARITY is ACTIVE_LOW but port 'dma_req_rstn' is not *resetn - please double check the POLARITY setting.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'dma_req_aclk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
WARNING: [IP_Flow 19-3238] Range of address space is set to a full 4G (Address Block 'reg0' of Memory Map 's_axi'). Consider reducing this by setting the range of the address block to a lower number, or alternatively reduce the number of bits on the address line in your HDL's top level file interface.
|
||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
||||
# adi_ip_infer_streaming_interfaces axi_spdif_tx
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'spdif_data_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_req_rstn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axis'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dma_req_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_req_rstn'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axis_aresetn'.
|
||||
# adi_add_bus "dma_ack" "slave" \
|
||||
# "xilinx.com:interface:axis_rtl:1.0" \
|
||||
# "xilinx.com:interface:axis:1.0" \
|
||||
# [list {"dma_req_davalid" "TVALID"} \
|
||||
# {"dma_req_daready" "TREADY"} \
|
||||
# {"dma_req_datype" "TUSER"} ]
|
||||
# adi_add_bus "dma_req" "master" \
|
||||
# "xilinx.com:interface:axis_rtl:1.0" \
|
||||
# "xilinx.com:interface:axis:1.0" \
|
||||
# [list {"dma_req_drvalid" "TVALID"} \
|
||||
# {"dma_req_drready" "TREADY"} \
|
||||
# {"dma_req_drtype" "TUSER"} \
|
||||
# {"dma_req_drlast" "TLAST"} ]
|
||||
# adi_add_bus_clock "dma_req_aclk" "dma_req:dma_ack" "dma_req_rstn"
|
||||
# adi_set_bus_dependency "s_axis" "s_axis" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0)"
|
||||
# adi_set_bus_dependency "dma_ack" "dma_req_da" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
|
||||
# adi_set_bus_dependency "dma_req" "dma_req_dr" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
|
||||
# adi_set_ports_dependency "dma_req_aclk" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
|
||||
# adi_set_ports_dependency "dma_req_rstn" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
|
||||
# ipx::save_core [ipx::current_core]
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 10:23:28 2021...
|
||||
@@ -0,0 +1,70 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "DEVICE_FAMILY" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DMA_TYPE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "S_AXI_ADDRESS_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "S_AXI_DATA_WIDTH" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEVICE_FAMILY { PARAM_VALUE.DEVICE_FAMILY } {
|
||||
# Procedure called to update DEVICE_FAMILY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEVICE_FAMILY { PARAM_VALUE.DEVICE_FAMILY } {
|
||||
# Procedure called to validate DEVICE_FAMILY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DMA_TYPE { PARAM_VALUE.DMA_TYPE } {
|
||||
# Procedure called to update DMA_TYPE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DMA_TYPE { PARAM_VALUE.DMA_TYPE } {
|
||||
# Procedure called to validate DMA_TYPE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.S_AXI_ADDRESS_WIDTH { PARAM_VALUE.S_AXI_ADDRESS_WIDTH } {
|
||||
# Procedure called to update S_AXI_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.S_AXI_ADDRESS_WIDTH { PARAM_VALUE.S_AXI_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate S_AXI_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.S_AXI_DATA_WIDTH { PARAM_VALUE.S_AXI_DATA_WIDTH } {
|
||||
# Procedure called to update S_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.S_AXI_DATA_WIDTH { PARAM_VALUE.S_AXI_DATA_WIDTH } {
|
||||
# Procedure called to validate S_AXI_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.S_AXI_DATA_WIDTH { MODELPARAM_VALUE.S_AXI_DATA_WIDTH PARAM_VALUE.S_AXI_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.S_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.S_AXI_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.S_AXI_ADDRESS_WIDTH { MODELPARAM_VALUE.S_AXI_ADDRESS_WIDTH PARAM_VALUE.S_AXI_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.S_AXI_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.S_AXI_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEVICE_FAMILY { MODELPARAM_VALUE.DEVICE_FAMILY PARAM_VALUE.DEVICE_FAMILY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEVICE_FAMILY}] ${MODELPARAM_VALUE.DEVICE_FAMILY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DMA_TYPE { MODELPARAM_VALUE.DMA_TYPE PARAM_VALUE.DMA_TYPE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DMA_TYPE}] ${MODELPARAM_VALUE.DMA_TYPE}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user