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josh
2023-03-18 15:35:53 +08:00
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adi_library/axi_usb_fx3/Makefile
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_usb_fx3
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += axi_usb_fx3.v
GENERIC_DEPS += axi_usb_fx3_core.v
GENERIC_DEPS += axi_usb_fx3_if.v
GENERIC_DEPS += axi_usb_fx3_reg.v
XILINX_DEPS += axi_usb_fx3_ip.tcl
include ../scripts/library.mk
adi_library/axi_usb_fx3/axi_usb_fx3.cache/wt/project.wpc
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version:1
6d6f64655f636f756e7465727c42617463684d6f6465:1
eof:
adi_library/axi_usb_fx3/axi_usb_fx3.hw/axi_usb_fx3.lpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
adi_library/axi_usb_fx3/axi_usb_fx3.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_usb_fx3 (
// gpif ii
input dma_rdy,
input dma_wmk,
input [ 3:0] fifo_rdy,
output pclk,
inout [31:0] data,
output [ 1:0] addr,
output slcs_n,
output slrd_n,
output sloe_n,
output slwr_n,
output pktend_n,
output epswitch_n,
// irq
output irq,
// DEBUG
output [74:0] debug_fx32dma,
output [73:0] debug_dma2fx3,
output [14:0] debug_status,
// s2mm
input [31:0] s_axis_tdata,
input [ 3:0] s_axis_tkeep,
input s_axis_tlast,
input s_axis_tvalid,
output s_axis_tready,
// mm2s
input m_axis_tready,
output [31:0] m_axis_tdata,
output [ 3:0] m_axis_tkeep,
output m_axis_tlast,
output m_axis_tvalid,
// axi lite
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready);
// internal clocks & resets
wire up_rstn;
wire up_clk;
// internal signals
wire [13:0] up_raddr;
wire [31:0] up_rdata;
wire up_rack;
wire up_wack;
wire up_wreq;
wire [13:0] up_waddr;
wire [31:0] up_wdata;
wire up_rreq_s;
wire [ 7:0] fifo0_header_size;
wire [15:0] fifo0_buffer_size;
wire [ 7:0] fifo1_header_size;
wire [15:0] fifo1_buffer_size;
wire [ 7:0] fifo2_header_size;
wire [15:0] fifo2_buffer_size;
wire [ 7:0] fifo3_header_size;
wire [15:0] fifo3_buffer_size;
wire [ 7:0] fifo4_header_size;
wire [15:0] fifo4_buffer_size;
wire [ 7:0] fifo5_header_size;
wire [15:0] fifo5_buffer_size;
wire [ 7:0] fifo6_header_size;
wire [15:0] fifo6_buffer_size;
wire [ 7:0] fifo7_header_size;
wire [15:0] fifo7_buffer_size;
wire [ 7:0] fifo8_header_size;
wire [15:0] fifo8_buffer_size;
wire [ 7:0] fifo9_header_size;
wire [15:0] fifo9_buffer_size;
wire [ 7:0] fifoa_header_size;
wire [15:0] fifoa_buffer_size;
wire fifo0_direction;
wire fifo1_direction;
wire fifo2_direction;
wire fifo3_direction;
wire fifo4_direction;
wire fifo5_direction;
wire fifo6_direction;
wire fifo7_direction;
wire fifo8_direction;
wire fifo9_direction;
wire fifoa_direction;
wire [10:0] fifo_direction;
wire fx32dma_valid;
wire fx32dma_ready;
wire [31:0] fx32dma_data;
wire fx32dma_sop;
wire fx32dma_eop;
wire dma2fx3_ready;
wire dma2fx3_valid;
wire [31:0] dma2fx3_data;
wire dma2fx3_eop;
wire [ 2:0] test_mode_tpm;
wire [ 2:0] test_mode_tpg;
wire monitor_error;
wire eot_fx32dma;
wire eot_dma2fx3;
wire error;
wire [ 4:0] fifo_num;
wire [10:0] fifo_ready;
wire [31:0] length_fx32dma;
wire [31:0] length_dma2fx3;
wire trig;
wire zlp;
// signal name changes
assign up_clk = s_axi_aclk;
assign pclk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign fifo_direction = {fifo9_direction, fifo8_direction, fifo7_direction, fifo6_direction, fifo5_direction, fifo4_direction, fifo3_direction, fifo2_direction, fifo1_direction, fifo0_direction};
// DEBUG
assign debug_dma2fx3 = {s_axis_tdata, dma2fx3_data, s_axis_tkeep, s_axis_tlast, s_axis_tvalid, s_axis_tready, dma2fx3_ready, dma2fx3_valid, dma2fx3_eop};
assign debug_fx32dma = {fx32dma_eop, m_axis_tdata, fx32dma_data, m_axis_tkeep, m_axis_tlast, m_axis_tvalid, m_axis_tready, fx32dma_ready, fx32dma_valid, fx32dma_sop};
assign debug_status = {irq, error, monitor_error, test_mode_tpg, test_mode_tpm, trig, fifo_num};
// packetizer, TPM/TPG and DMA interface
axi_usb_fx3_core ep_packetizer(
.clk(pclk),
.reset(!up_rstn),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tlast(s_axis_tlast),
.s_axis_tready(s_axis_tready),
.s_axis_tvalid(s_axis_tvalid),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tlast(m_axis_tlast),
.m_axis_tready(m_axis_tready),
.m_axis_tvalid(m_axis_tvalid),
.fifo0_header_size(fifo0_header_size),
.fifo0_buffer_size(fifo0_buffer_size),
.fifo1_header_size(fifo1_header_size),
.fifo1_buffer_size(fifo1_buffer_size),
.fifo2_header_size(fifo2_header_size),
.fifo2_buffer_size(fifo2_buffer_size),
.fifo3_header_size(fifo3_header_size),
.fifo3_buffer_size(fifo3_buffer_size),
.fifo4_header_size(fifo4_header_size),
.fifo4_buffer_size(fifo4_buffer_size),
.fifo5_header_size(fifo5_header_size),
.fifo5_buffer_size(fifo5_buffer_size),
.fifo6_header_size(fifo6_header_size),
.fifo6_buffer_size(fifo6_buffer_size),
.fifo7_header_size(fifo7_header_size),
.fifo7_buffer_size(fifo7_buffer_size),
.fifo8_header_size(fifo8_header_size),
.fifo8_buffer_size(fifo8_buffer_size),
.fifo9_header_size(fifo9_header_size),
.fifo9_buffer_size(fifo9_buffer_size),
.fifoa_header_size(fifoa_header_size),
.fifoa_buffer_size(fifoa_buffer_size),
.fifob_header_size(0),
.fifob_buffer_size(0),
.fifoc_header_size(0),
.fifoc_buffer_size(0),
.fifod_header_size(0),
.fifod_buffer_size(0),
.fifoe_header_size(0),
.fifoe_buffer_size(0),
.fifof_header_size(0),
.fifof_buffer_size(0),
.length_fx32dma(length_fx32dma),
.length_dma2fx3(length_dma2fx3),
.fx32dma_valid(fx32dma_valid),
.fx32dma_ready(fx32dma_ready),
.fx32dma_data(fx32dma_data),
.fx32dma_sop(fx32dma_sop),
.fx32dma_eop(fx32dma_eop),
.dma2fx3_ready(dma2fx3_ready),
.dma2fx3_valid(dma2fx3_valid),
.dma2fx3_data(dma2fx3_data),
.dma2fx3_eop(dma2fx3_eop),
.error(error),
.eot_fx32dma(eot_fx32dma),
.eot_dma2fx3(eot_dma2fx3),
.test_mode_tpm(test_mode_tpm),
.test_mode_tpg(test_mode_tpg),
.monitor_error(monitor_error),
.zlp(zlp),
.fifo_num(fifo_num));
// register map
axi_usb_fx3_reg fx3_registers(
.fifo_rdy(fifo_ready),
.eot_fx32dma(eot_fx32dma),
.eot_dma2fx3(eot_dma2fx3),
.trig(trig),
.zlp(zlp),
.fifo_num(fifo_num),
.error(error),
.test_mode_tpm(test_mode_tpm),
.test_mode_tpg(test_mode_tpg),
.monitor_error(monitor_error),
.irq(irq),
.fifo0_direction(fifo0_direction),
.fifo0_header_size(fifo0_header_size),
.fifo0_buffer_size(fifo0_buffer_size),
.fifo1_direction(fifo1_direction),
.fifo1_header_size(fifo1_header_size),
.fifo1_buffer_size(fifo1_buffer_size),
.fifo2_direction(fifo2_direction),
.fifo2_header_size(fifo2_header_size),
.fifo2_buffer_size(fifo2_buffer_size),
.fifo3_direction(fifo3_direction),
.fifo3_header_size(fifo3_header_size),
.fifo3_buffer_size(fifo3_buffer_size),
.fifo4_direction(fifo4_direction),
.fifo4_header_size(fifo4_header_size),
.fifo4_buffer_size(fifo4_buffer_size),
.fifo5_direction(fifo5_direction),
.fifo5_header_size(fifo5_header_size),
.fifo5_buffer_size(fifo5_buffer_size),
.fifo6_direction(fifo6_direction),
.fifo6_header_size(fifo6_header_size),
.fifo6_buffer_size(fifo6_buffer_size),
.fifo7_direction(fifo7_direction),
.fifo7_header_size(fifo7_header_size),
.fifo7_buffer_size(fifo7_buffer_size),
.fifo8_direction(fifo8_direction),
.fifo8_header_size(fifo8_header_size),
.fifo8_buffer_size(fifo8_buffer_size),
.fifo9_direction(fifo9_direction),
.fifo9_header_size(fifo9_header_size),
.fifo9_buffer_size(fifo9_buffer_size),
.fifoa_direction(fifoa_direction),
.fifoa_header_size(fifoa_header_size),
.fifoa_buffer_size(fifoa_buffer_size),
.length_fx32dma(length_fx32dma),
.length_dma2fx3(length_dma2fx3),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_wack(up_wack),
.up_rreq(up_rreq),
.up_raddr(up_raddr),
.up_rdata(up_rdata),
.up_rack(up_rack));
// GPIF II interface
axi_usb_fx3_if fx3_if(
.pclk(pclk), //output clk 100 Mhz and 180 phase shift
.reset_n(up_rstn),
.dma_rdy(dma_rdy),
.dma_wmk(dma_wmk),
.fifo_rdy(fifo_rdy),
.data(data),
.addr(addr), //output fifo address
.slcs_n(slcs_n), //output chip select
.slrd_n(slrd_n), //output read select
.sloe_n(sloe_n), //output output enable select
.slwr_n(slwr_n), //output write select
.pktend_n(pktend_n), //output pkt end
.epswitch_n(epswitch_n), //output pkt end
.fifo_ready(fifo_ready),
.fifo_num(fifo_num),
.fifo_direction(fifo_direction),
.trig(trig),
.fx32dma_valid(fx32dma_valid),
.fx32dma_ready(fx32dma_ready),
.fx32dma_data(fx32dma_data),
.fx32dma_sop(fx32dma_sop),
.fx32dma_eop(fx32dma_eop),
.eot_fx32dma(eot_fx32dma),
.dma2fx3_ready(dma2fx3_ready),
.dma2fx3_valid(dma2fx3_valid),
.dma2fx3_data(dma2fx3_data),
.dma2fx3_eop(dma2fx3_eop));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
adi_library/axi_usb_fx3/axi_usb_fx3.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="1"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
<MsgAttr Name="StringsToMatch" Val="features"/>
<MsgAttr Name="StringsToMatch" Val="should"/>
<MsgAttr Name="StringsToMatch" Val="NOT"/>
<MsgAttr Name="StringsToMatch" Val="be"/>
<MsgAttr Name="StringsToMatch" Val="used"/>
<MsgAttr Name="StringsToMatch" Val="in"/>
<MsgAttr Name="StringsToMatch" Val="production"/>
<MsgAttr Name="StringsToMatch" Val="systems."/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Place 30-73"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="10"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val=""/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="11"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1343"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="2"/>
<MsgAttr Name="Note" Val=""/>
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</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1306"/>
<MsgAttr Name="Severity" Val="ANY"/>
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</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="NewSeverity" Val="ERROR"/>
<MsgAttr Name="Id" Val="BD 41-1276"/>
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="4"/>
<MsgAttr Name="Note" Val=""/>
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<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="5"/>
<MsgAttr Name="Note" Val=""/>
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</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="6"/>
<MsgAttr Name="Note" Val=""/>
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<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="7"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Synth 8-3331"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
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<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
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<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
<BootPmcSettings Version="1" Minor="0">
<Parameters>
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
</Parameters>
</BootPmcSettings>
</Project>
adi_library/axi_usb_fx3/axi_usb_fx3_core.v
+601
View File
@@ -0,0 +1,601 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_usb_fx3_core (
input clk,
input reset,
// s2mm
input [31:0] s_axis_tdata,
input [ 3:0] s_axis_tkeep,
input s_axis_tlast,
output reg s_axis_tready,
input s_axis_tvalid,
// mm2s
output reg [31:0] m_axis_tdata,
output reg [ 3:0] m_axis_tkeep,
output reg m_axis_tlast,
input m_axis_tready,
output reg m_axis_tvalid,
// configuration
input [ 7:0] fifo0_header_size,
input [15:0] fifo0_buffer_size,
input [ 7:0] fifo1_header_size,
input [15:0] fifo1_buffer_size,
input [ 7:0] fifo2_header_size,
input [15:0] fifo2_buffer_size,
input [ 7:0] fifo3_header_size,
input [15:0] fifo3_buffer_size,
input [ 7:0] fifo4_header_size,
input [15:0] fifo4_buffer_size,
input [ 7:0] fifo5_header_size,
input [15:0] fifo5_buffer_size,
input [ 7:0] fifo6_header_size,
input [15:0] fifo6_buffer_size,
input [ 7:0] fifo7_header_size,
input [15:0] fifo7_buffer_size,
input [ 7:0] fifo8_header_size,
input [15:0] fifo8_buffer_size,
input [ 7:0] fifo9_header_size,
input [15:0] fifo9_buffer_size,
input [ 7:0] fifoa_header_size,
input [15:0] fifoa_buffer_size,
input [ 7:0] fifob_header_size,
input [15:0] fifob_buffer_size,
input [ 7:0] fifoc_header_size,
input [15:0] fifoc_buffer_size,
input [ 7:0] fifod_header_size,
input [15:0] fifod_buffer_size,
input [ 7:0] fifoe_header_size,
input [15:0] fifoe_buffer_size,
input [ 7:0] fifof_header_size,
input [15:0] fifof_buffer_size,
output reg [31:0] length_fx32dma,
output reg [31:0] length_dma2fx3,
// fx3 interface
// IN -> TO HOST / FX3
// OUT -> FROM HOST / FX3
input fx32dma_valid,
output fx32dma_ready,
input [31:0] fx32dma_data,
input fx32dma_sop,
output reg fx32dma_eop,
input dma2fx3_ready,
output reg dma2fx3_valid,
output reg [31:0] dma2fx3_data,
output reg dma2fx3_eop,
output error,
output reg eot_fx32dma,
output reg eot_dma2fx3,
input [ 2:0] test_mode_tpm,
input [ 2:0] test_mode_tpg,
output reg monitor_error,
input zlp,
input [ 4:0] fifo_num);
// internal parameters
localparam IDLE = 3'b001;
localparam READ_HEADER = 3'b010;
localparam ADD_FOOTER = 3'b010;
localparam READ_DATA = 3'b100;
// internal signals
wire test_mode_active_tpm;
wire test_mode_active_tpg;
// internal registers
reg [31:0] data_size_transaction = 32'hffffffff;
reg [15:0] buffer_size_current = 16'h0;
reg [ 7:0] header_size_current = 8'h0;
reg error_fx32dma = 1'b0;
reg error_dma2fx3 = 1'b0;
reg [ 2:0] state_fx32dma = 3'h0;
reg [ 2:0] next_state_fx32dma = 3'h0;
reg [ 2:0] state_dma2fx3 = 3'h0;
reg [ 2:0] next_state_dma2fx3 = 3'h0;
reg [ 7:0] header_pointer = 8'h0;
reg header_read = 1'b0;
reg [31:0] dma2fx3_counter = 32'h0;
reg [ 7:0] footer_pointer = 8'h0;
reg [31:0] dma2fx3_data_reg = 32'h0;
reg [31:0] expected_data = 32'h0;
reg first_transfer = 1'b0;
function [31:0] pn23;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[22] ^ din[17];
dout[30] = din[21] ^ din[16];
dout[29] = din[20] ^ din[15];
dout[28] = din[19] ^ din[14];
dout[27] = din[18] ^ din[13];
dout[26] = din[17] ^ din[12];
dout[25] = din[16] ^ din[11];
dout[24] = din[15] ^ din[10];
dout[23] = din[14] ^ din[ 9];
dout[22] = din[13] ^ din[ 8];
dout[21] = din[12] ^ din[ 7];
dout[20] = din[11] ^ din[ 6];
dout[19] = din[10] ^ din[ 5];
dout[18] = din[ 9] ^ din[ 4];
dout[17] = din[ 8] ^ din[ 3];
dout[16] = din[ 7] ^ din[ 2];
dout[15] = din[ 6] ^ din[ 1];
dout[14] = din[ 5] ^ din[ 0];
dout[13] = din[ 4] ^ din[22] ^ din[17];
dout[12] = din[ 3] ^ din[21] ^ din[16];
dout[11] = din[ 2] ^ din[20] ^ din[15];
dout[10] = din[ 1] ^ din[19] ^ din[14];
dout[ 9] = din[ 0] ^ din[18] ^ din[13];
dout[ 8] = din[22] ^ din[12];
dout[ 7] = din[21] ^ din[11];
dout[ 6] = din[20] ^ din[10];
dout[ 5] = din[19] ^ din[ 9];
dout[ 4] = din[18] ^ din[ 8];
dout[ 3] = din[17] ^ din[ 7];
dout[ 2] = din[16] ^ din[ 6];
dout[ 1] = din[15] ^ din[ 5];
dout[ 0] = din[14] ^ din[ 4];
pn23 = dout;
end
endfunction
function [31:0] pn9;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[ 8] ^ din[ 4];
dout[30] = din[ 7] ^ din[ 3];
dout[29] = din[ 6] ^ din[ 2];
dout[28] = din[ 5] ^ din[ 1];
dout[27] = din[ 4] ^ din[ 0];
dout[26] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[25] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[24] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[23] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[22] = din[ 8] ^ din[ 0];
dout[21] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[20] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[19] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[18] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[17] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[13] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0];
dout[ 1] = din[5] ^ din[7] ^ din[8] ^ din[4];
dout[ 0] = din[4] ^ din[6] ^ din[7] ^ din[3];
pn9 = dout;
end
endfunction
assign error = error_fx32dma | error_dma2fx3;
assign test_mode_active_tpm = |test_mode_tpm;
assign test_mode_active_tpg = |test_mode_tpg;
// fx32dma
assign fx32dma_ready = m_axis_tready;
always @(*) begin
case (fifo_num)
5'h0: buffer_size_current = fifo0_buffer_size;
5'h1: buffer_size_current = fifo1_buffer_size;
5'h2: buffer_size_current = fifo2_buffer_size;
5'h3: buffer_size_current = fifo3_buffer_size;
5'h4: buffer_size_current = fifo4_buffer_size;
5'h5: buffer_size_current = fifo5_buffer_size;
5'h6: buffer_size_current = fifo6_buffer_size;
5'h7: buffer_size_current = fifo7_buffer_size;
5'h8: buffer_size_current = fifo8_buffer_size;
5'h9: buffer_size_current = fifo9_buffer_size;
5'ha: buffer_size_current = fifoa_buffer_size;
5'hb: buffer_size_current = fifob_buffer_size;
5'hc: buffer_size_current = fifoc_buffer_size;
5'hd: buffer_size_current = fifod_buffer_size;
5'he: buffer_size_current = fifoe_buffer_size;
5'hf: buffer_size_current = fifof_buffer_size;
default: buffer_size_current = fifo0_buffer_size;
endcase
case (fifo_num)
5'h0: header_size_current = fifo0_header_size;
5'h1: header_size_current = fifo1_header_size;
5'h2: header_size_current = fifo2_header_size;
5'h3: header_size_current = fifo3_header_size;
5'h4: header_size_current = fifo4_header_size;
5'h5: header_size_current = fifo5_header_size;
5'h6: header_size_current = fifo6_header_size;
5'h7: header_size_current = fifo7_header_size;
5'h8: header_size_current = fifo8_header_size;
5'h9: header_size_current = fifo9_header_size;
5'ha: header_size_current = fifoa_header_size;
5'hb: header_size_current = fifob_header_size;
5'hc: header_size_current = fifoc_header_size;
5'hd: header_size_current = fifod_header_size;
5'he: header_size_current = fifoe_header_size;
5'hf: header_size_current = fifof_header_size;
default: header_size_current = fifo0_header_size;
endcase
end
// state machine
always @(posedge clk) begin
if (reset == 1'b1 || error_fx32dma == 1'b1) begin
state_fx32dma <= IDLE;
end else begin
state_fx32dma <= next_state_fx32dma;
end
end
always @(*) begin
case(state_fx32dma)
IDLE:
if(fx32dma_sop == 1'b1) begin
next_state_fx32dma = READ_HEADER;
end else begin
next_state_fx32dma = state_fx32dma;
end
READ_HEADER:
if(header_read == 1'b1) begin
next_state_fx32dma = READ_DATA;
end else begin
next_state_fx32dma = state_fx32dma;
end
READ_DATA:
if(data_size_transaction <= 4) begin
next_state_fx32dma = IDLE;
end else begin
next_state_fx32dma = state_fx32dma;
end
default: next_state_fx32dma = IDLE;
endcase
end
always @(*) begin
m_axis_tdata = fx32dma_data;
fx32dma_eop = 1'b0;
m_axis_tlast = 1'b0;
case(state_fx32dma)
IDLE: begin
m_axis_tvalid = 1'b0;
m_axis_tkeep = 4'h0;
eot_fx32dma = 1'b0;
end
READ_HEADER: begin
m_axis_tvalid = 1'b0;
m_axis_tkeep = 4'h0;
m_axis_tlast = 1'b0;
eot_fx32dma = 1'b0;
end
READ_DATA: begin
m_axis_tvalid = fx32dma_valid;
if (fx32dma_valid == 1'b1) begin
if (data_size_transaction > 12 ) begin
fx32dma_eop = 1'b0;
end else begin
fx32dma_eop = 1'b1;
end
if (data_size_transaction > 4) begin
m_axis_tlast = 1'b0;
m_axis_tkeep = 4'hf;
eot_fx32dma = 1'b0;
end else begin
m_axis_tlast = 1'b1;
eot_fx32dma = 1'b1;
m_axis_tlast = 1'b1;
case (data_size_transaction)
1: m_axis_tkeep = 4'h1;
2: m_axis_tkeep = 4'h3;
3: m_axis_tkeep = 4'h7;
default: m_axis_tkeep = 4'hf;
endcase
end
end else begin
m_axis_tkeep = 4'h0;
eot_fx32dma = 1'b0;
end
end
default: begin
m_axis_tvalid = 1'b0;
m_axis_tkeep = 4'h0;
m_axis_tlast = 1'b0;
eot_fx32dma = 1'b0;
end
endcase
end
always @(posedge clk) begin
header_read <= 1'b0;
if (state_fx32dma == IDLE) begin
if (fx32dma_sop == 1'b1) begin
header_pointer <= 8'h4;
if (fx32dma_data != 32'h0ff00ff0) begin
error_fx32dma <= 1'b1;
end else begin
error_fx32dma <= 1'b0;
end
end
case (test_mode_tpm)
4'h1: expected_data <= 32'haaaaaaaa;
default: expected_data <= 32'hffffffff;
endcase
end
if (state_fx32dma == READ_HEADER) begin
if (fx32dma_valid == 1'b1) begin
if (m_axis_tready == 1'b0) begin
error_fx32dma <= 1'b1;
end
if(header_pointer < header_size_current - 4) begin
header_pointer <= header_pointer + 8;
end else begin
header_read <= 1'b1;
end
if (header_pointer == 4) begin
data_size_transaction <= fx32dma_data;
length_fx32dma <= fx32dma_data;
if (fx32dma_data > buffer_size_current) begin
error_fx32dma <= 1'b1;
end
end
end
end
if (state_fx32dma == READ_DATA) begin
first_transfer <= 1'b1;
if (fx32dma_valid == 1'b1) begin
first_transfer <= 1'b0;
if (data_size_transaction > 4) begin
data_size_transaction <= data_size_transaction - 4;
end
end
// monitor
if (test_mode_active_tpm == 1'b1) begin
if (first_transfer == 1) begin
expected_data <= fx32dma_data;
end else begin
case (test_mode_tpm)
4'h1: expected_data <= ~expected_data;
4'h2: expected_data <= ~expected_data;
4'h3: expected_data <= pn9(expected_data);
4'h4: expected_data <= pn23(expected_data);
4'h7: expected_data <= expected_data + 1;
default: expected_data <= 0;
endcase
if (expected_data != m_axis_tdata) begin
monitor_error <= 1'b1;
end else begin
monitor_error <= 1'b0;
end
end
end
end
end
// dma2fx3
always @(posedge clk) begin
if (reset == 1'b1 || error_dma2fx3 == 1'b1) begin
state_dma2fx3 <= IDLE;
end else begin
state_dma2fx3 <= next_state_dma2fx3;
end
end
always @(*) begin
case(state_dma2fx3)
IDLE:
if(dma2fx3_ready == 1'b1) begin
if (zlp == 1'b1) begin
next_state_dma2fx3 = ADD_FOOTER;
end else begin
next_state_dma2fx3 = READ_DATA;
end
end else begin
next_state_dma2fx3 = IDLE;
end
READ_DATA:
if(s_axis_tlast == 1'b1 || dma2fx3_counter >= buffer_size_current - 4) begin
next_state_dma2fx3 = ADD_FOOTER;
end else begin
next_state_dma2fx3 = READ_DATA;
end
ADD_FOOTER:
if(dma2fx3_eop == 1'b1) begin
next_state_dma2fx3 = IDLE;
end else begin
next_state_dma2fx3 = ADD_FOOTER;
end
default: next_state_dma2fx3 = IDLE;
endcase
end
always @(*) begin
case(state_dma2fx3)
IDLE: begin
s_axis_tready = 1'b0;
dma2fx3_valid = 1'b0;
eot_dma2fx3 = 1'b0;
dma2fx3_eop = 1'b0;
dma2fx3_data = dma2fx3_data_reg;
end
READ_DATA: begin
eot_dma2fx3 = 1'b0;
if (test_mode_active_tpg == 1'b1) begin
s_axis_tready = 1'b0;
dma2fx3_valid = 1'b1;
end else begin
dma2fx3_valid = s_axis_tvalid & s_axis_tready;
s_axis_tready = dma2fx3_ready;
end
dma2fx3_eop = 1'b0;
if (test_mode_active_tpg == 1'b1) begin
dma2fx3_data = dma2fx3_data_reg;
end else begin
dma2fx3_data = s_axis_tdata;
end
end
ADD_FOOTER: begin
s_axis_tready = 1'b0;
dma2fx3_valid = 1'b1;
if (footer_pointer == header_size_current) begin
dma2fx3_eop = 1'b1;
eot_dma2fx3 = 1'b1;
end else begin
dma2fx3_eop = 1'b0;
eot_dma2fx3 = 1'b0;
end
dma2fx3_data = dma2fx3_data_reg;
end
default: begin
s_axis_tready = 1'b0;
dma2fx3_valid = 1'b0;
eot_dma2fx3 = 1'b0;
dma2fx3_eop = 1'b0;
dma2fx3_data = dma2fx3_data_reg;
end
endcase
end
always @(posedge clk) begin
if(state_dma2fx3 == IDLE) begin
footer_pointer <= 4;
dma2fx3_counter <= 0;
case (test_mode_tpg)
4'h1: dma2fx3_data_reg <= 32'haaaaaaaa;
default: dma2fx3_data_reg <= 32'hffffffff;
endcase
if (zlp == 1'b1) begin
dma2fx3_data_reg <= 32'h0ff00ff0;
end
end
if(state_dma2fx3 == READ_DATA) begin
if (test_mode_active_tpg == 1'b1) begin
if (dma2fx3_ready == 1'b1) begin
dma2fx3_counter <= dma2fx3_counter + 4;
if (dma2fx3_counter >= buffer_size_current - 4) begin
dma2fx3_data_reg <= 32'h0ff00ff0;
end else begin
case (test_mode_tpg)
4'h1: dma2fx3_data_reg <= ~dma2fx3_data_reg;
4'h2: dma2fx3_data_reg <= ~dma2fx3_data_reg;
4'h3: dma2fx3_data_reg <= pn9(dma2fx3_data_reg);
4'h4: dma2fx3_data_reg <= pn23(dma2fx3_data_reg);
4'h7: dma2fx3_data_reg <= dma2fx3_data_reg + 1;
default: dma2fx3_data_reg <= 0;
endcase
end
end
end else begin
dma2fx3_data_reg <= 32'h0ff00ff0;
if (s_axis_tvalid== 1'b1 && s_axis_tready == 1'b1) begin
case (s_axis_tkeep)
1: dma2fx3_counter <= dma2fx3_counter + 1;
3: dma2fx3_counter <= dma2fx3_counter + 2;
7: dma2fx3_counter <= dma2fx3_counter + 3;
default: dma2fx3_counter <= dma2fx3_counter + 4;
endcase
end
end
end
if(state_dma2fx3 == ADD_FOOTER) begin
footer_pointer <= footer_pointer + 4;
length_dma2fx3 <= dma2fx3_counter;
case(footer_pointer)
32'h4: dma2fx3_data_reg <= dma2fx3_counter;
32'h8: dma2fx3_data_reg <= 32'h0;
default: dma2fx3_data_reg <= 32'h0;
endcase
end
end
endmodule
adi_library/axi_usb_fx3/axi_usb_fx3_if.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_usb_fx3_if (
input dma_rdy,
input dma_wmk,
input [ 3:0] fifo_rdy,
input pclk,
input reset_n,
inout [31:0] data,
output reg [ 1:0] addr,
output reg slcs_n,
output reg slrd_n,
output reg sloe_n,
output reg slwr_n,
output reg pktend_n,
output epswitch_n,
input [ 4:0] fifo_num,
input [10:0] fifo_direction,
input trig,
output reg [10:0] fifo_ready,
output reg fx32dma_valid,
input fx32dma_ready,
output reg [31:0] fx32dma_data,
output reg fx32dma_sop,
input fx32dma_eop,
input eot_fx32dma,
output reg dma2fx3_ready,
input dma2fx3_valid,
input [31:0] dma2fx3_data,
input dma2fx3_eop);
// internal registers
reg [ 3:0] state_gpif_ii = 4'h0;
reg [ 3:0] next_state_gpif_ii = 4'h0;
reg current_direction = 0;
reg current_fifo = 0;
reg slcs_n_d1 = 0;
reg slcs_n_d2 = 0;
reg slcs_n_d3 = 0;
reg slcs_n_d4 = 0;
reg slrd_n_d1 = 0;
reg slrd_n_d2 = 0;
reg slrd_n_d3 = 0;
reg sloe_n_d1 = 0;
reg pip = 0;
localparam IDLE = 4'b0001;
localparam READ_START = 4'b0010;
localparam READ_DATA = 4'b0100;
localparam WRITE_DATA = 4'b1000;
assign data = (state_gpif_ii == WRITE_DATA && dma2fx3_valid && current_fifo) ? dma2fx3_data : 32'hz;
assign epswitch_n = 1'b1;
always @(fifo_num, fifo_rdy, fifo_direction) begin
case(fifo_num)
5'h0: begin
current_direction = fifo_direction[0];
current_fifo = fifo_rdy[0];
end
5'h1: begin
current_direction = fifo_direction[1];
current_fifo = fifo_rdy[1];
end
5'h2: begin
current_direction = fifo_direction[2];
current_fifo = fifo_rdy[2];
end
5'h3: begin
current_direction = fifo_direction[3];
current_fifo = fifo_rdy[3];
end
5'h4: begin
current_direction = fifo_direction[4];
current_fifo = fifo_rdy[0];
end
5'h5: begin
current_direction = fifo_direction[5];
current_fifo = fifo_rdy[0];
end
5'h6: begin
current_direction = fifo_direction[6];
current_fifo = fifo_rdy[0];
end
5'h7: begin
current_direction = fifo_direction[7];
current_fifo = fifo_rdy[0];
end
5'h8: begin
current_direction = fifo_direction[8];
current_fifo = fifo_rdy[0];
end
5'h9: begin
current_direction = fifo_direction[9];
current_fifo = fifo_rdy[0];
end
default: begin
current_direction = 0;
current_fifo = fifo_rdy[0];
end
endcase
end
// STATE MACHINE GPIF II
always @(posedge pclk) begin
if (reset_n == 1'b0 || trig == 1'b0 ) begin
state_gpif_ii <= IDLE;
end else begin
state_gpif_ii <= next_state_gpif_ii;
end
end
always @(*) begin
case(state_gpif_ii)
IDLE:
if(trig == 1'b1 && current_fifo == 1'b1) begin
if (current_direction == 0) begin
next_state_gpif_ii = READ_START;
end else begin
next_state_gpif_ii = WRITE_DATA;
end
end else begin
next_state_gpif_ii = IDLE;
end
READ_START:
next_state_gpif_ii = READ_DATA;
READ_DATA:
if (eot_fx32dma == 1'b1) begin
next_state_gpif_ii = IDLE;
end else begin
next_state_gpif_ii = READ_DATA;
end
WRITE_DATA:
if(dma2fx3_eop == 1'b1) begin
next_state_gpif_ii = IDLE;
end else begin
next_state_gpif_ii = WRITE_DATA;
end
default: next_state_gpif_ii = IDLE;
endcase
end
always @(*) begin
case(state_gpif_ii)
IDLE: begin
slcs_n = 1'b1;
sloe_n = 1'b1;
slrd_n = 1'b1;
fx32dma_valid = 1'b0;
fx32dma_sop = 1'b0;
fx32dma_data = 32'h0;
slwr_n = 1'b1;
pktend_n = 1'b1;
dma2fx3_ready = 1'b0;
end
READ_START: begin
slcs_n = 1'b0;
sloe_n = 1'b0;
slrd_n = 1'b1;
fx32dma_valid = 1'b0;
fx32dma_sop = 1'b0;
fx32dma_data = 32'h0;
slwr_n = 1'b1;
pktend_n = 1'b1;
dma2fx3_ready = 1'b0;
end
READ_DATA: begin
slcs_n = 1'b0;
sloe_n = 1'b0;
slrd_n = !fx32dma_ready | fx32dma_eop;
fx32dma_valid = !slcs_n_d4 & !slrd_n_d3;
fx32dma_sop = !slcs_n_d4 & !slrd_n_d3 & pip;
fx32dma_data = data;
slwr_n = 1'b1;
pktend_n = 1'b1;
dma2fx3_ready = 1'b0;
end
WRITE_DATA: begin
slcs_n = 1'b0;
sloe_n = 1'b1;
slrd_n = 1'b1;
fx32dma_valid = 1'b0;
fx32dma_sop = 1'b0;
fx32dma_data = 32'h0;
slwr_n = !dma2fx3_valid | !current_fifo;
dma2fx3_ready = current_fifo;
pktend_n = !dma2fx3_eop;
end
default: begin
slcs_n = 1'b1;
sloe_n = 1'b1;
slrd_n = 1'b1;
fx32dma_valid = 1'b0;
fx32dma_sop = 1'b0;
fx32dma_data = 32'h0;
slwr_n = 1'b1;
pktend_n = 1'b1;
dma2fx3_ready = 1'b0;
end
endcase
end
always @(posedge pclk) begin
fifo_ready <= {7'h0,fifo_rdy};
slrd_n_d1 <= slrd_n;
slrd_n_d2 <= slrd_n_d1;
slrd_n_d3 <= slrd_n_d2;
slcs_n_d1 <= slcs_n;
slcs_n_d2 <= slcs_n_d1;
slcs_n_d3 <= slcs_n_d2;
slcs_n_d4 <= slcs_n_d3;
addr <= fifo_num[1:0];
if (state_gpif_ii == IDLE) begin
pip <= 1'b1;
end else begin
if (fx32dma_sop == 1'b1) begin
pip <= 1'b0;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
adi_library/axi_usb_fx3/axi_usb_fx3_ip.log
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adi_library/axi_usb_fx3/axi_usb_fx3_ip.tcl
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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create axi_usb_fx3
adi_ip_files axi_usb_fx3 [list \
"$ad_hdl_dir/library/common/up_axi.v" \
"axi_usb_fx3_core.v" \
"axi_usb_fx3_if.v" \
"axi_usb_fx3_reg.v" \
"axi_usb_fx3.v"]
adi_ip_properties axi_usb_fx3
adi_ip_infer_streaming_interfaces axi_usb_fx3
ipx::associate_bus_interfaces -busif m_axis -clock s_axi_aclk [ipx::current_core]
ipx::associate_bus_interfaces -busif s_axis -clock s_axi_aclk [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/axi_usb_fx3/axi_usb_fx3_reg.v
+361
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_usb_fx3_reg (
// gpif ii
input [10:0] fifo_rdy,
input eot_fx32dma,
input eot_dma2fx3,
output trig,
output zlp,
output [ 4:0] fifo_num,
input error,
output [ 2:0] test_mode_tpm,
output [ 2:0] test_mode_tpg,
input monitor_error,
output irq,
output fifo0_direction,
output [ 7:0] fifo0_header_size,
output [15:0] fifo0_buffer_size,
output fifo1_direction,
output [ 7:0] fifo1_header_size,
output [15:0] fifo1_buffer_size,
output fifo2_direction,
output [ 7:0] fifo2_header_size,
output [15:0] fifo2_buffer_size,
output fifo3_direction,
output [ 7:0] fifo3_header_size,
output [15:0] fifo3_buffer_size,
output fifo4_direction,
output [ 7:0] fifo4_header_size,
output [15:0] fifo4_buffer_size,
output fifo5_direction,
output [ 7:0] fifo5_header_size,
output [15:0] fifo5_buffer_size,
output fifo6_direction,
output [ 7:0] fifo6_header_size,
output [15:0] fifo6_buffer_size,
output fifo7_direction,
output [ 7:0] fifo7_header_size,
output [15:0] fifo7_buffer_size,
output fifo8_direction,
output [ 7:0] fifo8_header_size,
output [15:0] fifo8_buffer_size,
output fifo9_direction,
output [ 7:0] fifo9_header_size,
output [15:0] fifo9_buffer_size,
output fifoa_direction,
output [ 7:0] fifoa_header_size,
output [15:0] fifoa_buffer_size,
input [31:0] length_fx32dma,
input [31:0] length_dma2fx3,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire fifo0_enable;
wire fifo1_enable;
wire fifo2_enable;
wire fifo3_enable;
wire fifo4_enable;
wire fifo5_enable;
wire fifo6_enable;
wire fifo7_enable;
wire fifo8_enable;
wire fifo9_enable;
wire fifoa_enable;
// internal registers
reg [31:0] fifo0_config = 32'h0;
reg [31:0] fifo1_config = 32'h0;
reg [31:0] fifo2_config = 32'h0;
reg [31:0] fifo3_config = 32'h0;
reg [31:0] fifo4_config = 32'h0;
reg [31:0] fifo5_config = 32'h0;
reg [31:0] fifo6_config = 32'h0;
reg [31:0] fifo7_config = 32'h0;
reg [31:0] fifo8_config = 32'h0;
reg [31:0] fifo9_config = 32'h0;
reg [31:0] fifoa_config = 32'h0;
reg [31:0] fifo_status = 32'h0;
reg [31:0] irq_config = 32'h0; // bit 1 - enable error interrupt, bit 0 - enable ready interrupt
reg [31:0] transfer_config = 32'h0;
reg [31:0] transfer_status = 32'h0;
reg [31:0] tpm_config = 32'h0;
reg [31:0] tpm_status = 32'h0;
reg [31:0] tpg_config = 32'h0;
reg [31:0] tpg_status = 32'h0;
assign up_wreq_s = ((up_waddr[13:8] == 6'h00)) ? up_wreq : 1'b0;
assign up_rreq_s = ((up_raddr[13:8] == 6'h00)) ? up_rreq : 1'b0;
assign trig = transfer_config[31];
assign zlp = transfer_config[30];
assign fifo_num = transfer_config[4:0];
assign test_mode_tpm = tpm_config[2:0];
assign test_mode_tpg = tpg_config[2:0];
assign fifo0_enable = fifo0_config[31];
assign fifo0_direction = fifo0_config[30];
assign fifo0_header_size = fifo0_config[23:16];
assign fifo0_buffer_size = fifo0_config[15:0];
assign fifo1_enable = fifo1_config[31];
assign fifo1_direction = fifo1_config[30];
assign fifo1_header_size = fifo1_config[23:16];
assign fifo1_buffer_size = fifo1_config[15:0];
assign fifo2_enable = fifo2_config[31];
assign fifo2_direction = fifo2_config[30];
assign fifo2_header_size = fifo2_config[23:16];
assign fifo2_buffer_size = fifo2_config[15:0];
assign fifo3_enable = fifo3_config[31];
assign fifo3_direction = fifo3_config[30];
assign fifo3_header_size = fifo3_config[23:16];
assign fifo3_buffer_size = fifo3_config[15:0];
assign fifo4_enable = fifo4_config[31];
assign fifo4_direction = fifo4_config[30];
assign fifo4_header_size = fifo4_config[23:16];
assign fifo4_buffer_size = fifo4_config[15:0];
assign fifo5_enable = fifo5_config[31];
assign fifo5_direction = fifo5_config[30];
assign fifo5_header_size = fifo5_config[23:16];
assign fifo5_buffer_size = fifo5_config[15:0];
assign fifo6_enable = fifo6_config[31];
assign fifo6_direction = fifo6_config[30];
assign fifo6_header_size = fifo6_config[23:16];
assign fifo6_buffer_size = fifo6_config[15:0];
assign fifo7_enable = fifo7_config[31];
assign fifo7_direction = fifo7_config[30];
assign fifo7_header_size = fifo7_config[23:16];
assign fifo7_buffer_size = fifo7_config[15:0];
assign fifo8_enable = fifo8_config[31];
assign fifo8_direction = fifo8_config[30];
assign fifo8_header_size = fifo8_config[23:16];
assign fifo8_buffer_size = fifo8_config[15:0];
assign fifo9_enable = fifo9_config[31];
assign fifo9_direction = fifo9_config[30];
assign fifo9_header_size = fifo9_config[23:16];
assign fifo9_buffer_size = fifo9_config[15:0];
assign fifoa_enable = fifoa_config[31];
assign fifoa_direction = fifoa_config[30];
assign fifoa_header_size = fifoa_config[23:16];
assign fifoa_buffer_size = fifoa_config[15:0];
// generate interrupt if fifo is enabled and fifo is ready
// or if an error has been encountered and irq is enabled
assign irq = ( ((fifo0_enable & fifo_rdy[0]) | (fifo1_enable & fifo_rdy[1]) |
(fifo2_enable & fifo_rdy[2]) | (fifo3_enable & fifo_rdy[3]) |
(fifo4_enable & fifo_rdy[4]) | (fifo5_enable & fifo_rdy[5]) |
(fifo6_enable & fifo_rdy[6]) | (fifo7_enable & fifo_rdy[7]) |
(fifo8_enable & fifo_rdy[8]) | (fifo9_enable & fifo_rdy[9]) |
(fifoa_enable & fifo_rdy[10])) & irq_config[0] ) | (error & irq_config[1] ) ;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
fifo0_config <= 32'h00100400;
fifo1_config <= 32'h00100400;
fifo2_config <= 32'h00100400;
fifo3_config <= 32'h00100400;
fifo4_config <= 32'h00100400;
fifo5_config <= 32'h00100400;
fifo6_config <= 32'h00100400;
fifo7_config <= 32'h00100400;
fifo8_config <= 32'h00100400;
fifo9_config <= 32'h00100400;
fifoa_config <= 32'h00100400;
irq_config <= 32'h0;
transfer_config <= 32'h0;
transfer_status <= 32'h0;
tpm_config <= 32'h0;
tpm_status <= 32'h0;
tpg_config <= 32'h0;
tpg_status <= 32'h0;
fifo_status <= 32'h0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h0)) begin
fifo0_config <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
fifo1_config <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h2)) begin
fifo2_config <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h3)) begin
fifo3_config <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h4)) begin
fifo4_config <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h5)) begin
fifo5_config <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h6)) begin
fifo6_config <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h7)) begin
fifo7_config <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h8)) begin
fifo8_config <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h9)) begin
fifo9_config <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'ha)) begin
fifoa_config <= up_wdata;
end
fifo_status[10:0] <= fifo_rdy;
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h11)) begin
irq_config <= up_wdata;
end
if (eot_fx32dma == 1'b1 || eot_dma2fx3 == 1'b1 || error == 1'b1) begin
transfer_config[31] <= 1'b0;
transfer_config[30] <= 1'b0;
end else if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h12)) begin
transfer_config <= up_wdata;
end
if (error == 1'b1) begin
transfer_status[0] <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h13)) begin
transfer_status[0] <= transfer_status[0] & ~up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h14)) begin
tpm_config <= up_wdata;
end
if (monitor_error == 1'b1) begin
tpm_status[0] <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h15)) begin
tpm_status[0] <= tpm_status[0] & ~up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h16)) begin
tpg_config <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h17)) begin
tpg_status <= up_wdata;
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[4:0])
5'h0: up_rdata <= fifo0_config;
5'h1: up_rdata <= fifo1_config;
5'h2: up_rdata <= fifo2_config;
5'h3: up_rdata <= fifo3_config;
5'h4: up_rdata <= fifo4_config;
5'h5: up_rdata <= fifo5_config;
5'h6: up_rdata <= fifo6_config;
5'h7: up_rdata <= fifo7_config;
5'h8: up_rdata <= fifo8_config;
5'h9: up_rdata <= fifo9_config;
5'ha: up_rdata <= fifoa_config;
5'h10: up_rdata <= fifo_status;
5'h11: up_rdata <= irq_config;
5'h12: up_rdata <= transfer_config;
5'h13: up_rdata <= transfer_status;
5'h14: up_rdata <= tpm_config;
5'h15: up_rdata <= tpm_status;
5'h16: up_rdata <= tpg_config;
5'h17: up_rdata <= tpg_status;
5'h18: up_rdata <= length_fx32dma;
5'h19: up_rdata <= length_dma2fx3;
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
adi_library/axi_usb_fx3/component.xml
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adi_library/axi_usb_fx3/vivado.jou
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#-----------------------------------------------------------
# Vivado v2019.1.3 (64-bit)
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
# Start of session at: Thu Dec 9 15:16:39 2021
# Process ID: 6356
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_usb_fx3
# Command line: vivado -mode batch -source axi_usb_fx3_ip.tcl
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_usb_fx3/vivado.log
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_usb_fx3/vivado.jou
#-----------------------------------------------------------
source axi_usb_fx3_ip.tcl
adi_library/axi_usb_fx3/vivado.log
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adi_library/axi_usb_fx3/xgui/axi_usb_fx3_v1_0.tcl
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
ipgui::add_page $IPINST -name "Page 0"
}