initial commit

adi_library/intel/avl_adxcvr_octet_swap/Makefile

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+####################################################################################
+## Copyright 2018(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+
+LIBRARY_NAME := avl_adxcvr_octet_swap
+
+INTEL_DEPS += avl_adxcvr_octet_swap.v
+INTEL_DEPS += avl_adxcvr_octet_swap_hw.tcl
+
+include ../../scripts/library.mk

adi_library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v

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+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module avl_adxcvr_octet_swap #(
+  parameter NUM_OF_LANES = 1
+) (
+  input clk,
+  input reset,
+
+  input in_valid,
+  output in_ready,
+  input [NUM_OF_LANES*32-1:0] in_data,
+  input [3:0] in_sof,
+
+  output out_valid,
+  input out_ready,
+  output [NUM_OF_LANES*32-1:0] out_data,
+  output [3:0] out_sof
+);
+
+assign in_ready = out_ready;
+assign out_valid = in_valid;
+
+generate
+  genvar i;
+  genvar j;
+
+  for (j = 0; j < 4; j = j + 1) begin: gen_octet
+    for (i = 0; i < NUM_OF_LANES; i = i + 1) begin: gen_lane
+      assign out_data[i*32+j*8+7:i*32+j*8] = in_data[i*32+(3-j)*8+7:i*32+(3-j)*8];
+    end
+    assign out_sof[j] = in_sof[3-j];
+  end
+endgenerate
+
+endmodule

adi_library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap_hw.tcl

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+
+package require qsys
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
+
+ad_ip_create avl_adxcvr_octet_swap "avl_adxcvvr_octet_swap helper" avl_adxcvr_octet_swap_elaboration
+set_module_property HIDE_FROM_SOPC true
+set_module_property HIDE_FROM_QSYS true
+set_module_property HIDE_FROM_QUARTUS true
+
+# files
+
+ad_ip_files avl_adxcvr_octet_swap { \
+  avl_adxcvr_octet_swap.v
+}
+
+# parameters
+
+ad_ip_parameter NUM_OF_LANES INTEGER 4 true
+ad_ip_parameter TX_OR_RX_N INTEGER 0 false
+
+# interfaces
+
+add_interface clock clock end
+add_interface_port clock clk clk Input 1
+
+add_interface reset reset end
+add_interface_port reset reset reset Input 1
+set_interface_property reset associatedClock clock
+
+add_interface in_sof conduit end
+add_interface_port in_sof in_sof export Input 4
+
+add_interface out_sof conduit end
+add_interface_port out_sof out_sof export Output 4
+
+proc avl_adxcvr_octet_swap_elaboration {} {
+  set num_lanes [get_parameter_value NUM_OF_LANES]
+  set tx [get_parameter_value TX_OR_RX_N]
+
+  add_interface in avalon_streaming sink
+  set_interface_property in associatedClock clock
+  set_interface_property in associatedReset reset
+  add_interface_port in in_data data input [expr 32*$num_lanes]
+  add_interface_port in in_valid valid input 1
+  add_interface_port in in_ready ready output 1
+  set_interface_property in dataBitsPerSymbol [expr 32*$num_lanes]
+
+  add_interface out avalon_streaming source
+  set_interface_property out associatedClock clock
+  set_interface_property out associatedReset reset
+  add_interface_port out out_data data output [expr 32*$num_lanes]
+  add_interface_port out out_valid valid output 1
+  add_interface_port out out_ready ready input 1
+  set_interface_property out dataBitsPerSymbol [expr 32*$num_lanes]
+
+  if {$tx} {
+    set_port_property in_sof TERMINATION true
+    set_port_property in_sof TERMINATION_VALUE 0
+    set_port_property out_sof TERMINATION true
+  }
+}