Archived
initial commit
This commit is contained in:
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
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||||
//
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||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
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||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
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||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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||||
//
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||||
// OR
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||||
//
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||||
// 2. An ADI specific BSD license, which can be found in the top level directory
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||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
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||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// dc filter- y(n) = c*x(n) + (1-c)*y(n-1)
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// NOT IMPLEMENTED
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`timescale 1ps/1ps
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module ad_dcfilter #(
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// data path disable
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parameter DISABLE = 0) (
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// data interface
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input clk,
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input valid,
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input [15:0] data,
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output reg valid_out,
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output reg [15:0] data_out,
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// control interface
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input dcfilt_enb,
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input [15:0] dcfilt_coeff,
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input [15:0] dcfilt_offset);
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// internal registers
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reg valid_d = 'd0;
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reg [15:0] data_d = 'd0;
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reg valid_2d = 'd0;
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reg [15:0] data_2d = 'd0;
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// internal signals
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wire [47:0] dc_offset_s;
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always @(posedge clk) begin
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valid_d <= valid;
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if (valid == 1'b1) begin
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data_d <= data + dcfilt_offset;
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end
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valid_2d <= valid_d;
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data_2d <= data_d;
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valid_out <= valid_2d;
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data_out <= data_2d;
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@@ -0,0 +1,90 @@
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// ***************************************************************************
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||||
// ***************************************************************************
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||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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||||
//
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// OR
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||||
//
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||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
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||||
//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ps/1ps
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module ad_mul #(
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parameter A_DATA_WIDTH = 17,
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parameter B_DATA_WIDTH = 17,
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parameter DELAY_DATA_WIDTH = 16) (
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// data_p = data_a * data_b;
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input clk,
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input [ A_DATA_WIDTH-1:0] data_a,
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input [ B_DATA_WIDTH-1:0] data_b,
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output [A_DATA_WIDTH + B_DATA_WIDTH-1:0] data_p,
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// delay interface
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input [(DELAY_DATA_WIDTH-1):0] ddata_in,
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output reg [(DELAY_DATA_WIDTH-1):0] ddata_out);
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// internal registers
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reg [(DELAY_DATA_WIDTH-1):0] p1_ddata = 'd0;
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reg [(DELAY_DATA_WIDTH-1):0] p2_ddata = 'd0;
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// a/b reg, m-reg, p-reg delay match
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always @(posedge clk) begin
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p1_ddata <= ddata_in;
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p2_ddata <= p1_ddata;
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ddata_out <= p2_ddata;
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end
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lpm_mult #(
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.lpm_type ("lpm_mult"),
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.lpm_widtha (A_DATA_WIDTH),
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.lpm_widthb (B_DATA_WIDTH),
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.lpm_widthp (A_DATA_WIDTH + B_DATA_WIDTH),
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.lpm_representation ("SIGNED"),
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.lpm_pipeline (3))
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i_lpm_mult (
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.clken (1'b1),
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.aclr (1'b0),
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.sclr (1'b0),
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.sum (1'b0),
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.clock (clk),
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.dataa (data_a),
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.datab (data_b),
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.result (data_p));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@@ -0,0 +1,10 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := intel_mem_asym
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INTEL_DEPS += intel_mem_asym_hw.tcl
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include ../../../scripts/library.mk
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@@ -0,0 +1,60 @@
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package require qsys
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source ../../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
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ad_ip_create intel_mem_asym {Intel Asymmetric Memory}
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set_module_property COMPOSITION_CALLBACK p_intel_mem_asym
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# parameters
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ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
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ad_ip_parameter A_ADDRESS_WIDTH INTEGER 8
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ad_ip_parameter A_DATA_WIDTH INTEGER 512
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ad_ip_parameter B_ADDRESS_WIDTH INTEGER 8
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ad_ip_parameter B_DATA_WIDTH INTEGER 64
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# compose
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proc p_intel_mem_asym {} {
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set m_addr_width_a [get_parameter_value "A_ADDRESS_WIDTH"]
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set m_data_width_a [get_parameter_value "A_DATA_WIDTH"]
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set m_addr_width_b [get_parameter_value "B_ADDRESS_WIDTH"]
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set m_data_width_b [get_parameter_value "B_DATA_WIDTH"]
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set m_size [expr ((2**$m_addr_width_a)*$m_data_width_a)]
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if {$m_addr_width_a == 0} {
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set m_size [expr ((2**$m_addr_width_b)*$m_data_width_b)]
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}
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add_instance intel_mem ram_2port 1.0
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set_instance_parameter_value intel_mem {GUI_MODE} 0
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set_instance_parameter_value intel_mem {GUI_MEM_IN_BITS} 1
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set_instance_parameter_value intel_mem {GUI_MEMSIZE_BITS} $m_size
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set_instance_parameter_value intel_mem {GUI_VAR_WIDTH} 1
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set_instance_parameter_value intel_mem {GUI_QA_WIDTH} $m_data_width_a
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set_instance_parameter_value intel_mem {GUI_DATAA_WIDTH} $m_data_width_a
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set_instance_parameter_value intel_mem {GUI_QB_WIDTH} $m_data_width_b
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set_instance_parameter_value intel_mem {GUI_READ_OUTPUT_QB} {false}
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set_instance_parameter_value intel_mem {GUI_RAM_BLOCK_TYPE} {M20K}
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set_instance_parameter_value intel_mem {GUI_CLOCK_TYPE} 1
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add_interface mem_i_wrclock clock end
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add_interface mem_i_wren conduit end
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add_interface mem_i_wraddress conduit end
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add_interface mem_i_datain conduit end
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add_interface mem_i_rdclock clock end
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add_interface mem_i_rdaddress conduit end
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add_interface mem_o_dataout conduit end
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set_interface_property mem_i_wrclock EXPORT_OF intel_mem.wrclock
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set_interface_property mem_i_wren EXPORT_OF intel_mem.wren
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set_interface_property mem_i_wraddress EXPORT_OF intel_mem.wraddress
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set_interface_property mem_i_datain EXPORT_OF intel_mem.data
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set_interface_property mem_i_rdclock EXPORT_OF intel_mem.rdclock
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set_interface_property mem_i_rdaddress EXPORT_OF intel_mem.rdaddress
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set_interface_property mem_o_dataout EXPORT_OF intel_mem.q
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}
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@@ -0,0 +1,10 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := intel_serdes
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INTEL_DEPS += intel_serdes_hw.tcl
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include ../../../scripts/library.mk
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@@ -0,0 +1,138 @@
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package require qsys
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source ../../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
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ad_ip_create intel_serdes {Intel SERDES}
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set_module_property COMPOSITION_CALLBACK p_intel_serdes
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# parameters
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ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
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ad_ip_parameter MODE STRING "CLK" false
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ad_ip_parameter DDR_OR_SDR_N INTEGER 1 false
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ad_ip_parameter SERDES_FACTOR INTEGER 8 false
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ad_ip_parameter CLKIN_FREQUENCY FLOAT 500.0 false
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set_parameter_property MODE ALLOWED_RANGES {"CLK" "IN" "IN_NODPA" "OUT"}
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set_parameter_property DDR_OR_SDR_N ALLOWED_RANGES {0 1}
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set_parameter_property SERDES_FACTOR ALLOWED_RANGES {4 8}
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set_parameter_property CLKIN_FREQUENCY DISPLAY_UNITS "MHz"
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proc p_intel_serdes {} {
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set m_mode [get_parameter_value "MODE"]
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set m_ddr_or_sdr_n [get_parameter_value "DDR_OR_SDR_N"]
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set m_serdes_factor [get_parameter_value "SERDES_FACTOR"]
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set m_clkin_frequency [get_parameter_value "CLKIN_FREQUENCY"]
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set m_hs_data_rate [expr ($m_clkin_frequency * ($m_ddr_or_sdr_n + 1))]
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set m_ls_data_rate [expr ($m_hs_data_rate/$m_serdes_factor)]
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set m_ls_phase 22.5
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set m_ld_phase 315.0
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set m_ld_duty_cycle 12.5
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if {$m_serdes_factor == 4} {
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set m_ls_phase 45
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set m_ld_phase 270.0
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set m_ld_duty_cycle 25.0
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}
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## arria 10 only
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if {$m_mode == "CLK"} {
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add_instance intel_serdes_pll altera_iopll 19.1
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set_instance_parameter_value intel_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
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set_instance_parameter_value intel_serdes_pll {gui_use_locked} {1}
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set_instance_parameter_value intel_serdes_pll {gui_operation_mode} {lvds}
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set_instance_parameter_value intel_serdes_pll {gui_number_of_clocks} {3}
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set_instance_parameter_value intel_serdes_pll {gui_en_lvds_ports} {Enable LVDS_CLK/LOADEN 0}
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set_instance_parameter_value intel_serdes_pll {gui_en_phout_ports} {true}
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set_instance_parameter_value intel_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
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set_instance_parameter_value intel_serdes_pll {gui_ps_units0} {degrees}
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set_instance_parameter_value intel_serdes_pll {gui_phase_shift_deg0} {180.0}
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set_instance_parameter_value intel_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
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set_instance_parameter_value intel_serdes_pll {gui_ps_units1} {degrees}
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set_instance_parameter_value intel_serdes_pll {gui_phase_shift_deg1} $m_ld_phase
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set_instance_parameter_value intel_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle
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set_instance_parameter_value intel_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
|
||||
set_instance_parameter_value intel_serdes_pll {gui_phase_shift_deg2} $m_ls_phase
|
||||
set_instance_parameter_value intel_serdes_pll {gui_ps_units2} {degrees}
|
||||
add_interface rst reset sink
|
||||
set_interface_property rst EXPORT_OF intel_serdes_pll.reset
|
||||
add_interface ref_clk clock sink
|
||||
set_interface_property ref_clk EXPORT_OF intel_serdes_pll.refclk
|
||||
add_interface locked conduit end
|
||||
set_interface_property locked EXPORT_OF intel_serdes_pll.locked
|
||||
add_interface hs_phase conduit end
|
||||
set_interface_property hs_phase EXPORT_OF intel_serdes_pll.phout
|
||||
add_interface hs_clk conduit end
|
||||
set_interface_property hs_clk EXPORT_OF intel_serdes_pll.lvds_clk
|
||||
add_interface loaden conduit end
|
||||
set_interface_property loaden EXPORT_OF intel_serdes_pll.loaden
|
||||
add_interface ls_clk clock source
|
||||
set_interface_property ls_clk EXPORT_OF intel_serdes_pll.outclk2
|
||||
return
|
||||
}
|
||||
|
||||
if {$m_mode == "IN" || $m_mode == "IN_NODPA"} {
|
||||
add_instance intel_serdes_in altera_lvds 19.1
|
||||
if {$m_mode == "IN"} {
|
||||
set_instance_parameter_value intel_serdes_in {MODE} {RX_DPA-FIFO}
|
||||
} else {
|
||||
set_instance_parameter_value intel_serdes_in {MODE} {RX_Non-DPA}
|
||||
}
|
||||
set_instance_parameter_value intel_serdes_in {NUM_CHANNELS} {1}
|
||||
set_instance_parameter_value intel_serdes_in {DATA_RATE} $m_hs_data_rate
|
||||
set_instance_parameter_value intel_serdes_in {J_FACTOR} $m_serdes_factor
|
||||
set_instance_parameter_value intel_serdes_in {USE_EXTERNAL_PLL} {true}
|
||||
set_instance_parameter_value intel_serdes_in {INCLOCK_FREQUENCY} $m_clkin_frequency
|
||||
set_instance_parameter_value intel_serdes_in {PLL_USE_RESET} {false}
|
||||
add_interface data_in conduit end
|
||||
set_interface_property data_in EXPORT_OF intel_serdes_in.rx_in
|
||||
add_interface clk conduit end
|
||||
set_interface_property clk EXPORT_OF intel_serdes_in.ext_fclk
|
||||
add_interface loaden conduit end
|
||||
set_interface_property loaden EXPORT_OF intel_serdes_in.ext_loaden
|
||||
add_interface div_clk conduit end
|
||||
set_interface_property div_clk EXPORT_OF intel_serdes_in.ext_coreclock
|
||||
if {$m_mode == "IN"} {
|
||||
add_interface hs_phase conduit end
|
||||
set_interface_property hs_phase EXPORT_OF intel_serdes_in.ext_vcoph
|
||||
add_interface locked conduit end
|
||||
set_interface_property locked EXPORT_OF intel_serdes_in.ext_pll_locked
|
||||
add_interface delay_locked conduit end
|
||||
set_interface_property delay_locked EXPORT_OF intel_serdes_in.rx_dpa_locked
|
||||
}
|
||||
add_interface data_s conduit end
|
||||
set_interface_property data_s EXPORT_OF intel_serdes_in.rx_out
|
||||
return
|
||||
}
|
||||
|
||||
if {$m_mode == "OUT"} {
|
||||
add_instance intel_serdes_out altera_lvds 19.1
|
||||
set_instance_parameter_value intel_serdes_out {MODE} {TX}
|
||||
set_instance_parameter_value intel_serdes_out {NUM_CHANNELS} {1}
|
||||
set_instance_parameter_value intel_serdes_out {DATA_RATE} $m_hs_data_rate
|
||||
set_instance_parameter_value intel_serdes_out {J_FACTOR} $m_serdes_factor
|
||||
set_instance_parameter_value intel_serdes_out {TX_EXPORT_CORECLOCK} {false}
|
||||
set_instance_parameter_value intel_serdes_out {TX_USE_OUTCLOCK} {false}
|
||||
set_instance_parameter_value intel_serdes_out {USE_EXTERNAL_PLL} {true}
|
||||
set_instance_parameter_value intel_serdes_out {INCLOCK_FREQUENCY} $m_clkin_frequency
|
||||
set_instance_parameter_value intel_serdes_out {PLL_USE_RESET} {false}
|
||||
add_interface data_out conduit end
|
||||
set_interface_property data_out EXPORT_OF intel_serdes_out.tx_out
|
||||
add_interface clk conduit end
|
||||
set_interface_property clk EXPORT_OF intel_serdes_out.ext_fclk
|
||||
add_interface loaden conduit end
|
||||
set_interface_property loaden EXPORT_OF intel_serdes_out.ext_loaden
|
||||
add_interface div_clk conduit end
|
||||
set_interface_property div_clk EXPORT_OF intel_serdes_out.ext_coreclock
|
||||
add_interface data_s conduit end
|
||||
set_interface_property data_s EXPORT_OF intel_serdes_out.tx_in
|
||||
return
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,4 @@
|
||||
|
||||
set_false_path -from [get_registers *up_clock_mon:i_clock_mon|d_count_run_m3*] -to [get_registers *up_clock_mon:i_clock_mon|up_count_running_m1*]
|
||||
set_false_path -from [get_registers *up_clock_mon:i_clock_mon|up_count_run*] -to [get_registers *up_clock_mon:i_clock_mon|d_count_run_m1*]
|
||||
set_false_path -from [get_registers *up_clock_mon:i_clock_mon|d_count*] -to [get_registers *up_clock_mon:i_clock_mon|up_d_count*]
|
||||
@@ -0,0 +1,4 @@
|
||||
|
||||
set_false_path -to [get_pins -hierarchical -nocase rst_async_d*|CLRN]
|
||||
set_false_path -to [get_pins -hierarchical -nocase rst_sync|CLRN]
|
||||
|
||||
@@ -0,0 +1,4 @@
|
||||
|
||||
set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_cntrl|d_xfer_toggle*] -to [get_registers *up_xfer_cntrl:i_xfer_cntrl|up_xfer_state_m1*]
|
||||
set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_cntrl|up_xfer_toggle*] -to [get_registers *up_xfer_cntrl:i_xfer_cntrl|d_xfer_toggle_m1*]
|
||||
set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_cntrl|up_xfer_data*] -to [get_registers *up_xfer_cntrl:i_xfer_cntrl|d_data_cntrl*]
|
||||
@@ -0,0 +1,4 @@
|
||||
|
||||
set_false_path -from [get_registers *up_xfer_status:i_xfer_status|up_xfer_toggle*] -to [get_registers *up_xfer_status:i_xfer_status|d_xfer_state_m1*]
|
||||
set_false_path -from [get_registers *up_xfer_status:i_xfer_status|d_xfer_toggle*] -to [get_registers *up_xfer_status:i_xfer_status|up_xfer_toggle_m1*]
|
||||
set_false_path -from [get_registers *up_xfer_status:i_xfer_status|d_xfer_data*] -to [get_registers *up_xfer_status:i_xfer_status|up_data_status*]
|
||||
Reference in New Issue
Block a user