Archived
initial commit
This commit is contained in:
@@ -0,0 +1,40 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := ad_ip_jesd204_tpl_adc
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GENERIC_DEPS += ../../common/ad_datafmt.v
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GENERIC_DEPS += ../../common/ad_perfect_shuffle.v
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GENERIC_DEPS += ../../common/ad_pnmon.v
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GENERIC_DEPS += ../../common/ad_rst.v
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GENERIC_DEPS += ../../common/ad_xcvr_rx_if.v
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GENERIC_DEPS += ../../common/up_adc_channel.v
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GENERIC_DEPS += ../../common/up_adc_common.v
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GENERIC_DEPS += ../../common/up_axi.v
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GENERIC_DEPS += ../../common/up_clock_mon.v
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GENERIC_DEPS += ../../common/up_xfer_cntrl.v
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GENERIC_DEPS += ../../common/up_xfer_status.v
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GENERIC_DEPS += ad_ip_jesd204_tpl_adc.v
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GENERIC_DEPS += ad_ip_jesd204_tpl_adc_channel.v
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GENERIC_DEPS += ad_ip_jesd204_tpl_adc_core.v
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GENERIC_DEPS += ad_ip_jesd204_tpl_adc_deframer.v
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GENERIC_DEPS += ad_ip_jesd204_tpl_adc_pnmon.v
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GENERIC_DEPS += ad_ip_jesd204_tpl_adc_regmap.v
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XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc
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XILINX_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc
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XILINX_DEPS += ../../xilinx/common/up_xfer_cntrl_constr.xdc
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XILINX_DEPS += ../../xilinx/common/up_xfer_status_constr.xdc
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XILINX_DEPS += ../ad_ip_jesd204_tpl_common/up_tpl_common.v
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XILINX_DEPS += ad_ip_jesd204_tpl_adc_ip.tcl
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INTEL_DEPS += ../../intel/common/up_clock_mon_constr.sdc
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INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
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INTEL_DEPS += ../../intel/common/up_xfer_cntrl_constr.sdc
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INTEL_DEPS += ../../intel/common/up_xfer_status_constr.sdc
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INTEL_DEPS += ../../jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v
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INTEL_DEPS += ad_ip_jesd204_tpl_adc_hw.tcl
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include ../../scripts/library.mk
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@@ -0,0 +1,3 @@
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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eof:
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+6
@@ -0,0 +1,6 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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<labtools version="1" minor="0"/>
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@@ -0,0 +1,209 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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||||
// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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||||
//
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||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory, or at:
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||||
// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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||||
//
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||||
// OR
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||||
//
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||||
// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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||||
// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_ip_jesd204_tpl_adc #(
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parameter ID = 0,
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parameter FPGA_TECHNOLOGY = 0,
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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parameter DEV_PACKAGE = 0,
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parameter NUM_LANES = 1,
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parameter NUM_CHANNELS = 4,
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parameter SAMPLES_PER_FRAME = 1,
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parameter CONVERTER_RESOLUTION = 14,
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parameter BITS_PER_SAMPLE = 16,
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parameter OCTETS_PER_BEAT = 4,
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parameter TWOS_COMPLEMENT = 1
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) (
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// jesd interface
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// link_clk is (line-rate/40)
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input link_clk,
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input [OCTETS_PER_BEAT-1:0] link_sof,
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input link_valid,
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input [NUM_LANES*8*OCTETS_PER_BEAT-1:0] link_data,
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output link_ready,
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// dma interface
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output [NUM_CHANNELS-1:0] enable,
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output [NUM_CHANNELS-1:0] adc_valid,
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output [NUM_LANES*8*OCTETS_PER_BEAT-1:0] adc_data,
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input adc_dovf,
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input adc_sync_in,
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output adc_rst,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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output s_axi_awready,
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input [12:0] s_axi_awaddr,
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input [2:0] s_axi_awprot,
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input s_axi_wvalid,
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output s_axi_wready,
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input [31:0] s_axi_wdata,
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input [3:0] s_axi_wstrb,
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output s_axi_bvalid,
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input s_axi_bready,
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output [1:0] s_axi_bresp,
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input s_axi_arvalid,
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output s_axi_arready,
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input [12:0] s_axi_araddr,
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input [2:0] s_axi_arprot,
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output s_axi_rvalid,
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input s_axi_rready,
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output [1:0] s_axi_rresp,
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output [31:0] s_axi_rdata
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);
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// Number of samples per channel that are processed in parallel.
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localparam DATA_PATH_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES / NUM_CHANNELS / BITS_PER_SAMPLE;
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localparam LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8;
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localparam DMA_DATA_WIDTH = BITS_PER_SAMPLE * DATA_PATH_WIDTH * NUM_CHANNELS;
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localparam BYTES_PER_FRAME = (NUM_CHANNELS * BITS_PER_SAMPLE * SAMPLES_PER_FRAME) / ( 8 * NUM_LANES);
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wire [NUM_CHANNELS-1:0] dfmt_enable_s;
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wire [NUM_CHANNELS-1:0] dfmt_sign_extend_s;
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wire [NUM_CHANNELS-1:0] dfmt_type_s;
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||||
wire [NUM_CHANNELS*4-1:0] pn_seq_sel_s;
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wire [NUM_CHANNELS-1:0] pn_err_s;
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wire [NUM_CHANNELS-1:0] pn_oos_s;
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||||
wire adc_rst_sync_s;
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wire adc_rst_s;
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wire adc_sync;
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wire adc_sync_status;
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assign adc_rst = adc_rst_s | adc_rst_sync_s;
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// regmap
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ad_ip_jesd204_tpl_adc_regmap #(
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.ID (ID),
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.FPGA_FAMILY (FPGA_FAMILY),
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||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
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||||
.NUM_CHANNELS (NUM_CHANNELS),
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||||
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
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.NUM_PROFILES(1)
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) i_regmap (
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.s_axi_aclk (s_axi_aclk),
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.s_axi_aresetn (s_axi_aresetn),
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.s_axi_awvalid (s_axi_awvalid),
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||||
.s_axi_awready (s_axi_awready),
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||||
.s_axi_awaddr (s_axi_awaddr),
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.s_axi_awprot (s_axi_awprot),
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.s_axi_wvalid (s_axi_wvalid),
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||||
.s_axi_wready (s_axi_wready),
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||||
.s_axi_wdata (s_axi_wdata),
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||||
.s_axi_wstrb (s_axi_wstrb),
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||||
.s_axi_bvalid (s_axi_bvalid),
|
||||
.s_axi_bresp (s_axi_bresp),
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||||
.s_axi_bready (s_axi_bready),
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||||
.s_axi_arvalid (s_axi_arvalid),
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||||
.s_axi_arready (s_axi_arready),
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||||
.s_axi_araddr (s_axi_araddr),
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||||
.s_axi_arprot (s_axi_arprot),
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||||
.s_axi_rvalid (s_axi_rvalid),
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.s_axi_rready (s_axi_rready),
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.s_axi_rresp (s_axi_rresp),
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.s_axi_rdata (s_axi_rdata),
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.link_clk (link_clk),
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.dfmt_enable (dfmt_enable_s),
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.dfmt_sign_extend (dfmt_sign_extend_s),
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||||
.dfmt_type (dfmt_type_s),
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||||
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.pn_seq_sel (pn_seq_sel_s),
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||||
.pn_err (pn_err_s),
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||||
.pn_oos (pn_oos_s),
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||||
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||||
.enable (enable),
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.adc_sync (adc_sync),
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||||
.adc_sync_status (adc_sync_status),
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||||
.adc_rst (adc_rst_s),
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.adc_dovf (adc_dovf),
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||||
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||||
.jesd_m (NUM_CHANNELS),
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||||
.jesd_l (NUM_LANES),
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.jesd_s (SAMPLES_PER_FRAME),
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||||
.jesd_f (BYTES_PER_FRAME),
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||||
.jesd_n (CONVERTER_RESOLUTION),
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||||
.jesd_np (BITS_PER_SAMPLE),
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.up_profile_sel ()
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||||
);
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ad_ip_jesd204_tpl_adc_core #(
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||||
.NUM_LANES (NUM_LANES),
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||||
.NUM_CHANNELS (NUM_CHANNELS),
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||||
.BITS_PER_SAMPLE (BITS_PER_SAMPLE),
|
||||
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
|
||||
.SAMPLES_PER_FRAME (SAMPLES_PER_FRAME),
|
||||
.OCTETS_PER_BEAT (OCTETS_PER_BEAT),
|
||||
.LINK_DATA_WIDTH (LINK_DATA_WIDTH),
|
||||
.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
|
||||
.TWOS_COMPLEMENT (TWOS_COMPLEMENT),
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||||
.DATA_PATH_WIDTH (DATA_PATH_WIDTH)
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||||
) i_core (
|
||||
.clk (link_clk),
|
||||
|
||||
.dfmt_enable (dfmt_enable_s),
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||||
.dfmt_sign_extend (dfmt_sign_extend_s),
|
||||
.dfmt_type (dfmt_type_s),
|
||||
|
||||
.pn_seq_sel (pn_seq_sel_s),
|
||||
.pn_err (pn_err_s),
|
||||
.pn_oos (pn_oos_s),
|
||||
|
||||
.link_valid (link_valid),
|
||||
.link_ready (link_ready),
|
||||
.link_sof (link_sof),
|
||||
.link_data (link_data),
|
||||
|
||||
.adc_sync (adc_sync),
|
||||
.adc_sync_status (adc_sync_status),
|
||||
.adc_sync_in (adc_sync_in),
|
||||
.adc_rst_sync (adc_rst_sync_s),
|
||||
|
||||
.adc_valid (adc_valid),
|
||||
.adc_data (adc_data)
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||||
);
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||||
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||||
endmodule
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@@ -0,0 +1,526 @@
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||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="05162beadd19449898b1626aaec4def0"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../common/ad_datafmt.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/ad_ip_jesd204_tpl_adc_channel.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/ad_ip_jesd204_tpl_adc_core.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/ad_ip_jesd204_tpl_adc_deframer.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/ad_ip_jesd204_tpl_adc_pnmon.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/ad_ip_jesd204_tpl_adc_regmap.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../common/ad_perfect_shuffle.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../common/ad_pnmon.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../common/ad_rst.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../common/ad_xcvr_rx_if.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../common/up_adc_channel.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../common/up_adc_common.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../common/up_axi.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../common/up_clock_mon.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../ad_ip_jesd204_tpl_common/up_tpl_common.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../common/up_xfer_cntrl.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../common/up_xfer_status.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/ad_ip_jesd204_tpl_adc.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<File Path="$PPRDIR/bd/bd.tcl">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="ad_ip_jesd204_tpl_adc"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../../xilinx/common/up_xfer_cntrl_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../xilinx/common/ad_rst_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../xilinx/common/up_xfer_status_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../xilinx/common/up_clock_mon_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,86 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// Each core or library found in this collection may have its own licensing terms.
|
||||
// The user should keep this in in mind while exploring these cores.
|
||||
//
|
||||
// Redistribution and use in source and binary forms,
|
||||
// with or without modification of this file, are permitted under the terms of either
|
||||
// (at the option of the user):
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory, or at:
|
||||
// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module ad_ip_jesd204_tpl_adc_channel #(
|
||||
parameter CONVERTER_RESOLUTION = 14,
|
||||
parameter DATA_PATH_WIDTH = 2,
|
||||
parameter TWOS_COMPLEMENT = 1,
|
||||
parameter BITS_PER_SAMPLE = 16
|
||||
) (
|
||||
input clk,
|
||||
|
||||
input [CONVERTER_RESOLUTION*DATA_PATH_WIDTH-1:0] raw_data,
|
||||
|
||||
output [BITS_PER_SAMPLE*DATA_PATH_WIDTH-1:0] fmt_data,
|
||||
|
||||
// Configuration and status
|
||||
input dfmt_enable,
|
||||
input dfmt_type,
|
||||
input dfmt_sign_extend,
|
||||
|
||||
input [3:0] pn_seq_sel,
|
||||
output pn_oos,
|
||||
output pn_err
|
||||
);
|
||||
|
||||
localparam OCTETS_PER_SAMPLE = BITS_PER_SAMPLE / 8;
|
||||
|
||||
// instantiations
|
||||
|
||||
ad_ip_jesd204_tpl_adc_pnmon #(
|
||||
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
|
||||
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
|
||||
.TWOS_COMPLEMENT (TWOS_COMPLEMENT)
|
||||
) i_pnmon (
|
||||
.clk (clk),
|
||||
.data (raw_data),
|
||||
|
||||
.pn_seq_sel (pn_seq_sel),
|
||||
.pn_oos (pn_oos),
|
||||
.pn_err (pn_err)
|
||||
);
|
||||
|
||||
generate
|
||||
genvar n;
|
||||
for (n = 0; n < DATA_PATH_WIDTH; n = n + 1) begin: g_datafmt
|
||||
ad_datafmt #(
|
||||
.DATA_WIDTH (CONVERTER_RESOLUTION),
|
||||
.OCTETS_PER_SAMPLE (OCTETS_PER_SAMPLE)
|
||||
) i_ad_datafmt (
|
||||
.clk (clk),
|
||||
|
||||
.valid (1'b1),
|
||||
.data (raw_data[n*CONVERTER_RESOLUTION+:CONVERTER_RESOLUTION]),
|
||||
.valid_out (),
|
||||
.data_out (fmt_data[n*BITS_PER_SAMPLE+:BITS_PER_SAMPLE]),
|
||||
|
||||
.dfmt_enable (dfmt_enable),
|
||||
.dfmt_type (dfmt_type),
|
||||
.dfmt_se (dfmt_sign_extend)
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,130 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// Each core or library found in this collection may have its own licensing terms.
|
||||
// The user should keep this in in mind while exploring these cores.
|
||||
//
|
||||
// Redistribution and use in source and binary forms,
|
||||
// with or without modification of this file, are permitted under the terms of either
|
||||
// (at the option of the user):
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory, or at:
|
||||
// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module ad_ip_jesd204_tpl_adc_core #(
|
||||
parameter NUM_LANES = 1,
|
||||
parameter NUM_CHANNELS = 1,
|
||||
parameter SAMPLES_PER_FRAME = 1,
|
||||
parameter CONVERTER_RESOLUTION = 14,
|
||||
parameter BITS_PER_SAMPLE = 16,
|
||||
parameter OCTETS_PER_BEAT = 4,
|
||||
parameter DATA_PATH_WIDTH = 1,
|
||||
parameter LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8,
|
||||
parameter DMA_DATA_WIDTH = DATA_PATH_WIDTH * BITS_PER_SAMPLE * NUM_CHANNELS,
|
||||
parameter TWOS_COMPLEMENT = 1
|
||||
) (
|
||||
input clk,
|
||||
|
||||
input [NUM_CHANNELS-1:0] dfmt_enable,
|
||||
input [NUM_CHANNELS-1:0] dfmt_sign_extend,
|
||||
input [NUM_CHANNELS-1:0] dfmt_type,
|
||||
|
||||
input [NUM_CHANNELS*4-1:0] pn_seq_sel,
|
||||
output [NUM_CHANNELS-1:0] pn_err,
|
||||
output [NUM_CHANNELS-1:0] pn_oos,
|
||||
|
||||
output [NUM_CHANNELS-1:0] adc_valid,
|
||||
output [DMA_DATA_WIDTH-1:0] adc_data,
|
||||
|
||||
input adc_sync,
|
||||
output adc_sync_status,
|
||||
input adc_sync_in,
|
||||
output adc_rst_sync,
|
||||
|
||||
input link_valid,
|
||||
output link_ready,
|
||||
input [OCTETS_PER_BEAT-1:0] link_sof,
|
||||
input [LINK_DATA_WIDTH-1:0] link_data
|
||||
);
|
||||
// Raw and formatted channel data widths
|
||||
localparam CDW_RAW = CONVERTER_RESOLUTION * DATA_PATH_WIDTH;
|
||||
localparam ADC_DATA_WIDTH = CDW_RAW * NUM_CHANNELS;
|
||||
localparam CDW_FMT = BITS_PER_SAMPLE * DATA_PATH_WIDTH;
|
||||
|
||||
wire [ADC_DATA_WIDTH-1:0] raw_data_s;
|
||||
|
||||
reg adc_sync_armed = 1'b0;
|
||||
reg adc_sync_in_d1 = 1'b0;
|
||||
reg adc_sync_d1 = 1'b0;
|
||||
|
||||
assign link_ready = 1'b1;
|
||||
assign adc_valid = {NUM_CHANNELS{link_valid}};
|
||||
assign adc_sync_status = adc_sync_armed;
|
||||
assign adc_rst_sync = adc_sync_armed;
|
||||
|
||||
always @(posedge clk) begin
|
||||
adc_sync_in_d1 <= adc_sync_in;
|
||||
adc_sync_d1 <= adc_sync;
|
||||
if ((~adc_sync_d1 & adc_sync) == 1'b1) begin
|
||||
adc_sync_armed <= ~adc_sync_armed;
|
||||
end else if ((~adc_sync_in_d1 & adc_sync_in) == 1'b1) begin
|
||||
adc_sync_armed <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// synchronization logic
|
||||
|
||||
ad_ip_jesd204_tpl_adc_deframer #(
|
||||
.NUM_LANES (NUM_LANES),
|
||||
.NUM_CHANNELS (NUM_CHANNELS),
|
||||
.BITS_PER_SAMPLE (BITS_PER_SAMPLE),
|
||||
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
|
||||
.SAMPLES_PER_FRAME (SAMPLES_PER_FRAME),
|
||||
.OCTETS_PER_BEAT (OCTETS_PER_BEAT),
|
||||
.LINK_DATA_WIDTH (LINK_DATA_WIDTH),
|
||||
.ADC_DATA_WIDTH (ADC_DATA_WIDTH)
|
||||
) i_deframer (
|
||||
.clk (clk),
|
||||
.link_sof (link_sof),
|
||||
.link_data (link_data),
|
||||
.adc_data (raw_data_s)
|
||||
);
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel
|
||||
ad_ip_jesd204_tpl_adc_channel #(
|
||||
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
|
||||
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
|
||||
.TWOS_COMPLEMENT (TWOS_COMPLEMENT),
|
||||
.BITS_PER_SAMPLE (BITS_PER_SAMPLE)
|
||||
) i_channel (
|
||||
.clk (clk),
|
||||
|
||||
.raw_data (raw_data_s[CDW_RAW*i+:CDW_RAW]),
|
||||
.fmt_data (adc_data[CDW_FMT*i+:CDW_FMT]),
|
||||
|
||||
.dfmt_enable (dfmt_enable[i]),
|
||||
.dfmt_sign_extend (dfmt_sign_extend[i]),
|
||||
.dfmt_type (dfmt_type[i]),
|
||||
|
||||
.pn_seq_sel (pn_seq_sel[i*4+:4]),
|
||||
.pn_err (pn_err[i]),
|
||||
.pn_oos (pn_oos[i])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,119 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// Each core or library found in this collection may have its own licensing terms.
|
||||
// The user should keep this in in mind while exploring these cores.
|
||||
//
|
||||
// Redistribution and use in source and binary forms,
|
||||
// with or without modification of this file, are permitted under the terms of either
|
||||
// (at the option of the user):
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory, or at:
|
||||
// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module ad_ip_jesd204_tpl_adc_deframer #(
|
||||
parameter NUM_LANES = 1,
|
||||
parameter NUM_CHANNELS = 4,
|
||||
parameter BITS_PER_SAMPLE = 16,
|
||||
parameter CONVERTER_RESOLUTION = 14,
|
||||
parameter SAMPLES_PER_FRAME = 1,
|
||||
parameter OCTETS_PER_BEAT = 8,
|
||||
parameter LINK_DATA_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES,
|
||||
parameter ADC_DATA_WIDTH = LINK_DATA_WIDTH * CONVERTER_RESOLUTION / BITS_PER_SAMPLE
|
||||
) (
|
||||
// jesd interface
|
||||
// clk is (line-rate/40)
|
||||
|
||||
input clk,
|
||||
input [OCTETS_PER_BEAT-1:0] link_sof,
|
||||
input [LINK_DATA_WIDTH-1:0] link_data,
|
||||
|
||||
// adc data output
|
||||
|
||||
output [ADC_DATA_WIDTH-1:0] adc_data
|
||||
);
|
||||
|
||||
|
||||
localparam SAMPLES_PER_BEAT = ADC_DATA_WIDTH / CONVERTER_RESOLUTION;
|
||||
localparam BITS_PER_CHANNEL_PER_FRAME = BITS_PER_SAMPLE * SAMPLES_PER_FRAME;
|
||||
localparam BITS_PER_LANE_PER_FRAME = BITS_PER_CHANNEL_PER_FRAME *
|
||||
NUM_CHANNELS / NUM_LANES;
|
||||
localparam FRAMES_PER_BEAT = OCTETS_PER_BEAT * 8 / BITS_PER_LANE_PER_FRAME;
|
||||
|
||||
wire [LINK_DATA_WIDTH-1:0] link_data_s;
|
||||
wire [LINK_DATA_WIDTH-1:0] link_data_msb_s;
|
||||
wire [LINK_DATA_WIDTH-1:0] frame_data_s;
|
||||
wire [LINK_DATA_WIDTH-1:0] adc_data_msb;
|
||||
|
||||
// data multiplex
|
||||
|
||||
genvar i;
|
||||
genvar j;
|
||||
generate
|
||||
/* Reorder octets MSB first */
|
||||
for (i = 0; i < LINK_DATA_WIDTH; i = i + 8) begin: g_adc_data
|
||||
assign link_data_msb_s[i+:8] = link_data_s[LINK_DATA_WIDTH-1-i-:8];
|
||||
end
|
||||
|
||||
/* Slice lanes into frames */
|
||||
ad_perfect_shuffle #(
|
||||
.NUM_GROUPS (NUM_LANES),
|
||||
.WORDS_PER_GROUP (FRAMES_PER_BEAT),
|
||||
.WORD_WIDTH (BITS_PER_LANE_PER_FRAME)
|
||||
) i_lanes_to_frames (
|
||||
.data_in (link_data_msb_s),
|
||||
.data_out (frame_data_s)
|
||||
);
|
||||
|
||||
/* Slice frames into channels */
|
||||
ad_perfect_shuffle #(
|
||||
.NUM_GROUPS (FRAMES_PER_BEAT),
|
||||
.WORDS_PER_GROUP (NUM_CHANNELS),
|
||||
.WORD_WIDTH (BITS_PER_CHANNEL_PER_FRAME)
|
||||
) i_frames_to_channels (
|
||||
.data_in (frame_data_s),
|
||||
.data_out (adc_data_msb)
|
||||
);
|
||||
|
||||
/* Reorder samples LSB first and remove tail bits */
|
||||
for (i = 0; i < SAMPLES_PER_BEAT; i = i + 1) begin: g_dac_data_msb
|
||||
localparam src_w = BITS_PER_SAMPLE;
|
||||
localparam dst_w = CONVERTER_RESOLUTION;
|
||||
localparam src_msb = LINK_DATA_WIDTH - 1 - i * src_w ;
|
||||
localparam dst_lsb = i * dst_w;
|
||||
|
||||
assign adc_data[dst_lsb+:dst_w] = adc_data_msb[src_msb-:dst_w];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// frame-alignment
|
||||
|
||||
generate
|
||||
genvar n;
|
||||
for (n = 0; n < NUM_LANES; n = n + 1) begin: g_xcvr_if
|
||||
localparam DW = OCTETS_PER_BEAT * 8;
|
||||
ad_xcvr_rx_if #(
|
||||
.OCTETS_PER_BEAT (OCTETS_PER_BEAT)
|
||||
) i_xcvr_if (
|
||||
.rx_clk (clk),
|
||||
.rx_ip_sof (link_sof),
|
||||
.rx_ip_data (link_data[n*DW+:DW]),
|
||||
.rx_sof (),
|
||||
.rx_data (link_data_s[n*DW+:DW])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,268 @@
|
||||
# ***************************************************************************
|
||||
# ***************************************************************************
|
||||
# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
|
||||
#
|
||||
# Each core or library found in this collection may have its own licensing terms.
|
||||
# The user should keep this in in mind while exploring these cores.
|
||||
#
|
||||
# Redistribution and use in source and binary forms,
|
||||
# with or without modification of this file, are permitted under the terms of either
|
||||
# (at the option of the user):
|
||||
#
|
||||
# 1. The GNU General Public License version 2 as published by the
|
||||
# Free Software Foundation, which can be found in the top level directory, or at:
|
||||
# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
|
||||
#
|
||||
# OR
|
||||
#
|
||||
# 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
|
||||
# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
|
||||
#
|
||||
# ***************************************************************************
|
||||
# ***************************************************************************
|
||||
|
||||
package require qsys
|
||||
source ../../scripts/adi_env.tcl
|
||||
source ../../scripts/adi_ip_intel.tcl
|
||||
|
||||
ad_ip_create ad_ip_jesd204_tpl_adc "JESD204 Transport Layer for ADCs" p_ad_ip_jesd204_tpl_adc_elab
|
||||
set_module_property VALIDATION_CALLBACK p_ad_ip_jesd204_tpl_adc_validate
|
||||
ad_ip_files ad_ip_jesd204_tpl_adc [list \
|
||||
$ad_hdl_dir/library/common/ad_rst.v \
|
||||
$ad_hdl_dir/library/common/ad_perfect_shuffle.v \
|
||||
$ad_hdl_dir/library/common/ad_pnmon.v \
|
||||
$ad_hdl_dir/library/common/ad_datafmt.v \
|
||||
$ad_hdl_dir/library/common/up_axi.v \
|
||||
$ad_hdl_dir/library/common/up_xfer_cntrl.v \
|
||||
$ad_hdl_dir/library/common/up_xfer_status.v \
|
||||
$ad_hdl_dir/library/common/up_clock_mon.v \
|
||||
$ad_hdl_dir/library/common/up_adc_common.v \
|
||||
$ad_hdl_dir/library/common/up_adc_channel.v \
|
||||
$ad_hdl_dir/library/common/ad_xcvr_rx_if.v \
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v \
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v \
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v \
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v \
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v \
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v \
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v \
|
||||
$ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \
|
||||
$ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \
|
||||
$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
|
||||
$ad_hdl_dir/library/intel/common/up_rst_constr.sdc]
|
||||
|
||||
# parameters
|
||||
|
||||
set group "General Configuration"
|
||||
|
||||
ad_ip_parameter ID INTEGER 0 true [list \
|
||||
DISPLAY_NAME "Core ID" \
|
||||
GROUP $group \
|
||||
]
|
||||
|
||||
set group "JESD204 Deframer Configuration"
|
||||
|
||||
ad_ip_parameter NUM_LANES INTEGER 1 true [list \
|
||||
DISPLAY_NAME "Number of Lanes (L)" \
|
||||
DISPLAY_UNITS "lanes" \
|
||||
ALLOWED_RANGES {1 2 3 4 8} \
|
||||
GROUP $group \
|
||||
]
|
||||
|
||||
ad_ip_parameter NUM_CHANNELS INTEGER 1 true [list \
|
||||
DISPLAY_NAME "Number of Converters (M)" \
|
||||
DISPLAY_UNITS "converters" \
|
||||
ALLOWED_RANGES {1 2 4 6 8 16 32 64} \
|
||||
GROUP $group \
|
||||
]
|
||||
|
||||
ad_ip_parameter BITS_PER_SAMPLE INTEGER 16 true [list \
|
||||
DISPLAY_NAME "Bits per Sample (N')" \
|
||||
ALLOWED_RANGES {8 12 16} \
|
||||
UNITS bits \
|
||||
GROUP $group \
|
||||
]
|
||||
|
||||
ad_ip_parameter CONVERTER_RESOLUTION INTEGER 16 true [list \
|
||||
DISPLAY_NAME "Converter Resolution (N)" \
|
||||
ALLOWED_RANGES {8 11 12 16} \
|
||||
UNITS bits \
|
||||
GROUP $group \
|
||||
]
|
||||
|
||||
ad_ip_parameter ENABLE_SAMPLES_PER_FRAME_MANUAL BOOLEAN 0 false [list \
|
||||
DISPLAY_NAME "Manual Samples per Frame" \
|
||||
GROUP $group \
|
||||
]
|
||||
|
||||
ad_ip_parameter SAMPLES_PER_FRAME INTEGER 1 true [list \
|
||||
DISPLAY_NAME "Samples per Frame (S)" \
|
||||
DISPLAY_UNITS "samples" \
|
||||
ALLOWED_RANGES {1 2 3 4 6 8 12 16} \
|
||||
DERIVED true \
|
||||
GROUP $group \
|
||||
]
|
||||
|
||||
ad_ip_parameter SAMPLES_PER_FRAME_MANUAL INTEGER 1 false [list \
|
||||
DISPLAY_NAME "Samples per Frame (S)" \
|
||||
DISPLAY_UNITS "samples" \
|
||||
ALLOWED_RANGES {1 2 3 4 6 8 12 16} \
|
||||
VISIBLE false \
|
||||
GROUP $group \
|
||||
]
|
||||
|
||||
ad_ip_parameter OCTETS_PER_FRAME INTEGER 1 false [list \
|
||||
DISPLAY_NAME "Octets per Frame (F)" \
|
||||
DISPLAY_UNITS "octets" \
|
||||
ALLOWED_RANGES {1 2 4 8 12 16} \
|
||||
DERIVED true \
|
||||
GROUP $group \
|
||||
]
|
||||
|
||||
set group "Deframer Output Information"
|
||||
|
||||
# Parameters in this group are informative only and can be read back after the
|
||||
# core has been configured to find out the expected layout of the input data.
|
||||
# E.g.
|
||||
# set NUM_OF_CHANNELS [get_instance_parameter_value jesd204_transport NUM_CHANNELS]
|
||||
# set CHANNEL_DATA_WIDTH [get_instance_parameter_value jesd204_transport CHANNEL_DATA_WIDTH]
|
||||
#
|
||||
# add_instance util_adc_cpack util_cpack
|
||||
# set_instance_parameter_values util_adc_cpack [list \
|
||||
# CHANNEL_DATA_WIDTH $CHANNEL_DATA_WIDTH \
|
||||
# NUM_OF_CHANNELS $NUM_OF_CHANNELS \
|
||||
# ]
|
||||
|
||||
ad_ip_parameter SAMPLES_PER_CHANNEL INTEGER 1 false [list \
|
||||
DISPLAY_NAME "Samples per Channel per Beat" \
|
||||
DERIVED true \
|
||||
GROUP $group \
|
||||
]
|
||||
|
||||
ad_ip_parameter CHANNEL_DATA_WIDTH INTEGER 1 false [list \
|
||||
DISPLAY_NAME "Channel Data Width" \
|
||||
UNITS bits \
|
||||
DERIVED true \
|
||||
GROUP $group \
|
||||
]
|
||||
|
||||
set group "Datapath Configuration"
|
||||
|
||||
ad_ip_parameter TWOS_COMPLEMENT boolean 1 true [list \
|
||||
DISPLAY_NAME "Twos Complement" \
|
||||
GROUP $group \
|
||||
]
|
||||
|
||||
|
||||
# axi4 slave
|
||||
|
||||
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12
|
||||
|
||||
# core clock and start of frame
|
||||
|
||||
add_interface link_clk clock end
|
||||
add_interface_port link_clk link_clk clk Input 1
|
||||
ad_interface signal link_sof input 4 export
|
||||
|
||||
# We don't expect too large values for a and b, trivial implementation will do
|
||||
proc gcd {a b} {
|
||||
if {$a == $b} {
|
||||
return $b
|
||||
} elseif {$a > $b} {
|
||||
return [gcd [expr $a - $b] $b]
|
||||
} else {
|
||||
return [gcd $a [expr $b - $a]]
|
||||
}
|
||||
}
|
||||
|
||||
# validate
|
||||
|
||||
proc p_ad_ip_jesd204_tpl_adc_validate {} {
|
||||
set L [get_parameter_value "NUM_LANES"]
|
||||
set M [get_parameter_value "NUM_CHANNELS"]
|
||||
set NP [get_parameter_value "BITS_PER_SAMPLE"]
|
||||
set N [get_parameter_value "CONVERTER_RESOLUTION"]
|
||||
set S_manual [get_parameter_value "SAMPLES_PER_FRAME_MANUAL"]
|
||||
set enable_S_manual [get_parameter_value "ENABLE_SAMPLES_PER_FRAME_MANUAL"]
|
||||
|
||||
# With fixed values for M, L and N' all valid values for S and F have a
|
||||
# constant ratio of S / F. Choose a ratio so that S and F are co-prime.
|
||||
# Choosing values for F and S that have a common factor has higher latency
|
||||
# and no added benefits.
|
||||
#
|
||||
# Since converters often support those higher latency modes still allow a
|
||||
# manual override of the S parameter in case somebody wants to use those modes
|
||||
# anyway.
|
||||
#
|
||||
# To be able to set samples per frame manually ENABLE_SAMPLES_PER_FRAME_MANUAL
|
||||
# needs to be set to true and SAMPLES_PER_FRAME_MANUAL to the desired value.
|
||||
#
|
||||
# When manual sample per frame selection is enabled still verify that the
|
||||
# selected value is valid.
|
||||
|
||||
set S_min [expr $L * 8]
|
||||
set F_min [expr $M * $NP]
|
||||
set common_factor [gcd $S_min $F_min]
|
||||
set S_min [expr $S_min / $common_factor]
|
||||
set F_min [expr $F_min / $common_factor]
|
||||
|
||||
if {$enable_S_manual} {
|
||||
if {$S_manual % $S_min != 0} {
|
||||
send_message ERROR "For framer configuration (L=$L, M=$M, NP=$NP) samples per frame (S) must be an integer multiple of $S_min"
|
||||
set S $S_min
|
||||
set F $F_min
|
||||
} else {
|
||||
set S $S_manual
|
||||
set F [expr $S_manual * $M * $NP / $L / 8]
|
||||
}
|
||||
} else {
|
||||
set S $S_min
|
||||
set F $F_min
|
||||
}
|
||||
|
||||
set_parameter_value OCTETS_PER_FRAME $F
|
||||
set_parameter_value SAMPLES_PER_FRAME $S
|
||||
|
||||
set_parameter_property SAMPLES_PER_FRAME VISIBLE [expr !$enable_S_manual]
|
||||
set_parameter_property SAMPLES_PER_FRAME_MANUAL VISIBLE $enable_S_manual
|
||||
|
||||
set_parameter_value SAMPLES_PER_CHANNEL [expr 4 * $S / $F]
|
||||
set_parameter_value CHANNEL_DATA_WIDTH [expr 16 * (4 * $S / $F)]
|
||||
|
||||
}
|
||||
|
||||
# elaborate
|
||||
|
||||
proc p_ad_ip_jesd204_tpl_adc_elab {} {
|
||||
|
||||
# read core parameters
|
||||
|
||||
set m_num_of_lanes [get_parameter_value "NUM_LANES"]
|
||||
set m_num_of_channels [get_parameter_value "NUM_CHANNELS"]
|
||||
set channel_bus_witdh [expr 32*$m_num_of_lanes/$m_num_of_channels]
|
||||
|
||||
# link layer interface
|
||||
|
||||
add_interface link_data avalon_streaming sink
|
||||
add_interface_port link_data link_data data input [expr 32*$m_num_of_lanes]
|
||||
add_interface_port link_data link_valid valid input 1
|
||||
add_interface_port link_data link_ready ready output 1
|
||||
set_interface_property link_data associatedClock link_clk
|
||||
set_interface_property link_data dataBitsPerSymbol [expr 32*$m_num_of_lanes]
|
||||
|
||||
# dma interface
|
||||
|
||||
for {set i 0} {$i < $m_num_of_channels} {incr i} {
|
||||
add_interface adc_ch_$i conduit end
|
||||
add_interface_port adc_ch_$i adc_enable_$i enable output 1
|
||||
set_port_property adc_enable_$i fragment_list [format "enable(%d:%d)" $i $i]
|
||||
add_interface_port adc_ch_$i adc_valid_$i valid output 1
|
||||
set_port_property adc_valid_$i fragment_list [format "adc_valid(%d:%d)" $i $i]
|
||||
add_interface_port adc_ch_$i adc_data_$i data output $channel_bus_witdh
|
||||
set_port_property adc_data_$i fragment_list \
|
||||
[format "adc_data(%d:%d)" [expr $channel_bus_witdh*$i+$channel_bus_witdh-1] [expr $channel_bus_witdh*$i]]
|
||||
set_interface_property adc_ch_$i associatedClock link_clk
|
||||
}
|
||||
|
||||
ad_interface signal adc_dovf input 1 ovf
|
||||
}
|
||||
@@ -0,0 +1,833 @@
|
||||
|
||||
****** Vivado v2019.1.3 (64-bit)
|
||||
**** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
**** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
source ad_ip_jesd204_tpl_adc_ip.tcl
|
||||
# source ../../scripts/adi_env.tcl
|
||||
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
|
||||
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
|
||||
## if [info exists ::env(ADI_HDL_DIR)] {
|
||||
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
|
||||
## }
|
||||
## if [info exists ::env(ADI_GHDL_DIR)] {
|
||||
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
|
||||
## }
|
||||
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
|
||||
### variable auto_set_param_list
|
||||
### variable auto_set_param_list_overwritable
|
||||
### variable fpga_series_list
|
||||
### variable fpga_family_list
|
||||
### variable speed_grade_list
|
||||
### variable dev_package_list
|
||||
### variable xcvr_type_list
|
||||
### variable fpga_voltage_list
|
||||
### set auto_set_param_list { \
|
||||
### DEV_PACKAGE \
|
||||
### SPEED_GRADE \
|
||||
### FPGA_FAMILY \
|
||||
### FPGA_TECHNOLOGY }
|
||||
### set auto_set_param_list_overwritable { \
|
||||
### FPGA_VOLTAGE \
|
||||
### XCVR_TYPE }
|
||||
### set fpga_technology_list { \
|
||||
### { Unknown 0 } \
|
||||
### { 7series 1 } \
|
||||
### { ultrascale 2 } \
|
||||
### { ultrascale+ 3 }}
|
||||
### set fpga_family_list { \
|
||||
### { Unknown 0 } \
|
||||
### { artix 1 } \
|
||||
### { kintex 2 } \
|
||||
### { virtex 3 } \
|
||||
### { zynq 4 }}
|
||||
### set speed_grade_list { \
|
||||
### { Unknown 0 } \
|
||||
### { -1 10 } \
|
||||
### { -1L 11 } \
|
||||
### { -1H 12 } \
|
||||
### { -1HV 13 } \
|
||||
### { -1LV 14 } \
|
||||
### { -2 20 } \
|
||||
### { -2L 21 } \
|
||||
### { -2LV 22 } \
|
||||
### { -3 30 }}
|
||||
### set dev_package_list { \
|
||||
### { Unknown 0 } \
|
||||
### { rf 1 } \
|
||||
### { fl 2 } \
|
||||
### { ff 3 } \
|
||||
### { fb 4 } \
|
||||
### { hc 5 } \
|
||||
### { fh 6 } \
|
||||
### { cs 7 } \
|
||||
### { cp 8 } \
|
||||
### { ft 9 } \
|
||||
### { fg 10 } \
|
||||
### { sb 11 } \
|
||||
### { rb 12 } \
|
||||
### { rs 13 } \
|
||||
### { cl 14 } \
|
||||
### { sf 15 } \
|
||||
### { ba 16 } \
|
||||
### { fa 17 } \
|
||||
### { fs 18 } \
|
||||
### { fi 19 }}
|
||||
### set xcvr_type_list { \
|
||||
### { Unknown 0 } \
|
||||
### { GTPE2_NOT_SUPPORTED 1 } \
|
||||
### { GTXE2 2 } \
|
||||
### { GTHE2_NOT_SUPPORTED 3 } \
|
||||
### { GTZE2_NOT_SUPPORTED 4 } \
|
||||
### { GTHE3 5 } \
|
||||
### { GTYE3_NOT_SUPPORTED 6 } \
|
||||
### { GTRE4_NOT_SUPPORTED 7 } \
|
||||
### { GTHE4 8 } \
|
||||
### { GTYE4 9 } \
|
||||
### { GTME4_NOT_SUPPORTED 10}}
|
||||
### set fpga_voltage_list {0 5000} ;
|
||||
### proc adi_device_spec {cellpath param} {
|
||||
###
|
||||
### set list_pointer [string tolower $param]
|
||||
### set list_pointer [append list_pointer "_list"]
|
||||
###
|
||||
### upvar 1 $list_pointer $list_pointer
|
||||
###
|
||||
### set ip [get_bd_cells $cellpath]
|
||||
### set part [get_property PART [current_project]]
|
||||
###
|
||||
### switch -regexp -- $param {
|
||||
### FPGA_TECHNOLOGY {
|
||||
### switch -regexp -- $part {
|
||||
### ^xc7 {set series_name 7series}
|
||||
### ^xczu {set series_name ultrascale+}
|
||||
### ^xc.u.p {set series_name ultrascale+}
|
||||
### ^xc.u {set series_name ultrascale }
|
||||
### default {
|
||||
### puts "Undefined fpga technology for \"$part\"!"
|
||||
### exit -1
|
||||
### }
|
||||
### }
|
||||
### return "$series_name"
|
||||
### }
|
||||
### FPGA_FAMILY {
|
||||
### set fpga_family [get_property FAMILY $part]
|
||||
### foreach i $fpga_family_list {
|
||||
### regexp ^[lindex $i 0] $fpga_family matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### SPEED_GRADE {
|
||||
### set speed_grade [get_property SPEED $part]
|
||||
### return "$speed_grade"
|
||||
### }
|
||||
### DEV_PACKAGE {
|
||||
### set dev_package [get_property PACKAGE $part]
|
||||
### foreach i $dev_package_list {
|
||||
### regexp ^[lindex $i 0] $dev_package matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### XCVR_TYPE {
|
||||
### set matched ""
|
||||
### set dev_transcivers "none"
|
||||
### foreach x [list_property $part] {
|
||||
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
|
||||
### }
|
||||
### foreach i $xcvr_type_list {
|
||||
### regexp ^[lindex $i 0] $dev_transcivers matched
|
||||
### }
|
||||
### if { $matched eq "" } {
|
||||
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### FPGA_VOLTAGE {
|
||||
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
|
||||
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
|
||||
###
|
||||
### return "$fpga_voltage"
|
||||
### }
|
||||
### default {
|
||||
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
|
||||
### }
|
||||
### }
|
||||
### }
|
||||
## if {![info exists REQUIRED_VIVADO_VERSION]} {
|
||||
## set REQUIRED_VIVADO_VERSION "2019.1"
|
||||
## }
|
||||
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
|
||||
## set IGNORE_VERSION_CHECK 1
|
||||
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
|
||||
## set IGNORE_VERSION_CHECK 0
|
||||
## }
|
||||
## proc adi_ip_ttcl {ip_name ip_constr_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
|
||||
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_sim_ttcl {ip_name ip_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
|
||||
## set f [ipx::add_file $ip_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_bd {ip_name ip_bd_files} {
|
||||
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
|
||||
## if {$proj_filegroup == {}} {
|
||||
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
|
||||
## }
|
||||
##
|
||||
## foreach file $ip_bd_files {
|
||||
## set f [ipx::add_file $file $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type tclSource \
|
||||
## ] $f
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_infer_streaming_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_ip_infer_mm_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
|
||||
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency $port
|
||||
## if {$driver_value != {}} {
|
||||
## set_property DRIVER_VALUE $driver_value $port
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_set_bus_dependency {bus prefix dependency} {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
|
||||
## adi_set_ports_dependency $prefix $dependency 0
|
||||
## }
|
||||
## proc adi_add_port_map {bus phys logic} {
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## }
|
||||
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## adi_add_port_map $bus {*}$port_map
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
|
||||
## for {set i 0} {$i < $num} {incr i} {
|
||||
## set bus_name [format "%s%d" $bus_name_prefix $i]
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## if {$dependency ne ""} {
|
||||
## set bus_dependency [string map [list "{i}" $i] $dependency]
|
||||
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
|
||||
## }
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## lassign $port_map phys logic width width_dep
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
|
||||
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
|
||||
## if {$width_dep ne ""} {
|
||||
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
|
||||
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
|
||||
## set width_dep_r "(($width_dep) * $i)"
|
||||
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
|
||||
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
|
||||
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
|
||||
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
|
||||
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
|
||||
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
|
||||
## set_property display_name $clock_inf_name $clock_inf
|
||||
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
|
||||
## set_property physical_name $clock_signal_name $clock_map
|
||||
##
|
||||
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
|
||||
## set_property value $bus_inf_name $assoc_busif
|
||||
##
|
||||
## if { $reset_signal_name != "" } {
|
||||
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
|
||||
## set_property value $reset_signal_name $assoc_reset
|
||||
##
|
||||
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
|
||||
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
|
||||
## set_property display_name $reset_inf_name $reset_inf
|
||||
## set_property interface_mode $reset_signal_mode $reset_inf
|
||||
## set reset_map [ipx::add_port_map "RST" $reset_inf]
|
||||
## set_property physical_name $reset_signal_name $reset_map
|
||||
##
|
||||
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
|
||||
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
|
||||
## set_property value "ACTIVE_LOW" $reset_polarity
|
||||
## } else {
|
||||
## set_property value "ACTIVE_HIGH" $reset_polarity
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_add_core_dependencies {vlnvs} {
|
||||
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
|
||||
## foreach vlnv $vlnvs {
|
||||
## ipx::add_subcore $vlnv $file_group
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_create {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
## global ad_ghdl_dir
|
||||
## global REQUIRED_VIVADO_VERSION
|
||||
## global IGNORE_VERSION_CHECK
|
||||
##
|
||||
## set VIVADO_VERSION [version -short]
|
||||
## if {$IGNORE_VERSION_CHECK} {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## }
|
||||
## } else {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "ERROR: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
|
||||
## exit 2
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## create_project $ip_name . -force
|
||||
##
|
||||
## ## Load custom message severity definitions
|
||||
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
|
||||
##
|
||||
## set lib_dirs $ad_hdl_dir/library
|
||||
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
|
||||
## lappend lib_dirs $ad_ghdl_dir/library
|
||||
## }
|
||||
##
|
||||
## set_property ip_repo_paths $lib_dirs [current_fileset]
|
||||
## update_ip_catalog
|
||||
## }
|
||||
## proc adi_ip_files {ip_name ip_files} {
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## foreach m_file $ip_files {
|
||||
## if {[file extension $m_file] eq ".xdc"} {
|
||||
## add_files -norecurse -fileset constrs_1 $m_file
|
||||
## } else {
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
|
||||
## }
|
||||
## }
|
||||
## set_property "top" "$ip_name" $proj_fileset
|
||||
## }
|
||||
## proc adi_ip_properties_lite {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
##
|
||||
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
|
||||
##
|
||||
## set_property name $ip_name [ipx::current_core]
|
||||
##
|
||||
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
|
||||
## set_property company_url {http://www.analog.com} [ipx::current_core]
|
||||
##
|
||||
## set i_families ""
|
||||
## foreach i_part [get_parts] {
|
||||
## lappend i_families [get_property FAMILY $i_part]
|
||||
## }
|
||||
## set i_families [lsort -unique $i_families]
|
||||
## set s_families [get_property supported_families [ipx::current_core]]
|
||||
## foreach i_family $i_families {
|
||||
## set s_families "$s_families $i_family Production"
|
||||
## set s_families "$s_families $i_family Beta"
|
||||
## }
|
||||
## set_property supported_families $s_families [ipx::current_core]
|
||||
##
|
||||
## ipx::save_core [ipx::current_core]
|
||||
##
|
||||
## ipx::remove_all_bus_interface [ipx::current_core]
|
||||
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
|
||||
## foreach map $memory_maps {
|
||||
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
|
||||
## }
|
||||
##
|
||||
## ipx::update_checksums [ipx::current_core]
|
||||
## ipx::save_core [ipx::current_core]
|
||||
## }
|
||||
## proc adi_ip_properties {ip_name} {
|
||||
##
|
||||
## adi_ip_properties_lite $ip_name
|
||||
##
|
||||
## ipx::infer_bus_interface {\
|
||||
## s_axi_awvalid \
|
||||
## s_axi_awaddr \
|
||||
## s_axi_awprot \
|
||||
## s_axi_awready \
|
||||
## s_axi_wvalid \
|
||||
## s_axi_wdata \
|
||||
## s_axi_wstrb \
|
||||
## s_axi_wready \
|
||||
## s_axi_bvalid \
|
||||
## s_axi_bresp \
|
||||
##
|
||||
## s_axi_bready \
|
||||
## s_axi_arvalid \
|
||||
## s_axi_araddr \
|
||||
## s_axi_arprot \
|
||||
## s_axi_arready \
|
||||
## s_axi_rvalid \
|
||||
## s_axi_rdata \
|
||||
## s_axi_rresp \
|
||||
## s_axi_rready} \
|
||||
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
|
||||
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
|
||||
##
|
||||
## if {$raddr_width != $waddr_width} {
|
||||
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
|
||||
## set range 65536
|
||||
## } else {
|
||||
## if {$raddr_width >= 16} {
|
||||
## set range 65536
|
||||
## } else {
|
||||
## set range [expr 1 << $raddr_width]
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
## set_property range $range [ipx::get_address_blocks axi_lite \
|
||||
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
|
||||
## ipx::save_core
|
||||
## }
|
||||
## proc adi_init_bd_tcl {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## if { [file exists bd] } {
|
||||
## file delete -force bd
|
||||
## }
|
||||
## file mkdir bd
|
||||
##
|
||||
## set bd_tcl [open "bd/bd.tcl" w]
|
||||
##
|
||||
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
|
||||
## puts $bd_tcl "proc init {cellpath otherInfo} {"
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl ""
|
||||
## set auto_set_param ""
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
|
||||
## puts $bd_tcl $auto_set_param
|
||||
## }
|
||||
##
|
||||
## set auto_set_overwritable_param ""
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_overwritable_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_overwritable_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
|
||||
## puts $bd_tcl $auto_set_overwritable_param
|
||||
## }
|
||||
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
|
||||
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
|
||||
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set parent_dir \"../\""
|
||||
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
|
||||
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
|
||||
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " break"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " append parent_dir \"../\""
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## close $bd_tcl
|
||||
##
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
|
||||
##
|
||||
## set local_mk [open "temporary_case_dependencies.mk" w]
|
||||
## seek $local_mk 0 start
|
||||
## puts $local_mk "CLEAN_TARGET += bd"
|
||||
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
|
||||
## close $local_mk
|
||||
## }
|
||||
## proc adi_add_auto_fpga_spec_params {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_device_spec_param {ip_param} {
|
||||
##
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## set list_pointer [string tolower $ip_param]
|
||||
## set list_pointer [append list_pointer "_list"]
|
||||
##
|
||||
## global $list_pointer
|
||||
##
|
||||
## # set j 1D list from the original list
|
||||
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
|
||||
##
|
||||
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
|
||||
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "range_long" \
|
||||
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
|
||||
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## } else {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "pairs" \
|
||||
## "value_validation_pairs" $j ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## }
|
||||
##
|
||||
## # FPGA info grup
|
||||
## set info_group_name "FPGA info"
|
||||
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
|
||||
## if { [string trim $info_group] eq "" } {
|
||||
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
|
||||
## -parent $page0 -display_name $info_group_name]
|
||||
## }
|
||||
##
|
||||
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
|
||||
## set_property -dict [list "widget" "comboBox" ] $p
|
||||
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
|
||||
## }
|
||||
## proc adi_if_define {name} {
|
||||
##
|
||||
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
|
||||
## ipx::create_bus_definition analog.com interface $name 1.0
|
||||
##
|
||||
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
|
||||
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
|
||||
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
|
||||
##
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## }
|
||||
## proc adi_if_ports {dir width name {type none}} {
|
||||
##
|
||||
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
|
||||
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
|
||||
## set_property master_presence required $m_intf
|
||||
## set_property slave_presence required $m_intf
|
||||
## set_property master_width $width $m_intf
|
||||
## set_property slave_width $width $m_intf
|
||||
##
|
||||
## set m_dir "in"
|
||||
## set s_dir "out"
|
||||
## if {$dir eq "output"} {
|
||||
## set m_dir "out"
|
||||
## set s_dir "in"
|
||||
## }
|
||||
##
|
||||
## set_property master_direction $m_dir $m_intf
|
||||
## set_property slave_direction $s_dir $m_intf
|
||||
##
|
||||
## if {$type ne "none"} {
|
||||
## set_property is_${type} true $m_intf
|
||||
## }
|
||||
##
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## }
|
||||
## proc adi_if_infer_bus {if_name mode name maps} {
|
||||
##
|
||||
## ipx::add_bus_interface $name [ipx::current_core]
|
||||
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
|
||||
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
|
||||
## set_property interface_mode $mode $m_bus_if
|
||||
##
|
||||
## foreach map $maps {
|
||||
## set m_maps [regexp -all -inline {\S+} $map]
|
||||
## lassign $m_maps p_name p_map
|
||||
## ipx::add_port_map $p_name $m_bus_if
|
||||
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
|
||||
## }
|
||||
## }
|
||||
# adi_ip_create ad_ip_jesd204_tpl_adc
|
||||
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
|
||||
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1343} -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1306} -new_severity WARNING
|
||||
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
|
||||
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
|
||||
## set_msg_config -id {Synth 8-3331} -new_severity INFO
|
||||
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
|
||||
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
|
||||
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
|
||||
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'.)
|
||||
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
|
||||
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
|
||||
# adi_ip_files ad_ip_jesd204_tpl_adc [list \
|
||||
# "$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
# "$ad_hdl_dir/library/common/ad_perfect_shuffle.v" \
|
||||
# "$ad_hdl_dir/library/common/ad_pnmon.v" \
|
||||
# "$ad_hdl_dir/library/common/ad_datafmt.v" \
|
||||
# "$ad_hdl_dir/library/common/up_axi.v" \
|
||||
# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||
# "$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
# "$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
# "$ad_hdl_dir/library/common/up_adc_common.v" \
|
||||
# "$ad_hdl_dir/library/common/up_adc_channel.v" \
|
||||
# "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
|
||||
# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
|
||||
# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
|
||||
# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
|
||||
# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
|
||||
# "../ad_ip_jesd204_tpl_common/up_tpl_common.v" \
|
||||
# "ad_ip_jesd204_tpl_adc_core.v" \
|
||||
# "ad_ip_jesd204_tpl_adc_channel.v" \
|
||||
# "ad_ip_jesd204_tpl_adc_deframer.v" \
|
||||
# "ad_ip_jesd204_tpl_adc_pnmon.v" \
|
||||
# "ad_ip_jesd204_tpl_adc_regmap.v" \
|
||||
# "ad_ip_jesd204_tpl_adc.v" \
|
||||
# ]
|
||||
# adi_ip_properties ad_ip_jesd204_tpl_adc
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
WARNING: [IP_Flow 19-5150] The Range '(((NUM_LANES * 8) * OCTETS_PER_BEAT) - 1):0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5150] The Range '(((NUM_LANES * 8) * OCTETS_PER_BEAT) - 1):0' is present in all ports of the interface 'link'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'adc' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'link' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5150] The Range '(NUM_CHANNELS - 1):0' is present in all ports of the interface 'interface_spi_engine_offload_ctrl'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'link_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'link': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'link_clk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
||||
# adi_init_bd_tcl
|
||||
# adi_ip_bd ad_ip_jesd204_tpl_adc "bd/bd.tcl"
|
||||
# set cc [ipx::current_core]
|
||||
# set_property display_name "JESD204 Transport Layer for ADCs" $cc
|
||||
# set_property description "JESD204 Transport Layer for ADCs" $cc
|
||||
# adi_add_bus "link" "master" \
|
||||
# "xilinx.com:interface:axis_rtl:1.0" \
|
||||
# "xilinx.com:interface:axis:1.0" \
|
||||
# [list \
|
||||
# {"link_ready" "TREADY"} \
|
||||
# {"link_valid" "TVALID"} \
|
||||
# {"link_data" "TDATA"} \
|
||||
# ]
|
||||
# adi_add_bus_clock "link_clk" "link"
|
||||
# foreach {p v} {
|
||||
# "NUM_LANES" "1 2 3 4 8 16" \
|
||||
# "NUM_CHANNELS" "1 2 4 6 8 16 32 64" \
|
||||
# "BITS_PER_SAMPLE" "8 12 16" \
|
||||
# "CONVERTER_RESOLUTION" "8 11 12 16" \
|
||||
# "SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \
|
||||
# "OCTETS_PER_BEAT" "4 8" \
|
||||
# } { \
|
||||
# set_property -dict [list \
|
||||
# "value_validation_type" "list" \
|
||||
# "value_validation_list" $v \
|
||||
# ] [ipx::get_user_parameters $p -of_objects $cc]
|
||||
# }
|
||||
# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
# set general_group [ipgui::add_group -name "General Configuration" -component $cc \
|
||||
# -parent $page0 -display_name "General Configuration"]
|
||||
# set p [ipgui::get_guiparamspec -name "ID" -component $cc]
|
||||
# ipgui::move_param -component $cc -order 0 $p -parent $general_group
|
||||
# set_property -dict [list \
|
||||
# "display_name" "Core ID" \
|
||||
# ] $p
|
||||
# set framer_group [ipgui::add_group -name "JESD204 Deframer Configuration" -component $cc \
|
||||
# -parent $page0 -display_name "JESD204 Deframer Cofiguration"]
|
||||
# set i 0
|
||||
# foreach {k v} { \
|
||||
# "NUM_LANES" "Number of Lanes (L)" \
|
||||
# "NUM_CHANNELS" "Number of Conveters (M)" \
|
||||
# "BITS_PER_SAMPLE" "Bits per Sample (N')" \
|
||||
# "CONVERTER_RESOLUTION" "Converter Resolution (N)" \
|
||||
# "SAMPLES_PER_FRAME" "Samples per Frame (S)" \
|
||||
# "OCTETS_PER_BEAT" "Octets per Beat" \
|
||||
# } { \
|
||||
# set p [ipgui::get_guiparamspec -name $k -component $cc]
|
||||
# ipgui::move_param -component $cc -order $i $p -parent $framer_group
|
||||
# set_property -dict [list \
|
||||
# WIDGET "comboBox" \
|
||||
# DISPLAY_NAME $v \
|
||||
# ] $p
|
||||
# incr i
|
||||
# }
|
||||
# set datapath_group [ipgui::add_group -name "Datapath Configuration" -component $cc \
|
||||
# -parent $page0 -display_name "Datapath Cofiguration"]
|
||||
# set i 0
|
||||
# foreach {k v w} {
|
||||
# "TWOS_COMPLEMENT" "Use twos complement" "checkBox" \
|
||||
# } { \
|
||||
# set p [ipgui::get_guiparamspec -name $k -component $cc]
|
||||
# ipgui::move_param -component $cc -order $i $p -parent $datapath_group
|
||||
# set_property -dict [list \
|
||||
# WIDGET $w \
|
||||
# DISPLAY_NAME $v \
|
||||
# ] $p
|
||||
# incr i
|
||||
# }
|
||||
# adi_add_auto_fpga_spec_params
|
||||
# ipx::create_xgui_files [ipx::current_core]
|
||||
# ipx::save_core [ipx::current_core]
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:24:32 2021...
|
||||
@@ -0,0 +1,140 @@
|
||||
# ***************************************************************************
|
||||
# ***************************************************************************
|
||||
# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
|
||||
#
|
||||
# Each core or library found in this collection may have its own licensing terms.
|
||||
# The user should keep this in in mind while exploring these cores.
|
||||
#
|
||||
# Redistribution and use in source and binary forms,
|
||||
# with or without modification of this file, are permitted under the terms of either
|
||||
# (at the option of the user):
|
||||
#
|
||||
# 1. The GNU General Public License version 2 as published by the
|
||||
# Free Software Foundation, which can be found in the top level directory, or at:
|
||||
# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
|
||||
#
|
||||
# OR
|
||||
#
|
||||
# 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
|
||||
# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
|
||||
#
|
||||
# ***************************************************************************
|
||||
# ***************************************************************************
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create ad_ip_jesd204_tpl_adc
|
||||
adi_ip_files ad_ip_jesd204_tpl_adc [list \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/common/ad_perfect_shuffle.v" \
|
||||
"$ad_hdl_dir/library/common/ad_pnmon.v" \
|
||||
"$ad_hdl_dir/library/common/ad_datafmt.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
"$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
"$ad_hdl_dir/library/common/up_adc_common.v" \
|
||||
"$ad_hdl_dir/library/common/up_adc_channel.v" \
|
||||
"$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
|
||||
"../ad_ip_jesd204_tpl_common/up_tpl_common.v" \
|
||||
"ad_ip_jesd204_tpl_adc_core.v" \
|
||||
"ad_ip_jesd204_tpl_adc_channel.v" \
|
||||
"ad_ip_jesd204_tpl_adc_deframer.v" \
|
||||
"ad_ip_jesd204_tpl_adc_pnmon.v" \
|
||||
"ad_ip_jesd204_tpl_adc_regmap.v" \
|
||||
"ad_ip_jesd204_tpl_adc.v" \
|
||||
]
|
||||
|
||||
adi_ip_properties ad_ip_jesd204_tpl_adc
|
||||
|
||||
adi_init_bd_tcl
|
||||
adi_ip_bd ad_ip_jesd204_tpl_adc "bd/bd.tcl"
|
||||
|
||||
set cc [ipx::current_core]
|
||||
|
||||
set_property display_name "JESD204 Transport Layer for ADCs" $cc
|
||||
set_property description "JESD204 Transport Layer for ADCs" $cc
|
||||
|
||||
adi_add_bus "link" "master" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
[list \
|
||||
{"link_ready" "TREADY"} \
|
||||
{"link_valid" "TVALID"} \
|
||||
{"link_data" "TDATA"} \
|
||||
]
|
||||
adi_add_bus_clock "link_clk" "link"
|
||||
|
||||
foreach {p v} {
|
||||
"NUM_LANES" "1 2 3 4 8 16" \
|
||||
"NUM_CHANNELS" "1 2 4 6 8 16 32 64" \
|
||||
"BITS_PER_SAMPLE" "8 12 16" \
|
||||
"CONVERTER_RESOLUTION" "8 11 12 16" \
|
||||
"SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \
|
||||
"OCTETS_PER_BEAT" "4 8" \
|
||||
} { \
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "list" \
|
||||
"value_validation_list" $v \
|
||||
] [ipx::get_user_parameters $p -of_objects $cc]
|
||||
}
|
||||
|
||||
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
|
||||
set general_group [ipgui::add_group -name "General Configuration" -component $cc \
|
||||
-parent $page0 -display_name "General Configuration"]
|
||||
|
||||
set p [ipgui::get_guiparamspec -name "ID" -component $cc]
|
||||
ipgui::move_param -component $cc -order 0 $p -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Core ID" \
|
||||
] $p
|
||||
|
||||
set framer_group [ipgui::add_group -name "JESD204 Deframer Configuration" -component $cc \
|
||||
-parent $page0 -display_name "JESD204 Deframer Cofiguration"]
|
||||
|
||||
set i 0
|
||||
|
||||
foreach {k v} { \
|
||||
"NUM_LANES" "Number of Lanes (L)" \
|
||||
"NUM_CHANNELS" "Number of Conveters (M)" \
|
||||
"BITS_PER_SAMPLE" "Bits per Sample (N')" \
|
||||
"CONVERTER_RESOLUTION" "Converter Resolution (N)" \
|
||||
"SAMPLES_PER_FRAME" "Samples per Frame (S)" \
|
||||
"OCTETS_PER_BEAT" "Octets per Beat" \
|
||||
} { \
|
||||
set p [ipgui::get_guiparamspec -name $k -component $cc]
|
||||
ipgui::move_param -component $cc -order $i $p -parent $framer_group
|
||||
set_property -dict [list \
|
||||
WIDGET "comboBox" \
|
||||
DISPLAY_NAME $v \
|
||||
] $p
|
||||
incr i
|
||||
}
|
||||
|
||||
set datapath_group [ipgui::add_group -name "Datapath Configuration" -component $cc \
|
||||
-parent $page0 -display_name "Datapath Cofiguration"]
|
||||
|
||||
set i 0
|
||||
|
||||
foreach {k v w} {
|
||||
"TWOS_COMPLEMENT" "Use twos complement" "checkBox" \
|
||||
} { \
|
||||
set p [ipgui::get_guiparamspec -name $k -component $cc]
|
||||
ipgui::move_param -component $cc -order $i $p -parent $datapath_group
|
||||
set_property -dict [list \
|
||||
WIDGET $w \
|
||||
DISPLAY_NAME $v \
|
||||
] $p
|
||||
incr i
|
||||
}
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,121 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// Each core or library found in this collection may have its own licensing terms.
|
||||
// The user should keep this in in mind while exploring these cores.
|
||||
//
|
||||
// Redistribution and use in source and binary forms,
|
||||
// with or without modification of this file, are permitted under the terms of either
|
||||
// (at the option of the user):
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory, or at:
|
||||
// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module ad_ip_jesd204_tpl_adc_pnmon #(
|
||||
parameter CONVERTER_RESOLUTION = 16,
|
||||
parameter DATA_PATH_WIDTH = 1,
|
||||
parameter TWOS_COMPLEMENT = 1
|
||||
) (
|
||||
input clk,
|
||||
|
||||
// data interface
|
||||
input [CONVERTER_RESOLUTION*DATA_PATH_WIDTH-1:0] data,
|
||||
|
||||
// pn out of sync and error
|
||||
output pn_oos,
|
||||
output pn_err,
|
||||
|
||||
// processor interface PN9 (0x0), PN23 (0x1)
|
||||
input [3:0] pn_seq_sel
|
||||
);
|
||||
|
||||
localparam DW = DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1;
|
||||
|
||||
// Max width of largest PN and data width
|
||||
localparam PN_W = DW > 22 ? DW : 22;
|
||||
|
||||
// internal registers
|
||||
reg [PN_W:0] pn_data_pn = 'd0;
|
||||
|
||||
// internal signals
|
||||
wire [PN_W:0] pn_data_pn_s;
|
||||
wire [DW:0] pn_data_in_s;
|
||||
wire [PN_W:0] pn_data_init;
|
||||
|
||||
wire [DW:0] pn23;
|
||||
wire [DW+23:0] full_state_pn23;
|
||||
wire [DW:0] pn9;
|
||||
wire [DW+9:0] full_state_pn9;
|
||||
|
||||
// pn sequence select
|
||||
generate if (PN_W > DW) begin
|
||||
reg [PN_W-DW-1:0] pn_data_in_d = 'd0;
|
||||
always @(posedge clk) begin
|
||||
pn_data_in_d <= pn_data_in_s[PN_W-DW-1:0];
|
||||
end
|
||||
assign pn_data_init = {pn_data_in_d, pn_data_in_s};
|
||||
end else begin
|
||||
assign pn_data_init = pn_data_in_s;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign pn_data_pn_s = (pn_oos == 1'b1) ? pn_data_init : pn_data_pn;
|
||||
|
||||
wire tc = TWOS_COMPLEMENT ? 1'b1 : 1'b0;
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: g_pn_swizzle
|
||||
localparam src_lsb = i * CONVERTER_RESOLUTION;
|
||||
localparam src_msb = src_lsb + CONVERTER_RESOLUTION - 1;
|
||||
localparam dst_lsb = (DATA_PATH_WIDTH - i - 1) * CONVERTER_RESOLUTION;
|
||||
localparam dst_msb = dst_lsb + CONVERTER_RESOLUTION - 1;
|
||||
|
||||
assign pn_data_in_s[dst_msb] = (~tc) ^ data[src_msb];
|
||||
assign pn_data_in_s[dst_msb-1:dst_lsb] = data[src_msb-1:src_lsb];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// PN23 x^23 + x^18 + 1
|
||||
assign pn23 = full_state_pn23[23+:DW+1] ^ full_state_pn23[18+:DW+1];
|
||||
assign full_state_pn23 = {pn_data_pn_s[22:0],pn23};
|
||||
|
||||
// PN9 x^9 + x^5 + 1
|
||||
assign pn9 = full_state_pn9[9+:DW+1] ^ full_state_pn9[5+:DW+1];
|
||||
assign full_state_pn9 = {pn_data_pn_s[8:0],pn9};
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (pn_seq_sel == 4'd0) begin
|
||||
pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn9} : pn9;
|
||||
end else begin
|
||||
pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn23} : pn23;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// pn oos & pn err
|
||||
|
||||
ad_pnmon #(
|
||||
.DATA_WIDTH (DW+1)
|
||||
) i_pnmon (
|
||||
.adc_clk (clk),
|
||||
.adc_valid_in (1'b1),
|
||||
.adc_data_in (pn_data_in_s),
|
||||
.adc_data_pn (pn_data_pn[DW:0]),
|
||||
.adc_pn_oos (pn_oos),
|
||||
.adc_pn_err (pn_err)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,344 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// Each core or library found in this collection may have its own licensing terms.
|
||||
// The user should keep this in in mind while exploring these cores.
|
||||
//
|
||||
// Redistribution and use in source and binary forms,
|
||||
// with or without modification of this file, are permitted under the terms of either
|
||||
// (at the option of the user):
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory, or at:
|
||||
// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module ad_ip_jesd204_tpl_adc_regmap #(
|
||||
parameter ID = 0,
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter FPGA_FAMILY = 0,
|
||||
parameter SPEED_GRADE = 0,
|
||||
parameter DEV_PACKAGE = 0,
|
||||
parameter NUM_CHANNELS = 1,
|
||||
parameter DATA_PATH_WIDTH = 1,
|
||||
parameter NUM_PROFILES = 1 // Number of supported JESD profiles
|
||||
) (
|
||||
// axi interface
|
||||
input s_axi_aclk,
|
||||
input s_axi_aresetn,
|
||||
input s_axi_awvalid,
|
||||
input [12:0] s_axi_awaddr,
|
||||
input [2:0] s_axi_awprot,
|
||||
output s_axi_awready,
|
||||
input s_axi_wvalid,
|
||||
input [31:0] s_axi_wdata,
|
||||
input [3:0] s_axi_wstrb,
|
||||
output s_axi_wready,
|
||||
output s_axi_bvalid,
|
||||
output [ 1:0] s_axi_bresp,
|
||||
input s_axi_bready,
|
||||
input s_axi_arvalid,
|
||||
input [12:0] s_axi_araddr,
|
||||
input [2:0] s_axi_arprot,
|
||||
output s_axi_arready,
|
||||
output s_axi_rvalid,
|
||||
output [1:0] s_axi_rresp,
|
||||
output [31:0] s_axi_rdata,
|
||||
input s_axi_rready,
|
||||
|
||||
// control interface
|
||||
input link_clk,
|
||||
|
||||
// Data format conversion configuration
|
||||
output [NUM_CHANNELS-1:0] dfmt_enable,
|
||||
output [NUM_CHANNELS-1:0] dfmt_sign_extend,
|
||||
output [NUM_CHANNELS-1:0] dfmt_type,
|
||||
|
||||
// PN sequence monitor
|
||||
output [NUM_CHANNELS*4-1:0] pn_seq_sel,
|
||||
input [NUM_CHANNELS-1:0] pn_err,
|
||||
input [NUM_CHANNELS-1:0] pn_oos,
|
||||
|
||||
output [NUM_CHANNELS-1:0] enable,
|
||||
|
||||
input adc_sync_status,
|
||||
output adc_sync,
|
||||
output adc_rst,
|
||||
|
||||
// Underflow
|
||||
input adc_dovf,
|
||||
|
||||
// Deframer interface
|
||||
input [NUM_PROFILES*8-1: 0] jesd_m,
|
||||
input [NUM_PROFILES*8-1: 0] jesd_l,
|
||||
input [NUM_PROFILES*8-1: 0] jesd_s,
|
||||
input [NUM_PROFILES*8-1: 0] jesd_f,
|
||||
input [NUM_PROFILES*8-1: 0] jesd_n,
|
||||
input [NUM_PROFILES*8-1: 0] jesd_np,
|
||||
|
||||
output [$clog2(NUM_PROFILES):0] up_profile_sel
|
||||
);
|
||||
|
||||
localparam [31:0] CLK_RATIO = DATA_PATH_WIDTH;
|
||||
|
||||
reg up_rack = 1'b0;
|
||||
reg up_wack = 1'b0;
|
||||
reg [31:0] up_rdata = 32'h00;
|
||||
reg [31:0] up_rdata_all;
|
||||
|
||||
reg up_status_pn_err = 1'b0;
|
||||
reg up_status_pn_oos = 1'b0;
|
||||
|
||||
reg adc_status = 1'b0;
|
||||
|
||||
// internal clocks & resets
|
||||
wire up_clk;
|
||||
wire up_rstn;
|
||||
|
||||
wire up_wreq_s;
|
||||
wire [10:0] up_waddr_s;
|
||||
wire [31:0] up_wdata_s;
|
||||
wire [NUM_CHANNELS+1:0] up_wack_s;
|
||||
wire up_rreq_s;
|
||||
wire [10:0] up_raddr_s;
|
||||
wire [31:0] up_rdata_s[0:NUM_CHANNELS+1];
|
||||
wire [NUM_CHANNELS+1:0] up_rack_s;
|
||||
|
||||
wire [NUM_CHANNELS-1:0] up_adc_pn_err_s;
|
||||
wire [NUM_CHANNELS-1:0] up_adc_pn_oos_s;
|
||||
|
||||
// signal name changes
|
||||
|
||||
assign up_clk = s_axi_aclk;
|
||||
assign up_rstn = s_axi_aresetn;
|
||||
|
||||
// status
|
||||
|
||||
always @(posedge link_clk) begin
|
||||
if (adc_rst == 1'b1) begin
|
||||
adc_status <= 1'b0;
|
||||
end else begin
|
||||
adc_status <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// up bus interface
|
||||
|
||||
up_axi #(
|
||||
.AXI_ADDRESS_WIDTH (13)
|
||||
) i_up_axi (
|
||||
.up_clk (up_clk),
|
||||
.up_rstn (up_rstn),
|
||||
|
||||
.up_axi_awvalid (s_axi_awvalid),
|
||||
.up_axi_awaddr ({3'b0,s_axi_awaddr}),
|
||||
.up_axi_awready (s_axi_awready),
|
||||
.up_axi_wvalid (s_axi_wvalid),
|
||||
.up_axi_wdata (s_axi_wdata),
|
||||
.up_axi_wstrb (s_axi_wstrb),
|
||||
.up_axi_wready (s_axi_wready),
|
||||
.up_axi_bvalid (s_axi_bvalid),
|
||||
.up_axi_bresp (s_axi_bresp),
|
||||
.up_axi_bready (s_axi_bready),
|
||||
.up_axi_arvalid (s_axi_arvalid),
|
||||
.up_axi_araddr ({3'b0,s_axi_araddr}),
|
||||
.up_axi_arready (s_axi_arready),
|
||||
.up_axi_rvalid (s_axi_rvalid),
|
||||
.up_axi_rresp (s_axi_rresp),
|
||||
.up_axi_rdata (s_axi_rdata),
|
||||
.up_axi_rready (s_axi_rready),
|
||||
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack)
|
||||
);
|
||||
|
||||
integer n;
|
||||
|
||||
always @(*) begin
|
||||
up_rdata_all = 'h00;
|
||||
for (n = 0; n <= NUM_CHANNELS+1; n = n + 1) begin
|
||||
up_rdata_all = up_rdata_all | up_rdata_s[n];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_status_pn_err <= 'd0;
|
||||
up_status_pn_oos <= 'd0;
|
||||
up_rdata <= 'd0;
|
||||
up_rack <= 'd0;
|
||||
up_wack <= 'd0;
|
||||
end else begin
|
||||
up_status_pn_err <= |up_adc_pn_err_s;
|
||||
up_status_pn_oos <= |up_adc_pn_oos_s;
|
||||
|
||||
up_rdata <= up_rdata_all;
|
||||
up_rack <= |up_rack_s;
|
||||
up_wack <= |up_wack_s;
|
||||
end
|
||||
end
|
||||
|
||||
// common processor control
|
||||
|
||||
up_adc_common #(
|
||||
.COMMON_ID (6'h0),
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.DRP_DISABLE (1),
|
||||
.USERPORTS_DISABLE (1),
|
||||
.GPIO_DISABLE (1),
|
||||
.START_CODE_DISABLE (1)
|
||||
) i_up_adc_common (
|
||||
.mmcm_rst (),
|
||||
.adc_clk (link_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_r1_mode (),
|
||||
.adc_ddr_edgesel (),
|
||||
.adc_pin_mode (),
|
||||
.adc_status (adc_status),
|
||||
.adc_sync_status (adc_sync_status),
|
||||
.adc_status_ovf (adc_dovf),
|
||||
.adc_clk_ratio (CLK_RATIO),
|
||||
.adc_start_code (),
|
||||
.adc_sref_sync (),
|
||||
.adc_sync (adc_sync),
|
||||
|
||||
.up_status_pn_err (up_status_pn_err),
|
||||
.up_status_pn_oos (up_status_pn_oos),
|
||||
.up_status_or (1'b0),
|
||||
.up_drp_sel (),
|
||||
.up_drp_wr (),
|
||||
.up_drp_addr (),
|
||||
.up_drp_wdata (),
|
||||
.up_drp_rdata (32'd0),
|
||||
.up_drp_ready (1'd0),
|
||||
.up_drp_locked (1'd1),
|
||||
.up_usr_chanmax_out (),
|
||||
.up_usr_chanmax_in (NUM_CHANNELS),
|
||||
.up_adc_gpio_in (32'd0),
|
||||
.up_adc_gpio_out (),
|
||||
.up_adc_ce (),
|
||||
.up_pps_rcounter (32'd0),
|
||||
.up_pps_status (1'b0),
|
||||
.up_pps_irq_mask (),
|
||||
|
||||
.up_clk (up_clk),
|
||||
.up_rstn (up_rstn),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr ({3'b0,up_waddr_s}),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s[0]),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr ({3'b0,up_raddr_s}),
|
||||
.up_rdata (up_rdata_s[0]),
|
||||
.up_rack (up_rack_s[0])
|
||||
);
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel
|
||||
up_adc_channel #(
|
||||
.COMMON_ID (6'h1 + i/16),
|
||||
.CHANNEL_ID (i % 16),
|
||||
.USERPORTS_DISABLE (1),
|
||||
.DCFILTER_DISABLE (1),
|
||||
.IQCORRECTION_DISABLE (1)
|
||||
) i_up_adc_channel (
|
||||
.adc_clk (link_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_enable (enable[i]),
|
||||
.adc_iqcor_enb (),
|
||||
.adc_dcfilt_enb (),
|
||||
.adc_dfmt_enable (dfmt_enable[i]),
|
||||
.adc_dfmt_se (dfmt_sign_extend[i]),
|
||||
.adc_dfmt_type (dfmt_type[i]),
|
||||
.adc_dcfilt_offset (),
|
||||
.adc_dcfilt_coeff (),
|
||||
.adc_iqcor_coeff_1 (),
|
||||
.adc_iqcor_coeff_2 (),
|
||||
.adc_pnseq_sel (pn_seq_sel[i*4+:4]),
|
||||
.adc_data_sel (),
|
||||
.adc_pn_err (pn_err[i]),
|
||||
.adc_pn_oos (pn_oos[i]),
|
||||
.adc_or (1'b0),
|
||||
.adc_usr_datatype_be (1'b0),
|
||||
.adc_usr_datatype_signed (1'b1),
|
||||
.adc_usr_datatype_shift (8'd0),
|
||||
.adc_usr_datatype_total_bits (8'd16),
|
||||
.adc_usr_datatype_bits (8'd16),
|
||||
.adc_usr_decimation_m (16'd1),
|
||||
.adc_usr_decimation_n (16'd1),
|
||||
|
||||
.up_adc_pn_err (up_adc_pn_err_s[i]),
|
||||
.up_adc_pn_oos (up_adc_pn_oos_s[i]),
|
||||
.up_adc_or (),
|
||||
.up_usr_datatype_be (),
|
||||
.up_usr_datatype_signed (),
|
||||
.up_usr_datatype_shift (),
|
||||
.up_usr_datatype_total_bits (),
|
||||
.up_usr_datatype_bits (),
|
||||
.up_usr_decimation_m (),
|
||||
.up_usr_decimation_n (),
|
||||
|
||||
.up_clk (up_clk),
|
||||
.up_rstn (up_rstn),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr ({3'b0,up_waddr_s}),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s[i+1]),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr ({3'b0,up_raddr_s}),
|
||||
.up_rdata (up_rdata_s[i+1]),
|
||||
.up_rack (up_rack_s[i+1])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
up_tpl_common #(
|
||||
.COMMON_ID(2'h0), // Offset of regmap
|
||||
.NUM_PROFILES(NUM_PROFILES) // Number of JESD profiles
|
||||
) i_up_tpl_adc (
|
||||
|
||||
.jesd_m (jesd_m),
|
||||
.jesd_l (jesd_l),
|
||||
.jesd_s (jesd_s),
|
||||
.jesd_f (jesd_f),
|
||||
.jesd_n (jesd_n),
|
||||
.jesd_np (jesd_np),
|
||||
|
||||
.up_profile_sel (up_profile_sel),
|
||||
|
||||
// bus interface
|
||||
.up_clk (up_clk),
|
||||
.up_rstn (up_rstn),
|
||||
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s[NUM_CHANNELS+1]),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_s[NUM_CHANNELS+1]),
|
||||
.up_rack (up_rack_s[NUM_CHANNELS+1])
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,47 @@
|
||||
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
bd::mark_propagate_only $ip " \
|
||||
DEV_PACKAGE \
|
||||
SPEED_GRADE \
|
||||
FPGA_FAMILY \
|
||||
FPGA_TECHNOLOGY"
|
||||
|
||||
adi_auto_assign_device_spec $cellpath
|
||||
}
|
||||
|
||||
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable/overwritable parameters
|
||||
foreach i $auto_set_param_list_overwritable {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,2 @@
|
||||
CLEAN_TARGET += bd
|
||||
CLEAN_TARGET += temporary_case_dependencies.mk
|
||||
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Wed Dec 8 20:24:15 2021
|
||||
# Process ID: 145684
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc
|
||||
# Command line: vivado -mode batch -source ad_ip_jesd204_tpl_adc_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source ad_ip_jesd204_tpl_adc_ip.tcl
|
||||
@@ -0,0 +1,838 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Wed Dec 8 20:24:15 2021
|
||||
# Process ID: 145684
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc
|
||||
# Command line: vivado -mode batch -source ad_ip_jesd204_tpl_adc_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source ad_ip_jesd204_tpl_adc_ip.tcl
|
||||
# source ../../scripts/adi_env.tcl
|
||||
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
|
||||
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
|
||||
## if [info exists ::env(ADI_HDL_DIR)] {
|
||||
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
|
||||
## }
|
||||
## if [info exists ::env(ADI_GHDL_DIR)] {
|
||||
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
|
||||
## }
|
||||
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
|
||||
### variable auto_set_param_list
|
||||
### variable auto_set_param_list_overwritable
|
||||
### variable fpga_series_list
|
||||
### variable fpga_family_list
|
||||
### variable speed_grade_list
|
||||
### variable dev_package_list
|
||||
### variable xcvr_type_list
|
||||
### variable fpga_voltage_list
|
||||
### set auto_set_param_list { \
|
||||
### DEV_PACKAGE \
|
||||
### SPEED_GRADE \
|
||||
### FPGA_FAMILY \
|
||||
### FPGA_TECHNOLOGY }
|
||||
### set auto_set_param_list_overwritable { \
|
||||
### FPGA_VOLTAGE \
|
||||
### XCVR_TYPE }
|
||||
### set fpga_technology_list { \
|
||||
### { Unknown 0 } \
|
||||
### { 7series 1 } \
|
||||
### { ultrascale 2 } \
|
||||
### { ultrascale+ 3 }}
|
||||
### set fpga_family_list { \
|
||||
### { Unknown 0 } \
|
||||
### { artix 1 } \
|
||||
### { kintex 2 } \
|
||||
### { virtex 3 } \
|
||||
### { zynq 4 }}
|
||||
### set speed_grade_list { \
|
||||
### { Unknown 0 } \
|
||||
### { -1 10 } \
|
||||
### { -1L 11 } \
|
||||
### { -1H 12 } \
|
||||
### { -1HV 13 } \
|
||||
### { -1LV 14 } \
|
||||
### { -2 20 } \
|
||||
### { -2L 21 } \
|
||||
### { -2LV 22 } \
|
||||
### { -3 30 }}
|
||||
### set dev_package_list { \
|
||||
### { Unknown 0 } \
|
||||
### { rf 1 } \
|
||||
### { fl 2 } \
|
||||
### { ff 3 } \
|
||||
### { fb 4 } \
|
||||
### { hc 5 } \
|
||||
### { fh 6 } \
|
||||
### { cs 7 } \
|
||||
### { cp 8 } \
|
||||
### { ft 9 } \
|
||||
### { fg 10 } \
|
||||
### { sb 11 } \
|
||||
### { rb 12 } \
|
||||
### { rs 13 } \
|
||||
### { cl 14 } \
|
||||
### { sf 15 } \
|
||||
### { ba 16 } \
|
||||
### { fa 17 } \
|
||||
### { fs 18 } \
|
||||
### { fi 19 }}
|
||||
### set xcvr_type_list { \
|
||||
### { Unknown 0 } \
|
||||
### { GTPE2_NOT_SUPPORTED 1 } \
|
||||
### { GTXE2 2 } \
|
||||
### { GTHE2_NOT_SUPPORTED 3 } \
|
||||
### { GTZE2_NOT_SUPPORTED 4 } \
|
||||
### { GTHE3 5 } \
|
||||
### { GTYE3_NOT_SUPPORTED 6 } \
|
||||
### { GTRE4_NOT_SUPPORTED 7 } \
|
||||
### { GTHE4 8 } \
|
||||
### { GTYE4 9 } \
|
||||
### { GTME4_NOT_SUPPORTED 10}}
|
||||
### set fpga_voltage_list {0 5000} ;
|
||||
### proc adi_device_spec {cellpath param} {
|
||||
###
|
||||
### set list_pointer [string tolower $param]
|
||||
### set list_pointer [append list_pointer "_list"]
|
||||
###
|
||||
### upvar 1 $list_pointer $list_pointer
|
||||
###
|
||||
### set ip [get_bd_cells $cellpath]
|
||||
### set part [get_property PART [current_project]]
|
||||
###
|
||||
### switch -regexp -- $param {
|
||||
### FPGA_TECHNOLOGY {
|
||||
### switch -regexp -- $part {
|
||||
### ^xc7 {set series_name 7series}
|
||||
### ^xczu {set series_name ultrascale+}
|
||||
### ^xc.u.p {set series_name ultrascale+}
|
||||
### ^xc.u {set series_name ultrascale }
|
||||
### default {
|
||||
### puts "Undefined fpga technology for \"$part\"!"
|
||||
### exit -1
|
||||
### }
|
||||
### }
|
||||
### return "$series_name"
|
||||
### }
|
||||
### FPGA_FAMILY {
|
||||
### set fpga_family [get_property FAMILY $part]
|
||||
### foreach i $fpga_family_list {
|
||||
### regexp ^[lindex $i 0] $fpga_family matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### SPEED_GRADE {
|
||||
### set speed_grade [get_property SPEED $part]
|
||||
### return "$speed_grade"
|
||||
### }
|
||||
### DEV_PACKAGE {
|
||||
### set dev_package [get_property PACKAGE $part]
|
||||
### foreach i $dev_package_list {
|
||||
### regexp ^[lindex $i 0] $dev_package matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### XCVR_TYPE {
|
||||
### set matched ""
|
||||
### set dev_transcivers "none"
|
||||
### foreach x [list_property $part] {
|
||||
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
|
||||
### }
|
||||
### foreach i $xcvr_type_list {
|
||||
### regexp ^[lindex $i 0] $dev_transcivers matched
|
||||
### }
|
||||
### if { $matched eq "" } {
|
||||
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### FPGA_VOLTAGE {
|
||||
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
|
||||
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
|
||||
###
|
||||
### return "$fpga_voltage"
|
||||
### }
|
||||
### default {
|
||||
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
|
||||
### }
|
||||
### }
|
||||
### }
|
||||
## if {![info exists REQUIRED_VIVADO_VERSION]} {
|
||||
## set REQUIRED_VIVADO_VERSION "2019.1"
|
||||
## }
|
||||
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
|
||||
## set IGNORE_VERSION_CHECK 1
|
||||
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
|
||||
## set IGNORE_VERSION_CHECK 0
|
||||
## }
|
||||
## proc adi_ip_ttcl {ip_name ip_constr_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
|
||||
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_sim_ttcl {ip_name ip_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
|
||||
## set f [ipx::add_file $ip_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_bd {ip_name ip_bd_files} {
|
||||
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
|
||||
## if {$proj_filegroup == {}} {
|
||||
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
|
||||
## }
|
||||
##
|
||||
## foreach file $ip_bd_files {
|
||||
## set f [ipx::add_file $file $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type tclSource \
|
||||
## ] $f
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_infer_streaming_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_ip_infer_mm_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
|
||||
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency $port
|
||||
## if {$driver_value != {}} {
|
||||
## set_property DRIVER_VALUE $driver_value $port
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_set_bus_dependency {bus prefix dependency} {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
|
||||
## adi_set_ports_dependency $prefix $dependency 0
|
||||
## }
|
||||
## proc adi_add_port_map {bus phys logic} {
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## }
|
||||
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## adi_add_port_map $bus {*}$port_map
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
|
||||
## for {set i 0} {$i < $num} {incr i} {
|
||||
## set bus_name [format "%s%d" $bus_name_prefix $i]
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## if {$dependency ne ""} {
|
||||
## set bus_dependency [string map [list "{i}" $i] $dependency]
|
||||
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
|
||||
## }
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## lassign $port_map phys logic width width_dep
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
|
||||
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
|
||||
## if {$width_dep ne ""} {
|
||||
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
|
||||
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
|
||||
## set width_dep_r "(($width_dep) * $i)"
|
||||
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
|
||||
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
|
||||
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
|
||||
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
|
||||
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
|
||||
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
|
||||
## set_property display_name $clock_inf_name $clock_inf
|
||||
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
|
||||
## set_property physical_name $clock_signal_name $clock_map
|
||||
##
|
||||
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
|
||||
## set_property value $bus_inf_name $assoc_busif
|
||||
##
|
||||
## if { $reset_signal_name != "" } {
|
||||
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
|
||||
## set_property value $reset_signal_name $assoc_reset
|
||||
##
|
||||
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
|
||||
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
|
||||
## set_property display_name $reset_inf_name $reset_inf
|
||||
## set_property interface_mode $reset_signal_mode $reset_inf
|
||||
## set reset_map [ipx::add_port_map "RST" $reset_inf]
|
||||
## set_property physical_name $reset_signal_name $reset_map
|
||||
##
|
||||
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
|
||||
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
|
||||
## set_property value "ACTIVE_LOW" $reset_polarity
|
||||
## } else {
|
||||
## set_property value "ACTIVE_HIGH" $reset_polarity
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_add_core_dependencies {vlnvs} {
|
||||
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
|
||||
## foreach vlnv $vlnvs {
|
||||
## ipx::add_subcore $vlnv $file_group
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_create {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
## global ad_ghdl_dir
|
||||
## global REQUIRED_VIVADO_VERSION
|
||||
## global IGNORE_VERSION_CHECK
|
||||
##
|
||||
## set VIVADO_VERSION [version -short]
|
||||
## if {$IGNORE_VERSION_CHECK} {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## }
|
||||
## } else {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "ERROR: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
|
||||
## exit 2
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## create_project $ip_name . -force
|
||||
##
|
||||
## ## Load custom message severity definitions
|
||||
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
|
||||
##
|
||||
## set lib_dirs $ad_hdl_dir/library
|
||||
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
|
||||
## lappend lib_dirs $ad_ghdl_dir/library
|
||||
## }
|
||||
##
|
||||
## set_property ip_repo_paths $lib_dirs [current_fileset]
|
||||
## update_ip_catalog
|
||||
## }
|
||||
## proc adi_ip_files {ip_name ip_files} {
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## foreach m_file $ip_files {
|
||||
## if {[file extension $m_file] eq ".xdc"} {
|
||||
## add_files -norecurse -fileset constrs_1 $m_file
|
||||
## } else {
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
|
||||
## }
|
||||
## }
|
||||
## set_property "top" "$ip_name" $proj_fileset
|
||||
## }
|
||||
## proc adi_ip_properties_lite {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
##
|
||||
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
|
||||
##
|
||||
## set_property name $ip_name [ipx::current_core]
|
||||
##
|
||||
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
|
||||
## set_property company_url {http://www.analog.com} [ipx::current_core]
|
||||
##
|
||||
## set i_families ""
|
||||
## foreach i_part [get_parts] {
|
||||
## lappend i_families [get_property FAMILY $i_part]
|
||||
## }
|
||||
## set i_families [lsort -unique $i_families]
|
||||
## set s_families [get_property supported_families [ipx::current_core]]
|
||||
## foreach i_family $i_families {
|
||||
## set s_families "$s_families $i_family Production"
|
||||
## set s_families "$s_families $i_family Beta"
|
||||
## }
|
||||
## set_property supported_families $s_families [ipx::current_core]
|
||||
##
|
||||
## ipx::save_core [ipx::current_core]
|
||||
##
|
||||
## ipx::remove_all_bus_interface [ipx::current_core]
|
||||
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
|
||||
## foreach map $memory_maps {
|
||||
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
|
||||
## }
|
||||
##
|
||||
## ipx::update_checksums [ipx::current_core]
|
||||
## ipx::save_core [ipx::current_core]
|
||||
## }
|
||||
## proc adi_ip_properties {ip_name} {
|
||||
##
|
||||
## adi_ip_properties_lite $ip_name
|
||||
##
|
||||
## ipx::infer_bus_interface {\
|
||||
## s_axi_awvalid \
|
||||
## s_axi_awaddr \
|
||||
## s_axi_awprot \
|
||||
## s_axi_awready \
|
||||
## s_axi_wvalid \
|
||||
## s_axi_wdata \
|
||||
## s_axi_wstrb \
|
||||
## s_axi_wready \
|
||||
## s_axi_bvalid \
|
||||
## s_axi_bresp \
|
||||
##
|
||||
## s_axi_bready \
|
||||
## s_axi_arvalid \
|
||||
## s_axi_araddr \
|
||||
## s_axi_arprot \
|
||||
## s_axi_arready \
|
||||
## s_axi_rvalid \
|
||||
## s_axi_rdata \
|
||||
## s_axi_rresp \
|
||||
## s_axi_rready} \
|
||||
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
|
||||
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
|
||||
##
|
||||
## if {$raddr_width != $waddr_width} {
|
||||
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
|
||||
## set range 65536
|
||||
## } else {
|
||||
## if {$raddr_width >= 16} {
|
||||
## set range 65536
|
||||
## } else {
|
||||
## set range [expr 1 << $raddr_width]
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
## set_property range $range [ipx::get_address_blocks axi_lite \
|
||||
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
|
||||
## ipx::save_core
|
||||
## }
|
||||
## proc adi_init_bd_tcl {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## if { [file exists bd] } {
|
||||
## file delete -force bd
|
||||
## }
|
||||
## file mkdir bd
|
||||
##
|
||||
## set bd_tcl [open "bd/bd.tcl" w]
|
||||
##
|
||||
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
|
||||
## puts $bd_tcl "proc init {cellpath otherInfo} {"
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl ""
|
||||
## set auto_set_param ""
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
|
||||
## puts $bd_tcl $auto_set_param
|
||||
## }
|
||||
##
|
||||
## set auto_set_overwritable_param ""
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_overwritable_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_overwritable_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
|
||||
## puts $bd_tcl $auto_set_overwritable_param
|
||||
## }
|
||||
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
|
||||
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
|
||||
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set parent_dir \"../\""
|
||||
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
|
||||
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
|
||||
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " break"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " append parent_dir \"../\""
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## close $bd_tcl
|
||||
##
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
|
||||
##
|
||||
## set local_mk [open "temporary_case_dependencies.mk" w]
|
||||
## seek $local_mk 0 start
|
||||
## puts $local_mk "CLEAN_TARGET += bd"
|
||||
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
|
||||
## close $local_mk
|
||||
## }
|
||||
## proc adi_add_auto_fpga_spec_params {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_device_spec_param {ip_param} {
|
||||
##
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## set list_pointer [string tolower $ip_param]
|
||||
## set list_pointer [append list_pointer "_list"]
|
||||
##
|
||||
## global $list_pointer
|
||||
##
|
||||
## # set j 1D list from the original list
|
||||
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
|
||||
##
|
||||
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
|
||||
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "range_long" \
|
||||
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
|
||||
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## } else {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "pairs" \
|
||||
## "value_validation_pairs" $j ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## }
|
||||
##
|
||||
## # FPGA info grup
|
||||
## set info_group_name "FPGA info"
|
||||
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
|
||||
## if { [string trim $info_group] eq "" } {
|
||||
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
|
||||
## -parent $page0 -display_name $info_group_name]
|
||||
## }
|
||||
##
|
||||
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
|
||||
## set_property -dict [list "widget" "comboBox" ] $p
|
||||
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
|
||||
## }
|
||||
## proc adi_if_define {name} {
|
||||
##
|
||||
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
|
||||
## ipx::create_bus_definition analog.com interface $name 1.0
|
||||
##
|
||||
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
|
||||
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
|
||||
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
|
||||
##
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## }
|
||||
## proc adi_if_ports {dir width name {type none}} {
|
||||
##
|
||||
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
|
||||
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
|
||||
## set_property master_presence required $m_intf
|
||||
## set_property slave_presence required $m_intf
|
||||
## set_property master_width $width $m_intf
|
||||
## set_property slave_width $width $m_intf
|
||||
##
|
||||
## set m_dir "in"
|
||||
## set s_dir "out"
|
||||
## if {$dir eq "output"} {
|
||||
## set m_dir "out"
|
||||
## set s_dir "in"
|
||||
## }
|
||||
##
|
||||
## set_property master_direction $m_dir $m_intf
|
||||
## set_property slave_direction $s_dir $m_intf
|
||||
##
|
||||
## if {$type ne "none"} {
|
||||
## set_property is_${type} true $m_intf
|
||||
## }
|
||||
##
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## }
|
||||
## proc adi_if_infer_bus {if_name mode name maps} {
|
||||
##
|
||||
## ipx::add_bus_interface $name [ipx::current_core]
|
||||
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
|
||||
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
|
||||
## set_property interface_mode $mode $m_bus_if
|
||||
##
|
||||
## foreach map $maps {
|
||||
## set m_maps [regexp -all -inline {\S+} $map]
|
||||
## lassign $m_maps p_name p_map
|
||||
## ipx::add_port_map $p_name $m_bus_if
|
||||
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
|
||||
## }
|
||||
## }
|
||||
# adi_ip_create ad_ip_jesd204_tpl_adc
|
||||
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
|
||||
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1343} -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1306} -new_severity WARNING
|
||||
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
|
||||
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
|
||||
## set_msg_config -id {Synth 8-3331} -new_severity INFO
|
||||
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
|
||||
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
|
||||
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
|
||||
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'.)
|
||||
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
|
||||
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
|
||||
# adi_ip_files ad_ip_jesd204_tpl_adc [list \
|
||||
# "$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
# "$ad_hdl_dir/library/common/ad_perfect_shuffle.v" \
|
||||
# "$ad_hdl_dir/library/common/ad_pnmon.v" \
|
||||
# "$ad_hdl_dir/library/common/ad_datafmt.v" \
|
||||
# "$ad_hdl_dir/library/common/up_axi.v" \
|
||||
# "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||
# "$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
# "$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
# "$ad_hdl_dir/library/common/up_adc_common.v" \
|
||||
# "$ad_hdl_dir/library/common/up_adc_channel.v" \
|
||||
# "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
|
||||
# "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
|
||||
# "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
|
||||
# "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
|
||||
# "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
|
||||
# "../ad_ip_jesd204_tpl_common/up_tpl_common.v" \
|
||||
# "ad_ip_jesd204_tpl_adc_core.v" \
|
||||
# "ad_ip_jesd204_tpl_adc_channel.v" \
|
||||
# "ad_ip_jesd204_tpl_adc_deframer.v" \
|
||||
# "ad_ip_jesd204_tpl_adc_pnmon.v" \
|
||||
# "ad_ip_jesd204_tpl_adc_regmap.v" \
|
||||
# "ad_ip_jesd204_tpl_adc.v" \
|
||||
# ]
|
||||
# adi_ip_properties ad_ip_jesd204_tpl_adc
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_datafmt.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_pnmon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_rst.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_xcvr_rx_if.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_channel.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_adc_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_clock_mon.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/ad_ip_jesd204_tpl_adc'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
WARNING: [IP_Flow 19-5150] The Range '(((NUM_LANES * 8) * OCTETS_PER_BEAT) - 1):0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5150] The Range '(((NUM_LANES * 8) * OCTETS_PER_BEAT) - 1):0' is present in all ports of the interface 'link'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'adc' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_in' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'link' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5150] The Range '(NUM_CHANNELS - 1):0' is present in all ports of the interface 'interface_spi_engine_offload_ctrl'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'link_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data' and definition port 'DATA'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'adc_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'link': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'link_clk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
||||
# adi_init_bd_tcl
|
||||
# adi_ip_bd ad_ip_jesd204_tpl_adc "bd/bd.tcl"
|
||||
# set cc [ipx::current_core]
|
||||
# set_property display_name "JESD204 Transport Layer for ADCs" $cc
|
||||
# set_property description "JESD204 Transport Layer for ADCs" $cc
|
||||
# adi_add_bus "link" "master" \
|
||||
# "xilinx.com:interface:axis_rtl:1.0" \
|
||||
# "xilinx.com:interface:axis:1.0" \
|
||||
# [list \
|
||||
# {"link_ready" "TREADY"} \
|
||||
# {"link_valid" "TVALID"} \
|
||||
# {"link_data" "TDATA"} \
|
||||
# ]
|
||||
# adi_add_bus_clock "link_clk" "link"
|
||||
# foreach {p v} {
|
||||
# "NUM_LANES" "1 2 3 4 8 16" \
|
||||
# "NUM_CHANNELS" "1 2 4 6 8 16 32 64" \
|
||||
# "BITS_PER_SAMPLE" "8 12 16" \
|
||||
# "CONVERTER_RESOLUTION" "8 11 12 16" \
|
||||
# "SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \
|
||||
# "OCTETS_PER_BEAT" "4 8" \
|
||||
# } { \
|
||||
# set_property -dict [list \
|
||||
# "value_validation_type" "list" \
|
||||
# "value_validation_list" $v \
|
||||
# ] [ipx::get_user_parameters $p -of_objects $cc]
|
||||
# }
|
||||
# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
# set general_group [ipgui::add_group -name "General Configuration" -component $cc \
|
||||
# -parent $page0 -display_name "General Configuration"]
|
||||
# set p [ipgui::get_guiparamspec -name "ID" -component $cc]
|
||||
# ipgui::move_param -component $cc -order 0 $p -parent $general_group
|
||||
# set_property -dict [list \
|
||||
# "display_name" "Core ID" \
|
||||
# ] $p
|
||||
# set framer_group [ipgui::add_group -name "JESD204 Deframer Configuration" -component $cc \
|
||||
# -parent $page0 -display_name "JESD204 Deframer Cofiguration"]
|
||||
# set i 0
|
||||
# foreach {k v} { \
|
||||
# "NUM_LANES" "Number of Lanes (L)" \
|
||||
# "NUM_CHANNELS" "Number of Conveters (M)" \
|
||||
# "BITS_PER_SAMPLE" "Bits per Sample (N')" \
|
||||
# "CONVERTER_RESOLUTION" "Converter Resolution (N)" \
|
||||
# "SAMPLES_PER_FRAME" "Samples per Frame (S)" \
|
||||
# "OCTETS_PER_BEAT" "Octets per Beat" \
|
||||
# } { \
|
||||
# set p [ipgui::get_guiparamspec -name $k -component $cc]
|
||||
# ipgui::move_param -component $cc -order $i $p -parent $framer_group
|
||||
# set_property -dict [list \
|
||||
# WIDGET "comboBox" \
|
||||
# DISPLAY_NAME $v \
|
||||
# ] $p
|
||||
# incr i
|
||||
# }
|
||||
# set datapath_group [ipgui::add_group -name "Datapath Configuration" -component $cc \
|
||||
# -parent $page0 -display_name "Datapath Cofiguration"]
|
||||
# set i 0
|
||||
# foreach {k v w} {
|
||||
# "TWOS_COMPLEMENT" "Use twos complement" "checkBox" \
|
||||
# } { \
|
||||
# set p [ipgui::get_guiparamspec -name $k -component $cc]
|
||||
# ipgui::move_param -component $cc -order $i $p -parent $datapath_group
|
||||
# set_property -dict [list \
|
||||
# WIDGET $w \
|
||||
# DISPLAY_NAME $v \
|
||||
# ] $p
|
||||
# incr i
|
||||
# }
|
||||
# adi_add_auto_fpga_spec_params
|
||||
# ipx::create_xgui_files [ipx::current_core]
|
||||
# ipx::save_core [ipx::current_core]
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:24:32 2021...
|
||||
@@ -0,0 +1,202 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
#Adding Group
|
||||
set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${General_Configuration}
|
||||
|
||||
#Adding Group
|
||||
set JESD204_Deframer_Configuration [ipgui::add_group $IPINST -name "JESD204 Deframer Configuration" -parent ${Page_0} -display_name {JESD204 Deframer Cofiguration}]
|
||||
ipgui::add_param $IPINST -name "NUM_LANES" -parent ${JESD204_Deframer_Configuration} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "NUM_CHANNELS" -parent ${JESD204_Deframer_Configuration} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "BITS_PER_SAMPLE" -parent ${JESD204_Deframer_Configuration} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "CONVERTER_RESOLUTION" -parent ${JESD204_Deframer_Configuration} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "SAMPLES_PER_FRAME" -parent ${JESD204_Deframer_Configuration} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "OCTETS_PER_BEAT" -parent ${JESD204_Deframer_Configuration} -widget comboBox
|
||||
|
||||
#Adding Group
|
||||
set Datapath_Configuration [ipgui::add_group $IPINST -name "Datapath Configuration" -parent ${Page_0} -display_name {Datapath Cofiguration}]
|
||||
ipgui::add_param $IPINST -name "TWOS_COMPLEMENT" -parent ${Datapath_Configuration} -widget checkBox
|
||||
|
||||
#Adding Group
|
||||
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.BITS_PER_SAMPLE { PARAM_VALUE.BITS_PER_SAMPLE } {
|
||||
# Procedure called to update BITS_PER_SAMPLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.BITS_PER_SAMPLE { PARAM_VALUE.BITS_PER_SAMPLE } {
|
||||
# Procedure called to validate BITS_PER_SAMPLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CONVERTER_RESOLUTION { PARAM_VALUE.CONVERTER_RESOLUTION } {
|
||||
# Procedure called to update CONVERTER_RESOLUTION when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CONVERTER_RESOLUTION { PARAM_VALUE.CONVERTER_RESOLUTION } {
|
||||
# Procedure called to validate CONVERTER_RESOLUTION
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to validate DEV_PACKAGE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to validate FPGA_FAMILY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to validate FPGA_TECHNOLOGY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_CHANNELS { PARAM_VALUE.NUM_CHANNELS } {
|
||||
# Procedure called to update NUM_CHANNELS when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_CHANNELS { PARAM_VALUE.NUM_CHANNELS } {
|
||||
# Procedure called to validate NUM_CHANNELS
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
|
||||
# Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
|
||||
# Procedure called to validate NUM_LANES
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.OCTETS_PER_BEAT { PARAM_VALUE.OCTETS_PER_BEAT } {
|
||||
# Procedure called to update OCTETS_PER_BEAT when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.OCTETS_PER_BEAT { PARAM_VALUE.OCTETS_PER_BEAT } {
|
||||
# Procedure called to validate OCTETS_PER_BEAT
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SAMPLES_PER_FRAME { PARAM_VALUE.SAMPLES_PER_FRAME } {
|
||||
# Procedure called to update SAMPLES_PER_FRAME when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SAMPLES_PER_FRAME { PARAM_VALUE.SAMPLES_PER_FRAME } {
|
||||
# Procedure called to validate SAMPLES_PER_FRAME
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to validate SPEED_GRADE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.TWOS_COMPLEMENT { PARAM_VALUE.TWOS_COMPLEMENT } {
|
||||
# Procedure called to update TWOS_COMPLEMENT when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.TWOS_COMPLEMENT { PARAM_VALUE.TWOS_COMPLEMENT } {
|
||||
# Procedure called to validate TWOS_COMPLEMENT
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_CHANNELS { MODELPARAM_VALUE.NUM_CHANNELS PARAM_VALUE.NUM_CHANNELS } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_CHANNELS}] ${MODELPARAM_VALUE.NUM_CHANNELS}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SAMPLES_PER_FRAME { MODELPARAM_VALUE.SAMPLES_PER_FRAME PARAM_VALUE.SAMPLES_PER_FRAME } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SAMPLES_PER_FRAME}] ${MODELPARAM_VALUE.SAMPLES_PER_FRAME}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CONVERTER_RESOLUTION { MODELPARAM_VALUE.CONVERTER_RESOLUTION PARAM_VALUE.CONVERTER_RESOLUTION } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CONVERTER_RESOLUTION}] ${MODELPARAM_VALUE.CONVERTER_RESOLUTION}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.BITS_PER_SAMPLE { MODELPARAM_VALUE.BITS_PER_SAMPLE PARAM_VALUE.BITS_PER_SAMPLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.BITS_PER_SAMPLE}] ${MODELPARAM_VALUE.BITS_PER_SAMPLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.OCTETS_PER_BEAT { MODELPARAM_VALUE.OCTETS_PER_BEAT PARAM_VALUE.OCTETS_PER_BEAT } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.OCTETS_PER_BEAT}] ${MODELPARAM_VALUE.OCTETS_PER_BEAT}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.TWOS_COMPLEMENT { MODELPARAM_VALUE.TWOS_COMPLEMENT PARAM_VALUE.TWOS_COMPLEMENT } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.TWOS_COMPLEMENT}] ${MODELPARAM_VALUE.TWOS_COMPLEMENT}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user