Archived
initial commit
This commit is contained in:
@@ -0,0 +1,41 @@
|
||||
####################################################################################
|
||||
## Copyright 2018(c) Analog Devices, Inc.
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
LIBRARY_NAME := axi_jesd204_rx
|
||||
|
||||
GENERIC_DEPS += ../../common/up_axi.v
|
||||
GENERIC_DEPS += axi_jesd204_rx.v
|
||||
GENERIC_DEPS += jesd204_up_ilas_mem.v
|
||||
GENERIC_DEPS += jesd204_up_rx.v
|
||||
GENERIC_DEPS += jesd204_up_rx_lane.v
|
||||
|
||||
XILINX_DEPS += axi_jesd204_rx_constr.xdc
|
||||
XILINX_DEPS += axi_jesd204_rx_ip.tcl
|
||||
XILINX_DEPS += axi_jesd204_rx_ooc.ttcl
|
||||
|
||||
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml
|
||||
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg_rtl.xml
|
||||
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_event.xml
|
||||
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_event_rtl.xml
|
||||
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config.xml
|
||||
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config_rtl.xml
|
||||
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_status.xml
|
||||
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_status_rtl.xml
|
||||
|
||||
XILINX_LIB_DEPS += jesd204/axi_jesd204_common
|
||||
|
||||
XILINX_INTERFACE_DEPS += jesd204/interfaces
|
||||
|
||||
INTEL_DEPS += ../../common/up_clock_mon.v
|
||||
INTEL_DEPS += ../../intel/common/up_clock_mon_constr.sdc
|
||||
INTEL_DEPS += ../../util_cdc/sync_bits.v
|
||||
INTEL_DEPS += ../../util_cdc/sync_data.v
|
||||
INTEL_DEPS += ../../util_cdc/sync_event.v
|
||||
INTEL_DEPS += ../axi_jesd204_common/jesd204_up_common.v
|
||||
INTEL_DEPS += ../axi_jesd204_common/jesd204_up_sysref.v
|
||||
INTEL_DEPS += axi_jesd204_rx_constr.sdc
|
||||
INTEL_DEPS += axi_jesd204_rx_hw.tcl
|
||||
|
||||
include ../../scripts/library.mk
|
||||
@@ -0,0 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c42617463684d6f6465:1
|
||||
eof:
|
||||
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
|
||||
@@ -0,0 +1,335 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_jesd204_rx #(
|
||||
parameter ID = 0,
|
||||
parameter NUM_LANES = 1,
|
||||
parameter NUM_LINKS = 1,
|
||||
parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
|
||||
parameter ENABLE_LINK_STATS = 0
|
||||
) (
|
||||
input s_axi_aclk,
|
||||
input s_axi_aresetn,
|
||||
|
||||
input s_axi_awvalid,
|
||||
input [13:0] s_axi_awaddr,
|
||||
output s_axi_awready,
|
||||
input [2:0] s_axi_awprot,
|
||||
input s_axi_wvalid,
|
||||
input [31:0] s_axi_wdata,
|
||||
input [3:0] s_axi_wstrb,
|
||||
output s_axi_wready,
|
||||
output s_axi_bvalid,
|
||||
output [1:0] s_axi_bresp,
|
||||
input s_axi_bready,
|
||||
input s_axi_arvalid,
|
||||
input [13:0] s_axi_araddr,
|
||||
output s_axi_arready,
|
||||
input [2:0] s_axi_arprot,
|
||||
output s_axi_rvalid,
|
||||
input s_axi_rready,
|
||||
output [ 1:0] s_axi_rresp,
|
||||
output [31:0] s_axi_rdata,
|
||||
|
||||
output irq,
|
||||
|
||||
input core_clk,
|
||||
input core_reset_ext,
|
||||
output core_reset,
|
||||
|
||||
output [NUM_LANES-1:0] core_cfg_lanes_disable,
|
||||
output [NUM_LINKS-1:0] core_cfg_links_disable,
|
||||
output [7:0] core_cfg_beats_per_multiframe,
|
||||
output [7:0] core_cfg_octets_per_frame,
|
||||
output core_cfg_disable_scrambler,
|
||||
output core_cfg_disable_char_replacement,
|
||||
output [7:0] core_cfg_lmfc_offset,
|
||||
output core_cfg_sysref_oneshot,
|
||||
output core_cfg_sysref_disable,
|
||||
output core_cfg_buffer_early_release,
|
||||
output [7:0] core_cfg_buffer_delay,
|
||||
output [7:0] core_cfg_frame_align_err_threshold,
|
||||
|
||||
input [NUM_LANES-1:0] core_ilas_config_valid,
|
||||
input [2*NUM_LANES-1:0] core_ilas_config_addr,
|
||||
input [32*NUM_LANES-1:0] core_ilas_config_data,
|
||||
|
||||
input core_event_sysref_alignment_error,
|
||||
input core_event_sysref_edge,
|
||||
input core_event_frame_alignment_error,
|
||||
input core_event_unexpected_lane_state_error,
|
||||
|
||||
output [6:0] core_ctrl_err_statistics_mask,
|
||||
output core_ctrl_err_statistics_reset,
|
||||
|
||||
input [32*NUM_LANES-1:0] core_status_err_statistics_cnt,
|
||||
|
||||
input [1:0] core_status_ctrl_state,
|
||||
input [2*NUM_LANES-1:0] core_status_lane_cgs_state,
|
||||
input [3*NUM_LANES-1:0] core_status_lane_emb_state,
|
||||
input [NUM_LANES-1:0] core_status_lane_ifs_ready,
|
||||
input [14*NUM_LANES-1:0] core_status_lane_latency,
|
||||
input [8*NUM_LANES-1:0] core_status_lane_frame_align_err_cnt
|
||||
);
|
||||
|
||||
localparam PCORE_VERSION = 32'h00010461; // 1.04.a
|
||||
localparam PCORE_MAGIC = 32'h32303452; // 204R
|
||||
|
||||
localparam DATA_PATH_WIDTH = LINK_MODE == 2 ? 3 : 2;
|
||||
|
||||
/* Register interface signals */
|
||||
reg [31:0] up_rdata = 'h0;
|
||||
reg up_wack = 1'b0;
|
||||
reg up_rack = 1'b0;
|
||||
reg up_rreq_d1 = 1'b0;
|
||||
wire up_wreq;
|
||||
wire up_rreq;
|
||||
wire [31:0] up_wdata;
|
||||
wire [11:0] up_waddr;
|
||||
wire [11:0] up_raddr;
|
||||
wire [31:0] up_rdata_common;
|
||||
wire [31:0] up_rdata_sysref;
|
||||
wire [31:0] up_rdata_rx;
|
||||
|
||||
wire [4:0] up_irq_trigger;
|
||||
|
||||
wire up_cfg_is_writeable;
|
||||
wire up_cfg_sysref_oneshot;
|
||||
wire up_cfg_sysref_disable;
|
||||
wire up_cfg_buffer_early_release;
|
||||
wire [7:0] up_cfg_buffer_delay;
|
||||
wire [7:0] up_cfg_lmfc_offset;
|
||||
wire [7:0] up_cfg_frame_align_err_threshold;
|
||||
|
||||
wire up_reset;
|
||||
wire up_reset_synchronizer;
|
||||
wire up_event_frame_alignment_error;
|
||||
wire up_event_unexpected_lane_state_error;
|
||||
|
||||
sync_event #(
|
||||
.NUM_OF_EVENTS (2)
|
||||
) i_sync_frame_align_err (
|
||||
.in_clk(core_clk),
|
||||
.in_event({core_event_unexpected_lane_state_error,
|
||||
core_event_frame_alignment_error}),
|
||||
.out_clk(s_axi_aclk),
|
||||
.out_event({up_event_unexpected_lane_state_error,
|
||||
up_event_frame_alignment_error})
|
||||
);
|
||||
|
||||
assign up_irq_trigger = {3'b0,
|
||||
up_event_unexpected_lane_state_error,
|
||||
up_event_frame_alignment_error} &
|
||||
{5{~up_cfg_is_writeable}};
|
||||
|
||||
up_axi #(
|
||||
.AXI_ADDRESS_WIDTH (14)
|
||||
) i_up_axi (
|
||||
.up_rstn(~up_reset),
|
||||
.up_clk(s_axi_aclk),
|
||||
.up_axi_awvalid(s_axi_awvalid),
|
||||
.up_axi_awaddr(s_axi_awaddr),
|
||||
.up_axi_awready(s_axi_awready),
|
||||
.up_axi_wvalid(s_axi_wvalid),
|
||||
.up_axi_wdata(s_axi_wdata),
|
||||
.up_axi_wstrb(s_axi_wstrb),
|
||||
.up_axi_wready(s_axi_wready),
|
||||
.up_axi_bvalid(s_axi_bvalid),
|
||||
.up_axi_bresp(s_axi_bresp),
|
||||
.up_axi_bready(s_axi_bready),
|
||||
.up_axi_arvalid(s_axi_arvalid),
|
||||
.up_axi_araddr(s_axi_araddr),
|
||||
.up_axi_arready(s_axi_arready),
|
||||
.up_axi_rvalid(s_axi_rvalid),
|
||||
.up_axi_rresp(s_axi_rresp),
|
||||
.up_axi_rdata(s_axi_rdata),
|
||||
.up_axi_rready(s_axi_rready),
|
||||
.up_wreq(up_wreq),
|
||||
.up_waddr(up_waddr),
|
||||
.up_wdata(up_wdata),
|
||||
.up_wack(up_wack),
|
||||
.up_rreq(up_rreq),
|
||||
.up_raddr(up_raddr),
|
||||
.up_rdata(up_rdata),
|
||||
.up_rack(up_rack)
|
||||
);
|
||||
|
||||
jesd204_up_common #(
|
||||
.PCORE_VERSION(PCORE_VERSION),
|
||||
.PCORE_MAGIC(PCORE_MAGIC),
|
||||
.ID(ID),
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.NUM_LINKS(NUM_LINKS),
|
||||
.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
|
||||
.NUM_IRQS(5),
|
||||
.EXTRA_CFG_WIDTH(27),
|
||||
.LINK_MODE(LINK_MODE),
|
||||
.ENABLE_LINK_STATS(ENABLE_LINK_STATS)
|
||||
) i_up_common (
|
||||
.up_clk(s_axi_aclk),
|
||||
.ext_resetn(s_axi_aresetn),
|
||||
|
||||
.up_reset(up_reset),
|
||||
.up_reset_synchronizer(up_reset_synchronizer),
|
||||
|
||||
.core_clk(core_clk),
|
||||
.core_reset_ext(core_reset_ext),
|
||||
.core_reset(core_reset),
|
||||
|
||||
.up_raddr(up_raddr),
|
||||
.up_rdata(up_rdata_common),
|
||||
.up_wreq(up_wreq),
|
||||
.up_waddr(up_waddr),
|
||||
.up_wdata(up_wdata),
|
||||
|
||||
.up_cfg_is_writeable(up_cfg_is_writeable),
|
||||
|
||||
.up_irq_trigger(up_irq_trigger),
|
||||
.irq(irq),
|
||||
|
||||
.core_cfg_beats_per_multiframe(core_cfg_beats_per_multiframe),
|
||||
.core_cfg_octets_per_frame(core_cfg_octets_per_frame),
|
||||
.core_cfg_lanes_disable(core_cfg_lanes_disable),
|
||||
.core_cfg_links_disable(core_cfg_links_disable),
|
||||
.core_cfg_disable_scrambler(core_cfg_disable_scrambler),
|
||||
.core_cfg_disable_char_replacement(core_cfg_disable_char_replacement),
|
||||
|
||||
.up_extra_cfg({
|
||||
/* 19-26 */ up_cfg_frame_align_err_threshold,
|
||||
/* 18 */ up_cfg_sysref_disable,
|
||||
/* 17 */ up_cfg_sysref_oneshot,
|
||||
/* 16 */ up_cfg_buffer_early_release,
|
||||
/* 08-15 */ up_cfg_buffer_delay,
|
||||
/* 00-07 */ up_cfg_lmfc_offset
|
||||
}),
|
||||
.core_extra_cfg({
|
||||
/* 19-26 */ core_cfg_frame_align_err_threshold,
|
||||
/* 18 */ core_cfg_sysref_disable,
|
||||
/* 17 */ core_cfg_sysref_oneshot,
|
||||
/* 16 */ core_cfg_buffer_early_release,
|
||||
/* 08-15 */ core_cfg_buffer_delay,
|
||||
/* 00-07 */ core_cfg_lmfc_offset
|
||||
})
|
||||
);
|
||||
|
||||
jesd204_up_sysref #(
|
||||
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
|
||||
) i_up_sysref (
|
||||
.up_clk(s_axi_aclk),
|
||||
.up_reset(up_reset),
|
||||
|
||||
.core_clk(core_clk),
|
||||
.core_event_sysref_edge(core_event_sysref_edge),
|
||||
.core_event_sysref_alignment_error(core_event_sysref_alignment_error),
|
||||
|
||||
.up_raddr(up_raddr),
|
||||
.up_rdata(up_rdata_sysref),
|
||||
.up_wreq(up_wreq),
|
||||
.up_waddr(up_waddr),
|
||||
.up_wdata(up_wdata),
|
||||
|
||||
.up_cfg_is_writeable(up_cfg_is_writeable),
|
||||
|
||||
.up_cfg_lmfc_offset(up_cfg_lmfc_offset),
|
||||
.up_cfg_sysref_oneshot(up_cfg_sysref_oneshot),
|
||||
.up_cfg_sysref_disable(up_cfg_sysref_disable)
|
||||
);
|
||||
|
||||
jesd204_up_rx #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
|
||||
) i_up_rx (
|
||||
.up_clk(s_axi_aclk),
|
||||
.up_reset(up_reset),
|
||||
.up_reset_synchronizer(up_reset_synchronizer),
|
||||
|
||||
.core_clk(core_clk),
|
||||
.core_reset(core_reset),
|
||||
|
||||
.up_rreq(up_rreq),
|
||||
.up_raddr(up_raddr),
|
||||
.up_rdata(up_rdata_rx),
|
||||
.up_wreq(up_wreq),
|
||||
.up_waddr(up_waddr),
|
||||
.up_wdata(up_wdata),
|
||||
|
||||
.up_cfg_is_writeable(up_cfg_is_writeable),
|
||||
|
||||
.up_cfg_buffer_early_release(up_cfg_buffer_early_release),
|
||||
.up_cfg_buffer_delay(up_cfg_buffer_delay),
|
||||
|
||||
.up_cfg_frame_align_err_threshold(up_cfg_frame_align_err_threshold),
|
||||
|
||||
.core_ctrl_err_statistics_reset(core_ctrl_err_statistics_reset),
|
||||
.core_ctrl_err_statistics_mask(core_ctrl_err_statistics_mask),
|
||||
|
||||
.core_status_ctrl_state(core_status_ctrl_state),
|
||||
.core_status_lane_cgs_state(core_status_lane_cgs_state),
|
||||
.core_status_lane_emb_state(core_status_lane_emb_state),
|
||||
.core_status_lane_ifs_ready(core_status_lane_ifs_ready),
|
||||
.core_status_lane_latency(core_status_lane_latency),
|
||||
.core_status_lane_frame_align_err_cnt(core_status_lane_frame_align_err_cnt),
|
||||
|
||||
.core_status_err_statistics_cnt(core_status_err_statistics_cnt),
|
||||
|
||||
.core_ilas_config_valid(core_ilas_config_valid),
|
||||
.core_ilas_config_addr(core_ilas_config_addr),
|
||||
.core_ilas_config_data(core_ilas_config_data)
|
||||
);
|
||||
|
||||
always @(posedge s_axi_aclk) begin
|
||||
up_wack <= up_wreq;
|
||||
|
||||
// ILAS memory takes one clock cycle before the data is ready, hence the extra
|
||||
// delay.
|
||||
up_rreq_d1 <= up_rreq;
|
||||
up_rack <= up_rreq_d1;
|
||||
if (up_rreq_d1 == 1'b1) begin
|
||||
up_rdata <= up_rdata_common | up_rdata_sysref | up_rdata_rx;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,411 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="1e23432a3fd14206ab7694702b9effd9"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/jesd204_up_ilas_mem.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/jesd204_up_rx.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/jesd204_up_rx_lane.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../common/up_axi.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_jesd204_rx.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_jesd204_rx_ooc.ttcl"/>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_jesd204_rx"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/axi_jesd204_rx_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,81 @@
|
||||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact [email protected] for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
|
||||
set script_dir [file dirname [info script]]
|
||||
|
||||
source "$script_dir/util_cdc_constr.tcl"
|
||||
|
||||
util_cdc_sync_data_constr {*|jesd204_up_rx:i_up_rx|sync_data:i_cdc_status}
|
||||
util_cdc_sync_data_constr {*|jesd204_up_rx:i_up_rx|sync_data:i_cdc_cfg}
|
||||
util_cdc_sync_event_constr {*|jesd204_up_sysref:i_up_sysref|sync_event:i_cdc_sysref_event}
|
||||
util_cdc_sync_bits_constr {*|jesd204_up_rx:i_up_rx|jesd204_up_rx_lane:gen_lane[*].i_up_rx_lane|sync_bits:i_cdc_status_ready}
|
||||
|
||||
# set_max_skew?
|
||||
set_false_path \
|
||||
-to [get_registers {*|jesd204_up_rx:i_up_rx|jesd204_up_rx_lane:gen_lane[*].i_up_rx_lane|up_status_latency[*]}]
|
||||
|
||||
util_cdc_sync_bits_constr {*|jesd204_up_rx:i_up_rx|jesd204_up_rx_lane:gen_lane[*].i_up_rx_lane|jesd204_up_ilas_mem:i_ilas_mem|sync_bits:i_cdc_ilas_ready}
|
||||
|
||||
set_false_path \
|
||||
-from [get_registers {*|jesd204_up_common:i_up_common|up_reset_core}] \
|
||||
-to [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[*]}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[0]}] \
|
||||
-to [get_registers {*|jesd204_up_common:i_up_common|up_reset_synchronizer_vector[*]}]
|
||||
|
||||
set_false_path \
|
||||
-to [get_pins -compatibility_mode {*|jesd204_up_common:i_up_common|up_core_reset_ext_synchronizer_vector[*]|clrn}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_registers {*|jesd204_up_common:i_up_common|up_cfg_*}] \
|
||||
-to [get_registers {*|jesd204_up_common:i_up_common|core_cfg_*}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_registers {*|jesd204_up_rx:i_up_rx|up_cfg_*}] \
|
||||
-to [get_registers {*|jesd204_up_common:i_up_common|core_extra_cfg[*]}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_registers {*|jesd204_up_sysref:i_up_sysref|up_cfg_*}] \
|
||||
-to [get_registers {*|jesd204_up_common:i_up_common|core_extra_cfg[*]}]
|
||||
@@ -0,0 +1,153 @@
|
||||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact [email protected] for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
|
||||
set axi_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
|
||||
set core_clk [get_clocks -of_objects [get_ports core_clk]]
|
||||
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -hier {*cdc_sync_stage1_reg*}] \
|
||||
[get_cells -hier {*cdc_sync_stage2_reg*}]
|
||||
|
||||
# Used for synchronizing resets with asynchronous de-assert
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -hier {up_reset_vector_reg*}] \
|
||||
[get_cells -hier {core_reset_vector_reg*}] \
|
||||
[get_cells -hier {up_reset_synchronizer_vector_reg*}] \
|
||||
[get_cells -hier {up_core_reset_ext_synchronizer_vector_reg*}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_up_rx/i_cdc_status/in_toggle_d1_reg/C}] \
|
||||
-to [get_pins {i_up_rx/i_cdc_status/i_sync_out/cdc_sync_stage1_reg[0]/D}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_up_rx/i_cdc_status/out_toggle_d1_reg/C}] \
|
||||
-to [get_pins {i_up_rx/i_cdc_status/i_sync_in/cdc_sync_stage1_reg[0]/D}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_up_rx/i_cdc_cfg/in_toggle_d1_reg/C}] \
|
||||
-to [get_pins {i_up_rx/i_cdc_cfg/i_sync_out/cdc_sync_stage1_reg[0]/D}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_up_rx/i_cdc_cfg/out_toggle_d1_reg/C}] \
|
||||
-to [get_pins {i_up_rx/i_cdc_cfg/i_sync_in/cdc_sync_stage1_reg[0]/D}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_up_sysref/i_cdc_sysref_event/in_toggle_d1_reg/C}] \
|
||||
-to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_out/cdc_sync_stage1_reg[0]/D}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_up_sysref/i_cdc_sysref_event/out_toggle_d1_reg/C}] \
|
||||
-to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_in/cdc_sync_stage1_reg[0]/D}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_up_sysref/i_cdc_sysref_event/cdc_hold_reg*/C}] \
|
||||
-to [get_pins {i_up_sysref/i_cdc_sysref_event/out_event_reg*/D}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_sync_frame_align_err/in_toggle_d1_reg/C}] \
|
||||
-to [get_pins {i_sync_frame_align_err/i_sync_out/cdc_sync_stage1_reg[0]/D}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_sync_frame_align_err/out_toggle_d1_reg/C}] \
|
||||
-to [get_pins {i_sync_frame_align_err/i_sync_in/cdc_sync_stage1_reg[0]/D}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_sync_frame_align_err/cdc_hold_reg*/C}] \
|
||||
-to [get_pins {i_sync_frame_align_err/out_event_reg*/D}]
|
||||
|
||||
# Don't place them too far appart
|
||||
set_max_delay -datapath_only \
|
||||
-from [get_pins {i_up_rx/i_cdc_status/cdc_hold_reg[*]/C}] \
|
||||
-to [get_pins {i_up_rx/i_cdc_status/out_data_reg[*]/D}] \
|
||||
[get_property -min PERIOD $axi_clk]
|
||||
|
||||
set_false_path \
|
||||
-from $core_clk \
|
||||
-to [get_pins {i_up_rx/*i_up_rx_lane/i_cdc_status_ready/cdc_sync_stage1_reg*/D}]
|
||||
|
||||
set_max_delay -datapath_only \
|
||||
-from [get_pins {i_up_rx/i_cdc_cfg/cdc_hold_reg[*]/C}] \
|
||||
-to [get_pins {i_up_rx/i_cdc_cfg/out_data_reg[*]/D}] \
|
||||
[get_property -min PERIOD $core_clk]
|
||||
|
||||
set_max_delay -datapath_only \
|
||||
-from $core_clk \
|
||||
-to [get_pins {i_up_rx/*i_up_rx_lane/up_status_latency_reg[*]/D}] \
|
||||
[get_property -min PERIOD $axi_clk]
|
||||
|
||||
set_false_path \
|
||||
-from $core_clk \
|
||||
-to [get_pins {i_up_rx/*i_up_rx_lane/i_ilas_mem/i_cdc_ilas_ready/cdc_sync_stage1_reg[0]/D}]
|
||||
|
||||
# Use -quiet here since the ILAS mem is missing in non 8b10b configuration
|
||||
set_max_delay -quiet -datapath_only \
|
||||
-from [get_pins {i_up_rx/gen_lane[*].i_up_rx_lane/i_ilas_mem/mem_reg_*/*/CLK}] \
|
||||
-to [get_pins {i_up_rx/gen_lane[*].i_up_rx_lane/i_ilas_mem/up_rdata_reg[*]/D}] \
|
||||
[get_property -min PERIOD $axi_clk]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_up_common/up_reset_core_reg/C}] \
|
||||
-to [get_pins {i_up_common/core_reset_vector_reg[*]/PRE}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_up_common/core_reset_vector_reg[0]/C}] \
|
||||
-to [get_pins {i_up_common/up_reset_synchronizer_vector_reg[*]/PRE}]
|
||||
|
||||
set_false_path \
|
||||
-to [get_pins {i_up_common/up_core_reset_ext_synchronizer_vector_reg[*]/PRE}]
|
||||
|
||||
set_max_delay -datapath_only \
|
||||
-from [get_pins {i_up_common/up_cfg_*_reg*/C}] \
|
||||
-to [get_pins {i_up_common/core_cfg_*_reg*/D}] \
|
||||
[get_property -min PERIOD $core_clk]
|
||||
|
||||
set_max_delay -datapath_only \
|
||||
-from [get_pins {i_up_rx/up_cfg_*_reg*/C}] \
|
||||
-to [get_pins {i_up_common/core_extra_cfg_reg[*]/D}] \
|
||||
[get_property -min PERIOD $core_clk]
|
||||
|
||||
set_max_delay -datapath_only \
|
||||
-from [get_pins {i_up_sysref/up_cfg_*_reg*/C}] \
|
||||
-to [get_pins {i_up_common/core_extra_cfg_reg[*]/D}] \
|
||||
[get_property -min PERIOD $core_clk]
|
||||
@@ -0,0 +1,170 @@
|
||||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact [email protected] for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
|
||||
package require qsys
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
|
||||
|
||||
ad_ip_create axi_jesd204_rx "ADI JESD204 Receive AXI Interface"
|
||||
|
||||
set_module_property INTERNAL true
|
||||
|
||||
# files
|
||||
|
||||
ad_ip_files axi_jesd204_rx [list \
|
||||
axi_jesd204_rx.v \
|
||||
axi_jesd204_rx_constr.sdc \
|
||||
jesd204_up_rx.v \
|
||||
jesd204_up_rx_lane.v \
|
||||
jesd204_up_ilas_mem.v \
|
||||
../axi_jesd204_common/jesd204_up_common.v \
|
||||
../axi_jesd204_common/jesd204_up_sysref.v \
|
||||
$ad_hdl_dir/library/common/up_axi.v \
|
||||
$ad_hdl_dir/library/common/up_clock_mon.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_bits.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_data.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_event.v \
|
||||
$ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl \
|
||||
$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
|
||||
]
|
||||
|
||||
# parameters
|
||||
|
||||
add_parameter ID NATURAL 0
|
||||
set_parameter_property ID DISPLAY_NAME "Peripheral ID"
|
||||
set_parameter_property ID HDL_PARAMETER true
|
||||
|
||||
add_parameter NUM_LANES INTEGER 1
|
||||
set_parameter_property NUM_LANES DISPLAY_NAME "Number of Lanes"
|
||||
set_parameter_property NUM_LANES ALLOWED_RANGES 1:8
|
||||
set_parameter_property NUM_LANES HDL_PARAMETER true
|
||||
|
||||
add_parameter NUM_LINKS INTEGER 1
|
||||
set_parameter_property NUM_LINKS DISPLAY_NAME "Number of Links"
|
||||
set_parameter_property NUM_LINKS ALLOWED_RANGES 1:8
|
||||
set_parameter_property NUM_LINKS HDL_PARAMETER true
|
||||
|
||||
# axi4 slave interface
|
||||
|
||||
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 14
|
||||
|
||||
# interrupt
|
||||
|
||||
add_interface interrupt interrupt end
|
||||
set_interface_property interrupt associatedClock s_axi_clock
|
||||
set_interface_property interrupt associatedReset s_axi_reset
|
||||
#set_interface_property interrupt associatedAddressablePoint s_axi
|
||||
add_interface_port interrupt irq irq Output 1
|
||||
|
||||
# core clock
|
||||
|
||||
add_interface core_clock clock end
|
||||
add_interface_port core_clock core_clk clk Input 1
|
||||
|
||||
# core reset ext
|
||||
|
||||
add_interface core_reset_ext reset end
|
||||
set_interface_property core_reset_ext associatedClock core_clock
|
||||
add_interface_port core_reset_ext core_reset_ext reset Input 1
|
||||
|
||||
# core reset
|
||||
|
||||
add_interface core_reset reset start
|
||||
set_interface_property core_reset associatedClock core_clock
|
||||
set_interface_property core_reset associatedResetSinks core_reset_ext
|
||||
add_interface_port core_reset core_reset reset Output 1
|
||||
|
||||
# config interface
|
||||
|
||||
add_interface config conduit end
|
||||
set_interface_property config associatedClock core_clock
|
||||
set_interface_property config associatedReset core_reset
|
||||
|
||||
add_interface_port config core_cfg_beats_per_multiframe beats_per_multiframe Output 8
|
||||
add_interface_port config core_cfg_buffer_delay buffer_delay Output 8
|
||||
add_interface_port config core_cfg_buffer_early_release buffer_early_release Output 1
|
||||
add_interface_port config core_cfg_disable_char_replacement disable_char_replacement Output 1
|
||||
add_interface_port config core_cfg_disable_scrambler disable_scrambler Output 1
|
||||
add_interface_port config core_cfg_lanes_disable lanes_disable Output NUM_LANES
|
||||
add_interface_port config core_cfg_links_disable links_disable Output NUM_LINKS
|
||||
add_interface_port config core_cfg_lmfc_offset lmfc_offset Output 8
|
||||
add_interface_port config core_cfg_octets_per_frame octets_per_frame Output 8
|
||||
add_interface_port config core_cfg_sysref_disable sysref_disable Output 1
|
||||
add_interface_port config core_cfg_sysref_oneshot sysref_oneshot Output 1
|
||||
add_interface_port config core_cfg_frame_align_err_threshold frame_align_err_threshold Output 8
|
||||
add_interface_port config core_ctrl_err_statistics_reset err_statistics_reset Output 1
|
||||
add_interface_port config core_ctrl_err_statistics_mask err_statistics_mask Output 3
|
||||
|
||||
# status interface
|
||||
|
||||
add_interface status conduit end
|
||||
set_interface_property status associatedClock core_clock
|
||||
set_interface_property status associatedReset core_reset
|
||||
|
||||
add_interface_port status core_status_ctrl_state ctrl_state Input 2
|
||||
add_interface_port status core_status_lane_cgs_state lane_cgs_state Input 2*NUM_LANES
|
||||
add_interface_port status core_status_lane_ifs_ready lane_ifs_ready Input NUM_LANES
|
||||
add_interface_port status core_status_lane_latency lane_latency Input 14*NUM_LANES
|
||||
add_interface_port status core_status_lane_frame_align_err_cnt lane_frame_align_err_cnt Input 8*NUM_LANES
|
||||
add_interface_port status core_status_err_statistics_cnt err_statistics_cnt Input 32*NUM_LANES
|
||||
|
||||
# event interface
|
||||
|
||||
add_interface event conduit end
|
||||
set_interface_property event associatedClock core_clock
|
||||
set_interface_property event associatedReset core_reset
|
||||
|
||||
add_interface_port event core_event_sysref_alignment_error sysref_alignment_error Input 1
|
||||
add_interface_port event core_event_sysref_edge sysref_edge Input 1
|
||||
|
||||
# ilas_config
|
||||
|
||||
add_interface ilas_config conduit end
|
||||
set_interface_property ilas_config associatedClock core_clock
|
||||
set_interface_property ilas_config associatedReset core_reset
|
||||
|
||||
add_interface_port ilas_config core_ilas_config_addr addr Input 2*NUM_LANES
|
||||
add_interface_port ilas_config core_ilas_config_data data Input 32*NUM_LANES
|
||||
add_interface_port ilas_config core_ilas_config_valid valid Input NUM_LANES
|
||||
@@ -0,0 +1,840 @@
|
||||
|
||||
****** Vivado v2019.1.3 (64-bit)
|
||||
**** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
**** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
source axi_jesd204_rx_ip.tcl
|
||||
# source ../../scripts/adi_env.tcl
|
||||
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
|
||||
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
|
||||
## if [info exists ::env(ADI_HDL_DIR)] {
|
||||
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
|
||||
## }
|
||||
## if [info exists ::env(ADI_GHDL_DIR)] {
|
||||
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
|
||||
## }
|
||||
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
|
||||
### variable auto_set_param_list
|
||||
### variable auto_set_param_list_overwritable
|
||||
### variable fpga_series_list
|
||||
### variable fpga_family_list
|
||||
### variable speed_grade_list
|
||||
### variable dev_package_list
|
||||
### variable xcvr_type_list
|
||||
### variable fpga_voltage_list
|
||||
### set auto_set_param_list { \
|
||||
### DEV_PACKAGE \
|
||||
### SPEED_GRADE \
|
||||
### FPGA_FAMILY \
|
||||
### FPGA_TECHNOLOGY }
|
||||
### set auto_set_param_list_overwritable { \
|
||||
### FPGA_VOLTAGE \
|
||||
### XCVR_TYPE }
|
||||
### set fpga_technology_list { \
|
||||
### { Unknown 0 } \
|
||||
### { 7series 1 } \
|
||||
### { ultrascale 2 } \
|
||||
### { ultrascale+ 3 }}
|
||||
### set fpga_family_list { \
|
||||
### { Unknown 0 } \
|
||||
### { artix 1 } \
|
||||
### { kintex 2 } \
|
||||
### { virtex 3 } \
|
||||
### { zynq 4 }}
|
||||
### set speed_grade_list { \
|
||||
### { Unknown 0 } \
|
||||
### { -1 10 } \
|
||||
### { -1L 11 } \
|
||||
### { -1H 12 } \
|
||||
### { -1HV 13 } \
|
||||
### { -1LV 14 } \
|
||||
### { -2 20 } \
|
||||
### { -2L 21 } \
|
||||
### { -2LV 22 } \
|
||||
### { -3 30 }}
|
||||
### set dev_package_list { \
|
||||
### { Unknown 0 } \
|
||||
### { rf 1 } \
|
||||
### { fl 2 } \
|
||||
### { ff 3 } \
|
||||
### { fb 4 } \
|
||||
### { hc 5 } \
|
||||
### { fh 6 } \
|
||||
### { cs 7 } \
|
||||
### { cp 8 } \
|
||||
### { ft 9 } \
|
||||
### { fg 10 } \
|
||||
### { sb 11 } \
|
||||
### { rb 12 } \
|
||||
### { rs 13 } \
|
||||
### { cl 14 } \
|
||||
### { sf 15 } \
|
||||
### { ba 16 } \
|
||||
### { fa 17 } \
|
||||
### { fs 18 } \
|
||||
### { fi 19 }}
|
||||
### set xcvr_type_list { \
|
||||
### { Unknown 0 } \
|
||||
### { GTPE2_NOT_SUPPORTED 1 } \
|
||||
### { GTXE2 2 } \
|
||||
### { GTHE2_NOT_SUPPORTED 3 } \
|
||||
### { GTZE2_NOT_SUPPORTED 4 } \
|
||||
### { GTHE3 5 } \
|
||||
### { GTYE3_NOT_SUPPORTED 6 } \
|
||||
### { GTRE4_NOT_SUPPORTED 7 } \
|
||||
### { GTHE4 8 } \
|
||||
### { GTYE4 9 } \
|
||||
### { GTME4_NOT_SUPPORTED 10}}
|
||||
### set fpga_voltage_list {0 5000} ;
|
||||
### proc adi_device_spec {cellpath param} {
|
||||
###
|
||||
### set list_pointer [string tolower $param]
|
||||
### set list_pointer [append list_pointer "_list"]
|
||||
###
|
||||
### upvar 1 $list_pointer $list_pointer
|
||||
###
|
||||
### set ip [get_bd_cells $cellpath]
|
||||
### set part [get_property PART [current_project]]
|
||||
###
|
||||
### switch -regexp -- $param {
|
||||
### FPGA_TECHNOLOGY {
|
||||
### switch -regexp -- $part {
|
||||
### ^xc7 {set series_name 7series}
|
||||
### ^xczu {set series_name ultrascale+}
|
||||
### ^xc.u.p {set series_name ultrascale+}
|
||||
### ^xc.u {set series_name ultrascale }
|
||||
### default {
|
||||
### puts "Undefined fpga technology for \"$part\"!"
|
||||
### exit -1
|
||||
### }
|
||||
### }
|
||||
### return "$series_name"
|
||||
### }
|
||||
### FPGA_FAMILY {
|
||||
### set fpga_family [get_property FAMILY $part]
|
||||
### foreach i $fpga_family_list {
|
||||
### regexp ^[lindex $i 0] $fpga_family matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### SPEED_GRADE {
|
||||
### set speed_grade [get_property SPEED $part]
|
||||
### return "$speed_grade"
|
||||
### }
|
||||
### DEV_PACKAGE {
|
||||
### set dev_package [get_property PACKAGE $part]
|
||||
### foreach i $dev_package_list {
|
||||
### regexp ^[lindex $i 0] $dev_package matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### XCVR_TYPE {
|
||||
### set matched ""
|
||||
### set dev_transcivers "none"
|
||||
### foreach x [list_property $part] {
|
||||
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
|
||||
### }
|
||||
### foreach i $xcvr_type_list {
|
||||
### regexp ^[lindex $i 0] $dev_transcivers matched
|
||||
### }
|
||||
### if { $matched eq "" } {
|
||||
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### FPGA_VOLTAGE {
|
||||
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
|
||||
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
|
||||
###
|
||||
### return "$fpga_voltage"
|
||||
### }
|
||||
### default {
|
||||
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
|
||||
### }
|
||||
### }
|
||||
### }
|
||||
## if {![info exists REQUIRED_VIVADO_VERSION]} {
|
||||
## set REQUIRED_VIVADO_VERSION "2019.1"
|
||||
## }
|
||||
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
|
||||
## set IGNORE_VERSION_CHECK 1
|
||||
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
|
||||
## set IGNORE_VERSION_CHECK 0
|
||||
## }
|
||||
## proc adi_ip_ttcl {ip_name ip_constr_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
|
||||
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_sim_ttcl {ip_name ip_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
|
||||
## set f [ipx::add_file $ip_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_bd {ip_name ip_bd_files} {
|
||||
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
|
||||
## if {$proj_filegroup == {}} {
|
||||
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
|
||||
## }
|
||||
##
|
||||
## foreach file $ip_bd_files {
|
||||
## set f [ipx::add_file $file $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type tclSource \
|
||||
## ] $f
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_infer_streaming_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_ip_infer_mm_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
|
||||
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency $port
|
||||
## if {$driver_value != {}} {
|
||||
## set_property DRIVER_VALUE $driver_value $port
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_set_bus_dependency {bus prefix dependency} {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
|
||||
## adi_set_ports_dependency $prefix $dependency 0
|
||||
## }
|
||||
## proc adi_add_port_map {bus phys logic} {
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## }
|
||||
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## adi_add_port_map $bus {*}$port_map
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
|
||||
## for {set i 0} {$i < $num} {incr i} {
|
||||
## set bus_name [format "%s%d" $bus_name_prefix $i]
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## if {$dependency ne ""} {
|
||||
## set bus_dependency [string map [list "{i}" $i] $dependency]
|
||||
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
|
||||
## }
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## lassign $port_map phys logic width width_dep
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
|
||||
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
|
||||
## if {$width_dep ne ""} {
|
||||
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
|
||||
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
|
||||
## set width_dep_r "(($width_dep) * $i)"
|
||||
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
|
||||
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
|
||||
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
|
||||
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
|
||||
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
|
||||
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
|
||||
## set_property display_name $clock_inf_name $clock_inf
|
||||
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
|
||||
## set_property physical_name $clock_signal_name $clock_map
|
||||
##
|
||||
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
|
||||
## set_property value $bus_inf_name $assoc_busif
|
||||
##
|
||||
## if { $reset_signal_name != "" } {
|
||||
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
|
||||
## set_property value $reset_signal_name $assoc_reset
|
||||
##
|
||||
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
|
||||
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
|
||||
## set_property display_name $reset_inf_name $reset_inf
|
||||
## set_property interface_mode $reset_signal_mode $reset_inf
|
||||
## set reset_map [ipx::add_port_map "RST" $reset_inf]
|
||||
## set_property physical_name $reset_signal_name $reset_map
|
||||
##
|
||||
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
|
||||
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
|
||||
## set_property value "ACTIVE_LOW" $reset_polarity
|
||||
## } else {
|
||||
## set_property value "ACTIVE_HIGH" $reset_polarity
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_add_core_dependencies {vlnvs} {
|
||||
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
|
||||
## foreach vlnv $vlnvs {
|
||||
## ipx::add_subcore $vlnv $file_group
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_create {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
## global ad_ghdl_dir
|
||||
## global REQUIRED_VIVADO_VERSION
|
||||
## global IGNORE_VERSION_CHECK
|
||||
##
|
||||
## set VIVADO_VERSION [version -short]
|
||||
## if {$IGNORE_VERSION_CHECK} {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## }
|
||||
## } else {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "ERROR: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
|
||||
## exit 2
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## create_project $ip_name . -force
|
||||
##
|
||||
## ## Load custom message severity definitions
|
||||
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
|
||||
##
|
||||
## set lib_dirs $ad_hdl_dir/library
|
||||
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
|
||||
## lappend lib_dirs $ad_ghdl_dir/library
|
||||
## }
|
||||
##
|
||||
## set_property ip_repo_paths $lib_dirs [current_fileset]
|
||||
## update_ip_catalog
|
||||
## }
|
||||
## proc adi_ip_files {ip_name ip_files} {
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## foreach m_file $ip_files {
|
||||
## if {[file extension $m_file] eq ".xdc"} {
|
||||
## add_files -norecurse -fileset constrs_1 $m_file
|
||||
## } else {
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
|
||||
## }
|
||||
## }
|
||||
## set_property "top" "$ip_name" $proj_fileset
|
||||
## }
|
||||
## proc adi_ip_properties_lite {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
##
|
||||
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
|
||||
##
|
||||
## set_property name $ip_name [ipx::current_core]
|
||||
##
|
||||
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
|
||||
## set_property company_url {http://www.analog.com} [ipx::current_core]
|
||||
##
|
||||
## set i_families ""
|
||||
## foreach i_part [get_parts] {
|
||||
## lappend i_families [get_property FAMILY $i_part]
|
||||
## }
|
||||
## set i_families [lsort -unique $i_families]
|
||||
## set s_families [get_property supported_families [ipx::current_core]]
|
||||
## foreach i_family $i_families {
|
||||
## set s_families "$s_families $i_family Production"
|
||||
## set s_families "$s_families $i_family Beta"
|
||||
## }
|
||||
## set_property supported_families $s_families [ipx::current_core]
|
||||
##
|
||||
## ipx::save_core [ipx::current_core]
|
||||
##
|
||||
## ipx::remove_all_bus_interface [ipx::current_core]
|
||||
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
|
||||
## foreach map $memory_maps {
|
||||
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
|
||||
## }
|
||||
##
|
||||
## ipx::update_checksums [ipx::current_core]
|
||||
## ipx::save_core [ipx::current_core]
|
||||
## }
|
||||
## proc adi_ip_properties {ip_name} {
|
||||
##
|
||||
## adi_ip_properties_lite $ip_name
|
||||
##
|
||||
## ipx::infer_bus_interface {\
|
||||
## s_axi_awvalid \
|
||||
## s_axi_awaddr \
|
||||
## s_axi_awprot \
|
||||
## s_axi_awready \
|
||||
## s_axi_wvalid \
|
||||
## s_axi_wdata \
|
||||
## s_axi_wstrb \
|
||||
## s_axi_wready \
|
||||
## s_axi_bvalid \
|
||||
## s_axi_bresp \
|
||||
##
|
||||
## s_axi_bready \
|
||||
## s_axi_arvalid \
|
||||
## s_axi_araddr \
|
||||
## s_axi_arprot \
|
||||
## s_axi_arready \
|
||||
## s_axi_rvalid \
|
||||
## s_axi_rdata \
|
||||
## s_axi_rresp \
|
||||
## s_axi_rready} \
|
||||
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
|
||||
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
|
||||
##
|
||||
## if {$raddr_width != $waddr_width} {
|
||||
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
|
||||
## set range 65536
|
||||
## } else {
|
||||
## if {$raddr_width >= 16} {
|
||||
## set range 65536
|
||||
## } else {
|
||||
## set range [expr 1 << $raddr_width]
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
## set_property range $range [ipx::get_address_blocks axi_lite \
|
||||
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
|
||||
## ipx::save_core
|
||||
## }
|
||||
## proc adi_init_bd_tcl {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## if { [file exists bd] } {
|
||||
## file delete -force bd
|
||||
## }
|
||||
## file mkdir bd
|
||||
##
|
||||
## set bd_tcl [open "bd/bd.tcl" w]
|
||||
##
|
||||
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
|
||||
## puts $bd_tcl "proc init {cellpath otherInfo} {"
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl ""
|
||||
## set auto_set_param ""
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
|
||||
## puts $bd_tcl $auto_set_param
|
||||
## }
|
||||
##
|
||||
## set auto_set_overwritable_param ""
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_overwritable_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_overwritable_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
|
||||
## puts $bd_tcl $auto_set_overwritable_param
|
||||
## }
|
||||
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
|
||||
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
|
||||
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set parent_dir \"../\""
|
||||
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
|
||||
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
|
||||
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " break"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " append parent_dir \"../\""
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## close $bd_tcl
|
||||
##
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
|
||||
##
|
||||
## set local_mk [open "temporary_case_dependencies.mk" w]
|
||||
## seek $local_mk 0 start
|
||||
## puts $local_mk "CLEAN_TARGET += bd"
|
||||
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
|
||||
## close $local_mk
|
||||
## }
|
||||
## proc adi_add_auto_fpga_spec_params {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_device_spec_param {ip_param} {
|
||||
##
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## set list_pointer [string tolower $ip_param]
|
||||
## set list_pointer [append list_pointer "_list"]
|
||||
##
|
||||
## global $list_pointer
|
||||
##
|
||||
## # set j 1D list from the original list
|
||||
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
|
||||
##
|
||||
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
|
||||
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "range_long" \
|
||||
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
|
||||
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## } else {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "pairs" \
|
||||
## "value_validation_pairs" $j ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## }
|
||||
##
|
||||
## # FPGA info grup
|
||||
## set info_group_name "FPGA info"
|
||||
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
|
||||
## if { [string trim $info_group] eq "" } {
|
||||
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
|
||||
## -parent $page0 -display_name $info_group_name]
|
||||
## }
|
||||
##
|
||||
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
|
||||
## set_property -dict [list "widget" "comboBox" ] $p
|
||||
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
|
||||
## }
|
||||
## proc adi_if_define {name} {
|
||||
##
|
||||
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
|
||||
## ipx::create_bus_definition analog.com interface $name 1.0
|
||||
##
|
||||
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
|
||||
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
|
||||
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
|
||||
##
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## }
|
||||
## proc adi_if_ports {dir width name {type none}} {
|
||||
##
|
||||
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
|
||||
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
|
||||
## set_property master_presence required $m_intf
|
||||
## set_property slave_presence required $m_intf
|
||||
## set_property master_width $width $m_intf
|
||||
## set_property slave_width $width $m_intf
|
||||
##
|
||||
## set m_dir "in"
|
||||
## set s_dir "out"
|
||||
## if {$dir eq "output"} {
|
||||
## set m_dir "out"
|
||||
## set s_dir "in"
|
||||
## }
|
||||
##
|
||||
## set_property master_direction $m_dir $m_intf
|
||||
## set_property slave_direction $s_dir $m_intf
|
||||
##
|
||||
## if {$type ne "none"} {
|
||||
## set_property is_${type} true $m_intf
|
||||
## }
|
||||
##
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## }
|
||||
## proc adi_if_infer_bus {if_name mode name maps} {
|
||||
##
|
||||
## ipx::add_bus_interface $name [ipx::current_core]
|
||||
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
|
||||
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
|
||||
## set_property interface_mode $mode $m_bus_if
|
||||
##
|
||||
## foreach map $maps {
|
||||
## set m_maps [regexp -all -inline {\S+} $map]
|
||||
## lassign $m_maps p_name p_map
|
||||
## ipx::add_port_map $p_name $m_bus_if
|
||||
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
|
||||
## }
|
||||
## }
|
||||
# adi_ip_create axi_jesd204_rx
|
||||
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
|
||||
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1343} -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1306} -new_severity WARNING
|
||||
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
|
||||
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
|
||||
## set_msg_config -id {Synth 8-3331} -new_severity INFO
|
||||
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
|
||||
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
|
||||
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
|
||||
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx'.)
|
||||
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
|
||||
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
|
||||
# adi_ip_files axi_jesd204_rx [list \
|
||||
# "../../common/up_axi.v" \
|
||||
# "jesd204_up_rx.v" \
|
||||
# "jesd204_up_rx_lane.v" \
|
||||
# "jesd204_up_ilas_mem.v" \
|
||||
# "axi_jesd204_rx_constr.xdc" \
|
||||
# "axi_jesd204_rx_ooc.ttcl" \
|
||||
# "axi_jesd204_rx.v" \
|
||||
# ]
|
||||
# adi_ip_properties axi_jesd204_rx
|
||||
WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl' ignored by IP packager.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
WARNING: [IP_Flow 19-5150] The Range '((32 * NUM_LANES) - 1):0' is present in all ports of the interface 'core_ilas_config'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_ilas_config' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_reset on bus interface abstraction jesd204_rx_cfg_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_mask on bus interface abstraction jesd204_rx_cfg_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_cfg' of definition 'analog.com:interface:jesd204_rx_cfg:1.0' (from User Repositories).
|
||||
INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 'core_status_ctrl'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
||||
WARNING: [IP_Flow 19-5150] The Range '((2 * NUM_LANES) - 1):0' is present in all ports of the interface 'core_status_lane_cgs'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5150] The Range '((3 * NUM_LANES) - 1):0' is present in all ports of the interface 'core_status_lane_emb'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port sync on bus interface abstraction jesd204_tx_status_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_event_unexpected_lane_error' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port sync on bus interface abstraction jesd204_tx_status_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status_ctrl_0' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port sync on bus interface abstraction jesd204_tx_status_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status_ctrl_1' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port sync on bus interface abstraction jesd204_tx_status_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status_lane_cgs' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port sync on bus interface abstraction jesd204_tx_status_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status_lane_emb' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5150] The Range '((8 * NUM_LANES) - 1):0' is present in all ports of the interface 'core_status_err_cnt'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port lane_frame_align on bus interface abstraction jesd204_rx_status_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port lane_latency_ready on bus interface abstraction jesd204_rx_status_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status' of definition 'analog.com:interface:jesd204_rx_status:1.0' (from User Repositories).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_event' of definition 'analog.com:interface:jesd204_tx_event:1.0' (from User Repositories).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_ctrl_err_statistics_reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'core_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'core_ctrl_err_statistics_reset'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'core_ilas_config': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_lanes_disable' and definition port 'lanes_disable'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_links_disable' and definition port 'links_disable'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_beats_per_multiframe' and definition port 'beats_per_multiframe'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_octets_per_frame' and definition port 'octets_per_frame'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_lmfc_offset' and definition port 'lmfc_offset'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_buffer_early_release' and definition port 'buffer_early_release'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_buffer_delay' and definition port 'buffer_delay'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_disable_char_replacement' and definition port 'disable_char_replacement'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_disable_scrambler' and definition port 'disable_scrambler'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_frame_align_err_threshold' and definition port 'frame_align_err_threshold'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'core_cfg': A port map to the required logical port "err_statistics_reset" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'core_cfg': A port map to the required logical port "err_statistics_mask" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'core_event_unexpected_lane_error': A port map to the required logical port "sync" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'core_status_ctrl_0': A port map to the required logical port "sync" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'core_status_ctrl_1': A port map to the required logical port "sync" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'core_status_lane_cgs': A port map to the required logical port "sync" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'core_status_lane_emb': A port map to the required logical port "sync" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'core_status': A port map to the required logical port "lane_frame_align" of the bus abstraction "analog.com:interface:jesd204_rx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'core_status': A port map to the required logical port "lane_latency_ready" of the bus abstraction "analog.com:interface:jesd204_rx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'core_clk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
||||
# adi_ip_ttcl axi_jesd204_rx "axi_jesd204_rx_ooc.ttcl"
|
||||
# set_property PROCESSING_ORDER LATE [ipx::get_files axi_jesd204_rx_constr.xdc \
|
||||
# -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \
|
||||
# -filter {NAME =~ *synthesis*}]]
|
||||
# adi_ip_add_core_dependencies { \
|
||||
# analog.com:user:axi_jesd204_common:1.0 \
|
||||
# }
|
||||
# set_property display_name "ADI JESD204C Receive AXI Interface" [ipx::current_core]
|
||||
# set_property description "ADI JESD204C Receive AXI Interface" [ipx::current_core]
|
||||
# adi_add_bus "rx_cfg" "master" \
|
||||
# "analog.com:interface:jesd204_rx_cfg_rtl:1.0" \
|
||||
# "analog.com:interface:jesd204_rx_cfg:1.0" \
|
||||
# { \
|
||||
# { "core_cfg_lanes_disable" "lanes_disable" } \
|
||||
# { "core_cfg_links_disable" "links_disable" } \
|
||||
# { "core_cfg_beats_per_multiframe" "beats_per_multiframe" } \
|
||||
# { "core_cfg_octets_per_frame" "octets_per_frame" } \
|
||||
# { "core_cfg_lmfc_offset" "lmfc_offset" } \
|
||||
# { "core_cfg_sysref_oneshot" "sysref_oneshot" } \
|
||||
# { "core_cfg_sysref_disable" "sysref_disable" } \
|
||||
# { "core_ctrl_err_statistics_reset" "err_statistics_reset" } \
|
||||
# { "core_ctrl_err_statistics_mask" "err_statistics_mask" } \
|
||||
# { "core_cfg_buffer_early_release" "buffer_early_release" } \
|
||||
# { "core_cfg_buffer_delay" "buffer_delay" } \
|
||||
# { "core_cfg_disable_char_replacement" "disable_char_replacement" } \
|
||||
# { "core_cfg_disable_scrambler" "disable_scrambler" } \
|
||||
# { "core_cfg_frame_align_err_threshold" "frame_align_err_threshold" } \
|
||||
# }
|
||||
# adi_add_bus "rx_ilas_config" "slave" \
|
||||
# "analog.com:interface:jesd204_rx_ilas_config_rtl:1.0" \
|
||||
# "analog.com:interface:jesd204_rx_ilas_config:1.0" \
|
||||
# { \
|
||||
# { "core_ilas_config_valid" "valid" } \
|
||||
# { "core_ilas_config_addr" "addr" } \
|
||||
# { "core_ilas_config_data" "data" } \
|
||||
# }
|
||||
# adi_add_bus "rx_event" "slave" \
|
||||
# "analog.com:interface:jesd204_rx_event_rtl:1.0" \
|
||||
# "analog.com:interface:jesd204_rx_event:1.0" \
|
||||
# { \
|
||||
# { "core_event_sysref_alignment_error" "sysref_alignment_error" } \
|
||||
# { "core_event_sysref_edge" "sysref_edge" } \
|
||||
# { "core_event_frame_alignment_error" "frame_alignment_error" } \
|
||||
# { "core_event_unexpected_lane_state_error" "unexpected_lane_state_error" } \
|
||||
# }
|
||||
# adi_add_bus "rx_status" "slave" \
|
||||
# "analog.com:interface:jesd204_rx_status_rtl:1.0" \
|
||||
# "analog.com:interface:jesd204_rx_status:1.0" \
|
||||
# { \
|
||||
# { "core_status_ctrl_state" "ctrl_state" } \
|
||||
# { "core_status_lane_cgs_state" "lane_cgs_state" } \
|
||||
# { "core_status_lane_emb_state" "lane_emb_state" } \
|
||||
# { "core_status_lane_ifs_ready" "lane_ifs_ready" } \
|
||||
# { "core_status_lane_latency" "lane_latency" } \
|
||||
# { "core_status_lane_frame_align_err_cnt" "lane_frame_align_err_cnt" } \
|
||||
# { "core_status_err_statistics_cnt" "err_statistics_cnt" } \
|
||||
# }
|
||||
# ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
|
||||
# adi_add_bus_clock "core_clk" "rx_status:rx_event:rx_ilas_config:rx_cfg" \
|
||||
# "core_reset" "master"
|
||||
# set_property DRIVER_VALUE "0" [ipx::get_ports "core_reset_ext"]
|
||||
# adi_set_bus_dependency "rx_ilas_config" "rx_ilas_config" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
|
||||
# set cc [ipx::current_core]
|
||||
# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
# set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
|
||||
# ipgui::move_param -component $cc -order 0 $p -parent $page0
|
||||
# set_property -dict [list \
|
||||
# "display_name" "Link Layer mode" \
|
||||
# "tooltip" "Link Layer mode" \
|
||||
# "widget" "comboBox" \
|
||||
# ] $p
|
||||
# set_property -dict [list \
|
||||
# value_validation_type pairs \
|
||||
# value_validation_pairs {64B66B 2 8B10B 1} \
|
||||
# ] [ipx::get_user_parameters $p -of_objects $cc]
|
||||
# ipx::create_xgui_files [ipx::current_core]
|
||||
# ipx::save_core [ipx::current_core]
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:24:55 2021...
|
||||
@@ -0,0 +1,153 @@
|
||||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact [email protected] for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_jesd204_rx
|
||||
adi_ip_files axi_jesd204_rx [list \
|
||||
"../../common/up_axi.v" \
|
||||
"jesd204_up_rx.v" \
|
||||
"jesd204_up_rx_lane.v" \
|
||||
"jesd204_up_ilas_mem.v" \
|
||||
"axi_jesd204_rx_constr.xdc" \
|
||||
"axi_jesd204_rx_ooc.ttcl" \
|
||||
"axi_jesd204_rx.v" \
|
||||
]
|
||||
|
||||
adi_ip_properties axi_jesd204_rx
|
||||
|
||||
adi_ip_ttcl axi_jesd204_rx "axi_jesd204_rx_ooc.ttcl"
|
||||
|
||||
set_property PROCESSING_ORDER LATE [ipx::get_files axi_jesd204_rx_constr.xdc \
|
||||
-of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \
|
||||
-filter {NAME =~ *synthesis*}]]
|
||||
|
||||
adi_ip_add_core_dependencies { \
|
||||
analog.com:user:axi_jesd204_common:1.0 \
|
||||
}
|
||||
|
||||
set_property display_name "ADI JESD204C Receive AXI Interface" [ipx::current_core]
|
||||
set_property description "ADI JESD204C Receive AXI Interface" [ipx::current_core]
|
||||
|
||||
adi_add_bus "rx_cfg" "master" \
|
||||
"analog.com:interface:jesd204_rx_cfg_rtl:1.0" \
|
||||
"analog.com:interface:jesd204_rx_cfg:1.0" \
|
||||
{ \
|
||||
{ "core_cfg_lanes_disable" "lanes_disable" } \
|
||||
{ "core_cfg_links_disable" "links_disable" } \
|
||||
{ "core_cfg_beats_per_multiframe" "beats_per_multiframe" } \
|
||||
{ "core_cfg_octets_per_frame" "octets_per_frame" } \
|
||||
{ "core_cfg_lmfc_offset" "lmfc_offset" } \
|
||||
{ "core_cfg_sysref_oneshot" "sysref_oneshot" } \
|
||||
{ "core_cfg_sysref_disable" "sysref_disable" } \
|
||||
{ "core_ctrl_err_statistics_reset" "err_statistics_reset" } \
|
||||
{ "core_ctrl_err_statistics_mask" "err_statistics_mask" } \
|
||||
{ "core_cfg_buffer_early_release" "buffer_early_release" } \
|
||||
{ "core_cfg_buffer_delay" "buffer_delay" } \
|
||||
{ "core_cfg_disable_char_replacement" "disable_char_replacement" } \
|
||||
{ "core_cfg_disable_scrambler" "disable_scrambler" } \
|
||||
{ "core_cfg_frame_align_err_threshold" "frame_align_err_threshold" } \
|
||||
}
|
||||
|
||||
adi_add_bus "rx_ilas_config" "slave" \
|
||||
"analog.com:interface:jesd204_rx_ilas_config_rtl:1.0" \
|
||||
"analog.com:interface:jesd204_rx_ilas_config:1.0" \
|
||||
{ \
|
||||
{ "core_ilas_config_valid" "valid" } \
|
||||
{ "core_ilas_config_addr" "addr" } \
|
||||
{ "core_ilas_config_data" "data" } \
|
||||
}
|
||||
|
||||
adi_add_bus "rx_event" "slave" \
|
||||
"analog.com:interface:jesd204_rx_event_rtl:1.0" \
|
||||
"analog.com:interface:jesd204_rx_event:1.0" \
|
||||
{ \
|
||||
{ "core_event_sysref_alignment_error" "sysref_alignment_error" } \
|
||||
{ "core_event_sysref_edge" "sysref_edge" } \
|
||||
{ "core_event_frame_alignment_error" "frame_alignment_error" } \
|
||||
{ "core_event_unexpected_lane_state_error" "unexpected_lane_state_error" } \
|
||||
}
|
||||
|
||||
adi_add_bus "rx_status" "slave" \
|
||||
"analog.com:interface:jesd204_rx_status_rtl:1.0" \
|
||||
"analog.com:interface:jesd204_rx_status:1.0" \
|
||||
{ \
|
||||
{ "core_status_ctrl_state" "ctrl_state" } \
|
||||
{ "core_status_lane_cgs_state" "lane_cgs_state" } \
|
||||
{ "core_status_lane_emb_state" "lane_emb_state" } \
|
||||
{ "core_status_lane_ifs_ready" "lane_ifs_ready" } \
|
||||
{ "core_status_lane_latency" "lane_latency" } \
|
||||
{ "core_status_lane_frame_align_err_cnt" "lane_frame_align_err_cnt" } \
|
||||
{ "core_status_err_statistics_cnt" "err_statistics_cnt" } \
|
||||
}
|
||||
|
||||
ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core]
|
||||
|
||||
adi_add_bus_clock "core_clk" "rx_status:rx_event:rx_ilas_config:rx_cfg" \
|
||||
"core_reset" "master"
|
||||
|
||||
set_property DRIVER_VALUE "0" [ipx::get_ports "core_reset_ext"]
|
||||
|
||||
adi_set_bus_dependency "rx_ilas_config" "rx_ilas_config" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
|
||||
set cc [ipx::current_core]
|
||||
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
|
||||
# Link layer mode
|
||||
set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
|
||||
ipgui::move_param -component $cc -order 0 $p -parent $page0
|
||||
set_property -dict [list \
|
||||
"display_name" "Link Layer mode" \
|
||||
"tooltip" "Link Layer mode" \
|
||||
"widget" "comboBox" \
|
||||
] $p
|
||||
|
||||
set_property -dict [list \
|
||||
value_validation_type pairs \
|
||||
value_validation_pairs {64B66B 2 8B10B 1} \
|
||||
] [ipx::get_user_parameters $p -of_objects $cc]
|
||||
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,61 @@
|
||||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact [email protected] for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
|
||||
<: setFileUsedIn { out_of_context synthesis implementation } :>
|
||||
<: ;#Component and file information :>
|
||||
<: set ComponentName [getComponentNameString] :>
|
||||
<: setOutputDirectory "./" :>
|
||||
<: setFileName $ComponentName :>
|
||||
<: setFileExtension "_ooc.xdc" :>
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation.
|
||||
# These are default values for timing driven synthesis during OOC flow.
|
||||
# These values will be overwritten during implementation with information
|
||||
# from top level.
|
||||
|
||||
create_clock -name s_axi_aclk -period 10 [get_ports s_axi_aclk]
|
||||
create_clock -name core_clk -period 2.5 [get_ports core_clk]
|
||||
|
||||
################################################################################
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,122 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_up_ilas_mem (
|
||||
input up_clk,
|
||||
|
||||
input up_rreq,
|
||||
input [1:0] up_raddr,
|
||||
output reg [31:0] up_rdata,
|
||||
|
||||
input core_clk,
|
||||
input core_reset,
|
||||
|
||||
input core_ilas_config_valid,
|
||||
input [1:0] core_ilas_config_addr,
|
||||
input [31:0] core_ilas_config_data,
|
||||
|
||||
output up_ilas_ready
|
||||
);
|
||||
|
||||
reg [31:0] mem[0:3];
|
||||
reg core_ilas_captured = 1'b0;
|
||||
|
||||
sync_bits i_cdc_ilas_ready (
|
||||
.in_bits(core_ilas_captured),
|
||||
.out_resetn(1'b1),
|
||||
.out_clk(up_clk),
|
||||
.out_bits(up_ilas_ready)
|
||||
);
|
||||
|
||||
always @(posedge core_clk) begin
|
||||
if (core_reset == 1'b1) begin
|
||||
core_ilas_captured <= 1'b0;
|
||||
end else begin
|
||||
if (core_ilas_config_valid == 1'b1 && core_ilas_config_addr == 'h3) begin
|
||||
core_ilas_captured <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rreq == 1'b1) begin
|
||||
up_rdata <= mem[up_raddr];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge core_clk) begin
|
||||
if (core_ilas_config_valid == 1'b1) begin
|
||||
mem[core_ilas_config_addr] <= core_ilas_config_data;
|
||||
end
|
||||
end
|
||||
|
||||
/*
|
||||
* Shift register with variable tap for accessing the stored data.
|
||||
*
|
||||
* This has slightly better utilization on Xilinx based platforms than the dual
|
||||
* port RAM approach, but there is no equivalent primitive on Intel resulting
|
||||
* in increased utilization since it needs to be implemented used registers and
|
||||
* muxes.
|
||||
*
|
||||
* We might make this a device dependent configuration option at some point.
|
||||
|
||||
reg [3:0] mem[0:31];
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
for (i = 0; i < 32; i = i + 1) begin: gen_ilas_mem
|
||||
assign up_rdata[i] = mem[i][~up_raddr];
|
||||
|
||||
always @(posedge core_clk) begin
|
||||
if (core_ilas_config_valid == 1'b1) begin
|
||||
mem[i] <= {mem[i][2:0],core_ilas_config_data[i]};
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
*/
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,237 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_up_rx # (
|
||||
parameter NUM_LANES = 1,
|
||||
parameter DATA_PATH_WIDTH = 2
|
||||
) (
|
||||
input up_clk,
|
||||
input up_reset,
|
||||
input up_reset_synchronizer,
|
||||
|
||||
input up_rreq,
|
||||
input [11:0] up_raddr,
|
||||
output reg [31:0] up_rdata,
|
||||
input up_wreq,
|
||||
input [11:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
|
||||
input core_clk,
|
||||
input core_reset,
|
||||
|
||||
input [NUM_LANES-1:0] core_ilas_config_valid,
|
||||
input [2*NUM_LANES-1:0] core_ilas_config_addr,
|
||||
input [32*NUM_LANES-1:0] core_ilas_config_data,
|
||||
|
||||
input [1:0] core_status_ctrl_state,
|
||||
input [2*NUM_LANES-1:0] core_status_lane_cgs_state,
|
||||
input [3*NUM_LANES-1:0] core_status_lane_emb_state,
|
||||
input [NUM_LANES-1:0] core_status_lane_ifs_ready,
|
||||
input [14*NUM_LANES-1:0] core_status_lane_latency,
|
||||
input [8*NUM_LANES-1:0] core_status_lane_frame_align_err_cnt,
|
||||
|
||||
input [32*NUM_LANES-1:0] core_status_err_statistics_cnt,
|
||||
output [6:0] core_ctrl_err_statistics_mask,
|
||||
output core_ctrl_err_statistics_reset,
|
||||
|
||||
input up_cfg_is_writeable,
|
||||
output reg up_cfg_buffer_early_release,
|
||||
output reg [7:0] up_cfg_buffer_delay,
|
||||
|
||||
output reg [7:0] up_cfg_frame_align_err_threshold
|
||||
);
|
||||
|
||||
localparam ELASTIC_BUFFER_SIZE = 256;
|
||||
|
||||
wire [1:0] up_status_ctrl_state;
|
||||
wire [2*NUM_LANES-1:0] up_status_lane_cgs_state;
|
||||
wire [8*NUM_LANES-1:0] up_status_lane_frame_align_err_cnt;
|
||||
wire [3*NUM_LANES-1:0] up_status_lane_emb_state;
|
||||
wire [31:0] up_lane_rdata[0:NUM_LANES-1];
|
||||
wire [32*NUM_LANES-1:0] up_status_err_statistics_cnt;
|
||||
|
||||
reg up_ctrl_err_statistics_reset = 0;
|
||||
reg [6:0] up_ctrl_err_statistics_mask = 7'h0;
|
||||
|
||||
sync_data #(
|
||||
.NUM_OF_BITS(2+NUM_LANES*(3+2+32+8))
|
||||
) i_cdc_status (
|
||||
.in_clk(core_clk),
|
||||
.in_data({
|
||||
core_status_err_statistics_cnt,
|
||||
core_status_ctrl_state,
|
||||
core_status_lane_cgs_state,
|
||||
core_status_lane_emb_state,
|
||||
core_status_lane_frame_align_err_cnt
|
||||
}),
|
||||
.out_clk(up_clk),
|
||||
.out_data({
|
||||
up_status_err_statistics_cnt,
|
||||
up_status_ctrl_state,
|
||||
up_status_lane_cgs_state,
|
||||
up_status_lane_emb_state,
|
||||
up_status_lane_frame_align_err_cnt
|
||||
})
|
||||
);
|
||||
|
||||
sync_data #(
|
||||
.NUM_OF_BITS(8)
|
||||
) i_cdc_cfg (
|
||||
.in_clk(up_clk),
|
||||
.in_data({
|
||||
up_ctrl_err_statistics_mask,
|
||||
up_ctrl_err_statistics_reset
|
||||
}),
|
||||
.out_clk(core_clk),
|
||||
.out_data({
|
||||
core_ctrl_err_statistics_mask,
|
||||
core_ctrl_err_statistics_reset
|
||||
})
|
||||
);
|
||||
|
||||
localparam LANE_BASE_ADDR = 'h300 / 32;
|
||||
|
||||
always @(*) begin
|
||||
case (up_raddr)
|
||||
/* Core configuration */
|
||||
12'h010: up_rdata = ELASTIC_BUFFER_SIZE; /* Elastic buffer size in octets */
|
||||
|
||||
/* JESD RX configuraton */
|
||||
12'h090: up_rdata = {
|
||||
/* 17-31 */ 15'h00, /* Reserved for future additions */
|
||||
/* 16 */ up_cfg_buffer_early_release, /* Release buffer as soon as all lanes are ready. */
|
||||
/* 10-15 */ 6'b0000, /* Reserved for future extensions of buffer_delay */
|
||||
/* 02-09 */ up_cfg_buffer_delay, /* Buffer release delay */
|
||||
/* 00-01 */ 2'b00 /* Data path width alignment */
|
||||
};
|
||||
12'h91: up_rdata = {
|
||||
/* 15-31 */ 17'h00, /* Reserved for future additions */
|
||||
/* 08-14 */ up_ctrl_err_statistics_mask,
|
||||
/* 01-07 */ 7'h0,
|
||||
/* 00 */ up_ctrl_err_statistics_reset
|
||||
};
|
||||
12'h92: up_rdata = {
|
||||
/* 08-31 */ 24'h0,
|
||||
/* 00-07 */ up_cfg_frame_align_err_threshold
|
||||
};
|
||||
|
||||
/* 0x93-0x9f reserved for future use */
|
||||
|
||||
/* JESD RX status */
|
||||
12'ha0: up_rdata = {
|
||||
/* 04-31 */ 28'h00, /* Reserved for future additions */
|
||||
/* 02-03 */ 2'b00, /* Reserved for future extensions of ctrl_state */
|
||||
/* 00-01 */ up_status_ctrl_state /* State of the internal state machine */
|
||||
};
|
||||
default: begin
|
||||
if (up_raddr[11:3] >= LANE_BASE_ADDR &&
|
||||
up_raddr[11:3] < LANE_BASE_ADDR + NUM_LANES) begin
|
||||
up_rdata = up_lane_rdata[up_raddr[11:3] - LANE_BASE_ADDR];
|
||||
end else begin
|
||||
up_rdata = 'h00;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_reset == 1'b1) begin
|
||||
up_cfg_buffer_early_release <= 1'b0;
|
||||
up_cfg_buffer_delay <= 'h00;
|
||||
up_ctrl_err_statistics_mask <= 7'h0;
|
||||
up_ctrl_err_statistics_reset <= 1'b0;
|
||||
up_cfg_frame_align_err_threshold <= 8'd4;
|
||||
end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
|
||||
case (up_waddr)
|
||||
/* JESD RX configuraton */
|
||||
12'h090: begin
|
||||
up_cfg_buffer_early_release <= up_wdata[16];
|
||||
up_cfg_buffer_delay <= up_wdata[9:DATA_PATH_WIDTH];
|
||||
end
|
||||
endcase
|
||||
end else if (up_wreq == 1'b1) begin
|
||||
case (up_waddr)
|
||||
12'h91: begin
|
||||
up_ctrl_err_statistics_mask <= up_wdata[14:8];
|
||||
up_ctrl_err_statistics_reset <= up_wdata[0];
|
||||
end
|
||||
12'h92: begin
|
||||
up_cfg_frame_align_err_threshold <= up_wdata[7:0];
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
genvar i;
|
||||
generate for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
|
||||
jesd204_up_rx_lane i_up_rx_lane (
|
||||
.up_clk(up_clk),
|
||||
.up_reset_synchronizer(up_reset_synchronizer),
|
||||
|
||||
.up_rreq(up_rreq),
|
||||
.up_raddr(up_raddr[2:0]),
|
||||
.up_rdata(up_lane_rdata[i]),
|
||||
|
||||
.up_status_cgs_state(up_status_lane_cgs_state[2*i+1:2*i]),
|
||||
.up_status_err_statistics_cnt(up_status_err_statistics_cnt[32*i+31:32*i]),
|
||||
.up_status_emb_state(up_status_lane_emb_state[3*i+2:3*i]),
|
||||
.up_status_lane_frame_align_err_cnt(up_status_lane_frame_align_err_cnt[8*i+7:8*i]),
|
||||
|
||||
.core_clk(core_clk),
|
||||
.core_reset(core_reset),
|
||||
|
||||
.core_ilas_config_valid(core_ilas_config_valid[i]),
|
||||
.core_ilas_config_addr(core_ilas_config_addr[2*i+1:2*i]),
|
||||
.core_ilas_config_data(core_ilas_config_data[32*i+31:32*i]),
|
||||
|
||||
.core_status_ifs_ready(core_status_lane_ifs_ready[i]),
|
||||
.core_status_latency(core_status_lane_latency[14*i+13:14*i])
|
||||
);
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,152 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_up_rx_lane (
|
||||
input up_clk,
|
||||
input up_reset_synchronizer,
|
||||
|
||||
input up_rreq,
|
||||
input [2:0] up_raddr,
|
||||
output reg [31:0] up_rdata,
|
||||
|
||||
input [1:0] up_status_cgs_state,
|
||||
input [31:0] up_status_err_statistics_cnt,
|
||||
input [2:0] up_status_emb_state,
|
||||
input [7:0] up_status_lane_frame_align_err_cnt,
|
||||
|
||||
input core_clk,
|
||||
input core_reset,
|
||||
|
||||
input core_ilas_config_valid,
|
||||
input [1:0] core_ilas_config_addr,
|
||||
input [31:0] core_ilas_config_data,
|
||||
|
||||
input core_status_ifs_ready,
|
||||
input [13:0] core_status_latency
|
||||
);
|
||||
|
||||
wire [1:0] up_status_ctrl_state;
|
||||
|
||||
wire up_status_ifs_ready;
|
||||
reg [13:0] up_status_latency = 'h00;
|
||||
|
||||
wire [31:0] up_ilas_rdata;
|
||||
wire up_ilas_ready;
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1)
|
||||
) i_cdc_status_ready (
|
||||
.in_bits({
|
||||
core_status_ifs_ready
|
||||
}),
|
||||
.out_clk(up_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits({
|
||||
up_status_ifs_ready
|
||||
})
|
||||
);
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_reset_synchronizer == 1'b1) begin
|
||||
up_status_latency <= 'h00;
|
||||
end else begin
|
||||
if (up_status_ifs_ready == 1'b1) begin
|
||||
up_status_latency <= core_status_latency;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
if (up_raddr[2] == 1'b1) begin
|
||||
if (up_ilas_ready == 1'b1) begin
|
||||
up_rdata = up_ilas_rdata;
|
||||
end else begin
|
||||
up_rdata = 'h00;
|
||||
end
|
||||
end else begin
|
||||
case (up_raddr[1:0])
|
||||
2'b00: up_rdata = {
|
||||
/* 11-31 */ 21'h0, /* Reserved for future use */
|
||||
/* 08-10 */ up_status_emb_state,
|
||||
/* 06-07 */ 2'h00,
|
||||
/* 05 */ up_ilas_ready,
|
||||
/* 04 */ up_status_ifs_ready,
|
||||
/* 02-03 */ 2'b00, /* Reserved for future extensions of cgs_state */
|
||||
/* 00-01 */ up_status_cgs_state
|
||||
};
|
||||
2'b01: up_rdata = {
|
||||
/* 14-31 */ 18'h00, /* Reserved for future use */
|
||||
/* 00-13 */ up_status_latency
|
||||
};
|
||||
2'b10: up_rdata = {
|
||||
/* 00-31 */ up_status_err_statistics_cnt
|
||||
};
|
||||
2'b11: up_rdata = {
|
||||
/* 08-31 */ 24'h0, /* Reserved for future use */
|
||||
/* 00-07 */ up_status_lane_frame_align_err_cnt
|
||||
};
|
||||
default: up_rdata = 'h00;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
jesd204_up_ilas_mem i_ilas_mem (
|
||||
.up_clk(up_clk),
|
||||
|
||||
.up_rreq(up_rreq),
|
||||
.up_raddr(up_raddr[1:0]),
|
||||
.up_rdata(up_ilas_rdata),
|
||||
.up_ilas_ready(up_ilas_ready),
|
||||
|
||||
.core_clk(core_clk),
|
||||
.core_reset(core_reset),
|
||||
|
||||
.core_ilas_config_valid(core_ilas_config_valid),
|
||||
.core_ilas_config_addr(core_ilas_config_addr),
|
||||
.core_ilas_config_data(core_ilas_config_data)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Wed Dec 8 20:24:45 2021
|
||||
# Process ID: 145873
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx
|
||||
# Command line: vivado -mode batch -source axi_jesd204_rx_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source axi_jesd204_rx_ip.tcl
|
||||
@@ -0,0 +1,845 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Wed Dec 8 20:24:45 2021
|
||||
# Process ID: 145873
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx
|
||||
# Command line: vivado -mode batch -source axi_jesd204_rx_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source axi_jesd204_rx_ip.tcl
|
||||
# source ../../scripts/adi_env.tcl
|
||||
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
|
||||
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
|
||||
## if [info exists ::env(ADI_HDL_DIR)] {
|
||||
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
|
||||
## }
|
||||
## if [info exists ::env(ADI_GHDL_DIR)] {
|
||||
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
|
||||
## }
|
||||
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
|
||||
### variable auto_set_param_list
|
||||
### variable auto_set_param_list_overwritable
|
||||
### variable fpga_series_list
|
||||
### variable fpga_family_list
|
||||
### variable speed_grade_list
|
||||
### variable dev_package_list
|
||||
### variable xcvr_type_list
|
||||
### variable fpga_voltage_list
|
||||
### set auto_set_param_list { \
|
||||
### DEV_PACKAGE \
|
||||
### SPEED_GRADE \
|
||||
### FPGA_FAMILY \
|
||||
### FPGA_TECHNOLOGY }
|
||||
### set auto_set_param_list_overwritable { \
|
||||
### FPGA_VOLTAGE \
|
||||
### XCVR_TYPE }
|
||||
### set fpga_technology_list { \
|
||||
### { Unknown 0 } \
|
||||
### { 7series 1 } \
|
||||
### { ultrascale 2 } \
|
||||
### { ultrascale+ 3 }}
|
||||
### set fpga_family_list { \
|
||||
### { Unknown 0 } \
|
||||
### { artix 1 } \
|
||||
### { kintex 2 } \
|
||||
### { virtex 3 } \
|
||||
### { zynq 4 }}
|
||||
### set speed_grade_list { \
|
||||
### { Unknown 0 } \
|
||||
### { -1 10 } \
|
||||
### { -1L 11 } \
|
||||
### { -1H 12 } \
|
||||
### { -1HV 13 } \
|
||||
### { -1LV 14 } \
|
||||
### { -2 20 } \
|
||||
### { -2L 21 } \
|
||||
### { -2LV 22 } \
|
||||
### { -3 30 }}
|
||||
### set dev_package_list { \
|
||||
### { Unknown 0 } \
|
||||
### { rf 1 } \
|
||||
### { fl 2 } \
|
||||
### { ff 3 } \
|
||||
### { fb 4 } \
|
||||
### { hc 5 } \
|
||||
### { fh 6 } \
|
||||
### { cs 7 } \
|
||||
### { cp 8 } \
|
||||
### { ft 9 } \
|
||||
### { fg 10 } \
|
||||
### { sb 11 } \
|
||||
### { rb 12 } \
|
||||
### { rs 13 } \
|
||||
### { cl 14 } \
|
||||
### { sf 15 } \
|
||||
### { ba 16 } \
|
||||
### { fa 17 } \
|
||||
### { fs 18 } \
|
||||
### { fi 19 }}
|
||||
### set xcvr_type_list { \
|
||||
### { Unknown 0 } \
|
||||
### { GTPE2_NOT_SUPPORTED 1 } \
|
||||
### { GTXE2 2 } \
|
||||
### { GTHE2_NOT_SUPPORTED 3 } \
|
||||
### { GTZE2_NOT_SUPPORTED 4 } \
|
||||
### { GTHE3 5 } \
|
||||
### { GTYE3_NOT_SUPPORTED 6 } \
|
||||
### { GTRE4_NOT_SUPPORTED 7 } \
|
||||
### { GTHE4 8 } \
|
||||
### { GTYE4 9 } \
|
||||
### { GTME4_NOT_SUPPORTED 10}}
|
||||
### set fpga_voltage_list {0 5000} ;
|
||||
### proc adi_device_spec {cellpath param} {
|
||||
###
|
||||
### set list_pointer [string tolower $param]
|
||||
### set list_pointer [append list_pointer "_list"]
|
||||
###
|
||||
### upvar 1 $list_pointer $list_pointer
|
||||
###
|
||||
### set ip [get_bd_cells $cellpath]
|
||||
### set part [get_property PART [current_project]]
|
||||
###
|
||||
### switch -regexp -- $param {
|
||||
### FPGA_TECHNOLOGY {
|
||||
### switch -regexp -- $part {
|
||||
### ^xc7 {set series_name 7series}
|
||||
### ^xczu {set series_name ultrascale+}
|
||||
### ^xc.u.p {set series_name ultrascale+}
|
||||
### ^xc.u {set series_name ultrascale }
|
||||
### default {
|
||||
### puts "Undefined fpga technology for \"$part\"!"
|
||||
### exit -1
|
||||
### }
|
||||
### }
|
||||
### return "$series_name"
|
||||
### }
|
||||
### FPGA_FAMILY {
|
||||
### set fpga_family [get_property FAMILY $part]
|
||||
### foreach i $fpga_family_list {
|
||||
### regexp ^[lindex $i 0] $fpga_family matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### SPEED_GRADE {
|
||||
### set speed_grade [get_property SPEED $part]
|
||||
### return "$speed_grade"
|
||||
### }
|
||||
### DEV_PACKAGE {
|
||||
### set dev_package [get_property PACKAGE $part]
|
||||
### foreach i $dev_package_list {
|
||||
### regexp ^[lindex $i 0] $dev_package matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### XCVR_TYPE {
|
||||
### set matched ""
|
||||
### set dev_transcivers "none"
|
||||
### foreach x [list_property $part] {
|
||||
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
|
||||
### }
|
||||
### foreach i $xcvr_type_list {
|
||||
### regexp ^[lindex $i 0] $dev_transcivers matched
|
||||
### }
|
||||
### if { $matched eq "" } {
|
||||
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### FPGA_VOLTAGE {
|
||||
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
|
||||
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
|
||||
###
|
||||
### return "$fpga_voltage"
|
||||
### }
|
||||
### default {
|
||||
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
|
||||
### }
|
||||
### }
|
||||
### }
|
||||
## if {![info exists REQUIRED_VIVADO_VERSION]} {
|
||||
## set REQUIRED_VIVADO_VERSION "2019.1"
|
||||
## }
|
||||
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
|
||||
## set IGNORE_VERSION_CHECK 1
|
||||
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
|
||||
## set IGNORE_VERSION_CHECK 0
|
||||
## }
|
||||
## proc adi_ip_ttcl {ip_name ip_constr_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
|
||||
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_sim_ttcl {ip_name ip_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
|
||||
## set f [ipx::add_file $ip_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_bd {ip_name ip_bd_files} {
|
||||
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
|
||||
## if {$proj_filegroup == {}} {
|
||||
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
|
||||
## }
|
||||
##
|
||||
## foreach file $ip_bd_files {
|
||||
## set f [ipx::add_file $file $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type tclSource \
|
||||
## ] $f
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_infer_streaming_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_ip_infer_mm_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
|
||||
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency $port
|
||||
## if {$driver_value != {}} {
|
||||
## set_property DRIVER_VALUE $driver_value $port
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_set_bus_dependency {bus prefix dependency} {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
|
||||
## adi_set_ports_dependency $prefix $dependency 0
|
||||
## }
|
||||
## proc adi_add_port_map {bus phys logic} {
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## }
|
||||
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## adi_add_port_map $bus {*}$port_map
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
|
||||
## for {set i 0} {$i < $num} {incr i} {
|
||||
## set bus_name [format "%s%d" $bus_name_prefix $i]
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## if {$dependency ne ""} {
|
||||
## set bus_dependency [string map [list "{i}" $i] $dependency]
|
||||
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
|
||||
## }
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## lassign $port_map phys logic width width_dep
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
|
||||
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
|
||||
## if {$width_dep ne ""} {
|
||||
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
|
||||
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
|
||||
## set width_dep_r "(($width_dep) * $i)"
|
||||
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
|
||||
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
|
||||
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
|
||||
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
|
||||
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
|
||||
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
|
||||
## set_property display_name $clock_inf_name $clock_inf
|
||||
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
|
||||
## set_property physical_name $clock_signal_name $clock_map
|
||||
##
|
||||
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
|
||||
## set_property value $bus_inf_name $assoc_busif
|
||||
##
|
||||
## if { $reset_signal_name != "" } {
|
||||
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
|
||||
## set_property value $reset_signal_name $assoc_reset
|
||||
##
|
||||
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
|
||||
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
|
||||
## set_property display_name $reset_inf_name $reset_inf
|
||||
## set_property interface_mode $reset_signal_mode $reset_inf
|
||||
## set reset_map [ipx::add_port_map "RST" $reset_inf]
|
||||
## set_property physical_name $reset_signal_name $reset_map
|
||||
##
|
||||
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
|
||||
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
|
||||
## set_property value "ACTIVE_LOW" $reset_polarity
|
||||
## } else {
|
||||
## set_property value "ACTIVE_HIGH" $reset_polarity
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_add_core_dependencies {vlnvs} {
|
||||
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
|
||||
## foreach vlnv $vlnvs {
|
||||
## ipx::add_subcore $vlnv $file_group
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_create {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
## global ad_ghdl_dir
|
||||
## global REQUIRED_VIVADO_VERSION
|
||||
## global IGNORE_VERSION_CHECK
|
||||
##
|
||||
## set VIVADO_VERSION [version -short]
|
||||
## if {$IGNORE_VERSION_CHECK} {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## }
|
||||
## } else {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "ERROR: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
|
||||
## exit 2
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## create_project $ip_name . -force
|
||||
##
|
||||
## ## Load custom message severity definitions
|
||||
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
|
||||
##
|
||||
## set lib_dirs $ad_hdl_dir/library
|
||||
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
|
||||
## lappend lib_dirs $ad_ghdl_dir/library
|
||||
## }
|
||||
##
|
||||
## set_property ip_repo_paths $lib_dirs [current_fileset]
|
||||
## update_ip_catalog
|
||||
## }
|
||||
## proc adi_ip_files {ip_name ip_files} {
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## foreach m_file $ip_files {
|
||||
## if {[file extension $m_file] eq ".xdc"} {
|
||||
## add_files -norecurse -fileset constrs_1 $m_file
|
||||
## } else {
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
|
||||
## }
|
||||
## }
|
||||
## set_property "top" "$ip_name" $proj_fileset
|
||||
## }
|
||||
## proc adi_ip_properties_lite {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
##
|
||||
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
|
||||
##
|
||||
## set_property name $ip_name [ipx::current_core]
|
||||
##
|
||||
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
|
||||
## set_property company_url {http://www.analog.com} [ipx::current_core]
|
||||
##
|
||||
## set i_families ""
|
||||
## foreach i_part [get_parts] {
|
||||
## lappend i_families [get_property FAMILY $i_part]
|
||||
## }
|
||||
## set i_families [lsort -unique $i_families]
|
||||
## set s_families [get_property supported_families [ipx::current_core]]
|
||||
## foreach i_family $i_families {
|
||||
## set s_families "$s_families $i_family Production"
|
||||
## set s_families "$s_families $i_family Beta"
|
||||
## }
|
||||
## set_property supported_families $s_families [ipx::current_core]
|
||||
##
|
||||
## ipx::save_core [ipx::current_core]
|
||||
##
|
||||
## ipx::remove_all_bus_interface [ipx::current_core]
|
||||
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
|
||||
## foreach map $memory_maps {
|
||||
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
|
||||
## }
|
||||
##
|
||||
## ipx::update_checksums [ipx::current_core]
|
||||
## ipx::save_core [ipx::current_core]
|
||||
## }
|
||||
## proc adi_ip_properties {ip_name} {
|
||||
##
|
||||
## adi_ip_properties_lite $ip_name
|
||||
##
|
||||
## ipx::infer_bus_interface {\
|
||||
## s_axi_awvalid \
|
||||
## s_axi_awaddr \
|
||||
## s_axi_awprot \
|
||||
## s_axi_awready \
|
||||
## s_axi_wvalid \
|
||||
## s_axi_wdata \
|
||||
## s_axi_wstrb \
|
||||
## s_axi_wready \
|
||||
## s_axi_bvalid \
|
||||
## s_axi_bresp \
|
||||
##
|
||||
## s_axi_bready \
|
||||
## s_axi_arvalid \
|
||||
## s_axi_araddr \
|
||||
## s_axi_arprot \
|
||||
## s_axi_arready \
|
||||
## s_axi_rvalid \
|
||||
## s_axi_rdata \
|
||||
## s_axi_rresp \
|
||||
## s_axi_rready} \
|
||||
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
|
||||
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
|
||||
##
|
||||
## if {$raddr_width != $waddr_width} {
|
||||
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
|
||||
## set range 65536
|
||||
## } else {
|
||||
## if {$raddr_width >= 16} {
|
||||
## set range 65536
|
||||
## } else {
|
||||
## set range [expr 1 << $raddr_width]
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
## set_property range $range [ipx::get_address_blocks axi_lite \
|
||||
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
|
||||
## ipx::save_core
|
||||
## }
|
||||
## proc adi_init_bd_tcl {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## if { [file exists bd] } {
|
||||
## file delete -force bd
|
||||
## }
|
||||
## file mkdir bd
|
||||
##
|
||||
## set bd_tcl [open "bd/bd.tcl" w]
|
||||
##
|
||||
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
|
||||
## puts $bd_tcl "proc init {cellpath otherInfo} {"
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl ""
|
||||
## set auto_set_param ""
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
|
||||
## puts $bd_tcl $auto_set_param
|
||||
## }
|
||||
##
|
||||
## set auto_set_overwritable_param ""
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_overwritable_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_overwritable_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
|
||||
## puts $bd_tcl $auto_set_overwritable_param
|
||||
## }
|
||||
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
|
||||
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
|
||||
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set parent_dir \"../\""
|
||||
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
|
||||
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
|
||||
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " break"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " append parent_dir \"../\""
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## close $bd_tcl
|
||||
##
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
|
||||
##
|
||||
## set local_mk [open "temporary_case_dependencies.mk" w]
|
||||
## seek $local_mk 0 start
|
||||
## puts $local_mk "CLEAN_TARGET += bd"
|
||||
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
|
||||
## close $local_mk
|
||||
## }
|
||||
## proc adi_add_auto_fpga_spec_params {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_device_spec_param {ip_param} {
|
||||
##
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## set list_pointer [string tolower $ip_param]
|
||||
## set list_pointer [append list_pointer "_list"]
|
||||
##
|
||||
## global $list_pointer
|
||||
##
|
||||
## # set j 1D list from the original list
|
||||
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
|
||||
##
|
||||
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
|
||||
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "range_long" \
|
||||
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
|
||||
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## } else {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "pairs" \
|
||||
## "value_validation_pairs" $j ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## }
|
||||
##
|
||||
## # FPGA info grup
|
||||
## set info_group_name "FPGA info"
|
||||
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
|
||||
## if { [string trim $info_group] eq "" } {
|
||||
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
|
||||
## -parent $page0 -display_name $info_group_name]
|
||||
## }
|
||||
##
|
||||
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
|
||||
## set_property -dict [list "widget" "comboBox" ] $p
|
||||
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
|
||||
## }
|
||||
## proc adi_if_define {name} {
|
||||
##
|
||||
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
|
||||
## ipx::create_bus_definition analog.com interface $name 1.0
|
||||
##
|
||||
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
|
||||
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
|
||||
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
|
||||
##
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## }
|
||||
## proc adi_if_ports {dir width name {type none}} {
|
||||
##
|
||||
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
|
||||
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
|
||||
## set_property master_presence required $m_intf
|
||||
## set_property slave_presence required $m_intf
|
||||
## set_property master_width $width $m_intf
|
||||
## set_property slave_width $width $m_intf
|
||||
##
|
||||
## set m_dir "in"
|
||||
## set s_dir "out"
|
||||
## if {$dir eq "output"} {
|
||||
## set m_dir "out"
|
||||
## set s_dir "in"
|
||||
## }
|
||||
##
|
||||
## set_property master_direction $m_dir $m_intf
|
||||
## set_property slave_direction $s_dir $m_intf
|
||||
##
|
||||
## if {$type ne "none"} {
|
||||
## set_property is_${type} true $m_intf
|
||||
## }
|
||||
##
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## }
|
||||
## proc adi_if_infer_bus {if_name mode name maps} {
|
||||
##
|
||||
## ipx::add_bus_interface $name [ipx::current_core]
|
||||
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
|
||||
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
|
||||
## set_property interface_mode $mode $m_bus_if
|
||||
##
|
||||
## foreach map $maps {
|
||||
## set m_maps [regexp -all -inline {\S+} $map]
|
||||
## lassign $m_maps p_name p_map
|
||||
## ipx::add_port_map $p_name $m_bus_if
|
||||
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
|
||||
## }
|
||||
## }
|
||||
# adi_ip_create axi_jesd204_rx
|
||||
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
|
||||
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1343} -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1306} -new_severity WARNING
|
||||
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
|
||||
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
|
||||
## set_msg_config -id {Synth 8-3331} -new_severity INFO
|
||||
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
|
||||
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
|
||||
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
|
||||
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx'.)
|
||||
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
|
||||
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
|
||||
# adi_ip_files axi_jesd204_rx [list \
|
||||
# "../../common/up_axi.v" \
|
||||
# "jesd204_up_rx.v" \
|
||||
# "jesd204_up_rx_lane.v" \
|
||||
# "jesd204_up_ilas_mem.v" \
|
||||
# "axi_jesd204_rx_constr.xdc" \
|
||||
# "axi_jesd204_rx_ooc.ttcl" \
|
||||
# "axi_jesd204_rx.v" \
|
||||
# ]
|
||||
# adi_ip_properties axi_jesd204_rx
|
||||
WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl' ignored by IP packager.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
WARNING: [IP_Flow 19-5150] The Range '((32 * NUM_LANES) - 1):0' is present in all ports of the interface 'core_ilas_config'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_ilas_config' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_reset on bus interface abstraction jesd204_rx_cfg_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_mask on bus interface abstraction jesd204_rx_cfg_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_cfg' of definition 'analog.com:interface:jesd204_rx_cfg:1.0' (from User Repositories).
|
||||
INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 'core_status_ctrl'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
||||
WARNING: [IP_Flow 19-5150] The Range '((2 * NUM_LANES) - 1):0' is present in all ports of the interface 'core_status_lane_cgs'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5150] The Range '((3 * NUM_LANES) - 1):0' is present in all ports of the interface 'core_status_lane_emb'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port sync on bus interface abstraction jesd204_tx_status_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_event_unexpected_lane_error' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port sync on bus interface abstraction jesd204_tx_status_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status_ctrl_0' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port sync on bus interface abstraction jesd204_tx_status_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status_ctrl_1' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port sync on bus interface abstraction jesd204_tx_status_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status_lane_cgs' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port sync on bus interface abstraction jesd204_tx_status_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status_lane_emb' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5150] The Range '((8 * NUM_LANES) - 1):0' is present in all ports of the interface 'core_status_err_cnt'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port lane_frame_align on bus interface abstraction jesd204_rx_status_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port lane_latency_ready on bus interface abstraction jesd204_rx_status_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_status' of definition 'analog.com:interface:jesd204_rx_status:1.0' (from User Repositories).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_event' of definition 'analog.com:interface:jesd204_tx_event:1.0' (from User Repositories).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_ctrl_err_statistics_reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'core_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'core_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'core_ctrl_err_statistics_reset'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'core_ilas_config': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_lanes_disable' and definition port 'lanes_disable'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_links_disable' and definition port 'links_disable'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_beats_per_multiframe' and definition port 'beats_per_multiframe'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_octets_per_frame' and definition port 'octets_per_frame'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_lmfc_offset' and definition port 'lmfc_offset'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_buffer_early_release' and definition port 'buffer_early_release'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_buffer_delay' and definition port 'buffer_delay'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_disable_char_replacement' and definition port 'disable_char_replacement'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_disable_scrambler' and definition port 'disable_scrambler'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'core_cfg_frame_align_err_threshold' and definition port 'frame_align_err_threshold'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'core_cfg': A port map to the required logical port "err_statistics_reset" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'core_cfg': A port map to the required logical port "err_statistics_mask" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'core_event_unexpected_lane_error': A port map to the required logical port "sync" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'core_status_ctrl_0': A port map to the required logical port "sync" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'core_status_ctrl_1': A port map to the required logical port "sync" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'core_status_lane_cgs': A port map to the required logical port "sync" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'core_status_lane_emb': A port map to the required logical port "sync" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'core_status': A port map to the required logical port "lane_frame_align" of the bus abstraction "analog.com:interface:jesd204_rx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'core_status': A port map to the required logical port "lane_latency_ready" of the bus abstraction "analog.com:interface:jesd204_rx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'core_clk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
||||
# adi_ip_ttcl axi_jesd204_rx "axi_jesd204_rx_ooc.ttcl"
|
||||
# set_property PROCESSING_ORDER LATE [ipx::get_files axi_jesd204_rx_constr.xdc \
|
||||
# -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \
|
||||
# -filter {NAME =~ *synthesis*}]]
|
||||
# adi_ip_add_core_dependencies { \
|
||||
# analog.com:user:axi_jesd204_common:1.0 \
|
||||
# }
|
||||
# set_property display_name "ADI JESD204C Receive AXI Interface" [ipx::current_core]
|
||||
# set_property description "ADI JESD204C Receive AXI Interface" [ipx::current_core]
|
||||
# adi_add_bus "rx_cfg" "master" \
|
||||
# "analog.com:interface:jesd204_rx_cfg_rtl:1.0" \
|
||||
# "analog.com:interface:jesd204_rx_cfg:1.0" \
|
||||
# { \
|
||||
# { "core_cfg_lanes_disable" "lanes_disable" } \
|
||||
# { "core_cfg_links_disable" "links_disable" } \
|
||||
# { "core_cfg_beats_per_multiframe" "beats_per_multiframe" } \
|
||||
# { "core_cfg_octets_per_frame" "octets_per_frame" } \
|
||||
# { "core_cfg_lmfc_offset" "lmfc_offset" } \
|
||||
# { "core_cfg_sysref_oneshot" "sysref_oneshot" } \
|
||||
# { "core_cfg_sysref_disable" "sysref_disable" } \
|
||||
# { "core_ctrl_err_statistics_reset" "err_statistics_reset" } \
|
||||
# { "core_ctrl_err_statistics_mask" "err_statistics_mask" } \
|
||||
# { "core_cfg_buffer_early_release" "buffer_early_release" } \
|
||||
# { "core_cfg_buffer_delay" "buffer_delay" } \
|
||||
# { "core_cfg_disable_char_replacement" "disable_char_replacement" } \
|
||||
# { "core_cfg_disable_scrambler" "disable_scrambler" } \
|
||||
# { "core_cfg_frame_align_err_threshold" "frame_align_err_threshold" } \
|
||||
# }
|
||||
# adi_add_bus "rx_ilas_config" "slave" \
|
||||
# "analog.com:interface:jesd204_rx_ilas_config_rtl:1.0" \
|
||||
# "analog.com:interface:jesd204_rx_ilas_config:1.0" \
|
||||
# { \
|
||||
# { "core_ilas_config_valid" "valid" } \
|
||||
# { "core_ilas_config_addr" "addr" } \
|
||||
# { "core_ilas_config_data" "data" } \
|
||||
# }
|
||||
# adi_add_bus "rx_event" "slave" \
|
||||
# "analog.com:interface:jesd204_rx_event_rtl:1.0" \
|
||||
# "analog.com:interface:jesd204_rx_event:1.0" \
|
||||
# { \
|
||||
# { "core_event_sysref_alignment_error" "sysref_alignment_error" } \
|
||||
# { "core_event_sysref_edge" "sysref_edge" } \
|
||||
# { "core_event_frame_alignment_error" "frame_alignment_error" } \
|
||||
# { "core_event_unexpected_lane_state_error" "unexpected_lane_state_error" } \
|
||||
# }
|
||||
# adi_add_bus "rx_status" "slave" \
|
||||
# "analog.com:interface:jesd204_rx_status_rtl:1.0" \
|
||||
# "analog.com:interface:jesd204_rx_status:1.0" \
|
||||
# { \
|
||||
# { "core_status_ctrl_state" "ctrl_state" } \
|
||||
# { "core_status_lane_cgs_state" "lane_cgs_state" } \
|
||||
# { "core_status_lane_emb_state" "lane_emb_state" } \
|
||||
# { "core_status_lane_ifs_ready" "lane_ifs_ready" } \
|
||||
# { "core_status_lane_latency" "lane_latency" } \
|
||||
# { "core_status_lane_frame_align_err_cnt" "lane_frame_align_err_cnt" } \
|
||||
# { "core_status_err_statistics_cnt" "err_statistics_cnt" } \
|
||||
# }
|
||||
# ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
|
||||
# adi_add_bus_clock "core_clk" "rx_status:rx_event:rx_ilas_config:rx_cfg" \
|
||||
# "core_reset" "master"
|
||||
# set_property DRIVER_VALUE "0" [ipx::get_ports "core_reset_ext"]
|
||||
# adi_set_bus_dependency "rx_ilas_config" "rx_ilas_config" \
|
||||
# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
|
||||
# set cc [ipx::current_core]
|
||||
# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
# set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
|
||||
# ipgui::move_param -component $cc -order 0 $p -parent $page0
|
||||
# set_property -dict [list \
|
||||
# "display_name" "Link Layer mode" \
|
||||
# "tooltip" "Link Layer mode" \
|
||||
# "widget" "comboBox" \
|
||||
# ] $p
|
||||
# set_property -dict [list \
|
||||
# value_validation_type pairs \
|
||||
# value_validation_pairs {64B66B 2 8B10B 1} \
|
||||
# ] [ipx::get_user_parameters $p -of_objects $cc]
|
||||
# ipx::create_xgui_files [ipx::current_core]
|
||||
# ipx::save_core [ipx::current_core]
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:24:55 2021...
|
||||
@@ -0,0 +1,85 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "LINK_MODE" -parent ${Page_0} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "ENABLE_LINK_STATS" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "NUM_LANES" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "NUM_LINKS" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ENABLE_LINK_STATS { PARAM_VALUE.ENABLE_LINK_STATS } {
|
||||
# Procedure called to update ENABLE_LINK_STATS when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ENABLE_LINK_STATS { PARAM_VALUE.ENABLE_LINK_STATS } {
|
||||
# Procedure called to validate ENABLE_LINK_STATS
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } {
|
||||
# Procedure called to update LINK_MODE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } {
|
||||
# Procedure called to validate LINK_MODE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
|
||||
# Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
|
||||
# Procedure called to validate NUM_LANES
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } {
|
||||
# Procedure called to update NUM_LINKS when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } {
|
||||
# Procedure called to validate NUM_LINKS
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_LINKS { MODELPARAM_VALUE.NUM_LINKS PARAM_VALUE.NUM_LINKS } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_LINKS}] ${MODELPARAM_VALUE.NUM_LINKS}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.LINK_MODE { MODELPARAM_VALUE.LINK_MODE PARAM_VALUE.LINK_MODE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.LINK_MODE}] ${MODELPARAM_VALUE.LINK_MODE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ENABLE_LINK_STATS { MODELPARAM_VALUE.ENABLE_LINK_STATS PARAM_VALUE.ENABLE_LINK_STATS } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ENABLE_LINK_STATS}] ${MODELPARAM_VALUE.ENABLE_LINK_STATS}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user