initial commit

adi_library/jesd204/axi_jesd204_tx/Makefile

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+####################################################################################
+## Copyright 2018(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+
+LIBRARY_NAME := axi_jesd204_tx
+
+GENERIC_DEPS += ../../common/up_axi.v
+GENERIC_DEPS += axi_jesd204_tx.v
+GENERIC_DEPS += jesd204_up_tx.v
+
+XILINX_DEPS += axi_jesd204_tx_constr.xdc
+XILINX_DEPS += axi_jesd204_tx_ip.tcl
+XILINX_DEPS += axi_jesd204_tx_ooc.ttcl
+
+XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml
+XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg_rtl.xml
+XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl.xml
+XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl_rtl.xml
+XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_event.xml
+XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_event_rtl.xml
+XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config.xml
+XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml
+XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_status.xml
+XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_status_rtl.xml
+
+XILINX_LIB_DEPS += jesd204/axi_jesd204_common
+
+XILINX_INTERFACE_DEPS += jesd204/interfaces
+
+INTEL_DEPS += ../../common/up_clock_mon.v
+INTEL_DEPS += ../../intel/common/up_clock_mon_constr.sdc
+INTEL_DEPS += ../../util_cdc/sync_bits.v
+INTEL_DEPS += ../../util_cdc/sync_data.v
+INTEL_DEPS += ../../util_cdc/sync_event.v
+INTEL_DEPS += ../axi_jesd204_common/jesd204_up_common.v
+INTEL_DEPS += ../axi_jesd204_common/jesd204_up_sysref.v
+INTEL_DEPS += axi_jesd204_tx_constr.sdc
+INTEL_DEPS += axi_jesd204_tx_hw.tcl
+
+include ../../scripts/library.mk

adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx.cache/wt/project.wpc

@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c42617463684d6f6465:1
+eof:

adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx.hw/axi_jesd204_tx.lpr

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2019.1.3 (64-bit)                   -->
+<!--                                                              -->
+<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>

adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v

@@ -0,0 +1,301 @@
+//
+// The ADI JESD204 Core is released under the following license, which is
+// different than all other HDL cores in this repository.
+//
+// Please read this, and understand the freedoms and responsibilities you have
+// by using this source code/core.
+//
+// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
+//
+// This core is free software, you can use run, copy, study, change, ask
+// questions about and improve this core. Distribution of source, or resulting
+// binaries (including those inside an FPGA or ASIC) require you to release the
+// source of the entire project (excluding the system libraries provide by the
+// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
+// License version 2 as published by the Free Software Foundation.
+//
+// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License version 2
+// along with this source code, and binary.  If not, see
+// <http://www.gnu.org/licenses/>.
+//
+// Commercial licenses (with commercial support) of this JESD204 core are also
+// available under terms different than the General Public License. (e.g. they
+// do not require you to accompany any image (FPGA or ASIC) using the JESD204
+// core with any corresponding source code.) For these alternate terms you must
+// purchase a license from Analog Devices Technology Licensing Office. Users
+// interested in such a license should contact [email protected] for
+// more information. This commercial license is sub-licensable (if you purchase
+// chips from Analog Devices, incorporate them into your PCB level product, and
+// purchase a JESD204 license, end users of your product will also have a
+// license to use this core in a commercial setting without releasing their
+// source code).
+//
+// In addition, we kindly ask you to acknowledge ADI in any program, application
+// or publication in which you use this JESD204 HDL core. (You are not required
+// to do so; it is up to your common sense to decide whether you want to comply
+// with this request or not.) For general publications, we suggest referencing :
+// “The design and implementation of the JESD204 HDL Core used in this project
+// is copyright © 2016-2017, Analog Devices, Inc.”
+//
+
+`timescale 1ns/100ps
+
+module axi_jesd204_tx #(
+  parameter ID = 0,
+  parameter NUM_LANES = 1,
+  parameter NUM_LINKS = 1,
+  parameter LINK_MODE = 1,  // 2 - 64B/66B;  1 - 8B/10B
+  parameter ENABLE_LINK_STATS = 0
+) (
+  input s_axi_aclk,
+  input s_axi_aresetn,
+
+  input s_axi_awvalid,
+  input [13:0] s_axi_awaddr,
+  output s_axi_awready,
+  input [2:0] s_axi_awprot,
+  input s_axi_wvalid,
+  input [31:0] s_axi_wdata,
+  input [3:0] s_axi_wstrb,
+  output s_axi_wready,
+  output s_axi_bvalid,
+  output [1:0] s_axi_bresp,
+  input s_axi_bready,
+  input s_axi_arvalid,
+  input [13:0] s_axi_araddr,
+  output s_axi_arready,
+  input [2:0] s_axi_arprot,
+  output s_axi_rvalid,
+  input s_axi_rready,
+  output [1:0] s_axi_rresp,
+  output [31:0] s_axi_rdata,
+
+  output irq,
+
+  input core_clk,
+  input core_reset_ext,
+  output core_reset,
+
+  output [NUM_LANES-1:0] core_cfg_lanes_disable,
+  output [NUM_LINKS-1:0] core_cfg_links_disable,
+  output [7:0] core_cfg_beats_per_multiframe,
+  output [7:0] core_cfg_octets_per_frame,
+  output [7:0] core_cfg_lmfc_offset,
+  output core_cfg_sysref_oneshot,
+  output core_cfg_sysref_disable,
+  output core_cfg_continuous_cgs,
+  output core_cfg_continuous_ilas,
+  output core_cfg_skip_ilas,
+  output [7:0] core_cfg_mframes_per_ilas,
+  output core_cfg_disable_char_replacement,
+  output core_cfg_disable_scrambler,
+
+  input core_ilas_config_rd,
+  input [1:0] core_ilas_config_addr,
+  output [32*NUM_LANES-1:0] core_ilas_config_data,
+
+  input core_event_sysref_alignment_error,
+  input core_event_sysref_edge,
+
+  output core_ctrl_manual_sync_request,
+
+  input [1:0] core_status_state,
+  input [NUM_LINKS-1:0] core_status_sync
+);
+
+localparam PCORE_VERSION = 32'h00010361; // 1.03.a
+localparam PCORE_MAGIC = 32'h32303454; // 204T
+
+localparam DATA_PATH_WIDTH = LINK_MODE == 2 ? 3 : 2;
+
+wire up_reset;
+
+/* Register interface signals */
+reg [31:0] up_rdata = 'd0;
+reg up_wack = 1'b0;
+reg up_rack = 1'b0;
+wire up_wreq;
+wire up_rreq;
+wire [31:0] up_wdata;
+wire [11:0] up_waddr;
+wire [11:0] up_raddr;
+wire [31:0] up_rdata_common;
+wire [31:0] up_rdata_sysref;
+wire [31:0] up_rdata_tx;
+
+wire up_cfg_skip_ilas;
+wire up_cfg_continuous_ilas;
+wire up_cfg_continuous_cgs;
+wire [7:0] up_cfg_mframes_per_ilas;
+wire [7:0] up_cfg_lmfc_offset;
+wire up_cfg_sysref_oneshot;
+wire up_cfg_sysref_disable;
+wire up_cfg_is_writeable;
+
+wire [4:0] up_irq_trigger;
+
+assign up_irq_trigger[4:0] = 5'b00000;
+
+up_axi #(
+  .AXI_ADDRESS_WIDTH (14)
+) i_up_axi (
+  .up_rstn(~up_reset),
+  .up_clk(s_axi_aclk),
+  .up_axi_awvalid(s_axi_awvalid),
+  .up_axi_awaddr(s_axi_awaddr),
+  .up_axi_awready(s_axi_awready),
+  .up_axi_wvalid(s_axi_wvalid),
+  .up_axi_wdata(s_axi_wdata),
+  .up_axi_wstrb(s_axi_wstrb),
+  .up_axi_wready(s_axi_wready),
+  .up_axi_bvalid(s_axi_bvalid),
+  .up_axi_bresp(s_axi_bresp),
+  .up_axi_bready(s_axi_bready),
+  .up_axi_arvalid(s_axi_arvalid),
+  .up_axi_araddr(s_axi_araddr),
+  .up_axi_arready(s_axi_arready),
+  .up_axi_rvalid(s_axi_rvalid),
+  .up_axi_rresp(s_axi_rresp),
+  .up_axi_rdata(s_axi_rdata),
+  .up_axi_rready(s_axi_rready),
+  .up_wreq(up_wreq),
+  .up_waddr(up_waddr),
+  .up_wdata(up_wdata),
+  .up_wack(up_wack),
+  .up_rreq(up_rreq),
+  .up_raddr(up_raddr),
+  .up_rdata(up_rdata),
+  .up_rack(up_rack)
+);
+
+jesd204_up_common #(
+  .PCORE_VERSION(PCORE_VERSION),
+  .PCORE_MAGIC(PCORE_MAGIC),
+  .ID(ID),
+  .NUM_LANES(NUM_LANES),
+  .NUM_LINKS(NUM_LINKS),
+  .DATA_PATH_WIDTH(DATA_PATH_WIDTH),
+  .NUM_IRQS(5),
+  .EXTRA_CFG_WIDTH(21),
+  .MAX_OCTETS_PER_FRAME(8),
+  .LINK_MODE(LINK_MODE),
+  .ENABLE_LINK_STATS(ENABLE_LINK_STATS)
+) i_up_common (
+  .up_clk(s_axi_aclk),
+  .ext_resetn(s_axi_aresetn),
+
+  .up_reset(up_reset),
+
+  .up_reset_synchronizer(),
+
+  .core_clk(core_clk),
+  .core_reset_ext(core_reset_ext),
+  .core_reset(core_reset),
+
+  .up_raddr(up_raddr),
+  .up_rdata(up_rdata_common),
+
+  .up_wreq(up_wreq),
+  .up_waddr(up_waddr),
+  .up_wdata(up_wdata),
+
+  .up_cfg_is_writeable(up_cfg_is_writeable),
+
+  .up_irq_trigger(up_irq_trigger),
+  .irq(irq),
+
+  .core_cfg_beats_per_multiframe(core_cfg_beats_per_multiframe),
+  .core_cfg_octets_per_frame(core_cfg_octets_per_frame),
+  .core_cfg_lanes_disable(core_cfg_lanes_disable),
+  .core_cfg_links_disable(core_cfg_links_disable),
+  .core_cfg_disable_scrambler(core_cfg_disable_scrambler),
+  .core_cfg_disable_char_replacement(core_cfg_disable_char_replacement),
+
+  .up_extra_cfg({
+    /*    20 */ up_cfg_sysref_disable,
+    /*    19 */ up_cfg_sysref_oneshot,
+    /*    18 */ up_cfg_continuous_cgs,
+    /*    17 */ up_cfg_continuous_ilas,
+    /*    16 */ up_cfg_skip_ilas,
+    /* 08-15 */ up_cfg_lmfc_offset,
+    /* 00-07 */ up_cfg_mframes_per_ilas
+  }),
+  .core_extra_cfg({
+    /*    20 */ core_cfg_sysref_disable,
+    /*    19 */ core_cfg_sysref_oneshot,
+    /*    18 */ core_cfg_continuous_cgs,
+    /*    17 */ core_cfg_continuous_ilas,
+    /*    16 */ core_cfg_skip_ilas,
+    /* 08-15 */ core_cfg_lmfc_offset,
+    /* 00-07 */ core_cfg_mframes_per_ilas
+  })
+);
+
+jesd204_up_sysref #(
+  .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
+) i_up_sysref (
+  .up_clk(s_axi_aclk),
+  .up_reset(up_reset),
+
+  .core_clk(core_clk),
+  .core_event_sysref_alignment_error(core_event_sysref_alignment_error),
+  .core_event_sysref_edge(core_event_sysref_edge),
+
+  .up_cfg_lmfc_offset(up_cfg_lmfc_offset),
+  .up_cfg_sysref_oneshot(up_cfg_sysref_oneshot),
+  .up_cfg_sysref_disable(up_cfg_sysref_disable),
+
+  .up_raddr(up_raddr),
+  .up_rdata(up_rdata_sysref),
+
+  .up_wreq(up_wreq),
+  .up_waddr(up_waddr),
+  .up_wdata(up_wdata),
+
+  .up_cfg_is_writeable(up_cfg_is_writeable)
+);
+
+jesd204_up_tx #(
+  .NUM_LANES(NUM_LANES),
+  .NUM_LINKS(NUM_LINKS)
+) i_up_tx (
+  .up_clk(s_axi_aclk),
+  .up_reset(up_reset),
+
+  .core_clk(core_clk),
+  .core_ilas_config_rd(core_ilas_config_rd),
+  .core_ilas_config_addr(core_ilas_config_addr),
+  .core_ilas_config_data(core_ilas_config_data),
+
+  .core_ctrl_manual_sync_request(core_ctrl_manual_sync_request),
+
+  .core_status_state(core_status_state),
+  .core_status_sync(core_status_sync),
+
+  .up_raddr(up_raddr),
+  .up_rdata(up_rdata_tx),
+  .up_wreq(up_wreq),
+  .up_waddr(up_waddr),
+  .up_wdata(up_wdata),
+
+  .up_cfg_is_writeable(up_cfg_is_writeable),
+
+  .up_cfg_continuous_cgs(up_cfg_continuous_cgs),
+  .up_cfg_continuous_ilas(up_cfg_continuous_ilas),
+  .up_cfg_skip_ilas(up_cfg_skip_ilas),
+  .up_cfg_mframes_per_ilas(up_cfg_mframes_per_ilas)
+);
+
+always @(posedge s_axi_aclk) begin
+  up_wack <= up_wreq;
+  up_rack <= up_rreq;
+  if (up_rreq == 1'b1) begin
+    up_rdata <= up_rdata_common | up_rdata_sysref | up_rdata_tx;
+  end
+end
+
+endmodule

adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx.xpr

@@ -0,0 +1,397 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2019.1.3 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="74061ab0f56249a4b544a4ba2c732afa"/>
+    <Option Name="Part" Val="xc7vx485tffg1157-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
+    <Option Name="IPRepoPath" Val="$PPRDIR/../../../../ghdl/library"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSAVendor" Val="xilinx"/>
+    <Option Name="DSANumComputeUnits" Val="60"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/jesd204_up_tx.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../common/up_axi.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/axi_jesd204_tx.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/axi_jesd204_tx_ooc.ttcl"/>
+      <File Path="$PPRDIR/component.xml">
+        <FileInfo SFType="IPXACT"/>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="axi_jesd204_tx"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/axi_jesd204_tx_constr.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="IES">
+      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="10">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+  </Runs>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val="Vivado 12-1790"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="1"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+    <MsgAttr Name="StringsToMatch" Val="Evaluation"/>
+    <MsgAttr Name="StringsToMatch" Val="features"/>
+    <MsgAttr Name="StringsToMatch" Val="should"/>
+    <MsgAttr Name="StringsToMatch" Val="NOT"/>
+    <MsgAttr Name="StringsToMatch" Val="be"/>
+    <MsgAttr Name="StringsToMatch" Val="used"/>
+    <MsgAttr Name="StringsToMatch" Val="in"/>
+    <MsgAttr Name="StringsToMatch" Val="production"/>
+    <MsgAttr Name="StringsToMatch" Val="systems."/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val="Place 30-73"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="10"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+    <MsgAttr Name="StringsToMatch" Val="axi_spi"/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val=""/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="11"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+    <MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val="BD 41-1343"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="2"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val="BD 41-1306"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="3"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="ERROR"/>
+    <MsgAttr Name="Id" Val="BD 41-1276"/>
+    <MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="4"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="INFO"/>
+    <MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="5"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="INFO"/>
+    <MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="6"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="INFO"/>
+    <MsgAttr Name="Id" Val="IP_Flow 19-459"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="7"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="INFO"/>
+    <MsgAttr Name="Id" Val="Synth 8-3331"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="8"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="INFO"/>
+    <MsgAttr Name="Id" Val="Designutils 20-3303"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="9"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+    <MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
+  </MsgRule>
+  <Board/>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+  <BootPmcSettings Version="1" Minor="0">
+    <Parameters>
+      <Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
+      <Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
+      <Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
+      <Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
+      <Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
+      <Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
+      <Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
+      <Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
+      <Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
+      <Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
+      <Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
+      <Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
+      <Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
+      <Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
+      <Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
+      <Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
+      <Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
+      <Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
+      <Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
+      <Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
+      <Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
+    </Parameters>
+  </BootPmcSettings>
+</Project>

adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc

@@ -0,0 +1,79 @@
+#
+# The ADI JESD204 Core is released under the following license, which is
+# different than all other HDL cores in this repository.
+#
+# Please read this, and understand the freedoms and responsibilities you have
+# by using this source code/core.
+#
+# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
+#
+# This core is free software, you can use run, copy, study, change, ask
+# questions about and improve this core. Distribution of source, or resulting
+# binaries (including those inside an FPGA or ASIC) require you to release the
+# source of the entire project (excluding the system libraries provide by the
+# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
+# License version 2 as published by the Free Software Foundation.
+#
+# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License version 2
+# along with this source code, and binary.  If not, see
+# <http://www.gnu.org/licenses/>.
+#
+# Commercial licenses (with commercial support) of this JESD204 core are also
+# available under terms different than the General Public License. (e.g. they
+# do not require you to accompany any image (FPGA or ASIC) using the JESD204
+# core with any corresponding source code.) For these alternate terms you must
+# purchase a license from Analog Devices Technology Licensing Office. Users
+# interested in such a license should contact [email protected] for
+# more information. This commercial license is sub-licensable (if you purchase
+# chips from Analog Devices, incorporate them into your PCB level product, and
+# purchase a JESD204 license, end users of your product will also have a
+# license to use this core in a commercial setting without releasing their
+# source code).
+#
+# In addition, we kindly ask you to acknowledge ADI in any program, application
+# or publication in which you use this JESD204 HDL core. (You are not required
+# to do so; it is up to your common sense to decide whether you want to comply
+# with this request or not.) For general publications, we suggest referencing :
+# “The design and implementation of the JESD204 HDL Core used in this project
+# is copyright © 2016-2017, Analog Devices, Inc.”
+#
+
+set script_dir [file dirname [info script]]
+
+source "$script_dir/util_cdc_constr.tcl"
+
+util_cdc_sync_event_constr {*|jesd204_up_sysref:i_up_sysref|sync_event:i_cdc_sysref_event}
+util_cdc_sync_event_constr {*|jesd204_up_tx:i_up_tx|sync_event:i_cdc_manual_sync_request}
+util_cdc_sync_data_constr {*|jesd204_up_tx:i_up_tx|sync_data:i_cdc_status}
+util_cdc_sync_bits_constr {*|jesd204_up_tx:i_up_tx|sync_bits:i_cdc_sync}
+
+set_false_path \
+  -from [get_registers {*|jesd204_up_common:i_up_common|up_reset_core}] \
+  -to [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[*]}]
+
+set_false_path \
+  -from [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[0]}] \
+  -to [get_registers {*|jesd204_up_common:i_up_common|up_reset_synchronizer_vector[*]}]
+
+set_false_path \
+  -to [get_pins -compatibility_mode {*|jesd204_up_common:i_up_common|up_core_reset_ext_synchronizer_vector[*]|clrn}]
+
+set_false_path \
+  -from [get_registers {*|jesd204_up_common:i_up_common|up_cfg_*}] \
+  -to [get_registers {*|jesd204_up_common:i_up_common|core_cfg_*}]
+
+set_false_path \
+  -from [get_registers {*|jesd204_up_tx:i_up_tx|up_cfg_ilas_data_*}] \
+  -to [get_registers {*|jesd204_up_tx:i_up_tx|core_ilas_config_data[*]}]
+
+set_false_path \
+  -from [get_registers {*|jesd204_up_tx:i_up_tx|up_cfg_*}] \
+  -to [get_registers {*|jesd204_up_common:i_up_common|core_extra_cfg[*]}]
+
+set_false_path \
+  -from [get_registers {*|jesd204_up_sysref:i_up_sysref|up_cfg_*}] \
+  -to [get_registers {*|jesd204_up_common:i_up_common|core_extra_cfg[*]}]

adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc

@@ -0,0 +1,126 @@
+#
+# The ADI JESD204 Core is released under the following license, which is
+# different than all other HDL cores in this repository.
+#
+# Please read this, and understand the freedoms and responsibilities you have
+# by using this source code/core.
+#
+# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
+#
+# This core is free software, you can use run, copy, study, change, ask
+# questions about and improve this core. Distribution of source, or resulting
+# binaries (including those inside an FPGA or ASIC) require you to release the
+# source of the entire project (excluding the system libraries provide by the
+# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
+# License version 2 as published by the Free Software Foundation.
+#
+# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License version 2
+# along with this source code, and binary.  If not, see
+# <http://www.gnu.org/licenses/>.
+#
+# Commercial licenses (with commercial support) of this JESD204 core are also
+# available under terms different than the General Public License. (e.g. they
+# do not require you to accompany any image (FPGA or ASIC) using the JESD204
+# core with any corresponding source code.) For these alternate terms you must
+# purchase a license from Analog Devices Technology Licensing Office. Users
+# interested in such a license should contact [email protected] for
+# more information. This commercial license is sub-licensable (if you purchase
+# chips from Analog Devices, incorporate them into your PCB level product, and
+# purchase a JESD204 license, end users of your product will also have a
+# license to use this core in a commercial setting without releasing their
+# source code).
+#
+# In addition, we kindly ask you to acknowledge ADI in any program, application
+# or publication in which you use this JESD204 HDL core. (You are not required
+# to do so; it is up to your common sense to decide whether you want to comply
+# with this request or not.) For general publications, we suggest referencing :
+# “The design and implementation of the JESD204 HDL Core used in this project
+# is copyright © 2016-2017, Analog Devices, Inc.”
+#
+
+set axi_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
+set core_clk [get_clocks -of_objects [get_ports core_clk]]
+
+set_property ASYNC_REG TRUE \
+  [get_cells -hier {*cdc_sync_stage1_reg*}] \
+  [get_cells -hier {*cdc_sync_stage2_reg*}]
+
+# Used for synchronizing resets with asynchronous de-assert
+set_property ASYNC_REG TRUE \
+  [get_cells -hier {up_reset_vector_reg*}] \
+  [get_cells -hier {core_reset_vector_reg*}] \
+  [get_cells -hier {up_reset_synchronizer_vector_reg*}] \
+  [get_cells -hier {up_core_reset_ext_synchronizer_vector_reg*}]
+
+set_false_path \
+  -from [get_pins {i_up_tx/i_cdc_status/out_toggle_d1_reg/C}] \
+  -to [get_pins {i_up_tx/i_cdc_status/i_sync_in/cdc_sync_stage1_reg[0]/D}]
+
+set_false_path \
+  -from [get_pins {i_up_tx/i_cdc_status/in_toggle_d1_reg/C}] \
+  -to [get_pins {i_up_tx/i_cdc_status/i_sync_out/cdc_sync_stage1_reg[0]/D}]
+
+set_false_path \
+  -from [get_pins {i_up_sysref/i_cdc_sysref_event/in_toggle_d1_reg/C}] \
+  -to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_out/cdc_sync_stage1_reg[0]/D}]
+
+set_false_path \
+  -from [get_pins {i_up_sysref/i_cdc_sysref_event/out_toggle_d1_reg/C}] \
+  -to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_in/cdc_sync_stage1_reg[0]/D}]
+
+set_false_path \
+  -from [get_pins {i_up_sysref/i_cdc_sysref_event/cdc_hold_reg*/C}] \
+  -to [get_pins {i_up_sysref/i_cdc_sysref_event/out_event_reg*/D}]
+
+# Don't place them too far appart
+set_max_delay -datapath_only \
+  -from [get_pins {i_up_tx/i_cdc_status/cdc_hold_reg[*]/C}] \
+  -to [get_pins {i_up_tx/i_cdc_status/out_data_reg[*]/D}] \
+  [get_property -min PERIOD $axi_clk]
+
+set_false_path \
+  -from $core_clk \
+  -to [get_pins {i_up_tx/i_cdc_sync/cdc_sync_stage1_reg[*]/D}]
+
+set_false_path \
+  -from [get_pins {i_up_common/up_reset_core_reg/C}] \
+  -to [get_pins {i_up_common/core_reset_vector_reg[*]/PRE}]
+
+set_false_path \
+  -from [get_pins {i_up_common/core_reset_vector_reg[0]/C}] \
+  -to [get_pins {i_up_common/up_reset_synchronizer_vector_reg[*]/PRE}]
+
+set_false_path \
+  -to [get_pins {i_up_common/up_core_reset_ext_synchronizer_vector_reg[*]/PRE}]
+
+set_max_delay -datapath_only \
+  -from [get_pins {i_up_common/up_cfg_*_reg*/C}] \
+  -to [get_pins {i_up_common/core_cfg_*_reg*/D}] \
+  [get_property -min PERIOD $core_clk]
+
+set_max_delay -datapath_only \
+  -from [get_pins {i_up_tx/up_cfg_ilas_data_*_reg*/C}] \
+  -to [get_cells {i_up_tx/*core_ilas_config_data_reg*}] \
+  [get_property -min PERIOD $core_clk]
+
+set_max_delay -datapath_only \
+  -from [get_pins {i_up_tx/up_cfg_*_reg*/C}] \
+  -to [get_pins {i_up_common/core_extra_cfg_reg[*]/D}] \
+  [get_property -min PERIOD $core_clk]
+
+set_max_delay -datapath_only \
+  -from [get_pins {i_up_sysref/up_cfg_*_reg*/C}] \
+  -to [get_pins {i_up_common/core_extra_cfg_reg[*]/D}] \
+  [get_property -min PERIOD $core_clk]
+
+set_false_path \
+  -from [get_pins {i_up_tx/i_cdc_manual_sync_request/out_toggle_d1_reg/C}] \
+  -to [get_pins {i_up_tx/i_cdc_manual_sync_request/i_sync_in/cdc_sync_stage1_reg[0]/D}]
+
+set_false_path \
+  -from [get_pins {i_up_tx/i_cdc_manual_sync_request/in_toggle_d1_reg/C}] \
+  -to [get_pins {i_up_tx/i_cdc_manual_sync_request/i_sync_out/cdc_sync_stage1_reg[0]/D}]

adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl

@@ -0,0 +1,171 @@
+#
+# The ADI JESD204 Core is released under the following license, which is
+# different than all other HDL cores in this repository.
+#
+# Please read this, and understand the freedoms and responsibilities you have
+# by using this source code/core.
+#
+# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
+#
+# This core is free software, you can use run, copy, study, change, ask
+# questions about and improve this core. Distribution of source, or resulting
+# binaries (including those inside an FPGA or ASIC) require you to release the
+# source of the entire project (excluding the system libraries provide by the
+# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
+# License version 2 as published by the Free Software Foundation.
+#
+# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License version 2
+# along with this source code, and binary.  If not, see
+# <http://www.gnu.org/licenses/>.
+#
+# Commercial licenses (with commercial support) of this JESD204 core are also
+# available under terms different than the General Public License. (e.g. they
+# do not require you to accompany any image (FPGA or ASIC) using the JESD204
+# core with any corresponding source code.) For these alternate terms you must
+# purchase a license from Analog Devices Technology Licensing Office. Users
+# interested in such a license should contact [email protected] for
+# more information. This commercial license is sub-licensable (if you purchase
+# chips from Analog Devices, incorporate them into your PCB level product, and
+# purchase a JESD204 license, end users of your product will also have a
+# license to use this core in a commercial setting without releasing their
+# source code).
+#
+# In addition, we kindly ask you to acknowledge ADI in any program, application
+# or publication in which you use this JESD204 HDL core. (You are not required
+# to do so; it is up to your common sense to decide whether you want to comply
+# with this request or not.) For general publications, we suggest referencing :
+# “The design and implementation of the JESD204 HDL Core used in this project
+# is copyright © 2016-2017, Analog Devices, Inc.”
+#
+
+package require qsys
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
+
+ad_ip_create axi_jesd204_tx "ADI JESD204 Transmit AXI Interface"
+
+set_module_property INTERNAL true
+
+# files
+
+ad_ip_files axi_jesd204_tx [list \
+  axi_jesd204_tx.v \
+  axi_jesd204_tx_constr.sdc \
+  jesd204_up_tx.v \
+  ../axi_jesd204_common/jesd204_up_common.v \
+  ../axi_jesd204_common/jesd204_up_sysref.v \
+  $ad_hdl_dir/library/common/up_axi.v \
+  $ad_hdl_dir/library/common/up_clock_mon.v \
+  $ad_hdl_dir/library/util_cdc/sync_bits.v \
+  $ad_hdl_dir/library/util_cdc/sync_data.v \
+  $ad_hdl_dir/library/util_cdc/sync_event.v \
+  $ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl \
+  $ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
+]
+
+# parameters
+
+add_parameter ID NATURAL 0
+set_parameter_property ID DISPLAY_NAME "Peripheral ID"
+set_parameter_property ID HDL_PARAMETER true
+
+add_parameter NUM_LANES INTEGER 1
+set_parameter_property NUM_LANES DISPLAY_NAME "Number of Lanes"
+set_parameter_property NUM_LANES ALLOWED_RANGES 1:8
+set_parameter_property NUM_LANES HDL_PARAMETER true
+
+add_parameter NUM_LINKS INTEGER 1
+set_parameter_property NUM_LINKS DISPLAY_NAME "Number of Links"
+set_parameter_property NUM_LINKS ALLOWED_RANGES 1:8
+set_parameter_property NUM_LINKS HDL_PARAMETER true
+
+# axi4 slave interface
+
+ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 14
+
+# interrupt
+
+add_interface interrupt interrupt end
+set_interface_property interrupt associatedClock s_axi_clock
+set_interface_property interrupt associatedReset s_axi_reset
+#set_interface_property interrupt associatedAddressablePoint s_axi
+add_interface_port interrupt irq irq Output 1
+
+# core clock
+
+add_interface core_clock clock end
+add_interface_port core_clock core_clk clk Input 1
+
+# core reset ext
+
+add_interface core_reset_ext reset end
+set_interface_property core_reset_ext associatedClock core_clock
+add_interface_port core_reset_ext core_reset_ext reset Input 1
+
+# core reset
+
+add_interface core_reset reset start
+set_interface_property core_reset associatedClock core_clock
+set_interface_property core_reset associatedResetSinks core_reset_ext
+add_interface_port core_reset core_reset reset Output 1
+
+# config interface
+
+add_interface config conduit end
+set_interface_property config associatedClock core_clock
+set_interface_property config associatedReset core_reset
+
+add_interface_port config core_cfg_beats_per_multiframe beats_per_multiframe Output 8
+add_interface_port config core_cfg_continuous_cgs continuous_cgs Output 1
+add_interface_port config core_cfg_continuous_ilas continuous_ilas Output 1
+add_interface_port config core_cfg_disable_char_replacement disable_char_replacement Output 1
+add_interface_port config core_cfg_disable_scrambler disable_scrambler Output 1
+add_interface_port config core_cfg_lanes_disable lanes_disable Output NUM_LANES
+add_interface_port config core_cfg_links_disable links_disable Output NUM_LINKS
+add_interface_port config core_cfg_lmfc_offset lmfc_offset Output 8
+add_interface_port config core_cfg_mframes_per_ilas mframes_per_ilas Output 8
+add_interface_port config core_cfg_octets_per_frame octets_per_frame Output 8
+add_interface_port config core_cfg_skip_ilas skip_ilas Output 1
+add_interface_port config core_cfg_sysref_disable sysref_disable Output 1
+add_interface_port config core_cfg_sysref_oneshot sysref_oneshot Output 1
+
+# control interface
+
+add_interface control conduit end
+set_interface_property control associatedClock core_clock
+set_interface_property control associatedReset core_reset
+
+add_interface_port control core_ctrl_manual_sync_request manual_sync_request Output 1
+
+# ilas config interface
+
+add_interface ilas_config conduit end
+set_interface_property ilas_config associatedClock core_clock
+set_interface_property ilas_config associatedReset core_reset
+
+add_interface_port ilas_config core_ilas_config_addr addr Input 2
+add_interface_port ilas_config core_ilas_config_data data Output 32*NUM_LANES
+add_interface_port ilas_config core_ilas_config_rd rd Input 1
+
+# event interface
+
+add_interface event conduit end
+set_interface_property event associatedClock core_clock
+set_interface_property event associatedReset core_reset
+
+add_interface_port event core_event_sysref_alignment_error sysref_alignment_error Input 1
+add_interface_port event core_event_sysref_edge sysref_edge Input 1
+
+# status interface
+
+add_interface status conduit end
+set_interface_property status associatedClock core_clock
+set_interface_property status associatedReset core_reset
+
+add_interface_port status core_status_state state Input 2
+add_interface_port status core_status_sync sync Input 1

adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl

@@ -0,0 +1,154 @@
+#
+# The ADI JESD204 Core is released under the following license, which is
+# different than all other HDL cores in this repository.
+#
+# Please read this, and understand the freedoms and responsibilities you have
+# by using this source code/core.
+#
+# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
+#
+# This core is free software, you can use run, copy, study, change, ask
+# questions about and improve this core. Distribution of source, or resulting
+# binaries (including those inside an FPGA or ASIC) require you to release the
+# source of the entire project (excluding the system libraries provide by the
+# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
+# License version 2 as published by the Free Software Foundation.
+#
+# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License version 2
+# along with this source code, and binary.  If not, see
+# <http://www.gnu.org/licenses/>.
+#
+# Commercial licenses (with commercial support) of this JESD204 core are also
+# available under terms different than the General Public License. (e.g. they
+# do not require you to accompany any image (FPGA or ASIC) using the JESD204
+# core with any corresponding source code.) For these alternate terms you must
+# purchase a license from Analog Devices Technology Licensing Office. Users
+# interested in such a license should contact [email protected] for
+# more information. This commercial license is sub-licensable (if you purchase
+# chips from Analog Devices, incorporate them into your PCB level product, and
+# purchase a JESD204 license, end users of your product will also have a
+# license to use this core in a commercial setting without releasing their
+# source code).
+#
+# In addition, we kindly ask you to acknowledge ADI in any program, application
+# or publication in which you use this JESD204 HDL core. (You are not required
+# to do so; it is up to your common sense to decide whether you want to comply
+# with this request or not.) For general publications, we suggest referencing :
+# “The design and implementation of the JESD204 HDL Core used in this project
+# is copyright © 2016-2017, Analog Devices, Inc.”
+#
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
+
+adi_ip_create axi_jesd204_tx
+adi_ip_files axi_jesd204_tx [list \
+  "../../common/up_axi.v" \
+  "axi_jesd204_tx_constr.xdc" \
+  "axi_jesd204_tx_ooc.ttcl" \
+  "jesd204_up_tx.v" \
+  "axi_jesd204_tx.v" \
+]
+
+adi_ip_properties axi_jesd204_tx
+
+adi_ip_ttcl axi_jesd204_tx "axi_jesd204_tx_ooc.ttcl"
+
+set_property PROCESSING_ORDER LATE [ipx::get_files axi_jesd204_tx_constr.xdc \
+  -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \
+  -filter {NAME =~ *synthesis*}]]
+
+adi_ip_add_core_dependencies { \
+  analog.com:user:axi_jesd204_common:1.0 \
+}
+
+set_property display_name "ADI JESD204C Transmit AXI Interface" [ipx::current_core]
+set_property description "ADI JESD204B Transmit AXI Interface" [ipx::current_core]
+
+adi_add_bus "tx_cfg" "master" \
+  "analog.com:interface:jesd204_tx_cfg_rtl:1.0" \
+  "analog.com:interface:jesd204_tx_cfg:1.0" \
+  { \
+    { "core_cfg_lanes_disable" "lanes_disable" } \
+    { "core_cfg_links_disable" "links_disable" } \
+    { "core_cfg_beats_per_multiframe" "beats_per_multiframe" } \
+    { "core_cfg_octets_per_frame" "octets_per_frame" } \
+    { "core_cfg_lmfc_offset" "lmfc_offset" } \
+    { "core_cfg_sysref_oneshot" "sysref_oneshot" } \
+    { "core_cfg_sysref_disable" "sysref_disable" } \
+    { "core_cfg_continuous_cgs" "continuous_cgs" } \
+    { "core_cfg_continuous_ilas" "continuous_ilas" } \
+    { "core_cfg_skip_ilas" "skip_ilas" } \
+    { "core_cfg_mframes_per_ilas" "mframes_per_ilas" } \
+    { "core_cfg_disable_char_replacement" "disable_char_replacement" } \
+    { "core_cfg_disable_scrambler" "disable_scrambler" } \
+  }
+
+adi_add_bus "tx_ilas_config" "slave" \
+  "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" \
+  "analog.com:interface:jesd204_tx_ilas_config:1.0" \
+  { \
+    { "core_ilas_config_rd" "rd" } \
+    { "core_ilas_config_addr" "addr" } \
+    { "core_ilas_config_data" "data" } \
+  }
+
+adi_add_bus "tx_event" "slave" \
+  "analog.com:interface:jesd204_tx_event_rtl:1.0" \
+  "analog.com:interface:jesd204_tx_event:1.0" \
+  { \
+    { "core_event_sysref_alignment_error" "sysref_alignment_error" } \
+    { "core_event_sysref_edge" "sysref_edge" } \
+  }
+
+adi_add_bus "tx_status" "slave" \
+  "analog.com:interface:jesd204_tx_status_rtl:1.0" \
+  "analog.com:interface:jesd204_tx_status:1.0" \
+  { \
+    { "core_status_state" "state" } \
+    { "core_status_sync" "sync" } \
+  }
+
+adi_add_bus "tx_ctrl" "master" \
+  "analog.com:interface:jesd204_tx_ctrl_rtl:1.0" \
+  "analog.com:interface:jesd204_tx_ctrl:1.0" \
+  { \
+    { "core_ctrl_manual_sync_request" "manual_sync_request" } \
+  }
+
+ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core]
+
+adi_add_bus_clock "core_clk" "tx_status:tx_event:tx_ilas_config:tx_cfg:tx_ctrl" \
+  "core_reset" "master"
+
+set_property DRIVER_VALUE "0" [ipx::get_ports "core_reset_ext"]
+
+adi_set_bus_dependency "tx_ilas_config" "tx_ilas_config" \
+	"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
+
+adi_set_bus_dependency "tx_ctrl" "tx_ctrl" \
+	"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
+
+set cc [ipx::current_core]
+set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
+
+# Link layer mode
+set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
+ipgui::move_param -component $cc -order 0 $p -parent $page0
+set_property -dict [list \
+ "display_name" "Link Layer mode" \
+ "tooltip" "Link Layer mode" \
+ "widget" "comboBox" \
+] $p
+
+set_property -dict [list \
+  value_validation_type pairs \
+  value_validation_pairs {64B66B 2 8B10B 1} \
+] [ipx::get_user_parameters $p -of_objects $cc]
+
+ipx::create_xgui_files [ipx::current_core]
+ipx::save_core [ipx::current_core]

adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl

@@ -0,0 +1,61 @@
+#
+# The ADI JESD204 Core is released under the following license, which is
+# different than all other HDL cores in this repository.
+#
+# Please read this, and understand the freedoms and responsibilities you have
+# by using this source code/core.
+#
+# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
+#
+# This core is free software, you can use run, copy, study, change, ask
+# questions about and improve this core. Distribution of source, or resulting
+# binaries (including those inside an FPGA or ASIC) require you to release the
+# source of the entire project (excluding the system libraries provide by the
+# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
+# License version 2 as published by the Free Software Foundation.
+#
+# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License version 2
+# along with this source code, and binary.  If not, see
+# <http://www.gnu.org/licenses/>.
+#
+# Commercial licenses (with commercial support) of this JESD204 core are also
+# available under terms different than the General Public License. (e.g. they
+# do not require you to accompany any image (FPGA or ASIC) using the JESD204
+# core with any corresponding source code.) For these alternate terms you must
+# purchase a license from Analog Devices Technology Licensing Office. Users
+# interested in such a license should contact [email protected] for
+# more information. This commercial license is sub-licensable (if you purchase
+# chips from Analog Devices, incorporate them into your PCB level product, and
+# purchase a JESD204 license, end users of your product will also have a
+# license to use this core in a commercial setting without releasing their
+# source code).
+#
+# In addition, we kindly ask you to acknowledge ADI in any program, application
+# or publication in which you use this JESD204 HDL core. (You are not required
+# to do so; it is up to your common sense to decide whether you want to comply
+# with this request or not.) For general publications, we suggest referencing :
+# “The design and implementation of the JESD204 HDL Core used in this project
+# is copyright © 2016-2017, Analog Devices, Inc.”
+#
+
+<: setFileUsedIn { out_of_context synthesis implementation } :>
+<: ;#Component and file information :>
+<: set ComponentName [getComponentNameString] :>
+<: setOutputDirectory "./" :>
+<: setFileName $ComponentName :>
+<: setFileExtension "_ooc.xdc" :>
+
+# This XDC is used only for OOC mode of synthesis, implementation.
+# These are default values for timing driven synthesis during OOC flow.
+# These values will be overwritten during implementation with information
+# from top level.
+
+create_clock -name s_axi_aclk -period 10  [get_ports s_axi_aclk]
+create_clock -name core_clk   -period 2.5 [get_ports core_clk]
+
+################################################################################
+

adi_library/jesd204/axi_jesd204_tx/jesd204_up_tx.v

@@ -0,0 +1,305 @@
+//
+// The ADI JESD204 Core is released under the following license, which is
+// different than all other HDL cores in this repository.
+//
+// Please read this, and understand the freedoms and responsibilities you have
+// by using this source code/core.
+//
+// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
+//
+// This core is free software, you can use run, copy, study, change, ask
+// questions about and improve this core. Distribution of source, or resulting
+// binaries (including those inside an FPGA or ASIC) require you to release the
+// source of the entire project (excluding the system libraries provide by the
+// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
+// License version 2 as published by the Free Software Foundation.
+//
+// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License version 2
+// along with this source code, and binary.  If not, see
+// <http://www.gnu.org/licenses/>.
+//
+// Commercial licenses (with commercial support) of this JESD204 core are also
+// available under terms different than the General Public License. (e.g. they
+// do not require you to accompany any image (FPGA or ASIC) using the JESD204
+// core with any corresponding source code.) For these alternate terms you must
+// purchase a license from Analog Devices Technology Licensing Office. Users
+// interested in such a license should contact [email protected] for
+// more information. This commercial license is sub-licensable (if you purchase
+// chips from Analog Devices, incorporate them into your PCB level product, and
+// purchase a JESD204 license, end users of your product will also have a
+// license to use this core in a commercial setting without releasing their
+// source code).
+//
+// In addition, we kindly ask you to acknowledge ADI in any program, application
+// or publication in which you use this JESD204 HDL core. (You are not required
+// to do so; it is up to your common sense to decide whether you want to comply
+// with this request or not.) For general publications, we suggest referencing :
+// “The design and implementation of the JESD204 HDL Core used in this project
+// is copyright © 2016-2017, Analog Devices, Inc.”
+//
+
+`timescale 1ns/100ps
+
+module jesd204_up_tx # (
+  parameter NUM_LANES = 1,
+  parameter NUM_LINKS = 1
+) (
+  input up_clk,
+  input up_reset,
+
+  input [11:0] up_raddr,
+  output reg [31:0] up_rdata,
+  input up_wreq,
+  input [11:0] up_waddr,
+  input [31:0] up_wdata,
+
+  input up_cfg_is_writeable,
+
+  output reg up_cfg_skip_ilas,
+  output reg up_cfg_continuous_ilas,
+  output reg up_cfg_continuous_cgs,
+  output reg [7:0] up_cfg_mframes_per_ilas,
+
+  input core_clk,
+  input core_ilas_config_rd,
+  input [1:0] core_ilas_config_addr,
+  output reg [32*NUM_LANES-1:0] core_ilas_config_data,
+
+  output core_ctrl_manual_sync_request,
+
+  input [1:0] core_status_state,
+  input [NUM_LINKS-1:0] core_status_sync
+);
+
+reg [31:0] up_cfg_ilas_data[0:NUM_LANES-1][0:3];
+reg up_ctrl_manual_sync_request = 1'b0;
+
+wire [1:0] up_status_state;
+wire [NUM_LINKS-1:0] up_status_sync;
+
+sync_bits #(
+  .NUM_OF_BITS (NUM_LINKS))
+i_cdc_sync (
+  .in_bits(core_status_sync),
+  .out_clk(up_clk),
+  .out_resetn(1'b1),
+  .out_bits(up_status_sync)
+);
+
+sync_data #(
+  .NUM_OF_BITS(2)
+) i_cdc_status (
+  .in_clk(core_clk),
+  .in_data(core_status_state),
+  .out_clk(up_clk),
+  .out_data(up_status_state)
+);
+
+sync_event #(
+  .NUM_OF_EVENTS(1),
+  .ASYNC_CLK(1)
+) i_cdc_manual_sync_request (
+  .in_clk(up_clk),
+  .in_event(up_ctrl_manual_sync_request),
+  .out_clk(core_clk),
+  .out_event(core_ctrl_manual_sync_request)
+);
+
+integer i;
+
+always @(*) begin
+  case (up_raddr)
+  /* JESD TX configuration */
+  12'h090: up_rdata = {
+    /* 03-31 */ 29'h00, /* Reserved for future additions */
+    /*    02 */ up_cfg_skip_ilas, /* Don't send ILAS, go directly from CGS to DATA */
+    /*    01 */ up_cfg_continuous_ilas, /* Continuously send ILAS sequence */
+    /*    00 */ up_cfg_continuous_cgs /* Continuously send CGS characters */
+  };
+  12'h091: up_rdata = {
+    /* 08-31 */ 24'h00, /* Reserved for future additions */
+    /* 00-07 */ up_cfg_mframes_per_ilas /* Number of multiframes send during the ILAS */
+  };
+
+  /* JESD TX status */
+  12'ha0: up_rdata = {
+    /* 12-31 */ 20'h00, /* Reserved for future additions */
+    /* 04-11 */ up_status_sync, /* Raw value of the SYNC pin */
+    /* 02-03 */ 2'b0, /* Reserved fo future extension of the status_state field */
+    /* 00-01 */ up_status_state /* State of the internal state machine (0=CGS, 1=ILAS, 2=DATA) */
+  };
+  default: begin
+    if (up_raddr[10:3] >= ('h300/32) &&
+        up_raddr[10:3] < (('h300/32) + NUM_LANES) &&
+      up_raddr[2] == 1'b1) begin
+      up_rdata = up_cfg_ilas_data[up_raddr[5:3]][up_raddr[1:0]];
+    end else begin
+       up_rdata = 32'h00000000;
+    end
+  end
+  endcase
+
+end
+
+always @(posedge up_clk) begin
+  if (up_reset == 1'b1) begin
+    up_cfg_skip_ilas <= 1'b0;
+    up_cfg_continuous_ilas <= 1'b0;
+    up_cfg_continuous_cgs <= 1'b0;
+    up_cfg_mframes_per_ilas <= 'h3;
+  end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
+    case (up_waddr)
+    /* JESD TX configuraton */
+    12'h090: begin
+      up_cfg_skip_ilas <= up_wdata[2];
+      up_cfg_continuous_ilas <= up_wdata[1];
+      up_cfg_continuous_cgs <= up_wdata[0];
+    end
+    12'h091: begin
+//      We'll enable this if we ever have a usecase
+//      cfg_mframes_per_ilas <= up_wdata[7:0];
+    end
+    endcase
+  end
+end
+
+always @(posedge up_clk) begin
+  if (up_reset == 1'b1) begin
+    up_ctrl_manual_sync_request <= 1'b0;
+  end else if (up_wreq == 1'b1 && up_waddr == 12'h092) begin
+    up_ctrl_manual_sync_request <= up_wdata[0];
+  end else begin
+    up_ctrl_manual_sync_request <= 1'b0;
+  end
+end
+
+/* Shared ILAS data can be access through any lane register map window */
+
+/* Shared ILAS data */
+reg [7:0] up_cfg_ilas_data_did = 'h00;
+reg [3:0] up_cfg_ilas_data_bid = 'h00;
+reg [4:0] up_cfg_ilas_data_l = 'h00;
+reg up_cfg_ilas_data_scr = 'h00;
+reg [7:0] up_cfg_ilas_data_f = 'h00;
+reg [4:0] up_cfg_ilas_data_k = 'h00;
+reg [7:0] up_cfg_ilas_data_m = 'h00;
+reg [4:0] up_cfg_ilas_data_n = 'h00;
+reg [1:0] up_cfg_ilas_data_cs = 'h00;
+reg [4:0] up_cfg_ilas_data_np = 'h00;
+reg [2:0] up_cfg_ilas_data_subclassv = 'h00;
+reg [4:0] up_cfg_ilas_data_s = 'h00;
+reg [2:0] up_cfg_ilas_data_jesdv = 'h00;
+reg [4:0] up_cfg_ilas_data_cf = 'h00;
+reg up_cfg_ilas_data_hd = 'h00;
+
+/* Per lane ILAS data */
+reg [4:0] up_cfg_ilas_data_lid[0:NUM_LANES-1];
+reg [7:0] up_cfg_ilas_data_fchk[0:NUM_LANES-1];
+
+always @(*) begin
+  for (i = 0; i < NUM_LANES; i = i + 1) begin
+    up_cfg_ilas_data[i][0] = {
+      4'b0000,
+      up_cfg_ilas_data_bid,
+      up_cfg_ilas_data_did,
+      16'h00
+    };
+    up_cfg_ilas_data[i][1] = {
+      3'b000,
+      up_cfg_ilas_data_k,
+      up_cfg_ilas_data_f,
+      up_cfg_ilas_data_scr,
+      2'b00,
+      up_cfg_ilas_data_l,
+      3'b000,
+      up_cfg_ilas_data_lid[i]
+    };
+    up_cfg_ilas_data[i][2] = {
+      up_cfg_ilas_data_jesdv,
+      up_cfg_ilas_data_s,
+      up_cfg_ilas_data_subclassv,
+      up_cfg_ilas_data_np,
+      up_cfg_ilas_data_cs,
+      1'b0,
+      up_cfg_ilas_data_n,
+      up_cfg_ilas_data_m
+    };
+    up_cfg_ilas_data[i][3] = {
+      up_cfg_ilas_data_fchk[i],
+      16'h0000,
+      up_cfg_ilas_data_hd,
+      2'b00,
+      up_cfg_ilas_data_cf
+    };
+  end
+end
+
+always @(posedge up_clk) begin
+  if (up_reset == 1'b1) begin
+    up_cfg_ilas_data_did <= 'h00;
+    up_cfg_ilas_data_bid <= 'h00;
+    up_cfg_ilas_data_scr <= 'h00;
+    up_cfg_ilas_data_f <= 'h00;
+    up_cfg_ilas_data_k <= 'h00;
+    up_cfg_ilas_data_m <= 'h00;
+    up_cfg_ilas_data_n <= 'h00;
+    up_cfg_ilas_data_cs <= 'h00;
+    up_cfg_ilas_data_np <= 'h00;
+    up_cfg_ilas_data_subclassv <= 'h00;
+    up_cfg_ilas_data_s <= 'h00;
+    up_cfg_ilas_data_jesdv <= 'h00;
+    up_cfg_ilas_data_cf <= 'h00;
+    up_cfg_ilas_data_hd <= 'h00;
+    up_cfg_ilas_data_l <= 'h00;
+    for (i = 0; i < NUM_LANES; i = i + 1) begin
+      up_cfg_ilas_data_lid[i] <= 'h00;
+      up_cfg_ilas_data_fchk[i] <= 'h00;
+    end
+  end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
+    for (i = 0; i < NUM_LANES; i = i + 1) begin
+      if (up_waddr[10:2] == ('h310 / 16) + i*2) begin
+        case (up_waddr[1:0])
+          2'h0: begin
+            up_cfg_ilas_data_bid <= up_wdata[27:24];
+            up_cfg_ilas_data_did <= up_wdata[23:16];
+          end
+          2'h1: begin
+            up_cfg_ilas_data_k <= up_wdata[28:24];
+            up_cfg_ilas_data_f <= up_wdata[23:16];
+            up_cfg_ilas_data_scr <= up_wdata[15];
+            up_cfg_ilas_data_l <= up_wdata[12:8];
+            up_cfg_ilas_data_lid[i] <= up_wdata[4:0];
+          end
+          2'h2: begin
+            up_cfg_ilas_data_jesdv <= up_wdata[31:29];
+            up_cfg_ilas_data_s <= up_wdata[28:24];
+            up_cfg_ilas_data_subclassv <= up_wdata[23:21];
+            up_cfg_ilas_data_np <= up_wdata[20:16];
+            up_cfg_ilas_data_cs <= up_wdata[15:14];
+            up_cfg_ilas_data_n <= up_wdata[12:8];
+            up_cfg_ilas_data_m <= up_wdata[7:0];
+          end
+          2'h3: begin
+            up_cfg_ilas_data_fchk[i] <= up_wdata[31:24];
+            up_cfg_ilas_data_hd <= up_wdata[7];
+            up_cfg_ilas_data_cf <= up_wdata[4:0];
+          end
+        endcase
+      end
+    end
+  end
+end
+
+always @(posedge core_clk) begin
+  if (core_ilas_config_rd == 1'b1) begin
+    for (i = 0; i < NUM_LANES; i = i + 1) begin
+      core_ilas_config_data[i*32+:32] <= up_cfg_ilas_data[i][core_ilas_config_addr];
+    end
+  end
+end
+
+endmodule

adi_library/jesd204/axi_jesd204_tx/vivado.jou

@@ -0,0 +1,12 @@
+#-----------------------------------------------------------
+# Vivado v2019.1.3 (64-bit)
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+# IP Build 2633630 on Wed Sep  4 12:30:14 MDT 2019
+# Start of session at: Thu Dec  9 15:17:11 2021
+# Process ID: 6698
+# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_tx
+# Command line: vivado -mode batch -source axi_jesd204_tx_ip.tcl
+# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_tx/vivado.log
+# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_tx/vivado.jou
+#-----------------------------------------------------------
+source axi_jesd204_tx_ip.tcl

adi_library/jesd204/axi_jesd204_tx/xgui/axi_jesd204_tx_v1_0.tcl

@@ -0,0 +1,85 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "LINK_MODE" -parent ${Page_0} -widget comboBox
+  ipgui::add_param $IPINST -name "ENABLE_LINK_STATS" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "NUM_LANES" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "NUM_LINKS" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.ENABLE_LINK_STATS { PARAM_VALUE.ENABLE_LINK_STATS } {
+	# Procedure called to update ENABLE_LINK_STATS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.ENABLE_LINK_STATS { PARAM_VALUE.ENABLE_LINK_STATS } {
+	# Procedure called to validate ENABLE_LINK_STATS
+	return true
+}
+
+proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
+	# Procedure called to update ID when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
+	# Procedure called to validate ID
+	return true
+}
+
+proc update_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } {
+	# Procedure called to update LINK_MODE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } {
+	# Procedure called to validate LINK_MODE
+	return true
+}
+
+proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
+	# Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
+	# Procedure called to validate NUM_LANES
+	return true
+}
+
+proc update_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } {
+	# Procedure called to update NUM_LINKS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } {
+	# Procedure called to validate NUM_LINKS
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
+}
+
+proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES}
+}
+
+proc update_MODELPARAM_VALUE.NUM_LINKS { MODELPARAM_VALUE.NUM_LINKS PARAM_VALUE.NUM_LINKS } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.NUM_LINKS}] ${MODELPARAM_VALUE.NUM_LINKS}
+}
+
+proc update_MODELPARAM_VALUE.LINK_MODE { MODELPARAM_VALUE.LINK_MODE PARAM_VALUE.LINK_MODE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.LINK_MODE}] ${MODELPARAM_VALUE.LINK_MODE}
+}
+
+proc update_MODELPARAM_VALUE.ENABLE_LINK_STATS { MODELPARAM_VALUE.ENABLE_LINK_STATS PARAM_VALUE.ENABLE_LINK_STATS } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.ENABLE_LINK_STATS}] ${MODELPARAM_VALUE.ENABLE_LINK_STATS}
+}
+