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josh
2023-03-18 15:35:53 +08:00
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adi_library/jesd204/jesd204_rx/.timestamp_intel
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adi_library/jesd204/jesd204_rx/Makefile
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := jesd204_rx
GENERIC_DEPS += align_mux.v
GENERIC_DEPS += elastic_buffer.v
GENERIC_DEPS += jesd204_ilas_monitor.v
GENERIC_DEPS += jesd204_lane_latency_monitor.v
GENERIC_DEPS += jesd204_rx.v
GENERIC_DEPS += jesd204_rx_cgs.v
GENERIC_DEPS += jesd204_rx_ctrl.v
GENERIC_DEPS += jesd204_rx_frame_align_monitor.v
GENERIC_DEPS += jesd204_rx_frame_mark.v
GENERIC_DEPS += jesd204_rx_lane.v
XILINX_DEPS += error_monitor.v
XILINX_DEPS += jesd204_rx_constr.ttcl
XILINX_DEPS += jesd204_rx_ctrl_64b.v
XILINX_DEPS += jesd204_rx_header.v
XILINX_DEPS += jesd204_rx_ip.tcl
XILINX_DEPS += jesd204_rx_lane_64b.v
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_event.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_event_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_status.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_status_rtl.xml
XILINX_LIB_DEPS += jesd204/jesd204_common
XILINX_INTERFACE_DEPS += jesd204/interfaces
INTEL_DEPS += ../jesd204_common/jesd204_eof_generator.v
INTEL_DEPS += ../jesd204_common/jesd204_lmfc.v
INTEL_DEPS += ../jesd204_common/jesd204_scrambler.v
INTEL_DEPS += ../jesd204_common/pipeline_stage.v
INTEL_DEPS += jesd204_rx_constr.sdc
INTEL_DEPS += jesd204_rx_hw.tcl
include ../../scripts/library.mk
adi_library/jesd204/jesd204_rx/align_mux.v
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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
`timescale 1ns/100ps
module align_mux #(
parameter DATA_PATH_WIDTH = 4
) (
input clk,
input [1:0] align,
input [DATA_PATH_WIDTH*8-1:0] in_data,
input [DATA_PATH_WIDTH-1:0] in_charisk,
output reg [DATA_PATH_WIDTH*8-1:0] out_data,
output reg [DATA_PATH_WIDTH-1:0] out_charisk
);
reg [DATA_PATH_WIDTH*8-1:0] in_data_d1;
reg [DATA_PATH_WIDTH-1:0] in_charisk_d1;
always @(posedge clk) begin
in_data_d1 <= in_data;
in_charisk_d1 <= in_charisk;
end
always @(*) begin
case (align)
'h0: out_data = in_data_d1;
'h1: out_data = {in_data[7:0],in_data_d1[31:8]};
'h2: out_data = {in_data[15:0],in_data_d1[31:16]};
'h3: out_data = {in_data[23:0],in_data_d1[31:24]};
endcase
case (align)
'h0: out_charisk = in_charisk_d1;
'h1: out_charisk = {in_charisk[0:0],in_charisk_d1[3:1]};
'h2: out_charisk = {in_charisk[1:0],in_charisk_d1[3:2]};
'h3: out_charisk = {in_charisk[2:0],in_charisk_d1[3:3]};
endcase
end
endmodule
adi_library/jesd204/jesd204_rx/component.xml
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adi_library/jesd204/jesd204_rx/elastic_buffer.v
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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
`timescale 1ns/100ps
module elastic_buffer #(
parameter WIDTH = 32,
parameter SIZE = 256
) (
input clk,
input reset,
input [WIDTH-1:0] wr_data,
output reg [WIDTH-1:0] rd_data,
input ready_n,
input do_release_n
);
localparam ADDR_WIDTH = SIZE > 128 ? 7 :
SIZE > 64 ? 6 :
SIZE > 32 ? 5 :
SIZE > 16 ? 4 :
SIZE > 8 ? 3 :
SIZE > 4 ? 2 :
SIZE > 2 ? 1 : 0;
reg [ADDR_WIDTH:0] wr_addr = 'h00;
reg [ADDR_WIDTH:0] rd_addr = 'h00;
reg [WIDTH-1:0] mem[0:SIZE - 1];
always @(posedge clk) begin
if (ready_n == 1'b1) begin
wr_addr <= 'h00;
end else begin
mem[wr_addr] <= wr_data;
wr_addr <= wr_addr + 1'b1;
end
end
always @(posedge clk) begin
if (do_release_n == 1'b1) begin
rd_addr <= 'h00;
end else begin
rd_addr <= rd_addr + 1'b1;
rd_data <= mem[rd_addr];
end
end
endmodule
adi_library/jesd204/jesd204_rx/error_monitor.v
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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
`timescale 1ns/100ps
module error_monitor #(
parameter EVENT_WIDTH = 16,
parameter CNT_WIDTH = 32
) (
input clk,
input reset,
input active,
input [EVENT_WIDTH-1:0] error_event,
input [EVENT_WIDTH-1:0] error_event_mask,
output reg [CNT_WIDTH-1:0] status_err_cnt = 'h0
);
localparam EVENT_WIDTH_LOG = $clog2(EVENT_WIDTH);
reg [EVENT_WIDTH-1:0] err;
function [EVENT_WIDTH_LOG-1:0] num_set_bits;
input [EVENT_WIDTH-1:0] x;
integer j;
begin
num_set_bits = 0;
for (j = 0; j < EVENT_WIDTH; j = j + 1) begin
num_set_bits = num_set_bits + x[j];
end
end
endfunction
always @(posedge clk) begin
if (active == 1'b1) begin
err <= (~error_event_mask) & error_event;
end else begin
err <= {EVENT_WIDTH{1'b0}};
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
status_err_cnt <= 'h0;
end else if (~&status_err_cnt[CNT_WIDTH-1:EVENT_WIDTH_LOG]) begin
status_err_cnt <= status_err_cnt + num_set_bits(err);
end
end
endmodule
adi_library/jesd204/jesd204_rx/gui/jesd204_rx_v1_0.gtcl
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# This file is automatically written. Do not modify.
proc gen_USERPARAMETER_DATA_PATH_WIDTH_VALUE {LINK_MODE } {expr $LINK_MODE*4}
adi_library/jesd204/jesd204_rx/jesd204_ilas_monitor.v
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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
`timescale 1ns/100ps
module jesd204_ilas_monitor #(
parameter DATA_PATH_WIDTH = 4
) (
input clk,
input reset,
input [DATA_PATH_WIDTH*8-1:0] data,
input [DATA_PATH_WIDTH-1:0] charisk28,
output reg ilas_config_valid,
output reg [1:0] ilas_config_addr,
output reg [DATA_PATH_WIDTH*8-1:0] ilas_config_data,
output data_ready_n
);
reg [3:0] multi_frame_counter = 'h00;
reg [7:0] frame_counter = 'h00;
reg [7:0] length = 'h00;
localparam STATE_ILAS = 1'b1;
localparam STATE_DATA = 1'b0;
reg state = STATE_ILAS;
reg next_state;
reg prev_was_last = 1'b0;
reg frame_length_error = 1'b0;
assign data_ready_n = next_state;
always @(*) begin
next_state = state;
if (reset == 1'b0 && prev_was_last == 1'b1) begin
if (charisk28[0] != 1'b1 || data[7:5] != 3'h0) begin
next_state = STATE_DATA;
end
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
state <= STATE_ILAS;
end else begin
state <= next_state;
end
end
always @(posedge clk) begin
if (reset == 1'b1 || (charisk28[3] == 1'b1 && data[31:29] == 3'h3)) begin
prev_was_last <= 1'b1;
end else begin
prev_was_last <= 1'b0;
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
multi_frame_counter <= 'h00;
end else if (charisk28[0] == 1'b1 && data[7:5] == 3'h0 && state == STATE_ILAS) begin
multi_frame_counter <= multi_frame_counter + 1'b1;
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
length <= 'h00;
end else if (prev_was_last == 1'b1) begin
if (length == 'h00) begin
length <= frame_counter;
end
end
end
always @(posedge clk) begin
frame_length_error <= 1'b0;
if (prev_was_last == 1'b1) begin
if (length != 'h00 && length != frame_counter) begin
frame_length_error <= 1'b1;
end
end
end
always @(posedge clk) begin
if (prev_was_last == 1'b1) begin
frame_counter <= 'h00;
end else begin
frame_counter <= frame_counter + 1'b1;
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
ilas_config_valid <= 1'b0;
end else if (state == STATE_ILAS) begin
if (charisk28[1] == 1'b1 && data[15:13] == 3'h4) begin
ilas_config_valid <= 1'b1;
end else if (ilas_config_addr == 'h3) begin
ilas_config_valid <= 1'b0;
end
end
end
always @(posedge clk) begin
if (ilas_config_valid == 1'b0) begin
ilas_config_addr <= 1'b0;
end else if (ilas_config_valid == 1'b1) begin
ilas_config_addr <= ilas_config_addr + 1'b1;
end
end
always @(posedge clk) begin
ilas_config_data <= data;
end
endmodule
adi_library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v
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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
`timescale 1ns/100ps
module jesd204_lane_latency_monitor #(
parameter NUM_LANES = 1
) (
input clk,
input reset,
input [NUM_LANES-1:0] lane_ready,
input [NUM_LANES*2-1:0] lane_frame_align,
output [14*NUM_LANES-1:0] lane_latency,
output [NUM_LANES-1:0] lane_latency_ready
);
reg [11:0] beat_counter;
reg [11:0] lane_latency_mem[0:NUM_LANES-1];
reg [NUM_LANES-1:0] lane_captured = 'h00;
always @(posedge clk) begin
if (reset == 1'b1) begin
beat_counter <= 'h0;
end else if (beat_counter != 'hfff) begin
beat_counter <= beat_counter + 1'b1;
end
end
generate
genvar i;
for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
always @(posedge clk) begin
if (reset == 1'b1) begin
lane_latency_mem[i] <= 'h00;
lane_captured[i] <= 1'b0;
end else if (lane_ready[i] == 1'b1 && lane_captured[i] == 1'b0) begin
lane_latency_mem[i] <= beat_counter;
lane_captured[i] <= 1'b1;
end
end
assign lane_latency[i*14+13:i*14] = {lane_latency_mem[i],lane_frame_align[i*2+1:i*2]};
assign lane_latency_ready[i] = lane_captured[i];
end
endgenerate
endmodule
adi_library/jesd204/jesd204_rx/jesd204_rx.cache/wt/project.wpc
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version:1
6d6f64655f636f756e7465727c42617463684d6f6465:1
eof:
adi_library/jesd204/jesd204_rx/jesd204_rx.hw/jesd204_rx.lpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
adi_library/jesd204/jesd204_rx/jesd204_rx.v
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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
`timescale 1ns/100ps
module jesd204_rx #(
parameter NUM_LANES = 1,
parameter NUM_LINKS = 1,
parameter NUM_INPUT_PIPELINE = 1,
parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
/* Only 4 is supported at the moment for 8b/10b and 8 for 64b */
parameter DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4,
parameter ENABLE_FRAME_ALIGN_CHECK = 1,
parameter ENABLE_FRAME_ALIGN_ERR_RESET = 0
) (
input clk,
input reset,
input [DATA_PATH_WIDTH*8*NUM_LANES-1:0] phy_data,
input [2*NUM_LANES-1:0] phy_header,
input [DATA_PATH_WIDTH*NUM_LANES-1:0] phy_charisk,
input [DATA_PATH_WIDTH*NUM_LANES-1:0] phy_notintable,
input [DATA_PATH_WIDTH*NUM_LANES-1:0] phy_disperr,
input [NUM_LANES-1:0] phy_block_sync,
input sysref,
output lmfc_edge,
output lmfc_clk,
output event_sysref_alignment_error,
output event_sysref_edge,
output event_frame_alignment_error,
output event_unexpected_lane_state_error,
output [NUM_LINKS-1:0] sync,
output phy_en_char_align,
output [DATA_PATH_WIDTH*8*NUM_LANES-1:0] rx_data,
output rx_valid,
output [DATA_PATH_WIDTH-1:0] rx_eof,
output [DATA_PATH_WIDTH-1:0] rx_sof,
input [NUM_LANES-1:0] cfg_lanes_disable,
input [NUM_LINKS-1:0] cfg_links_disable,
input [7:0] cfg_beats_per_multiframe,
input [7:0] cfg_octets_per_frame,
input [7:0] cfg_lmfc_offset,
input cfg_sysref_disable,
input cfg_sysref_oneshot,
input cfg_buffer_early_release,
input [7:0] cfg_buffer_delay,
input cfg_disable_char_replacement,
input cfg_disable_scrambler,
input ctrl_err_statistics_reset,
input [6:0] ctrl_err_statistics_mask,
input [7:0] cfg_frame_align_err_threshold,
output [32*NUM_LANES-1:0] status_err_statistics_cnt,
output [NUM_LANES-1:0] ilas_config_valid,
output [NUM_LANES*2-1:0] ilas_config_addr,
output [NUM_LANES*32-1:0] ilas_config_data,
output [1:0] status_ctrl_state,
output [2*NUM_LANES-1:0] status_lane_cgs_state,
output [NUM_LANES-1:0] status_lane_ifs_ready,
output [14*NUM_LANES-1:0] status_lane_latency,
output [3*NUM_LANES-1:0] status_lane_emb_state,
output [8*NUM_LANES-1:0] status_lane_frame_align_err_cnt
);
/*
* Can be used to enable additional pipeline stages to ease timing. Usually not
* necessary.
*/
localparam CHAR_INFO_REGISTERED = 0;
localparam ALIGN_MUX_REGISTERED = 0;
localparam SCRAMBLER_REGISTERED = 0;
/*
* Maximum number of octets per multiframe for ADI JESD204 DACs is 256 (Adjust
* as necessary). Divide by data path width.
*/
localparam MAX_OCTETS_PER_FRAME = 16;
localparam MAX_OCTETS_PER_MULTIFRAME =
(MAX_OCTETS_PER_FRAME * 32) > 1024 ? 1024 : (MAX_OCTETS_PER_FRAME * 32);
localparam MAX_BEATS_PER_MULTIFRAME = MAX_OCTETS_PER_MULTIFRAME / DATA_PATH_WIDTH;
localparam ELASTIC_BUFFER_SIZE = MAX_BEATS_PER_MULTIFRAME;
localparam LMFC_COUNTER_WIDTH = MAX_BEATS_PER_MULTIFRAME > 256 ? 9 :
MAX_BEATS_PER_MULTIFRAME > 128 ? 8 :
MAX_BEATS_PER_MULTIFRAME > 64 ? 7 :
MAX_BEATS_PER_MULTIFRAME > 32 ? 6 :
MAX_BEATS_PER_MULTIFRAME > 16 ? 5 :
MAX_BEATS_PER_MULTIFRAME > 8 ? 4 :
MAX_BEATS_PER_MULTIFRAME > 4 ? 3 :
MAX_BEATS_PER_MULTIFRAME > 2 ? 2 : 1;
/* Helper for common expressions */
localparam DW = 8*DATA_PATH_WIDTH*NUM_LANES;
localparam CW = DATA_PATH_WIDTH*NUM_LANES;
localparam HW = 2*NUM_LANES;
wire [NUM_LANES-1:0] cgs_reset;
wire [NUM_LANES-1:0] cgs_ready;
wire [NUM_LANES-1:0] ifs_reset;
reg buffer_release_n = 1'b1;
reg buffer_release_d1 = 1'b0;
wire [NUM_LANES-1:0] buffer_ready_n;
wire all_buffer_ready_n;
reg core_reset;
reg eof_reset = 1'b1;
wire [DW-1:0] phy_data_r;
wire [HW-1:0] phy_header_r;
wire [CW-1:0] phy_charisk_r;
wire [CW-1:0] phy_notintable_r;
wire [CW-1:0] phy_disperr_r;
wire [NUM_LANES-1:0] phy_block_sync_r;
wire [DW-1:0] rx_data_s;
wire rx_valid_s = buffer_release_d1;
wire [7:0] lmfc_counter;
wire latency_monitor_reset;
wire [2*NUM_LANES-1:0] frame_align;
wire [NUM_LANES-1:0] ifs_ready;
wire event_data_phase;
wire err_statistics_reset;
reg [NUM_LANES-1:0] frame_align_err_thresh_met = {NUM_LANES{1'b0}};
reg [NUM_LANES-1:0] event_frame_alignment_error_per_lane = {NUM_LANES{1'b0}};
reg buffer_release_opportunity = 1'b0;
always @(posedge clk) begin
if (lmfc_counter == cfg_buffer_delay ||
cfg_buffer_early_release == 1'b1) begin
buffer_release_opportunity <= 1'b1;
end else begin
buffer_release_opportunity <= 1'b0;
end
end
assign all_buffer_ready_n = |(buffer_ready_n & ~cfg_lanes_disable);
always @(posedge clk) begin
if (reset == 1'b1) begin
buffer_release_n <= 1'b1;
end else begin
if (buffer_release_opportunity == 1'b1) begin
buffer_release_n <= all_buffer_ready_n;
end
end
buffer_release_d1 <= ~buffer_release_n;
eof_reset <= buffer_release_n;
end
pipeline_stage #(
.WIDTH(NUM_LANES + (3 * CW) + HW + DW),
.REGISTERED(NUM_INPUT_PIPELINE)
) i_input_pipeline_stage (
.clk(clk),
.in({
phy_data,
phy_header,
phy_charisk,
phy_notintable,
phy_disperr,
phy_block_sync
}),
.out({
phy_data_r,
phy_header_r,
phy_charisk_r,
phy_notintable_r,
phy_disperr_r,
phy_block_sync_r
})
);
pipeline_stage #(
.WIDTH(DW+1),
.REGISTERED(1)
) i_output_pipeline_stage (
.clk(clk),
.in({
rx_data_s,
rx_valid_s
}),
.out({
rx_data,
rx_valid
})
);
jesd204_lmfc i_lmfc (
.clk(clk),
.reset(core_reset),
.cfg_beats_per_multiframe(cfg_beats_per_multiframe),
.cfg_lmfc_offset(cfg_lmfc_offset),
.cfg_sysref_oneshot(cfg_sysref_oneshot),
.cfg_sysref_disable(cfg_sysref_disable),
.sysref(sysref),
.lmfc_edge(lmfc_edge),
.lmfc_clk(lmfc_clk),
.lmfc_counter(lmfc_counter),
.lmc_edge(),
.lmc_quarter_edge(),
.eoemb(),
.sysref_edge(event_sysref_edge),
.sysref_alignment_error(event_sysref_alignment_error)
);
jesd204_eof_generator #(
.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
.MAX_OCTETS_PER_FRAME(MAX_OCTETS_PER_FRAME)
) i_eof_gen (
.clk(clk),
.reset(eof_reset),
.lmfc_edge(lmfc_edge),
.cfg_octets_per_frame(cfg_octets_per_frame),
.cfg_generate_eomf(1'b0),
.sof(rx_sof),
.eof(rx_eof),
.eomf()
);
generate
genvar i;
if (LINK_MODE[0] == 1) begin : mode_8b10b
wire unexpected_lane_state_error;
reg unexpected_lane_state_error_d = 1'b0;
jesd204_rx_ctrl #(
.NUM_LANES(NUM_LANES),
.NUM_LINKS(NUM_LINKS)
) i_rx_ctrl (
.clk(clk),
.reset(core_reset),
.cfg_lanes_disable(cfg_lanes_disable),
.cfg_links_disable(cfg_links_disable),
.phy_ready(1'b1),
.phy_en_char_align(phy_en_char_align),
.lmfc_edge(lmfc_edge),
.sync(sync),
.latency_monitor_reset(latency_monitor_reset),
.cgs_reset(cgs_reset),
.cgs_ready(cgs_ready),
.ifs_reset(ifs_reset),
.status_state(status_ctrl_state),
.event_data_phase(event_data_phase)
);
// Reset core when frame alignment errors occur
if(ENABLE_FRAME_ALIGN_CHECK && ENABLE_FRAME_ALIGN_ERR_RESET) begin : gen_frame_align_err_reset
reg [7:0] reset_cnt;
always @(posedge clk) begin
if(reset) begin
reset_cnt <= 8'h00;
end else begin
if(|frame_align_err_thresh_met) begin
reset_cnt <= 8'hFF;
end else if(reset_cnt != 0) begin
reset_cnt <= reset_cnt - 1'b1;
end
end
core_reset <= reset | (reset_cnt != 0);
end
end else begin : gen_no_frame_align_err_reset
always @(*) begin
core_reset = reset;
end
end
assign err_statistics_reset = ctrl_err_statistics_reset ||
event_data_phase;
for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
localparam D_START = i * DATA_PATH_WIDTH*8;
localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1;
localparam C_START = i * DATA_PATH_WIDTH;
localparam C_STOP = C_START + DATA_PATH_WIDTH-1;
jesd204_rx_lane #(
.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
.CHAR_INFO_REGISTERED(CHAR_INFO_REGISTERED),
.ALIGN_MUX_REGISTERED(ALIGN_MUX_REGISTERED),
.SCRAMBLER_REGISTERED(SCRAMBLER_REGISTERED),
.ELASTIC_BUFFER_SIZE(ELASTIC_BUFFER_SIZE),
.ENABLE_FRAME_ALIGN_CHECK(ENABLE_FRAME_ALIGN_CHECK)
) i_lane (
.clk(clk),
.reset(core_reset),
.phy_data(phy_data_r[D_STOP:D_START]),
.phy_charisk(phy_charisk_r[C_STOP:C_START]),
.phy_notintable(phy_notintable_r[C_STOP:C_START]),
.phy_disperr(phy_disperr_r[C_STOP:C_START]),
.cgs_reset(cgs_reset[i]),
.cgs_ready(cgs_ready[i]),
.ifs_reset(ifs_reset[i]),
.rx_data(rx_data_s[D_STOP:D_START]),
.buffer_release_n(buffer_release_n),
.buffer_ready_n(buffer_ready_n[i]),
.cfg_beats_per_multiframe(cfg_beats_per_multiframe),
.cfg_octets_per_frame(cfg_octets_per_frame),
.cfg_disable_scrambler(cfg_disable_scrambler),
.err_statistics_reset(err_statistics_reset),
.ctrl_err_statistics_mask(ctrl_err_statistics_mask[2:0]),
.status_err_statistics_cnt(status_err_statistics_cnt[32*i+31:32*i]),
.ilas_config_valid(ilas_config_valid[i]),
.ilas_config_addr(ilas_config_addr[2*i+1:2*i]),
.ilas_config_data(ilas_config_data[D_STOP:D_START]),
.status_cgs_state(status_lane_cgs_state[2*i+1:2*i]),
.status_ifs_ready(ifs_ready[i]),
.status_frame_align(frame_align[2*i+1:2*i]),
.status_frame_align_err_cnt(status_lane_frame_align_err_cnt[8*i+7:8*i])
);
if(ENABLE_FRAME_ALIGN_CHECK) begin : gen_frame_align_err_thresh
always @(posedge clk) begin
if (reset) begin
frame_align_err_thresh_met[i] <= 1'b0;
event_frame_alignment_error_per_lane[i] <= 1'b0;
end else begin
if (status_lane_frame_align_err_cnt[8*i+7:8*i] >= cfg_frame_align_err_threshold) begin
frame_align_err_thresh_met[i] <= cgs_ready[i];
event_frame_alignment_error_per_lane[i] <= ~frame_align_err_thresh_met[i];
end else begin
frame_align_err_thresh_met[i] <= 1'b0;
event_frame_alignment_error_per_lane[i] <= 1'b0;
end
end
end
end
end
assign event_frame_alignment_error = |event_frame_alignment_error_per_lane;
/* If one of the enabled lanes falls out of DATA phase while the link is in DATA phase
* report an error event */
assign unexpected_lane_state_error = |(~(cgs_ready|cfg_lanes_disable)) & &status_ctrl_state;
always @(posedge clk) begin
unexpected_lane_state_error_d <= unexpected_lane_state_error;
end
assign event_unexpected_lane_state_error = unexpected_lane_state_error & ~unexpected_lane_state_error_d;
/* Delay matching based on the number of pipeline stages */
reg [NUM_LANES-1:0] ifs_ready_d1 = 1'b0;
reg [NUM_LANES-1:0] ifs_ready_d2 = 1'b0;
reg [NUM_LANES-1:0] ifs_ready_mux;
always @(posedge clk) begin
ifs_ready_d1 <= ifs_ready;
ifs_ready_d2 <= ifs_ready_d1;
end
always @(*) begin
case (SCRAMBLER_REGISTERED + ALIGN_MUX_REGISTERED)
1: ifs_ready_mux = ifs_ready_d1;
2: ifs_ready_mux = ifs_ready_d2;
default: ifs_ready_mux = ifs_ready;
endcase
end
jesd204_lane_latency_monitor #(
.NUM_LANES(NUM_LANES)
) i_lane_latency_monitor (
.clk(clk),
.reset(latency_monitor_reset),
.lane_ready(ifs_ready_mux),
.lane_frame_align(frame_align),
.lane_latency_ready(status_lane_ifs_ready),
.lane_latency(status_lane_latency)
);
end
if (LINK_MODE[1] == 1) begin : mode_64b66b
wire [NUM_LANES-1:0] emb_lock;
always @(*) begin
core_reset = reset;
end
jesd204_rx_ctrl_64b #(
.NUM_LANES(NUM_LANES)
) i_jesd204_rx_ctrl_64b (
.clk(clk),
.reset(core_reset),
.cfg_lanes_disable(cfg_lanes_disable),
.phy_block_sync(phy_block_sync_r),
.emb_lock(emb_lock),
.all_emb_lock(all_emb_lock),
.buffer_release_n(buffer_release_n),
.status_state(status_ctrl_state),
.event_unexpected_lane_state_error(event_unexpected_lane_state_error)
);
for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
localparam D_START = i * DATA_PATH_WIDTH*8;
localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1;
localparam H_START = i * 2;
localparam H_STOP = H_START + 2-1;
wire [7:0] status_lane_skew;
jesd204_rx_lane_64b #(
.ELASTIC_BUFFER_SIZE(ELASTIC_BUFFER_SIZE)
) i_lane (
.clk(clk),
.reset(core_reset),
.phy_data(phy_data_r[D_STOP:D_START]),
.phy_header(phy_header_r[H_STOP:H_START]),
.phy_block_sync(phy_block_sync_r[i]),
.cfg_disable_scrambler(cfg_disable_scrambler),
.cfg_header_mode(2'b0),
.cfg_rx_thresh_emb_err(5'd8),
.cfg_beats_per_multiframe(cfg_beats_per_multiframe),
.rx_data(rx_data_s[D_STOP:D_START]),
.buffer_release_n(buffer_release_n),
.buffer_ready_n(buffer_ready_n[i]),
.all_buffer_ready_n(all_buffer_ready_n),
.lmfc_edge(lmfc_edge),
.emb_lock(emb_lock[i]),
.ctrl_err_statistics_reset(ctrl_err_statistics_reset),
.ctrl_err_statistics_mask(ctrl_err_statistics_mask[6:3]),
.status_err_statistics_cnt(status_err_statistics_cnt[32*i+31:32*i]),
.status_lane_emb_state(status_lane_emb_state[3*i+2:3*i]),
.status_lane_skew(status_lane_skew)
);
assign status_lane_latency[14*(i+1)-1:14*i] = {3'b0,status_lane_skew,3'b0};
end
// Assign unused outputs
assign sync = 'b0;
assign phy_en_char_align = 1'b0;
assign ilas_config_valid ='b0;
assign ilas_config_addr = 'b0;
assign ilas_config_data = 'b0;
assign status_lane_cgs_state = 'b0;
assign status_lane_ifs_ready = {NUM_LANES{1'b1}};
assign event_frame_alignment_error = 1'b0;
end
endgenerate
endmodule
adi_library/jesd204/jesd204_rx/jesd204_rx.xpr
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<Board/>
<DashboardSummary Version="1" Minor="0">
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<Dashboard Name="default_dashboard">
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</Gadget>
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<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
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</Gadget>
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
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adi_library/jesd204/jesd204_rx/jesd204_rx_cgs.v
+125
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@@ -0,0 +1,125 @@
//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
`timescale 1ns/100ps
module jesd204_rx_cgs #(
parameter DATA_PATH_WIDTH = 4
) (
input clk,
input reset,
input [DATA_PATH_WIDTH-1:0] char_is_cgs,
input [DATA_PATH_WIDTH-1:0] char_is_error,
output ready,
output [1:0] status_state
);
localparam CGS_STATE_INIT = 2'b00;
localparam CGS_STATE_CHECK = 2'b01;
localparam CGS_STATE_DATA = 2'b10;
reg [1:0] state = CGS_STATE_INIT;
reg rdy = 1'b0;
reg [1:0] beat_error_count = 'h00;
wire beat_is_cgs = &char_is_cgs;
wire beat_has_error = |char_is_error;
wire beat_is_all_error = &char_is_error;
assign ready = rdy;
assign status_state = state;
always @(posedge clk) begin
if (state == CGS_STATE_INIT) begin
beat_error_count <= 'h00;
end else begin
if (beat_has_error == 1'b1) begin
beat_error_count <= beat_error_count + 1'b1;
end else begin
beat_error_count <= 'h00;
end
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
state <= CGS_STATE_INIT;
end else begin
case (state)
CGS_STATE_INIT: begin
if (beat_is_cgs == 1'b1) begin
state <= CGS_STATE_CHECK;
end
end
CGS_STATE_CHECK: begin
if (beat_has_error == 1'b1) begin
if (beat_error_count == 'h3 ||
beat_is_all_error == 1'b1) begin
state <= CGS_STATE_INIT;
end
end else begin
state <= CGS_STATE_DATA;
end
end
CGS_STATE_DATA: begin
if (beat_has_error == 1'b1) begin
state <= CGS_STATE_CHECK;
end
end
endcase
end
end
always @(posedge clk) begin
case (state)
CGS_STATE_INIT: rdy <= 1'b0;
CGS_STATE_DATA: rdy <= 1'b1;
default: rdy <= rdy;
endcase
end
endmodule
adi_library/jesd204/jesd204_rx/jesd204_rx_constr.sdc
+47
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@@ -0,0 +1,47 @@
#
# The ADI JESD204 Core is released under the following license, which is
# different than all other HDL cores in this repository.
#
# Please read this, and understand the freedoms and responsibilities you have
# by using this source code/core.
#
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
#
# This core is free software, you can use run, copy, study, change, ask
# questions about and improve this core. Distribution of source, or resulting
# binaries (including those inside an FPGA or ASIC) require you to release the
# source of the entire project (excluding the system libraries provide by the
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License version 2
# along with this source code, and binary. If not, see
# <http://www.gnu.org/licenses/>.
#
# Commercial licenses (with commercial support) of this JESD204 core are also
# available under terms different than the General Public License. (e.g. they
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
# core with any corresponding source code.) For these alternate terms you must
# purchase a license from Analog Devices Technology Licensing Office. Users
# interested in such a license should contact [email protected] for
# more information. This commercial license is sub-licensable (if you purchase
# chips from Analog Devices, incorporate them into your PCB level product, and
# purchase a JESD204 license, end users of your product will also have a
# license to use this core in a commercial setting without releasing their
# source code).
#
# In addition, we kindly ask you to acknowledge ADI in any program, application
# or publication in which you use this JESD204 HDL core. (You are not required
# to do so; it is up to your common sense to decide whether you want to comply
# with this request or not.) For general publications, we suggest referencing :
# “The design and implementation of the JESD204 HDL Core used in this project
# is copyright © 2016-2017, Analog Devices, Inc.”
#
# SYNC~ is a asynchronous interface
set_false_path \
-from [get_registers *|jesd204_rx_ctrl:i_rx_ctrl|sync_n[0]]
adi_library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl
+58
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@@ -0,0 +1,58 @@
#
# The ADI JESD204 Core is released under the following license, which is
# different than all other HDL cores in this repository.
#
# Please read this, and understand the freedoms and responsibilities you have
# by using this source code/core.
#
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
#
# This core is free software, you can use run, copy, study, change, ask
# questions about and improve this core. Distribution of source, or resulting
# binaries (including those inside an FPGA or ASIC) require you to release the
# source of the entire project (excluding the system libraries provide by the
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License version 2
# along with this source code, and binary. If not, see
# <http://www.gnu.org/licenses/>.
#
# Commercial licenses (with commercial support) of this JESD204 core are also
# available under terms different than the General Public License. (e.g. they
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
# core with any corresponding source code.) For these alternate terms you must
# purchase a license from Analog Devices Technology Licensing Office. Users
# interested in such a license should contact [email protected] for
# more information. This commercial license is sub-licensable (if you purchase
# chips from Analog Devices, incorporate them into your PCB level product, and
# purchase a JESD204 license, end users of your product will also have a
# license to use this core in a commercial setting without releasing their
# source code).
#
# In addition, we kindly ask you to acknowledge ADI in any program, application
# or publication in which you use this JESD204 HDL core. (You are not required
# to do so; it is up to your common sense to decide whether you want to comply
# with this request or not.) For general publications, we suggest referencing :
# “The design and implementation of the JESD204 HDL Core used in this project
# is copyright © 2016-2017, Analog Devices, Inc.”
#
<: set ComponentName [getComponentNameString] :>
<: setOutputDirectory "./" :>
<: setFileName [ttcl_add $ComponentName "_constr"] :>
<: setFileExtension ".xdc" :>
<: setFileProcessingOrder late :>
<: set sysref_iob [get_property PARAM_VALUE.SYSREF_IOB] :>
set_property ASYNC_REG TRUE \
[get_cells {i_lmfc/sysref_d1_reg}] \
[get_cells {i_lmfc/sysref_d2_reg}]
# Make sure that the device clock to sysref skew is at least somewhat
# predictable
set_property IOB <=: $sysref_iob :> \
[get_cells {i_lmfc/sysref_r_reg}]
adi_library/jesd204/jesd204_rx/jesd204_rx_ctrl.v
+180
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@@ -0,0 +1,180 @@
//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
`timescale 1ns/100ps
module jesd204_rx_ctrl #(
parameter NUM_LANES = 1,
parameter NUM_LINKS = 1
) (
input clk,
input reset,
input [NUM_LANES-1:0] cfg_lanes_disable,
input [NUM_LINKS-1:0] cfg_links_disable,
input phy_ready,
output phy_en_char_align,
output [NUM_LANES-1:0] cgs_reset,
input [NUM_LANES-1:0] cgs_ready,
output [NUM_LANES-1:0] ifs_reset,
input lmfc_edge,
output [NUM_LINKS-1:0] sync,
output reg latency_monitor_reset,
output [1:0] status_state,
output event_data_phase
);
localparam STATE_RESET = 0;
localparam STATE_WAIT_FOR_PHY = 1;
localparam STATE_CGS = 2;
localparam STATE_SYNCHRONIZED = 3;
reg [2:0] state = STATE_RESET;
reg [2:0] next_state = STATE_RESET;
reg [NUM_LANES-1:0] cgs_rst = {NUM_LANES{1'b1}};
reg [NUM_LANES-1:0] ifs_rst = {NUM_LANES{1'b1}};
reg [NUM_LINKS-1:0] sync_n = {NUM_LINKS{1'b1}};
reg en_align = 1'b0;
reg state_good = 1'b0;
reg [7:0] good_counter = 'h00;
wire [7:0] good_cnt_limit_s;
wire good_cnt_limit_reached_s;
assign cgs_reset = cgs_rst;
assign ifs_reset = ifs_rst;
assign sync = sync_n;
assign phy_en_char_align = en_align;
assign status_state = state;
always @(posedge clk) begin
case (state)
STATE_RESET: begin
cgs_rst <= {NUM_LANES{1'b1}};
ifs_rst <= {NUM_LANES{1'b1}};
sync_n <= {NUM_LINKS{1'b1}};
latency_monitor_reset <= 1'b1;
end
STATE_CGS: begin
sync_n <= cfg_links_disable;
cgs_rst <= cfg_lanes_disable;
end
STATE_SYNCHRONIZED: begin
if (lmfc_edge == 1'b1) begin
sync_n <= {NUM_LINKS{1'b1}};
ifs_rst <= cfg_lanes_disable;
latency_monitor_reset <= 1'b0;
end
end
endcase
end
always @(*) begin
case (state)
STATE_RESET: state_good = 1'b1;
STATE_WAIT_FOR_PHY: state_good = phy_ready;
STATE_CGS: state_good = &(cgs_ready | cfg_lanes_disable);
STATE_SYNCHRONIZED: state_good = 1'b1;
default: state_good = 1'b0;
endcase
end
assign good_cnt_limit_s = (state == STATE_CGS) ? 'hff : 'h7;
assign good_cnt_limit_reached_s = good_counter == good_cnt_limit_s;
always @(posedge clk) begin
if (reset) begin
good_counter <= 'h00;
end else if (state_good == 1'b1) begin
if (good_cnt_limit_reached_s) begin
good_counter <= 'h00;
end else begin
good_counter <= good_counter + 1'b1;
end
end else begin
good_counter <= 'h00;
end
end
always @(posedge clk) begin
case (state)
STATE_CGS: en_align <= 1'b1;
default: en_align <= 1'b0;
endcase
end
always @(*) begin
case (state)
STATE_RESET: next_state = STATE_WAIT_FOR_PHY;
STATE_WAIT_FOR_PHY: next_state = STATE_CGS;
STATE_CGS: next_state = STATE_SYNCHRONIZED;
default: next_state = state_good ? state : STATE_RESET;
endcase
end
always @(posedge clk) begin
if (reset == 1'b1) begin
state <= STATE_RESET;
end else begin
if (good_cnt_limit_reached_s) begin
state <= next_state;
end
end
end
assign event_data_phase = state == STATE_CGS &&
next_state == STATE_SYNCHRONIZED &&
good_cnt_limit_reached_s;
endmodule
adi_library/jesd204/jesd204_rx/jesd204_rx_ctrl_64b.v
+140
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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
`timescale 1ns/100ps
module jesd204_rx_ctrl_64b #(
parameter NUM_LANES = 1
) (
input clk,
input reset,
input [NUM_LANES-1:0] cfg_lanes_disable,
input [NUM_LANES-1:0] phy_block_sync,
input [NUM_LANES-1:0] emb_lock,
output all_emb_lock,
input buffer_release_n,
output [1:0] status_state,
output reg event_unexpected_lane_state_error
);
localparam STATE_RESET = 2'b00;
localparam STATE_WAIT_BS = 2'b01;
localparam STATE_BLOCK_SYNC = 2'b10;
localparam STATE_DATA = 2'b11;
reg [1:0] state = STATE_RESET;
reg [1:0] next_state;
reg [5:0] good_cnt;
reg rst_good_cnt;
wire [NUM_LANES-1:0] phy_block_sync_masked;
wire [NUM_LANES-1:0] emb_lock_masked;
wire all_block_sync;
assign phy_block_sync_masked = phy_block_sync | cfg_lanes_disable;
assign emb_lock_masked = emb_lock | cfg_lanes_disable;
assign all_block_sync = &phy_block_sync_masked;
assign all_emb_lock = &emb_lock_masked;
always @(*) begin
next_state = state;
rst_good_cnt = 1'b1;
event_unexpected_lane_state_error = 1'b0;
case (state)
STATE_RESET:
next_state = STATE_WAIT_BS;
STATE_WAIT_BS:
if (all_block_sync) begin
rst_good_cnt = 1'b0;
if (&good_cnt) begin
next_state = STATE_BLOCK_SYNC;
end
end
STATE_BLOCK_SYNC:
if (~all_block_sync) begin
next_state = STATE_WAIT_BS;
end else if (all_emb_lock & ~buffer_release_n) begin
rst_good_cnt = 1'b0;
if (&good_cnt) begin
next_state = STATE_DATA;
end
end
STATE_DATA:
if (~all_block_sync) begin
next_state = STATE_WAIT_BS;
event_unexpected_lane_state_error = 1'b1;
end else if (~all_emb_lock | buffer_release_n) begin
next_state = STATE_BLOCK_SYNC;
event_unexpected_lane_state_error = 1'b1;
end
endcase
end
// Wait n consecutive valid cycles before jumping into next state
always @(posedge clk) begin
if (reset || rst_good_cnt) begin
good_cnt <= 'h0;
end else begin
good_cnt <= good_cnt + 1;
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
state <= STATE_RESET;
end else begin
state <= next_state;
end
end
assign status_state = state;
endmodule
adi_library/jesd204/jesd204_rx/jesd204_rx_frame_align_monitor.v
+181
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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
`timescale 1ns/100ps
module jesd204_rx_frame_align_monitor #(
parameter DATA_PATH_WIDTH = 4
) (
input clk,
input reset,
input [7:0] cfg_beats_per_multiframe,
input [7:0] cfg_octets_per_frame,
input cfg_disable_scrambler,
input [DATA_PATH_WIDTH-1:0] charisk28,
input [DATA_PATH_WIDTH*8-1:0] data,
output reg [7:0] align_err_cnt
);
// Reset alignment error count on good multiframe alignment,
// or on good frame or multiframe alignment
// If disabled, misalignments could me masked if
// due to cfg_beats_per_multiframe mismatch or due to
// a slip of a multiple of cfg_octets_per_frame octets
localparam RESET_COUNT_ON_MF_ONLY = 1'b1;
localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 :
DATA_PATH_WIDTH == 4 ? 2 : 1;
function automatic [DPW_LOG2*2-1:0] count_ones(input [DATA_PATH_WIDTH*2-1:0] val);
reg [DPW_LOG2*2-1:0] ii;
begin
count_ones = 0;
for(ii = 0; ii != (DATA_PATH_WIDTH*2-1); ii=ii+1) begin
count_ones = count_ones + val[ii];
end
end
endfunction
reg [DATA_PATH_WIDTH-1:0] char_is_a;
reg [DATA_PATH_WIDTH-1:0] char_is_f;
wire [DATA_PATH_WIDTH-1:0] eof;
wire [DATA_PATH_WIDTH-1:0] eomf;
reg [DATA_PATH_WIDTH-1:0] eof_err;
reg [DATA_PATH_WIDTH-1:0] eof_good;
reg [DATA_PATH_WIDTH-1:0] eomf_err;
reg [DATA_PATH_WIDTH-1:0] eomf_good;
reg align_good;
reg align_err;
reg [DPW_LOG2*2-1:0] cur_align_err_cnt;
wire [8:0] align_err_cnt_next;
jesd204_rx_frame_mark #(
.DATA_PATH_WIDTH (DATA_PATH_WIDTH)
) frame_mark (
.clk (clk),
.reset (reset),
.cfg_beats_per_multiframe (cfg_beats_per_multiframe),
.cfg_octets_per_frame (cfg_octets_per_frame),
.charisk28 (charisk28),
.data (data),
.sof (),
.eof (eof),
.somf (),
.eomf (eomf)
);
genvar ii;
generate
for (ii = 0; ii < DATA_PATH_WIDTH; ii = ii + 1) begin: gen_k_char
always @(*) begin
char_is_a[ii] = 1'b0;
char_is_f[ii] = 1'b0;
if(charisk28[ii]) begin
if(data[ii*8+7:ii*8+5] == 3'd3) begin
char_is_a[ii] = 1'b1;
end
if(data[ii*8+7:ii*8+5] == 3'd7) begin
char_is_f[ii] = 1'b1;
end
end
end
// TODO: support cfg_disable_scrambler
always @(posedge clk) begin
if(reset) begin
eomf_err[ii] <= 1'b0;
eomf_good[ii] <= 1'b0;
eof_err[ii] <= 1'b0;
eof_good[ii] <= 1'b0;
end else begin
eomf_err[ii] <= !cfg_disable_scrambler && (char_is_a[ii] && !eomf[ii]);
eomf_good[ii] <= !cfg_disable_scrambler && (char_is_a[ii] && eomf[ii]);
eof_err[ii] <= !cfg_disable_scrambler && (char_is_f[ii] && !eof[ii]);
eof_good[ii] <= !cfg_disable_scrambler && (char_is_f[ii] && eof[ii]);
end
end
end
endgenerate
always @(posedge clk) begin
if(reset) begin
align_good <= 1'b0;
align_err <= 1'b0;
end else begin
if(RESET_COUNT_ON_MF_ONLY) begin
align_good <= |eomf_good;
end else begin
align_good <= |({eomf_good, eof_good});
end
align_err <= |({eomf_err, eof_err});
end
end
assign align_err_cnt_next = {1'b0, align_err_cnt} + cur_align_err_cnt;
// Alignment error counter
// Resets upon good alignment
always @(posedge clk) begin
if(reset) begin
align_err_cnt <= 8'd0;
cur_align_err_cnt <= 'd0;
end else begin
cur_align_err_cnt <= count_ones({eomf_err, eof_err});
if(align_good && !align_err) begin
align_err_cnt <= 8'd0;
end else if(align_err_cnt_next[8]) begin
align_err_cnt <= 8'hFF;
end else begin
align_err_cnt <= align_err_cnt_next[7:0];
end
end
end
endmodule
adi_library/jesd204/jesd204_rx/jesd204_rx_frame_mark.v
+193
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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
// Limitations:
// DATA_PATH_WIDTH = 4
// F*K=4, multiples of DATA_PATH_WIDTH
// F=1,2,3,4,6, and multiples of DATA_PATH_WIDTH
`timescale 1ns/100ps
module jesd204_rx_frame_mark #(
parameter DATA_PATH_WIDTH = 4
) (
input clk,
input reset,
input [7:0] cfg_beats_per_multiframe,
input [7:0] cfg_octets_per_frame,
input [DATA_PATH_WIDTH-1:0] charisk28,
input [DATA_PATH_WIDTH*8-1:0] data,
output reg [DATA_PATH_WIDTH-1:0] sof,
output reg [DATA_PATH_WIDTH-1:0] eof,
output reg [DATA_PATH_WIDTH-1:0] somf,
output reg [DATA_PATH_WIDTH-1:0] eomf
);
localparam MAX_OCTETS_PER_FRAME = 16;
localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
localparam CW = MAX_OCTETS_PER_FRAME > 128 ? 8 :
MAX_OCTETS_PER_FRAME > 64 ? 7 :
MAX_OCTETS_PER_FRAME > 32 ? 6 :
MAX_OCTETS_PER_FRAME > 16 ? 5 :
MAX_OCTETS_PER_FRAME > 8 ? 4 :
MAX_OCTETS_PER_FRAME > 4 ? 3 :
MAX_OCTETS_PER_FRAME > 2 ? 2 : 1;
localparam BEATS_PER_FRAME_WIDTH = CW-DPW_LOG2;
reg [1:0] beat_cnt_mod_3;
reg [BEATS_PER_FRAME_WIDTH-1:0] beat_cnt_frame;
wire cur_sof;
wire cur_eof;
reg [7:0] beat_cnt_mf;
wire cur_somf;
wire cur_eomf;
wire [BEATS_PER_FRAME_WIDTH-1:0] cfg_beats_per_frame = cfg_octets_per_frame[CW-1:DPW_LOG2];
reg [DATA_PATH_WIDTH-1:0] sof_f_3[2:0];
reg [DATA_PATH_WIDTH-1:0] eof_f_3[2:0];
reg [DATA_PATH_WIDTH-1:0] sof_f_6[2:0];
reg [DATA_PATH_WIDTH-1:0] eof_f_6[2:0];
initial begin
sof_f_3[0] = {4'b1001};
sof_f_3[1] = {4'b0100};
sof_f_3[2] = {4'b0010};
eof_f_3[0] = {4'b0100};
eof_f_3[1] = {4'b0010};
eof_f_3[2] = {4'b1001};
sof_f_6[0] = {4'b0001};
sof_f_6[1] = {4'b0100};
sof_f_6[2] = {4'b0000};
eof_f_6[0] = {4'b0000};
eof_f_6[1] = {4'b0010};
eof_f_6[2] = {4'b1000};
end
// Beat count % 3, to support F=3,6
always @(posedge clk) begin
if(reset) begin
beat_cnt_mod_3 <= 2'd0;
end else begin
if(beat_cnt_mod_3 == 2'd2) begin
beat_cnt_mod_3 <= 2'd0;
end else begin
beat_cnt_mod_3 <= beat_cnt_mod_3 + 1'b1;
end
end
end
// Beat count per frame
always @(posedge clk) begin
if(reset) begin
beat_cnt_frame <= {BEATS_PER_FRAME_WIDTH{1'b0}};
end else begin
if(beat_cnt_frame == cfg_beats_per_frame) begin
beat_cnt_frame <= {BEATS_PER_FRAME_WIDTH{1'b0}};
end else begin
beat_cnt_frame <= beat_cnt_frame + 1'b1;
end
end
end
assign cur_sof = beat_cnt_frame == 0;
assign cur_eof = beat_cnt_frame == cfg_beats_per_frame;
// cfg_octets_per_frame must be a multiple of DATA_PATH_WIDTH'
// except for the following supported special cases
always @(*) begin
case(cfg_octets_per_frame)
8'd0:
begin
sof = {DATA_PATH_WIDTH{1'b1}};
eof = {DATA_PATH_WIDTH{1'b1}};
end
8'd1:
begin
sof = {DATA_PATH_WIDTH/2{2'b01}};
eof = {DATA_PATH_WIDTH/2{2'b10}};
end
8'd2:
begin
sof = sof_f_3[beat_cnt_mod_3];
eof = eof_f_3[beat_cnt_mod_3];
end
8'd5:
begin
sof = sof_f_6[beat_cnt_mod_3];
eof = eof_f_6[beat_cnt_mod_3];
end
default:
begin
sof = {{DATA_PATH_WIDTH-1{1'b0}}, cur_sof};
eof = {cur_eof, {DATA_PATH_WIDTH-1{1'b0}}};
end
endcase
end
// Beat count per multiframe
always @(posedge clk) begin
if(reset) begin
beat_cnt_mf <= 8'b0;
end else begin
if(beat_cnt_mf == cfg_beats_per_multiframe) begin
beat_cnt_mf <= 8'b0;
end else begin
beat_cnt_mf <= beat_cnt_mf + 1'b1;
end
end
end
assign cur_somf = beat_cnt_mf == 0;
assign cur_eomf = beat_cnt_mf == cfg_beats_per_multiframe;
// Only support F*K equals a multipe of DATA_PATH_WIDTH,
always @(*) begin
somf = {{DATA_PATH_WIDTH-1{1'b0}}, cur_somf};
eomf = {cur_eomf, {DATA_PATH_WIDTH-1{1'b0}}};
end
endmodule
adi_library/jesd204/jesd204_rx/jesd204_rx_header.v
+207
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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
`timescale 1ns/100ps
module jesd204_rx_header (
input clk,
input reset,
input sh_lock,
input [1:0] header,
input [1:0] cfg_header_mode, // 0 - CRC12 ; 1 - CRC3; 2 - FEC; 3 - CMD
input [4:0] cfg_rx_thresh_emb_err,
input [7:0] cfg_beats_per_multiframe,
output emb_lock,
output valid_eomb,
output valid_eoemb,
// Received header data qualified by valid_eomb
output [11:0] crc12,
output [2:0] crc3,
output [25:0] fec,
output [18:0] cmd,
output reg [7:0] sh_count = 'h0,
output [2:0] status_lane_emb_state,
output reg event_invalid_header,
output reg event_unexpected_eomb,
output reg event_unexpected_eoemb
);
localparam STATE_EMB_INIT = 3'b001;
localparam STATE_EMB_HUNT = 3'b010;
localparam STATE_EMB_LOCK = 3'b100;
localparam BIT_EMB_INIT = 0;
localparam BIT_EMB_HUNT = 1;
localparam BIT_EMB_LOCK = 2;
reg [2:0] state = STATE_EMB_INIT;
reg [2:0] next_state;
reg [31:0] sync_word = 'h0;
wire header_bit;
wire invalid_sequence;
wire invalid_eoemb;
wire invalid_eomb;
wire [6:0] cmd0;
wire [6:0] cmd1;
wire [18:0] cmd3;
wire eoemb;
wire eomb;
assign header_bit = header == 2'b01;
always @(posedge clk) begin
sync_word <= {sync_word[30:0],header_bit};
end
assign crc12 = {sync_word[31:29],sync_word[27:25],
sync_word[23:21],sync_word[19:17]};
assign crc3 = {sync_word[31:29]};
assign cmd0 = {sync_word[15:13],sync_word[11],
sync_word[7:5]};
assign cmd1 = {sync_word[27:25],
sync_word[19:17],
sync_word[11]};
assign cmd3 = {sync_word[31:29],sync_word[27:25],
sync_word[23:21],sync_word[19:17],
sync_word[15:13],sync_word[11],
sync_word[7:5]};
assign cmd = cfg_header_mode == 0 ? {12'b0,cmd0} :
cfg_header_mode == 1 ? {12'b0,cmd1} :
cfg_header_mode == 3 ? cmd3 : 'b0;
assign fec = {sync_word[31:10],sync_word[8:5]};
assign eomb = sync_word[4:0] == 5'b00001;
assign eoemb = sync_word[9] & eomb;
always @(posedge clk) begin
if (next_state[BIT_EMB_INIT] || sh_count == cfg_beats_per_multiframe) begin
sh_count <= 'h0;
end else begin
sh_count <= sh_count + 8'b1;
end
end
reg [1:0] emb_vcount = 'b0;
always @(posedge clk) begin
if (state[BIT_EMB_INIT]) begin
emb_vcount <= 'b0;
end else if (state[BIT_EMB_HUNT] && (sh_count == 0 && eoemb)) begin
emb_vcount <= emb_vcount + 'b1;
end
end
reg [4:0] emb_icount = 'b0;
always @(posedge clk) begin
if (state[BIT_EMB_INIT]) begin
emb_icount <= 'b0;
end else if (state[BIT_EMB_LOCK]) begin
if (sh_count == 0 && eoemb) begin
emb_icount <= 'b0;
end else if (invalid_eoemb || invalid_eomb) begin
emb_icount <= emb_icount + 5'b1;
end
end
end
always @(*) begin
next_state = state;
case (state)
STATE_EMB_INIT:
if (eoemb) begin
next_state = STATE_EMB_HUNT;
end
STATE_EMB_HUNT:
if (invalid_sequence) begin
next_state = STATE_EMB_INIT;
end else if (eoemb && emb_vcount == 2'd3) begin
next_state = STATE_EMB_LOCK;
end
STATE_EMB_LOCK:
if (emb_icount == cfg_rx_thresh_emb_err) begin
next_state = STATE_EMB_INIT;
end
endcase
if (sh_lock == 1'b0) next_state = STATE_EMB_INIT;
end
assign invalid_eoemb = (sh_count == 0 && ~eoemb);
assign invalid_eomb = (sh_count[4:0] == 0 && ~eomb);
assign valid_eomb = next_state[BIT_EMB_LOCK] && eomb;
assign valid_eoemb = next_state[BIT_EMB_LOCK] && eoemb;
assign invalid_sequence = (invalid_eoemb || invalid_eomb);
always @(posedge clk) begin
if (reset == 1'b1) begin
state <= STATE_EMB_INIT;
end else begin
state <= next_state;
end
end
assign emb_lock = next_state[BIT_EMB_LOCK];
// Status & error events
assign status_lane_emb_state = state;
always @(posedge clk) begin
event_invalid_header <= (~state[BIT_EMB_INIT]) && (header[0] == header[1]);
event_unexpected_eomb <= (~state[BIT_EMB_INIT]) && (sh_count[4:0] != 0 && eomb);
event_unexpected_eoemb <= (~state[BIT_EMB_INIT]) && invalid_eoemb;
end
endmodule
adi_library/jesd204/jesd204_rx/jesd204_rx_hw.tcl
+239
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@@ -0,0 +1,239 @@
#
# The ADI JESD204 Core is released under the following license, which is
# different than all other HDL cores in this repository.
#
# Please read this, and understand the freedoms and responsibilities you have
# by using this source code/core.
#
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
#
# This core is free software, you can use run, copy, study, change, ask
# questions about and improve this core. Distribution of source, or resulting
# binaries (including those inside an FPGA or ASIC) require you to release the
# source of the entire project (excluding the system libraries provide by the
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License version 2
# along with this source code, and binary. If not, see
# <http://www.gnu.org/licenses/>.
#
# Commercial licenses (with commercial support) of this JESD204 core are also
# available under terms different than the General Public License. (e.g. they
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
# core with any corresponding source code.) For these alternate terms you must
# purchase a license from Analog Devices Technology Licensing Office. Users
# interested in such a license should contact [email protected] for
# more information. This commercial license is sub-licensable (if you purchase
# chips from Analog Devices, incorporate them into your PCB level product, and
# purchase a JESD204 license, end users of your product will also have a
# license to use this core in a commercial setting without releasing their
# source code).
#
# In addition, we kindly ask you to acknowledge ADI in any program, application
# or publication in which you use this JESD204 HDL core. (You are not required
# to do so; it is up to your common sense to decide whether you want to comply
# with this request or not.) For general publications, we suggest referencing :
# “The design and implementation of the JESD204 HDL Core used in this project
# is copyright © 2016-2017, Analog Devices, Inc.”
#
package require qsys
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
ad_ip_create jesd204_rx "ADI JESD204 Receive" jesd204_rx_elaboration_callback
set_module_property INTERNAL true
# files
ad_ip_files jesd204_rx [list \
jesd204_rx.v \
align_mux.v \
elastic_buffer.v \
jesd204_ilas_monitor.v \
jesd204_lane_latency_monitor.v \
jesd204_rx_cgs.v \
jesd204_rx_ctrl.v \
jesd204_rx_lane.v \
jesd204_rx_frame_mark.v \
jesd204_rx_frame_align_monitor.v \
jesd204_rx_constr.sdc \
../jesd204_common/jesd204_eof_generator.v \
../jesd204_common/jesd204_lmfc.v \
../jesd204_common/jesd204_scrambler.v \
../jesd204_common/pipeline_stage.v \
]
# parameters
add_parameter NUM_LANES INTEGER 1
set_parameter_property NUM_LANES DISPLAY_NAME "Number of Lanes"
set_parameter_property NUM_LANES ALLOWED_RANGES 1:8
set_parameter_property NUM_LANES HDL_PARAMETER true
add_parameter NUM_LINKS INTEGER 1
set_parameter_property NUM_LINKS DISPLAY_NAME "Number of Links"
set_parameter_property NUM_LINKS ALLOWED_RANGES 1:8
set_parameter_property NUM_LINKS HDL_PARAMETER true
add_parameter NUM_INPUT_PIPELINE INTEGER 1
set_parameter_property NUM_INPUT_PIPELINE DISPLAY_NAME "Number of input pipeline stages"
set_parameter_property NUM_INPUT_PIPELINE ALLOWED_RANGES 1:3
set_parameter_property NUM_INPUT_PIPELINE HDL_PARAMETER true
#ad_ip_parameter PORT_ENABLE_RX_EOF BOOLEAN false false
#ad_ip_parameter PORT_ENABLE_LMFC_CLK BOOLEAN false false
#ad_ip_parameter PORT_ENABLE_LMFC_EDGE BOOLEAN false false
# clock
add_interface clock clock end
add_interface_port clock clk clk Input 1
# reset
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
add_interface_port reset reset reset Input 1
# SYSREF~ interface
add_interface sysref conduit end
set_interface_property sysref associatedClock clock
set_interface_property sysref associatedReset reset
add_interface_port sysref sysref export Input 1
# SYNC interface
add_interface sync conduit end
set_interface_property sync associatedClock clock
set_interface_property sync associatedReset reset
add_interface_port sync sync export Output NUM_LINKS
# config interface
add_interface config conduit end
set_interface_property config associatedClock clock
set_interface_property config associatedReset reset
add_interface_port config cfg_beats_per_multiframe beats_per_multiframe Input 8
add_interface_port config cfg_buffer_delay buffer_delay Input 8
add_interface_port config cfg_buffer_early_release buffer_early_release Input 1
add_interface_port config cfg_disable_char_replacement disable_char_replacement Input 1
add_interface_port config cfg_disable_scrambler disable_scrambler Input 1
add_interface_port config cfg_lanes_disable lanes_disable Input NUM_LANES
add_interface_port config cfg_links_disable links_disable Input NUM_LINKS
add_interface_port config cfg_lmfc_offset lmfc_offset Input 8
add_interface_port config cfg_octets_per_frame octets_per_frame Input 8
add_interface_port config cfg_sysref_disable sysref_disable Input 1
add_interface_port config cfg_sysref_oneshot sysref_oneshot Input 1
add_interface_port config cfg_frame_align_err_threshold frame_align_err_threshold Input 8
add_interface_port config ctrl_err_statistics_reset err_statistics_reset Input 1
add_interface_port config ctrl_err_statistics_mask err_statistics_mask Input 3
# status interface
add_interface status conduit end
set_interface_property status associatedClock clock
set_interface_property status associatedReset reset
add_interface_port status status_ctrl_state ctrl_state Output 2
add_interface_port status status_lane_cgs_state lane_cgs_state Output 2*NUM_LANES
add_interface_port status status_lane_ifs_ready lane_ifs_ready Output NUM_LANES
add_interface_port status status_lane_latency lane_latency Output 14*NUM_LANES
add_interface_port status status_err_statistics_cnt err_statistics_cnt Output 32*NUM_LANES
add_interface_port status status_lane_frame_align_err_cnt lane_frame_align_err_cnt Output 8*NUM_LANES
# event interface
add_interface event conduit end
set_interface_property event associatedClock clock
set_interface_property event associatedReset reset
add_interface_port event event_sysref_alignment_error sysref_alignment_error Output 1
add_interface_port event event_sysref_edge sysref_edge Output 1
# ilas_config interface
add_interface ilas_config conduit end
set_interface_property ilas_config associatedClock clock
set_interface_property ilas_config associatedReset reset
add_interface_port ilas_config ilas_config_addr addr Output NUM_LANES*2
add_interface_port ilas_config ilas_config_data data Output NUM_LANES*32
add_interface_port ilas_config ilas_config_valid valid Output NUM_LANES
# rx_eof interface
add_interface rx_eof conduit end
#set_interface_property rx_eof associatedClock clock
#set_interface_property rx_eof associatedReset reset
add_interface_port rx_eof rx_eof export Output 4
set_port_property rx_eof TERMINATION TRUE
# rx_sof interface
add_interface rx_sof conduit end
#set_interface_property rx_sof associatedClock clock
#set_interface_property rx_sof associatedReset reset
add_interface_port rx_sof rx_sof export Output 4
# lmfc_clk interface
add_interface lmfc_clk conduit end
#set_interface_property lmfc_clk associatedClock clock
#set_interface_property lmfc_clk associatedReset reset
add_interface_port lmfc_clk lmfc_clk export Output 1
set_port_property lmfc_clk TERMINATION TRUE
# lmfc_edge interface
add_interface lmfc_edge conduit end
#set_interface_property lmfc_edge associatedClock clock
#set_interface_property lmfc_edge associatedReset reset
add_interface_port lmfc_edge lmfc_edge export Output 1
set_port_property lmfc_edge TERMINATION TRUE
proc jesd204_rx_elaboration_callback {} {
set num_lanes [get_parameter_value "NUM_LANES"]
# rx_data interface
add_interface rx_data avalon_streaming source
set_interface_property rx_data associatedClock clock
add_interface_port rx_data rx_data data output [expr 32*$num_lanes]
add_interface_port rx_data rx_valid valid output 1
set_interface_property rx_data dataBitsPerSymbol [expr 32*$num_lanes]
# phy interfaces
for {set i 0 } {$i < $num_lanes} {incr i} {
add_interface rx_phy${i} conduit end
# set_interface_property rx_phy${i} associatedClock clock
# set_interface_property rx_phy${i} associatedReset reset
add_interface_port rx_phy${i} rx_phy${i}_data char Input 32
set_port_property rx_phy${i}_data fragment_list \
[format "phy_data(%d:%d)" [expr 32*$i+31] [expr 32*$i]]
add_interface_port rx_phy${i} rx_phy${i}_charisk charisk Input 4
set_port_property rx_phy${i}_charisk fragment_list \
[format "phy_charisk(%d:%d)" [expr 4*$i+3] [expr 4*$i]]
add_interface_port rx_phy${i} rx_phy${i}_disperr disperr Input 4
set_port_property rx_phy${i}_disperr fragment_list \
[format "phy_disperr(%d:%d)" [expr 4*$i+3] [expr 4*$i]]
add_interface_port rx_phy${i} rx_phy${i}_notintable notintable Input 4
set_port_property rx_phy${i}_notintable fragment_list \
[format "phy_notintable(%d:%d)" [expr 4*$i+3] [expr 4*$i]]
add_interface_port rx_phy${i} rx_phy${i}_patternalign_en patternalign_en Output 1
set_port_property rx_phy${i}_patternalign_en fragment_list "phy_en_char_align"
}
}
adi_library/jesd204/jesd204_rx/jesd204_rx_ip.log
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****** Vivado v2019.1.3 (64-bit)
**** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
**** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
source jesd204_rx_ip.tcl
# source ../../scripts/adi_env.tcl
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
## if [info exists ::env(ADI_HDL_DIR)] {
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
## }
## if [info exists ::env(ADI_GHDL_DIR)] {
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
## }
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
### variable auto_set_param_list
### variable auto_set_param_list_overwritable
### variable fpga_series_list
### variable fpga_family_list
### variable speed_grade_list
### variable dev_package_list
### variable xcvr_type_list
### variable fpga_voltage_list
### set auto_set_param_list { \
### DEV_PACKAGE \
### SPEED_GRADE \
### FPGA_FAMILY \
### FPGA_TECHNOLOGY }
### set auto_set_param_list_overwritable { \
### FPGA_VOLTAGE \
### XCVR_TYPE }
### set fpga_technology_list { \
### { Unknown 0 } \
### { 7series 1 } \
### { ultrascale 2 } \
### { ultrascale+ 3 }}
### set fpga_family_list { \
### { Unknown 0 } \
### { artix 1 } \
### { kintex 2 } \
### { virtex 3 } \
### { zynq 4 }}
### set speed_grade_list { \
### { Unknown 0 } \
### { -1 10 } \
### { -1L 11 } \
### { -1H 12 } \
### { -1HV 13 } \
### { -1LV 14 } \
### { -2 20 } \
### { -2L 21 } \
### { -2LV 22 } \
### { -3 30 }}
### set dev_package_list { \
### { Unknown 0 } \
### { rf 1 } \
### { fl 2 } \
### { ff 3 } \
### { fb 4 } \
### { hc 5 } \
### { fh 6 } \
### { cs 7 } \
### { cp 8 } \
### { ft 9 } \
### { fg 10 } \
### { sb 11 } \
### { rb 12 } \
### { rs 13 } \
### { cl 14 } \
### { sf 15 } \
### { ba 16 } \
### { fa 17 } \
### { fs 18 } \
### { fi 19 }}
### set xcvr_type_list { \
### { Unknown 0 } \
### { GTPE2_NOT_SUPPORTED 1 } \
### { GTXE2 2 } \
### { GTHE2_NOT_SUPPORTED 3 } \
### { GTZE2_NOT_SUPPORTED 4 } \
### { GTHE3 5 } \
### { GTYE3_NOT_SUPPORTED 6 } \
### { GTRE4_NOT_SUPPORTED 7 } \
### { GTHE4 8 } \
### { GTYE4 9 } \
### { GTME4_NOT_SUPPORTED 10}}
### set fpga_voltage_list {0 5000} ;
### proc adi_device_spec {cellpath param} {
###
### set list_pointer [string tolower $param]
### set list_pointer [append list_pointer "_list"]
###
### upvar 1 $list_pointer $list_pointer
###
### set ip [get_bd_cells $cellpath]
### set part [get_property PART [current_project]]
###
### switch -regexp -- $param {
### FPGA_TECHNOLOGY {
### switch -regexp -- $part {
### ^xc7 {set series_name 7series}
### ^xczu {set series_name ultrascale+}
### ^xc.u.p {set series_name ultrascale+}
### ^xc.u {set series_name ultrascale }
### default {
### puts "Undefined fpga technology for \"$part\"!"
### exit -1
### }
### }
### return "$series_name"
### }
### FPGA_FAMILY {
### set fpga_family [get_property FAMILY $part]
### foreach i $fpga_family_list {
### regexp ^[lindex $i 0] $fpga_family matched
### }
### return "$matched"
### }
### SPEED_GRADE {
### set speed_grade [get_property SPEED $part]
### return "$speed_grade"
### }
### DEV_PACKAGE {
### set dev_package [get_property PACKAGE $part]
### foreach i $dev_package_list {
### regexp ^[lindex $i 0] $dev_package matched
### }
### return "$matched"
### }
### XCVR_TYPE {
### set matched ""
### set dev_transcivers "none"
### foreach x [list_property $part] {
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
### }
### foreach i $xcvr_type_list {
### regexp ^[lindex $i 0] $dev_transcivers matched
### }
### if { $matched eq "" } {
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
### }
### return "$matched"
### }
### FPGA_VOLTAGE {
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
###
### return "$fpga_voltage"
### }
### default {
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
### }
### }
### }
## if {![info exists REQUIRED_VIVADO_VERSION]} {
## set REQUIRED_VIVADO_VERSION "2019.1"
## }
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
## set IGNORE_VERSION_CHECK 1
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
## set IGNORE_VERSION_CHECK 0
## }
## proc adi_ip_ttcl {ip_name ip_constr_files} {
##
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
## set_property -dict [list \
## type ttcl \
## ] $f
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
## }
## proc adi_ip_sim_ttcl {ip_name ip_files} {
##
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
## set f [ipx::add_file $ip_files $proj_filegroup]
## set_property -dict [list \
## type ttcl \
## ] $f
## ipx::reorder_files -front $ip_files $proj_filegroup
## }
## proc adi_ip_bd {ip_name ip_bd_files} {
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
## if {$proj_filegroup == {}} {
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
## }
##
## foreach file $ip_bd_files {
## set f [ipx::add_file $file $proj_filegroup]
## set_property -dict [list \
## type tclSource \
## ] $f
## }
## }
## proc adi_ip_infer_streaming_interfaces {ip_name} {
##
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
##
## }
## proc adi_ip_infer_mm_interfaces {ip_name} {
##
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
##
## }
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
## set_property ENABLEMENT_DEPENDENCY $dependency $port
## if {$driver_value != {}} {
## set_property DRIVER_VALUE $driver_value $port
## }
## }
## }
## proc adi_set_bus_dependency {bus prefix dependency} {
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
## adi_set_ports_dependency $prefix $dependency 0
## }
## proc adi_add_port_map {bus phys logic} {
## set map [ipx::add_port_map $phys $bus]
## set_property "PHYSICAL_NAME" $phys $map
## set_property "LOGICAL_NAME" $logic $map
## }
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
##
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
## set_property "BUS_TYPE_VLNV" $bus_type $bus
## set_property "INTERFACE_MODE" $mode $bus
##
## foreach port_map $port_maps {
## adi_add_port_map $bus {*}$port_map
## }
## }
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
## for {set i 0} {$i < $num} {incr i} {
## set bus_name [format "%s%d" $bus_name_prefix $i]
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
##
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
## set_property "BUS_TYPE_VLNV" $bus_type $bus
## set_property "INTERFACE_MODE" $mode $bus
##
## if {$dependency ne ""} {
## set bus_dependency [string map [list "{i}" $i] $dependency]
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
## }
##
## foreach port_map $port_maps {
## lassign $port_map phys logic width width_dep
## set map [ipx::add_port_map $phys $bus]
## set_property "PHYSICAL_NAME" $phys $map
## set_property "LOGICAL_NAME" $logic $map
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
## if {$width_dep ne ""} {
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
## set width_dep_r "(($width_dep) * $i)"
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
## }
## }
## }
## }
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
## set_property display_name $clock_inf_name $clock_inf
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
## set_property physical_name $clock_signal_name $clock_map
##
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
## set_property value $bus_inf_name $assoc_busif
##
## if { $reset_signal_name != "" } {
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
## set_property value $reset_signal_name $assoc_reset
##
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
## set_property display_name $reset_inf_name $reset_inf
## set_property interface_mode $reset_signal_mode $reset_inf
## set reset_map [ipx::add_port_map "RST" $reset_inf]
## set_property physical_name $reset_signal_name $reset_map
##
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
## set_property value "ACTIVE_LOW" $reset_polarity
## } else {
## set_property value "ACTIVE_HIGH" $reset_polarity
## }
## }
## }
## proc adi_ip_add_core_dependencies {vlnvs} {
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
## foreach vlnv $vlnvs {
## ipx::add_subcore $vlnv $file_group
## }
## }
## }
## proc adi_ip_create {ip_name} {
##
## global ad_hdl_dir
## global ad_ghdl_dir
## global REQUIRED_VIVADO_VERSION
## global IGNORE_VERSION_CHECK
##
## set VIVADO_VERSION [version -short]
## if {$IGNORE_VERSION_CHECK} {
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
## puts -nonewline "got $VIVADO_VERSION.\n"
## }
## } else {
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
## puts -nonewline "ERROR: vivado version mismatch; "
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
## puts -nonewline "got $VIVADO_VERSION.\n"
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
## exit 2
## }
## }
##
## create_project $ip_name . -force
##
## ## Load custom message severity definitions
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
##
## set lib_dirs $ad_hdl_dir/library
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
## lappend lib_dirs $ad_ghdl_dir/library
## }
##
## set_property ip_repo_paths $lib_dirs [current_fileset]
## update_ip_catalog
## }
## proc adi_ip_files {ip_name ip_files} {
## set proj_fileset [get_filesets sources_1]
## foreach m_file $ip_files {
## if {[file extension $m_file] eq ".xdc"} {
## add_files -norecurse -fileset constrs_1 $m_file
## } else {
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
## }
## }
## set_property "top" "$ip_name" $proj_fileset
## }
## proc adi_ip_properties_lite {ip_name} {
##
## global ad_hdl_dir
##
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
##
## set_property name $ip_name [ipx::current_core]
##
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
## set_property company_url {http://www.analog.com} [ipx::current_core]
##
## set i_families ""
## foreach i_part [get_parts] {
## lappend i_families [get_property FAMILY $i_part]
## }
## set i_families [lsort -unique $i_families]
## set s_families [get_property supported_families [ipx::current_core]]
## foreach i_family $i_families {
## set s_families "$s_families $i_family Production"
## set s_families "$s_families $i_family Beta"
## }
## set_property supported_families $s_families [ipx::current_core]
##
## ipx::save_core [ipx::current_core]
##
## ipx::remove_all_bus_interface [ipx::current_core]
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
## foreach map $memory_maps {
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
## }
##
## ipx::update_checksums [ipx::current_core]
## ipx::save_core [ipx::current_core]
## }
## proc adi_ip_properties {ip_name} {
##
## adi_ip_properties_lite $ip_name
##
## ipx::infer_bus_interface {\
## s_axi_awvalid \
## s_axi_awaddr \
## s_axi_awprot \
## s_axi_awready \
## s_axi_wvalid \
## s_axi_wdata \
## s_axi_wstrb \
## s_axi_wready \
## s_axi_bvalid \
## s_axi_bresp \
##
## s_axi_bready \
## s_axi_arvalid \
## s_axi_araddr \
## s_axi_arprot \
## s_axi_arready \
## s_axi_rvalid \
## s_axi_rdata \
## s_axi_rresp \
## s_axi_rready} \
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
##
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
##
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
##
## if {$raddr_width != $waddr_width} {
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
## set range 65536
## } else {
## if {$raddr_width >= 16} {
## set range 65536
## } else {
## set range [expr 1 << $raddr_width]
## }
## }
##
## ipx::add_memory_map {s_axi} [ipx::current_core]
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
## set_property range $range [ipx::get_address_blocks axi_lite \
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
## ipx::save_core
## }
## proc adi_init_bd_tcl {} {
##
## global auto_set_param_list
## global auto_set_param_list_overwritable
## set cc [ipx::current_core]
##
## if { [file exists bd] } {
## file delete -force bd
## }
## file mkdir bd
##
## set bd_tcl [open "bd/bd.tcl" w]
##
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
## puts $bd_tcl "proc init {cellpath otherInfo} {"
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
## puts $bd_tcl ""
## set auto_set_param ""
## foreach i $auto_set_param_list {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
## append auto_set_param " $i \\\n"
## }
## }
## if { $auto_set_param ne "" } {
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
## puts $bd_tcl $auto_set_param
## }
##
## set auto_set_overwritable_param ""
## foreach i $auto_set_param_list_overwritable {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
## append auto_set_overwritable_param " $i \\\n"
## }
## }
## if { $auto_set_overwritable_param ne "" } {
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
## puts $bd_tcl $auto_set_overwritable_param
## }
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
## puts $bd_tcl "}"
## puts $bd_tcl ""
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
## puts $bd_tcl ""
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
## puts $bd_tcl ""
## puts $bd_tcl " set parent_dir \"../\""
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
## puts $bd_tcl " break"
## puts $bd_tcl " }"
## puts $bd_tcl " append parent_dir \"../\""
## puts $bd_tcl " }"
## puts $bd_tcl ""
## puts $bd_tcl " # Find predefindes auto assignable parameters"
## puts $bd_tcl " foreach i \$auto_set_param_list {"
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
## puts $bd_tcl " }"
## puts $bd_tcl " }"
## puts $bd_tcl ""
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
## puts $bd_tcl " }"
## puts $bd_tcl " }"
## puts $bd_tcl "}"
## puts $bd_tcl ""
## close $bd_tcl
##
## set proj_fileset [get_filesets sources_1]
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
##
## set local_mk [open "temporary_case_dependencies.mk" w]
## seek $local_mk 0 start
## puts $local_mk "CLEAN_TARGET += bd"
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
## close $local_mk
## }
## proc adi_add_auto_fpga_spec_params {} {
##
## global auto_set_param_list
## global auto_set_param_list_overwritable
## set cc [ipx::current_core]
##
## foreach i $auto_set_param_list {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
## adi_add_device_spec_param $i
## }
## }
## foreach i $auto_set_param_list_overwritable {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
## adi_add_device_spec_param $i
## }
## }
## }
## proc adi_add_device_spec_param {ip_param} {
##
## set cc [ipx::current_core]
##
## set list_pointer [string tolower $ip_param]
## set list_pointer [append list_pointer "_list"]
##
## global $list_pointer
##
## # set j 1D list from the original list
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
##
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
## set_property -dict [list \
## "value_validation_type" "range_long" \
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
## [ipx::get_user_parameters $ip_param -of_objects $cc]
## } else {
## set_property -dict [list \
## "value_validation_type" "pairs" \
## "value_validation_pairs" $j ] \
## [ipx::get_user_parameters $ip_param -of_objects $cc]
## }
##
## # FPGA info grup
## set info_group_name "FPGA info"
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
## if { [string trim $info_group] eq "" } {
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
## -parent $page0 -display_name $info_group_name]
## }
##
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
## set_property -dict [list "widget" "comboBox" ] $p
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
## }
## proc adi_if_define {name} {
##
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
## ipx::create_bus_definition analog.com interface $name 1.0
##
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
##
## ipx::save_abstraction_definition [ipx::current_busabs]
## ipx::save_bus_definition [ipx::current_busdef]
## }
## proc adi_if_ports {dir width name {type none}} {
##
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
## set_property master_presence required $m_intf
## set_property slave_presence required $m_intf
## set_property master_width $width $m_intf
## set_property slave_width $width $m_intf
##
## set m_dir "in"
## set s_dir "out"
## if {$dir eq "output"} {
## set m_dir "out"
## set s_dir "in"
## }
##
## set_property master_direction $m_dir $m_intf
## set_property slave_direction $s_dir $m_intf
##
## if {$type ne "none"} {
## set_property is_${type} true $m_intf
## }
##
## ipx::save_bus_definition [ipx::current_busdef]
## ipx::save_abstraction_definition [ipx::current_busabs]
## }
## proc adi_if_infer_bus {if_name mode name maps} {
##
## ipx::add_bus_interface $name [ipx::current_core]
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
## set_property interface_mode $mode $m_bus_if
##
## foreach map $maps {
## set m_maps [regexp -all -inline {\S+} $map]
## lassign $m_maps p_name p_map
## ipx::add_port_map $p_name $m_bus_if
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
## }
## }
# adi_ip_create jesd204_rx
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
## set_msg_config -id {BD 41-1343} -new_severity WARNING
## set_msg_config -id {BD 41-1306} -new_severity WARNING
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
## set_msg_config -id {Synth 8-3331} -new_severity INFO
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx'.)
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
# adi_ip_files jesd204_rx [list \
# "jesd204_rx_lane.v" \
# "jesd204_rx_lane_64b.v" \
# "jesd204_rx_header.v" \
# "jesd204_rx_cgs.v" \
# "jesd204_rx_ctrl.v" \
# "jesd204_rx_ctrl_64b.v" \
# "elastic_buffer.v" \
# "error_monitor.v" \
# "jesd204_ilas_monitor.v" \
# "align_mux.v" \
# "jesd204_lane_latency_monitor.v" \
# "jesd204_rx_frame_mark.v" \
# "jesd204_rx_frame_align_monitor.v" \
# "jesd204_rx_constr.ttcl" \
# "jesd204_rx.v" \
# ]
# adi_ip_properties_lite jesd204_rx
WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl' ignored by IP packager.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_data_r' has a dependency on the module local parameter or undefined parameter 'DW'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_header_r' has a dependency on the module local parameter or undefined parameter 'HW'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_charisk_r' has a dependency on the module local parameter or undefined parameter 'CW'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_notintable_r' has a dependency on the module local parameter or undefined parameter 'CW'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_disperr_r' has a dependency on the module local parameter or undefined parameter 'CW'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'rx_data_s' has a dependency on the module local parameter or undefined parameter 'DW'.
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'ilas_config' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'phy' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave.
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'phy_block' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'phy_char_align' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'rx' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
WARNING: [IP_Flow 19-5464] No port map found for required logical port err_statistics_reset on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave.
WARNING: [IP_Flow 19-5464] No port map found for required logical port err_statistics_mask on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'cfg' of definition 'analog.com:interface:jesd204_rx_cfg:1.0' (from User Repositories).
INFO: [IP_Flow 19-5107] Inferred bus interface 'event_unexpected_lane_error' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
INFO: [IP_Flow 19-5107] Inferred bus interface 'status_ctrl' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
INFO: [IP_Flow 19-5107] Inferred bus interface 'status_lane_cgs' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
INFO: [IP_Flow 19-5107] Inferred bus interface 'status_lane_emb' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
WARNING: [IP_Flow 19-5150] The Range '((8 * NUM_LANES) - 1):0' is present in all ports of the interface 'status_err_cnt'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
WARNING: [IP_Flow 19-5463] No port map found for required logical port lane_frame_align on bus interface abstraction jesd204_rx_status_rtl for interface type master.
WARNING: [IP_Flow 19-5463] No port map found for required logical port lane_latency_ready on bus interface abstraction jesd204_rx_status_rtl for interface type master.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'status' of definition 'analog.com:interface:jesd204_rx_status:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
INFO: [IP_Flow 19-5107] Inferred bus interface 'event' of definition 'analog.com:interface:jesd204_tx_event:1.0' (from User Repositories).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_err_statistics_reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'lmfc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-818] Not transferring value dependency attribute "((spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) ? 8 : 4)" into user parameter "DATA_PATH_WIDTH".
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ilas_config_data' and definition port 'DATA'.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'.
WARNING: [IP_Flow 19-1965] Bus Interface 'ilas_config': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'.
WARNING: [IP_Flow 19-1965] Bus Interface 'phy': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'phy_block': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'phy_block': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'phy_en_char_align' and definition port 'EN'.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'.
WARNING: [IP_Flow 19-1965] Bus Interface 'phy_char_align': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'.
WARNING: [IP_Flow 19-1965] Bus Interface 'rx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_reset" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_mask" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_ctrl_state' and definition port 'ctrl_state'.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_lane_cgs_state' and definition port 'lane_cgs_state'.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_lane_emb_state' and definition port 'lane_emb_state'.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_lane_ifs_ready' and definition port 'lane_ifs_ready'.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_lane_latency' and definition port 'lane_latency'.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_err_statistics_cnt' and definition port 'err_statistics_cnt'.
WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "lane_frame_align" of the bus abstraction "analog.com:interface:jesd204_rx_status_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "lane_latency_ready" of the bus abstraction "analog.com:interface:jesd204_rx_status_rtl:1.0" is missing.
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
WARNING: [IP_Flow 19-3153] Bus Interface 'lmfc_clk': ASSOCIATED_BUSIF bus parameter is missing.
WARNING: [IP_Flow 19-4751] Bus Interface 'lmfc_clk': FREQ_HZ bus parameter is missing for output clock interface.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
# adi_ip_ttcl jesd204_rx "jesd204_rx_constr.ttcl"
# adi_ip_add_core_dependencies { \
# analog.com:user:jesd204_common:1.0 \
# }
# set_property display_name "ADI JESD204 Receive" [ipx::current_core]
# set_property description "ADI JESD204 Receive" [ipx::current_core]
# adi_add_multi_bus 16 "rx_phy" "slave" \
# "xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0" \
# "xilinx.com:display_jesd204:jesd204_rx_bus:1.0" \
# [list \
# { "phy_data" "rxdata" 32 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')) * 8)"} \
# { "phy_charisk" "rxcharisk" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \
# { "phy_disperr" "rxdisperr" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \
# { "phy_notintable" "rxnotintable" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \
# { "phy_header" "rxheader" 2} \
# { "phy_block_sync" "rxblock_sync" 1} \
# ] \
# "(spirit:decode(id('MODELPARAM_VALUE.NUM_LANES')) > {i})"
# adi_add_bus "rx_cfg" "slave" \
# "analog.com:interface:jesd204_rx_cfg_rtl:1.0" \
# "analog.com:interface:jesd204_rx_cfg:1.0" \
# { \
# { "cfg_lanes_disable" "lanes_disable" } \
# { "cfg_links_disable" "links_disable" } \
# { "cfg_beats_per_multiframe" "beats_per_multiframe" } \
# { "cfg_octets_per_frame" "octets_per_frame" } \
# { "cfg_lmfc_offset" "lmfc_offset" } \
# { "cfg_sysref_oneshot" "sysref_oneshot" } \
# { "cfg_sysref_disable" "sysref_disable" } \
# { "cfg_buffer_delay" "buffer_delay" } \
# { "cfg_buffer_early_release" "buffer_early_release" } \
# { "cfg_disable_char_replacement" "disable_char_replacement" } \
# { "ctrl_err_statistics_reset" "err_statistics_reset" } \
# { "ctrl_err_statistics_mask" "err_statistics_mask" } \
# { "cfg_disable_scrambler" "disable_scrambler" } \
# { "cfg_frame_align_err_threshold" "frame_align_err_threshold" } \
# }
# adi_add_bus "rx_status" "master" \
# "analog.com:interface:jesd204_rx_status_rtl:1.0" \
# "analog.com:interface:jesd204_rx_status:1.0" \
# { \
# { "status_ctrl_state" "ctrl_state" } \
# { "status_lane_cgs_state" "lane_cgs_state" } \
# { "status_lane_emb_state" "lane_emb_state" } \
# { "status_err_statistics_cnt" "err_statistics_cnt" } \
# { "status_lane_ifs_ready" "lane_ifs_ready" } \
# { "status_lane_latency" "lane_latency" } \
# { "status_lane_frame_align_err_cnt" "lane_frame_align_err_cnt" } \
# }
# adi_add_bus "rx_ilas_config" "master" \
# "analog.com:interface:jesd204_rx_ilas_config_rtl:1.0" \
# "analog.com:interface:jesd204_rx_ilas_config:1.0" \
# { \
# { "ilas_config_valid" "valid" } \
# { "ilas_config_addr" "addr" } \
# { "ilas_config_data" "data" } \
# }
# adi_add_bus "rx_event" "master" \
# "analog.com:interface:jesd204_rx_event_rtl:1.0" \
# "analog.com:interface:jesd204_rx_event:1.0" \
# { \
# { "event_sysref_alignment_error" "sysref_alignment_error" } \
# { "event_sysref_edge" "sysref_edge" } \
# { "event_frame_alignment_error" "frame_alignment_error" } \
# { "event_unexpected_lane_state_error" "unexpected_lane_state_error" } \
# }
# adi_add_bus_clock "clk" "rx_cfg:rx_ilas_config:rx_event:rx_status:rx_data" "reset"
# adi_set_bus_dependency "rx_ilas_config" "rx_ilas_config" \
# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
# adi_set_ports_dependency "sync" \
# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
# adi_set_ports_dependency "phy_en_char_align" \
# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
# set cc [ipx::current_core]
# set_property -dict [list \
# driver_value 0 \
# ] [ipx::get_ports phy_header -of_objects $cc]
# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
# set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
# ipgui::move_param -component $cc -order 0 $p -parent $page0
# set_property -dict [list \
# "display_name" "Link Layer mode" \
# "tooltip" "Link Layer mode" \
# "widget" "comboBox" \
# ] $p
# set_property -dict [list \
# value_validation_type pairs \
# value_validation_pairs {64B66B 2 8B10B 1} \
# ] [ipx::get_user_parameters $p -of_objects $cc]
# set param [ipx::get_user_parameters DATA_PATH_WIDTH -of_objects $cc]
# set_property -dict [list \
# enablement_value false \
# value_tcl_expr {expr $LINK_MODE*4} \
# ] $param
# set param [ipx::add_user_parameter SYSREF_IOB $cc]
# set_property -dict {value_resolve_type user value_format bool value true} $param
# set param [ipgui::add_param -name {SYSREF_IOB} -component $cc -parent $page0]
# set_property -dict [list \
# display_name {Place SYSREF in IOB} \
# widget {checkBox} \
# show_label true \
# ] $param
# ipx::create_xgui_files [ipx::current_core]
# ipx::save_core [ipx::current_core]
INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:25:18 2021...
adi_library/jesd204/jesd204_rx/jesd204_rx_ip.tcl
+203
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@@ -0,0 +1,203 @@
#
# The ADI JESD204 Core is released under the following license, which is
# different than all other HDL cores in this repository.
#
# Please read this, and understand the freedoms and responsibilities you have
# by using this source code/core.
#
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
#
# This core is free software, you can use run, copy, study, change, ask
# questions about and improve this core. Distribution of source, or resulting
# binaries (including those inside an FPGA or ASIC) require you to release the
# source of the entire project (excluding the system libraries provide by the
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License version 2
# along with this source code, and binary. If not, see
# <http://www.gnu.org/licenses/>.
#
# Commercial licenses (with commercial support) of this JESD204 core are also
# available under terms different than the General Public License. (e.g. they
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
# core with any corresponding source code.) For these alternate terms you must
# purchase a license from Analog Devices Technology Licensing Office. Users
# interested in such a license should contact [email protected] for
# more information. This commercial license is sub-licensable (if you purchase
# chips from Analog Devices, incorporate them into your PCB level product, and
# purchase a JESD204 license, end users of your product will also have a
# license to use this core in a commercial setting without releasing their
# source code).
#
# In addition, we kindly ask you to acknowledge ADI in any program, application
# or publication in which you use this JESD204 HDL core. (You are not required
# to do so; it is up to your common sense to decide whether you want to comply
# with this request or not.) For general publications, we suggest referencing :
# “The design and implementation of the JESD204 HDL Core used in this project
# is copyright © 2016-2017, Analog Devices, Inc.”
#
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create jesd204_rx
adi_ip_files jesd204_rx [list \
"jesd204_rx_lane.v" \
"jesd204_rx_lane_64b.v" \
"jesd204_rx_header.v" \
"jesd204_rx_cgs.v" \
"jesd204_rx_ctrl.v" \
"jesd204_rx_ctrl_64b.v" \
"elastic_buffer.v" \
"error_monitor.v" \
"jesd204_ilas_monitor.v" \
"align_mux.v" \
"jesd204_lane_latency_monitor.v" \
"jesd204_rx_frame_mark.v" \
"jesd204_rx_frame_align_monitor.v" \
"jesd204_rx_constr.ttcl" \
"jesd204_rx.v" \
]
adi_ip_properties_lite jesd204_rx
adi_ip_ttcl jesd204_rx "jesd204_rx_constr.ttcl"
adi_ip_add_core_dependencies { \
analog.com:user:jesd204_common:1.0 \
}
set_property display_name "ADI JESD204 Receive" [ipx::current_core]
set_property description "ADI JESD204 Receive" [ipx::current_core]
#adi_add_bus "rx_data" "master" \
# "xilinx.com:interface:axis_rtl:1.0" \
# "xilinx.com:interface:axis:1.0" \
# { \
# { "rx_valid" "TVALID" } \
# { "rx_data" "TDATA" } \
# }
adi_add_multi_bus 16 "rx_phy" "slave" \
"xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0" \
"xilinx.com:display_jesd204:jesd204_rx_bus:1.0" \
[list \
{ "phy_data" "rxdata" 32 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')) * 8)"} \
{ "phy_charisk" "rxcharisk" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \
{ "phy_disperr" "rxdisperr" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \
{ "phy_notintable" "rxnotintable" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \
{ "phy_header" "rxheader" 2} \
{ "phy_block_sync" "rxblock_sync" 1} \
] \
"(spirit:decode(id('MODELPARAM_VALUE.NUM_LANES')) > {i})"
adi_add_bus "rx_cfg" "slave" \
"analog.com:interface:jesd204_rx_cfg_rtl:1.0" \
"analog.com:interface:jesd204_rx_cfg:1.0" \
{ \
{ "cfg_lanes_disable" "lanes_disable" } \
{ "cfg_links_disable" "links_disable" } \
{ "cfg_beats_per_multiframe" "beats_per_multiframe" } \
{ "cfg_octets_per_frame" "octets_per_frame" } \
{ "cfg_lmfc_offset" "lmfc_offset" } \
{ "cfg_sysref_oneshot" "sysref_oneshot" } \
{ "cfg_sysref_disable" "sysref_disable" } \
{ "cfg_buffer_delay" "buffer_delay" } \
{ "cfg_buffer_early_release" "buffer_early_release" } \
{ "cfg_disable_char_replacement" "disable_char_replacement" } \
{ "ctrl_err_statistics_reset" "err_statistics_reset" } \
{ "ctrl_err_statistics_mask" "err_statistics_mask" } \
{ "cfg_disable_scrambler" "disable_scrambler" } \
{ "cfg_frame_align_err_threshold" "frame_align_err_threshold" } \
}
adi_add_bus "rx_status" "master" \
"analog.com:interface:jesd204_rx_status_rtl:1.0" \
"analog.com:interface:jesd204_rx_status:1.0" \
{ \
{ "status_ctrl_state" "ctrl_state" } \
{ "status_lane_cgs_state" "lane_cgs_state" } \
{ "status_lane_emb_state" "lane_emb_state" } \
{ "status_err_statistics_cnt" "err_statistics_cnt" } \
{ "status_lane_ifs_ready" "lane_ifs_ready" } \
{ "status_lane_latency" "lane_latency" } \
{ "status_lane_frame_align_err_cnt" "lane_frame_align_err_cnt" } \
}
adi_add_bus "rx_ilas_config" "master" \
"analog.com:interface:jesd204_rx_ilas_config_rtl:1.0" \
"analog.com:interface:jesd204_rx_ilas_config:1.0" \
{ \
{ "ilas_config_valid" "valid" } \
{ "ilas_config_addr" "addr" } \
{ "ilas_config_data" "data" } \
}
adi_add_bus "rx_event" "master" \
"analog.com:interface:jesd204_rx_event_rtl:1.0" \
"analog.com:interface:jesd204_rx_event:1.0" \
{ \
{ "event_sysref_alignment_error" "sysref_alignment_error" } \
{ "event_sysref_edge" "sysref_edge" } \
{ "event_frame_alignment_error" "frame_alignment_error" } \
{ "event_unexpected_lane_state_error" "unexpected_lane_state_error" } \
}
adi_add_bus_clock "clk" "rx_cfg:rx_ilas_config:rx_event:rx_status:rx_data" "reset"
adi_set_bus_dependency "rx_ilas_config" "rx_ilas_config" \
"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
adi_set_ports_dependency "sync" \
"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
adi_set_ports_dependency "phy_en_char_align" \
"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
set cc [ipx::current_core]
set_property -dict [list \
driver_value 0 \
] [ipx::get_ports phy_header -of_objects $cc]
# Arrange GUI page layout
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
# Link layer mode
set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
ipgui::move_param -component $cc -order 0 $p -parent $page0
set_property -dict [list \
"display_name" "Link Layer mode" \
"tooltip" "Link Layer mode" \
"widget" "comboBox" \
] $p
set_property -dict [list \
value_validation_type pairs \
value_validation_pairs {64B66B 2 8B10B 1} \
] [ipx::get_user_parameters $p -of_objects $cc]
# Data width selection
set param [ipx::get_user_parameters DATA_PATH_WIDTH -of_objects $cc]
set_property -dict [list \
enablement_value false \
value_tcl_expr {expr $LINK_MODE*4} \
] $param
set param [ipx::add_user_parameter SYSREF_IOB $cc]
set_property -dict {value_resolve_type user value_format bool value true} $param
set param [ipgui::add_param -name {SYSREF_IOB} -component $cc -parent $page0]
set_property -dict [list \
display_name {Place SYSREF in IOB} \
widget {checkBox} \
show_label true \
] $param
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/jesd204/jesd204_rx/jesd204_rx_lane.v
+333
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@@ -0,0 +1,333 @@
//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
`timescale 1ns/100ps
module jesd204_rx_lane #(
parameter DATA_PATH_WIDTH = 4,
parameter CHAR_INFO_REGISTERED = 0,
parameter ALIGN_MUX_REGISTERED = 0,
parameter SCRAMBLER_REGISTERED = 0,
parameter ELASTIC_BUFFER_SIZE = 256,
parameter ENABLE_FRAME_ALIGN_CHECK = 0
) (
input clk,
input reset,
input [DATA_PATH_WIDTH*8-1:0] phy_data,
input [DATA_PATH_WIDTH-1:0] phy_charisk,
input [DATA_PATH_WIDTH-1:0] phy_notintable,
input [DATA_PATH_WIDTH-1:0] phy_disperr,
input cgs_reset,
output cgs_ready,
input ifs_reset,
output [DATA_PATH_WIDTH*8-1:0] rx_data,
output buffer_ready_n,
input buffer_release_n,
input [7:0] cfg_beats_per_multiframe,
input [7:0] cfg_octets_per_frame,
input cfg_disable_scrambler,
output ilas_config_valid,
output [1:0] ilas_config_addr,
output [DATA_PATH_WIDTH*8-1:0] ilas_config_data,
input err_statistics_reset,
input [2:0]ctrl_err_statistics_mask,
output reg [31:0] status_err_statistics_cnt,
output [1:0] status_cgs_state,
output status_ifs_ready,
output [1:0] status_frame_align,
output [7:0] status_frame_align_err_cnt
);
localparam MAX_DATA_PATH_WIDTH = 8;
wire [7:0] char[0:DATA_PATH_WIDTH-1];
wire [DATA_PATH_WIDTH-1:0] char_is_valid;
reg [DATA_PATH_WIDTH-1:0] char_is_cgs = 1'b0; // K28.5 /K/
reg [DATA_PATH_WIDTH-1:0] char_is_error = 1'b0;
reg [DATA_PATH_WIDTH-1:0] charisk28 = 4'b0000;
wire cgs_beat_is_cgs = &char_is_cgs;
wire cgs_beat_has_error = |char_is_error;
reg ifs_ready = 1'b0;
reg [1:0] frame_align = 'h00;
wire [DATA_PATH_WIDTH*8-1:0] phy_data_s;
wire [DATA_PATH_WIDTH-1:0] charisk28_aligned_s;
wire [DATA_PATH_WIDTH*8-1:0] data_aligned_s;
wire [DATA_PATH_WIDTH-1:0] charisk28_aligned;
wire [DATA_PATH_WIDTH*8-1:0] data_aligned;
wire [DATA_PATH_WIDTH*8-1:0] data_scrambled_s;
wire [DATA_PATH_WIDTH*8-1:0] data_scrambled;
reg [DATA_PATH_WIDTH-1:0] unexpected_char;
reg [DATA_PATH_WIDTH-1:0] phy_char_err;
wire ilas_monitor_reset_s;
wire ilas_monitor_reset;
wire buffer_ready_n_s;
assign status_ifs_ready = ifs_ready;
assign status_frame_align = frame_align;
genvar i;
generate
for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_char
assign char[i] = phy_data[i*8+7:i*8];
assign char_is_valid[i] = ~(phy_notintable[i] | phy_disperr[i]);
always @(*) begin
char_is_error[i] = ~char_is_valid[i];
char_is_cgs[i] = 1'b0;
charisk28[i] = 1'b0;
unexpected_char[i] = 1'b0;
if (phy_charisk[i] == 1'b1 && char_is_valid[i] == 1'b1) begin
if (char[i][4:0] == 'd28) begin
charisk28[i] = 1'b1;
if (char[i][7:5] == 'd5) begin
char_is_cgs[i] = 1'b1;
end
end else begin
unexpected_char[i] = 1'b1;
end
end
end
end
endgenerate
always @(posedge clk) begin
if (cgs_ready == 1'b1) begin
/*
* Set the bit in phy_char_err if at least one of the monitored error
* conditions has occured.
*/
phy_char_err <= (~{DATA_PATH_WIDTH{ctrl_err_statistics_mask[0]}} & phy_disperr) |
(~{DATA_PATH_WIDTH{ctrl_err_statistics_mask[1]}} & phy_notintable) |
(~{DATA_PATH_WIDTH{ctrl_err_statistics_mask[2]}} & unexpected_char);
end else begin
phy_char_err <= {DATA_PATH_WIDTH{1'b0}};
end
end
function [7:0] num_set_bits;
input [DATA_PATH_WIDTH-1:0] x;
integer j;
begin
num_set_bits = 0;
for (j = 0; j < DATA_PATH_WIDTH; j = j + 1) begin
num_set_bits = num_set_bits + x[j];
end
end
endfunction
always @(posedge clk) begin
if (reset == 1'b1 || err_statistics_reset == 1'b1) begin
status_err_statistics_cnt <= 32'h0;
end else if (status_err_statistics_cnt[31:5] != 27'h7ffffff) begin
status_err_statistics_cnt <= status_err_statistics_cnt + num_set_bits(phy_char_err);
end
end
always @(posedge clk) begin
if (ifs_reset == 1'b1) begin
ifs_ready <= 1'b0;
end else if (cgs_beat_is_cgs == 1'b0 && cgs_beat_has_error == 1'b0) begin
ifs_ready <= 1'b1;
end
end
always @(posedge clk) begin
if (ifs_ready == 1'b0) begin
if (char_is_cgs[0] == 1'b0) begin
frame_align <= 'h0;
end else if (char_is_cgs[1] == 1'b0) begin
frame_align <= 'h1;
end else if (char_is_cgs[2] == 1'b0) begin
frame_align <= 'h2;
end else begin
frame_align <= 'h3;
end
end
end
pipeline_stage #(
.WIDTH(DATA_PATH_WIDTH*8),
.REGISTERED(CHAR_INFO_REGISTERED)
) i_pipeline_stage0 (
.clk(clk),
.in(phy_data),
.out(phy_data_s)
);
align_mux i_align_mux (
.clk(clk),
.align(frame_align),
.in_data(phy_data_s),
.out_data(data_aligned_s),
.in_charisk(charisk28),
.out_charisk(charisk28_aligned_s)
);
assign ilas_monitor_reset_s = ~ifs_ready;
pipeline_stage #(
.WIDTH(1 + DATA_PATH_WIDTH * (8 + 1)),
.REGISTERED(ALIGN_MUX_REGISTERED)
) i_pipeline_stage1 (
.clk(clk),
.in({
ilas_monitor_reset_s,
data_aligned_s,
charisk28_aligned_s
}),
.out({
ilas_monitor_reset,
data_aligned,
charisk28_aligned
})
);
generate
if(ENABLE_FRAME_ALIGN_CHECK) begin : gen_frame_align_monitor
jesd204_rx_frame_align_monitor #(
.DATA_PATH_WIDTH (DATA_PATH_WIDTH)
) i_align_monitor (
.clk (clk),
.reset (buffer_ready_n_s),
.cfg_beats_per_multiframe (cfg_beats_per_multiframe),
.cfg_octets_per_frame (cfg_octets_per_frame),
.cfg_disable_scrambler (cfg_disable_scrambler),
.charisk28 (charisk28_aligned),
.data (data_aligned),
.align_err_cnt (status_frame_align_err_cnt)
);
end else begin : gen_no_frame_align_monitor
assign status_frame_align_err_cnt = 32'd0;
end
endgenerate
jesd204_scrambler #(
.WIDTH(DATA_PATH_WIDTH*8),
.DESCRAMBLE(1)
) i_descrambler (
.clk(clk),
.reset(buffer_ready_n_s),
.enable(~cfg_disable_scrambler),
.data_in(data_aligned),
.data_out(data_scrambled_s)
);
pipeline_stage #(
.WIDTH(1 + DATA_PATH_WIDTH * 8),
.REGISTERED(SCRAMBLER_REGISTERED)
) i_pipeline_stage2 (
.clk(clk),
.in({
buffer_ready_n_s,
data_scrambled_s
}),
.out({
buffer_ready_n,
data_scrambled
})
);
elastic_buffer #(
.WIDTH(DATA_PATH_WIDTH*8),
.SIZE(ELASTIC_BUFFER_SIZE)
) i_elastic_buffer (
.clk(clk),
.reset(reset),
.wr_data(data_scrambled),
.rd_data(rx_data),
.ready_n(buffer_ready_n),
.do_release_n(buffer_release_n)
);
jesd204_ilas_monitor #(
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
) i_ilas_monitor (
.clk(clk),
.reset(ilas_monitor_reset),
.data(data_aligned),
.charisk28(charisk28_aligned),
.data_ready_n(buffer_ready_n_s),
.ilas_config_valid(ilas_config_valid),
.ilas_config_addr(ilas_config_addr),
.ilas_config_data(ilas_config_data)
);
jesd204_rx_cgs #(
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
) i_cgs (
.clk(clk),
.reset(cgs_reset),
.char_is_cgs(char_is_cgs),
.char_is_error(char_is_error),
.ready(cgs_ready),
.status_state(status_cgs_state)
);
endmodule
adi_library/jesd204/jesd204_rx/jesd204_rx_lane_64b.v
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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
`timescale 1ns/100ps
module jesd204_rx_lane_64b #(
parameter ELASTIC_BUFFER_SIZE = 256
) (
input clk,
input reset,
input [63:0] phy_data,
input [1:0] phy_header,
input phy_block_sync,
output [63:0] rx_data,
output reg buffer_ready_n = 'b1,
input all_buffer_ready_n,
input buffer_release_n,
input lmfc_edge,
output emb_lock,
input cfg_disable_scrambler,
input [1:0] cfg_header_mode, // 0 - CRC12 ; 1 - CRC3; 2 - FEC; 3 - CMD
input [4:0] cfg_rx_thresh_emb_err,
input [7:0] cfg_beats_per_multiframe,
input ctrl_err_statistics_reset,
input [3:0] ctrl_err_statistics_mask,
output [31:0] status_err_statistics_cnt,
output [2:0] status_lane_emb_state,
output reg [7:0] status_lane_skew
);
reg [11:0] crc12_calculated_prev;
wire [63:0] data_descrambled_s;
wire [63:0] data_descrambled;
wire [11:0] crc12_received;
wire [11:0] crc12_calculated;
wire event_invalid_header;
wire event_unexpected_eomb;
wire event_unexpected_eoemb;
wire event_crc12_mismatch;
wire err_cnt_rst;
wire [63:0] rx_data_msb_s;
wire eomb;
wire eoemb;
wire [7:0] sh_count;
jesd204_rx_header i_rx_header (
.clk(clk),
.reset(reset),
.sh_lock(phy_block_sync),
.header(phy_header),
.cfg_header_mode(cfg_header_mode),
.cfg_rx_thresh_emb_err(cfg_rx_thresh_emb_err),
.cfg_beats_per_multiframe(cfg_beats_per_multiframe),
.emb_lock(emb_lock),
.valid_eomb(eomb),
.valid_eoemb(eoemb),
.crc12(crc12_received),
.crc3(),
.fec(),
.cmd(),
.sh_count(sh_count),
.status_lane_emb_state(status_lane_emb_state),
.event_invalid_header(event_invalid_header),
.event_unexpected_eomb(event_unexpected_eomb),
.event_unexpected_eoemb(event_unexpected_eoemb)
);
jesd204_crc12 i_crc12 (
.clk(clk),
.reset(reset),
.init(eomb),
.data_in(phy_data),
.crc12(crc12_calculated)
);
reg crc12_on = 'b0;
always @(posedge clk) begin
if (reset == 1'b1) begin
crc12_on <= 1'b0;
end else if (eomb) begin
crc12_on <= 1'b1;
end
end
reg crc12_rdy = 'b0;
always @(posedge clk) begin
if (reset == 1'b1) begin
crc12_rdy <= 1'b0;
end else if (crc12_on && eomb) begin
crc12_rdy <= 1'b1;
end
end
always @(posedge clk) begin
if (eomb) begin
crc12_calculated_prev <= crc12_calculated;
end
end
assign event_crc12_mismatch = crc12_rdy && eomb && (crc12_calculated_prev != crc12_received);
assign err_cnt_rst = reset || ctrl_err_statistics_reset;
error_monitor #(
.EVENT_WIDTH(4),
.CNT_WIDTH(32)
) i_error_monitor (
.clk(clk),
.reset(err_cnt_rst),
.active(1'b1),
.error_event({
event_invalid_header,
event_unexpected_eomb,
event_unexpected_eoemb,
event_crc12_mismatch
}),
.error_event_mask(ctrl_err_statistics_mask),
.status_err_cnt(status_err_statistics_cnt)
);
jesd204_scrambler_64b #(
.WIDTH(64),
.DESCRAMBLE(1)
) i_descrambler (
.clk(clk),
.reset(reset),
.enable(~cfg_disable_scrambler),
.data_in(phy_data),
.data_out(data_descrambled_s)
);
pipeline_stage #(
.WIDTH(64),
.REGISTERED(1)
) i_pipeline_stage2 (
.clk(clk),
.in({
data_descrambled_s
}),
.out({
data_descrambled
})
);
// Control when data is written to the elastic buffer
// Start writing to the buffer when current lane is multiblock locked, but if
// other lanes are not writing in the next half multiblock period stop
// writing.
// This limits the supported lane skew to half of the multiframe
always @(posedge clk) begin
if (reset | ~emb_lock) begin
buffer_ready_n <= 1'b1;
end else if (sh_count == {1'b0,cfg_beats_per_multiframe[7:1]} && all_buffer_ready_n) begin
buffer_ready_n <= 1'b1;
end else if (eoemb) begin
buffer_ready_n <= 1'b0;
end
end
elastic_buffer #(
.WIDTH(64),
.SIZE(ELASTIC_BUFFER_SIZE)
) i_elastic_buffer (
.clk(clk),
.reset(reset),
.wr_data(data_descrambled),
.rd_data(rx_data_msb_s),
.ready_n(buffer_ready_n),
.do_release_n(buffer_release_n)
);
// Measure the delay from the eoemb to the next LMFC edge.
always @(posedge clk) begin
if (lmfc_edge) begin
status_lane_skew <= sh_count;
end
end
/* Reorder octets LSB first */
genvar i;
generate
for (i = 0; i < 64; i = i + 8) begin: g_link_data
assign rx_data[i+:8] = rx_data_msb_s[64-1-i-:8];
end
endgenerate
endmodule
adi_library/jesd204/jesd204_rx/vivado.jou
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#-----------------------------------------------------------
# Vivado v2019.1.3 (64-bit)
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
# Start of session at: Wed Dec 8 20:25:03 2021
# Process ID: 145992
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx
# Command line: vivado -mode batch -source jesd204_rx_ip.tcl
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx/vivado.log
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx/vivado.jou
#-----------------------------------------------------------
source jesd204_rx_ip.tcl
adi_library/jesd204/jesd204_rx/vivado.log
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#-----------------------------------------------------------
# Vivado v2019.1.3 (64-bit)
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
# Start of session at: Wed Dec 8 20:25:03 2021
# Process ID: 145992
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx
# Command line: vivado -mode batch -source jesd204_rx_ip.tcl
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx/vivado.log
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx/vivado.jou
#-----------------------------------------------------------
source jesd204_rx_ip.tcl
# source ../../scripts/adi_env.tcl
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
## if [info exists ::env(ADI_HDL_DIR)] {
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
## }
## if [info exists ::env(ADI_GHDL_DIR)] {
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
## }
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
### variable auto_set_param_list
### variable auto_set_param_list_overwritable
### variable fpga_series_list
### variable fpga_family_list
### variable speed_grade_list
### variable dev_package_list
### variable xcvr_type_list
### variable fpga_voltage_list
### set auto_set_param_list { \
### DEV_PACKAGE \
### SPEED_GRADE \
### FPGA_FAMILY \
### FPGA_TECHNOLOGY }
### set auto_set_param_list_overwritable { \
### FPGA_VOLTAGE \
### XCVR_TYPE }
### set fpga_technology_list { \
### { Unknown 0 } \
### { 7series 1 } \
### { ultrascale 2 } \
### { ultrascale+ 3 }}
### set fpga_family_list { \
### { Unknown 0 } \
### { artix 1 } \
### { kintex 2 } \
### { virtex 3 } \
### { zynq 4 }}
### set speed_grade_list { \
### { Unknown 0 } \
### { -1 10 } \
### { -1L 11 } \
### { -1H 12 } \
### { -1HV 13 } \
### { -1LV 14 } \
### { -2 20 } \
### { -2L 21 } \
### { -2LV 22 } \
### { -3 30 }}
### set dev_package_list { \
### { Unknown 0 } \
### { rf 1 } \
### { fl 2 } \
### { ff 3 } \
### { fb 4 } \
### { hc 5 } \
### { fh 6 } \
### { cs 7 } \
### { cp 8 } \
### { ft 9 } \
### { fg 10 } \
### { sb 11 } \
### { rb 12 } \
### { rs 13 } \
### { cl 14 } \
### { sf 15 } \
### { ba 16 } \
### { fa 17 } \
### { fs 18 } \
### { fi 19 }}
### set xcvr_type_list { \
### { Unknown 0 } \
### { GTPE2_NOT_SUPPORTED 1 } \
### { GTXE2 2 } \
### { GTHE2_NOT_SUPPORTED 3 } \
### { GTZE2_NOT_SUPPORTED 4 } \
### { GTHE3 5 } \
### { GTYE3_NOT_SUPPORTED 6 } \
### { GTRE4_NOT_SUPPORTED 7 } \
### { GTHE4 8 } \
### { GTYE4 9 } \
### { GTME4_NOT_SUPPORTED 10}}
### set fpga_voltage_list {0 5000} ;
### proc adi_device_spec {cellpath param} {
###
### set list_pointer [string tolower $param]
### set list_pointer [append list_pointer "_list"]
###
### upvar 1 $list_pointer $list_pointer
###
### set ip [get_bd_cells $cellpath]
### set part [get_property PART [current_project]]
###
### switch -regexp -- $param {
### FPGA_TECHNOLOGY {
### switch -regexp -- $part {
### ^xc7 {set series_name 7series}
### ^xczu {set series_name ultrascale+}
### ^xc.u.p {set series_name ultrascale+}
### ^xc.u {set series_name ultrascale }
### default {
### puts "Undefined fpga technology for \"$part\"!"
### exit -1
### }
### }
### return "$series_name"
### }
### FPGA_FAMILY {
### set fpga_family [get_property FAMILY $part]
### foreach i $fpga_family_list {
### regexp ^[lindex $i 0] $fpga_family matched
### }
### return "$matched"
### }
### SPEED_GRADE {
### set speed_grade [get_property SPEED $part]
### return "$speed_grade"
### }
### DEV_PACKAGE {
### set dev_package [get_property PACKAGE $part]
### foreach i $dev_package_list {
### regexp ^[lindex $i 0] $dev_package matched
### }
### return "$matched"
### }
### XCVR_TYPE {
### set matched ""
### set dev_transcivers "none"
### foreach x [list_property $part] {
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
### }
### foreach i $xcvr_type_list {
### regexp ^[lindex $i 0] $dev_transcivers matched
### }
### if { $matched eq "" } {
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
### }
### return "$matched"
### }
### FPGA_VOLTAGE {
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
###
### return "$fpga_voltage"
### }
### default {
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
### }
### }
### }
## if {![info exists REQUIRED_VIVADO_VERSION]} {
## set REQUIRED_VIVADO_VERSION "2019.1"
## }
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
## set IGNORE_VERSION_CHECK 1
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
## set IGNORE_VERSION_CHECK 0
## }
## proc adi_ip_ttcl {ip_name ip_constr_files} {
##
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
## set_property -dict [list \
## type ttcl \
## ] $f
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
## }
## proc adi_ip_sim_ttcl {ip_name ip_files} {
##
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
## set f [ipx::add_file $ip_files $proj_filegroup]
## set_property -dict [list \
## type ttcl \
## ] $f
## ipx::reorder_files -front $ip_files $proj_filegroup
## }
## proc adi_ip_bd {ip_name ip_bd_files} {
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
## if {$proj_filegroup == {}} {
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
## }
##
## foreach file $ip_bd_files {
## set f [ipx::add_file $file $proj_filegroup]
## set_property -dict [list \
## type tclSource \
## ] $f
## }
## }
## proc adi_ip_infer_streaming_interfaces {ip_name} {
##
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
##
## }
## proc adi_ip_infer_mm_interfaces {ip_name} {
##
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
##
## }
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
## set_property ENABLEMENT_DEPENDENCY $dependency $port
## if {$driver_value != {}} {
## set_property DRIVER_VALUE $driver_value $port
## }
## }
## }
## proc adi_set_bus_dependency {bus prefix dependency} {
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
## adi_set_ports_dependency $prefix $dependency 0
## }
## proc adi_add_port_map {bus phys logic} {
## set map [ipx::add_port_map $phys $bus]
## set_property "PHYSICAL_NAME" $phys $map
## set_property "LOGICAL_NAME" $logic $map
## }
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
##
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
## set_property "BUS_TYPE_VLNV" $bus_type $bus
## set_property "INTERFACE_MODE" $mode $bus
##
## foreach port_map $port_maps {
## adi_add_port_map $bus {*}$port_map
## }
## }
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
## for {set i 0} {$i < $num} {incr i} {
## set bus_name [format "%s%d" $bus_name_prefix $i]
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
##
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
## set_property "BUS_TYPE_VLNV" $bus_type $bus
## set_property "INTERFACE_MODE" $mode $bus
##
## if {$dependency ne ""} {
## set bus_dependency [string map [list "{i}" $i] $dependency]
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
## }
##
## foreach port_map $port_maps {
## lassign $port_map phys logic width width_dep
## set map [ipx::add_port_map $phys $bus]
## set_property "PHYSICAL_NAME" $phys $map
## set_property "LOGICAL_NAME" $logic $map
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
## if {$width_dep ne ""} {
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
## set width_dep_r "(($width_dep) * $i)"
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
## }
## }
## }
## }
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
## set_property display_name $clock_inf_name $clock_inf
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
## set_property physical_name $clock_signal_name $clock_map
##
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
## set_property value $bus_inf_name $assoc_busif
##
## if { $reset_signal_name != "" } {
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
## set_property value $reset_signal_name $assoc_reset
##
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
## set_property display_name $reset_inf_name $reset_inf
## set_property interface_mode $reset_signal_mode $reset_inf
## set reset_map [ipx::add_port_map "RST" $reset_inf]
## set_property physical_name $reset_signal_name $reset_map
##
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
## set_property value "ACTIVE_LOW" $reset_polarity
## } else {
## set_property value "ACTIVE_HIGH" $reset_polarity
## }
## }
## }
## proc adi_ip_add_core_dependencies {vlnvs} {
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
## foreach vlnv $vlnvs {
## ipx::add_subcore $vlnv $file_group
## }
## }
## }
## proc adi_ip_create {ip_name} {
##
## global ad_hdl_dir
## global ad_ghdl_dir
## global REQUIRED_VIVADO_VERSION
## global IGNORE_VERSION_CHECK
##
## set VIVADO_VERSION [version -short]
## if {$IGNORE_VERSION_CHECK} {
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
## puts -nonewline "got $VIVADO_VERSION.\n"
## }
## } else {
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
## puts -nonewline "ERROR: vivado version mismatch; "
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
## puts -nonewline "got $VIVADO_VERSION.\n"
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
## exit 2
## }
## }
##
## create_project $ip_name . -force
##
## ## Load custom message severity definitions
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
##
## set lib_dirs $ad_hdl_dir/library
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
## lappend lib_dirs $ad_ghdl_dir/library
## }
##
## set_property ip_repo_paths $lib_dirs [current_fileset]
## update_ip_catalog
## }
## proc adi_ip_files {ip_name ip_files} {
## set proj_fileset [get_filesets sources_1]
## foreach m_file $ip_files {
## if {[file extension $m_file] eq ".xdc"} {
## add_files -norecurse -fileset constrs_1 $m_file
## } else {
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
## }
## }
## set_property "top" "$ip_name" $proj_fileset
## }
## proc adi_ip_properties_lite {ip_name} {
##
## global ad_hdl_dir
##
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
##
## set_property name $ip_name [ipx::current_core]
##
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
## set_property company_url {http://www.analog.com} [ipx::current_core]
##
## set i_families ""
## foreach i_part [get_parts] {
## lappend i_families [get_property FAMILY $i_part]
## }
## set i_families [lsort -unique $i_families]
## set s_families [get_property supported_families [ipx::current_core]]
## foreach i_family $i_families {
## set s_families "$s_families $i_family Production"
## set s_families "$s_families $i_family Beta"
## }
## set_property supported_families $s_families [ipx::current_core]
##
## ipx::save_core [ipx::current_core]
##
## ipx::remove_all_bus_interface [ipx::current_core]
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
## foreach map $memory_maps {
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
## }
##
## ipx::update_checksums [ipx::current_core]
## ipx::save_core [ipx::current_core]
## }
## proc adi_ip_properties {ip_name} {
##
## adi_ip_properties_lite $ip_name
##
## ipx::infer_bus_interface {\
## s_axi_awvalid \
## s_axi_awaddr \
## s_axi_awprot \
## s_axi_awready \
## s_axi_wvalid \
## s_axi_wdata \
## s_axi_wstrb \
## s_axi_wready \
## s_axi_bvalid \
## s_axi_bresp \
##
## s_axi_bready \
## s_axi_arvalid \
## s_axi_araddr \
## s_axi_arprot \
## s_axi_arready \
## s_axi_rvalid \
## s_axi_rdata \
## s_axi_rresp \
## s_axi_rready} \
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
##
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
##
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
##
## if {$raddr_width != $waddr_width} {
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
## set range 65536
## } else {
## if {$raddr_width >= 16} {
## set range 65536
## } else {
## set range [expr 1 << $raddr_width]
## }
## }
##
## ipx::add_memory_map {s_axi} [ipx::current_core]
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
## set_property range $range [ipx::get_address_blocks axi_lite \
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
## ipx::save_core
## }
## proc adi_init_bd_tcl {} {
##
## global auto_set_param_list
## global auto_set_param_list_overwritable
## set cc [ipx::current_core]
##
## if { [file exists bd] } {
## file delete -force bd
## }
## file mkdir bd
##
## set bd_tcl [open "bd/bd.tcl" w]
##
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
## puts $bd_tcl "proc init {cellpath otherInfo} {"
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
## puts $bd_tcl ""
## set auto_set_param ""
## foreach i $auto_set_param_list {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
## append auto_set_param " $i \\\n"
## }
## }
## if { $auto_set_param ne "" } {
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
## puts $bd_tcl $auto_set_param
## }
##
## set auto_set_overwritable_param ""
## foreach i $auto_set_param_list_overwritable {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
## append auto_set_overwritable_param " $i \\\n"
## }
## }
## if { $auto_set_overwritable_param ne "" } {
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
## puts $bd_tcl $auto_set_overwritable_param
## }
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
## puts $bd_tcl "}"
## puts $bd_tcl ""
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
## puts $bd_tcl ""
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
## puts $bd_tcl ""
## puts $bd_tcl " set parent_dir \"../\""
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
## puts $bd_tcl " break"
## puts $bd_tcl " }"
## puts $bd_tcl " append parent_dir \"../\""
## puts $bd_tcl " }"
## puts $bd_tcl ""
## puts $bd_tcl " # Find predefindes auto assignable parameters"
## puts $bd_tcl " foreach i \$auto_set_param_list {"
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
## puts $bd_tcl " }"
## puts $bd_tcl " }"
## puts $bd_tcl ""
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
## puts $bd_tcl " }"
## puts $bd_tcl " }"
## puts $bd_tcl "}"
## puts $bd_tcl ""
## close $bd_tcl
##
## set proj_fileset [get_filesets sources_1]
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
##
## set local_mk [open "temporary_case_dependencies.mk" w]
## seek $local_mk 0 start
## puts $local_mk "CLEAN_TARGET += bd"
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
## close $local_mk
## }
## proc adi_add_auto_fpga_spec_params {} {
##
## global auto_set_param_list
## global auto_set_param_list_overwritable
## set cc [ipx::current_core]
##
## foreach i $auto_set_param_list {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
## adi_add_device_spec_param $i
## }
## }
## foreach i $auto_set_param_list_overwritable {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
## adi_add_device_spec_param $i
## }
## }
## }
## proc adi_add_device_spec_param {ip_param} {
##
## set cc [ipx::current_core]
##
## set list_pointer [string tolower $ip_param]
## set list_pointer [append list_pointer "_list"]
##
## global $list_pointer
##
## # set j 1D list from the original list
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
##
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
## set_property -dict [list \
## "value_validation_type" "range_long" \
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
## [ipx::get_user_parameters $ip_param -of_objects $cc]
## } else {
## set_property -dict [list \
## "value_validation_type" "pairs" \
## "value_validation_pairs" $j ] \
## [ipx::get_user_parameters $ip_param -of_objects $cc]
## }
##
## # FPGA info grup
## set info_group_name "FPGA info"
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
## if { [string trim $info_group] eq "" } {
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
## -parent $page0 -display_name $info_group_name]
## }
##
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
## set_property -dict [list "widget" "comboBox" ] $p
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
## }
## proc adi_if_define {name} {
##
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
## ipx::create_bus_definition analog.com interface $name 1.0
##
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
##
## ipx::save_abstraction_definition [ipx::current_busabs]
## ipx::save_bus_definition [ipx::current_busdef]
## }
## proc adi_if_ports {dir width name {type none}} {
##
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
## set_property master_presence required $m_intf
## set_property slave_presence required $m_intf
## set_property master_width $width $m_intf
## set_property slave_width $width $m_intf
##
## set m_dir "in"
## set s_dir "out"
## if {$dir eq "output"} {
## set m_dir "out"
## set s_dir "in"
## }
##
## set_property master_direction $m_dir $m_intf
## set_property slave_direction $s_dir $m_intf
##
## if {$type ne "none"} {
## set_property is_${type} true $m_intf
## }
##
## ipx::save_bus_definition [ipx::current_busdef]
## ipx::save_abstraction_definition [ipx::current_busabs]
## }
## proc adi_if_infer_bus {if_name mode name maps} {
##
## ipx::add_bus_interface $name [ipx::current_core]
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
## set_property interface_mode $mode $m_bus_if
##
## foreach map $maps {
## set m_maps [regexp -all -inline {\S+} $map]
## lassign $m_maps p_name p_map
## ipx::add_port_map $p_name $m_bus_if
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
## }
## }
# adi_ip_create jesd204_rx
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
## set_msg_config -id {BD 41-1343} -new_severity WARNING
## set_msg_config -id {BD 41-1306} -new_severity WARNING
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
## set_msg_config -id {Synth 8-3331} -new_severity INFO
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx'.)
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
# adi_ip_files jesd204_rx [list \
# "jesd204_rx_lane.v" \
# "jesd204_rx_lane_64b.v" \
# "jesd204_rx_header.v" \
# "jesd204_rx_cgs.v" \
# "jesd204_rx_ctrl.v" \
# "jesd204_rx_ctrl_64b.v" \
# "elastic_buffer.v" \
# "error_monitor.v" \
# "jesd204_ilas_monitor.v" \
# "align_mux.v" \
# "jesd204_lane_latency_monitor.v" \
# "jesd204_rx_frame_mark.v" \
# "jesd204_rx_frame_align_monitor.v" \
# "jesd204_rx_constr.ttcl" \
# "jesd204_rx.v" \
# ]
# adi_ip_properties_lite jesd204_rx
WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl' ignored by IP packager.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_data_r' has a dependency on the module local parameter or undefined parameter 'DW'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_header_r' has a dependency on the module local parameter or undefined parameter 'HW'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_charisk_r' has a dependency on the module local parameter or undefined parameter 'CW'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_notintable_r' has a dependency on the module local parameter or undefined parameter 'CW'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_disperr_r' has a dependency on the module local parameter or undefined parameter 'CW'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'rx_data_s' has a dependency on the module local parameter or undefined parameter 'DW'.
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'ilas_config' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'phy' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave.
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'phy_block' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'phy_char_align' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'rx' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
WARNING: [IP_Flow 19-5464] No port map found for required logical port err_statistics_reset on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave.
WARNING: [IP_Flow 19-5464] No port map found for required logical port err_statistics_mask on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'cfg' of definition 'analog.com:interface:jesd204_rx_cfg:1.0' (from User Repositories).
INFO: [IP_Flow 19-5107] Inferred bus interface 'event_unexpected_lane_error' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
INFO: [IP_Flow 19-5107] Inferred bus interface 'status_ctrl' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
INFO: [IP_Flow 19-5107] Inferred bus interface 'status_lane_cgs' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
INFO: [IP_Flow 19-5107] Inferred bus interface 'status_lane_emb' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'rx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
WARNING: [IP_Flow 19-5150] The Range '((8 * NUM_LANES) - 1):0' is present in all ports of the interface 'status_err_cnt'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
WARNING: [IP_Flow 19-5463] No port map found for required logical port lane_frame_align on bus interface abstraction jesd204_rx_status_rtl for interface type master.
WARNING: [IP_Flow 19-5463] No port map found for required logical port lane_latency_ready on bus interface abstraction jesd204_rx_status_rtl for interface type master.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'status' of definition 'analog.com:interface:jesd204_rx_status:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
INFO: [IP_Flow 19-5107] Inferred bus interface 'event' of definition 'analog.com:interface:jesd204_tx_event:1.0' (from User Repositories).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_err_statistics_reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'lmfc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-818] Not transferring value dependency attribute "((spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) ? 8 : 4)" into user parameter "DATA_PATH_WIDTH".
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'ilas_config_data' and definition port 'DATA'.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'.
WARNING: [IP_Flow 19-1965] Bus Interface 'ilas_config': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'.
WARNING: [IP_Flow 19-1965] Bus Interface 'phy': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'phy_block': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'phy_block': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'phy_en_char_align' and definition port 'EN'.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'.
WARNING: [IP_Flow 19-1965] Bus Interface 'phy_char_align': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data' and definition port 'DATA'.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'.
WARNING: [IP_Flow 19-1965] Bus Interface 'rx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_reset" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_mask" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_ctrl_state' and definition port 'ctrl_state'.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_lane_cgs_state' and definition port 'lane_cgs_state'.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_lane_emb_state' and definition port 'lane_emb_state'.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_lane_ifs_ready' and definition port 'lane_ifs_ready'.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_lane_latency' and definition port 'lane_latency'.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_err_statistics_cnt' and definition port 'err_statistics_cnt'.
WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "lane_frame_align" of the bus abstraction "analog.com:interface:jesd204_rx_status_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "lane_latency_ready" of the bus abstraction "analog.com:interface:jesd204_rx_status_rtl:1.0" is missing.
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
WARNING: [IP_Flow 19-3153] Bus Interface 'lmfc_clk': ASSOCIATED_BUSIF bus parameter is missing.
WARNING: [IP_Flow 19-4751] Bus Interface 'lmfc_clk': FREQ_HZ bus parameter is missing for output clock interface.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
# adi_ip_ttcl jesd204_rx "jesd204_rx_constr.ttcl"
# adi_ip_add_core_dependencies { \
# analog.com:user:jesd204_common:1.0 \
# }
# set_property display_name "ADI JESD204 Receive" [ipx::current_core]
# set_property description "ADI JESD204 Receive" [ipx::current_core]
# adi_add_multi_bus 16 "rx_phy" "slave" \
# "xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0" \
# "xilinx.com:display_jesd204:jesd204_rx_bus:1.0" \
# [list \
# { "phy_data" "rxdata" 32 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')) * 8)"} \
# { "phy_charisk" "rxcharisk" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \
# { "phy_disperr" "rxdisperr" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \
# { "phy_notintable" "rxnotintable" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \
# { "phy_header" "rxheader" 2} \
# { "phy_block_sync" "rxblock_sync" 1} \
# ] \
# "(spirit:decode(id('MODELPARAM_VALUE.NUM_LANES')) > {i})"
# adi_add_bus "rx_cfg" "slave" \
# "analog.com:interface:jesd204_rx_cfg_rtl:1.0" \
# "analog.com:interface:jesd204_rx_cfg:1.0" \
# { \
# { "cfg_lanes_disable" "lanes_disable" } \
# { "cfg_links_disable" "links_disable" } \
# { "cfg_beats_per_multiframe" "beats_per_multiframe" } \
# { "cfg_octets_per_frame" "octets_per_frame" } \
# { "cfg_lmfc_offset" "lmfc_offset" } \
# { "cfg_sysref_oneshot" "sysref_oneshot" } \
# { "cfg_sysref_disable" "sysref_disable" } \
# { "cfg_buffer_delay" "buffer_delay" } \
# { "cfg_buffer_early_release" "buffer_early_release" } \
# { "cfg_disable_char_replacement" "disable_char_replacement" } \
# { "ctrl_err_statistics_reset" "err_statistics_reset" } \
# { "ctrl_err_statistics_mask" "err_statistics_mask" } \
# { "cfg_disable_scrambler" "disable_scrambler" } \
# { "cfg_frame_align_err_threshold" "frame_align_err_threshold" } \
# }
# adi_add_bus "rx_status" "master" \
# "analog.com:interface:jesd204_rx_status_rtl:1.0" \
# "analog.com:interface:jesd204_rx_status:1.0" \
# { \
# { "status_ctrl_state" "ctrl_state" } \
# { "status_lane_cgs_state" "lane_cgs_state" } \
# { "status_lane_emb_state" "lane_emb_state" } \
# { "status_err_statistics_cnt" "err_statistics_cnt" } \
# { "status_lane_ifs_ready" "lane_ifs_ready" } \
# { "status_lane_latency" "lane_latency" } \
# { "status_lane_frame_align_err_cnt" "lane_frame_align_err_cnt" } \
# }
# adi_add_bus "rx_ilas_config" "master" \
# "analog.com:interface:jesd204_rx_ilas_config_rtl:1.0" \
# "analog.com:interface:jesd204_rx_ilas_config:1.0" \
# { \
# { "ilas_config_valid" "valid" } \
# { "ilas_config_addr" "addr" } \
# { "ilas_config_data" "data" } \
# }
# adi_add_bus "rx_event" "master" \
# "analog.com:interface:jesd204_rx_event_rtl:1.0" \
# "analog.com:interface:jesd204_rx_event:1.0" \
# { \
# { "event_sysref_alignment_error" "sysref_alignment_error" } \
# { "event_sysref_edge" "sysref_edge" } \
# { "event_frame_alignment_error" "frame_alignment_error" } \
# { "event_unexpected_lane_state_error" "unexpected_lane_state_error" } \
# }
# adi_add_bus_clock "clk" "rx_cfg:rx_ilas_config:rx_event:rx_status:rx_data" "reset"
# adi_set_bus_dependency "rx_ilas_config" "rx_ilas_config" \
# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
# adi_set_ports_dependency "sync" \
# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
# adi_set_ports_dependency "phy_en_char_align" \
# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
# set cc [ipx::current_core]
# set_property -dict [list \
# driver_value 0 \
# ] [ipx::get_ports phy_header -of_objects $cc]
# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
# set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
# ipgui::move_param -component $cc -order 0 $p -parent $page0
# set_property -dict [list \
# "display_name" "Link Layer mode" \
# "tooltip" "Link Layer mode" \
# "widget" "comboBox" \
# ] $p
# set_property -dict [list \
# value_validation_type pairs \
# value_validation_pairs {64B66B 2 8B10B 1} \
# ] [ipx::get_user_parameters $p -of_objects $cc]
# set param [ipx::get_user_parameters DATA_PATH_WIDTH -of_objects $cc]
# set_property -dict [list \
# enablement_value false \
# value_tcl_expr {expr $LINK_MODE*4} \
# ] $param
# set param [ipx::add_user_parameter SYSREF_IOB $cc]
# set_property -dict {value_resolve_type user value_format bool value true} $param
# set param [ipgui::add_param -name {SYSREF_IOB} -component $cc -parent $page0]
# set_property -dict [list \
# display_name {Place SYSREF in IOB} \
# widget {checkBox} \
# show_label true \
# ] $param
# ipx::create_xgui_files [ipx::current_core]
# ipx::save_core [ipx::current_core]
INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:25:18 2021...
adi_library/jesd204/jesd204_rx/xgui/jesd204_rx_v1_0.tcl
+134
View File
@@ -0,0 +1,134 @@
# Loading additional proc with user specified bodies to compute parameter values.
source [file join [file dirname [file dirname [info script]]] gui/jesd204_rx_v1_0.gtcl]
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "LINK_MODE" -parent ${Page_0} -widget comboBox
ipgui::add_param $IPINST -name "DATA_PATH_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "ENABLE_FRAME_ALIGN_CHECK" -parent ${Page_0}
ipgui::add_param $IPINST -name "ENABLE_FRAME_ALIGN_ERR_RESET" -parent ${Page_0}
ipgui::add_param $IPINST -name "NUM_INPUT_PIPELINE" -parent ${Page_0}
ipgui::add_param $IPINST -name "NUM_LANES" -parent ${Page_0}
ipgui::add_param $IPINST -name "NUM_LINKS" -parent ${Page_0}
ipgui::add_param $IPINST -name "SYSREF_IOB" -parent ${Page_0}
}
proc update_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH PARAM_VALUE.LINK_MODE } {
# Procedure called to update DATA_PATH_WIDTH when any of the dependent parameters in the arguments change
set DATA_PATH_WIDTH ${PARAM_VALUE.DATA_PATH_WIDTH}
set LINK_MODE ${PARAM_VALUE.LINK_MODE}
set values(LINK_MODE) [get_property value $LINK_MODE]
set_property value [gen_USERPARAMETER_DATA_PATH_WIDTH_VALUE $values(LINK_MODE)] $DATA_PATH_WIDTH
}
proc validate_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH } {
# Procedure called to validate DATA_PATH_WIDTH
return true
}
proc update_PARAM_VALUE.ENABLE_FRAME_ALIGN_CHECK { PARAM_VALUE.ENABLE_FRAME_ALIGN_CHECK } {
# Procedure called to update ENABLE_FRAME_ALIGN_CHECK when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ENABLE_FRAME_ALIGN_CHECK { PARAM_VALUE.ENABLE_FRAME_ALIGN_CHECK } {
# Procedure called to validate ENABLE_FRAME_ALIGN_CHECK
return true
}
proc update_PARAM_VALUE.ENABLE_FRAME_ALIGN_ERR_RESET { PARAM_VALUE.ENABLE_FRAME_ALIGN_ERR_RESET } {
# Procedure called to update ENABLE_FRAME_ALIGN_ERR_RESET when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ENABLE_FRAME_ALIGN_ERR_RESET { PARAM_VALUE.ENABLE_FRAME_ALIGN_ERR_RESET } {
# Procedure called to validate ENABLE_FRAME_ALIGN_ERR_RESET
return true
}
proc update_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } {
# Procedure called to update LINK_MODE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } {
# Procedure called to validate LINK_MODE
return true
}
proc update_PARAM_VALUE.NUM_INPUT_PIPELINE { PARAM_VALUE.NUM_INPUT_PIPELINE } {
# Procedure called to update NUM_INPUT_PIPELINE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_INPUT_PIPELINE { PARAM_VALUE.NUM_INPUT_PIPELINE } {
# Procedure called to validate NUM_INPUT_PIPELINE
return true
}
proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
# Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
# Procedure called to validate NUM_LANES
return true
}
proc update_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } {
# Procedure called to update NUM_LINKS when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } {
# Procedure called to validate NUM_LINKS
return true
}
proc update_PARAM_VALUE.SYSREF_IOB { PARAM_VALUE.SYSREF_IOB } {
# Procedure called to update SYSREF_IOB when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SYSREF_IOB { PARAM_VALUE.SYSREF_IOB } {
# Procedure called to validate SYSREF_IOB
return true
}
proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES}
}
proc update_MODELPARAM_VALUE.NUM_LINKS { MODELPARAM_VALUE.NUM_LINKS PARAM_VALUE.NUM_LINKS } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_LINKS}] ${MODELPARAM_VALUE.NUM_LINKS}
}
proc update_MODELPARAM_VALUE.NUM_INPUT_PIPELINE { MODELPARAM_VALUE.NUM_INPUT_PIPELINE PARAM_VALUE.NUM_INPUT_PIPELINE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_INPUT_PIPELINE}] ${MODELPARAM_VALUE.NUM_INPUT_PIPELINE}
}
proc update_MODELPARAM_VALUE.LINK_MODE { MODELPARAM_VALUE.LINK_MODE PARAM_VALUE.LINK_MODE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.LINK_MODE}] ${MODELPARAM_VALUE.LINK_MODE}
}
proc update_MODELPARAM_VALUE.DATA_PATH_WIDTH { MODELPARAM_VALUE.DATA_PATH_WIDTH PARAM_VALUE.DATA_PATH_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DATA_PATH_WIDTH}] ${MODELPARAM_VALUE.DATA_PATH_WIDTH}
}
proc update_MODELPARAM_VALUE.ENABLE_FRAME_ALIGN_CHECK { MODELPARAM_VALUE.ENABLE_FRAME_ALIGN_CHECK PARAM_VALUE.ENABLE_FRAME_ALIGN_CHECK } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ENABLE_FRAME_ALIGN_CHECK}] ${MODELPARAM_VALUE.ENABLE_FRAME_ALIGN_CHECK}
}
proc update_MODELPARAM_VALUE.ENABLE_FRAME_ALIGN_ERR_RESET { MODELPARAM_VALUE.ENABLE_FRAME_ALIGN_ERR_RESET PARAM_VALUE.ENABLE_FRAME_ALIGN_ERR_RESET } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ENABLE_FRAME_ALIGN_ERR_RESET}] ${MODELPARAM_VALUE.ENABLE_FRAME_ALIGN_ERR_RESET}
}