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//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact [email protected] for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module jesd204_rx_header (
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input clk,
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input reset,
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input sh_lock,
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input [1:0] header,
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input [1:0] cfg_header_mode, // 0 - CRC12 ; 1 - CRC3; 2 - FEC; 3 - CMD
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input [4:0] cfg_rx_thresh_emb_err,
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input [7:0] cfg_beats_per_multiframe,
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output emb_lock,
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output valid_eomb,
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output valid_eoemb,
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// Received header data qualified by valid_eomb
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output [11:0] crc12,
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output [2:0] crc3,
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output [25:0] fec,
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output [18:0] cmd,
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output reg [7:0] sh_count = 'h0,
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output [2:0] status_lane_emb_state,
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output reg event_invalid_header,
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output reg event_unexpected_eomb,
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output reg event_unexpected_eoemb
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);
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localparam STATE_EMB_INIT = 3'b001;
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localparam STATE_EMB_HUNT = 3'b010;
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localparam STATE_EMB_LOCK = 3'b100;
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localparam BIT_EMB_INIT = 0;
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localparam BIT_EMB_HUNT = 1;
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localparam BIT_EMB_LOCK = 2;
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reg [2:0] state = STATE_EMB_INIT;
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reg [2:0] next_state;
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reg [31:0] sync_word = 'h0;
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wire header_bit;
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wire invalid_sequence;
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wire invalid_eoemb;
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wire invalid_eomb;
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wire [6:0] cmd0;
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wire [6:0] cmd1;
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wire [18:0] cmd3;
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wire eoemb;
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wire eomb;
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assign header_bit = header == 2'b01;
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always @(posedge clk) begin
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sync_word <= {sync_word[30:0],header_bit};
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end
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assign crc12 = {sync_word[31:29],sync_word[27:25],
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sync_word[23:21],sync_word[19:17]};
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assign crc3 = {sync_word[31:29]};
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assign cmd0 = {sync_word[15:13],sync_word[11],
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sync_word[7:5]};
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assign cmd1 = {sync_word[27:25],
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sync_word[19:17],
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sync_word[11]};
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assign cmd3 = {sync_word[31:29],sync_word[27:25],
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sync_word[23:21],sync_word[19:17],
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sync_word[15:13],sync_word[11],
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sync_word[7:5]};
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assign cmd = cfg_header_mode == 0 ? {12'b0,cmd0} :
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cfg_header_mode == 1 ? {12'b0,cmd1} :
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cfg_header_mode == 3 ? cmd3 : 'b0;
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assign fec = {sync_word[31:10],sync_word[8:5]};
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assign eomb = sync_word[4:0] == 5'b00001;
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assign eoemb = sync_word[9] & eomb;
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always @(posedge clk) begin
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if (next_state[BIT_EMB_INIT] || sh_count == cfg_beats_per_multiframe) begin
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sh_count <= 'h0;
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end else begin
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sh_count <= sh_count + 8'b1;
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end
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end
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reg [1:0] emb_vcount = 'b0;
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always @(posedge clk) begin
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if (state[BIT_EMB_INIT]) begin
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emb_vcount <= 'b0;
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end else if (state[BIT_EMB_HUNT] && (sh_count == 0 && eoemb)) begin
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emb_vcount <= emb_vcount + 'b1;
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end
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end
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reg [4:0] emb_icount = 'b0;
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always @(posedge clk) begin
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if (state[BIT_EMB_INIT]) begin
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emb_icount <= 'b0;
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end else if (state[BIT_EMB_LOCK]) begin
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if (sh_count == 0 && eoemb) begin
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emb_icount <= 'b0;
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end else if (invalid_eoemb || invalid_eomb) begin
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emb_icount <= emb_icount + 5'b1;
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end
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end
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end
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always @(*) begin
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next_state = state;
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case (state)
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STATE_EMB_INIT:
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if (eoemb) begin
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next_state = STATE_EMB_HUNT;
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end
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STATE_EMB_HUNT:
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if (invalid_sequence) begin
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next_state = STATE_EMB_INIT;
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end else if (eoemb && emb_vcount == 2'd3) begin
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next_state = STATE_EMB_LOCK;
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end
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STATE_EMB_LOCK:
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if (emb_icount == cfg_rx_thresh_emb_err) begin
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next_state = STATE_EMB_INIT;
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end
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endcase
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if (sh_lock == 1'b0) next_state = STATE_EMB_INIT;
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end
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assign invalid_eoemb = (sh_count == 0 && ~eoemb);
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assign invalid_eomb = (sh_count[4:0] == 0 && ~eomb);
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assign valid_eomb = next_state[BIT_EMB_LOCK] && eomb;
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assign valid_eoemb = next_state[BIT_EMB_LOCK] && eoemb;
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assign invalid_sequence = (invalid_eoemb || invalid_eomb);
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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state <= STATE_EMB_INIT;
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end else begin
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state <= next_state;
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end
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end
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assign emb_lock = next_state[BIT_EMB_LOCK];
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// Status & error events
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assign status_lane_emb_state = state;
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always @(posedge clk) begin
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event_invalid_header <= (~state[BIT_EMB_INIT]) && (header[0] == header[1]);
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event_unexpected_eomb <= (~state[BIT_EMB_INIT]) && (sh_count[4:0] != 0 && eomb);
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event_unexpected_eoemb <= (~state[BIT_EMB_INIT]) && invalid_eoemb;
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end
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endmodule
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