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This commit is contained in:
@@ -0,0 +1,17 @@
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||||
####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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||||
####################################################################################
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LIBRARY_NAME := jesd204_rx_static_config
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GENERIC_DEPS += jesd204_rx_static_config.v
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XILINX_DEPS += jesd204_rx_static_config_ip.tcl
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg_rtl.xml
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XILINX_INTERFACE_DEPS += jesd204/interfaces
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include ../../scripts/library.mk
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@@ -0,0 +1,511 @@
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<?xml version="1.0" encoding="UTF-8"?>
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||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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||||
<spirit:vendor>analog.com</spirit:vendor>
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||||
<spirit:library>user</spirit:library>
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||||
<spirit:name>jesd204_rx_static_config</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
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||||
<spirit:name>rx_cfg</spirit:name>
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||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="jesd204_rx_cfg" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="jesd204_rx_cfg_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>lanes_disable</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
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||||
<spirit:name>cfg_lanes_disable</spirit:name>
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||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>beats_per_multiframe</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cfg_beats_per_multiframe</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>octets_per_frame</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cfg_octets_per_frame</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>lmfc_offset</spirit:name>
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||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
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||||
<spirit:name>cfg_lmfc_offset</spirit:name>
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||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sysref_oneshot</spirit:name>
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||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cfg_sysref_oneshot</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>sysref_disable</spirit:name>
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||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
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||||
<spirit:name>cfg_sysref_disable</spirit:name>
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||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>buffer_early_release</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cfg_buffer_early_release</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>frame_align_err_threshold</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cfg_frame_align_err_threshold</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
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||||
<spirit:busInterface>
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||||
<spirit:name>rx_cfg_signal_clock</spirit:name>
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||||
<spirit:displayName>rx_cfg_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.RX_CFG_SIGNAL_CLOCK.ASSOCIATED_BUSIF">rx_cfg</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>jesd204_rx_static_config</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>af3b4ef0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>jesd204_rx_static_config</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>af3b4ef0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>c8f96f8b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cfg_lanes_disable</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.NUM_LANES')) - 1)">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cfg_links_disable</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.NUM_LINKS')) - 1)">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cfg_beats_per_multiframe</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cfg_octets_per_frame</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cfg_lmfc_offset</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cfg_sysref_oneshot</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cfg_sysref_disable</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cfg_buffer_delay</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cfg_buffer_early_release</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cfg_disable_scrambler</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cfg_disable_char_replacement</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cfg_frame_align_err_threshold</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>NUM_LANES</spirit:name>
|
||||
<spirit:displayName>Num Lanes</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_LANES">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>NUM_LINKS</spirit:name>
|
||||
<spirit:displayName>Num Links</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_LINKS">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>OCTETS_PER_FRAME</spirit:name>
|
||||
<spirit:displayName>Octets Per Frame</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.OCTETS_PER_FRAME">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>FRAMES_PER_MULTIFRAME</spirit:name>
|
||||
<spirit:displayName>Frames Per Multiframe</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FRAMES_PER_MULTIFRAME">32</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SCR</spirit:name>
|
||||
<spirit:displayName>Scr</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SCR">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>BUFFER_EARLY_RELEASE</spirit:name>
|
||||
<spirit:displayName>Buffer Early Release</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUFFER_EARLY_RELEASE">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>LINK_MODE</spirit:name>
|
||||
<spirit:displayName>Link Mode</spirit:displayName>
|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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<spirit:description>jesd204_rx_static_config_v1_0</spirit:description>
|
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<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_LANES</spirit:name>
|
||||
<spirit:displayName>Num Lanes</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_LANES">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_LINKS</spirit:name>
|
||||
<spirit:displayName>Num Links</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_LINKS">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>OCTETS_PER_FRAME</spirit:name>
|
||||
<spirit:displayName>Octets Per Frame</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.OCTETS_PER_FRAME">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FRAMES_PER_MULTIFRAME</spirit:name>
|
||||
<spirit:displayName>Frames Per Multiframe</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FRAMES_PER_MULTIFRAME">32</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SCR</spirit:name>
|
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<spirit:displayName>Scr</spirit:displayName>
|
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SCR">1</spirit:value>
|
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</spirit:parameter>
|
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<spirit:parameter>
|
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<spirit:name>BUFFER_EARLY_RELEASE</spirit:name>
|
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<spirit:displayName>Buffer Early Release</spirit:displayName>
|
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.BUFFER_EARLY_RELEASE">0</spirit:value>
|
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</spirit:parameter>
|
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<spirit:parameter>
|
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<spirit:name>LINK_MODE</spirit:name>
|
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<spirit:displayName>Link Mode</spirit:displayName>
|
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.LINK_MODE">1</spirit:value>
|
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</spirit:parameter>
|
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<spirit:parameter>
|
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<spirit:name>Component_Name</spirit:name>
|
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">jesd204_rx_static_config_v1_0</spirit:value>
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</spirit:parameter>
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version:1
|
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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eof:
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@@ -0,0 +1,6 @@
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<?xml version="1.0" encoding="UTF-8"?>
|
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<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
|
||||
@@ -0,0 +1,89 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_rx_static_config #(
|
||||
parameter NUM_LANES = 1,
|
||||
parameter NUM_LINKS = 1,
|
||||
parameter OCTETS_PER_FRAME = 1,
|
||||
parameter FRAMES_PER_MULTIFRAME = 32,
|
||||
parameter SCR = 1,
|
||||
parameter BUFFER_EARLY_RELEASE = 0,
|
||||
parameter LINK_MODE = 1 // 2 - 64B/66B; 1 - 8B/10B
|
||||
) (
|
||||
input clk,
|
||||
|
||||
output [NUM_LANES-1:0] cfg_lanes_disable,
|
||||
output [NUM_LINKS-1:0] cfg_links_disable,
|
||||
output [7:0] cfg_beats_per_multiframe,
|
||||
output [7:0] cfg_octets_per_frame,
|
||||
output [7:0] cfg_lmfc_offset,
|
||||
output cfg_sysref_oneshot,
|
||||
output cfg_sysref_disable,
|
||||
|
||||
output [7:0] cfg_buffer_delay,
|
||||
output cfg_buffer_early_release,
|
||||
output cfg_disable_scrambler,
|
||||
output cfg_disable_char_replacement,
|
||||
output [7:0] cfg_frame_align_err_threshold
|
||||
);
|
||||
|
||||
/* Only 4 is supported at the moment for 8b/10b and 8 for 64b */
|
||||
localparam DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4;
|
||||
|
||||
assign cfg_beats_per_multiframe = (FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME / DATA_PATH_WIDTH) - 1;
|
||||
assign cfg_octets_per_frame = OCTETS_PER_FRAME - 1;
|
||||
assign cfg_lmfc_offset = 3;
|
||||
assign cfg_sysref_oneshot = 1'b0;
|
||||
assign cfg_sysref_disable = 1'b0;
|
||||
assign cfg_buffer_delay = 'h0;
|
||||
assign cfg_buffer_early_release = BUFFER_EARLY_RELEASE;
|
||||
assign cfg_lanes_disable = {NUM_LANES{1'b0}};
|
||||
assign cfg_links_disable = {NUM_LINKS{1'b0}};
|
||||
assign cfg_disable_scrambler = SCR ? 1'b0 : 1'b1;
|
||||
assign cfg_disable_char_replacement = cfg_disable_scrambler;
|
||||
assign cfg_frame_align_err_threshold = 8'd4;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,376 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="67c056f0f2c6404c8956198504246fa8"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
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<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/jesd204_rx_static_config.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="jesd204_rx_static_config"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,713 @@
|
||||
|
||||
****** Vivado v2019.1.3 (64-bit)
|
||||
**** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
**** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
source jesd204_rx_static_config_ip.tcl
|
||||
# source ../../scripts/adi_env.tcl
|
||||
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
|
||||
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
|
||||
## if [info exists ::env(ADI_HDL_DIR)] {
|
||||
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
|
||||
## }
|
||||
## if [info exists ::env(ADI_GHDL_DIR)] {
|
||||
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
|
||||
## }
|
||||
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
|
||||
### variable auto_set_param_list
|
||||
### variable auto_set_param_list_overwritable
|
||||
### variable fpga_series_list
|
||||
### variable fpga_family_list
|
||||
### variable speed_grade_list
|
||||
### variable dev_package_list
|
||||
### variable xcvr_type_list
|
||||
### variable fpga_voltage_list
|
||||
### set auto_set_param_list { \
|
||||
### DEV_PACKAGE \
|
||||
### SPEED_GRADE \
|
||||
### FPGA_FAMILY \
|
||||
### FPGA_TECHNOLOGY }
|
||||
### set auto_set_param_list_overwritable { \
|
||||
### FPGA_VOLTAGE \
|
||||
### XCVR_TYPE }
|
||||
### set fpga_technology_list { \
|
||||
### { Unknown 0 } \
|
||||
### { 7series 1 } \
|
||||
### { ultrascale 2 } \
|
||||
### { ultrascale+ 3 }}
|
||||
### set fpga_family_list { \
|
||||
### { Unknown 0 } \
|
||||
### { artix 1 } \
|
||||
### { kintex 2 } \
|
||||
### { virtex 3 } \
|
||||
### { zynq 4 }}
|
||||
### set speed_grade_list { \
|
||||
### { Unknown 0 } \
|
||||
### { -1 10 } \
|
||||
### { -1L 11 } \
|
||||
### { -1H 12 } \
|
||||
### { -1HV 13 } \
|
||||
### { -1LV 14 } \
|
||||
### { -2 20 } \
|
||||
### { -2L 21 } \
|
||||
### { -2LV 22 } \
|
||||
### { -3 30 }}
|
||||
### set dev_package_list { \
|
||||
### { Unknown 0 } \
|
||||
### { rf 1 } \
|
||||
### { fl 2 } \
|
||||
### { ff 3 } \
|
||||
### { fb 4 } \
|
||||
### { hc 5 } \
|
||||
### { fh 6 } \
|
||||
### { cs 7 } \
|
||||
### { cp 8 } \
|
||||
### { ft 9 } \
|
||||
### { fg 10 } \
|
||||
### { sb 11 } \
|
||||
### { rb 12 } \
|
||||
### { rs 13 } \
|
||||
### { cl 14 } \
|
||||
### { sf 15 } \
|
||||
### { ba 16 } \
|
||||
### { fa 17 } \
|
||||
### { fs 18 } \
|
||||
### { fi 19 }}
|
||||
### set xcvr_type_list { \
|
||||
### { Unknown 0 } \
|
||||
### { GTPE2_NOT_SUPPORTED 1 } \
|
||||
### { GTXE2 2 } \
|
||||
### { GTHE2_NOT_SUPPORTED 3 } \
|
||||
### { GTZE2_NOT_SUPPORTED 4 } \
|
||||
### { GTHE3 5 } \
|
||||
### { GTYE3_NOT_SUPPORTED 6 } \
|
||||
### { GTRE4_NOT_SUPPORTED 7 } \
|
||||
### { GTHE4 8 } \
|
||||
### { GTYE4 9 } \
|
||||
### { GTME4_NOT_SUPPORTED 10}}
|
||||
### set fpga_voltage_list {0 5000} ;
|
||||
### proc adi_device_spec {cellpath param} {
|
||||
###
|
||||
### set list_pointer [string tolower $param]
|
||||
### set list_pointer [append list_pointer "_list"]
|
||||
###
|
||||
### upvar 1 $list_pointer $list_pointer
|
||||
###
|
||||
### set ip [get_bd_cells $cellpath]
|
||||
### set part [get_property PART [current_project]]
|
||||
###
|
||||
### switch -regexp -- $param {
|
||||
### FPGA_TECHNOLOGY {
|
||||
### switch -regexp -- $part {
|
||||
### ^xc7 {set series_name 7series}
|
||||
### ^xczu {set series_name ultrascale+}
|
||||
### ^xc.u.p {set series_name ultrascale+}
|
||||
### ^xc.u {set series_name ultrascale }
|
||||
### default {
|
||||
### puts "Undefined fpga technology for \"$part\"!"
|
||||
### exit -1
|
||||
### }
|
||||
### }
|
||||
### return "$series_name"
|
||||
### }
|
||||
### FPGA_FAMILY {
|
||||
### set fpga_family [get_property FAMILY $part]
|
||||
### foreach i $fpga_family_list {
|
||||
### regexp ^[lindex $i 0] $fpga_family matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### SPEED_GRADE {
|
||||
### set speed_grade [get_property SPEED $part]
|
||||
### return "$speed_grade"
|
||||
### }
|
||||
### DEV_PACKAGE {
|
||||
### set dev_package [get_property PACKAGE $part]
|
||||
### foreach i $dev_package_list {
|
||||
### regexp ^[lindex $i 0] $dev_package matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### XCVR_TYPE {
|
||||
### set matched ""
|
||||
### set dev_transcivers "none"
|
||||
### foreach x [list_property $part] {
|
||||
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
|
||||
### }
|
||||
### foreach i $xcvr_type_list {
|
||||
### regexp ^[lindex $i 0] $dev_transcivers matched
|
||||
### }
|
||||
### if { $matched eq "" } {
|
||||
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### FPGA_VOLTAGE {
|
||||
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
|
||||
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
|
||||
###
|
||||
### return "$fpga_voltage"
|
||||
### }
|
||||
### default {
|
||||
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
|
||||
### }
|
||||
### }
|
||||
### }
|
||||
## if {![info exists REQUIRED_VIVADO_VERSION]} {
|
||||
## set REQUIRED_VIVADO_VERSION "2019.1"
|
||||
## }
|
||||
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
|
||||
## set IGNORE_VERSION_CHECK 1
|
||||
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
|
||||
## set IGNORE_VERSION_CHECK 0
|
||||
## }
|
||||
## proc adi_ip_ttcl {ip_name ip_constr_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
|
||||
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_sim_ttcl {ip_name ip_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
|
||||
## set f [ipx::add_file $ip_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_bd {ip_name ip_bd_files} {
|
||||
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
|
||||
## if {$proj_filegroup == {}} {
|
||||
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
|
||||
## }
|
||||
##
|
||||
## foreach file $ip_bd_files {
|
||||
## set f [ipx::add_file $file $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type tclSource \
|
||||
## ] $f
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_infer_streaming_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_ip_infer_mm_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
|
||||
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency $port
|
||||
## if {$driver_value != {}} {
|
||||
## set_property DRIVER_VALUE $driver_value $port
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_set_bus_dependency {bus prefix dependency} {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
|
||||
## adi_set_ports_dependency $prefix $dependency 0
|
||||
## }
|
||||
## proc adi_add_port_map {bus phys logic} {
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## }
|
||||
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## adi_add_port_map $bus {*}$port_map
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
|
||||
## for {set i 0} {$i < $num} {incr i} {
|
||||
## set bus_name [format "%s%d" $bus_name_prefix $i]
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## if {$dependency ne ""} {
|
||||
## set bus_dependency [string map [list "{i}" $i] $dependency]
|
||||
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
|
||||
## }
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## lassign $port_map phys logic width width_dep
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
|
||||
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
|
||||
## if {$width_dep ne ""} {
|
||||
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
|
||||
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
|
||||
## set width_dep_r "(($width_dep) * $i)"
|
||||
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
|
||||
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
|
||||
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
|
||||
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
|
||||
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
|
||||
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
|
||||
## set_property display_name $clock_inf_name $clock_inf
|
||||
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
|
||||
## set_property physical_name $clock_signal_name $clock_map
|
||||
##
|
||||
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
|
||||
## set_property value $bus_inf_name $assoc_busif
|
||||
##
|
||||
## if { $reset_signal_name != "" } {
|
||||
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
|
||||
## set_property value $reset_signal_name $assoc_reset
|
||||
##
|
||||
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
|
||||
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
|
||||
## set_property display_name $reset_inf_name $reset_inf
|
||||
## set_property interface_mode $reset_signal_mode $reset_inf
|
||||
## set reset_map [ipx::add_port_map "RST" $reset_inf]
|
||||
## set_property physical_name $reset_signal_name $reset_map
|
||||
##
|
||||
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
|
||||
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
|
||||
## set_property value "ACTIVE_LOW" $reset_polarity
|
||||
## } else {
|
||||
## set_property value "ACTIVE_HIGH" $reset_polarity
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_add_core_dependencies {vlnvs} {
|
||||
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
|
||||
## foreach vlnv $vlnvs {
|
||||
## ipx::add_subcore $vlnv $file_group
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_create {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
## global ad_ghdl_dir
|
||||
## global REQUIRED_VIVADO_VERSION
|
||||
## global IGNORE_VERSION_CHECK
|
||||
##
|
||||
## set VIVADO_VERSION [version -short]
|
||||
## if {$IGNORE_VERSION_CHECK} {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## }
|
||||
## } else {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "ERROR: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
|
||||
## exit 2
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## create_project $ip_name . -force
|
||||
##
|
||||
## ## Load custom message severity definitions
|
||||
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
|
||||
##
|
||||
## set lib_dirs $ad_hdl_dir/library
|
||||
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
|
||||
## lappend lib_dirs $ad_ghdl_dir/library
|
||||
## }
|
||||
##
|
||||
## set_property ip_repo_paths $lib_dirs [current_fileset]
|
||||
## update_ip_catalog
|
||||
## }
|
||||
## proc adi_ip_files {ip_name ip_files} {
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## foreach m_file $ip_files {
|
||||
## if {[file extension $m_file] eq ".xdc"} {
|
||||
## add_files -norecurse -fileset constrs_1 $m_file
|
||||
## } else {
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
|
||||
## }
|
||||
## }
|
||||
## set_property "top" "$ip_name" $proj_fileset
|
||||
## }
|
||||
## proc adi_ip_properties_lite {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
##
|
||||
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
|
||||
##
|
||||
## set_property name $ip_name [ipx::current_core]
|
||||
##
|
||||
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
|
||||
## set_property company_url {http://www.analog.com} [ipx::current_core]
|
||||
##
|
||||
## set i_families ""
|
||||
## foreach i_part [get_parts] {
|
||||
## lappend i_families [get_property FAMILY $i_part]
|
||||
## }
|
||||
## set i_families [lsort -unique $i_families]
|
||||
## set s_families [get_property supported_families [ipx::current_core]]
|
||||
## foreach i_family $i_families {
|
||||
## set s_families "$s_families $i_family Production"
|
||||
## set s_families "$s_families $i_family Beta"
|
||||
## }
|
||||
## set_property supported_families $s_families [ipx::current_core]
|
||||
##
|
||||
## ipx::save_core [ipx::current_core]
|
||||
##
|
||||
## ipx::remove_all_bus_interface [ipx::current_core]
|
||||
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
|
||||
## foreach map $memory_maps {
|
||||
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
|
||||
## }
|
||||
##
|
||||
## ipx::update_checksums [ipx::current_core]
|
||||
## ipx::save_core [ipx::current_core]
|
||||
## }
|
||||
## proc adi_ip_properties {ip_name} {
|
||||
##
|
||||
## adi_ip_properties_lite $ip_name
|
||||
##
|
||||
## ipx::infer_bus_interface {\
|
||||
## s_axi_awvalid \
|
||||
## s_axi_awaddr \
|
||||
## s_axi_awprot \
|
||||
## s_axi_awready \
|
||||
## s_axi_wvalid \
|
||||
## s_axi_wdata \
|
||||
## s_axi_wstrb \
|
||||
## s_axi_wready \
|
||||
## s_axi_bvalid \
|
||||
## s_axi_bresp \
|
||||
##
|
||||
## s_axi_bready \
|
||||
## s_axi_arvalid \
|
||||
## s_axi_araddr \
|
||||
## s_axi_arprot \
|
||||
## s_axi_arready \
|
||||
## s_axi_rvalid \
|
||||
## s_axi_rdata \
|
||||
## s_axi_rresp \
|
||||
## s_axi_rready} \
|
||||
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
|
||||
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
|
||||
##
|
||||
## if {$raddr_width != $waddr_width} {
|
||||
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
|
||||
## set range 65536
|
||||
## } else {
|
||||
## if {$raddr_width >= 16} {
|
||||
## set range 65536
|
||||
## } else {
|
||||
## set range [expr 1 << $raddr_width]
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
## set_property range $range [ipx::get_address_blocks axi_lite \
|
||||
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
|
||||
## ipx::save_core
|
||||
## }
|
||||
## proc adi_init_bd_tcl {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## if { [file exists bd] } {
|
||||
## file delete -force bd
|
||||
## }
|
||||
## file mkdir bd
|
||||
##
|
||||
## set bd_tcl [open "bd/bd.tcl" w]
|
||||
##
|
||||
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
|
||||
## puts $bd_tcl "proc init {cellpath otherInfo} {"
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl ""
|
||||
## set auto_set_param ""
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
|
||||
## puts $bd_tcl $auto_set_param
|
||||
## }
|
||||
##
|
||||
## set auto_set_overwritable_param ""
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_overwritable_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_overwritable_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
|
||||
## puts $bd_tcl $auto_set_overwritable_param
|
||||
## }
|
||||
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
|
||||
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
|
||||
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set parent_dir \"../\""
|
||||
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
|
||||
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
|
||||
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " break"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " append parent_dir \"../\""
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## close $bd_tcl
|
||||
##
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
|
||||
##
|
||||
## set local_mk [open "temporary_case_dependencies.mk" w]
|
||||
## seek $local_mk 0 start
|
||||
## puts $local_mk "CLEAN_TARGET += bd"
|
||||
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
|
||||
## close $local_mk
|
||||
## }
|
||||
## proc adi_add_auto_fpga_spec_params {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_device_spec_param {ip_param} {
|
||||
##
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## set list_pointer [string tolower $ip_param]
|
||||
## set list_pointer [append list_pointer "_list"]
|
||||
##
|
||||
## global $list_pointer
|
||||
##
|
||||
## # set j 1D list from the original list
|
||||
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
|
||||
##
|
||||
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
|
||||
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "range_long" \
|
||||
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
|
||||
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## } else {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "pairs" \
|
||||
## "value_validation_pairs" $j ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## }
|
||||
##
|
||||
## # FPGA info grup
|
||||
## set info_group_name "FPGA info"
|
||||
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
|
||||
## if { [string trim $info_group] eq "" } {
|
||||
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
|
||||
## -parent $page0 -display_name $info_group_name]
|
||||
## }
|
||||
##
|
||||
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
|
||||
## set_property -dict [list "widget" "comboBox" ] $p
|
||||
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
|
||||
## }
|
||||
## proc adi_if_define {name} {
|
||||
##
|
||||
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
|
||||
## ipx::create_bus_definition analog.com interface $name 1.0
|
||||
##
|
||||
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
|
||||
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
|
||||
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
|
||||
##
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## }
|
||||
## proc adi_if_ports {dir width name {type none}} {
|
||||
##
|
||||
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
|
||||
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
|
||||
## set_property master_presence required $m_intf
|
||||
## set_property slave_presence required $m_intf
|
||||
## set_property master_width $width $m_intf
|
||||
## set_property slave_width $width $m_intf
|
||||
##
|
||||
## set m_dir "in"
|
||||
## set s_dir "out"
|
||||
## if {$dir eq "output"} {
|
||||
## set m_dir "out"
|
||||
## set s_dir "in"
|
||||
## }
|
||||
##
|
||||
## set_property master_direction $m_dir $m_intf
|
||||
## set_property slave_direction $s_dir $m_intf
|
||||
##
|
||||
## if {$type ne "none"} {
|
||||
## set_property is_${type} true $m_intf
|
||||
## }
|
||||
##
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## }
|
||||
## proc adi_if_infer_bus {if_name mode name maps} {
|
||||
##
|
||||
## ipx::add_bus_interface $name [ipx::current_core]
|
||||
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
|
||||
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
|
||||
## set_property interface_mode $mode $m_bus_if
|
||||
##
|
||||
## foreach map $maps {
|
||||
## set m_maps [regexp -all -inline {\S+} $map]
|
||||
## lassign $m_maps p_name p_map
|
||||
## ipx::add_port_map $p_name $m_bus_if
|
||||
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
|
||||
## }
|
||||
## }
|
||||
# adi_ip_create jesd204_rx_static_config
|
||||
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
|
||||
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1343} -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1306} -new_severity WARNING
|
||||
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
|
||||
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
|
||||
## set_msg_config -id {Synth 8-3331} -new_severity INFO
|
||||
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
|
||||
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
|
||||
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
|
||||
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx_static_config'.)
|
||||
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
|
||||
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
|
||||
# adi_ip_files jesd204_rx_static_config [list \
|
||||
# "jesd204_rx_static_config.v" \
|
||||
# ]
|
||||
# adi_ip_properties_lite jesd204_rx_static_config
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_reset on bus interface abstraction jesd204_rx_cfg_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_mask on bus interface abstraction jesd204_rx_cfg_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'cfg' of definition 'analog.com:interface:jesd204_rx_cfg:1.0' (from User Repositories).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_lanes_disable' and definition port 'lanes_disable'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_links_disable' and definition port 'links_disable'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_beats_per_multiframe' and definition port 'beats_per_multiframe'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_octets_per_frame' and definition port 'octets_per_frame'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_lmfc_offset' and definition port 'lmfc_offset'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_buffer_early_release' and definition port 'buffer_early_release'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_buffer_delay' and definition port 'buffer_delay'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_disable_char_replacement' and definition port 'disable_char_replacement'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_disable_scrambler' and definition port 'disable_scrambler'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_frame_align_err_threshold' and definition port 'frame_align_err_threshold'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_reset" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_mask" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
# adi_add_bus "rx_cfg" "master" \
|
||||
# "analog.com:interface:jesd204_rx_cfg_rtl:1.0" \
|
||||
# "analog.com:interface:jesd204_rx_cfg:1.0" \
|
||||
# { \
|
||||
# { "cfg_lanes_disable" "lanes_disable" } \
|
||||
# { "cfg_beats_per_multiframe" "beats_per_multiframe" } \
|
||||
# { "cfg_octets_per_frame" "octets_per_frame" } \
|
||||
# { "cfg_lmfc_offset" "lmfc_offset" } \
|
||||
# { "cfg_sysref_oneshot" "sysref_oneshot" } \
|
||||
# { "cfg_sysref_disable" "sysref_disable" } \
|
||||
# { "cfg_buffer_early_release" "buffer_early_release" } \
|
||||
# { "cfg_frame_align_err_threshold" "frame_align_err_threshold" } \
|
||||
# }
|
||||
# adi_add_bus_clock "clk" "rx_cfg"
|
||||
# ipx::save_core [ipx::current_core]
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:17:28 2021...
|
||||
@@ -0,0 +1,70 @@
|
||||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact [email protected] for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create jesd204_rx_static_config
|
||||
adi_ip_files jesd204_rx_static_config [list \
|
||||
"jesd204_rx_static_config.v" \
|
||||
]
|
||||
|
||||
adi_ip_properties_lite jesd204_rx_static_config
|
||||
|
||||
adi_add_bus "rx_cfg" "master" \
|
||||
"analog.com:interface:jesd204_rx_cfg_rtl:1.0" \
|
||||
"analog.com:interface:jesd204_rx_cfg:1.0" \
|
||||
{ \
|
||||
{ "cfg_lanes_disable" "lanes_disable" } \
|
||||
{ "cfg_beats_per_multiframe" "beats_per_multiframe" } \
|
||||
{ "cfg_octets_per_frame" "octets_per_frame" } \
|
||||
{ "cfg_lmfc_offset" "lmfc_offset" } \
|
||||
{ "cfg_sysref_oneshot" "sysref_oneshot" } \
|
||||
{ "cfg_sysref_disable" "sysref_disable" } \
|
||||
{ "cfg_buffer_early_release" "buffer_early_release" } \
|
||||
{ "cfg_frame_align_err_threshold" "frame_align_err_threshold" } \
|
||||
}
|
||||
adi_add_bus_clock "clk" "rx_cfg"
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Thu Dec 9 15:17:21 2021
|
||||
# Process ID: 6777
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx_static_config
|
||||
# Command line: vivado -mode batch -source jesd204_rx_static_config_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx_static_config/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx_static_config/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source jesd204_rx_static_config_ip.tcl
|
||||
@@ -0,0 +1,718 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Thu Dec 9 15:17:21 2021
|
||||
# Process ID: 6777
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx_static_config
|
||||
# Command line: vivado -mode batch -source jesd204_rx_static_config_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx_static_config/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx_static_config/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source jesd204_rx_static_config_ip.tcl
|
||||
# source ../../scripts/adi_env.tcl
|
||||
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
|
||||
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
|
||||
## if [info exists ::env(ADI_HDL_DIR)] {
|
||||
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
|
||||
## }
|
||||
## if [info exists ::env(ADI_GHDL_DIR)] {
|
||||
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
|
||||
## }
|
||||
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
|
||||
### variable auto_set_param_list
|
||||
### variable auto_set_param_list_overwritable
|
||||
### variable fpga_series_list
|
||||
### variable fpga_family_list
|
||||
### variable speed_grade_list
|
||||
### variable dev_package_list
|
||||
### variable xcvr_type_list
|
||||
### variable fpga_voltage_list
|
||||
### set auto_set_param_list { \
|
||||
### DEV_PACKAGE \
|
||||
### SPEED_GRADE \
|
||||
### FPGA_FAMILY \
|
||||
### FPGA_TECHNOLOGY }
|
||||
### set auto_set_param_list_overwritable { \
|
||||
### FPGA_VOLTAGE \
|
||||
### XCVR_TYPE }
|
||||
### set fpga_technology_list { \
|
||||
### { Unknown 0 } \
|
||||
### { 7series 1 } \
|
||||
### { ultrascale 2 } \
|
||||
### { ultrascale+ 3 }}
|
||||
### set fpga_family_list { \
|
||||
### { Unknown 0 } \
|
||||
### { artix 1 } \
|
||||
### { kintex 2 } \
|
||||
### { virtex 3 } \
|
||||
### { zynq 4 }}
|
||||
### set speed_grade_list { \
|
||||
### { Unknown 0 } \
|
||||
### { -1 10 } \
|
||||
### { -1L 11 } \
|
||||
### { -1H 12 } \
|
||||
### { -1HV 13 } \
|
||||
### { -1LV 14 } \
|
||||
### { -2 20 } \
|
||||
### { -2L 21 } \
|
||||
### { -2LV 22 } \
|
||||
### { -3 30 }}
|
||||
### set dev_package_list { \
|
||||
### { Unknown 0 } \
|
||||
### { rf 1 } \
|
||||
### { fl 2 } \
|
||||
### { ff 3 } \
|
||||
### { fb 4 } \
|
||||
### { hc 5 } \
|
||||
### { fh 6 } \
|
||||
### { cs 7 } \
|
||||
### { cp 8 } \
|
||||
### { ft 9 } \
|
||||
### { fg 10 } \
|
||||
### { sb 11 } \
|
||||
### { rb 12 } \
|
||||
### { rs 13 } \
|
||||
### { cl 14 } \
|
||||
### { sf 15 } \
|
||||
### { ba 16 } \
|
||||
### { fa 17 } \
|
||||
### { fs 18 } \
|
||||
### { fi 19 }}
|
||||
### set xcvr_type_list { \
|
||||
### { Unknown 0 } \
|
||||
### { GTPE2_NOT_SUPPORTED 1 } \
|
||||
### { GTXE2 2 } \
|
||||
### { GTHE2_NOT_SUPPORTED 3 } \
|
||||
### { GTZE2_NOT_SUPPORTED 4 } \
|
||||
### { GTHE3 5 } \
|
||||
### { GTYE3_NOT_SUPPORTED 6 } \
|
||||
### { GTRE4_NOT_SUPPORTED 7 } \
|
||||
### { GTHE4 8 } \
|
||||
### { GTYE4 9 } \
|
||||
### { GTME4_NOT_SUPPORTED 10}}
|
||||
### set fpga_voltage_list {0 5000} ;
|
||||
### proc adi_device_spec {cellpath param} {
|
||||
###
|
||||
### set list_pointer [string tolower $param]
|
||||
### set list_pointer [append list_pointer "_list"]
|
||||
###
|
||||
### upvar 1 $list_pointer $list_pointer
|
||||
###
|
||||
### set ip [get_bd_cells $cellpath]
|
||||
### set part [get_property PART [current_project]]
|
||||
###
|
||||
### switch -regexp -- $param {
|
||||
### FPGA_TECHNOLOGY {
|
||||
### switch -regexp -- $part {
|
||||
### ^xc7 {set series_name 7series}
|
||||
### ^xczu {set series_name ultrascale+}
|
||||
### ^xc.u.p {set series_name ultrascale+}
|
||||
### ^xc.u {set series_name ultrascale }
|
||||
### default {
|
||||
### puts "Undefined fpga technology for \"$part\"!"
|
||||
### exit -1
|
||||
### }
|
||||
### }
|
||||
### return "$series_name"
|
||||
### }
|
||||
### FPGA_FAMILY {
|
||||
### set fpga_family [get_property FAMILY $part]
|
||||
### foreach i $fpga_family_list {
|
||||
### regexp ^[lindex $i 0] $fpga_family matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### SPEED_GRADE {
|
||||
### set speed_grade [get_property SPEED $part]
|
||||
### return "$speed_grade"
|
||||
### }
|
||||
### DEV_PACKAGE {
|
||||
### set dev_package [get_property PACKAGE $part]
|
||||
### foreach i $dev_package_list {
|
||||
### regexp ^[lindex $i 0] $dev_package matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### XCVR_TYPE {
|
||||
### set matched ""
|
||||
### set dev_transcivers "none"
|
||||
### foreach x [list_property $part] {
|
||||
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
|
||||
### }
|
||||
### foreach i $xcvr_type_list {
|
||||
### regexp ^[lindex $i 0] $dev_transcivers matched
|
||||
### }
|
||||
### if { $matched eq "" } {
|
||||
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### FPGA_VOLTAGE {
|
||||
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
|
||||
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
|
||||
###
|
||||
### return "$fpga_voltage"
|
||||
### }
|
||||
### default {
|
||||
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
|
||||
### }
|
||||
### }
|
||||
### }
|
||||
## if {![info exists REQUIRED_VIVADO_VERSION]} {
|
||||
## set REQUIRED_VIVADO_VERSION "2019.1"
|
||||
## }
|
||||
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
|
||||
## set IGNORE_VERSION_CHECK 1
|
||||
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
|
||||
## set IGNORE_VERSION_CHECK 0
|
||||
## }
|
||||
## proc adi_ip_ttcl {ip_name ip_constr_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
|
||||
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_sim_ttcl {ip_name ip_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
|
||||
## set f [ipx::add_file $ip_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_bd {ip_name ip_bd_files} {
|
||||
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
|
||||
## if {$proj_filegroup == {}} {
|
||||
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
|
||||
## }
|
||||
##
|
||||
## foreach file $ip_bd_files {
|
||||
## set f [ipx::add_file $file $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type tclSource \
|
||||
## ] $f
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_infer_streaming_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_ip_infer_mm_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
|
||||
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency $port
|
||||
## if {$driver_value != {}} {
|
||||
## set_property DRIVER_VALUE $driver_value $port
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_set_bus_dependency {bus prefix dependency} {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
|
||||
## adi_set_ports_dependency $prefix $dependency 0
|
||||
## }
|
||||
## proc adi_add_port_map {bus phys logic} {
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## }
|
||||
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## adi_add_port_map $bus {*}$port_map
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
|
||||
## for {set i 0} {$i < $num} {incr i} {
|
||||
## set bus_name [format "%s%d" $bus_name_prefix $i]
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## if {$dependency ne ""} {
|
||||
## set bus_dependency [string map [list "{i}" $i] $dependency]
|
||||
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
|
||||
## }
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## lassign $port_map phys logic width width_dep
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
|
||||
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
|
||||
## if {$width_dep ne ""} {
|
||||
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
|
||||
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
|
||||
## set width_dep_r "(($width_dep) * $i)"
|
||||
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
|
||||
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
|
||||
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
|
||||
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
|
||||
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
|
||||
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
|
||||
## set_property display_name $clock_inf_name $clock_inf
|
||||
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
|
||||
## set_property physical_name $clock_signal_name $clock_map
|
||||
##
|
||||
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
|
||||
## set_property value $bus_inf_name $assoc_busif
|
||||
##
|
||||
## if { $reset_signal_name != "" } {
|
||||
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
|
||||
## set_property value $reset_signal_name $assoc_reset
|
||||
##
|
||||
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
|
||||
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
|
||||
## set_property display_name $reset_inf_name $reset_inf
|
||||
## set_property interface_mode $reset_signal_mode $reset_inf
|
||||
## set reset_map [ipx::add_port_map "RST" $reset_inf]
|
||||
## set_property physical_name $reset_signal_name $reset_map
|
||||
##
|
||||
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
|
||||
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
|
||||
## set_property value "ACTIVE_LOW" $reset_polarity
|
||||
## } else {
|
||||
## set_property value "ACTIVE_HIGH" $reset_polarity
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_add_core_dependencies {vlnvs} {
|
||||
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
|
||||
## foreach vlnv $vlnvs {
|
||||
## ipx::add_subcore $vlnv $file_group
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_create {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
## global ad_ghdl_dir
|
||||
## global REQUIRED_VIVADO_VERSION
|
||||
## global IGNORE_VERSION_CHECK
|
||||
##
|
||||
## set VIVADO_VERSION [version -short]
|
||||
## if {$IGNORE_VERSION_CHECK} {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## }
|
||||
## } else {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "ERROR: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
|
||||
## exit 2
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## create_project $ip_name . -force
|
||||
##
|
||||
## ## Load custom message severity definitions
|
||||
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
|
||||
##
|
||||
## set lib_dirs $ad_hdl_dir/library
|
||||
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
|
||||
## lappend lib_dirs $ad_ghdl_dir/library
|
||||
## }
|
||||
##
|
||||
## set_property ip_repo_paths $lib_dirs [current_fileset]
|
||||
## update_ip_catalog
|
||||
## }
|
||||
## proc adi_ip_files {ip_name ip_files} {
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## foreach m_file $ip_files {
|
||||
## if {[file extension $m_file] eq ".xdc"} {
|
||||
## add_files -norecurse -fileset constrs_1 $m_file
|
||||
## } else {
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
|
||||
## }
|
||||
## }
|
||||
## set_property "top" "$ip_name" $proj_fileset
|
||||
## }
|
||||
## proc adi_ip_properties_lite {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
##
|
||||
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
|
||||
##
|
||||
## set_property name $ip_name [ipx::current_core]
|
||||
##
|
||||
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
|
||||
## set_property company_url {http://www.analog.com} [ipx::current_core]
|
||||
##
|
||||
## set i_families ""
|
||||
## foreach i_part [get_parts] {
|
||||
## lappend i_families [get_property FAMILY $i_part]
|
||||
## }
|
||||
## set i_families [lsort -unique $i_families]
|
||||
## set s_families [get_property supported_families [ipx::current_core]]
|
||||
## foreach i_family $i_families {
|
||||
## set s_families "$s_families $i_family Production"
|
||||
## set s_families "$s_families $i_family Beta"
|
||||
## }
|
||||
## set_property supported_families $s_families [ipx::current_core]
|
||||
##
|
||||
## ipx::save_core [ipx::current_core]
|
||||
##
|
||||
## ipx::remove_all_bus_interface [ipx::current_core]
|
||||
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
|
||||
## foreach map $memory_maps {
|
||||
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
|
||||
## }
|
||||
##
|
||||
## ipx::update_checksums [ipx::current_core]
|
||||
## ipx::save_core [ipx::current_core]
|
||||
## }
|
||||
## proc adi_ip_properties {ip_name} {
|
||||
##
|
||||
## adi_ip_properties_lite $ip_name
|
||||
##
|
||||
## ipx::infer_bus_interface {\
|
||||
## s_axi_awvalid \
|
||||
## s_axi_awaddr \
|
||||
## s_axi_awprot \
|
||||
## s_axi_awready \
|
||||
## s_axi_wvalid \
|
||||
## s_axi_wdata \
|
||||
## s_axi_wstrb \
|
||||
## s_axi_wready \
|
||||
## s_axi_bvalid \
|
||||
## s_axi_bresp \
|
||||
##
|
||||
## s_axi_bready \
|
||||
## s_axi_arvalid \
|
||||
## s_axi_araddr \
|
||||
## s_axi_arprot \
|
||||
## s_axi_arready \
|
||||
## s_axi_rvalid \
|
||||
## s_axi_rdata \
|
||||
## s_axi_rresp \
|
||||
## s_axi_rready} \
|
||||
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
|
||||
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
|
||||
##
|
||||
## if {$raddr_width != $waddr_width} {
|
||||
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
|
||||
## set range 65536
|
||||
## } else {
|
||||
## if {$raddr_width >= 16} {
|
||||
## set range 65536
|
||||
## } else {
|
||||
## set range [expr 1 << $raddr_width]
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
## set_property range $range [ipx::get_address_blocks axi_lite \
|
||||
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
|
||||
## ipx::save_core
|
||||
## }
|
||||
## proc adi_init_bd_tcl {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## if { [file exists bd] } {
|
||||
## file delete -force bd
|
||||
## }
|
||||
## file mkdir bd
|
||||
##
|
||||
## set bd_tcl [open "bd/bd.tcl" w]
|
||||
##
|
||||
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
|
||||
## puts $bd_tcl "proc init {cellpath otherInfo} {"
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl ""
|
||||
## set auto_set_param ""
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
|
||||
## puts $bd_tcl $auto_set_param
|
||||
## }
|
||||
##
|
||||
## set auto_set_overwritable_param ""
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_overwritable_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_overwritable_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
|
||||
## puts $bd_tcl $auto_set_overwritable_param
|
||||
## }
|
||||
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
|
||||
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
|
||||
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set parent_dir \"../\""
|
||||
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
|
||||
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
|
||||
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " break"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " append parent_dir \"../\""
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## close $bd_tcl
|
||||
##
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
|
||||
##
|
||||
## set local_mk [open "temporary_case_dependencies.mk" w]
|
||||
## seek $local_mk 0 start
|
||||
## puts $local_mk "CLEAN_TARGET += bd"
|
||||
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
|
||||
## close $local_mk
|
||||
## }
|
||||
## proc adi_add_auto_fpga_spec_params {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_device_spec_param {ip_param} {
|
||||
##
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## set list_pointer [string tolower $ip_param]
|
||||
## set list_pointer [append list_pointer "_list"]
|
||||
##
|
||||
## global $list_pointer
|
||||
##
|
||||
## # set j 1D list from the original list
|
||||
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
|
||||
##
|
||||
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
|
||||
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "range_long" \
|
||||
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
|
||||
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## } else {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "pairs" \
|
||||
## "value_validation_pairs" $j ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## }
|
||||
##
|
||||
## # FPGA info grup
|
||||
## set info_group_name "FPGA info"
|
||||
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
|
||||
## if { [string trim $info_group] eq "" } {
|
||||
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
|
||||
## -parent $page0 -display_name $info_group_name]
|
||||
## }
|
||||
##
|
||||
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
|
||||
## set_property -dict [list "widget" "comboBox" ] $p
|
||||
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
|
||||
## }
|
||||
## proc adi_if_define {name} {
|
||||
##
|
||||
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
|
||||
## ipx::create_bus_definition analog.com interface $name 1.0
|
||||
##
|
||||
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
|
||||
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
|
||||
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
|
||||
##
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## }
|
||||
## proc adi_if_ports {dir width name {type none}} {
|
||||
##
|
||||
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
|
||||
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
|
||||
## set_property master_presence required $m_intf
|
||||
## set_property slave_presence required $m_intf
|
||||
## set_property master_width $width $m_intf
|
||||
## set_property slave_width $width $m_intf
|
||||
##
|
||||
## set m_dir "in"
|
||||
## set s_dir "out"
|
||||
## if {$dir eq "output"} {
|
||||
## set m_dir "out"
|
||||
## set s_dir "in"
|
||||
## }
|
||||
##
|
||||
## set_property master_direction $m_dir $m_intf
|
||||
## set_property slave_direction $s_dir $m_intf
|
||||
##
|
||||
## if {$type ne "none"} {
|
||||
## set_property is_${type} true $m_intf
|
||||
## }
|
||||
##
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## }
|
||||
## proc adi_if_infer_bus {if_name mode name maps} {
|
||||
##
|
||||
## ipx::add_bus_interface $name [ipx::current_core]
|
||||
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
|
||||
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
|
||||
## set_property interface_mode $mode $m_bus_if
|
||||
##
|
||||
## foreach map $maps {
|
||||
## set m_maps [regexp -all -inline {\S+} $map]
|
||||
## lassign $m_maps p_name p_map
|
||||
## ipx::add_port_map $p_name $m_bus_if
|
||||
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
|
||||
## }
|
||||
## }
|
||||
# adi_ip_create jesd204_rx_static_config
|
||||
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
|
||||
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1343} -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1306} -new_severity WARNING
|
||||
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
|
||||
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
|
||||
## set_msg_config -id {Synth 8-3331} -new_severity INFO
|
||||
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
|
||||
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
|
||||
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
|
||||
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_rx_static_config'.)
|
||||
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
|
||||
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
|
||||
# adi_ip_files jesd204_rx_static_config [list \
|
||||
# "jesd204_rx_static_config.v" \
|
||||
# ]
|
||||
# adi_ip_properties_lite jesd204_rx_static_config
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_reset on bus interface abstraction jesd204_rx_cfg_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port err_statistics_mask on bus interface abstraction jesd204_rx_cfg_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'cfg' of definition 'analog.com:interface:jesd204_rx_cfg:1.0' (from User Repositories).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_lanes_disable' and definition port 'lanes_disable'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_links_disable' and definition port 'links_disable'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_beats_per_multiframe' and definition port 'beats_per_multiframe'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_octets_per_frame' and definition port 'octets_per_frame'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_lmfc_offset' and definition port 'lmfc_offset'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_buffer_early_release' and definition port 'buffer_early_release'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_buffer_delay' and definition port 'buffer_delay'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_disable_char_replacement' and definition port 'disable_char_replacement'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_disable_scrambler' and definition port 'disable_scrambler'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cfg_frame_align_err_threshold' and definition port 'frame_align_err_threshold'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_reset" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_mask" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
# adi_add_bus "rx_cfg" "master" \
|
||||
# "analog.com:interface:jesd204_rx_cfg_rtl:1.0" \
|
||||
# "analog.com:interface:jesd204_rx_cfg:1.0" \
|
||||
# { \
|
||||
# { "cfg_lanes_disable" "lanes_disable" } \
|
||||
# { "cfg_beats_per_multiframe" "beats_per_multiframe" } \
|
||||
# { "cfg_octets_per_frame" "octets_per_frame" } \
|
||||
# { "cfg_lmfc_offset" "lmfc_offset" } \
|
||||
# { "cfg_sysref_oneshot" "sysref_oneshot" } \
|
||||
# { "cfg_sysref_disable" "sysref_disable" } \
|
||||
# { "cfg_buffer_early_release" "buffer_early_release" } \
|
||||
# { "cfg_frame_align_err_threshold" "frame_align_err_threshold" } \
|
||||
# }
|
||||
# adi_add_bus_clock "clk" "rx_cfg"
|
||||
# ipx::save_core [ipx::current_core]
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:17:28 2021...
|
||||
@@ -0,0 +1,115 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "BUFFER_EARLY_RELEASE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "FRAMES_PER_MULTIFRAME" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "LINK_MODE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "NUM_LANES" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "NUM_LINKS" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "OCTETS_PER_FRAME" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "SCR" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.BUFFER_EARLY_RELEASE { PARAM_VALUE.BUFFER_EARLY_RELEASE } {
|
||||
# Procedure called to update BUFFER_EARLY_RELEASE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.BUFFER_EARLY_RELEASE { PARAM_VALUE.BUFFER_EARLY_RELEASE } {
|
||||
# Procedure called to validate BUFFER_EARLY_RELEASE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FRAMES_PER_MULTIFRAME { PARAM_VALUE.FRAMES_PER_MULTIFRAME } {
|
||||
# Procedure called to update FRAMES_PER_MULTIFRAME when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FRAMES_PER_MULTIFRAME { PARAM_VALUE.FRAMES_PER_MULTIFRAME } {
|
||||
# Procedure called to validate FRAMES_PER_MULTIFRAME
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } {
|
||||
# Procedure called to update LINK_MODE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } {
|
||||
# Procedure called to validate LINK_MODE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
|
||||
# Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
|
||||
# Procedure called to validate NUM_LANES
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } {
|
||||
# Procedure called to update NUM_LINKS when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } {
|
||||
# Procedure called to validate NUM_LINKS
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.OCTETS_PER_FRAME { PARAM_VALUE.OCTETS_PER_FRAME } {
|
||||
# Procedure called to update OCTETS_PER_FRAME when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.OCTETS_PER_FRAME { PARAM_VALUE.OCTETS_PER_FRAME } {
|
||||
# Procedure called to validate OCTETS_PER_FRAME
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SCR { PARAM_VALUE.SCR } {
|
||||
# Procedure called to update SCR when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SCR { PARAM_VALUE.SCR } {
|
||||
# Procedure called to validate SCR
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_LINKS { MODELPARAM_VALUE.NUM_LINKS PARAM_VALUE.NUM_LINKS } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_LINKS}] ${MODELPARAM_VALUE.NUM_LINKS}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.OCTETS_PER_FRAME { MODELPARAM_VALUE.OCTETS_PER_FRAME PARAM_VALUE.OCTETS_PER_FRAME } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.OCTETS_PER_FRAME}] ${MODELPARAM_VALUE.OCTETS_PER_FRAME}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FRAMES_PER_MULTIFRAME { MODELPARAM_VALUE.FRAMES_PER_MULTIFRAME PARAM_VALUE.FRAMES_PER_MULTIFRAME } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FRAMES_PER_MULTIFRAME}] ${MODELPARAM_VALUE.FRAMES_PER_MULTIFRAME}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SCR { MODELPARAM_VALUE.SCR PARAM_VALUE.SCR } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SCR}] ${MODELPARAM_VALUE.SCR}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.BUFFER_EARLY_RELEASE { MODELPARAM_VALUE.BUFFER_EARLY_RELEASE PARAM_VALUE.BUFFER_EARLY_RELEASE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.BUFFER_EARLY_RELEASE}] ${MODELPARAM_VALUE.BUFFER_EARLY_RELEASE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.LINK_MODE { MODELPARAM_VALUE.LINK_MODE PARAM_VALUE.LINK_MODE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.LINK_MODE}] ${MODELPARAM_VALUE.LINK_MODE}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user