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adi_library/jesd204/jesd204_soft_pcs_tx/.timestamp_intel
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adi_library/jesd204/jesd204_soft_pcs_tx/Makefile
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := jesd204_soft_pcs_tx
GENERIC_DEPS += jesd204_8b10b_encoder.v
GENERIC_DEPS += jesd204_soft_pcs_tx.v
INTEL_DEPS += jesd204_soft_pcs_tx_hw.tcl
include ../../scripts/library.mk
adi_library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v
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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
`timescale 1ns/100ps
module jesd204_8b10b_encoder (
input in_disparity,
input [7:0] in_char,
input in_charisk,
output [9:0] out_char,
output out_disparity
);
/*
* Only supports the subset of 8b10b that is used by JESD204.
* If non-supported control characters are supplied the output is undefined.
*/
reg [5:0] data6b;
reg [5:0] out6b;
reg may_invert6b;
reg disparity6b;
reg [3:0] data4b;
reg [3:0] out4b;
reg may_invert4b;
reg disparity4b;
wire disparity4b_in;
reg alt7;
always @(*) begin
if (in_charisk == 1'b1) begin
// Assume K28.x
data6b = 6'b000011;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end else begin
case (in_char[4:0])
5'd00: begin
data6b = 6'b000110;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd01: begin
data6b = 6'b010001;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd02: begin
data6b = 6'b010010;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd03: begin
data6b = 6'b100011;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd04: begin
data6b = 6'b010100;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd05: begin
data6b = 6'b100101;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd06: begin
data6b = 6'b100110;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd07: begin
data6b = 6'b111000;
may_invert6b = 1'b1;
disparity6b = 1'b0;
end
5'd08: begin
data6b = 6'b011000;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd09: begin
data6b = 6'b101001;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd10: begin
data6b = 6'b101010;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd11: begin
data6b = 6'b001011;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd12: begin
data6b = 6'b101100;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd13: begin
data6b = 6'b001101;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd14: begin
data6b = 6'b001110;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd15: begin
data6b = 6'b000101;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd16: begin
data6b = 6'b001001;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd17: begin
data6b = 6'b110001;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd18: begin
data6b = 6'b110010;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd19: begin
data6b = 6'b010011;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd20: begin
data6b = 6'b110100;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd21: begin
data6b = 6'b010101;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd22: begin
data6b = 6'b010110;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd23: begin
data6b = 6'b101000;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd24: begin
data6b = 6'b001100;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd25: begin
data6b = 6'b011001;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd26: begin
data6b = 6'b011010;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd27: begin
data6b = 6'b100100;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd28: begin
data6b = 6'b011100;
may_invert6b = 1'b0;
disparity6b = 1'b0;
end
5'd29: begin
data6b = 6'b100010;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
5'd30: begin
data6b = 6'b100001;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
default: begin
data6b = 6'b001010;
may_invert6b = 1'b1;
disparity6b = 1'b1;
end
endcase
end
end
always @(*) begin
if (in_charisk == 1'b1) begin
alt7 = 1'b1;
end else begin
// case (in_char[4:0])
// 5'd11, 5'd13, 5'd14: alt7 = in_disparity;
// 5'd17, 5'd18, 5'd20: alt7 = ~in_disparity;
// default: alt7 = 1'b0;
// endcase
// Slightly better packing
case ({may_invert6b,data6b[5:4]})
3'b000: alt7 = in_disparity;
3'b011: alt7 = ~in_disparity;
default: alt7 = 1'b0;
endcase
end
end
always @(*) begin
case (in_char[7:5])
3'd0: begin
data4b = 4'b0010;
may_invert4b = 1'b1;
disparity4b = 1'b1;
end
3'd1: begin
data4b = 4'b1001;
may_invert4b = in_charisk;
disparity4b = 1'b0;
end
3'd2: begin
data4b = 4'b1010;
may_invert4b = in_charisk;
disparity4b = 1'b0;
end
3'd3: begin
data4b = 4'b1100;
may_invert4b = 1'b1;
disparity4b = 1'b0;
end
3'd4: begin
data4b = 4'b0100;
may_invert4b = 1'b1;
disparity4b = 1'b1;
end
3'd5: begin
data4b = 4'b0101;
may_invert4b = in_charisk;
disparity4b = 1'b0;
end
3'd6: begin
data4b = 4'b0110;
may_invert4b = in_charisk;
disparity4b = 1'b0;
end
default: begin
if (alt7 == 1'b1) begin
data4b = 4'b0001;
end else begin
data4b = 4'b1000;
end
may_invert4b = 1'b1;
disparity4b = 1'b1;
end
endcase
end
assign disparity4b_in = in_disparity ^ disparity6b;
assign out_disparity = disparity4b_in ^ disparity4b;
always @(*) begin
if (in_disparity == 1'b0 && may_invert6b == 1'b1) begin
out6b = ~data6b;
end else begin
out6b = data6b;
end
if (disparity4b_in == 1'b0 && may_invert4b == 1'b1) begin
out4b = ~data4b;
end else begin
out4b = data4b;
end
end
assign out_char = {out4b,out6b};
endmodule
adi_library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v
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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
`timescale 1ns/100ps
module jesd204_soft_pcs_tx #(
parameter NUM_LANES = 1,
parameter DATA_PATH_WIDTH = 4,
parameter INVERT_OUTPUTS = 0
) (
input clk,
input reset,
input [NUM_LANES*DATA_PATH_WIDTH*8-1:0] char,
input [NUM_LANES*DATA_PATH_WIDTH-1:0] charisk,
output reg [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data
);
reg [NUM_LANES-1:0] disparity = 'h00;
wire [DATA_PATH_WIDTH:0] disparity_chain[0:NUM_LANES-1];
wire [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data_s;
always @(posedge clk) begin
data <= INVERT_OUTPUTS ? ~data_s : data_s;
end
generate
genvar lane;
genvar i;
for (lane = 0; lane < NUM_LANES; lane = lane + 1) begin: gen_lane
assign disparity_chain[lane][0] = disparity[lane];
always @(posedge clk) begin
if (reset == 1'b1) begin
disparity[lane] <= 1'b0;
end else begin
disparity[lane] <= disparity_chain[lane][DATA_PATH_WIDTH];
end
end
for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_dpw
localparam j = DATA_PATH_WIDTH * lane + i;
jesd204_8b10b_encoder i_enc (
.in_char(char[j*8+:8]),
.in_charisk(charisk[j]),
.out_char(data_s[j*10+:10]),
.in_disparity(disparity_chain[lane][i]),
.out_disparity(disparity_chain[lane][i+1])
);
end
end
endgenerate
endmodule
adi_library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl
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#
# The ADI JESD204 Core is released under the following license, which is
# different than all other HDL cores in this repository.
#
# Please read this, and understand the freedoms and responsibilities you have
# by using this source code/core.
#
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
#
# This core is free software, you can use run, copy, study, change, ask
# questions about and improve this core. Distribution of source, or resulting
# binaries (including those inside an FPGA or ASIC) require you to release the
# source of the entire project (excluding the system libraries provide by the
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License version 2
# along with this source code, and binary. If not, see
# <http://www.gnu.org/licenses/>.
#
# Commercial licenses (with commercial support) of this JESD204 core are also
# available under terms different than the General Public License. (e.g. they
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
# core with any corresponding source code.) For these alternate terms you must
# purchase a license from Analog Devices Technology Licensing Office. Users
# interested in such a license should contact [email protected] for
# more information. This commercial license is sub-licensable (if you purchase
# chips from Analog Devices, incorporate them into your PCB level product, and
# purchase a JESD204 license, end users of your product will also have a
# license to use this core in a commercial setting without releasing their
# source code).
#
# In addition, we kindly ask you to acknowledge ADI in any program, application
# or publication in which you use this JESD204 HDL core. (You are not required
# to do so; it is up to your common sense to decide whether you want to comply
# with this request or not.) For general publications, we suggest referencing :
# “The design and implementation of the JESD204 HDL Core used in this project
# is copyright © 2016-2017, Analog Devices, Inc.”
#
package require qsys
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
ad_ip_create jesd204_soft_pcs_tx "ADI JESD204 Transmit Soft PCS"
set_module_property INTERNAL true
ad_ip_parameter INVERT_OUTPUTS INTEGER 0
# files
ad_ip_files jesd204_soft_pcs_tx [list \
jesd204_soft_pcs_tx.v \
jesd204_8b10b_encoder.v \
]
# clock
add_interface clock clock end
add_interface_port clock clk clk Input 1
# reset
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
add_interface_port reset reset reset Input 1
# interfaces
add_interface tx_phy conduit start
#set_interface_property tx_phy associatedClock clock
#set_interface_property tx_phy associatedReset reset
add_interface_port tx_phy char char Input 32
add_interface_port tx_phy charisk charisk Input 4
add_interface tx_raw_data conduit end
#set_interface_property data associatedClock clock
#set_interface_property data associatedReset reset
add_interface_port tx_raw_data data raw_data Output 40