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josh
2023-03-18 15:35:53 +08:00
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adi_library/jesd204/jesd204_tx/Makefile
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := jesd204_tx
GENERIC_DEPS += jesd204_tx.v
GENERIC_DEPS += jesd204_tx_ctrl.v
GENERIC_DEPS += jesd204_tx_lane.v
XILINX_DEPS += jesd204_tx_constr.ttcl
XILINX_DEPS += jesd204_tx_header.v
XILINX_DEPS += jesd204_tx_ip.tcl
XILINX_DEPS += jesd204_tx_lane_64b.v
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_event.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_event_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_status.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_status_rtl.xml
XILINX_LIB_DEPS += jesd204/jesd204_common
XILINX_LIB_DEPS += util_cdc
XILINX_INTERFACE_DEPS += jesd204/interfaces
INTEL_DEPS += ../../util_cdc/sync_bits.v
INTEL_DEPS += ../jesd204_common/jesd204_eof_generator.v
INTEL_DEPS += ../jesd204_common/jesd204_lmfc.v
INTEL_DEPS += ../jesd204_common/jesd204_scrambler.v
INTEL_DEPS += ../jesd204_common/pipeline_stage.v
INTEL_DEPS += jesd204_tx_constr.sdc
INTEL_DEPS += jesd204_tx_hw.tcl
include ../../scripts/library.mk
adi_library/jesd204/jesd204_tx/component.xml
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adi_library/jesd204/jesd204_tx/gui/jesd204_tx_v1_0.gtcl
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# This file is automatically written. Do not modify.
proc gen_USERPARAMETER_DATA_PATH_WIDTH_VALUE {LINK_MODE } {expr $LINK_MODE*4}
adi_library/jesd204/jesd204_tx/jesd204_tx.cache/wt/project.wpc
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version:1
6d6f64655f636f756e7465727c42617463684d6f6465:1
eof:
adi_library/jesd204/jesd204_tx/jesd204_tx.hw/jesd204_tx.lpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
adi_library/jesd204/jesd204_tx/jesd204_tx.v
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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
`timescale 1ns/100ps
module jesd204_tx #(
parameter NUM_LANES = 1,
parameter NUM_LINKS = 1,
parameter NUM_OUTPUT_PIPELINE = 0,
parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
/* Only 4 is supported at the moment for 8b/10b and 8 for 64b */
parameter DATA_PATH_WIDTH = LINK_MODE[1] ? 8 : 4
) (
input clk,
input reset,
output [DATA_PATH_WIDTH*8*NUM_LANES-1:0] phy_data,
output [DATA_PATH_WIDTH*NUM_LANES-1:0] phy_charisk,
output [2*NUM_LANES-1:0] phy_header,
input sysref,
output lmfc_edge,
output lmfc_clk,
input [NUM_LINKS-1:0] sync,
input [DATA_PATH_WIDTH*8*NUM_LANES-1:0] tx_data,
output tx_ready,
input tx_valid,
input [NUM_LANES-1:0] cfg_lanes_disable,
input [NUM_LINKS-1:0] cfg_links_disable,
input [7:0] cfg_beats_per_multiframe,
input [7:0] cfg_octets_per_frame,
input [7:0] cfg_lmfc_offset,
input cfg_sysref_oneshot,
input cfg_sysref_disable,
input cfg_continuous_cgs,
input cfg_continuous_ilas,
input cfg_skip_ilas,
input [7:0] cfg_mframes_per_ilas,
input cfg_disable_char_replacement,
input cfg_disable_scrambler,
output ilas_config_rd,
output [1:0] ilas_config_addr,
input [32*NUM_LANES-1:0] ilas_config_data,
input ctrl_manual_sync_request,
output event_sysref_edge,
output event_sysref_alignment_error,
output [NUM_LINKS-1:0] status_sync,
output [1:0] status_state
);
localparam MAX_OCTETS_PER_FRAME = 8;
localparam MAX_OCTETS_PER_MULTIFRAME =
(MAX_OCTETS_PER_FRAME * 32) > 1024 ? 1024 : (MAX_OCTETS_PER_FRAME * 32);
localparam MAX_BEATS_PER_MULTIFRAME = MAX_OCTETS_PER_MULTIFRAME / DATA_PATH_WIDTH;
localparam LMFC_COUNTER_WIDTH = MAX_BEATS_PER_MULTIFRAME > 256 ? 9 :
MAX_BEATS_PER_MULTIFRAME > 128 ? 8 :
MAX_BEATS_PER_MULTIFRAME > 64 ? 7 :
MAX_BEATS_PER_MULTIFRAME > 32 ? 6 :
MAX_BEATS_PER_MULTIFRAME > 16 ? 5 :
MAX_BEATS_PER_MULTIFRAME > 8 ? 4 :
MAX_BEATS_PER_MULTIFRAME > 4 ? 3 :
MAX_BEATS_PER_MULTIFRAME > 2 ? 2 : 1;
localparam DW = DATA_PATH_WIDTH * 8 * NUM_LANES;
localparam CW = DATA_PATH_WIDTH * NUM_LANES;
localparam HW = 2 * NUM_LANES;
wire [DW-1:0] phy_data_r;
wire [CW-1:0] phy_charisk_r;
wire [HW-1:0] phy_header_r;
wire lmc_edge;
wire lmc_quarter_edge;
wire eoemb;
jesd204_lmfc i_lmfc (
.clk(clk),
.reset(reset),
.cfg_beats_per_multiframe(cfg_beats_per_multiframe),
.cfg_lmfc_offset(cfg_lmfc_offset),
.cfg_sysref_oneshot(cfg_sysref_oneshot),
.cfg_sysref_disable(cfg_sysref_disable),
.sysref(sysref),
.sysref_edge(event_sysref_edge),
.sysref_alignment_error(event_sysref_alignment_error),
.lmfc_edge(lmfc_edge),
.lmfc_clk(lmfc_clk),
.lmfc_counter(),
.lmc_edge(lmc_edge),
.lmc_quarter_edge(lmc_quarter_edge),
.eoemb(eoemb)
);
generate
genvar i;
if (LINK_MODE[0] == 1) begin : mode_8b10b
wire eof_gen_reset;
wire [DATA_PATH_WIDTH-1:0] eof;
wire eomf;
wire [NUM_LANES-1:0] lane_cgs_enable;
wire [DW-1:0] ilas_data;
wire [DATA_PATH_WIDTH-1:0] ilas_charisk;
wire cfg_generate_eomf = 1'b1;
jesd204_tx_ctrl #(
.NUM_LANES(NUM_LANES),
.NUM_LINKS(NUM_LINKS),
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
) i_tx_ctrl (
.clk(clk),
.reset(reset),
.sync(sync),
.lmfc_edge(lmfc_edge),
.lane_cgs_enable(lane_cgs_enable),
.eof_reset(eof_gen_reset),
.tx_ready(tx_ready),
.ilas_data(ilas_data),
.ilas_charisk(ilas_charisk),
.ilas_config_addr(ilas_config_addr),
.ilas_config_rd(ilas_config_rd),
.ilas_config_data(ilas_config_data),
.cfg_lanes_disable(cfg_lanes_disable),
.cfg_links_disable(cfg_links_disable),
.cfg_continuous_cgs(cfg_continuous_cgs),
.cfg_continuous_ilas(cfg_continuous_ilas),
.cfg_skip_ilas(cfg_skip_ilas),
.cfg_mframes_per_ilas(cfg_mframes_per_ilas),
.cfg_disable_char_replacement(cfg_disable_char_replacement),
.ctrl_manual_sync_request(ctrl_manual_sync_request),
.status_sync(status_sync),
.status_state(status_state)
);
jesd204_eof_generator #(
.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
.MAX_OCTETS_PER_FRAME(MAX_OCTETS_PER_FRAME)
) i_eof_gen (
.clk(clk),
.reset(eof_gen_reset),
.cfg_octets_per_frame(cfg_octets_per_frame),
.cfg_generate_eomf(cfg_generate_eomf),
.lmfc_edge(lmfc_edge),
.sof(),
.eof(eof),
.eomf(eomf)
);
for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
localparam D_START = i * DATA_PATH_WIDTH*8;
localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1;
localparam C_START = i * DATA_PATH_WIDTH;
localparam C_STOP = C_START + DATA_PATH_WIDTH-1;
jesd204_tx_lane #(
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
) i_lane (
.clk(clk),
.eof(eof),
.eomf(eomf),
.cgs_enable(lane_cgs_enable[i]),
.ilas_data(ilas_data[D_STOP:D_START]),
.ilas_charisk(ilas_charisk),
.tx_data(tx_data[D_STOP:D_START]),
.tx_ready(tx_ready),
.phy_data(phy_data_r[D_STOP:D_START]),
.phy_charisk(phy_charisk_r[C_STOP:C_START]),
.cfg_disable_scrambler(cfg_disable_scrambler)
);
end
assign phy_header_r = 'h0;
end
if (LINK_MODE[1] == 1) begin : mode_64b66b
reg tx_ready_loc;
for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
localparam D_START = i * DATA_PATH_WIDTH*8;
localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1;
localparam H_START = i * 2;
localparam H_STOP = H_START + 2 -1;
jesd204_tx_lane_64b i_lane(
.clk(clk),
.reset(reset),
.tx_data(tx_data[D_STOP:D_START]),
.tx_ready(tx_ready_loc),
.phy_data(phy_data_r[D_STOP:D_START]),
.phy_header(phy_header_r[H_STOP:H_START]),
.lmc_edge(lmc_edge),
.lmc_quarter_edge(lmc_quarter_edge),
.eoemb(eoemb),
.cfg_disable_scrambler(cfg_disable_scrambler),
.cfg_header_mode(2'b0),
.cfg_lane_disable(cfg_lanes_disable[i])
);
end
always @(posedge clk) begin
if (reset) begin
tx_ready_loc <= 1'b0;
end else if (lmfc_edge) begin
tx_ready_loc <= 1'b1;
end
end
assign tx_ready = tx_ready_loc;
// Link considered in DATA phase when SYSREF received and LEMC clock started
// running
assign status_state = {2{tx_ready_loc}};
assign phy_charisk_r = 'h0;
assign ilas_config_rd = 'h0;
assign ilas_config_addr = 'h0;
assign status_sync = 'h0;
end
endgenerate
pipeline_stage #(
.WIDTH(CW + DW + HW),
.REGISTERED(NUM_OUTPUT_PIPELINE)
) i_output_pipeline_stage (
.clk(clk),
.in({
phy_data_r,
phy_charisk_r,
phy_header_r
}),
.out({
phy_data,
phy_charisk,
phy_header
})
);
endmodule
adi_library/jesd204/jesd204_tx/jesd204_tx.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1343"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="2"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1306"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="3"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ERROR"/>
<MsgAttr Name="Id" Val="BD 41-1276"/>
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="4"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="5"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="6"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="7"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Synth 8-3331"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
<BootPmcSettings Version="1" Minor="0">
<Parameters>
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
</Parameters>
</BootPmcSettings>
</Project>
adi_library/jesd204/jesd204_tx/jesd204_tx_constr.sdc
+50
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@@ -0,0 +1,50 @@
#
# The ADI JESD204 Core is released under the following license, which is
# different than all other HDL cores in this repository.
#
# Please read this, and understand the freedoms and responsibilities you have
# by using this source code/core.
#
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
#
# This core is free software, you can use run, copy, study, change, ask
# questions about and improve this core. Distribution of source, or resulting
# binaries (including those inside an FPGA or ASIC) require you to release the
# source of the entire project (excluding the system libraries provide by the
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License version 2
# along with this source code, and binary. If not, see
# <http://www.gnu.org/licenses/>.
#
# Commercial licenses (with commercial support) of this JESD204 core are also
# available under terms different than the General Public License. (e.g. they
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
# core with any corresponding source code.) For these alternate terms you must
# purchase a license from Analog Devices Technology Licensing Office. Users
# interested in such a license should contact [email protected] for
# more information. This commercial license is sub-licensable (if you purchase
# chips from Analog Devices, incorporate them into your PCB level product, and
# purchase a JESD204 license, end users of your product will also have a
# license to use this core in a commercial setting without releasing their
# source code).
#
# In addition, we kindly ask you to acknowledge ADI in any program, application
# or publication in which you use this JESD204 HDL core. (You are not required
# to do so; it is up to your common sense to decide whether you want to comply
# with this request or not.) For general publications, we suggest referencing :
# “The design and implementation of the JESD204 HDL Core used in this project
# is copyright © 2016-2017, Analog Devices, Inc.”
#
set script_dir [file dirname [info script]]
source "$script_dir/util_cdc_constr.tcl"
# SYNC~ is a asynchronous interface
util_cdc_sync_bits_constr {*|jesd204_tx_ctrl:i_tx_ctrl|sync_bits:i_cdc_sync}
adi_library/jesd204/jesd204_tx/jesd204_tx_constr.ttcl
+58
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@@ -0,0 +1,58 @@
#
# The ADI JESD204 Core is released under the following license, which is
# different than all other HDL cores in this repository.
#
# Please read this, and understand the freedoms and responsibilities you have
# by using this source code/core.
#
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
#
# This core is free software, you can use run, copy, study, change, ask
# questions about and improve this core. Distribution of source, or resulting
# binaries (including those inside an FPGA or ASIC) require you to release the
# source of the entire project (excluding the system libraries provide by the
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License version 2
# along with this source code, and binary. If not, see
# <http://www.gnu.org/licenses/>.
#
# Commercial licenses (with commercial support) of this JESD204 core are also
# available under terms different than the General Public License. (e.g. they
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
# core with any corresponding source code.) For these alternate terms you must
# purchase a license from Analog Devices Technology Licensing Office. Users
# interested in such a license should contact [email protected] for
# more information. This commercial license is sub-licensable (if you purchase
# chips from Analog Devices, incorporate them into your PCB level product, and
# purchase a JESD204 license, end users of your product will also have a
# license to use this core in a commercial setting without releasing their
# source code).
#
# In addition, we kindly ask you to acknowledge ADI in any program, application
# or publication in which you use this JESD204 HDL core. (You are not required
# to do so; it is up to your common sense to decide whether you want to comply
# with this request or not.) For general publications, we suggest referencing :
# “The design and implementation of the JESD204 HDL Core used in this project
# is copyright © 2016-2017, Analog Devices, Inc.”
#
<: set ComponentName [getComponentNameString] :>
<: setOutputDirectory "./" :>
<: setFileName [ttcl_add $ComponentName "_constr"] :>
<: setFileExtension ".xdc" :>
<: setFileProcessingOrder late :>
<: set sysref_iob [get_property PARAM_VALUE.SYSREF_IOB] :>
set_property ASYNC_REG TRUE \
[get_cells {i_lmfc/sysref_d1_reg}] \
[get_cells {i_lmfc/sysref_d2_reg}]
# Make sure that the device clock to sysref skew is at least somewhat
# predictable
set_property IOB <=: $sysref_iob :> \
[get_cells {i_lmfc/sysref_r_reg}]
adi_library/jesd204/jesd204_tx/jesd204_tx_ctrl.v
+279
View File
@@ -0,0 +1,279 @@
//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
`timescale 1ns/100ps
module jesd204_tx_ctrl #(
parameter NUM_LANES = 1,
parameter NUM_LINKS = 1,
parameter DATA_PATH_WIDTH = 4
) (
input clk,
input reset,
input [NUM_LINKS-1:0] sync,
input lmfc_edge,
output reg [NUM_LANES-1:0] lane_cgs_enable,
output reg eof_reset,
output reg tx_ready,
output reg [DATA_PATH_WIDTH*8*NUM_LANES-1:0] ilas_data,
output reg [DATA_PATH_WIDTH-1:0] ilas_charisk,
output reg [1:0] ilas_config_addr,
output reg ilas_config_rd,
input [DATA_PATH_WIDTH*8*NUM_LANES-1:0] ilas_config_data,
input [NUM_LANES-1:0] cfg_lanes_disable,
input [NUM_LINKS-1:0] cfg_links_disable,
input cfg_continuous_cgs,
input cfg_continuous_ilas,
input cfg_skip_ilas,
input [7:0] cfg_mframes_per_ilas,
input cfg_disable_char_replacement,
input ctrl_manual_sync_request,
output [NUM_LINKS-1:0] status_sync,
output reg [1:0] status_state
);
reg lmfc_edge_d1 = 1'b0;
reg lmfc_edge_d2 = 1'b0;
reg ilas_reset = 1'b1;
reg ilas_data_reset = 1'b1;
reg sync_request = 1'b0;
reg sync_request_received = 1'b0;
reg [7:0] mframe_counter = 'h00;
reg [5:0] ilas_counter = 'h00;
reg ilas_config_rd_d1 = 1'b1;
reg last_ilas_mframe = 1'b0;
reg cgs_enable = 1'b1;
wire [NUM_LINKS-1:0] status_sync_masked;
sync_bits #(
.NUM_OF_BITS (NUM_LINKS))
i_cdc_sync (
.in_bits(sync),
.out_clk(clk),
.out_resetn(1'b1),
.out_bits(status_sync)
);
assign status_sync_masked = status_sync | cfg_links_disable;
always @(posedge clk) begin
if (reset == 1'b1) begin
sync_request <= {NUM_LINKS{1'b0}};
end else begin
/* TODO: SYNC must be asserted at least 4 frames before interpreted as a
* sync request and the /K28.5/ symbol generation has lasted for at
* least 1 frame + 9 octets */
if (cfg_continuous_cgs == 1'b1) begin
sync_request <= 1'b1;
end else begin
sync_request <= ~(&status_sync_masked) | ctrl_manual_sync_request;
end
end
end
always @(posedge clk) begin
if (sync_request == 1'b0 && sync_request_received == 1'b1) begin
lmfc_edge_d1 <= lmfc_edge;
lmfc_edge_d2 <= lmfc_edge_d1;
end else begin
lmfc_edge_d1 <= 1'b0;
lmfc_edge_d2 <= 1'b0;
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
sync_request_received <= 1'b0;
end else if (sync_request == 1'b1) begin
sync_request_received <= 1'b1;
end
end
always @(posedge clk) begin
if (cfg_skip_ilas == 1'b1 ||
mframe_counter == cfg_mframes_per_ilas) begin
last_ilas_mframe <= 1'b1;
end else begin
last_ilas_mframe <= 1'b0;
end
end
localparam STATE_WAIT = 2'b00;
localparam STATE_CGS = 2'b01;
localparam STATE_ILAS = 2'b10;
localparam STATE_DATA = 2'b11;
/* Timeline
*
* #1 lmfc_edge == 1, ilas_reset update
* #2 eof_reset update
* #3 {lane_,}cgs_enable, tx_ready update
*
* One multi-frame should at least be 3 clock cycles (TBD 64-bit data path)
*/
always @(posedge clk) begin
if (sync_request == 1'b1 || reset == 1'b1) begin
cgs_enable <= 1'b1;
lane_cgs_enable <= {NUM_LANES{1'b1}};
tx_ready <= 1'b0;
eof_reset <= 1'b1;
ilas_reset <= 1'b1;
ilas_data_reset <= 1'b1;
if (sync_request_received == 1'b0) begin
status_state <= STATE_WAIT;
end else begin
status_state <= STATE_CGS;
end
end else if (sync_request_received == 1'b1) begin
if (lmfc_edge == 1'b1 && last_ilas_mframe == 1'b1) begin
ilas_reset <= 1'b1;
status_state <= STATE_DATA;
end else if (lmfc_edge_d1 == 1'b1 && (cfg_continuous_ilas == 1'b1 ||
cgs_enable == 1'b1)) begin
ilas_reset <= 1'b0;
status_state <= STATE_ILAS;
end
if (lmfc_edge_d1 == 1'b1) begin
if (last_ilas_mframe == 1'b1 && cfg_continuous_ilas == 1'b0) begin
eof_reset <= cfg_disable_char_replacement;
ilas_data_reset <= 1'b1;
end else if (cgs_enable == 1'b1) begin
ilas_data_reset <= 1'b0;
end
end
if (lmfc_edge_d2 == 1'b1) begin
lane_cgs_enable <= cfg_lanes_disable;
cgs_enable <= 1'b0;
if (last_ilas_mframe == 1'b1 && cfg_continuous_ilas == 1'b0) begin
tx_ready <= 1'b1;
end
end
end
end
always @(posedge clk) begin
if (ilas_reset == 1'b1) begin
mframe_counter <= 'h00;
end else if (lmfc_edge_d1 == 1'b1) begin
mframe_counter <= mframe_counter + 1'b1;
end
end
always @(posedge clk) begin
if (ilas_reset == 1'b1) begin
ilas_config_rd <= 1'b0;
end else if (mframe_counter == 'h00 && lmfc_edge == 1'b1) begin
ilas_config_rd <= 1'b1;
end else if (ilas_config_addr == 'h3) begin
ilas_config_rd <= 1'b0;
end
ilas_config_rd_d1 <= ilas_config_rd;
end
always @(posedge clk) begin
if (ilas_config_rd == 1'b0) begin
ilas_config_addr <= 'h00;
end else begin
ilas_config_addr <= ilas_config_addr + 1'b1;
end
end
always @(posedge clk) begin
if (ilas_reset == 1'b1) begin
ilas_counter <= 'h00;
end else begin
ilas_counter <= ilas_counter + 1'b1;
end
end
wire [31:0] ilas_default_data = {
ilas_counter,2'h3,
ilas_counter,2'h2,
ilas_counter,2'h1,
ilas_counter,2'h0
};
always @(posedge clk) begin
if (ilas_data_reset == 1'b1) begin
ilas_data <= {NUM_LANES{32'h00}};
ilas_charisk <= 4'b0000;
end else begin
if (ilas_config_rd_d1 == 1'b1) begin
case (ilas_config_addr)
2'h1: begin
ilas_data <= (ilas_config_data & {NUM_LANES{32'hffff0000}}) |
{NUM_LANES{16'h00,8'h9c,8'h1c}}; // /Q/ /R/
ilas_charisk <= 4'b0011;
end
default: begin
ilas_data <= ilas_config_data;
ilas_charisk <= 4'b0000;
end
endcase
end else if (lmfc_edge_d2 == 1'b1) begin
ilas_data <= {NUM_LANES{ilas_default_data[31:8],8'h1c}}; // /R/
ilas_charisk <= 4'b0001;
end else if (lmfc_edge_d1 == 1'b1) begin
ilas_data <= {NUM_LANES{8'h7c,ilas_default_data[23:0]}}; // /A/
ilas_charisk <= 4'b1000;
end else begin
ilas_data <= {NUM_LANES{ilas_default_data}};
ilas_charisk <= 4'b0000;
end
end
end
endmodule
adi_library/jesd204/jesd204_tx/jesd204_tx_header.v
+108
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@@ -0,0 +1,108 @@
//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
`timescale 1ns/100ps
module jesd204_tx_header (
input clk,
input reset,
input [1:0] cfg_header_mode,
input lmc_edge,
input lmc_quarter_edge,
// Header content to be sent must be valid during lmc_edge
input eoemb,
input [2:0] crc3,
input [11:0] crc12,
input [25:0] fec,
input [18:0] cmd,
output [1:0] header
);
reg header_bit;
reg [31:0] sync_word = 'h0;
always @(posedge clk) begin
if (reset) begin
sync_word <= 'h0;
end else if (lmc_edge) begin
case (cfg_header_mode)
// CRC-12
2'b00 : sync_word <= {crc12[11:9],1'b1,crc12[8:6],1'b1,
crc12[5:3],1'b1,crc12[2:0],1'b1,
cmd[6:4],1'b1,cmd[3],1'b1,eoemb,1'b1,
cmd[2:0],5'b00001};
// CRC-3
2'b01 : sync_word <= { crc3[2:0],1'b1,cmd[6:4],1'b1,
3'b000,1'b1,cmd[3:1],1'b1,
3'b000,1'b1,cmd[0],1'b1,eoemb,1'b1,
3'b000,5'b00001};
// FEC
2'b10 : sync_word <= { fec[25:18],
fec[17:10],
fec[9:4],eoemb,fec[3],
fec[2:0],5'b00001};
// Stand alone command
2'b11 : sync_word <= { cmd[18:16],1'b1,cmd[15:13],1'b1,
cmd[12:10],1'b1,cmd[9:7],1'b1,
cmd[6:4],1'b1,cmd[3],1'b1,eoemb,1'b1,
cmd[2:0],5'b00001};
endcase
end else begin
if (lmc_quarter_edge && cfg_header_mode == 2'b01) begin
sync_word <= {crc3[2],crc3[1],crc3[0],sync_word[27:0],1'b0};
end else begin
sync_word <= {sync_word[30:0],1'b0};
end
end
end
assign header = {~sync_word[31],sync_word[31]};
endmodule
adi_library/jesd204/jesd204_tx/jesd204_tx_hw.tcl
+210
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@@ -0,0 +1,210 @@
#
# The ADI JESD204 Core is released under the following license, which is
# different than all other HDL cores in this repository.
#
# Please read this, and understand the freedoms and responsibilities you have
# by using this source code/core.
#
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
#
# This core is free software, you can use run, copy, study, change, ask
# questions about and improve this core. Distribution of source, or resulting
# binaries (including those inside an FPGA or ASIC) require you to release the
# source of the entire project (excluding the system libraries provide by the
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License version 2
# along with this source code, and binary. If not, see
# <http://www.gnu.org/licenses/>.
#
# Commercial licenses (with commercial support) of this JESD204 core are also
# available under terms different than the General Public License. (e.g. they
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
# core with any corresponding source code.) For these alternate terms you must
# purchase a license from Analog Devices Technology Licensing Office. Users
# interested in such a license should contact [email protected] for
# more information. This commercial license is sub-licensable (if you purchase
# chips from Analog Devices, incorporate them into your PCB level product, and
# purchase a JESD204 license, end users of your product will also have a
# license to use this core in a commercial setting without releasing their
# source code).
#
# In addition, we kindly ask you to acknowledge ADI in any program, application
# or publication in which you use this JESD204 HDL core. (You are not required
# to do so; it is up to your common sense to decide whether you want to comply
# with this request or not.) For general publications, we suggest referencing :
# “The design and implementation of the JESD204 HDL Core used in this project
# is copyright © 2016-2017, Analog Devices, Inc.”
#
package require qsys
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
ad_ip_create jesd204_tx "ADI JESD204 Transmit" jesd204_tx_elaboration_callback
set_module_property INTERNAL true
# files
ad_ip_files jesd204_tx [list \
jesd204_tx.v \
jesd204_tx_ctrl.v \
jesd204_tx_lane.v \
jesd204_tx_constr.sdc \
../jesd204_common/jesd204_eof_generator.v \
../jesd204_common/jesd204_lmfc.v \
../jesd204_common/jesd204_scrambler.v \
../jesd204_common/pipeline_stage.v \
$ad_hdl_dir/library/util_cdc/sync_bits.v \
$ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl \
]
# parameters
add_parameter NUM_LANES INTEGER 1
set_parameter_property NUM_LANES DISPLAY_NAME "Number of Lanes"
set_parameter_property NUM_LANES ALLOWED_RANGES 1:8
set_parameter_property NUM_LANES HDL_PARAMETER true
add_parameter NUM_LINKS INTEGER 1
set_parameter_property NUM_LINKS DISPLAY_NAME "Number of Links"
set_parameter_property NUM_LINKS ALLOWED_RANGES 1:8
set_parameter_property NUM_LINKS HDL_PARAMETER true
add_parameter NUM_OUTPUT_PIPELINE INTEGER 0
set_parameter_property NUM_OUTPUT_PIPELINE DISPLAY_NAME "Number of output pipeline stages"
set_parameter_property NUM_OUTPUT_PIPELINE ALLOWED_RANGES 0:3
set_parameter_property NUM_OUTPUT_PIPELINE HDL_PARAMETER true
# clock
add_interface clock clock end
add_interface_port clock clk clk Input 1
# reset
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
add_interface_port reset reset reset Input 1
# SYSREF~ interface
add_interface sysref conduit end
set_interface_property sysref associatedClock clock
set_interface_property sysref associatedReset reset
add_interface_port sysref sysref export Input 1
# SYNC interface
add_interface sync conduit end
set_interface_property sync associatedClock clock
set_interface_property sync associatedReset reset
add_interface_port sync sync export Input 1
# ilas_config interface
add_interface ilas_config conduit end
set_interface_property ilas_config associatedClock clock
set_interface_property ilas_config associatedReset reset
add_interface_port ilas_config ilas_config_addr addr Output 2
add_interface_port ilas_config ilas_config_data data Input 32*NUM_LANES
add_interface_port ilas_config ilas_config_rd rd Output 1
# event interface
add_interface event conduit end
set_interface_property event associatedClock clock
set_interface_property event associatedReset reset
add_interface_port event event_sysref_alignment_error sysref_alignment_error Output 1
add_interface_port event event_sysref_edge sysref_edge Output 1
# control interface
add_interface control conduit end
set_interface_property control associatedClock clock
set_interface_property control associatedReset reset
add_interface_port control ctrl_manual_sync_request manual_sync_request Input 1
# config interface
add_interface config conduit end
set_interface_property config associatedClock clock
set_interface_property config associatedReset reset
add_interface_port config cfg_beats_per_multiframe beats_per_multiframe Input 8
add_interface_port config cfg_continuous_cgs continuous_cgs Input 1
add_interface_port config cfg_continuous_ilas continuous_ilas Input 1
add_interface_port config cfg_disable_char_replacement disable_char_replacement Input 1
add_interface_port config cfg_disable_scrambler disable_scrambler Input 1
add_interface_port config cfg_lanes_disable lanes_disable Input NUM_LANES
add_interface_port config cfg_links_disable links_disable Input NUM_LINKS
add_interface_port config cfg_lmfc_offset lmfc_offset Input 8
add_interface_port config cfg_mframes_per_ilas mframes_per_ilas Input 8
add_interface_port config cfg_octets_per_frame octets_per_frame Input 8
add_interface_port config cfg_skip_ilas skip_ilas Input 1
add_interface_port config cfg_sysref_disable sysref_disable Input 1
add_interface_port config cfg_sysref_oneshot sysref_oneshot Input 1
# status interface
add_interface status conduit end
set_interface_property status associatedClock clock
set_interface_property status associatedReset reset
add_interface_port status status_state state Output 2
add_interface_port status status_sync sync Output 1
# lmfc_clk interface
add_interface lmfc_clk conduit end
#set_interface_property lmfc_clk associatedClock clock
#set_interface_property lmfc_clk associatedReset reset
add_interface_port lmfc_clk lmfc_clk export Output 1
set_port_property lmfc_clk TERMINATION TRUE
# lmfc_edge interface
add_interface lmfc_edge conduit end
#set_interface_property lmfc_edge associatedClock clock
#set_interface_property lmfc_edge associatedReset reset
add_interface_port lmfc_edge lmfc_edge export Output 1
set_port_property lmfc_edge TERMINATION TRUE
proc jesd204_tx_elaboration_callback {} {
set num_lanes [get_parameter_value "NUM_LANES"]
# tx_data interface
add_interface tx_data avalon_streaming sink
set_interface_property tx_data associatedClock clock
add_interface_port tx_data tx_data data input [expr 32*$num_lanes]
add_interface_port tx_data tx_ready ready output 1
add_interface_port tx_data tx_valid valid input 1
set_interface_property tx_data dataBitsPerSymbol [expr 32*$num_lanes]
# phy interfaces
for {set i 0 } {$i < $num_lanes} {incr i} {
add_interface tx_phy${i} conduit start
# set_interface_property tx_phy${i} associatedClock clock
# set_interface_property tx_phy${i} associatedReset reset
add_interface_port tx_phy${i} tx_phy${i}_data char Output 32
set_port_property tx_phy${i}_data fragment_list \
[format "phy_data(%d:%d)" [expr 32*$i+31] [expr 32*$i]]
add_interface_port tx_phy${i} tx_phy${i}_charisk charisk Output 4
set_port_property tx_phy${i}_charisk fragment_list \
[format "phy_charisk(%d:%d)" [expr 4*$i+3] [expr 4*$i]]
}
}
adi_library/jesd204/jesd204_tx/jesd204_tx_ip.log
+852
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@@ -0,0 +1,852 @@
****** Vivado v2019.1.3 (64-bit)
**** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
**** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
source jesd204_tx_ip.tcl
# source ../../scripts/adi_env.tcl
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
## if [info exists ::env(ADI_HDL_DIR)] {
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
## }
## if [info exists ::env(ADI_GHDL_DIR)] {
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
## }
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
### variable auto_set_param_list
### variable auto_set_param_list_overwritable
### variable fpga_series_list
### variable fpga_family_list
### variable speed_grade_list
### variable dev_package_list
### variable xcvr_type_list
### variable fpga_voltage_list
### set auto_set_param_list { \
### DEV_PACKAGE \
### SPEED_GRADE \
### FPGA_FAMILY \
### FPGA_TECHNOLOGY }
### set auto_set_param_list_overwritable { \
### FPGA_VOLTAGE \
### XCVR_TYPE }
### set fpga_technology_list { \
### { Unknown 0 } \
### { 7series 1 } \
### { ultrascale 2 } \
### { ultrascale+ 3 }}
### set fpga_family_list { \
### { Unknown 0 } \
### { artix 1 } \
### { kintex 2 } \
### { virtex 3 } \
### { zynq 4 }}
### set speed_grade_list { \
### { Unknown 0 } \
### { -1 10 } \
### { -1L 11 } \
### { -1H 12 } \
### { -1HV 13 } \
### { -1LV 14 } \
### { -2 20 } \
### { -2L 21 } \
### { -2LV 22 } \
### { -3 30 }}
### set dev_package_list { \
### { Unknown 0 } \
### { rf 1 } \
### { fl 2 } \
### { ff 3 } \
### { fb 4 } \
### { hc 5 } \
### { fh 6 } \
### { cs 7 } \
### { cp 8 } \
### { ft 9 } \
### { fg 10 } \
### { sb 11 } \
### { rb 12 } \
### { rs 13 } \
### { cl 14 } \
### { sf 15 } \
### { ba 16 } \
### { fa 17 } \
### { fs 18 } \
### { fi 19 }}
### set xcvr_type_list { \
### { Unknown 0 } \
### { GTPE2_NOT_SUPPORTED 1 } \
### { GTXE2 2 } \
### { GTHE2_NOT_SUPPORTED 3 } \
### { GTZE2_NOT_SUPPORTED 4 } \
### { GTHE3 5 } \
### { GTYE3_NOT_SUPPORTED 6 } \
### { GTRE4_NOT_SUPPORTED 7 } \
### { GTHE4 8 } \
### { GTYE4 9 } \
### { GTME4_NOT_SUPPORTED 10}}
### set fpga_voltage_list {0 5000} ;
### proc adi_device_spec {cellpath param} {
###
### set list_pointer [string tolower $param]
### set list_pointer [append list_pointer "_list"]
###
### upvar 1 $list_pointer $list_pointer
###
### set ip [get_bd_cells $cellpath]
### set part [get_property PART [current_project]]
###
### switch -regexp -- $param {
### FPGA_TECHNOLOGY {
### switch -regexp -- $part {
### ^xc7 {set series_name 7series}
### ^xczu {set series_name ultrascale+}
### ^xc.u.p {set series_name ultrascale+}
### ^xc.u {set series_name ultrascale }
### default {
### puts "Undefined fpga technology for \"$part\"!"
### exit -1
### }
### }
### return "$series_name"
### }
### FPGA_FAMILY {
### set fpga_family [get_property FAMILY $part]
### foreach i $fpga_family_list {
### regexp ^[lindex $i 0] $fpga_family matched
### }
### return "$matched"
### }
### SPEED_GRADE {
### set speed_grade [get_property SPEED $part]
### return "$speed_grade"
### }
### DEV_PACKAGE {
### set dev_package [get_property PACKAGE $part]
### foreach i $dev_package_list {
### regexp ^[lindex $i 0] $dev_package matched
### }
### return "$matched"
### }
### XCVR_TYPE {
### set matched ""
### set dev_transcivers "none"
### foreach x [list_property $part] {
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
### }
### foreach i $xcvr_type_list {
### regexp ^[lindex $i 0] $dev_transcivers matched
### }
### if { $matched eq "" } {
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
### }
### return "$matched"
### }
### FPGA_VOLTAGE {
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
###
### return "$fpga_voltage"
### }
### default {
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
### }
### }
### }
## if {![info exists REQUIRED_VIVADO_VERSION]} {
## set REQUIRED_VIVADO_VERSION "2019.1"
## }
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
## set IGNORE_VERSION_CHECK 1
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
## set IGNORE_VERSION_CHECK 0
## }
## proc adi_ip_ttcl {ip_name ip_constr_files} {
##
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
## set_property -dict [list \
## type ttcl \
## ] $f
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
## }
## proc adi_ip_sim_ttcl {ip_name ip_files} {
##
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
## set f [ipx::add_file $ip_files $proj_filegroup]
## set_property -dict [list \
## type ttcl \
## ] $f
## ipx::reorder_files -front $ip_files $proj_filegroup
## }
## proc adi_ip_bd {ip_name ip_bd_files} {
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
## if {$proj_filegroup == {}} {
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
## }
##
## foreach file $ip_bd_files {
## set f [ipx::add_file $file $proj_filegroup]
## set_property -dict [list \
## type tclSource \
## ] $f
## }
## }
## proc adi_ip_infer_streaming_interfaces {ip_name} {
##
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
##
## }
## proc adi_ip_infer_mm_interfaces {ip_name} {
##
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
##
## }
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
## set_property ENABLEMENT_DEPENDENCY $dependency $port
## if {$driver_value != {}} {
## set_property DRIVER_VALUE $driver_value $port
## }
## }
## }
## proc adi_set_bus_dependency {bus prefix dependency} {
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
## adi_set_ports_dependency $prefix $dependency 0
## }
## proc adi_add_port_map {bus phys logic} {
## set map [ipx::add_port_map $phys $bus]
## set_property "PHYSICAL_NAME" $phys $map
## set_property "LOGICAL_NAME" $logic $map
## }
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
##
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
## set_property "BUS_TYPE_VLNV" $bus_type $bus
## set_property "INTERFACE_MODE" $mode $bus
##
## foreach port_map $port_maps {
## adi_add_port_map $bus {*}$port_map
## }
## }
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
## for {set i 0} {$i < $num} {incr i} {
## set bus_name [format "%s%d" $bus_name_prefix $i]
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
##
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
## set_property "BUS_TYPE_VLNV" $bus_type $bus
## set_property "INTERFACE_MODE" $mode $bus
##
## if {$dependency ne ""} {
## set bus_dependency [string map [list "{i}" $i] $dependency]
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
## }
##
## foreach port_map $port_maps {
## lassign $port_map phys logic width width_dep
## set map [ipx::add_port_map $phys $bus]
## set_property "PHYSICAL_NAME" $phys $map
## set_property "LOGICAL_NAME" $logic $map
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
## if {$width_dep ne ""} {
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
## set width_dep_r "(($width_dep) * $i)"
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
## }
## }
## }
## }
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
## set_property display_name $clock_inf_name $clock_inf
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
## set_property physical_name $clock_signal_name $clock_map
##
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
## set_property value $bus_inf_name $assoc_busif
##
## if { $reset_signal_name != "" } {
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
## set_property value $reset_signal_name $assoc_reset
##
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
## set_property display_name $reset_inf_name $reset_inf
## set_property interface_mode $reset_signal_mode $reset_inf
## set reset_map [ipx::add_port_map "RST" $reset_inf]
## set_property physical_name $reset_signal_name $reset_map
##
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
## set_property value "ACTIVE_LOW" $reset_polarity
## } else {
## set_property value "ACTIVE_HIGH" $reset_polarity
## }
## }
## }
## proc adi_ip_add_core_dependencies {vlnvs} {
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
## foreach vlnv $vlnvs {
## ipx::add_subcore $vlnv $file_group
## }
## }
## }
## proc adi_ip_create {ip_name} {
##
## global ad_hdl_dir
## global ad_ghdl_dir
## global REQUIRED_VIVADO_VERSION
## global IGNORE_VERSION_CHECK
##
## set VIVADO_VERSION [version -short]
## if {$IGNORE_VERSION_CHECK} {
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
## puts -nonewline "got $VIVADO_VERSION.\n"
## }
## } else {
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
## puts -nonewline "ERROR: vivado version mismatch; "
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
## puts -nonewline "got $VIVADO_VERSION.\n"
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
## exit 2
## }
## }
##
## create_project $ip_name . -force
##
## ## Load custom message severity definitions
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
##
## set lib_dirs $ad_hdl_dir/library
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
## lappend lib_dirs $ad_ghdl_dir/library
## }
##
## set_property ip_repo_paths $lib_dirs [current_fileset]
## update_ip_catalog
## }
## proc adi_ip_files {ip_name ip_files} {
## set proj_fileset [get_filesets sources_1]
## foreach m_file $ip_files {
## if {[file extension $m_file] eq ".xdc"} {
## add_files -norecurse -fileset constrs_1 $m_file
## } else {
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
## }
## }
## set_property "top" "$ip_name" $proj_fileset
## }
## proc adi_ip_properties_lite {ip_name} {
##
## global ad_hdl_dir
##
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
##
## set_property name $ip_name [ipx::current_core]
##
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
## set_property company_url {http://www.analog.com} [ipx::current_core]
##
## set i_families ""
## foreach i_part [get_parts] {
## lappend i_families [get_property FAMILY $i_part]
## }
## set i_families [lsort -unique $i_families]
## set s_families [get_property supported_families [ipx::current_core]]
## foreach i_family $i_families {
## set s_families "$s_families $i_family Production"
## set s_families "$s_families $i_family Beta"
## }
## set_property supported_families $s_families [ipx::current_core]
##
## ipx::save_core [ipx::current_core]
##
## ipx::remove_all_bus_interface [ipx::current_core]
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
## foreach map $memory_maps {
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
## }
##
## ipx::update_checksums [ipx::current_core]
## ipx::save_core [ipx::current_core]
## }
## proc adi_ip_properties {ip_name} {
##
## adi_ip_properties_lite $ip_name
##
## ipx::infer_bus_interface {\
## s_axi_awvalid \
## s_axi_awaddr \
## s_axi_awprot \
## s_axi_awready \
## s_axi_wvalid \
## s_axi_wdata \
## s_axi_wstrb \
## s_axi_wready \
## s_axi_bvalid \
## s_axi_bresp \
##
## s_axi_bready \
## s_axi_arvalid \
## s_axi_araddr \
## s_axi_arprot \
## s_axi_arready \
## s_axi_rvalid \
## s_axi_rdata \
## s_axi_rresp \
## s_axi_rready} \
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
##
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
##
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
##
## if {$raddr_width != $waddr_width} {
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
## set range 65536
## } else {
## if {$raddr_width >= 16} {
## set range 65536
## } else {
## set range [expr 1 << $raddr_width]
## }
## }
##
## ipx::add_memory_map {s_axi} [ipx::current_core]
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
## set_property range $range [ipx::get_address_blocks axi_lite \
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
## ipx::save_core
## }
## proc adi_init_bd_tcl {} {
##
## global auto_set_param_list
## global auto_set_param_list_overwritable
## set cc [ipx::current_core]
##
## if { [file exists bd] } {
## file delete -force bd
## }
## file mkdir bd
##
## set bd_tcl [open "bd/bd.tcl" w]
##
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
## puts $bd_tcl "proc init {cellpath otherInfo} {"
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
## puts $bd_tcl ""
## set auto_set_param ""
## foreach i $auto_set_param_list {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
## append auto_set_param " $i \\\n"
## }
## }
## if { $auto_set_param ne "" } {
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
## puts $bd_tcl $auto_set_param
## }
##
## set auto_set_overwritable_param ""
## foreach i $auto_set_param_list_overwritable {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
## append auto_set_overwritable_param " $i \\\n"
## }
## }
## if { $auto_set_overwritable_param ne "" } {
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
## puts $bd_tcl $auto_set_overwritable_param
## }
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
## puts $bd_tcl "}"
## puts $bd_tcl ""
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
## puts $bd_tcl ""
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
## puts $bd_tcl ""
## puts $bd_tcl " set parent_dir \"../\""
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
## puts $bd_tcl " break"
## puts $bd_tcl " }"
## puts $bd_tcl " append parent_dir \"../\""
## puts $bd_tcl " }"
## puts $bd_tcl ""
## puts $bd_tcl " # Find predefindes auto assignable parameters"
## puts $bd_tcl " foreach i \$auto_set_param_list {"
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
## puts $bd_tcl " }"
## puts $bd_tcl " }"
## puts $bd_tcl ""
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
## puts $bd_tcl " }"
## puts $bd_tcl " }"
## puts $bd_tcl "}"
## puts $bd_tcl ""
## close $bd_tcl
##
## set proj_fileset [get_filesets sources_1]
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
##
## set local_mk [open "temporary_case_dependencies.mk" w]
## seek $local_mk 0 start
## puts $local_mk "CLEAN_TARGET += bd"
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
## close $local_mk
## }
## proc adi_add_auto_fpga_spec_params {} {
##
## global auto_set_param_list
## global auto_set_param_list_overwritable
## set cc [ipx::current_core]
##
## foreach i $auto_set_param_list {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
## adi_add_device_spec_param $i
## }
## }
## foreach i $auto_set_param_list_overwritable {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
## adi_add_device_spec_param $i
## }
## }
## }
## proc adi_add_device_spec_param {ip_param} {
##
## set cc [ipx::current_core]
##
## set list_pointer [string tolower $ip_param]
## set list_pointer [append list_pointer "_list"]
##
## global $list_pointer
##
## # set j 1D list from the original list
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
##
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
## set_property -dict [list \
## "value_validation_type" "range_long" \
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
## [ipx::get_user_parameters $ip_param -of_objects $cc]
## } else {
## set_property -dict [list \
## "value_validation_type" "pairs" \
## "value_validation_pairs" $j ] \
## [ipx::get_user_parameters $ip_param -of_objects $cc]
## }
##
## # FPGA info grup
## set info_group_name "FPGA info"
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
## if { [string trim $info_group] eq "" } {
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
## -parent $page0 -display_name $info_group_name]
## }
##
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
## set_property -dict [list "widget" "comboBox" ] $p
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
## }
## proc adi_if_define {name} {
##
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
## ipx::create_bus_definition analog.com interface $name 1.0
##
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
##
## ipx::save_abstraction_definition [ipx::current_busabs]
## ipx::save_bus_definition [ipx::current_busdef]
## }
## proc adi_if_ports {dir width name {type none}} {
##
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
## set_property master_presence required $m_intf
## set_property slave_presence required $m_intf
## set_property master_width $width $m_intf
## set_property slave_width $width $m_intf
##
## set m_dir "in"
## set s_dir "out"
## if {$dir eq "output"} {
## set m_dir "out"
## set s_dir "in"
## }
##
## set_property master_direction $m_dir $m_intf
## set_property slave_direction $s_dir $m_intf
##
## if {$type ne "none"} {
## set_property is_${type} true $m_intf
## }
##
## ipx::save_bus_definition [ipx::current_busdef]
## ipx::save_abstraction_definition [ipx::current_busabs]
## }
## proc adi_if_infer_bus {if_name mode name maps} {
##
## ipx::add_bus_interface $name [ipx::current_core]
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
## set_property interface_mode $mode $m_bus_if
##
## foreach map $maps {
## set m_maps [regexp -all -inline {\S+} $map]
## lassign $m_maps p_name p_map
## ipx::add_port_map $p_name $m_bus_if
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
## }
## }
# adi_ip_create jesd204_tx
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
## set_msg_config -id {BD 41-1343} -new_severity WARNING
## set_msg_config -id {BD 41-1306} -new_severity WARNING
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
## set_msg_config -id {Synth 8-3331} -new_severity INFO
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx'.)
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
# adi_ip_files jesd204_tx [list \
# "jesd204_tx_lane.v" \
# "jesd204_tx_lane_64b.v" \
# "jesd204_tx_header.v" \
# "jesd204_tx_ctrl.v" \
# "jesd204_tx_constr.ttcl" \
# "jesd204_tx.v"
# ]
# adi_ip_properties_lite jesd204_tx
WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx/jesd204_tx_constr.ttcl' ignored by IP packager.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_data_r' has a dependency on the module local parameter or undefined parameter 'DW'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_charisk_r' has a dependency on the module local parameter or undefined parameter 'CW'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_header_r' has a dependency on the module local parameter or undefined parameter 'HW'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'ilas_data' has a dependency on the module local parameter or undefined parameter 'DW'.
WARNING: [IP_Flow 19-5150] The Range '(NUM_LINKS - 1):0' is present in all ports of the interface 'status'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave.
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_manual_request' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'ilas_config' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'phy' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master.
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'status' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'tx' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 'ilas_config'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'interface_if_gt_tx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
WARNING: [IP_Flow 19-5150] The Range '((32 * NUM_LANES) - 1):0' is present in all ports of the interface 'ilas_config'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 'ilas_config'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
WARNING: [IP_Flow 19-5464] No port map found for required logical port buffer_early_release on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave.
WARNING: [IP_Flow 19-5464] No port map found for required logical port buffer_delay on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave.
WARNING: [IP_Flow 19-5464] No port map found for required logical port frame_align_err_threshold on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave.
WARNING: [IP_Flow 19-5464] No port map found for required logical port err_statistics_reset on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave.
WARNING: [IP_Flow 19-5464] No port map found for required logical port err_statistics_mask on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'cfg' of definition 'analog.com:interface:jesd204_rx_cfg:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
INFO: [IP_Flow 19-5107] Inferred bus interface 'event' of definition 'analog.com:interface:jesd204_tx_event:1.0' (from User Repositories).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl' of definition 'analog.com:interface:jesd204_tx_ctrl:1.0' (from User Repositories).
INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'lmfc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-818] Not transferring value dependency attribute "(LINK_MODE1 ? 8 : 4)" into user parameter "DATA_PATH_WIDTH".
WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_manual_request': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_manual_request': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'ilas_config': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'phy_data' and definition port 'DATA'.
WARNING: [IP_Flow 19-1965] Bus Interface 'phy': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync' and definition port 'SYNC'.
WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'tx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "buffer_early_release" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "buffer_delay" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "frame_align_err_threshold" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_reset" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_mask" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
WARNING: [IP_Flow 19-3153] Bus Interface 'lmfc_clk': ASSOCIATED_BUSIF bus parameter is missing.
WARNING: [IP_Flow 19-4751] Bus Interface 'lmfc_clk': FREQ_HZ bus parameter is missing for output clock interface.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
# adi_ip_ttcl jesd204_tx "jesd204_tx_constr.ttcl"
# adi_ip_add_core_dependencies { \
# analog.com:user:jesd204_common:1.0 \
# analog.com:user:util_cdc:1.0 \
# }
# set_property display_name "ADI JESD204 Transmit" [ipx::current_core]
# set_property description "ADI JESD204 Transmit" [ipx::current_core]
# adi_add_bus "tx_data" "slave" \
# "xilinx.com:interface:axis_rtl:1.0" \
# "xilinx.com:interface:axis:1.0" \
# { \
# { "tx_valid" "TVALID" } \
# { "tx_ready" "TREADY" } \
# { "tx_data" "TDATA" } \
# }
# adi_add_multi_bus 16 "tx_phy" "master" \
# "xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0" \
# "xilinx.com:display_jesd204:jesd204_tx_bus:1.0" \
# [list \
# { "phy_data" "txdata" 32 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')) * 8)"} \
# { "phy_charisk" "txcharisk" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \
# { "phy_header" "txheader" 2} \
# ] \
# "(spirit:decode(id('MODELPARAM_VALUE.NUM_LANES')) > {i})"
# adi_add_bus "tx_cfg" "slave" \
# "analog.com:interface:jesd204_tx_cfg_rtl:1.0" \
# "analog.com:interface:jesd204_tx_cfg:1.0" \
# { \
# { "cfg_lanes_disable" "lanes_disable" } \
# { "cfg_links_disable" "links_disable" } \
# { "cfg_beats_per_multiframe" "beats_per_multiframe" } \
# { "cfg_octets_per_frame" "octets_per_frame" } \
# { "cfg_lmfc_offset" "lmfc_offset" } \
# { "cfg_sysref_oneshot" "sysref_oneshot" } \
# { "cfg_sysref_disable" "sysref_disable" } \
# { "cfg_continuous_cgs" "continuous_cgs" } \
# { "cfg_continuous_ilas" "continuous_ilas" } \
# { "cfg_skip_ilas" "skip_ilas" } \
# { "cfg_mframes_per_ilas" "mframes_per_ilas" } \
# { "cfg_disable_char_replacement" "disable_char_replacement" } \
# { "cfg_disable_scrambler" "disable_scrambler" } \
# }
# adi_add_bus "tx_ilas_config" "master" \
# "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" \
# "analog.com:interface:jesd204_tx_ilas_config:1.0" \
# { \
# { "ilas_config_rd" "rd" } \
# { "ilas_config_addr" "addr" } \
# { "ilas_config_data" "data" } \
# }
# adi_add_bus "tx_event" "master" \
# "analog.com:interface:jesd204_tx_event_rtl:1.0" \
# "analog.com:interface:jesd204_tx_event:1.0" \
# { \
# { "event_sysref_alignment_error" "sysref_alignment_error" } \
# { "event_sysref_edge" "sysref_edge" } \
# }
# adi_add_bus "tx_status" "master" \
# "analog.com:interface:jesd204_tx_status_rtl:1.0" \
# "analog.com:interface:jesd204_tx_status:1.0" \
# { \
# { "status_state" "state" } \
# { "status_sync" "sync" } \
# }
# adi_add_bus "tx_ctrl" "slave" \
# "analog.com:interface:jesd204_tx_ctrl_rtl:1.0" \
# "analog.com:interface:jesd204_tx_ctrl:1.0" \
# { \
# { "ctrl_manual_sync_request" "manual_sync_request" } \
# }
# adi_add_bus_clock "clk" "tx_data:tx_cfg:tx_ilas_config:tx_event:tx_status:tx_ctrl" \
# "reset"
# adi_set_bus_dependency "tx_ilas_config" "tx_ilas_config" \
# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
# adi_set_bus_dependency "tx_ctrl" "tx_ctrl" \
# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
# adi_set_ports_dependency "sync" \
# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
# set cc [ipx::current_core]
# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
# set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
# ipgui::move_param -component $cc -order 0 $p -parent $page0
# set_property -dict [list \
# "display_name" "Link Layer mode" \
# "tooltip" "Link Layer mode" \
# "widget" "comboBox" \
# ] $p
# set_property -dict [list \
# value_validation_type pairs \
# value_validation_pairs {64B66B 2 8B10B 1} \
# ] [ipx::get_user_parameters $p -of_objects $cc]
# set param [ipx::get_user_parameters DATA_PATH_WIDTH -of_objects $cc]
# set_property -dict [list \
# enablement_value false \
# value_tcl_expr {expr $LINK_MODE*4} \
# ] $param
# set param [ipx::add_user_parameter SYSREF_IOB $cc]
# set_property -dict {value_resolve_type user value_format bool value true} $param
# set param [ipgui::add_param -name {SYSREF_IOB} -component $cc -parent $page0]
# set_property -dict [list \
# display_name {Place SYSREF in IOB} \
# widget {checkBox} \
# show_label true \
# ] $param
# ipx::create_xgui_files [ipx::current_core]
# ipx::save_core [ipx::current_core]
INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:17:38 2021...
adi_library/jesd204/jesd204_tx/jesd204_tx_ip.tcl
+190
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@@ -0,0 +1,190 @@
#
# The ADI JESD204 Core is released under the following license, which is
# different than all other HDL cores in this repository.
#
# Please read this, and understand the freedoms and responsibilities you have
# by using this source code/core.
#
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
#
# This core is free software, you can use run, copy, study, change, ask
# questions about and improve this core. Distribution of source, or resulting
# binaries (including those inside an FPGA or ASIC) require you to release the
# source of the entire project (excluding the system libraries provide by the
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License version 2
# along with this source code, and binary. If not, see
# <http://www.gnu.org/licenses/>.
#
# Commercial licenses (with commercial support) of this JESD204 core are also
# available under terms different than the General Public License. (e.g. they
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
# core with any corresponding source code.) For these alternate terms you must
# purchase a license from Analog Devices Technology Licensing Office. Users
# interested in such a license should contact [email protected] for
# more information. This commercial license is sub-licensable (if you purchase
# chips from Analog Devices, incorporate them into your PCB level product, and
# purchase a JESD204 license, end users of your product will also have a
# license to use this core in a commercial setting without releasing their
# source code).
#
# In addition, we kindly ask you to acknowledge ADI in any program, application
# or publication in which you use this JESD204 HDL core. (You are not required
# to do so; it is up to your common sense to decide whether you want to comply
# with this request or not.) For general publications, we suggest referencing :
# “The design and implementation of the JESD204 HDL Core used in this project
# is copyright © 2016-2017, Analog Devices, Inc.”
#
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create jesd204_tx
adi_ip_files jesd204_tx [list \
"jesd204_tx_lane.v" \
"jesd204_tx_lane_64b.v" \
"jesd204_tx_header.v" \
"jesd204_tx_ctrl.v" \
"jesd204_tx_constr.ttcl" \
"jesd204_tx.v"
]
adi_ip_properties_lite jesd204_tx
adi_ip_ttcl jesd204_tx "jesd204_tx_constr.ttcl"
adi_ip_add_core_dependencies { \
analog.com:user:jesd204_common:1.0 \
analog.com:user:util_cdc:1.0 \
}
set_property display_name "ADI JESD204 Transmit" [ipx::current_core]
set_property description "ADI JESD204 Transmit" [ipx::current_core]
adi_add_bus "tx_data" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
{ \
{ "tx_valid" "TVALID" } \
{ "tx_ready" "TREADY" } \
{ "tx_data" "TDATA" } \
}
adi_add_multi_bus 16 "tx_phy" "master" \
"xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0" \
"xilinx.com:display_jesd204:jesd204_tx_bus:1.0" \
[list \
{ "phy_data" "txdata" 32 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')) * 8)"} \
{ "phy_charisk" "txcharisk" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \
{ "phy_header" "txheader" 2} \
] \
"(spirit:decode(id('MODELPARAM_VALUE.NUM_LANES')) > {i})"
adi_add_bus "tx_cfg" "slave" \
"analog.com:interface:jesd204_tx_cfg_rtl:1.0" \
"analog.com:interface:jesd204_tx_cfg:1.0" \
{ \
{ "cfg_lanes_disable" "lanes_disable" } \
{ "cfg_links_disable" "links_disable" } \
{ "cfg_beats_per_multiframe" "beats_per_multiframe" } \
{ "cfg_octets_per_frame" "octets_per_frame" } \
{ "cfg_lmfc_offset" "lmfc_offset" } \
{ "cfg_sysref_oneshot" "sysref_oneshot" } \
{ "cfg_sysref_disable" "sysref_disable" } \
{ "cfg_continuous_cgs" "continuous_cgs" } \
{ "cfg_continuous_ilas" "continuous_ilas" } \
{ "cfg_skip_ilas" "skip_ilas" } \
{ "cfg_mframes_per_ilas" "mframes_per_ilas" } \
{ "cfg_disable_char_replacement" "disable_char_replacement" } \
{ "cfg_disable_scrambler" "disable_scrambler" } \
}
adi_add_bus "tx_ilas_config" "master" \
"analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" \
"analog.com:interface:jesd204_tx_ilas_config:1.0" \
{ \
{ "ilas_config_rd" "rd" } \
{ "ilas_config_addr" "addr" } \
{ "ilas_config_data" "data" } \
}
adi_add_bus "tx_event" "master" \
"analog.com:interface:jesd204_tx_event_rtl:1.0" \
"analog.com:interface:jesd204_tx_event:1.0" \
{ \
{ "event_sysref_alignment_error" "sysref_alignment_error" } \
{ "event_sysref_edge" "sysref_edge" } \
}
adi_add_bus "tx_status" "master" \
"analog.com:interface:jesd204_tx_status_rtl:1.0" \
"analog.com:interface:jesd204_tx_status:1.0" \
{ \
{ "status_state" "state" } \
{ "status_sync" "sync" } \
}
adi_add_bus "tx_ctrl" "slave" \
"analog.com:interface:jesd204_tx_ctrl_rtl:1.0" \
"analog.com:interface:jesd204_tx_ctrl:1.0" \
{ \
{ "ctrl_manual_sync_request" "manual_sync_request" } \
}
adi_add_bus_clock "clk" "tx_data:tx_cfg:tx_ilas_config:tx_event:tx_status:tx_ctrl" \
"reset"
adi_set_bus_dependency "tx_ilas_config" "tx_ilas_config" \
"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
adi_set_bus_dependency "tx_ctrl" "tx_ctrl" \
"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
adi_set_ports_dependency "sync" \
"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
set cc [ipx::current_core]
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
# Link layer mode
set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
ipgui::move_param -component $cc -order 0 $p -parent $page0
set_property -dict [list \
"display_name" "Link Layer mode" \
"tooltip" "Link Layer mode" \
"widget" "comboBox" \
] $p
set_property -dict [list \
value_validation_type pairs \
value_validation_pairs {64B66B 2 8B10B 1} \
] [ipx::get_user_parameters $p -of_objects $cc]
# Data width selection
set param [ipx::get_user_parameters DATA_PATH_WIDTH -of_objects $cc]
set_property -dict [list \
enablement_value false \
value_tcl_expr {expr $LINK_MODE*4} \
] $param
# SYSREF IOB placement
set param [ipx::add_user_parameter SYSREF_IOB $cc]
set_property -dict {value_resolve_type user value_format bool value true} $param
set param [ipgui::add_param -name {SYSREF_IOB} -component $cc -parent $page0]
set_property -dict [list \
display_name {Place SYSREF in IOB} \
widget {checkBox} \
show_label true \
] $param
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/jesd204/jesd204_tx/jesd204_tx_lane.v
+119
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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
`timescale 1ns/100ps
module jesd204_tx_lane #(
parameter DATA_PATH_WIDTH = 4
) (
input clk,
input [DATA_PATH_WIDTH-1:0] eof,
input eomf,
input cgs_enable,
input [DATA_PATH_WIDTH*8-1:0] ilas_data,
input [DATA_PATH_WIDTH-1:0] ilas_charisk,
input [DATA_PATH_WIDTH*8-1:0] tx_data,
input tx_ready,
output reg [DATA_PATH_WIDTH*8-1:0] phy_data,
output reg [DATA_PATH_WIDTH-1:0] phy_charisk,
input cfg_disable_scrambler
);
wire [DATA_PATH_WIDTH*8-1:0] scrambled_data;
wire [7:0] scrambled_char[0:DATA_PATH_WIDTH-1];
reg [7:0] char_align[0:DATA_PATH_WIDTH-1];
jesd204_scrambler #(
.WIDTH(DATA_PATH_WIDTH*8),
.DESCRAMBLE(0)
) i_scrambler (
.clk(clk),
.reset(~tx_ready),
.enable(~cfg_disable_scrambler),
.data_in(tx_data),
.data_out(scrambled_data)
);
generate
genvar i;
for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_char
assign scrambled_char[i] = scrambled_data[i*8+7:i*8];
always @(*) begin
if (i == DATA_PATH_WIDTH-1 && eomf == 1'b1) begin
char_align[i] = 8'h7c; // /A/
end else begin
char_align[i] = 8'hfc; // /F/
end
end
always @(posedge clk) begin
if (cgs_enable == 1'b1) begin
phy_charisk[i] <= 1'b1;
end else if (eof[i] == 1'b1 && scrambled_char[i] == char_align[i]) begin
phy_charisk[i] <= 1'b1;
end else begin
phy_charisk[i] <= ilas_charisk[i];
end
end
end
endgenerate
always @(posedge clk) begin
if (cgs_enable == 1'b1) begin
phy_data <= {DATA_PATH_WIDTH{8'hbc}};
end else begin
phy_data <= (tx_ready) ? scrambled_data : ilas_data;
end
end
endmodule
adi_library/jesd204/jesd204_tx/jesd204_tx_lane_64b.v
+143
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@@ -0,0 +1,143 @@
//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact [email protected] for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
`timescale 1ns/100ps
module jesd204_tx_lane_64b (
input clk,
input reset,
input [63:0] tx_data,
input tx_ready,
output reg [63:0] phy_data,
output [1:0] phy_header,
input lmc_edge,
input lmc_quarter_edge,
input eoemb,
// Scrambling mandatory in 64bxxb, keep this for debugging purposes
input cfg_disable_scrambler,
input [1:0] cfg_header_mode,
input cfg_lane_disable
);
reg [63:0] scrambled_data;
reg lmc_edge_d1 = 'b0;
reg lmc_edge_d2 = 'b0;
reg lmc_quarter_edge_d1 = 'b0;
reg lmc_quarter_edge_d2 = 'b0;
reg tx_ready_d1 = 'b0;
wire [63:0] tx_data_msb_s;
wire [63:0] scrambled_data_r;
wire [11:0] crc12;
/* Reorder octets MSB first */
genvar i;
generate
for (i = 0; i < 64; i = i + 8) begin: g_link_data
assign tx_data_msb_s[i+:8] = tx_data[64-1-i-:8];
end
endgenerate
jesd204_scrambler_64b #(
.WIDTH(64),
.DESCRAMBLE(0)
) i_scrambler (
.clk(clk),
.reset(reset),
.enable(~cfg_disable_scrambler),
.data_in(tx_data_msb_s),
.data_out(scrambled_data_r)
);
always @(posedge clk) begin
lmc_edge_d1 <= lmc_edge;
lmc_edge_d2 <= lmc_edge_d1;
lmc_quarter_edge_d1 <= lmc_quarter_edge;
lmc_quarter_edge_d2 <= lmc_quarter_edge_d1;
end
always @(posedge clk) begin
scrambled_data <= scrambled_data_r;
phy_data <= scrambled_data;
end
always @(posedge clk) begin
tx_ready_d1 <= tx_ready;
end
jesd204_crc12 i_crc12 (
.clk(clk),
.reset(~tx_ready_d1),
.init(lmc_edge_d2),
.data_in(scrambled_data),
.crc12(crc12)
);
jesd204_tx_header i_header_gen (
.clk(clk),
.reset(~tx_ready | cfg_lane_disable),
.cfg_header_mode(cfg_header_mode),
.lmc_edge(lmc_edge_d2),
.lmc_quarter_edge(lmc_quarter_edge_d2),
// Header content to be sent must be valid during lmc_edge
.eoemb(eoemb),
.crc3(3'b0),
.crc12(crc12),
.fec(26'b0),
.cmd(19'b0),
.header(phy_header)
);
endmodule
adi_library/jesd204/jesd204_tx/vivado.jou
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#-----------------------------------------------------------
# Vivado v2019.1.3 (64-bit)
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
# Start of session at: Thu Dec 9 15:17:28 2021
# Process ID: 6846
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx
# Command line: vivado -mode batch -source jesd204_tx_ip.tcl
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx/vivado.log
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx/vivado.jou
#-----------------------------------------------------------
source jesd204_tx_ip.tcl
adi_library/jesd204/jesd204_tx/vivado.log
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#-----------------------------------------------------------
# Vivado v2019.1.3 (64-bit)
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
# Start of session at: Thu Dec 9 15:17:28 2021
# Process ID: 6846
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx
# Command line: vivado -mode batch -source jesd204_tx_ip.tcl
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx/vivado.log
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx/vivado.jou
#-----------------------------------------------------------
source jesd204_tx_ip.tcl
# source ../../scripts/adi_env.tcl
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
## if [info exists ::env(ADI_HDL_DIR)] {
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
## }
## if [info exists ::env(ADI_GHDL_DIR)] {
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
## }
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
### variable auto_set_param_list
### variable auto_set_param_list_overwritable
### variable fpga_series_list
### variable fpga_family_list
### variable speed_grade_list
### variable dev_package_list
### variable xcvr_type_list
### variable fpga_voltage_list
### set auto_set_param_list { \
### DEV_PACKAGE \
### SPEED_GRADE \
### FPGA_FAMILY \
### FPGA_TECHNOLOGY }
### set auto_set_param_list_overwritable { \
### FPGA_VOLTAGE \
### XCVR_TYPE }
### set fpga_technology_list { \
### { Unknown 0 } \
### { 7series 1 } \
### { ultrascale 2 } \
### { ultrascale+ 3 }}
### set fpga_family_list { \
### { Unknown 0 } \
### { artix 1 } \
### { kintex 2 } \
### { virtex 3 } \
### { zynq 4 }}
### set speed_grade_list { \
### { Unknown 0 } \
### { -1 10 } \
### { -1L 11 } \
### { -1H 12 } \
### { -1HV 13 } \
### { -1LV 14 } \
### { -2 20 } \
### { -2L 21 } \
### { -2LV 22 } \
### { -3 30 }}
### set dev_package_list { \
### { Unknown 0 } \
### { rf 1 } \
### { fl 2 } \
### { ff 3 } \
### { fb 4 } \
### { hc 5 } \
### { fh 6 } \
### { cs 7 } \
### { cp 8 } \
### { ft 9 } \
### { fg 10 } \
### { sb 11 } \
### { rb 12 } \
### { rs 13 } \
### { cl 14 } \
### { sf 15 } \
### { ba 16 } \
### { fa 17 } \
### { fs 18 } \
### { fi 19 }}
### set xcvr_type_list { \
### { Unknown 0 } \
### { GTPE2_NOT_SUPPORTED 1 } \
### { GTXE2 2 } \
### { GTHE2_NOT_SUPPORTED 3 } \
### { GTZE2_NOT_SUPPORTED 4 } \
### { GTHE3 5 } \
### { GTYE3_NOT_SUPPORTED 6 } \
### { GTRE4_NOT_SUPPORTED 7 } \
### { GTHE4 8 } \
### { GTYE4 9 } \
### { GTME4_NOT_SUPPORTED 10}}
### set fpga_voltage_list {0 5000} ;
### proc adi_device_spec {cellpath param} {
###
### set list_pointer [string tolower $param]
### set list_pointer [append list_pointer "_list"]
###
### upvar 1 $list_pointer $list_pointer
###
### set ip [get_bd_cells $cellpath]
### set part [get_property PART [current_project]]
###
### switch -regexp -- $param {
### FPGA_TECHNOLOGY {
### switch -regexp -- $part {
### ^xc7 {set series_name 7series}
### ^xczu {set series_name ultrascale+}
### ^xc.u.p {set series_name ultrascale+}
### ^xc.u {set series_name ultrascale }
### default {
### puts "Undefined fpga technology for \"$part\"!"
### exit -1
### }
### }
### return "$series_name"
### }
### FPGA_FAMILY {
### set fpga_family [get_property FAMILY $part]
### foreach i $fpga_family_list {
### regexp ^[lindex $i 0] $fpga_family matched
### }
### return "$matched"
### }
### SPEED_GRADE {
### set speed_grade [get_property SPEED $part]
### return "$speed_grade"
### }
### DEV_PACKAGE {
### set dev_package [get_property PACKAGE $part]
### foreach i $dev_package_list {
### regexp ^[lindex $i 0] $dev_package matched
### }
### return "$matched"
### }
### XCVR_TYPE {
### set matched ""
### set dev_transcivers "none"
### foreach x [list_property $part] {
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
### }
### foreach i $xcvr_type_list {
### regexp ^[lindex $i 0] $dev_transcivers matched
### }
### if { $matched eq "" } {
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
### }
### return "$matched"
### }
### FPGA_VOLTAGE {
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
###
### return "$fpga_voltage"
### }
### default {
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
### }
### }
### }
## if {![info exists REQUIRED_VIVADO_VERSION]} {
## set REQUIRED_VIVADO_VERSION "2019.1"
## }
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
## set IGNORE_VERSION_CHECK 1
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
## set IGNORE_VERSION_CHECK 0
## }
## proc adi_ip_ttcl {ip_name ip_constr_files} {
##
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
## set_property -dict [list \
## type ttcl \
## ] $f
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
## }
## proc adi_ip_sim_ttcl {ip_name ip_files} {
##
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
## set f [ipx::add_file $ip_files $proj_filegroup]
## set_property -dict [list \
## type ttcl \
## ] $f
## ipx::reorder_files -front $ip_files $proj_filegroup
## }
## proc adi_ip_bd {ip_name ip_bd_files} {
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
## if {$proj_filegroup == {}} {
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
## }
##
## foreach file $ip_bd_files {
## set f [ipx::add_file $file $proj_filegroup]
## set_property -dict [list \
## type tclSource \
## ] $f
## }
## }
## proc adi_ip_infer_streaming_interfaces {ip_name} {
##
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
##
## }
## proc adi_ip_infer_mm_interfaces {ip_name} {
##
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
##
## }
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
## set_property ENABLEMENT_DEPENDENCY $dependency $port
## if {$driver_value != {}} {
## set_property DRIVER_VALUE $driver_value $port
## }
## }
## }
## proc adi_set_bus_dependency {bus prefix dependency} {
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
## adi_set_ports_dependency $prefix $dependency 0
## }
## proc adi_add_port_map {bus phys logic} {
## set map [ipx::add_port_map $phys $bus]
## set_property "PHYSICAL_NAME" $phys $map
## set_property "LOGICAL_NAME" $logic $map
## }
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
##
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
## set_property "BUS_TYPE_VLNV" $bus_type $bus
## set_property "INTERFACE_MODE" $mode $bus
##
## foreach port_map $port_maps {
## adi_add_port_map $bus {*}$port_map
## }
## }
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
## for {set i 0} {$i < $num} {incr i} {
## set bus_name [format "%s%d" $bus_name_prefix $i]
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
##
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
## set_property "BUS_TYPE_VLNV" $bus_type $bus
## set_property "INTERFACE_MODE" $mode $bus
##
## if {$dependency ne ""} {
## set bus_dependency [string map [list "{i}" $i] $dependency]
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
## }
##
## foreach port_map $port_maps {
## lassign $port_map phys logic width width_dep
## set map [ipx::add_port_map $phys $bus]
## set_property "PHYSICAL_NAME" $phys $map
## set_property "LOGICAL_NAME" $logic $map
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
## if {$width_dep ne ""} {
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
## set width_dep_r "(($width_dep) * $i)"
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
## }
## }
## }
## }
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
## set_property display_name $clock_inf_name $clock_inf
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
## set_property physical_name $clock_signal_name $clock_map
##
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
## set_property value $bus_inf_name $assoc_busif
##
## if { $reset_signal_name != "" } {
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
## set_property value $reset_signal_name $assoc_reset
##
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
## set_property display_name $reset_inf_name $reset_inf
## set_property interface_mode $reset_signal_mode $reset_inf
## set reset_map [ipx::add_port_map "RST" $reset_inf]
## set_property physical_name $reset_signal_name $reset_map
##
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
## set_property value "ACTIVE_LOW" $reset_polarity
## } else {
## set_property value "ACTIVE_HIGH" $reset_polarity
## }
## }
## }
## proc adi_ip_add_core_dependencies {vlnvs} {
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
## foreach vlnv $vlnvs {
## ipx::add_subcore $vlnv $file_group
## }
## }
## }
## proc adi_ip_create {ip_name} {
##
## global ad_hdl_dir
## global ad_ghdl_dir
## global REQUIRED_VIVADO_VERSION
## global IGNORE_VERSION_CHECK
##
## set VIVADO_VERSION [version -short]
## if {$IGNORE_VERSION_CHECK} {
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
## puts -nonewline "got $VIVADO_VERSION.\n"
## }
## } else {
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
## puts -nonewline "ERROR: vivado version mismatch; "
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
## puts -nonewline "got $VIVADO_VERSION.\n"
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
## exit 2
## }
## }
##
## create_project $ip_name . -force
##
## ## Load custom message severity definitions
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
##
## set lib_dirs $ad_hdl_dir/library
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
## lappend lib_dirs $ad_ghdl_dir/library
## }
##
## set_property ip_repo_paths $lib_dirs [current_fileset]
## update_ip_catalog
## }
## proc adi_ip_files {ip_name ip_files} {
## set proj_fileset [get_filesets sources_1]
## foreach m_file $ip_files {
## if {[file extension $m_file] eq ".xdc"} {
## add_files -norecurse -fileset constrs_1 $m_file
## } else {
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
## }
## }
## set_property "top" "$ip_name" $proj_fileset
## }
## proc adi_ip_properties_lite {ip_name} {
##
## global ad_hdl_dir
##
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
##
## set_property name $ip_name [ipx::current_core]
##
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
## set_property company_url {http://www.analog.com} [ipx::current_core]
##
## set i_families ""
## foreach i_part [get_parts] {
## lappend i_families [get_property FAMILY $i_part]
## }
## set i_families [lsort -unique $i_families]
## set s_families [get_property supported_families [ipx::current_core]]
## foreach i_family $i_families {
## set s_families "$s_families $i_family Production"
## set s_families "$s_families $i_family Beta"
## }
## set_property supported_families $s_families [ipx::current_core]
##
## ipx::save_core [ipx::current_core]
##
## ipx::remove_all_bus_interface [ipx::current_core]
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
## foreach map $memory_maps {
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
## }
##
## ipx::update_checksums [ipx::current_core]
## ipx::save_core [ipx::current_core]
## }
## proc adi_ip_properties {ip_name} {
##
## adi_ip_properties_lite $ip_name
##
## ipx::infer_bus_interface {\
## s_axi_awvalid \
## s_axi_awaddr \
## s_axi_awprot \
## s_axi_awready \
## s_axi_wvalid \
## s_axi_wdata \
## s_axi_wstrb \
## s_axi_wready \
## s_axi_bvalid \
## s_axi_bresp \
##
## s_axi_bready \
## s_axi_arvalid \
## s_axi_araddr \
## s_axi_arprot \
## s_axi_arready \
## s_axi_rvalid \
## s_axi_rdata \
## s_axi_rresp \
## s_axi_rready} \
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
##
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
##
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
##
## if {$raddr_width != $waddr_width} {
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
## set range 65536
## } else {
## if {$raddr_width >= 16} {
## set range 65536
## } else {
## set range [expr 1 << $raddr_width]
## }
## }
##
## ipx::add_memory_map {s_axi} [ipx::current_core]
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
## set_property range $range [ipx::get_address_blocks axi_lite \
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
## ipx::save_core
## }
## proc adi_init_bd_tcl {} {
##
## global auto_set_param_list
## global auto_set_param_list_overwritable
## set cc [ipx::current_core]
##
## if { [file exists bd] } {
## file delete -force bd
## }
## file mkdir bd
##
## set bd_tcl [open "bd/bd.tcl" w]
##
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
## puts $bd_tcl "proc init {cellpath otherInfo} {"
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
## puts $bd_tcl ""
## set auto_set_param ""
## foreach i $auto_set_param_list {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
## append auto_set_param " $i \\\n"
## }
## }
## if { $auto_set_param ne "" } {
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
## puts $bd_tcl $auto_set_param
## }
##
## set auto_set_overwritable_param ""
## foreach i $auto_set_param_list_overwritable {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
## append auto_set_overwritable_param " $i \\\n"
## }
## }
## if { $auto_set_overwritable_param ne "" } {
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
## puts $bd_tcl $auto_set_overwritable_param
## }
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
## puts $bd_tcl "}"
## puts $bd_tcl ""
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
## puts $bd_tcl ""
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
## puts $bd_tcl ""
## puts $bd_tcl " set parent_dir \"../\""
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
## puts $bd_tcl " break"
## puts $bd_tcl " }"
## puts $bd_tcl " append parent_dir \"../\""
## puts $bd_tcl " }"
## puts $bd_tcl ""
## puts $bd_tcl " # Find predefindes auto assignable parameters"
## puts $bd_tcl " foreach i \$auto_set_param_list {"
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
## puts $bd_tcl " }"
## puts $bd_tcl " }"
## puts $bd_tcl ""
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
## puts $bd_tcl " }"
## puts $bd_tcl " }"
## puts $bd_tcl "}"
## puts $bd_tcl ""
## close $bd_tcl
##
## set proj_fileset [get_filesets sources_1]
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
##
## set local_mk [open "temporary_case_dependencies.mk" w]
## seek $local_mk 0 start
## puts $local_mk "CLEAN_TARGET += bd"
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
## close $local_mk
## }
## proc adi_add_auto_fpga_spec_params {} {
##
## global auto_set_param_list
## global auto_set_param_list_overwritable
## set cc [ipx::current_core]
##
## foreach i $auto_set_param_list {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
## adi_add_device_spec_param $i
## }
## }
## foreach i $auto_set_param_list_overwritable {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
## adi_add_device_spec_param $i
## }
## }
## }
## proc adi_add_device_spec_param {ip_param} {
##
## set cc [ipx::current_core]
##
## set list_pointer [string tolower $ip_param]
## set list_pointer [append list_pointer "_list"]
##
## global $list_pointer
##
## # set j 1D list from the original list
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
##
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
## set_property -dict [list \
## "value_validation_type" "range_long" \
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
## [ipx::get_user_parameters $ip_param -of_objects $cc]
## } else {
## set_property -dict [list \
## "value_validation_type" "pairs" \
## "value_validation_pairs" $j ] \
## [ipx::get_user_parameters $ip_param -of_objects $cc]
## }
##
## # FPGA info grup
## set info_group_name "FPGA info"
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
## if { [string trim $info_group] eq "" } {
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
## -parent $page0 -display_name $info_group_name]
## }
##
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
## set_property -dict [list "widget" "comboBox" ] $p
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
## }
## proc adi_if_define {name} {
##
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
## ipx::create_bus_definition analog.com interface $name 1.0
##
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
##
## ipx::save_abstraction_definition [ipx::current_busabs]
## ipx::save_bus_definition [ipx::current_busdef]
## }
## proc adi_if_ports {dir width name {type none}} {
##
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
## set_property master_presence required $m_intf
## set_property slave_presence required $m_intf
## set_property master_width $width $m_intf
## set_property slave_width $width $m_intf
##
## set m_dir "in"
## set s_dir "out"
## if {$dir eq "output"} {
## set m_dir "out"
## set s_dir "in"
## }
##
## set_property master_direction $m_dir $m_intf
## set_property slave_direction $s_dir $m_intf
##
## if {$type ne "none"} {
## set_property is_${type} true $m_intf
## }
##
## ipx::save_bus_definition [ipx::current_busdef]
## ipx::save_abstraction_definition [ipx::current_busabs]
## }
## proc adi_if_infer_bus {if_name mode name maps} {
##
## ipx::add_bus_interface $name [ipx::current_core]
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
## set_property interface_mode $mode $m_bus_if
##
## foreach map $maps {
## set m_maps [regexp -all -inline {\S+} $map]
## lassign $m_maps p_name p_map
## ipx::add_port_map $p_name $m_bus_if
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
## }
## }
# adi_ip_create jesd204_tx
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
## set_msg_config -id {BD 41-1343} -new_severity WARNING
## set_msg_config -id {BD 41-1306} -new_severity WARNING
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
## set_msg_config -id {Synth 8-3331} -new_severity INFO
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx'.)
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
# adi_ip_files jesd204_tx [list \
# "jesd204_tx_lane.v" \
# "jesd204_tx_lane_64b.v" \
# "jesd204_tx_header.v" \
# "jesd204_tx_ctrl.v" \
# "jesd204_tx_constr.ttcl" \
# "jesd204_tx.v"
# ]
# adi_ip_properties_lite jesd204_tx
WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx/jesd204_tx_constr.ttcl' ignored by IP packager.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_data_r' has a dependency on the module local parameter or undefined parameter 'DW'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_charisk_r' has a dependency on the module local parameter or undefined parameter 'CW'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'phy_header_r' has a dependency on the module local parameter or undefined parameter 'HW'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'ilas_data' has a dependency on the module local parameter or undefined parameter 'DW'.
WARNING: [IP_Flow 19-5150] The Range '(NUM_LINKS - 1):0' is present in all ports of the interface 'status'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave.
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl_manual_request' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'ilas_config' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'phy' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master.
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'status' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'tx' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 'ilas_config'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'interface_if_gt_tx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
WARNING: [IP_Flow 19-5150] The Range '((32 * NUM_LANES) - 1):0' is present in all ports of the interface 'ilas_config'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
INFO: [IP_Flow 19-5151] The Range '1:0' is present in all ports of the interface 'ilas_config'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
WARNING: [IP_Flow 19-5464] No port map found for required logical port buffer_early_release on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave.
WARNING: [IP_Flow 19-5464] No port map found for required logical port buffer_delay on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave.
WARNING: [IP_Flow 19-5464] No port map found for required logical port frame_align_err_threshold on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave.
WARNING: [IP_Flow 19-5464] No port map found for required logical port err_statistics_reset on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave.
WARNING: [IP_Flow 19-5464] No port map found for required logical port err_statistics_mask on bus interface abstraction jesd204_rx_cfg_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'cfg' of definition 'analog.com:interface:jesd204_rx_cfg:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'tx'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
WARNING: [IP_Flow 19-5150] The Range '(((DATA_PATH_WIDTH * 8) * NUM_LANES) - 1):0' is present in all ports of the interface 'phy'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
INFO: [IP_Flow 19-5107] Inferred bus interface 'event' of definition 'analog.com:interface:jesd204_tx_event:1.0' (from User Repositories).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ctrl' of definition 'analog.com:interface:jesd204_tx_ctrl:1.0' (from User Repositories).
INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'lmfc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-818] Not transferring value dependency attribute "(LINK_MODE1 ? 8 : 4)" into user parameter "DATA_PATH_WIDTH".
WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_manual_request': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'ctrl_manual_request': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'ilas_config': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'phy_data' and definition port 'DATA'.
WARNING: [IP_Flow 19-1965] Bus Interface 'phy': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'status_sync' and definition port 'SYNC'.
WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'status': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'tx': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "buffer_early_release" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "buffer_delay" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "frame_align_err_threshold" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_reset" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'cfg': A port map to the required logical port "err_statistics_mask" of the bus abstraction "analog.com:interface:jesd204_rx_cfg_rtl:1.0" is missing.
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
WARNING: [IP_Flow 19-3153] Bus Interface 'lmfc_clk': ASSOCIATED_BUSIF bus parameter is missing.
WARNING: [IP_Flow 19-4751] Bus Interface 'lmfc_clk': FREQ_HZ bus parameter is missing for output clock interface.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
# adi_ip_ttcl jesd204_tx "jesd204_tx_constr.ttcl"
# adi_ip_add_core_dependencies { \
# analog.com:user:jesd204_common:1.0 \
# analog.com:user:util_cdc:1.0 \
# }
# set_property display_name "ADI JESD204 Transmit" [ipx::current_core]
# set_property description "ADI JESD204 Transmit" [ipx::current_core]
# adi_add_bus "tx_data" "slave" \
# "xilinx.com:interface:axis_rtl:1.0" \
# "xilinx.com:interface:axis:1.0" \
# { \
# { "tx_valid" "TVALID" } \
# { "tx_ready" "TREADY" } \
# { "tx_data" "TDATA" } \
# }
# adi_add_multi_bus 16 "tx_phy" "master" \
# "xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0" \
# "xilinx.com:display_jesd204:jesd204_tx_bus:1.0" \
# [list \
# { "phy_data" "txdata" 32 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')) * 8)"} \
# { "phy_charisk" "txcharisk" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \
# { "phy_header" "txheader" 2} \
# ] \
# "(spirit:decode(id('MODELPARAM_VALUE.NUM_LANES')) > {i})"
# adi_add_bus "tx_cfg" "slave" \
# "analog.com:interface:jesd204_tx_cfg_rtl:1.0" \
# "analog.com:interface:jesd204_tx_cfg:1.0" \
# { \
# { "cfg_lanes_disable" "lanes_disable" } \
# { "cfg_links_disable" "links_disable" } \
# { "cfg_beats_per_multiframe" "beats_per_multiframe" } \
# { "cfg_octets_per_frame" "octets_per_frame" } \
# { "cfg_lmfc_offset" "lmfc_offset" } \
# { "cfg_sysref_oneshot" "sysref_oneshot" } \
# { "cfg_sysref_disable" "sysref_disable" } \
# { "cfg_continuous_cgs" "continuous_cgs" } \
# { "cfg_continuous_ilas" "continuous_ilas" } \
# { "cfg_skip_ilas" "skip_ilas" } \
# { "cfg_mframes_per_ilas" "mframes_per_ilas" } \
# { "cfg_disable_char_replacement" "disable_char_replacement" } \
# { "cfg_disable_scrambler" "disable_scrambler" } \
# }
# adi_add_bus "tx_ilas_config" "master" \
# "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" \
# "analog.com:interface:jesd204_tx_ilas_config:1.0" \
# { \
# { "ilas_config_rd" "rd" } \
# { "ilas_config_addr" "addr" } \
# { "ilas_config_data" "data" } \
# }
# adi_add_bus "tx_event" "master" \
# "analog.com:interface:jesd204_tx_event_rtl:1.0" \
# "analog.com:interface:jesd204_tx_event:1.0" \
# { \
# { "event_sysref_alignment_error" "sysref_alignment_error" } \
# { "event_sysref_edge" "sysref_edge" } \
# }
# adi_add_bus "tx_status" "master" \
# "analog.com:interface:jesd204_tx_status_rtl:1.0" \
# "analog.com:interface:jesd204_tx_status:1.0" \
# { \
# { "status_state" "state" } \
# { "status_sync" "sync" } \
# }
# adi_add_bus "tx_ctrl" "slave" \
# "analog.com:interface:jesd204_tx_ctrl_rtl:1.0" \
# "analog.com:interface:jesd204_tx_ctrl:1.0" \
# { \
# { "ctrl_manual_sync_request" "manual_sync_request" } \
# }
# adi_add_bus_clock "clk" "tx_data:tx_cfg:tx_ilas_config:tx_event:tx_status:tx_ctrl" \
# "reset"
# adi_set_bus_dependency "tx_ilas_config" "tx_ilas_config" \
# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
# adi_set_bus_dependency "tx_ctrl" "tx_ctrl" \
# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
# adi_set_ports_dependency "sync" \
# "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
# set cc [ipx::current_core]
# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
# set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
# ipgui::move_param -component $cc -order 0 $p -parent $page0
# set_property -dict [list \
# "display_name" "Link Layer mode" \
# "tooltip" "Link Layer mode" \
# "widget" "comboBox" \
# ] $p
# set_property -dict [list \
# value_validation_type pairs \
# value_validation_pairs {64B66B 2 8B10B 1} \
# ] [ipx::get_user_parameters $p -of_objects $cc]
# set param [ipx::get_user_parameters DATA_PATH_WIDTH -of_objects $cc]
# set_property -dict [list \
# enablement_value false \
# value_tcl_expr {expr $LINK_MODE*4} \
# ] $param
# set param [ipx::add_user_parameter SYSREF_IOB $cc]
# set_property -dict {value_resolve_type user value_format bool value true} $param
# set param [ipgui::add_param -name {SYSREF_IOB} -component $cc -parent $page0]
# set_property -dict [list \
# display_name {Place SYSREF in IOB} \
# widget {checkBox} \
# show_label true \
# ] $param
# ipx::create_xgui_files [ipx::current_core]
# ipx::save_core [ipx::current_core]
INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:17:38 2021...
adi_library/jesd204/jesd204_tx/xgui/jesd204_tx_v1_0.tcl
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# Loading additional proc with user specified bodies to compute parameter values.
source [file join [file dirname [file dirname [info script]]] gui/jesd204_tx_v1_0.gtcl]
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "LINK_MODE" -parent ${Page_0} -widget comboBox
ipgui::add_param $IPINST -name "DATA_PATH_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "NUM_LANES" -parent ${Page_0}
ipgui::add_param $IPINST -name "NUM_LINKS" -parent ${Page_0}
ipgui::add_param $IPINST -name "NUM_OUTPUT_PIPELINE" -parent ${Page_0}
ipgui::add_param $IPINST -name "SYSREF_IOB" -parent ${Page_0}
}
proc update_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH PARAM_VALUE.LINK_MODE } {
# Procedure called to update DATA_PATH_WIDTH when any of the dependent parameters in the arguments change
set DATA_PATH_WIDTH ${PARAM_VALUE.DATA_PATH_WIDTH}
set LINK_MODE ${PARAM_VALUE.LINK_MODE}
set values(LINK_MODE) [get_property value $LINK_MODE]
set_property value [gen_USERPARAMETER_DATA_PATH_WIDTH_VALUE $values(LINK_MODE)] $DATA_PATH_WIDTH
}
proc validate_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH } {
# Procedure called to validate DATA_PATH_WIDTH
return true
}
proc update_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } {
# Procedure called to update LINK_MODE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } {
# Procedure called to validate LINK_MODE
return true
}
proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
# Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
# Procedure called to validate NUM_LANES
return true
}
proc update_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } {
# Procedure called to update NUM_LINKS when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } {
# Procedure called to validate NUM_LINKS
return true
}
proc update_PARAM_VALUE.NUM_OUTPUT_PIPELINE { PARAM_VALUE.NUM_OUTPUT_PIPELINE } {
# Procedure called to update NUM_OUTPUT_PIPELINE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_OUTPUT_PIPELINE { PARAM_VALUE.NUM_OUTPUT_PIPELINE } {
# Procedure called to validate NUM_OUTPUT_PIPELINE
return true
}
proc update_PARAM_VALUE.SYSREF_IOB { PARAM_VALUE.SYSREF_IOB } {
# Procedure called to update SYSREF_IOB when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SYSREF_IOB { PARAM_VALUE.SYSREF_IOB } {
# Procedure called to validate SYSREF_IOB
return true
}
proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES}
}
proc update_MODELPARAM_VALUE.NUM_LINKS { MODELPARAM_VALUE.NUM_LINKS PARAM_VALUE.NUM_LINKS } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_LINKS}] ${MODELPARAM_VALUE.NUM_LINKS}
}
proc update_MODELPARAM_VALUE.NUM_OUTPUT_PIPELINE { MODELPARAM_VALUE.NUM_OUTPUT_PIPELINE PARAM_VALUE.NUM_OUTPUT_PIPELINE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_OUTPUT_PIPELINE}] ${MODELPARAM_VALUE.NUM_OUTPUT_PIPELINE}
}
proc update_MODELPARAM_VALUE.LINK_MODE { MODELPARAM_VALUE.LINK_MODE PARAM_VALUE.LINK_MODE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.LINK_MODE}] ${MODELPARAM_VALUE.LINK_MODE}
}
proc update_MODELPARAM_VALUE.DATA_PATH_WIDTH { MODELPARAM_VALUE.DATA_PATH_WIDTH PARAM_VALUE.DATA_PATH_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DATA_PATH_WIDTH}] ${MODELPARAM_VALUE.DATA_PATH_WIDTH}
}