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//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact [email protected] for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module jesd204_tx_ctrl #(
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parameter NUM_LANES = 1,
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parameter NUM_LINKS = 1,
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parameter DATA_PATH_WIDTH = 4
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) (
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input clk,
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input reset,
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input [NUM_LINKS-1:0] sync,
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input lmfc_edge,
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output reg [NUM_LANES-1:0] lane_cgs_enable,
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output reg eof_reset,
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output reg tx_ready,
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output reg [DATA_PATH_WIDTH*8*NUM_LANES-1:0] ilas_data,
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output reg [DATA_PATH_WIDTH-1:0] ilas_charisk,
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output reg [1:0] ilas_config_addr,
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output reg ilas_config_rd,
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input [DATA_PATH_WIDTH*8*NUM_LANES-1:0] ilas_config_data,
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input [NUM_LANES-1:0] cfg_lanes_disable,
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input [NUM_LINKS-1:0] cfg_links_disable,
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input cfg_continuous_cgs,
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input cfg_continuous_ilas,
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input cfg_skip_ilas,
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input [7:0] cfg_mframes_per_ilas,
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input cfg_disable_char_replacement,
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input ctrl_manual_sync_request,
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output [NUM_LINKS-1:0] status_sync,
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output reg [1:0] status_state
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);
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reg lmfc_edge_d1 = 1'b0;
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reg lmfc_edge_d2 = 1'b0;
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reg ilas_reset = 1'b1;
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reg ilas_data_reset = 1'b1;
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reg sync_request = 1'b0;
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reg sync_request_received = 1'b0;
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reg [7:0] mframe_counter = 'h00;
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reg [5:0] ilas_counter = 'h00;
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reg ilas_config_rd_d1 = 1'b1;
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reg last_ilas_mframe = 1'b0;
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reg cgs_enable = 1'b1;
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wire [NUM_LINKS-1:0] status_sync_masked;
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sync_bits #(
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.NUM_OF_BITS (NUM_LINKS))
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i_cdc_sync (
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.in_bits(sync),
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.out_clk(clk),
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.out_resetn(1'b1),
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.out_bits(status_sync)
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);
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assign status_sync_masked = status_sync | cfg_links_disable;
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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sync_request <= {NUM_LINKS{1'b0}};
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end else begin
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/* TODO: SYNC must be asserted at least 4 frames before interpreted as a
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* sync request and the /K28.5/ symbol generation has lasted for at
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* least 1 frame + 9 octets */
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if (cfg_continuous_cgs == 1'b1) begin
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sync_request <= 1'b1;
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end else begin
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sync_request <= ~(&status_sync_masked) | ctrl_manual_sync_request;
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end
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end
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end
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always @(posedge clk) begin
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if (sync_request == 1'b0 && sync_request_received == 1'b1) begin
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lmfc_edge_d1 <= lmfc_edge;
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lmfc_edge_d2 <= lmfc_edge_d1;
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end else begin
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lmfc_edge_d1 <= 1'b0;
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lmfc_edge_d2 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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sync_request_received <= 1'b0;
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end else if (sync_request == 1'b1) begin
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sync_request_received <= 1'b1;
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end
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end
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always @(posedge clk) begin
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if (cfg_skip_ilas == 1'b1 ||
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mframe_counter == cfg_mframes_per_ilas) begin
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last_ilas_mframe <= 1'b1;
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end else begin
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last_ilas_mframe <= 1'b0;
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end
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end
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localparam STATE_WAIT = 2'b00;
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localparam STATE_CGS = 2'b01;
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localparam STATE_ILAS = 2'b10;
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localparam STATE_DATA = 2'b11;
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/* Timeline
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*
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* #1 lmfc_edge == 1, ilas_reset update
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* #2 eof_reset update
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* #3 {lane_,}cgs_enable, tx_ready update
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*
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* One multi-frame should at least be 3 clock cycles (TBD 64-bit data path)
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*/
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always @(posedge clk) begin
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if (sync_request == 1'b1 || reset == 1'b1) begin
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cgs_enable <= 1'b1;
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lane_cgs_enable <= {NUM_LANES{1'b1}};
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tx_ready <= 1'b0;
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eof_reset <= 1'b1;
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ilas_reset <= 1'b1;
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ilas_data_reset <= 1'b1;
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if (sync_request_received == 1'b0) begin
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status_state <= STATE_WAIT;
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end else begin
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status_state <= STATE_CGS;
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end
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end else if (sync_request_received == 1'b1) begin
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if (lmfc_edge == 1'b1 && last_ilas_mframe == 1'b1) begin
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ilas_reset <= 1'b1;
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status_state <= STATE_DATA;
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end else if (lmfc_edge_d1 == 1'b1 && (cfg_continuous_ilas == 1'b1 ||
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cgs_enable == 1'b1)) begin
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ilas_reset <= 1'b0;
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status_state <= STATE_ILAS;
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end
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if (lmfc_edge_d1 == 1'b1) begin
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if (last_ilas_mframe == 1'b1 && cfg_continuous_ilas == 1'b0) begin
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eof_reset <= cfg_disable_char_replacement;
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ilas_data_reset <= 1'b1;
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end else if (cgs_enable == 1'b1) begin
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ilas_data_reset <= 1'b0;
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end
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end
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if (lmfc_edge_d2 == 1'b1) begin
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lane_cgs_enable <= cfg_lanes_disable;
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cgs_enable <= 1'b0;
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if (last_ilas_mframe == 1'b1 && cfg_continuous_ilas == 1'b0) begin
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tx_ready <= 1'b1;
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end
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end
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end
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end
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always @(posedge clk) begin
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if (ilas_reset == 1'b1) begin
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mframe_counter <= 'h00;
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end else if (lmfc_edge_d1 == 1'b1) begin
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mframe_counter <= mframe_counter + 1'b1;
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end
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end
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always @(posedge clk) begin
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if (ilas_reset == 1'b1) begin
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ilas_config_rd <= 1'b0;
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end else if (mframe_counter == 'h00 && lmfc_edge == 1'b1) begin
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ilas_config_rd <= 1'b1;
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end else if (ilas_config_addr == 'h3) begin
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ilas_config_rd <= 1'b0;
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end
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ilas_config_rd_d1 <= ilas_config_rd;
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end
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always @(posedge clk) begin
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if (ilas_config_rd == 1'b0) begin
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ilas_config_addr <= 'h00;
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end else begin
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ilas_config_addr <= ilas_config_addr + 1'b1;
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end
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end
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always @(posedge clk) begin
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if (ilas_reset == 1'b1) begin
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ilas_counter <= 'h00;
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end else begin
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ilas_counter <= ilas_counter + 1'b1;
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end
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end
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wire [31:0] ilas_default_data = {
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ilas_counter,2'h3,
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ilas_counter,2'h2,
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ilas_counter,2'h1,
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ilas_counter,2'h0
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};
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always @(posedge clk) begin
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if (ilas_data_reset == 1'b1) begin
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ilas_data <= {NUM_LANES{32'h00}};
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ilas_charisk <= 4'b0000;
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end else begin
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if (ilas_config_rd_d1 == 1'b1) begin
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case (ilas_config_addr)
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2'h1: begin
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ilas_data <= (ilas_config_data & {NUM_LANES{32'hffff0000}}) |
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{NUM_LANES{16'h00,8'h9c,8'h1c}}; // /Q/ /R/
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ilas_charisk <= 4'b0011;
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end
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default: begin
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ilas_data <= ilas_config_data;
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ilas_charisk <= 4'b0000;
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end
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endcase
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end else if (lmfc_edge_d2 == 1'b1) begin
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ilas_data <= {NUM_LANES{ilas_default_data[31:8],8'h1c}}; // /R/
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ilas_charisk <= 4'b0001;
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end else if (lmfc_edge_d1 == 1'b1) begin
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ilas_data <= {NUM_LANES{8'h7c,ilas_default_data[23:0]}}; // /A/
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ilas_charisk <= 4'b1000;
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end else begin
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ilas_data <= {NUM_LANES{ilas_default_data}};
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ilas_charisk <= 4'b0000;
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end
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end
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end
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endmodule
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