Archived
initial commit
This commit is contained in:
@@ -0,0 +1,2 @@
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run/
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vcd/
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@@ -0,0 +1,17 @@
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#!/bin/bash
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SOURCE="axi_jesd204_rx_regmap_tb.v"
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SOURCE+=" ../axi_jesd204_rx/axi_jesd204_rx.v"
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SOURCE+=" ../axi_jesd204_rx/jesd204_up_rx.v"
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SOURCE+=" ../axi_jesd204_rx/jesd204_up_rx_lane.v"
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SOURCE+=" ../axi_jesd204_rx/jesd204_up_ilas_mem.v"
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SOURCE+=" ../axi_jesd204_common/jesd204_up_common.v"
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SOURCE+=" ../axi_jesd204_common/jesd204_up_sysref.v"
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SOURCE+=" ../../common/up_clock_mon.v"
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SOURCE+=" ../../common/up_axi.v"
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SOURCE+=" ../../util_cdc/sync_bits.v"
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SOURCE+=" ../../util_cdc/sync_data.v"
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SOURCE+=" ../../util_cdc/sync_event.v"
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cd `dirname $0`
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source run_tb.sh
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@@ -0,0 +1,378 @@
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//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
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`timescale 1ns/100ps
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module axi_jesd204_rx_regmap_tb;
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parameter VCD_FILE = "axi_jesd204_rx_regmap_tb.vcd";
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parameter NUM_LANES = 2;
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parameter NUM_LINKS = 1;
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`define TIMEOUT 1000000
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`include "tb_base.v"
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reg core_clk = 1'b0;
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always @(*) #4 core_clk <= ~core_clk;
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wire s_axi_aclk = clk;
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wire s_axi_aresetn = ~reset;
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reg s_axi_awvalid = 1'b0;
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reg s_axi_wvalid = 1'b0;
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reg [13:0] s_axi_awaddr = 'h00;
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reg [31:0] s_axi_wdata = 'h00;
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wire [1:0] s_axi_bresp;
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wire s_axi_awready;
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wire s_axi_wready;
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wire s_axi_bready = 1'b1;
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wire [3:0] s_axi_wstrb = 4'b1111;
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wire [2:0] s_axi_awprot = 3'b000;
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wire [2:0] s_axi_arprot = 3'b000;
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wire [1:0] s_axi_rresp;
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wire [31:0] s_axi_rdata;
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wire [NUM_LANES*32-1:0] core_status_err_statistics_cnt;
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reg [31:0] expected_reg_mem[0:1023];
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task write_reg;
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input [31:0] addr;
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input [31:0] value;
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begin
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@(posedge s_axi_aclk)
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s_axi_awvalid <= 1'b1;
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s_axi_wvalid <= 1'b1;
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s_axi_awaddr <= addr;
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s_axi_wdata <= value;
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@(posedge s_axi_aclk)
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while (s_axi_awvalid || s_axi_wvalid) begin
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@(posedge s_axi_aclk)
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if (s_axi_awready)
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s_axi_awvalid <= 1'b0;
|
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if (s_axi_wready)
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s_axi_wvalid <= 1'b0;
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end
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end
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endtask
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reg [13:0] s_axi_araddr = 'h0;
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reg s_axi_arvalid = 'h0;
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reg s_axi_rready = 'h0;
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wire s_axi_arready;
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wire s_axi_rvalid;
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task read_reg;
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input [31:0] addr;
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output [31:0] value;
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begin
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s_axi_arvalid <= 1'b1;
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s_axi_araddr <= addr;
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s_axi_rready <= 1'b1;
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@(posedge s_axi_aclk) #0;
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while (s_axi_arvalid) begin
|
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if (s_axi_arready == 1'b1) begin
|
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s_axi_arvalid <= 1'b0;
|
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end
|
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@(posedge s_axi_aclk) #0;
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end
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while (s_axi_rready) begin
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if (s_axi_rvalid == 1'b1) begin
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value <= s_axi_rdata;
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s_axi_rready <= 1'b0;
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end
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@(posedge s_axi_aclk) #0;
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end
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end
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endtask
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task read_reg_check;
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input [31:0] addr;
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output match;
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reg [31:0] value;
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reg [31:0] expected;
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begin
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read_reg(addr, value);
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expected = expected_reg_mem[addr[13:2]];
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match <= value === expected;
|
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if (value !== expected) begin
|
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$display("Address %h, Expected %h, Found %h", addr, expected, value);
|
||||
end
|
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end
|
||||
endtask
|
||||
|
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reg read_match = 1'b1;
|
||||
|
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always @(posedge clk) begin
|
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if (read_match == 1'b0) begin
|
||||
failed <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
task set_reset_reg_value;
|
||||
input [31:0] addr;
|
||||
input [31:0] value;
|
||||
begin
|
||||
expected_reg_mem[addr[13:2]] <= value;
|
||||
end
|
||||
endtask
|
||||
|
||||
task initialize_expected_reg_mem;
|
||||
integer i;
|
||||
begin
|
||||
for (i = 0; i < 1024; i = i + 1)
|
||||
expected_reg_mem[i] <= 'h00;
|
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/* Non zero power-on-reset values */
|
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set_reset_reg_value('h00, 32'h00010261); /* PCORE version register */
|
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set_reset_reg_value('h0c, 32'h32303452); /* PCORE magic register */
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set_reset_reg_value('h10, NUM_LANES); /* Number of lanes */
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set_reset_reg_value('h18, NUM_LINKS); /* Number of links */
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||||
set_reset_reg_value('h40, 32'h00000100); /* Elastic buffer size */
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set_reset_reg_value('h14, 'h2); /* Datapath width */
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set_reset_reg_value('hc0, 'h1); /* Core reset */
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set_reset_reg_value('hc4, 'h1); /* Core state */
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// set_reset_reg_value('hc8, 'h28000); /* clock monitor */
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set_reset_reg_value('h210, 'h3); /* OCTETS_PER_MULTIFRAME */
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|
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/* Lane error statistics */
|
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for (i = 0; i < NUM_LANES; i = i + 1) begin
|
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set_reset_reg_value('h308 + i*'h20, core_status_err_statistics_cnt[32*i+:32]);
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end
|
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end
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endtask
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|
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task check_all_registers;
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||||
integer i;
|
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begin
|
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for (i = 0; i < 'h400; i = i + 4) begin
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read_reg_check(i, read_match);
|
||||
end
|
||||
end
|
||||
endtask
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|
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task write_reg_and_update;
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input [31:0] addr;
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input [31:0] value;
|
||||
integer i;
|
||||
begin
|
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write_reg(addr, value);
|
||||
expected_reg_mem[addr[13:2]] <= value;
|
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|
||||
if (addr == 'hc0) begin
|
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expected_reg_mem['hc4/4][0] <= value[0];
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
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task invert_register;
|
||||
input [31:0] addr;
|
||||
reg [31:0] value;
|
||||
begin
|
||||
read_reg(addr, value);
|
||||
write_reg(addr, ~value);
|
||||
end
|
||||
endtask
|
||||
|
||||
task invert_all_registers;
|
||||
integer i;
|
||||
begin
|
||||
for (i = 0; i < 'h400; i = i + 4) begin
|
||||
invert_register(i);
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* ILAS memory */
|
||||
|
||||
reg core_ilas_config_valid = 1'b0;
|
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reg [1:0] core_ilas_config_addr = 2'b00;
|
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wire [NUM_LANES*32-1:0] core_ilas_config_data;
|
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|
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generate
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genvar l;
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for (l = 0; l < NUM_LANES; l = l + 1) begin
|
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localparam [3:0] l2 = l;
|
||||
assign core_ilas_config_data[32*l+31:32*l] = {
|
||||
l2,core_ilas_config_addr,2'h3,
|
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l2,core_ilas_config_addr,2'h2,
|
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l2,core_ilas_config_addr,2'h1,
|
||||
l2,core_ilas_config_addr,2'h0
|
||||
};
|
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|
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assign core_status_err_statistics_cnt[32*l+:32] = {28'hffaa550,l2};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
task set_ilas_registers;
|
||||
integer i;
|
||||
reg [3:0] lane;
|
||||
begin
|
||||
for (i = 0; i < 4; i = i + 1) begin
|
||||
@(posedge core_clk)
|
||||
core_ilas_config_valid <= 1'b1;
|
||||
core_ilas_config_addr <= i;
|
||||
end
|
||||
@(posedge core_clk)
|
||||
core_ilas_config_valid <= 1'b0;
|
||||
core_ilas_config_addr <= 0;
|
||||
@(posedge core_clk) #0;
|
||||
|
||||
/* Update the expected values */
|
||||
for (i = 0; i < NUM_LANES * 'h20; i = i + 'h20) begin
|
||||
lane = i / 20;
|
||||
set_reset_reg_value('h300 + i, 'h20);
|
||||
set_reset_reg_value('h310 + i, 'h03020100 | {4{lane,4'h0}});
|
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set_reset_reg_value('h314 + i, 'h07060504 | {4{lane,4'h0}});
|
||||
set_reset_reg_value('h318 + i, 'h0b0a0908 | {4{lane,4'h0}});
|
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set_reset_reg_value('h31c + i, 'h0f0e0d0c | {4{lane,4'h0}});
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
integer i;
|
||||
initial begin
|
||||
#1;
|
||||
initialize_expected_reg_mem();
|
||||
@(posedge s_axi_aresetn)
|
||||
check_all_registers();
|
||||
|
||||
/* Check scratch */
|
||||
write_reg_and_update('h08, 32'h12345678);
|
||||
check_all_registers();
|
||||
|
||||
/* Check IRQ mask */
|
||||
write_reg_and_update('h80, 32'h0);
|
||||
check_all_registers();
|
||||
|
||||
/* Check lanes enable */
|
||||
write_reg_and_update('h200, {NUM_LANES{1'b1}});
|
||||
check_all_registers();
|
||||
|
||||
/* Check JESD common config */
|
||||
write_reg_and_update('h210, 32'hff03ff);
|
||||
check_all_registers();
|
||||
write_reg_and_update('h214, 32'h03);
|
||||
check_all_registers();
|
||||
|
||||
/* Check links enable */
|
||||
write_reg_and_update('h218, {NUM_LINKS{1'b1}});
|
||||
check_all_registers();
|
||||
|
||||
/* Check JESD RX configuration */
|
||||
write_reg_and_update('h240, 32'h103fc);
|
||||
check_all_registers();
|
||||
|
||||
/* Reset core */
|
||||
write_reg_and_update('hc0, 32'h0);
|
||||
check_all_registers();
|
||||
|
||||
/* Should be read-only when core is out of reset */
|
||||
invert_register('h200); /* lanes enable */
|
||||
invert_register('h210); /* octets per frame, beats per multiframe */
|
||||
invert_register('h218); /* links enable */
|
||||
invert_register('h240); /* char replacement, scrambler */
|
||||
|
||||
check_all_registers();
|
||||
|
||||
/* Check ILAS */
|
||||
set_ilas_registers();
|
||||
check_all_registers();
|
||||
|
||||
/* Check that reset works for all registers */
|
||||
do_trigger_reset();
|
||||
initialize_expected_reg_mem();
|
||||
check_all_registers();
|
||||
invert_all_registers();
|
||||
do_trigger_reset();
|
||||
check_all_registers();
|
||||
end
|
||||
|
||||
axi_jesd204_rx #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.NUM_LINKS(NUM_LINKS)
|
||||
) i_axi (
|
||||
.s_axi_aclk(s_axi_aclk),
|
||||
.s_axi_aresetn(s_axi_aresetn),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
|
||||
.core_clk(core_clk),
|
||||
.core_reset_ext(1'b0),
|
||||
|
||||
.core_ilas_config_valid({NUM_LANES{core_ilas_config_valid}}),
|
||||
.core_ilas_config_addr({NUM_LANES{core_ilas_config_addr}}),
|
||||
.core_ilas_config_data(core_ilas_config_data),
|
||||
|
||||
.core_event_sysref_alignment_error(1'b0),
|
||||
.core_event_sysref_edge(1'b0),
|
||||
|
||||
.core_status_err_statistics_cnt(core_status_err_statistics_cnt),
|
||||
.core_ctrl_err_statistics_mask(),
|
||||
.core_ctrl_err_statistics_reset(),
|
||||
|
||||
.core_status_ctrl_state(2'b00),
|
||||
.core_status_lane_cgs_state(4'b0000),
|
||||
.core_status_lane_ifs_ready({NUM_LANES{1'b0}}),
|
||||
.core_status_lane_latency({NUM_LANES{14'h00}})
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,15 @@
|
||||
#!/bin/bash
|
||||
|
||||
SOURCE="axi_jesd204_tx_regmap_tb.v"
|
||||
SOURCE+=" ../axi_jesd204_tx/axi_jesd204_tx.v"
|
||||
SOURCE+=" ../axi_jesd204_tx/jesd204_up_tx.v"
|
||||
SOURCE+=" ../axi_jesd204_common/jesd204_up_common.v"
|
||||
SOURCE+=" ../axi_jesd204_common/jesd204_up_sysref.v"
|
||||
SOURCE+=" ../../common/up_axi.v"
|
||||
SOURCE+=" ../../common/up_clock_mon.v"
|
||||
SOURCE+=" ../../util_cdc/sync_bits.v"
|
||||
SOURCE+=" ../../util_cdc/sync_data.v"
|
||||
SOURCE+=" ../../util_cdc/sync_event.v"
|
||||
|
||||
cd `dirname $0`
|
||||
source run_tb.sh
|
||||
@@ -0,0 +1,366 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_jesd204_tx_regmap_tb;
|
||||
parameter VCD_FILE = "axi_jesd204_tx_regmap_tb.vcd";
|
||||
parameter NUM_LANES = 2;
|
||||
parameter NUM_LINKS = 2;
|
||||
|
||||
`define TIMEOUT 1000000
|
||||
`include "tb_base.v"
|
||||
|
||||
reg [1:0] core_status_state = 2'b00;
|
||||
reg [NUM_LINKS-1:0] core_status_sync = {NUM_LINKS{1'b0}};
|
||||
|
||||
wire s_axi_aclk = clk;
|
||||
wire s_axi_aresetn = ~reset;
|
||||
|
||||
reg s_axi_awvalid = 1'b0;
|
||||
reg s_axi_wvalid = 1'b0;
|
||||
reg [13:0] s_axi_awaddr = 'h00;
|
||||
reg [31:0] s_axi_wdata = 'h00;
|
||||
wire [1:0] s_axi_bresp;
|
||||
wire s_axi_awready;
|
||||
wire s_axi_wready;
|
||||
wire s_axi_bready = 1'b1;
|
||||
wire [3:0] s_axi_wstrb = 4'b1111;
|
||||
wire [2:0] s_axi_awprot = 3'b000;
|
||||
wire [2:0] s_axi_arprot = 3'b000;
|
||||
wire [1:0] s_axi_rresp;
|
||||
wire [31:0] s_axi_rdata;
|
||||
|
||||
reg [31:0] expected_reg_mem[0:1023];
|
||||
|
||||
task write_reg;
|
||||
input [31:0] addr;
|
||||
input [31:0] value;
|
||||
begin
|
||||
@(posedge s_axi_aclk)
|
||||
s_axi_awvalid <= 1'b1;
|
||||
s_axi_wvalid <= 1'b1;
|
||||
s_axi_awaddr <= addr;
|
||||
s_axi_wdata <= value;
|
||||
@(posedge s_axi_aclk)
|
||||
while (s_axi_awvalid || s_axi_wvalid) begin
|
||||
@(posedge s_axi_aclk)
|
||||
if (s_axi_awready)
|
||||
s_axi_awvalid <= 1'b0;
|
||||
if (s_axi_wready)
|
||||
s_axi_wvalid <= 1'b0;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
reg [13:0] s_axi_araddr = 'h0;
|
||||
reg s_axi_arvalid = 'h0;
|
||||
reg s_axi_rready = 'h0;
|
||||
wire s_axi_arready;
|
||||
wire s_axi_rvalid;
|
||||
|
||||
task read_reg;
|
||||
input [31:0] addr;
|
||||
output [31:0] value;
|
||||
begin
|
||||
s_axi_arvalid <= 1'b1;
|
||||
s_axi_araddr <= addr;
|
||||
s_axi_rready <= 1'b1;
|
||||
@(posedge s_axi_aclk) #0;
|
||||
while (s_axi_arvalid) begin
|
||||
if (s_axi_arready == 1'b1) begin
|
||||
s_axi_arvalid <= 1'b0;
|
||||
end
|
||||
@(posedge s_axi_aclk) #0;
|
||||
end
|
||||
|
||||
while (s_axi_rready) begin
|
||||
if (s_axi_rvalid == 1'b1) begin
|
||||
value <= s_axi_rdata;
|
||||
s_axi_rready <= 1'b0;
|
||||
end
|
||||
@(posedge s_axi_aclk) #0;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
task read_reg_check;
|
||||
input [31:0] addr;
|
||||
output match;
|
||||
reg [31:0] value;
|
||||
reg [31:0] expected;
|
||||
begin
|
||||
read_reg(addr, value);
|
||||
expected = expected_reg_mem[addr[13:2]];
|
||||
match <= value === expected;
|
||||
end
|
||||
endtask
|
||||
|
||||
reg read_match = 1'b1;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (read_match == 1'b0) begin
|
||||
failed <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
task set_reset_reg_value;
|
||||
input [31:0] addr;
|
||||
input [31:0] value;
|
||||
begin
|
||||
expected_reg_mem[addr[13:2]] <= value;
|
||||
end
|
||||
endtask
|
||||
|
||||
task initialize_expected_reg_mem;
|
||||
integer i;
|
||||
begin
|
||||
for (i = 0; i < 1024; i = i + 1)
|
||||
expected_reg_mem[i] <= 'h00;
|
||||
/* Non zero power-on-reset values */
|
||||
set_reset_reg_value('h00, 32'h00010161); /* PCORE version register */
|
||||
set_reset_reg_value('h0c, 32'h32303454); /* PCORE magic register */
|
||||
set_reset_reg_value('h10, NUM_LANES); /* Number of lanes */
|
||||
set_reset_reg_value('h14, 'h2); /* Datapath width */
|
||||
set_reset_reg_value('h18, NUM_LINKS); /* Number of links */
|
||||
set_reset_reg_value('hc0, 'h1); /* Link disable */
|
||||
set_reset_reg_value('hc4, 'h1); /* Core state */
|
||||
// set_reset_reg_value('hc8, 'h80000); /* clock monitor */
|
||||
set_reset_reg_value('h210, 'h3); /* OCTETS_PER_MULTIFRAME */
|
||||
|
||||
set_reset_reg_value('h244, 'h3); /* MFRAMES_PER_ILAS */
|
||||
end
|
||||
endtask
|
||||
|
||||
task check_all_registers;
|
||||
integer i;
|
||||
begin
|
||||
for (i = 0; i < 'h400; i = i + 4) begin
|
||||
read_reg_check(i, read_match);
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
task write_reg_and_update;
|
||||
input [31:0] addr;
|
||||
input [31:0] value;
|
||||
integer i;
|
||||
begin
|
||||
write_reg(addr, value);
|
||||
expected_reg_mem[addr[13:2]] <= value;
|
||||
|
||||
/* Special case for ILAS */
|
||||
if (addr >= 'h310 && addr < 'h310 + 32 * NUM_LANES) begin
|
||||
for (i = 0; i < NUM_LANES; i = i + 1) begin
|
||||
case (addr[3:2])
|
||||
2'b01: expected_reg_mem['h310/4 + i * 8 + 1][31:5] <= value[31:5];
|
||||
2'b11: expected_reg_mem['h310/4 + i * 8 + 3][23:0] <= value[23:0];
|
||||
default: expected_reg_mem['h310/4 + i * 8 + addr[3:2]] <= value;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
if (addr == 'hc0) begin
|
||||
expected_reg_mem['hc4/4][0] <= value[0];
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
task invert_register;
|
||||
input [31:0] addr;
|
||||
reg [31:0] value;
|
||||
begin
|
||||
read_reg(addr, value);
|
||||
write_reg(addr, ~value);
|
||||
end
|
||||
endtask
|
||||
|
||||
task invert_all_registers;
|
||||
integer i;
|
||||
begin
|
||||
for (i = 0; i < 'h400; i = i + 4) begin
|
||||
invert_register(i);
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
integer i;
|
||||
initial begin
|
||||
initialize_expected_reg_mem();
|
||||
@(posedge s_axi_aresetn)
|
||||
check_all_registers();
|
||||
|
||||
/* Check scratch */
|
||||
write_reg_and_update('h08, 32'h12345678);
|
||||
check_all_registers();
|
||||
|
||||
/* Check IRQ mask */
|
||||
write_reg_and_update('h80, 32'h0);
|
||||
check_all_registers();
|
||||
|
||||
/* Check lanes disable */
|
||||
write_reg_and_update('h200, {NUM_LANES{1'b1}});
|
||||
check_all_registers();
|
||||
|
||||
/* Check JESD common config */
|
||||
write_reg_and_update('h210, 32'hff03ff);
|
||||
check_all_registers();
|
||||
write_reg_and_update('h214, 32'h03);
|
||||
check_all_registers();
|
||||
|
||||
/* Check links disable */
|
||||
write_reg_and_update('h218, {NUM_LINKS{1'b1}});
|
||||
check_all_registers();
|
||||
|
||||
/* Check JESD TX configuration */
|
||||
write_reg_and_update('h240, 32'h07);
|
||||
check_all_registers();
|
||||
|
||||
/* Check mframes per ILAS - RO at the moment */
|
||||
write_reg('h244, 32'hff);
|
||||
check_all_registers();
|
||||
|
||||
/* Check status register */
|
||||
core_status_state = 2'b01; /* CGS */
|
||||
set_reset_reg_value('h280, 32'h00000001);
|
||||
check_all_registers();
|
||||
core_status_state = 2'b10; /* ILAS */
|
||||
set_reset_reg_value('h280, 32'h00000002);
|
||||
check_all_registers();
|
||||
core_status_state = 2'b11; /* DATA */
|
||||
set_reset_reg_value('h280, 32'h00000003);
|
||||
check_all_registers();
|
||||
core_status_state = 2'b00; /* WAIT */
|
||||
set_reset_reg_value('h280, 32'h00000000);
|
||||
check_all_registers();
|
||||
|
||||
core_status_sync = {NUM_LINKS{1'b1}}; /* SYNC deasserted */
|
||||
set_reset_reg_value('h280, ({NUM_LINKS{1'b1}} << 4));
|
||||
check_all_registers();
|
||||
core_status_sync = {NUM_LINKS{1'b0}}; /* SYNC asserted */
|
||||
set_reset_reg_value('h280, 32'h00000000);
|
||||
check_all_registers();
|
||||
|
||||
/* ILAS register */
|
||||
for (i = 0; i < NUM_LANES; i = i + 1) begin
|
||||
write_reg_and_update('h310 + i * 32, 32'h0fff0000);
|
||||
write_reg_and_update('h314 + i * 32, 32'h1fff9f1f ^ i);
|
||||
write_reg_and_update('h318 + i * 32, 32'hffffdfff ^ i);
|
||||
write_reg_and_update('h31c + i * 32, 32'h0f00009f ^ (2 << 24));
|
||||
end
|
||||
check_all_registers();
|
||||
|
||||
/* Reset core */
|
||||
write_reg_and_update('hc0, 32'h0);
|
||||
check_all_registers();
|
||||
|
||||
/* Should be read-only when core is out of reset */
|
||||
invert_register('h200);
|
||||
invert_register('h210);
|
||||
invert_register('h214);
|
||||
invert_register('h218);
|
||||
invert_register('h240);
|
||||
invert_register('h244);
|
||||
for (i = 0; i < NUM_LANES; i = i + 1) begin
|
||||
invert_register('h310 + i * 32);
|
||||
invert_register('h314 + i * 32);
|
||||
invert_register('h318 + i * 32);
|
||||
invert_register('h31c + i * 32);
|
||||
end
|
||||
|
||||
check_all_registers();
|
||||
|
||||
/* Check that reset works for all registers */
|
||||
do_trigger_reset();
|
||||
initialize_expected_reg_mem();
|
||||
check_all_registers();
|
||||
invert_all_registers();
|
||||
do_trigger_reset();
|
||||
check_all_registers();
|
||||
end
|
||||
|
||||
reg core_clk = 1'b0;
|
||||
always @(*) #4 core_clk <= ~core_clk;
|
||||
|
||||
axi_jesd204_tx #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.NUM_LINKS(NUM_LINKS)
|
||||
) i_axi (
|
||||
.s_axi_aclk(s_axi_aclk),
|
||||
.s_axi_aresetn(s_axi_aresetn),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
|
||||
.core_clk(core_clk),
|
||||
.core_reset_ext(1'b0),
|
||||
|
||||
.core_ilas_config_rd(1'b1),
|
||||
.core_ilas_config_addr(2'b00),
|
||||
|
||||
.core_event_sysref_alignment_error(1'b0),
|
||||
.core_event_sysref_edge(1'b0),
|
||||
|
||||
.core_status_state(core_status_state),
|
||||
.core_status_sync(core_status_sync)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,7 @@
|
||||
#!/bin/bash
|
||||
|
||||
SOURCE="crc12_tb.v"
|
||||
SOURCE+=" ../jesd204_common/jesd204_crc12.v"
|
||||
|
||||
cd `dirname $0`
|
||||
source run_tb.sh
|
||||
@@ -0,0 +1,105 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module crc12_tb;
|
||||
parameter VCD_FILE = "crc12_tb.vcd";
|
||||
|
||||
`define TIMEOUT 400
|
||||
|
||||
`include "tb_base.v"
|
||||
|
||||
reg [63:0] data_in = 'h0;
|
||||
reg [11:0] ref_crc12 = 'h0;
|
||||
wire [11:0] crc12;
|
||||
reg test_en = 1'b1;
|
||||
reg init = 1'b0;
|
||||
|
||||
jesd204_crc12 DUT (
|
||||
.clk (clk),
|
||||
.reset (1'b0),
|
||||
.init (init),
|
||||
.data_in (data_in),
|
||||
.crc12 (crc12)
|
||||
);
|
||||
|
||||
// Test against dataset from the standard
|
||||
// - Test contiguous input stream with init phase
|
||||
initial begin
|
||||
@(negedge reset);
|
||||
@(posedge clk);
|
||||
repeat (3) begin
|
||||
@(posedge clk) data_in <= 'h80_01_02_03_05_05_04_23;
|
||||
init <= 1'b1;
|
||||
@(posedge clk) data_in <= 'h0e_43_80_c2_0b_50_81_cd;
|
||||
init <= 1'b0;
|
||||
@(posedge clk) data_in <= 'h04_e7_83_92_5a_3c_aa_51;
|
||||
@(posedge clk) data_in <= 'h05_4d_87_d9_31_3d_11_51;
|
||||
end
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
test_en <= 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
@(negedge reset);
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
repeat(3) begin
|
||||
@(posedge clk) ref_crc12 <= 'hd00;
|
||||
@(posedge clk) ref_crc12 <= 'h11c;
|
||||
@(posedge clk) ref_crc12 <= 'hfea;
|
||||
@(posedge clk) ref_crc12 <= 'h5fe;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (ref_crc12 != crc12 && failed == 1'b0 && test_en) begin
|
||||
failed <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,17 @@
|
||||
#!/bin/bash
|
||||
|
||||
SOURCE="frame_align_tb.v"
|
||||
SOURCE+=" ../jesd204_common/jesd204_lmfc.v ../jesd204_common/jesd204_scrambler.v ../jesd204_common/jesd204_eof_generator.v"
|
||||
SOURCE+=" ../jesd204_common/pipeline_stage.v"
|
||||
SOURCE+=" ../jesd204_rx/jesd204_rx.v ../jesd204_rx/jesd204_rx_lane.v"
|
||||
SOURCE+=" ../jesd204_rx/jesd204_ilas_monitor.v ../jesd204_rx/align_mux.v ../jesd204_rx/jesd204_rx_cgs.v"
|
||||
SOURCE+=" ../jesd204_rx/jesd204_rx_ctrl.v ../jesd204_rx/elastic_buffer.v ../jesd204_rx/jesd204_lane_latency_monitor.v"
|
||||
SOURCE+=" ../jesd204_rx/jesd204_rx_frame_mark.v ../jesd204_rx/jesd204_rx_frame_align_monitor.v"
|
||||
SOURCE+=" ../jesd204_rx_static_config/jesd204_rx_static_config.v"
|
||||
SOURCE+=" ../jesd204_tx/jesd204_tx.v ../jesd204_tx/jesd204_tx_ctrl.v ../jesd204_tx/jesd204_tx_lane.v"
|
||||
SOURCE+=" ../jesd204_tx_static_config/jesd204_tx_static_config.v"
|
||||
SOURCE+=" ../jesd204_tx_static_config/jesd204_ilas_cfg_static.v"
|
||||
SOURCE+=" ../../util_cdc/sync_bits.v"
|
||||
|
||||
cd `dirname $0`
|
||||
source run_tb.sh
|
||||
@@ -0,0 +1,386 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module frame_align_tb;
|
||||
parameter VCD_FILE = "frame_align_tb.vcd";
|
||||
parameter NUM_LANES = 4;
|
||||
parameter NUM_LINKS = 1;
|
||||
parameter OCTETS_PER_FRAME = 4;
|
||||
parameter FRAMES_PER_MULTIFRAME = 16;
|
||||
parameter ENABLE_SCRAMBLER = 1;
|
||||
parameter BUFFER_EARLY_RELEASE = 1;
|
||||
parameter LANE_DELAY = 1;
|
||||
parameter ALIGN_ERROR_PERCENT = 50;
|
||||
|
||||
localparam BEATS_PER_MULTIFRAME = OCTETS_PER_FRAME * FRAMES_PER_MULTIFRAME / 4;
|
||||
localparam TX_LATENCY = 3;
|
||||
localparam RX_LATENCY = 3;
|
||||
localparam BASE_LATENCY = TX_LATENCY + RX_LATENCY;
|
||||
|
||||
`define TIMEOUT 1000000
|
||||
|
||||
`include "tb_base.v"
|
||||
|
||||
reg [5:0] tx_counter = 'h00;
|
||||
reg [5:0] rx_counter = 'h00;
|
||||
reg [NUM_LANES*32-1:0] rx_mask = 'hffff0000;
|
||||
wire tx_ready;
|
||||
wire rx_valid;
|
||||
wire [NUM_LANES*32-1:0] rx_data;
|
||||
reg data_mismatch = 1'b1;
|
||||
wire [NUM_LINKS-1:0] sync;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (sync == 1'b0) begin
|
||||
tx_counter <= 'h00000000;
|
||||
end else if (tx_ready == 1'b1) begin
|
||||
tx_counter <= tx_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (sync == 1'b0) begin
|
||||
rx_counter <= 'h00000000;
|
||||
if (ENABLE_SCRAMBLER == 1'b1) begin
|
||||
rx_mask <= {NUM_LANES{32'hffff0000}}; // First two octets are invalid due to scrambling
|
||||
end else begin
|
||||
rx_mask <= {NUM_LANES{32'hffffffff}};
|
||||
end
|
||||
end else if (rx_valid == 1'b1) begin
|
||||
rx_counter <= rx_counter + 1'b1;
|
||||
rx_mask <= {NUM_LANES{32'hffffffff}};
|
||||
end
|
||||
end
|
||||
|
||||
wire [31:0] tx_data = {tx_counter,2'h3,tx_counter,2'h2,tx_counter,2'h1,tx_counter,2'h0};
|
||||
wire [31:0] rx_ref_data = {rx_counter,2'h3,rx_counter,2'h2,rx_counter,2'h1,rx_counter,2'h0};
|
||||
|
||||
wire [NUM_LANES*32-1:0] phy_data_out;
|
||||
wire [NUM_LANES*4-1:0] phy_charisk_out;
|
||||
wire [NUM_LANES*32-1:0] phy_data_delayed;
|
||||
wire [NUM_LANES*4-1:0] phy_charisk_delayed;
|
||||
reg [NUM_LANES*32-1:0] phy_data_in;
|
||||
reg [NUM_LANES*4-1:0] phy_charisk_in;
|
||||
|
||||
reg align_err_mf;
|
||||
reg align_err_f;
|
||||
reg cur_err;
|
||||
|
||||
reg [5:0] sysref_counter = 'h00;
|
||||
reg sysref_rx = 1'b0;
|
||||
reg sysref_tx = 1'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (sysref_counter == 'h2f)
|
||||
sysref_rx <= ~sysref_rx;
|
||||
sysref_counter <= sysref_counter + 1'b1;
|
||||
sysref_tx <= sysref_rx;
|
||||
end
|
||||
|
||||
localparam MAX_LANE_DELAY = LANE_DELAY + NUM_LANES;
|
||||
|
||||
reg [10:0] phy_delay_fifo_wr;
|
||||
reg [36*NUM_LANES-1:0] phy_delay_fifo[0:MAX_LANE_DELAY-1];
|
||||
|
||||
always @(posedge clk) begin
|
||||
phy_delay_fifo[phy_delay_fifo_wr] <= {phy_charisk_out,phy_data_out};
|
||||
|
||||
if (reset == 1'b1 || phy_delay_fifo_wr == MAX_LANE_DELAY-1) begin
|
||||
phy_delay_fifo_wr <= 'h00;
|
||||
end else begin
|
||||
phy_delay_fifo_wr <= phy_delay_fifo_wr + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
initial begin
|
||||
align_err_mf = 1'b0;
|
||||
align_err_f = 1'b0;
|
||||
|
||||
#100000;
|
||||
align_err_f = 1'b1;
|
||||
#50000;
|
||||
align_err_f = 1'b0;
|
||||
#100000;
|
||||
|
||||
align_err_mf = 1'b1;
|
||||
#50000;
|
||||
align_err_mf = 1'b0;
|
||||
#100000;
|
||||
|
||||
align_err_f = 1'b1;
|
||||
align_err_mf = 1'b1;
|
||||
#50000;
|
||||
align_err_f = 1'b0;
|
||||
align_err_mf = 1'b0;
|
||||
#100000;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(ALIGN_ERROR_PERCENT != 0) begin
|
||||
cur_err <= $urandom_range(99) < ALIGN_ERROR_PERCENT;
|
||||
end else begin
|
||||
cur_err <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
genvar i;
|
||||
generate for (i = 0; i < NUM_LANES; i = i + 1) begin
|
||||
localparam OFF = MAX_LANE_DELAY - (i + LANE_DELAY);
|
||||
assign phy_data_delayed[32*i+31:32*i] =
|
||||
phy_delay_fifo[(phy_delay_fifo_wr + OFF) % MAX_LANE_DELAY][32*i+31:32*i];
|
||||
assign phy_charisk_delayed[4*i+3:4*i] =
|
||||
phy_delay_fifo[(phy_delay_fifo_wr + OFF) % MAX_LANE_DELAY][4*i+3+NUM_LANES*32:4*i+32*NUM_LANES];
|
||||
end endgenerate
|
||||
|
||||
always @(*) begin
|
||||
phy_data_in = phy_data_delayed;
|
||||
phy_charisk_in = phy_charisk_delayed;
|
||||
|
||||
if(cur_err) begin
|
||||
if(align_err_mf) begin
|
||||
phy_data_in = {NUM_LANES*4{8'h7C}};
|
||||
phy_charisk_in = {NUM_LANES*4{1'b1}};
|
||||
end else if(align_err_f) begin
|
||||
phy_data_in = {NUM_LANES*4{8'hFC}};
|
||||
phy_charisk_in = {NUM_LANES*4{1'b1}};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
wire [NUM_LANES-1:0] tx_cfg_lanes_disable;
|
||||
wire [NUM_LINKS-1:0] tx_cfg_links_disable;
|
||||
wire [7:0] tx_cfg_beats_per_multiframe;
|
||||
wire [7:0] tx_cfg_octets_per_frame;
|
||||
wire [7:0] tx_cfg_lmfc_offset;
|
||||
wire tx_cfg_sysref_disable;
|
||||
wire tx_cfg_sysref_oneshot;
|
||||
wire tx_cfg_continuous_cgs;
|
||||
wire tx_cfg_continuous_ilas;
|
||||
wire tx_cfg_skip_ilas;
|
||||
wire [7:0] tx_cfg_mframes_per_ilas;
|
||||
wire tx_cfg_disable_char_replacement;
|
||||
wire tx_cfg_disable_scrambler;
|
||||
|
||||
wire tx_ilas_config_rd;
|
||||
wire [1:0] tx_ilas_config_addr;
|
||||
wire [32*NUM_LANES-1:0] tx_ilas_config_data;
|
||||
|
||||
jesd204_tx_static_config #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.NUM_LINKS(NUM_LINKS),
|
||||
.OCTETS_PER_FRAME(OCTETS_PER_FRAME),
|
||||
.FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME),
|
||||
.SCR(ENABLE_SCRAMBLER)
|
||||
) i_tx_cfg (
|
||||
.clk(clk),
|
||||
|
||||
.cfg_lanes_disable(tx_cfg_lanes_disable),
|
||||
.cfg_links_disable(tx_cfg_links_disable),
|
||||
.cfg_beats_per_multiframe(tx_cfg_beats_per_multiframe),
|
||||
.cfg_octets_per_frame(tx_cfg_octets_per_frame),
|
||||
.cfg_lmfc_offset(tx_cfg_lmfc_offset),
|
||||
.cfg_sysref_disable(tx_cfg_sysref_disable),
|
||||
.cfg_sysref_oneshot(tx_cfg_sysref_oneshot),
|
||||
.cfg_continuous_cgs(tx_cfg_continuous_cgs),
|
||||
.cfg_continuous_ilas(tx_cfg_continuous_ilas),
|
||||
.cfg_skip_ilas(tx_cfg_skip_ilas),
|
||||
.cfg_mframes_per_ilas(tx_cfg_mframes_per_ilas),
|
||||
.cfg_disable_char_replacement(tx_cfg_disable_char_replacement),
|
||||
.cfg_disable_scrambler(tx_cfg_disable_scrambler),
|
||||
|
||||
.ilas_config_rd(tx_ilas_config_rd),
|
||||
.ilas_config_addr(tx_ilas_config_addr),
|
||||
.ilas_config_data(tx_ilas_config_data)
|
||||
);
|
||||
|
||||
jesd204_tx #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.NUM_LINKS(NUM_LINKS)
|
||||
) i_tx (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
|
||||
.cfg_lanes_disable(tx_cfg_lanes_disable),
|
||||
.cfg_links_disable(tx_cfg_links_disable),
|
||||
.cfg_beats_per_multiframe(tx_cfg_beats_per_multiframe),
|
||||
.cfg_octets_per_frame(tx_cfg_octets_per_frame),
|
||||
.cfg_lmfc_offset(tx_cfg_lmfc_offset),
|
||||
.cfg_sysref_disable(tx_cfg_sysref_disable),
|
||||
.cfg_sysref_oneshot(tx_cfg_sysref_oneshot),
|
||||
.cfg_continuous_cgs(tx_cfg_continuous_cgs),
|
||||
.cfg_continuous_ilas(tx_cfg_continuous_ilas),
|
||||
.cfg_skip_ilas(tx_cfg_skip_ilas),
|
||||
.cfg_mframes_per_ilas(tx_cfg_mframes_per_ilas),
|
||||
.cfg_disable_char_replacement(tx_cfg_disable_char_replacement),
|
||||
.cfg_disable_scrambler(tx_cfg_disable_scrambler),
|
||||
|
||||
.ilas_config_rd(tx_ilas_config_rd),
|
||||
.ilas_config_addr(tx_ilas_config_addr),
|
||||
.ilas_config_data(tx_ilas_config_data),
|
||||
|
||||
.ctrl_manual_sync_request(1'b0),
|
||||
|
||||
.tx_ready(tx_ready),
|
||||
.tx_data({NUM_LANES{tx_data}}),
|
||||
|
||||
.sync(sync),
|
||||
.sysref(sysref_tx),
|
||||
|
||||
.phy_data(phy_data_out),
|
||||
.phy_charisk(phy_charisk_out)
|
||||
);
|
||||
|
||||
wire [NUM_LANES-1:0] rx_cfg_lanes_disable;
|
||||
wire [NUM_LINKS-1:0] rx_cfg_links_disable;
|
||||
wire [7:0] rx_cfg_beats_per_multiframe;
|
||||
wire [7:0] rx_cfg_octets_per_frame;
|
||||
wire [7:0] rx_cfg_lmfc_offset;
|
||||
wire rx_sysref_disable;
|
||||
wire rx_sysref_oneshot;
|
||||
wire rx_cfg_disable_scrambler;
|
||||
wire rx_cfg_disable_char_replacement;
|
||||
wire rx_cfg_buffer_early_release;
|
||||
wire [7:0] rx_cfg_buffer_delay;
|
||||
wire [NUM_LANES-1:0] rx_status_lane_ifs_ready;
|
||||
wire [NUM_LANES*14-1:0] rx_status_lane_latency;
|
||||
wire [NUM_LANES*8-1:0] rx_status_lane_frame_align_err_cnt;
|
||||
wire [7:0] rx_cfg_frame_align_err_threshold;
|
||||
|
||||
jesd204_rx_static_config #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.OCTETS_PER_FRAME(OCTETS_PER_FRAME),
|
||||
.FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME),
|
||||
.SCR(ENABLE_SCRAMBLER),
|
||||
.BUFFER_EARLY_RELEASE(BUFFER_EARLY_RELEASE)
|
||||
) i_rx_cfg (
|
||||
.clk(clk),
|
||||
|
||||
.cfg_lanes_disable(rx_cfg_lanes_disable),
|
||||
.cfg_links_disable(rx_cfg_links_disable),
|
||||
.cfg_beats_per_multiframe(rx_cfg_beats_per_multiframe),
|
||||
.cfg_octets_per_frame(rx_cfg_octets_per_frame),
|
||||
.cfg_lmfc_offset(rx_cfg_lmfc_offset),
|
||||
.cfg_sysref_disable(rx_cfg_sysref_disable),
|
||||
.cfg_sysref_oneshot(rx_cfg_sysref_oneshot),
|
||||
.cfg_disable_scrambler(rx_cfg_disable_scrambler),
|
||||
.cfg_disable_char_replacement(rx_cfg_disable_char_replacement),
|
||||
.cfg_buffer_delay(rx_cfg_buffer_delay),
|
||||
.cfg_buffer_early_release(rx_cfg_buffer_early_release),
|
||||
.cfg_frame_align_err_threshold(rx_cfg_frame_align_err_threshold)
|
||||
);
|
||||
|
||||
jesd204_rx #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.ENABLE_FRAME_ALIGN_CHECK(1),
|
||||
.ENABLE_FRAME_ALIGN_ERR_RESET(1)
|
||||
) i_rx (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
|
||||
.cfg_lanes_disable(rx_cfg_lanes_disable),
|
||||
.cfg_links_disable(rx_cfg_links_disable),
|
||||
.cfg_beats_per_multiframe(rx_cfg_beats_per_multiframe),
|
||||
.cfg_octets_per_frame(rx_cfg_octets_per_frame),
|
||||
.cfg_lmfc_offset(rx_cfg_lmfc_offset),
|
||||
.cfg_sysref_disable(rx_cfg_sysref_disable),
|
||||
.cfg_sysref_oneshot(rx_cfg_sysref_oneshot),
|
||||
.cfg_disable_scrambler(rx_cfg_disable_scrambler),
|
||||
.cfg_disable_char_replacement(rx_cfg_disable_char_replacement),
|
||||
.cfg_buffer_delay(rx_cfg_buffer_delay),
|
||||
.cfg_buffer_early_release(rx_cfg_buffer_early_release),
|
||||
.cfg_frame_align_err_threshold(rx_cfg_frame_align_err_threshold),
|
||||
|
||||
.sync(sync),
|
||||
.sysref(sysref_rx),
|
||||
|
||||
.rx_data(rx_data),
|
||||
.rx_valid(rx_valid),
|
||||
|
||||
.phy_data(phy_data_in),
|
||||
.phy_charisk(phy_charisk_in),
|
||||
.phy_notintable({NUM_LANES{4'b0000}}),
|
||||
.phy_disperr({NUM_LANES{4'b0000}}),
|
||||
|
||||
.status_lane_ifs_ready(rx_status_lane_ifs_ready),
|
||||
.status_lane_latency(rx_status_lane_latency),
|
||||
.status_lane_frame_align_err_cnt(rx_status_lane_frame_align_err_cnt)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
data_mismatch <= 1'b0;
|
||||
end else if (rx_valid == 1'b1) begin
|
||||
if ((rx_data & rx_mask) !== ({NUM_LANES{rx_ref_data}} & rx_mask)) begin
|
||||
data_mismatch <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [NUM_LANES-1:0] lane_latency_match;
|
||||
|
||||
generate for (i = 0; i < NUM_LANES; i = i + 1) begin
|
||||
localparam LANE_OFFSET = BASE_LATENCY + LANE_DELAY + BEATS_PER_MULTIFRAME + i;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rx_status_lane_ifs_ready[i] == 1'b1 &&
|
||||
rx_status_lane_latency[i*14+13:i*14+2] == LANE_OFFSET) begin
|
||||
lane_latency_match[i] <= 1'b1;
|
||||
end else begin
|
||||
lane_latency_match[i] <= 1'b0;
|
||||
end
|
||||
end
|
||||
end endgenerate
|
||||
|
||||
always @(*) begin
|
||||
if (rx_valid !== 1'b1 || tx_ready !== 1'b1 || data_mismatch == 1'b1 ||
|
||||
&lane_latency_match != 1'b1) begin
|
||||
failed <= 1'b1;
|
||||
end else begin
|
||||
failed <= 1'b0;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
@@ -0,0 +1,16 @@
|
||||
#!/bin/bash
|
||||
|
||||
SOURCE="loopback_64b_tb.v"
|
||||
SOURCE+=" ../jesd204_common/jesd204_lmfc.v ../jesd204_common/jesd204_scrambler.v ../jesd204_common/jesd204_eof_generator.v"
|
||||
SOURCE+=" ../jesd204_common/pipeline_stage.v"
|
||||
SOURCE+=" ../jesd204_common/jesd204_scrambler_64b.v ../jesd204_common/jesd204_crc12.v"
|
||||
SOURCE+=" ../jesd204_rx/jesd204_rx.v ../jesd204_rx/jesd204_rx_ctrl_64b.v ../jesd204_rx/jesd204_rx_lane_64b.v"
|
||||
SOURCE+=" ../jesd204_rx/elastic_buffer.v ../jesd204_rx/error_monitor.v ../jesd204_rx/jesd204_rx_header.v"
|
||||
SOURCE+=" ../jesd204_rx_static_config/jesd204_rx_static_config.v"
|
||||
SOURCE+=" ../jesd204_tx/jesd204_tx.v ../jesd204_tx/jesd204_tx_lane_64b.v ../jesd204_tx/jesd204_tx_header.v"
|
||||
SOURCE+=" ../jesd204_tx_static_config/jesd204_tx_static_config.v"
|
||||
SOURCE+=" ../jesd204_tx_static_config/jesd204_ilas_cfg_static.v"
|
||||
SOURCE+=" ../../util_cdc/sync_bits.v"
|
||||
|
||||
cd `dirname $0`
|
||||
source run_tb.sh
|
||||
@@ -0,0 +1,360 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module loopback_64b_tb;
|
||||
parameter VCD_FILE = "loopback_64b_tb.vcd";
|
||||
parameter NUM_LANES = 4;
|
||||
parameter NUM_LINKS = 1;
|
||||
parameter OCTETS_PER_FRAME = 8;
|
||||
parameter FRAMES_PER_MULTIFRAME = 32;
|
||||
parameter ENABLE_SCRAMBLER = 1;
|
||||
parameter BUFFER_EARLY_RELEASE = 0;
|
||||
parameter LANE_DELAY = 1;
|
||||
|
||||
localparam BEATS_PER_MULTIFRAME = OCTETS_PER_FRAME * FRAMES_PER_MULTIFRAME / 8;
|
||||
localparam TX_LATENCY = 3;
|
||||
localparam RX_LATENCY = 3;
|
||||
localparam BASE_LATENCY = TX_LATENCY + RX_LATENCY;
|
||||
|
||||
`include "tb_base.v"
|
||||
|
||||
reg [5:0] tx_counter = 'h00;
|
||||
reg [5:0] rx_counter = 'h00;
|
||||
wire tx_ready;
|
||||
wire rx_valid;
|
||||
wire [NUM_LANES*64-1:0] rx_data;
|
||||
reg data_mismatch = 1'b1;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (tx_ready == 1'b1) begin
|
||||
tx_counter <= tx_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
reg rx_valid_d1 = 1'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
rx_valid_d1 <= rx_valid;
|
||||
if (rx_valid == 1'b1) begin
|
||||
if (rx_valid_d1 == 1'b0) begin
|
||||
// Resynchronize counter to the first received data
|
||||
rx_counter <= rx_data[7:2] + 1'b1;
|
||||
end else begin
|
||||
rx_counter <= rx_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire [63:0] tx_data =
|
||||
{{tx_counter,2'h0,tx_counter,2'h1,tx_counter,2'h2,tx_counter,2'h3},
|
||||
{tx_counter,2'h3,tx_counter,2'h2,tx_counter,2'h1,tx_counter,2'h0}};
|
||||
wire [63:0] rx_ref_data =
|
||||
{{rx_counter,2'h0,rx_counter,2'h1,rx_counter,2'h2,rx_counter,2'h3},
|
||||
{rx_counter,2'h3,rx_counter,2'h2,rx_counter,2'h1,rx_counter,2'h0}};
|
||||
|
||||
wire [NUM_LANES*64-1:0] phy_data_out;
|
||||
wire [NUM_LANES*2-1:0] phy_header_out;
|
||||
wire [NUM_LANES*64-1:0] phy_data_in;
|
||||
wire [NUM_LANES*2-1:0] phy_header_in;
|
||||
|
||||
reg [NUM_LANES-1:0] phy_block_sync = {NUM_LANES{1'b1}};
|
||||
|
||||
reg [5:0] sysref_counter = 'h00;
|
||||
reg sysref_rx = 1'b0;
|
||||
reg sysref_tx = 1'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (sysref_counter == 'h2f)
|
||||
sysref_rx <= ~sysref_rx;
|
||||
sysref_counter <= sysref_counter + 1'b1;
|
||||
sysref_tx <= sysref_rx;
|
||||
end
|
||||
|
||||
localparam MAX_LANE_DELAY = LANE_DELAY + NUM_LANES;
|
||||
|
||||
reg [10:0] phy_delay_fifo_wr;
|
||||
reg [(2+64)*NUM_LANES-1:0] phy_delay_fifo[0:MAX_LANE_DELAY-1];
|
||||
|
||||
always @(posedge clk) begin
|
||||
phy_delay_fifo[phy_delay_fifo_wr] <= {phy_header_out,phy_data_out};
|
||||
|
||||
if (reset == 1'b1 || phy_delay_fifo_wr == MAX_LANE_DELAY-1) begin
|
||||
phy_delay_fifo_wr <= 'h00;
|
||||
end else begin
|
||||
phy_delay_fifo_wr <= phy_delay_fifo_wr + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
genvar i;
|
||||
generate for (i = 0; i < NUM_LANES; i = i + 1) begin
|
||||
localparam OFF = MAX_LANE_DELAY - (i + LANE_DELAY);
|
||||
|
||||
assign phy_data_in[64*i+63:64*i] =
|
||||
phy_delay_fifo[(phy_delay_fifo_wr + OFF) % MAX_LANE_DELAY][64*i+63:64*i];
|
||||
|
||||
assign phy_header_in[2*i+1:2*i] =
|
||||
phy_delay_fifo[(phy_delay_fifo_wr + OFF) % MAX_LANE_DELAY][2*i+1+NUM_LANES*64 : 2*i+64*NUM_LANES];
|
||||
|
||||
end endgenerate
|
||||
|
||||
wire [NUM_LANES-1:0] tx_cfg_lanes_disable;
|
||||
wire [NUM_LINKS-1:0] tx_cfg_links_disable;
|
||||
wire [7:0] tx_cfg_beats_per_multiframe;
|
||||
wire [7:0] tx_cfg_octets_per_frame;
|
||||
wire [7:0] tx_cfg_lmfc_offset;
|
||||
wire tx_cfg_sysref_disable;
|
||||
wire tx_cfg_sysref_oneshot;
|
||||
wire tx_cfg_continuous_cgs;
|
||||
wire tx_cfg_continuous_ilas;
|
||||
wire tx_cfg_skip_ilas;
|
||||
wire [7:0] tx_cfg_mframes_per_ilas;
|
||||
wire tx_cfg_disable_char_replacement;
|
||||
wire tx_cfg_disable_scrambler;
|
||||
|
||||
wire tx_ilas_config_rd;
|
||||
wire [1:0] tx_ilas_config_addr;
|
||||
wire [32*NUM_LANES-1:0] tx_ilas_config_data;
|
||||
|
||||
jesd204_tx_static_config #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.NUM_LINKS(NUM_LINKS),
|
||||
.OCTETS_PER_FRAME(OCTETS_PER_FRAME),
|
||||
.FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME),
|
||||
.SCR(ENABLE_SCRAMBLER),
|
||||
.LINK_MODE(2)
|
||||
) i_tx_cfg (
|
||||
.clk(clk),
|
||||
|
||||
.cfg_lanes_disable(tx_cfg_lanes_disable),
|
||||
.cfg_links_disable(tx_cfg_links_disable),
|
||||
.cfg_beats_per_multiframe(tx_cfg_beats_per_multiframe),
|
||||
.cfg_octets_per_frame(tx_cfg_octets_per_frame),
|
||||
.cfg_lmfc_offset(tx_cfg_lmfc_offset),
|
||||
.cfg_sysref_disable(tx_cfg_sysref_disable),
|
||||
.cfg_sysref_oneshot(tx_cfg_sysref_oneshot),
|
||||
.cfg_continuous_cgs(tx_cfg_continuous_cgs),
|
||||
.cfg_continuous_ilas(tx_cfg_continuous_ilas),
|
||||
.cfg_skip_ilas(tx_cfg_skip_ilas),
|
||||
.cfg_mframes_per_ilas(tx_cfg_mframes_per_ilas),
|
||||
.cfg_disable_char_replacement(tx_cfg_disable_char_replacement),
|
||||
.cfg_disable_scrambler(tx_cfg_disable_scrambler),
|
||||
|
||||
.ilas_config_rd(tx_ilas_config_rd),
|
||||
.ilas_config_addr(tx_ilas_config_addr),
|
||||
.ilas_config_data(tx_ilas_config_data)
|
||||
);
|
||||
|
||||
jesd204_tx #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.NUM_LINKS(NUM_LINKS),
|
||||
.LINK_MODE(2)
|
||||
) i_tx (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
|
||||
.cfg_lanes_disable(tx_cfg_lanes_disable),
|
||||
.cfg_links_disable(tx_cfg_links_disable),
|
||||
.cfg_beats_per_multiframe(tx_cfg_beats_per_multiframe),
|
||||
.cfg_octets_per_frame(tx_cfg_octets_per_frame),
|
||||
.cfg_lmfc_offset(tx_cfg_lmfc_offset),
|
||||
.cfg_sysref_disable(tx_cfg_sysref_disable),
|
||||
.cfg_sysref_oneshot(tx_cfg_sysref_oneshot),
|
||||
.cfg_continuous_cgs(tx_cfg_continuous_cgs),
|
||||
.cfg_continuous_ilas(tx_cfg_continuous_ilas),
|
||||
.cfg_skip_ilas(tx_cfg_skip_ilas),
|
||||
.cfg_mframes_per_ilas(tx_cfg_mframes_per_ilas),
|
||||
.cfg_disable_char_replacement(tx_cfg_disable_char_replacement),
|
||||
.cfg_disable_scrambler(tx_cfg_disable_scrambler),
|
||||
|
||||
.ilas_config_rd(tx_ilas_config_rd),
|
||||
.ilas_config_addr(tx_ilas_config_addr),
|
||||
.ilas_config_data(tx_ilas_config_data),
|
||||
|
||||
.ctrl_manual_sync_request(1'b0),
|
||||
|
||||
.tx_ready(tx_ready),
|
||||
.tx_data({NUM_LANES{tx_data}}),
|
||||
.tx_valid(),
|
||||
|
||||
.sync(),
|
||||
.sysref(sysref_tx),
|
||||
|
||||
.phy_data(phy_data_out),
|
||||
.phy_charisk(),
|
||||
.phy_header(phy_header_out),
|
||||
|
||||
.lmfc_edge(),
|
||||
.lmfc_clk(),
|
||||
.event_sysref_edge(),
|
||||
.event_sysref_alignment_error(),
|
||||
.status_sync(),
|
||||
.status_state()
|
||||
);
|
||||
|
||||
wire [NUM_LANES-1:0] rx_cfg_lanes_disable;
|
||||
wire [NUM_LINKS-1:0] rx_cfg_links_disable;
|
||||
wire [7:0] rx_cfg_beats_per_multiframe;
|
||||
wire [7:0] rx_cfg_octets_per_frame;
|
||||
wire [7:0] rx_cfg_lmfc_offset;
|
||||
wire rx_sysref_disable;
|
||||
wire rx_sysref_oneshot;
|
||||
wire rx_cfg_disable_scrambler;
|
||||
wire rx_cfg_disable_char_replacement;
|
||||
wire rx_cfg_buffer_early_release;
|
||||
wire [7:0] rx_cfg_buffer_delay;
|
||||
wire [NUM_LANES*3-1:0] status_lane_emb_state;
|
||||
|
||||
jesd204_rx_static_config #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.OCTETS_PER_FRAME(OCTETS_PER_FRAME),
|
||||
.FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME),
|
||||
.SCR(ENABLE_SCRAMBLER),
|
||||
.BUFFER_EARLY_RELEASE(BUFFER_EARLY_RELEASE),
|
||||
.LINK_MODE(2)
|
||||
) i_rx_cfg (
|
||||
.clk(clk),
|
||||
|
||||
.cfg_lanes_disable(rx_cfg_lanes_disable),
|
||||
.cfg_links_disable(rx_cfg_links_disable),
|
||||
.cfg_beats_per_multiframe(rx_cfg_beats_per_multiframe),
|
||||
.cfg_octets_per_frame(rx_cfg_octets_per_frame),
|
||||
.cfg_lmfc_offset(rx_cfg_lmfc_offset),
|
||||
.cfg_sysref_disable(rx_cfg_sysref_disable),
|
||||
.cfg_sysref_oneshot(rx_cfg_sysref_oneshot),
|
||||
.cfg_disable_scrambler(rx_cfg_disable_scrambler),
|
||||
.cfg_disable_char_replacement(rx_cfg_disable_char_replacement),
|
||||
.cfg_buffer_delay(rx_cfg_buffer_delay),
|
||||
.cfg_buffer_early_release(rx_cfg_buffer_early_release)
|
||||
);
|
||||
|
||||
jesd204_rx #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.LINK_MODE(2)
|
||||
) i_rx (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
|
||||
.cfg_lanes_disable(rx_cfg_lanes_disable),
|
||||
.cfg_links_disable(rx_cfg_links_disable),
|
||||
.cfg_beats_per_multiframe(rx_cfg_beats_per_multiframe),
|
||||
.cfg_octets_per_frame(rx_cfg_octets_per_frame),
|
||||
.cfg_lmfc_offset(rx_cfg_lmfc_offset),
|
||||
.cfg_sysref_disable(rx_cfg_sysref_disable),
|
||||
.cfg_sysref_oneshot(rx_cfg_sysref_oneshot),
|
||||
.cfg_disable_scrambler(rx_cfg_disable_scrambler),
|
||||
.cfg_disable_char_replacement(rx_cfg_disable_char_replacement),
|
||||
.cfg_buffer_delay(rx_cfg_buffer_delay),
|
||||
.cfg_buffer_early_release(rx_cfg_buffer_early_release),
|
||||
|
||||
.ctrl_err_statistics_reset (1'b0),
|
||||
.ctrl_err_statistics_mask(7'b0),
|
||||
|
||||
.sync(),
|
||||
.sysref(sysref_rx),
|
||||
|
||||
.rx_data(rx_data),
|
||||
.rx_valid(rx_valid),
|
||||
.rx_eof(),
|
||||
.rx_sof(),
|
||||
|
||||
.phy_data(phy_data_in),
|
||||
.phy_charisk({NUM_LANES{4'b0}}),
|
||||
.phy_notintable({NUM_LANES{4'b0000}}),
|
||||
.phy_disperr({NUM_LANES{4'b0000}}),
|
||||
.phy_header(phy_header_in),
|
||||
.phy_block_sync(phy_block_sync),
|
||||
|
||||
.status_lane_ifs_ready(),
|
||||
.status_lane_latency(),
|
||||
.status_err_statistics_cnt(),
|
||||
|
||||
.lmfc_edge(),
|
||||
.lmfc_clk(),
|
||||
.event_sysref_alignment_error(),
|
||||
.event_sysref_edge(),
|
||||
.phy_en_char_align(),
|
||||
.ilas_config_valid(),
|
||||
.ilas_config_addr(),
|
||||
.ilas_config_data(),
|
||||
.status_ctrl_state(),
|
||||
.status_lane_cgs_state(),
|
||||
.status_lane_emb_state(status_lane_emb_state)
|
||||
);
|
||||
|
||||
integer ii;
|
||||
reg rx_status_mismatch = 1'b0;
|
||||
initial begin
|
||||
@(posedge rx_valid);
|
||||
for (ii=0;ii<NUM_LANES;ii=ii+1) begin
|
||||
#5000;
|
||||
if (status_lane_emb_state !== {NUM_LANES{3'b100}}) rx_status_mismatch = 1;
|
||||
phy_block_sync[ii] = 1'b0;
|
||||
#5000;
|
||||
phy_block_sync[ii] = 1'b1;
|
||||
end
|
||||
#5000;
|
||||
if (status_lane_emb_state !== {NUM_LANES{3'b100}}) rx_status_mismatch = 1;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
data_mismatch <= 1'b0;
|
||||
end else if (rx_valid_d1 && rx_valid) begin
|
||||
if (rx_data !== {NUM_LANES{rx_ref_data}}) begin
|
||||
data_mismatch <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @(*) begin
|
||||
if (data_mismatch || rx_status_mismatch) begin
|
||||
failed <= 1'b1;
|
||||
end else begin
|
||||
failed <= 1'b0;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
@@ -0,0 +1,17 @@
|
||||
#!/bin/bash
|
||||
|
||||
SOURCE="loopback_tb.v"
|
||||
SOURCE+=" ../jesd204_common/jesd204_lmfc.v ../jesd204_common/jesd204_scrambler.v ../jesd204_common/jesd204_eof_generator.v"
|
||||
SOURCE+=" ../jesd204_common/pipeline_stage.v"
|
||||
SOURCE+=" ../jesd204_rx/jesd204_rx.v ../jesd204_rx/jesd204_rx_lane.v"
|
||||
SOURCE+=" ../jesd204_rx/jesd204_ilas_monitor.v ../jesd204_rx/align_mux.v ../jesd204_rx/jesd204_rx_cgs.v"
|
||||
SOURCE+=" ../jesd204_rx/jesd204_rx_ctrl.v ../jesd204_rx/elastic_buffer.v ../jesd204_rx/jesd204_lane_latency_monitor.v"
|
||||
SOURCE+=" ../jesd204_rx/jesd204_rx_frame_mark.v ../jesd204_rx/jesd204_rx_frame_align_monitor.v"
|
||||
SOURCE+=" ../jesd204_rx_static_config/jesd204_rx_static_config.v"
|
||||
SOURCE+=" ../jesd204_tx/jesd204_tx.v ../jesd204_tx/jesd204_tx_ctrl.v ../jesd204_tx/jesd204_tx_lane.v"
|
||||
SOURCE+=" ../jesd204_tx_static_config/jesd204_tx_static_config.v"
|
||||
SOURCE+=" ../jesd204_tx_static_config/jesd204_ilas_cfg_static.v"
|
||||
SOURCE+=" ../../util_cdc/sync_bits.v"
|
||||
|
||||
cd `dirname $0`
|
||||
source run_tb.sh
|
||||
@@ -0,0 +1,327 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module loopback_tb;
|
||||
parameter VCD_FILE = "loopback_tb.vcd";
|
||||
parameter NUM_LANES = 4;
|
||||
parameter NUM_LINKS = 1;
|
||||
parameter OCTETS_PER_FRAME = 4;
|
||||
parameter FRAMES_PER_MULTIFRAME = 16;
|
||||
parameter ENABLE_SCRAMBLER = 1;
|
||||
parameter BUFFER_EARLY_RELEASE = 1;
|
||||
parameter LANE_DELAY = 1;
|
||||
|
||||
localparam BEATS_PER_MULTIFRAME = OCTETS_PER_FRAME * FRAMES_PER_MULTIFRAME / 4;
|
||||
localparam TX_LATENCY = 3;
|
||||
localparam RX_LATENCY = 3;
|
||||
localparam BASE_LATENCY = TX_LATENCY + RX_LATENCY;
|
||||
|
||||
`include "tb_base.v"
|
||||
|
||||
reg [5:0] tx_counter = 'h00;
|
||||
reg [5:0] rx_counter = 'h00;
|
||||
reg [NUM_LANES*32-1:0] rx_mask = 'hffff0000;
|
||||
wire tx_ready;
|
||||
wire rx_valid;
|
||||
wire [NUM_LANES*32-1:0] rx_data;
|
||||
reg data_mismatch = 1'b1;
|
||||
wire [NUM_LINKS-1:0] sync;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (sync == 1'b0) begin
|
||||
tx_counter <= 'h00000000;
|
||||
end else if (tx_ready == 1'b1) begin
|
||||
tx_counter <= tx_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (sync == 1'b0) begin
|
||||
rx_counter <= 'h00000000;
|
||||
if (ENABLE_SCRAMBLER == 1'b1) begin
|
||||
rx_mask <= {NUM_LANES{32'hffff0000}}; // First two octets are invalid due to scrambling
|
||||
end else begin
|
||||
rx_mask <= {NUM_LANES{32'hffffffff}};
|
||||
end
|
||||
end else if (rx_valid == 1'b1) begin
|
||||
rx_counter <= rx_counter + 1'b1;
|
||||
rx_mask <= {NUM_LANES{32'hffffffff}};
|
||||
end
|
||||
end
|
||||
|
||||
wire [31:0] tx_data = {tx_counter,2'h3,tx_counter,2'h2,tx_counter,2'h1,tx_counter,2'h0};
|
||||
wire [31:0] rx_ref_data = {rx_counter,2'h3,rx_counter,2'h2,rx_counter,2'h1,rx_counter,2'h0};
|
||||
|
||||
wire [NUM_LANES*32-1:0] phy_data_out;
|
||||
wire [NUM_LANES*4-1:0] phy_charisk_out;
|
||||
wire [NUM_LANES*32-1:0] phy_data_in;
|
||||
wire [NUM_LANES*4-1:0] phy_charisk_in;
|
||||
|
||||
reg [5:0] sysref_counter = 'h00;
|
||||
reg sysref_rx = 1'b0;
|
||||
reg sysref_tx = 1'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (sysref_counter == 'h2f)
|
||||
sysref_rx <= ~sysref_rx;
|
||||
sysref_counter <= sysref_counter + 1'b1;
|
||||
sysref_tx <= sysref_rx;
|
||||
end
|
||||
|
||||
localparam MAX_LANE_DELAY = LANE_DELAY + NUM_LANES;
|
||||
|
||||
reg [10:0] phy_delay_fifo_wr;
|
||||
reg [36*NUM_LANES-1:0] phy_delay_fifo[0:MAX_LANE_DELAY-1];
|
||||
|
||||
always @(posedge clk) begin
|
||||
phy_delay_fifo[phy_delay_fifo_wr] <= {phy_charisk_out,phy_data_out};
|
||||
|
||||
if (reset == 1'b1 || phy_delay_fifo_wr == MAX_LANE_DELAY-1) begin
|
||||
phy_delay_fifo_wr <= 'h00;
|
||||
end else begin
|
||||
phy_delay_fifo_wr <= phy_delay_fifo_wr + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
genvar i;
|
||||
generate for (i = 0; i < NUM_LANES; i = i + 1) begin
|
||||
localparam OFF = MAX_LANE_DELAY - (i + LANE_DELAY);
|
||||
assign phy_data_in[32*i+31:32*i] =
|
||||
phy_delay_fifo[(phy_delay_fifo_wr + OFF) % MAX_LANE_DELAY][32*i+31:32*i];
|
||||
assign phy_charisk_in[4*i+3:4*i] =
|
||||
phy_delay_fifo[(phy_delay_fifo_wr + OFF) % MAX_LANE_DELAY][4*i+3+NUM_LANES*32:4*i+32*NUM_LANES];
|
||||
end endgenerate
|
||||
|
||||
wire [NUM_LANES-1:0] tx_cfg_lanes_disable;
|
||||
wire [NUM_LINKS-1:0] tx_cfg_links_disable;
|
||||
wire [7:0] tx_cfg_beats_per_multiframe;
|
||||
wire [7:0] tx_cfg_octets_per_frame;
|
||||
wire [7:0] tx_cfg_lmfc_offset;
|
||||
wire tx_cfg_sysref_disable;
|
||||
wire tx_cfg_sysref_oneshot;
|
||||
wire tx_cfg_continuous_cgs;
|
||||
wire tx_cfg_continuous_ilas;
|
||||
wire tx_cfg_skip_ilas;
|
||||
wire [7:0] tx_cfg_mframes_per_ilas;
|
||||
wire tx_cfg_disable_char_replacement;
|
||||
wire tx_cfg_disable_scrambler;
|
||||
|
||||
wire tx_ilas_config_rd;
|
||||
wire [1:0] tx_ilas_config_addr;
|
||||
wire [32*NUM_LANES-1:0] tx_ilas_config_data;
|
||||
|
||||
jesd204_tx_static_config #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.NUM_LINKS(NUM_LINKS),
|
||||
.OCTETS_PER_FRAME(OCTETS_PER_FRAME),
|
||||
.FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME),
|
||||
.SCR(ENABLE_SCRAMBLER)
|
||||
) i_tx_cfg (
|
||||
.clk(clk),
|
||||
|
||||
.cfg_lanes_disable(tx_cfg_lanes_disable),
|
||||
.cfg_links_disable(tx_cfg_links_disable),
|
||||
.cfg_beats_per_multiframe(tx_cfg_beats_per_multiframe),
|
||||
.cfg_octets_per_frame(tx_cfg_octets_per_frame),
|
||||
.cfg_lmfc_offset(tx_cfg_lmfc_offset),
|
||||
.cfg_sysref_disable(tx_cfg_sysref_disable),
|
||||
.cfg_sysref_oneshot(tx_cfg_sysref_oneshot),
|
||||
.cfg_continuous_cgs(tx_cfg_continuous_cgs),
|
||||
.cfg_continuous_ilas(tx_cfg_continuous_ilas),
|
||||
.cfg_skip_ilas(tx_cfg_skip_ilas),
|
||||
.cfg_mframes_per_ilas(tx_cfg_mframes_per_ilas),
|
||||
.cfg_disable_char_replacement(tx_cfg_disable_char_replacement),
|
||||
.cfg_disable_scrambler(tx_cfg_disable_scrambler),
|
||||
|
||||
.ilas_config_rd(tx_ilas_config_rd),
|
||||
.ilas_config_addr(tx_ilas_config_addr),
|
||||
.ilas_config_data(tx_ilas_config_data)
|
||||
);
|
||||
|
||||
jesd204_tx #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.NUM_LINKS(NUM_LINKS)
|
||||
) i_tx (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
|
||||
.cfg_lanes_disable(tx_cfg_lanes_disable),
|
||||
.cfg_links_disable(tx_cfg_links_disable),
|
||||
.cfg_beats_per_multiframe(tx_cfg_beats_per_multiframe),
|
||||
.cfg_octets_per_frame(tx_cfg_octets_per_frame),
|
||||
.cfg_lmfc_offset(tx_cfg_lmfc_offset),
|
||||
.cfg_sysref_disable(tx_cfg_sysref_disable),
|
||||
.cfg_sysref_oneshot(tx_cfg_sysref_oneshot),
|
||||
.cfg_continuous_cgs(tx_cfg_continuous_cgs),
|
||||
.cfg_continuous_ilas(tx_cfg_continuous_ilas),
|
||||
.cfg_skip_ilas(tx_cfg_skip_ilas),
|
||||
.cfg_mframes_per_ilas(tx_cfg_mframes_per_ilas),
|
||||
.cfg_disable_char_replacement(tx_cfg_disable_char_replacement),
|
||||
.cfg_disable_scrambler(tx_cfg_disable_scrambler),
|
||||
|
||||
.ilas_config_rd(tx_ilas_config_rd),
|
||||
.ilas_config_addr(tx_ilas_config_addr),
|
||||
.ilas_config_data(tx_ilas_config_data),
|
||||
|
||||
.ctrl_manual_sync_request(1'b0),
|
||||
|
||||
.tx_ready(tx_ready),
|
||||
.tx_data({NUM_LANES{tx_data}}),
|
||||
|
||||
.sync(sync),
|
||||
.sysref(sysref_tx),
|
||||
|
||||
.phy_data(phy_data_out),
|
||||
.phy_charisk(phy_charisk_out)
|
||||
);
|
||||
|
||||
wire [NUM_LANES-1:0] rx_cfg_lanes_disable;
|
||||
wire [NUM_LINKS-1:0] rx_cfg_links_disable;
|
||||
wire [7:0] rx_cfg_beats_per_multiframe;
|
||||
wire [7:0] rx_cfg_octets_per_frame;
|
||||
wire [7:0] rx_cfg_lmfc_offset;
|
||||
wire rx_sysref_disable;
|
||||
wire rx_sysref_oneshot;
|
||||
wire rx_cfg_disable_scrambler;
|
||||
wire rx_cfg_disable_char_replacement;
|
||||
wire rx_cfg_buffer_early_release;
|
||||
wire [7:0] rx_cfg_buffer_delay;
|
||||
wire [NUM_LANES-1:0] rx_status_lane_ifs_ready;
|
||||
wire [NUM_LANES*14-1:0] rx_status_lane_latency;
|
||||
wire [NUM_LANES*32-1:0] rx_status_lane_frame_align_err_cnt;
|
||||
wire [31:0] rx_cfg_frame_align_err_threshold = 32'd4; // TODO: static config
|
||||
|
||||
jesd204_rx_static_config #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.OCTETS_PER_FRAME(OCTETS_PER_FRAME),
|
||||
.FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME),
|
||||
.SCR(ENABLE_SCRAMBLER),
|
||||
.BUFFER_EARLY_RELEASE(BUFFER_EARLY_RELEASE)
|
||||
) i_rx_cfg (
|
||||
.clk(clk),
|
||||
|
||||
.cfg_lanes_disable(rx_cfg_lanes_disable),
|
||||
.cfg_links_disable(rx_cfg_links_disable),
|
||||
.cfg_beats_per_multiframe(rx_cfg_beats_per_multiframe),
|
||||
.cfg_octets_per_frame(rx_cfg_octets_per_frame),
|
||||
.cfg_lmfc_offset(rx_cfg_lmfc_offset),
|
||||
.cfg_sysref_disable(rx_cfg_sysref_disable),
|
||||
.cfg_sysref_oneshot(rx_cfg_sysref_oneshot),
|
||||
.cfg_disable_scrambler(rx_cfg_disable_scrambler),
|
||||
.cfg_disable_char_replacement(rx_cfg_disable_char_replacement),
|
||||
.cfg_buffer_delay(rx_cfg_buffer_delay),
|
||||
.cfg_buffer_early_release(rx_cfg_buffer_early_release)
|
||||
);
|
||||
|
||||
jesd204_rx #(
|
||||
.NUM_LANES(NUM_LANES)
|
||||
) i_rx (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
|
||||
.cfg_lanes_disable(rx_cfg_lanes_disable),
|
||||
.cfg_links_disable(rx_cfg_links_disable),
|
||||
.cfg_beats_per_multiframe(rx_cfg_beats_per_multiframe),
|
||||
.cfg_octets_per_frame(rx_cfg_octets_per_frame),
|
||||
.cfg_lmfc_offset(rx_cfg_lmfc_offset),
|
||||
.cfg_sysref_disable(rx_cfg_sysref_disable),
|
||||
.cfg_sysref_oneshot(rx_cfg_sysref_oneshot),
|
||||
.cfg_disable_scrambler(rx_cfg_disable_scrambler),
|
||||
.cfg_disable_char_replacement(rx_cfg_disable_char_replacement),
|
||||
.cfg_buffer_delay(rx_cfg_buffer_delay),
|
||||
.cfg_buffer_early_release(rx_cfg_buffer_early_release),
|
||||
.cfg_frame_align_err_threshold(rx_cfg_frame_align_err_threshold),
|
||||
|
||||
.sync(sync),
|
||||
.sysref(sysref_rx),
|
||||
|
||||
.rx_data(rx_data),
|
||||
.rx_valid(rx_valid),
|
||||
|
||||
.phy_data(phy_data_in),
|
||||
.phy_charisk(phy_charisk_in),
|
||||
.phy_notintable({NUM_LANES{4'b0000}}),
|
||||
.phy_disperr({NUM_LANES{4'b0000}}),
|
||||
|
||||
.status_lane_ifs_ready(rx_status_lane_ifs_ready),
|
||||
.status_lane_latency(rx_status_lane_latency),
|
||||
.status_lane_frame_align_err_cnt(rx_status_lane_frame_align_err_cnt)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
data_mismatch <= 1'b0;
|
||||
end else if (rx_valid == 1'b1) begin
|
||||
if ((rx_data & rx_mask) !== ({NUM_LANES{rx_ref_data}} & rx_mask)) begin
|
||||
data_mismatch <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [NUM_LANES-1:0] lane_latency_match;
|
||||
|
||||
generate for (i = 0; i < NUM_LANES; i = i + 1) begin
|
||||
localparam LANE_OFFSET = BASE_LATENCY + LANE_DELAY + BEATS_PER_MULTIFRAME + i;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rx_status_lane_ifs_ready[i] == 1'b1 &&
|
||||
rx_status_lane_latency[i*14+13:i*14+2] == LANE_OFFSET) begin
|
||||
lane_latency_match[i] <= 1'b1;
|
||||
end else begin
|
||||
lane_latency_match[i] <= 1'b0;
|
||||
end
|
||||
end
|
||||
end endgenerate
|
||||
|
||||
always @(*) begin
|
||||
if (rx_valid !== 1'b1 || tx_ready !== 1'b1 || data_mismatch == 1'b1 ||
|
||||
&lane_latency_match != 1'b1) begin
|
||||
failed <= 1'b1;
|
||||
end else begin
|
||||
failed <= 1'b0;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
@@ -0,0 +1,30 @@
|
||||
NAME=`basename $0`
|
||||
|
||||
case "$SIMULATOR" in
|
||||
modelsim)
|
||||
# ModelSim flow
|
||||
vlib work
|
||||
vlog ${SOURCE} || exit 1
|
||||
vsim ${NAME} -do "add log /* -r; run -a" -gui || exit 1
|
||||
;;
|
||||
xcelium)
|
||||
# Xcelium flow
|
||||
xmvlog -NOWARN NONPRT ${SOURCE} || exit 1
|
||||
xmelab -access +rc ${NAME}
|
||||
xmsim ${NAME} -run -gui || exit 1
|
||||
;;
|
||||
xsim)
|
||||
# xsim flow
|
||||
xvlog -log ${NAME}_xvlog.log --sourcelibdir . ${SOURCE}
|
||||
xelab -log ${NAME}_xelab.log -debug all ${NAME}
|
||||
xsim work.${NAME} -R
|
||||
;;
|
||||
*)
|
||||
mkdir -p run
|
||||
mkdir -p vcd
|
||||
iverilog ${SOURCE} -o run/run_${NAME} $1 || exit 1
|
||||
|
||||
cd vcd
|
||||
../run/run_${NAME}
|
||||
;;
|
||||
esac
|
||||
@@ -0,0 +1,7 @@
|
||||
#!/bin/bash
|
||||
|
||||
SOURCE="rx_cgs_tb.v"
|
||||
SOURCE+=" ../jesd204_rx/jesd204_rx_cgs.v"
|
||||
|
||||
cd `dirname $0`
|
||||
source run_tb.sh
|
||||
@@ -0,0 +1,95 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module rx_cgs_tb;
|
||||
parameter VCD_FILE = "rx_cgs_tb.vcd";
|
||||
|
||||
`define TIMEOUT 1000
|
||||
`include "tb_base.v"
|
||||
|
||||
reg [3:0] char_is_error = 4'b0000;
|
||||
reg [3:0] char_is_cgs = 4'b1111;
|
||||
|
||||
integer counter = 'h00;
|
||||
wire ready;
|
||||
reg ready_prev = 1'b0;
|
||||
/*
|
||||
always @(posedge clk) begin
|
||||
if ($random % 2 == 0)
|
||||
char_is_error <= 4'b1111;
|
||||
else
|
||||
char_is_error <= 4'b0000;
|
||||
end
|
||||
*/
|
||||
always @(posedge clk) begin
|
||||
counter <= counter + 1;
|
||||
if (counter == 'h20) begin
|
||||
char_is_cgs <= 4'b0001;
|
||||
end else if (counter > 'h20) begin
|
||||
char_is_cgs <= 4'b0000;
|
||||
end
|
||||
end
|
||||
|
||||
jesd204_rx_cgs i_rx_cgs (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.char_is_cgs(char_is_cgs),
|
||||
.char_is_error(char_is_error),
|
||||
|
||||
.ready(ready)
|
||||
);
|
||||
|
||||
reg lost_sync = 1'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
ready_prev <= ready;
|
||||
if (ready_prev == 1'b1 && ready == 1'b0) begin
|
||||
lost_sync <= 1'b1;
|
||||
end
|
||||
failed <= lost_sync | ~ready;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,7 @@
|
||||
#!/bin/bash
|
||||
|
||||
SOURCE="rx_ctrl_tb.v"
|
||||
SOURCE+=" ../jesd204_rx/jesd204_rx_ctrl.v"
|
||||
|
||||
cd `dirname $0`
|
||||
source run_tb.sh
|
||||
@@ -0,0 +1,114 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module rx_ctrl_tb;
|
||||
parameter VCD_FILE = "rx_ctrl_tb.vcd";
|
||||
|
||||
`include "tb_base.v"
|
||||
|
||||
integer phy_reset_counter = 'h00;
|
||||
integer align_counter = 'h00;
|
||||
integer cgs_counter = 'h00;
|
||||
|
||||
reg phy_ready = 1'b0;
|
||||
reg aligned = 1'b0;
|
||||
reg cgs_ready = 1'b0;
|
||||
|
||||
wire en_align;
|
||||
wire cgs_reset;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
phy_reset_counter <= 'h00;
|
||||
phy_ready <= 1'b0;
|
||||
end else begin
|
||||
if (phy_reset_counter == 'h7) begin
|
||||
phy_ready <= 1'b1;
|
||||
end else begin
|
||||
phy_reset_counter <= phy_reset_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
aligned <= 1'b0;
|
||||
align_counter <= 'h00;
|
||||
end else if (phy_ready == 1'b1) begin
|
||||
if (en_align == 1'b1) begin
|
||||
if (align_counter == 'h20) begin
|
||||
aligned <= 1'b1;
|
||||
end else begin
|
||||
align_counter <= align_counter + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk or posedge cgs_reset) begin
|
||||
if (cgs_reset == 1'b1) begin
|
||||
cgs_counter <= 'h00;
|
||||
cgs_ready <= 1'b0;
|
||||
end else begin
|
||||
if (cgs_counter == 'h20) begin
|
||||
cgs_ready <= 1'b1;
|
||||
end else begin
|
||||
cgs_counter <= cgs_counter + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
jesd204_rx_ctrl i_rx_ctrl (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.phy_ready(phy_ready),
|
||||
.phy_en_char_align(en_align),
|
||||
.cgs_reset(cgs_reset),
|
||||
.cgs_ready(cgs_ready)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,10 @@
|
||||
#!/bin/bash
|
||||
|
||||
SOURCE="rx_lane_tb.v "
|
||||
SOURCE+=" ../jesd204_rx/jesd204_rx_lane.v ../jesd204_rx/jesd204_rx_cgs.v ../jesd204_rx/elastic_buffer.v"
|
||||
SOURCE+=" ../jesd204_rx/align_mux.v ../jesd204_rx/jesd204_ilas_monitor.v"
|
||||
SOURCE+=" ../jesd204_common/jesd204_scrambler.v"
|
||||
SOURCE+=" ../jesd204_common/pipeline_stage.v"
|
||||
|
||||
cd `dirname $0`
|
||||
source run_tb.sh
|
||||
@@ -0,0 +1,148 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module rx_lane_tb;
|
||||
parameter VCD_FILE = "rx_lane_tb.vcd";
|
||||
|
||||
`include "tb_base.v"
|
||||
|
||||
reg [31:0] data = {4{{3'd5,5'd28}}};
|
||||
reg [3:0] disperr = 4'b0000;
|
||||
reg [3:0] notintable = 4'b0000;
|
||||
reg [3:0] charisk = 4'b1111;
|
||||
|
||||
wire ilas_config_valid;
|
||||
wire [1:0] ilas_config_addr;
|
||||
wire [4*8-1:0] ilas_config_data;
|
||||
wire [31:0] status_err_statistics_cnt;
|
||||
|
||||
wire [4*8-1:0] rx_data;
|
||||
|
||||
wire [1:0] status_cgs_state;
|
||||
wire status_ifs_ready;
|
||||
wire [1:0] status_frame_align;
|
||||
|
||||
integer counter = 'h00;
|
||||
wire [31:0] counter2 = (counter - 'h20) * 4;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if ($urandom % 400 == 0)
|
||||
disperr <= 4'b1111;
|
||||
else if ($urandom % 400 == 1)
|
||||
disperr <= 4'b0001;
|
||||
else if ($urandom % 400 == 2)
|
||||
disperr <= 4'b0011;
|
||||
else if ($urandom % 400 == 3)
|
||||
disperr <= 4'b0111;
|
||||
else
|
||||
disperr <= 4'b0000;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if ($random % 500 == 0)
|
||||
notintable <= 4'b1111;
|
||||
else
|
||||
notintable <= 4'b0000;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
counter <= counter + 1;
|
||||
if (counter == 'h20) begin
|
||||
charisk <= 'h0001;
|
||||
data[31:8] <= {{24'h020100}};
|
||||
end else if (counter == 'h21) begin
|
||||
charisk <= 'h0000;
|
||||
data[31:0] <= {{32'h06050403}};
|
||||
end else if (counter > 'h21) begin
|
||||
data <= (counter2 + 'h2) << 24 |
|
||||
(counter2 + 'h1) << 16 |
|
||||
(counter2 + 'h0) << 8 |
|
||||
(counter2 - 'h1);
|
||||
charisk <= 4'b0000;
|
||||
end
|
||||
end
|
||||
|
||||
reg buffer_release_n = 1'b0;
|
||||
wire buffer_ready_n;
|
||||
|
||||
always @(posedge clk) begin
|
||||
buffer_release_n <= buffer_ready_n;
|
||||
end
|
||||
|
||||
jesd204_rx_lane i_rx_lane (
|
||||
.clk(clk),
|
||||
.reset(1'b0),
|
||||
|
||||
.phy_data(data),
|
||||
.phy_charisk(charisk),
|
||||
.phy_disperr(disperr),
|
||||
.phy_notintable(notintable),
|
||||
|
||||
.cgs_reset(reset),
|
||||
.cgs_ready(),
|
||||
|
||||
.ifs_reset(1'b0),
|
||||
|
||||
.rx_data(rx_data),
|
||||
|
||||
.buffer_release_n(buffer_release_n),
|
||||
.buffer_ready_n(buffer_ready_n),
|
||||
|
||||
.cfg_disable_scrambler(1'b0),
|
||||
.ilas_config_valid(ilas_config_valid),
|
||||
.ilas_config_addr(ilas_config_addr),
|
||||
.ilas_config_data(ilas_config_data),
|
||||
|
||||
.ctrl_err_statistics_reset(1'b0),
|
||||
.ctrl_err_statistics_mask(3'h7),
|
||||
.status_err_statistics_cnt(status_err_statistics_cnt),
|
||||
|
||||
.status_cgs_state(status_cgs_state),
|
||||
.status_ifs_ready(status_ifs_ready),
|
||||
.status_frame_align(status_frame_align)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,12 @@
|
||||
#!/bin/bash
|
||||
|
||||
SOURCE="rx_tb.v"
|
||||
SOURCE+=" ../jesd204_common/jesd204_lmfc.v ../jesd204_common/jesd204_scrambler.v ../jesd204_common/jesd204_eof_generator.v"
|
||||
SOURCE+=" ../jesd204_common/pipeline_stage.v"
|
||||
SOURCE+=" ../jesd204_rx_static_config/jesd204_rx_static_config.v "
|
||||
SOURCE+=" ../jesd204_rx/jesd204_rx.v ../jesd204_rx/jesd204_rx_lane.v ../jesd204_rx/jesd204_lane_latency_monitor.v"
|
||||
SOURCE+=" ../jesd204_rx/jesd204_ilas_monitor.v ../jesd204_rx/align_mux.v ../jesd204_rx/jesd204_rx_cgs.v"
|
||||
SOURCE+=" ../jesd204_rx/jesd204_rx_ctrl.v ../jesd204_rx/elastic_buffer.v"
|
||||
|
||||
cd `dirname $0`
|
||||
source run_tb.sh
|
||||
@@ -0,0 +1,215 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module rx_tb;
|
||||
parameter VCD_FILE = "rx_tb.vcd";
|
||||
parameter NUM_LANES = 1;
|
||||
parameter NUM_LINKS = 1;
|
||||
parameter OCTETS_PER_FRAME = 8;
|
||||
parameter FRAMES_PER_MULTIFRAME = 32;
|
||||
|
||||
`include "tb_base.v"
|
||||
|
||||
integer phy_reset_counter = 'h00;
|
||||
integer align_counter = 'h00;
|
||||
|
||||
reg phy_ready = 1'b0;
|
||||
reg aligned = 1'b0;
|
||||
|
||||
wire en_align;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
phy_reset_counter <= 'h00;
|
||||
phy_ready <= 1'b0;
|
||||
end else begin
|
||||
if (phy_reset_counter == 'h40) begin
|
||||
phy_ready <= 1'b1;
|
||||
end else begin
|
||||
phy_reset_counter <= phy_reset_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
aligned <= 1'b0;
|
||||
align_counter <= 'h00;
|
||||
end else if (phy_ready == 1'b1) begin
|
||||
if (en_align == 1'b1) begin
|
||||
if (align_counter == 'h20) begin
|
||||
aligned <= 1'b1;
|
||||
end else begin
|
||||
align_counter <= align_counter + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
localparam KCHAR_ILAS_START = {3'd0,5'd28};
|
||||
localparam KCHAR_LANE_ALIGN = {3'd3,5'd28};
|
||||
localparam KCHAR_ILAS_CONFIG = {3'd4,5'd28};
|
||||
localparam KCHAR_CGS = {3'd5,5'd28};
|
||||
localparam KCHAR_FRAME_ALIGN = {3'd7,5'd28};
|
||||
|
||||
reg [31:0] data = KCHAR_CGS;
|
||||
reg [3:0] charisk = 4'b1111;
|
||||
reg [3:0] disperr = 4'b0000;
|
||||
reg [3:0] notintable = 4'b0000;
|
||||
wire [NUM_LINKS-1:0] sync;
|
||||
|
||||
integer counter = 'h00;
|
||||
wire [31:0] counter2 = (counter - 'h10) * 4;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if ( &sync == 1'b0 ) begin
|
||||
counter <= 'h00;
|
||||
charisk <= 4'b1111;
|
||||
data <= {KCHAR_CGS,KCHAR_CGS,KCHAR_CGS,KCHAR_CGS};
|
||||
end else begin
|
||||
counter <= counter + 1;
|
||||
if (counter >= 'h8 && counter < 'h28) begin
|
||||
if (counter % 'h8 == 'h0) begin
|
||||
if (counter != 'h10) begin
|
||||
data <= {24'h00,KCHAR_ILAS_START};
|
||||
charisk <= 4'b0001;
|
||||
end else begin
|
||||
data <= {16'hffaa,KCHAR_ILAS_CONFIG,KCHAR_ILAS_START};
|
||||
charisk <= 4'b0011;
|
||||
end
|
||||
end else if (counter % 'h8 == 'h7) begin
|
||||
data <= {KCHAR_LANE_ALIGN,24'h00};
|
||||
charisk <= 4'b1000;
|
||||
end else begin
|
||||
data <= {32'h00};
|
||||
charisk <= 4'b0000;
|
||||
end
|
||||
end else if (counter > 'h10) begin
|
||||
data <= (counter2 + 'h2) << 24 |
|
||||
(counter2 + 'h1) << 16 |
|
||||
(counter2 + 'h0) << 8 |
|
||||
(counter2 - 'h1);
|
||||
charisk <= 4'b0000;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire [NUM_LANES-1:0] cfg_lanes_disable;
|
||||
wire [NUM_LINKS-1:0] cfg_links_disable;
|
||||
wire [7:0] cfg_beats_per_multiframe;
|
||||
wire [7:0] cfg_octets_per_frame;
|
||||
wire [7:0] cfg_lmfc_offset;
|
||||
wire cfg_sysref_oneshot;
|
||||
wire cfg_sysref_disable;
|
||||
wire cfg_disable_scrambler;
|
||||
wire cfg_buffer_early_release;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if ($urandom % 400 == 0)
|
||||
disperr <= 4'b1111;
|
||||
else if ($urandom % 400 == 1)
|
||||
disperr <= 4'b0001;
|
||||
else if ($urandom % 400 == 2)
|
||||
disperr <= 4'b0011;
|
||||
else if ($urandom % 400 == 3)
|
||||
disperr <= 4'b0111;
|
||||
else
|
||||
disperr <= 4'b0000;
|
||||
end
|
||||
wire [NUM_LANES*32-1:0] status_err_statistics_cnt;
|
||||
|
||||
jesd204_rx_static_config #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.NUM_LINKS(NUM_LINKS),
|
||||
.OCTETS_PER_FRAME(OCTETS_PER_FRAME),
|
||||
.FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME)
|
||||
) i_cfg (
|
||||
.clk(clk),
|
||||
|
||||
.cfg_lanes_disable(cfg_lanes_disable),
|
||||
.cfg_links_disable(cfg_links_disable),
|
||||
.cfg_beats_per_multiframe(cfg_beats_per_multiframe),
|
||||
.cfg_octets_per_frame(cfg_octets_per_frame),
|
||||
.cfg_lmfc_offset(cfg_lmfc_offset),
|
||||
.cfg_sysref_oneshot(cfg_sysref_oneshot),
|
||||
.cfg_sysref_disable(cfg_sysref_disable),
|
||||
.cfg_disable_scrambler(cfg_disable_scrambler),
|
||||
.cfg_buffer_early_release(cfg_buffer_early_release)
|
||||
);
|
||||
|
||||
jesd204_rx #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.NUM_LINKS(NUM_LINKS)
|
||||
) i_rx (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
|
||||
.cfg_lanes_disable(cfg_lanes_disable),
|
||||
.cfg_links_disable(cfg_links_disable),
|
||||
.cfg_beats_per_multiframe(cfg_beats_per_multiframe),
|
||||
.cfg_octets_per_frame(cfg_octets_per_frame),
|
||||
.cfg_lmfc_offset(cfg_lmfc_offset),
|
||||
.cfg_sysref_oneshot(cfg_sysref_oneshot),
|
||||
.cfg_sysref_disable(cfg_sysref_disable),
|
||||
.cfg_disable_scrambler(cfg_disable_scrambler),
|
||||
.cfg_buffer_early_release(cfg_buffer_early_release),
|
||||
|
||||
.ctrl_err_statistics_reset(1'b0),
|
||||
.ctrl_err_statistics_mask(3'h7),
|
||||
|
||||
.status_err_statistics_cnt(status_err_statistics_cnt),
|
||||
|
||||
.phy_en_char_align(en_align),
|
||||
|
||||
.phy_data({NUM_LANES{data}}),
|
||||
.phy_charisk({NUM_LANES{charisk}}),
|
||||
.phy_notintable({NUM_LANES{notintable}}),
|
||||
.phy_disperr({NUM_LANES{disperr}}),
|
||||
.sync(sync),
|
||||
.sysref(sysref)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,994 @@
|
||||
e949a63d63222000
|
||||
f44cb1c66f152c3e
|
||||
fc37ba9a78bb369f
|
||||
ffd7bf617e9e3d8f
|
||||
fe9ebf617fd73fff
|
||||
f8bbba9a7c373d8f
|
||||
ef15b1c6744c369f
|
||||
e322a63d69492c3e
|
||||
d6b699c25cdd2000
|
||||
cbb38e3950ea13c1
|
||||
c3c8856547440960
|
||||
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|
||||
c161809e40280001
|
||||
c744856543c80270
|
||||
d0ea8e394bb30960
|
||||
dcdd99c256b613c1
|
||||
e949a63d63222000
|
||||
f44cb1c66f152c3e
|
||||
fc37ba9a78bb369f
|
||||
ffd7bf617e9e3d8f
|
||||
fe9ebf617fd73fff
|
||||
f8bbba9a7c373d8f
|
||||
ef15b1c6744c369f
|
||||
e322a63d69492c3e
|
||||
d6b699c25cdd2000
|
||||
cbb38e3950ea13c1
|
||||
c3c8856547440960
|
||||
c028809e41610270
|
||||
c161809e40280001
|
||||
c744856543c80270
|
||||
d0ea8e394bb30960
|
||||
dcdd99c256b613c1
|
||||
e949a63d63222000
|
||||
f44cb1c66f152c3e
|
||||
fc37ba9a78bb369f
|
||||
ffd7bf617e9e3d8f
|
||||
fe9ebf617fd73fff
|
||||
f8bbba9a7c373d8f
|
||||
ef15b1c6744c369f
|
||||
e322a63d69492c3e
|
||||
d6b699c25cdd2000
|
||||
cbb38e3950ea13c1
|
||||
c3c8856547440960
|
||||
c028809e41610270
|
||||
c161809e40280001
|
||||
c744856543c80270
|
||||
d0ea8e394bb30960
|
||||
dcdd99c256b613c1
|
||||
e949a63d63222000
|
||||
f44cb1c66f152c3e
|
||||
fc37ba9a78bb369f
|
||||
ffd7bf617e9e3d8f
|
||||
fe9ebf617fd73fff
|
||||
f8bbba9a7c373d8f
|
||||
ef15b1c6744c369f
|
||||
e322a63d69492c3e
|
||||
d6b699c25cdd2000
|
||||
cbb38e3950ea13c1
|
||||
c3c8856547440960
|
||||
c028809e41610270
|
||||
c161809e40280001
|
||||
c744856543c80270
|
||||
d0ea8e394bb30960
|
||||
dcdd99c256b613c1
|
||||
e949a63d63222000
|
||||
f44cb1c66f152c3e
|
||||
fc37ba9a78bb369f
|
||||
ffd7bf617e9e3d8f
|
||||
fe9ebf617fd73fff
|
||||
f8bbba9a7c373d8f
|
||||
ef15b1c6744c369f
|
||||
e322a63d69492c3e
|
||||
d6b699c25cdd2000
|
||||
cbb38e3950ea13c1
|
||||
c3c8856547440960
|
||||
c028809e41610270
|
||||
c161809e40280001
|
||||
c744856543c80270
|
||||
d0ea8e394bb30960
|
||||
dcdd99c256b613c1
|
||||
e949a63d63222000
|
||||
f44cb1c66f152c3e
|
||||
fc37ba9a78bb369f
|
||||
ffd7bf617e9e3d8f
|
||||
fe9ebf617fd73fff
|
||||
f8bbba9a7c373d8f
|
||||
ef15b1c6744c369f
|
||||
e322a63d69492c3e
|
||||
d6b699c25cdd2000
|
||||
cbb38e3950ea13c1
|
||||
c3c8856547440960
|
||||
c028809e41610270
|
||||
c161809e40280001
|
||||
c744856543c80270
|
||||
d0ea8e394bb30960
|
||||
dcdd99c256b613c1
|
||||
e949a63d63222000
|
||||
f44cb1c66f152c3e
|
||||
fc37ba9a78bb369f
|
||||
ffd7bf617e9e3d8f
|
||||
fe9ebf617fd73fff
|
||||
f8bbba9a7c373d8f
|
||||
ef15b1c6744c369f
|
||||
e322a63d69492c3e
|
||||
d6b699c25cdd2000
|
||||
cbb38e3950ea13c1
|
||||
c3c8856547440960
|
||||
c028809e41610270
|
||||
c161809e40280001
|
||||
c744856543c80270
|
||||
d0ea8e394bb30960
|
||||
dcdd99c256b613c1
|
||||
e949a63d63222000
|
||||
f44cb1c66f152c3e
|
||||
fc37ba9a78bb369f
|
||||
ffd7bf617e9e3d8f
|
||||
fe9ebf617fd73fff
|
||||
f8bbba9a7c373d8f
|
||||
ef15b1c6744c369f
|
||||
e322a63d69492c3e
|
||||
d6b699c25cdd2000
|
||||
cbb38e3950ea13c1
|
||||
c3c8856547440960
|
||||
c028809e41610270
|
||||
c161809e40280001
|
||||
c744856543c80270
|
||||
d0ea8e394bb30960
|
||||
dcdd99c256b613c1
|
||||
e949a63d63222000
|
||||
f44cb1c66f152c3e
|
||||
fc37ba9a78bb369f
|
||||
ffd7bf617e9e3d8f
|
||||
fe9ebf617fd73fff
|
||||
f8bbba9a7c373d8f
|
||||
ef15b1c6744c369f
|
||||
e322a63d69492c3e
|
||||
d6b699c25cdd2000
|
||||
cbb38e3950ea13c1
|
||||
c3c8856547440960
|
||||
c028809e41610270
|
||||
c161809e40280001
|
||||
c744856543c80270
|
||||
d0ea8e394bb30960
|
||||
dcdd99c256b613c1
|
||||
e949a63d63222000
|
||||
f44cb1c66f152c3e
|
||||
fc37ba9a78bb369f
|
||||
ffd7bf617e9e3d8f
|
||||
fe9ebf617fd73fff
|
||||
f8bbba9a7c373d8f
|
||||
ef15b1c6744c369f
|
||||
e322a63d69492c3e
|
||||
d6b699c25cdd2000
|
||||
cbb38e3950ea13c1
|
||||
c3c8856547440960
|
||||
c028809e41610270
|
||||
c161809e40280001
|
||||
c744856543c80270
|
||||
d0ea8e394bb30960
|
||||
dcdd99c256b613c1
|
||||
e949a63d63222000
|
||||
f44cb1c66f152c3e
|
||||
fc37ba9a78bb369f
|
||||
ffd7bf617e9e3d8f
|
||||
fe9ebf617fd73fff
|
||||
f8bbba9a7c373d8f
|
||||
ef15b1c6744c369f
|
||||
e322a63d69492c3e
|
||||
d6b699c25cdd2000
|
||||
cbb38e3950ea13c1
|
||||
c3c8856547440960
|
||||
c028809e41610270
|
||||
c161809e40280001
|
||||
c744856543c80270
|
||||
d0ea8e394bb30960
|
||||
dcdd99c256b613c1
|
||||
e949a63d63222000
|
||||
f44cb1c66f152c3e
|
||||
fc37ba9a78bb369f
|
||||
ffd7bf617e9e3d8f
|
||||
fe9ebf617fd73fff
|
||||
f8bbba9a7c373d8f
|
||||
ef15b1c6744c369f
|
||||
e322a63d69492c3e
|
||||
d6b699c25cdd2000
|
||||
cbb38e3950ea13c1
|
||||
c3c8856547440960
|
||||
c028809e41610270
|
||||
c161809e40280001
|
||||
c744856543c80270
|
||||
d0ea8e394bb30960
|
||||
dcdd99c256b613c1
|
||||
e949a63d63222000
|
||||
f44cb1c66f152c3e
|
||||
fc37ba9a78bb369f
|
||||
ffd7bf617e9e3d8f
|
||||
fe9ebf617fd73fff
|
||||
f8bbba9a7c373d8f
|
||||
ef15b1c6744c369f
|
||||
e322a63d69492c3e
|
||||
d6b699c25cdd2000
|
||||
cbb38e3950ea13c1
|
||||
c3c8856547440960
|
||||
c028809e41610270
|
||||
c161809e40280001
|
||||
c744856543c80270
|
||||
d0ea8e394bb30960
|
||||
dcdd99c256b613c1
|
||||
e949a63d63222000
|
||||
f44cb1c66f152c3e
|
||||
fc37ba9a78bb369f
|
||||
ffd7bf617e9e3d8f
|
||||
fe9ebf617fd73fff
|
||||
f8bbba9a7c373d8f
|
||||
ef15b1c6744c369f
|
||||
e322a63d69492c3e
|
||||
d6b699c25cdd2000
|
||||
cbb38e3950ea13c1
|
||||
c3c8856547440960
|
||||
c028809e41610270
|
||||
c161809e40280001
|
||||
c744856543c80270
|
||||
d0ea8e394bb30960
|
||||
dcdd99c256b613c1
|
||||
e949a63d63222000
|
||||
f44cb1c66f152c3e
|
||||
fc37ba9a78bb369f
|
||||
ffd7bf617e9e3d8f
|
||||
fe9ebf617fd73fff
|
||||
f8bbba9a7c373d8f
|
||||
ef15b1c6744c369f
|
||||
e322a63d69492c3e
|
||||
d6b699c25cdd2000
|
||||
cbb38e3950ea13c1
|
||||
c3c8856547440960
|
||||
c028809e41610270
|
||||
c161809e40280001
|
||||
c744856543c80270
|
||||
d0ea8e394bb30960
|
||||
dcdd99c256b613c1
|
||||
e949a63d63222000
|
||||
f44cb1c66f152c3e
|
||||
fc37ba9a78bb369f
|
||||
ffd7bf617e9e3d8f
|
||||
fe9ebf617fd73fff
|
||||
f8bbba9a7c373d8f
|
||||
ef15b1c6744c369f
|
||||
e322a63d69492c3e
|
||||
d6b699c25cdd2000
|
||||
cbb38e3950ea13c1
|
||||
c3c8856547440960
|
||||
c028809e41610270
|
||||
c161809e40280001
|
||||
c744856543c80270
|
||||
d0ea8e394bb30960
|
||||
dcdd99c256b613c1
|
||||
e949a63d63222000
|
||||
f44cb1c66f152c3e
|
||||
fc37ba9a78bb369f
|
||||
ffd7bf617e9e3d8f
|
||||
fe9ebf617fd73fff
|
||||
f8bbba9a7c373d8f
|
||||
ef15b1c6744c369f
|
||||
e322a63d69492c3e
|
||||
d6b699c25cdd2000
|
||||
cbb38e3950ea13c1
|
||||
c3c8856547440960
|
||||
c028809e41610270
|
||||
c161809e40280001
|
||||
c744856543c80270
|
||||
d0ea8e394bb30960
|
||||
dcdd99c256b613c1
|
||||
e949a63d63222000
|
||||
f44cb1c66f152c3e
|
||||
fc37ba9a78bb369f
|
||||
ffd7bf617e9e3d8f
|
||||
fe9ebf617fd73fff
|
||||
f8bbba9a7c373d8f
|
||||
ef15b1c6744c369f
|
||||
e322a63d69492c3e
|
||||
d6b699c25cdd2000
|
||||
cbb38e3950ea13c1
|
||||
c3c8856547440960
|
||||
c028809e41610270
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|
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|
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|
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|
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|
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|
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|
||||
84f67bebbd278ca8
|
||||
16d30f6c6175ba84
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
cd8cda62b3bc4b39
|
||||
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|
||||
03efac484565e759
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
ecb14d78c9c07281
|
||||
011d471524a8890f
|
||||
845132665608c185
|
||||
2cac39d0e77c1506
|
||||
@@ -0,0 +1,7 @@
|
||||
#!/bin/bash
|
||||
|
||||
SOURCE="scrambler_64b_tb.v"
|
||||
SOURCE+=" ../jesd204_common/jesd204_scrambler_64b.v"
|
||||
|
||||
cd `dirname $0`
|
||||
source run_tb.sh
|
||||
@@ -0,0 +1,145 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module scrambler_64b_tb;
|
||||
parameter VCD_FILE = "scrambler_64b_tb.vcd";
|
||||
|
||||
`include "tb_base.v"
|
||||
reg failed_t1 = 1'b0;
|
||||
reg failed_t2 = 1'b0;
|
||||
|
||||
// Test scrambler against descrambler
|
||||
//
|
||||
// Descrambled data should match the input of the scrambler.
|
||||
reg [63:0] data_in = 'h0;
|
||||
reg [63:0] data_out_expected;
|
||||
wire [63:0] data_scrambled;
|
||||
wire [63:0] data_out;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
data_in <= 'h0001020304050607;
|
||||
end else begin
|
||||
data_in <= data_in + {8{8'h08}};
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
jesd204_scrambler_64b #(
|
||||
.DESCRAMBLE(0)
|
||||
) i_scrambler (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.enable(1'b1),
|
||||
.data_in(data_in),
|
||||
.data_out(data_scrambled)
|
||||
);
|
||||
|
||||
jesd204_scrambler_64b #(
|
||||
.DESCRAMBLE(1)
|
||||
) i_descrambler (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.enable(1'b1),
|
||||
.data_in(data_scrambled),
|
||||
.data_out(data_out)
|
||||
);
|
||||
always @(posedge clk) begin
|
||||
if (data_in != data_out && failed_t1 == 1'b0) begin
|
||||
failed_t1 <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// Test descrambler against reference data
|
||||
//
|
||||
// Check if descrambler can synchronize and a stream captured from
|
||||
// a scrambler output. The descrambled data stream should match the input of
|
||||
// the scrambler.
|
||||
reg [63:0] descrambler_data_in = 'h0;
|
||||
reg [63:0] data_ref = 'h0;
|
||||
wire[63:0] descrambler_data_out;
|
||||
|
||||
integer i;
|
||||
reg [63:0] scrambler_64b_input [0:993];
|
||||
reg [63:0] scrambler_64b_output [0:993];
|
||||
reg t2_enable = 1'b0;
|
||||
|
||||
initial begin
|
||||
$readmemh("scrambler_64b_input.txt", scrambler_64b_input); // Input to a scrambler
|
||||
$readmemh("scrambler_64b_output.txt", scrambler_64b_output); // Output of a scrambler
|
||||
@(negedge reset);
|
||||
@(posedge clk);
|
||||
for (i=0;i<994;i=i+1) begin
|
||||
@(posedge clk);
|
||||
descrambler_data_in <= scrambler_64b_output[i];
|
||||
data_ref <= scrambler_64b_input[i];
|
||||
if (i==1) t2_enable <= 1'b1;
|
||||
if (i==993) t2_enable <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
jesd204_scrambler_64b #(
|
||||
.DESCRAMBLE(1)
|
||||
) i_descrambler2 (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.enable(1'b1),
|
||||
.data_in(descrambler_data_in),
|
||||
.data_out(descrambler_data_out)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (data_ref != descrambler_data_out && failed_t2 == 1'b0 && t2_enable) begin
|
||||
failed_t2 <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
failed <= failed_t1 || failed_t2;
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,7 @@
|
||||
#!/bin/bash
|
||||
|
||||
SOURCE="scrambler_tb.v"
|
||||
SOURCE+=" ../jesd204_common/jesd204_scrambler.v"
|
||||
|
||||
cd `dirname $0`
|
||||
source run_tb.sh
|
||||
@@ -0,0 +1,91 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module scrambler_tb;
|
||||
parameter VCD_FILE = "scrambler_tb.vcd";
|
||||
|
||||
`include "tb_base.v"
|
||||
|
||||
reg [31:0] data_in;
|
||||
reg [31:0] data_out_expected;
|
||||
wire [31:0] data_scrambled;
|
||||
wire [31:0] data_out;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
data_in <= 'h03020100;
|
||||
end else begin
|
||||
data_in <= data_in + {4{8'h04}};
|
||||
end
|
||||
end
|
||||
|
||||
jesd204_scrambler #(
|
||||
.DESCRAMBLE(0)
|
||||
) i_scrambler (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.enable(1'b1),
|
||||
.data_in(data_in),
|
||||
.data_out(data_scrambled)
|
||||
);
|
||||
|
||||
jesd204_scrambler #(
|
||||
.DESCRAMBLE(1)
|
||||
) i_descrambler (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.enable(1'b1),
|
||||
.data_in(data_scrambled),
|
||||
.data_out(data_out)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (data_in != data_out && failed == 1'b0) begin
|
||||
failed <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,8 @@
|
||||
#!/bin/bash
|
||||
|
||||
SOURCE="soft_pcs_8b10b_sequence_tb.v"
|
||||
SOURCE+=" ../jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v"
|
||||
SOURCE+=" ../jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v"
|
||||
|
||||
cd `dirname $0`
|
||||
source run_tb.sh
|
||||
@@ -0,0 +1,134 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module soft_pcs_8b10b_sequence_tb;
|
||||
parameter VCD_FILE = "soft_pcs_8b10b_sequence_tb.vcd";
|
||||
|
||||
`include "tb_base.v"
|
||||
|
||||
// Send a random sequence of characters to the decoder and make sure the
|
||||
// decoder produces the same character sequence and no disparity or
|
||||
// not-in-table errors
|
||||
|
||||
wire [9:0] raw_data;
|
||||
|
||||
reg [7:0] encoder_char = 'h00;
|
||||
reg encoder_charisk = 1'b0;
|
||||
|
||||
wire [7:0] decoder_char;
|
||||
wire decoder_charisk;
|
||||
wire decoder_notintable;
|
||||
wire decoder_disperr;
|
||||
|
||||
reg encoder_disparity = 1'b0;
|
||||
wire encoder_disparity_s;
|
||||
reg decoder_disparity = 1'b0;
|
||||
wire decoder_disparity_s;
|
||||
|
||||
integer x;
|
||||
|
||||
reg inject_enc_disparity_error = 1'b0;
|
||||
|
||||
/*
|
||||
always @(posedge clk) begin
|
||||
if ({$random} % 256 == 0) begin
|
||||
inject_enc_disparity_error <= 1'b1;
|
||||
end else begin
|
||||
inject_enc_disparity_error <= 1'b0;
|
||||
end
|
||||
end
|
||||
*/
|
||||
|
||||
always @(posedge clk) begin
|
||||
x = {$random} % (256 + 5);
|
||||
if (x < 256) begin
|
||||
encoder_char <= x & 8'hff;
|
||||
encoder_charisk <= 1'b0;
|
||||
end else begin
|
||||
case (x - 256)
|
||||
0: encoder_char <= {3'd0,5'd28};
|
||||
1: encoder_char <= {3'd3,5'd28};
|
||||
2: encoder_char <= {3'd4,5'd28};
|
||||
3: encoder_char <= {3'd5,5'd28};
|
||||
4: encoder_char <= {3'd7,5'd28};
|
||||
endcase
|
||||
encoder_charisk <= 1'b1;
|
||||
end
|
||||
encoder_disparity <= encoder_disparity_s ^ inject_enc_disparity_error;
|
||||
decoder_disparity <= decoder_disparity_s;
|
||||
end
|
||||
|
||||
jesd204_8b10b_encoder i_enc (
|
||||
.in_char(encoder_char),
|
||||
.in_charisk(encoder_charisk),
|
||||
.out_char(raw_data),
|
||||
|
||||
.in_disparity(encoder_disparity),
|
||||
.out_disparity(encoder_disparity_s)
|
||||
);
|
||||
|
||||
jesd204_8b10b_decoder i_dec (
|
||||
.in_char(raw_data),
|
||||
.out_char(decoder_char),
|
||||
.out_notintable(decoder_notintable),
|
||||
.out_disperr(decoder_disperr),
|
||||
.out_charisk(decoder_charisk),
|
||||
|
||||
.in_disparity(decoder_disparity),
|
||||
.out_disparity(decoder_disparity_s)
|
||||
);
|
||||
|
||||
wire char_mismatch = encoder_char != decoder_char;
|
||||
wire charisk_mismatch = encoder_charisk != decoder_charisk;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (char_mismatch == 1'b1 || charisk_mismatch == 1'b1 ||
|
||||
decoder_notintable == 1'b1 || decoder_disperr == 1'b1) begin
|
||||
failed <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,8 @@
|
||||
#!/bin/bash
|
||||
|
||||
SOURCE="soft_pcs_8b10b_table_tb.v"
|
||||
SOURCE+=" ../jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v"
|
||||
SOURCE+=" ../jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v"
|
||||
|
||||
cd `dirname $0`
|
||||
source run_tb.sh
|
||||
@@ -0,0 +1,150 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module soft_pcs_8b10b_table_tb;
|
||||
parameter VCD_FILE = "soft_pcs_8b10b_table_tb.vcd";
|
||||
|
||||
`include "tb_base.v"
|
||||
|
||||
// Build a table of all valid 8b10b words using the encoder and then check
|
||||
// for every possible 10-bit value that the decoder correctly reports the
|
||||
// not-in-table flag
|
||||
|
||||
reg [1023:0] valid_table = 'h00;
|
||||
|
||||
reg [8:0] counter = 10'h00;
|
||||
|
||||
reg [7:0] encoder_char = 8'h00;
|
||||
reg encoder_charisk = 1'b0;
|
||||
reg encoder_disparity = 1'b0;
|
||||
wire [9:0] encoder_raw;
|
||||
|
||||
wire [7:0] decoder_char;
|
||||
wire decoder_notintable;
|
||||
wire decoder_charisk;
|
||||
reg [9:0] decoder_raw = 10'h00;
|
||||
|
||||
reg build_k28 = 1'b0;
|
||||
reg build_table = 1'b1;
|
||||
|
||||
reg decoder_disparity = 1'b0;
|
||||
wire decoder_disparity_s;
|
||||
|
||||
always @(posedge clk) begin
|
||||
counter <= counter + 1'b1;
|
||||
|
||||
if (counter == 'h1ff) begin
|
||||
build_k28 <= 1'b1;
|
||||
end else if (counter == 'h9 && build_k28 == 1'b1) begin
|
||||
build_table <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
encoder_disparity <= counter[0];
|
||||
if (build_k28 == 1'b0) begin
|
||||
encoder_char <= counter[8:1];
|
||||
encoder_charisk <= 1'b0;
|
||||
end else begin
|
||||
case (counter[8:1])
|
||||
0: encoder_char <= {3'd0,5'd28};
|
||||
1: encoder_char <= {3'd3,5'd28};
|
||||
2: encoder_char <= {3'd4,5'd28};
|
||||
3: encoder_char <= {3'd5,5'd28};
|
||||
4: encoder_char <= {3'd7,5'd28};
|
||||
endcase
|
||||
encoder_charisk <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
jesd204_8b10b_encoder i_enc (
|
||||
.in_char(encoder_char),
|
||||
.in_charisk(encoder_charisk),
|
||||
.in_disparity(encoder_disparity),
|
||||
.out_char(encoder_raw)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (build_table == 1'b1) begin
|
||||
valid_table[encoder_raw] <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (build_table == 1'b0) begin
|
||||
decoder_disparity <= ~decoder_disparity;
|
||||
if (decoder_disparity == 1'b1 && decoder_raw != 'h3ff) begin
|
||||
decoder_raw <= decoder_raw + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
end
|
||||
|
||||
jesd204_8b10b_decoder i_dec (
|
||||
.in_char(build_table ? encoder_raw : decoder_raw),
|
||||
.out_char(decoder_char),
|
||||
.out_notintable(decoder_notintable),
|
||||
.out_charisk(decoder_charisk),
|
||||
|
||||
.in_disparity(decoder_disparity),
|
||||
.out_disparity(decoder_disparity_s)
|
||||
);
|
||||
|
||||
wire decoder_should_be_in_table = valid_table[decoder_raw];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (build_table == 1'b0) begin
|
||||
if (decoder_notintable == decoder_should_be_in_table) begin
|
||||
$display("%b.%b, %d", decoder_raw[9:6], decoder_raw[5:0],
|
||||
decoder_should_be_in_table);
|
||||
failed <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,9 @@
|
||||
#!/bin/bash
|
||||
|
||||
SOURCE="soft_pcs_loopback_tb.v"
|
||||
SOURCE+=" ../jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v ../jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v"
|
||||
SOURCE+=" ../jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v ../jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v"
|
||||
SOURCE+=" ../jesd204_soft_pcs_rx/jesd204_pattern_align.v"
|
||||
|
||||
cd `dirname $0`
|
||||
source run_tb.sh
|
||||
@@ -0,0 +1,209 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A pcsTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module soft_pcs_loopback_tb;
|
||||
parameter VCD_FILE = "soft_pcs_loopback_tb.vcd";
|
||||
parameter DATA_PATH_WIDTH = 4;
|
||||
parameter LANE_INVERT = 0;
|
||||
|
||||
`include "tb_base.v"
|
||||
|
||||
reg [7:0] tx_char = {3'd5,5'd28};
|
||||
reg tx_charisk = 1'b1;
|
||||
reg [8*DATA_PATH_WIDTH-1:0] tx_char_pcs = 'h00;
|
||||
reg [DATA_PATH_WIDTH-1:0] tx_charisk_pcs = 'h00;
|
||||
|
||||
wire [7:0] rx_char;
|
||||
wire rx_charisk;
|
||||
wire rx_notintable;
|
||||
wire rx_disperr;
|
||||
wire [8*DATA_PATH_WIDTH-1:0] rx_char_pcs;
|
||||
wire [DATA_PATH_WIDTH-1:0] rx_charisk_pcs;
|
||||
wire [DATA_PATH_WIDTH-1:0] rx_notintable_pcs;
|
||||
wire [DATA_PATH_WIDTH-1:0] rx_disperr_pcs;
|
||||
reg rx_pattern_align_en = 1'b1;
|
||||
|
||||
wire [10*DATA_PATH_WIDTH-1:0] data_aligned;
|
||||
wire [10*DATA_PATH_WIDTH+9:0] data_aligned_full;
|
||||
reg [8:0] data_aligned_d1 = 'h00;
|
||||
reg [10*DATA_PATH_WIDTH-1:0] data_unaligned = 'h00;
|
||||
reg [3:0] bitshift = 'h00;
|
||||
|
||||
integer clk_div = 0;
|
||||
wire pcs_clk = clk_div < DATA_PATH_WIDTH / 2 ? 1'b1 : 1'b0;
|
||||
reg pcs_reset = 1'b1;
|
||||
|
||||
always @(posedge pcs_clk) begin
|
||||
pcs_reset <= 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (clk_div == DATA_PATH_WIDTH - 1) begin
|
||||
clk_div <= 0;
|
||||
end else begin
|
||||
clk_div <= clk_div + 1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pcs_clk) begin
|
||||
data_aligned_d1 <= data_aligned[DATA_PATH_WIDTH*10-1:DATA_PATH_WIDTH*10-9];
|
||||
end
|
||||
|
||||
assign data_aligned_full = {data_aligned,data_aligned_d1};
|
||||
|
||||
always @(*) begin
|
||||
data_unaligned <= data_aligned_full[bitshift+:DATA_PATH_WIDTH*10];
|
||||
end
|
||||
|
||||
jesd204_soft_pcs_tx #(
|
||||
.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
|
||||
.INVERT_OUTPUTS(LANE_INVERT)
|
||||
) i_soft_pcs_tx (
|
||||
.clk(pcs_clk),
|
||||
.reset(pcs_reset),
|
||||
|
||||
.char(tx_char_pcs),
|
||||
.charisk(tx_charisk_pcs),
|
||||
|
||||
.data(data_aligned)
|
||||
);
|
||||
|
||||
jesd204_soft_pcs_rx #(
|
||||
.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
|
||||
.INVERT_INPUTS(LANE_INVERT)
|
||||
) i_soft_pcs_rx (
|
||||
.clk(pcs_clk),
|
||||
.reset(pcs_reset),
|
||||
|
||||
.patternalign_en(rx_pattern_align_en),
|
||||
.data(data_unaligned),
|
||||
|
||||
.char(rx_char_pcs),
|
||||
.charisk(rx_charisk_pcs),
|
||||
.notintable(rx_notintable_pcs),
|
||||
.disperr(rx_disperr_pcs)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
tx_char_pcs <= {tx_char,tx_char_pcs[DATA_PATH_WIDTH*8-1:8]};
|
||||
tx_charisk_pcs <= {tx_charisk,tx_charisk_pcs[DATA_PATH_WIDTH-1:1]};
|
||||
end
|
||||
|
||||
integer rx_mux_select = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rx_mux_select == DATA_PATH_WIDTH - 1) begin
|
||||
rx_mux_select <= 0;
|
||||
end else begin
|
||||
rx_mux_select <= rx_mux_select + 1;
|
||||
end
|
||||
end
|
||||
|
||||
assign rx_charisk = rx_charisk_pcs[rx_mux_select];
|
||||
assign rx_notintable = rx_notintable_pcs[rx_mux_select];
|
||||
assign rx_disperr = rx_disperr_pcs[rx_mux_select];
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
for (i = 0; i < 8; i = i + 1) begin
|
||||
assign rx_char[i] = rx_char_pcs[rx_mux_select*8+i];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
integer counter = 0;
|
||||
|
||||
localparam STATE_SEND_ALIGN = 0;
|
||||
localparam STATE_SEND_DATA = 1;
|
||||
reg state = STATE_SEND_ALIGN;
|
||||
reg [7:0] rx_compare = 'h00;
|
||||
|
||||
always @(posedge clk) begin
|
||||
case(state)
|
||||
STATE_SEND_ALIGN: begin
|
||||
tx_char <= {3'd5,5'd28};
|
||||
tx_charisk <= 1'b1;
|
||||
|
||||
// Worst case alignment time is 40 * DATA_PATH_WIDTH
|
||||
if (counter < DATA_PATH_WIDTH * 60) begin
|
||||
rx_pattern_align_en <= 1'b1;
|
||||
end else begin
|
||||
rx_pattern_align_en <= 1'b0;
|
||||
end
|
||||
|
||||
if (counter == DATA_PATH_WIDTH * 64) begin
|
||||
state <= STATE_SEND_DATA;
|
||||
counter <= 0;
|
||||
rx_compare <= 'h00;
|
||||
end else begin
|
||||
counter <= counter + 1'b1;
|
||||
end
|
||||
end
|
||||
STATE_SEND_DATA: begin
|
||||
if (tx_charisk == 1'b1) begin
|
||||
tx_char <= 'h00;
|
||||
end else begin
|
||||
tx_char <= tx_char + 1'b1;
|
||||
end
|
||||
tx_charisk <= 1'b0;
|
||||
|
||||
if (rx_charisk == 1'b0) begin
|
||||
rx_compare <= rx_compare + 1'b1;
|
||||
if (rx_char != rx_compare || rx_disperr == 1'b1 || rx_notintable == 1'b1) begin
|
||||
failed <= 1'b1;
|
||||
end
|
||||
end else begin
|
||||
rx_compare <= 'h00;
|
||||
end
|
||||
|
||||
if (rx_char == 'd255) begin
|
||||
state <= STATE_SEND_ALIGN;
|
||||
bitshift <= {$random} % 10;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,7 @@
|
||||
#!/bin/bash
|
||||
|
||||
SOURCE="soft_pcs_pattern_align_tb.v"
|
||||
SOURCE+=" ../jesd204_soft_pcs_rx/jesd204_pattern_align.v"
|
||||
|
||||
cd `dirname $0`
|
||||
source run_tb.sh
|
||||
@@ -0,0 +1,117 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module soft_pcs_pattern_align_tb;
|
||||
parameter VCD_FILE = "soft_pcs_pattern_align_tb.vcd";
|
||||
|
||||
localparam [9:0] PATTERN_P = 10'b1010000011;
|
||||
localparam [9:0] PATTERN_N = 10'b0101111100;
|
||||
|
||||
`define TIMEOUT 1000000
|
||||
`include "tb_base.v"
|
||||
|
||||
integer counter = 0;
|
||||
|
||||
reg [3:0] bitshift = 4'd0;
|
||||
reg [9:0] comma_unaligned;
|
||||
reg comma_sync = 1'b0;
|
||||
wire [9:0] comma_aligned;
|
||||
reg [9:0] comma = PATTERN_P;
|
||||
|
||||
wire comma_match = comma == comma_aligned;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (counter == 63) begin
|
||||
if (comma_sync != 1'b1) begin
|
||||
failed <= 1'b1;
|
||||
end
|
||||
|
||||
comma_sync <= 1'b0;
|
||||
counter <= 0;
|
||||
bitshift <= {$random} % 10;
|
||||
comma <= {$random} % 2 ? PATTERN_P : PATTERN_N;
|
||||
end else begin
|
||||
counter <= counter + 1'b1;
|
||||
|
||||
// Takes two clock cycles for the new value to propagate
|
||||
if (counter > 1) begin
|
||||
// Shouldn't loose sync after it gained it
|
||||
if (comma_match == 1'b1) begin
|
||||
comma_sync <= 1'b1;
|
||||
end else if (comma_sync == 1'b1) begin
|
||||
failed <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
case (bitshift)
|
||||
4'd0: comma_unaligned <= comma[9:0];
|
||||
4'd1: comma_unaligned <= {comma[0],comma[9:1]};
|
||||
4'd2: comma_unaligned <= {comma[1:0],comma[9:2]};
|
||||
4'd3: comma_unaligned <= {comma[2:0],comma[9:3]};
|
||||
4'd4: comma_unaligned <= {comma[3:0],comma[9:4]};
|
||||
4'd5: comma_unaligned <= {comma[4:0],comma[9:5]};
|
||||
4'd6: comma_unaligned <= {comma[5:0],comma[9:6]};
|
||||
4'd7: comma_unaligned <= {comma[6:0],comma[9:7]};
|
||||
4'd8: comma_unaligned <= {comma[7:0],comma[9:8]};
|
||||
default: comma_unaligned <= {comma[8:0],comma[9]};
|
||||
endcase
|
||||
end
|
||||
|
||||
jesd204_pattern_align #(
|
||||
.DATA_PATH_WIDTH(1)
|
||||
) i_pa (
|
||||
.clk(clk),
|
||||
.reset(1'b0),
|
||||
.patternalign_en(1'b1),
|
||||
|
||||
.in_data(comma_unaligned),
|
||||
.out_data(comma_aligned)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,93 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
reg clk = 1'b0;
|
||||
reg [3:0] reset_shift = 4'b1111;
|
||||
reg trigger_reset = 1'b0;
|
||||
wire reset;
|
||||
|
||||
reg failed = 1'b0;
|
||||
|
||||
reg sysref = 1'b0;
|
||||
|
||||
initial
|
||||
begin
|
||||
$dumpfile (VCD_FILE);
|
||||
$dumpvars;
|
||||
`ifdef TIMEOUT
|
||||
#`TIMEOUT
|
||||
`else
|
||||
#100000
|
||||
`endif
|
||||
if (failed == 1'b0)
|
||||
$display("SUCCESS");
|
||||
else
|
||||
$display("FAILED");
|
||||
$finish;
|
||||
end
|
||||
|
||||
initial forever #10 clk <= ~clk;
|
||||
always @(posedge clk) begin
|
||||
if (trigger_reset == 1'b1) begin
|
||||
reset_shift <= 3'b111;
|
||||
end else begin
|
||||
reset_shift <= {reset_shift[2:0],1'b0};
|
||||
end
|
||||
end
|
||||
|
||||
assign reset = reset_shift[3];
|
||||
|
||||
|
||||
initial begin
|
||||
#1000;
|
||||
@(posedge clk) sysref <= 1'b1;
|
||||
@(posedge clk) sysref <= 1'b0;
|
||||
end
|
||||
|
||||
task do_trigger_reset;
|
||||
begin
|
||||
@(posedge clk) trigger_reset <= 1'b1;
|
||||
@(posedge clk) trigger_reset <= 1'b0;
|
||||
end
|
||||
endtask
|
||||
@@ -0,0 +1,11 @@
|
||||
#!/bin/bash
|
||||
|
||||
SOURCE="tx_64b_tb.v"
|
||||
SOURCE+=" ../jesd204_common/jesd204_lmfc.v ../jesd204_common/jesd204_scrambler_64b.v ../jesd204_common/jesd204_crc12.v"
|
||||
SOURCE+=" ../jesd204_tx/jesd204_tx.v ../jesd204_tx/jesd204_tx_lane_64b.v ../jesd204_tx/jesd204_tx_header.v"
|
||||
SOURCE+=" ../jesd204_tx_static_config/jesd204_tx_static_config.v ../jesd204_tx_static_config/jesd204_ilas_cfg_static.v"
|
||||
SOURCE+=" ../../util_cdc/sync_bits.v"
|
||||
SOURCE+=" ../jesd204_common/pipeline_stage.v"
|
||||
|
||||
cd `dirname $0`
|
||||
source run_tb.sh
|
||||
@@ -0,0 +1,176 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module tx_64b_tb;
|
||||
parameter VCD_FILE = "tx_tb.vcd";
|
||||
parameter NUM_LANES = 1;
|
||||
parameter NUM_LINKS = 1;
|
||||
parameter OCTETS_PER_FRAME = 4;
|
||||
parameter FRAMES_PER_MULTIFRAME = 32;
|
||||
|
||||
`include "tb_base.v"
|
||||
|
||||
|
||||
reg [NUM_LINKS-1:0] sync = {NUM_LINKS{1'b1}};
|
||||
reg [31:0] counter = 'h00;
|
||||
reg [63:0] tx_data = 'h00000000;
|
||||
|
||||
wire tx_ready;
|
||||
wire tx_valid = 1'b1;
|
||||
wire [NUM_LANES-1:0] cfg_lanes_disable;
|
||||
wire [NUM_LINKS-1:0] cfg_links_disable;
|
||||
wire [7:0] cfg_beats_per_multiframe;
|
||||
wire [7:0] cfg_octets_per_frame;
|
||||
wire [7:0] cfg_lmfc_offset;
|
||||
wire cfg_sysref_oneshot;
|
||||
wire cfg_sysref_disable;
|
||||
wire cfg_continuous_cgs;
|
||||
wire cfg_continuous_ilas;
|
||||
wire cfg_skip_ilas;
|
||||
wire [7:0] cfg_mframes_per_ilas;
|
||||
wire cfg_disable_char_replacement;
|
||||
wire cfg_disable_scrambler;
|
||||
wire tx_ilas_config_rd;
|
||||
wire [1:0] tx_ilas_config_addr;
|
||||
wire [32*NUM_LANES-1:0] tx_ilas_config_data;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
tx_data <= 'h00000000;
|
||||
end else if (tx_ready == 1'b1) begin
|
||||
tx_data <= tx_data + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
/* Generate independent SYNCs
|
||||
*
|
||||
* Each SYNC will be asserted/deasserted at different clock edges.
|
||||
* The assertion/deassertion order: first SYNC[0], ..., last SYNC[NUM_LINKS-1]
|
||||
*/
|
||||
always @(posedge clk) begin
|
||||
counter <= counter + 1'b1;
|
||||
end
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i=1; i<=NUM_LINKS; i=i+1) begin: SYNC_GENERATOR
|
||||
always @(posedge clk) begin
|
||||
if (counter >= (32'h100 | (i << 4)) && counter <= (32'h300 | (i << 4))) begin
|
||||
sync[i-1] <= 1'b0;
|
||||
end else begin
|
||||
sync[i-1] <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// DUT with static configuration
|
||||
|
||||
jesd204_tx_static_config #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.NUM_LINKS(NUM_LINKS),
|
||||
.OCTETS_PER_FRAME(OCTETS_PER_FRAME),
|
||||
.FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME)
|
||||
) i_cfg (
|
||||
.clk(clk),
|
||||
|
||||
.cfg_lanes_disable(cfg_lanes_disable),
|
||||
.cfg_links_disable(cfg_links_disable),
|
||||
.cfg_beats_per_multiframe(cfg_beats_per_multiframe),
|
||||
.cfg_octets_per_frame(cfg_octets_per_frame),
|
||||
.cfg_lmfc_offset(cfg_lmfc_offset),
|
||||
.cfg_continuous_cgs(cfg_continuous_cgs),
|
||||
.cfg_continuous_ilas(cfg_continuous_ilas),
|
||||
.cfg_skip_ilas(cfg_skip_ilas),
|
||||
.cfg_mframes_per_ilas(cfg_mframes_per_ilas),
|
||||
.cfg_disable_char_replacement(cfg_disable_char_replacement),
|
||||
.cfg_disable_scrambler(cfg_disable_scrambler),
|
||||
.cfg_sysref_oneshot(cfg_sysref_oneshot),
|
||||
.cfg_sysref_disable(cfg_sysref_disable),
|
||||
|
||||
.ilas_config_rd(tx_ilas_config_rd),
|
||||
.ilas_config_addr(tx_ilas_config_addr),
|
||||
.ilas_config_data(tx_ilas_config_data)
|
||||
);
|
||||
|
||||
jesd204_tx #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.NUM_LINKS(NUM_LINKS),
|
||||
.LINK_MODE(2)
|
||||
) i_tx (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
|
||||
.cfg_lanes_disable(cfg_lanes_disable),
|
||||
.cfg_links_disable(cfg_links_disable),
|
||||
.cfg_beats_per_multiframe(cfg_beats_per_multiframe),
|
||||
.cfg_octets_per_frame(cfg_octets_per_frame),
|
||||
.cfg_lmfc_offset(cfg_lmfc_offset),
|
||||
.cfg_continuous_cgs(cfg_continuous_cgs),
|
||||
.cfg_continuous_ilas(cfg_continuous_ilas),
|
||||
.cfg_skip_ilas(cfg_skip_ilas),
|
||||
.cfg_mframes_per_ilas(cfg_mframes_per_ilas),
|
||||
.cfg_disable_char_replacement(cfg_disable_char_replacement),
|
||||
.cfg_disable_scrambler(cfg_disable_scrambler),
|
||||
.cfg_sysref_oneshot(cfg_sysref_oneshot),
|
||||
.cfg_sysref_disable(cfg_sysref_disable),
|
||||
|
||||
.ilas_config_rd(tx_ilas_config_rd),
|
||||
.ilas_config_addr(tx_ilas_config_addr),
|
||||
.ilas_config_data(tx_ilas_config_data),
|
||||
|
||||
.ctrl_manual_sync_request (1'b0),
|
||||
|
||||
.tx_ready(tx_ready),
|
||||
.tx_valid(tx_valid),
|
||||
.tx_data({NUM_LANES{tx_data}}),
|
||||
|
||||
.sync(sync),
|
||||
.sysref(sysref)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,8 @@
|
||||
#!/bin/bash
|
||||
|
||||
SOURCE="tx_ctrl_phase_tb.v"
|
||||
SOURCE+=" ../jesd204_tx/jesd204_tx_ctrl.v"
|
||||
SOURCE+=" ../../util_cdc/sync_bits.v"
|
||||
|
||||
cd `dirname $0`
|
||||
source run_tb.sh
|
||||
@@ -0,0 +1,212 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
/*
|
||||
* Regardless of the phase relationship between LMFC and sync the output of the
|
||||
* ctrl core should be the same as long as the sync signal is in the same lmfc
|
||||
* cycle.
|
||||
*/
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module tx_ctrl_phase_tb;
|
||||
parameter VCD_FILE = "tx_ctrl_phase.vcd";
|
||||
parameter NUM_LANES = 1;
|
||||
parameter BEATS_PER_LMFC = 20;
|
||||
|
||||
`include "tb_base.v"
|
||||
|
||||
reg lmfc_edge = 1'b0;
|
||||
reg a_sync = 1'b0;
|
||||
reg b_sync = 1'b0;
|
||||
|
||||
wire [31:0] a_ilas_data;
|
||||
wire [3:0] a_ilas_charisk;
|
||||
wire [1:0] a_ilas_config_addr;
|
||||
wire a_ilas_config_rd;
|
||||
wire a_tx_ready;
|
||||
wire a_lane_cgs_enable;
|
||||
|
||||
wire [31:0] b_ilas_data;
|
||||
wire [3:0] b_ilas_charisk;
|
||||
wire [1:0] b_ilas_config_addr;
|
||||
wire b_ilas_config_rd;
|
||||
wire b_tx_ready;
|
||||
wire b_lane_cgs_enable;
|
||||
|
||||
reg reset2 = 1'b1;
|
||||
|
||||
integer reset_counter = 0;
|
||||
integer beat_counter = 0;
|
||||
integer lmfc_counter = 0;
|
||||
integer b_offset = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset2 == 1'b1) begin
|
||||
if (reset_counter == 7) begin
|
||||
reset2 <= 1'b0;
|
||||
reset_counter <= 0;
|
||||
end else begin
|
||||
reset_counter <= reset_counter + 1;
|
||||
end
|
||||
end
|
||||
|
||||
if (reset2 == 1'b1) begin
|
||||
beat_counter <= 0;
|
||||
a_sync <= 1'b0;
|
||||
b_sync <= 1'b0;
|
||||
end else begin
|
||||
beat_counter <= beat_counter + 1'b1;
|
||||
if (beat_counter == BEATS_PER_LMFC*2) begin
|
||||
a_sync <= 1'b1;
|
||||
end
|
||||
|
||||
if (beat_counter == BEATS_PER_LMFC*2 + b_offset) begin
|
||||
b_sync <= 1'b1;
|
||||
end
|
||||
|
||||
if (beat_counter == BEATS_PER_LMFC*9) begin
|
||||
b_offset <= b_offset + 1;
|
||||
reset2 <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
if (reset2 == 1'b1) begin
|
||||
lmfc_counter <= BEATS_PER_LMFC-3;
|
||||
end else begin
|
||||
lmfc_counter <= lmfc_counter + 1;
|
||||
if (lmfc_counter == BEATS_PER_LMFC-1) begin
|
||||
lmfc_counter <= 0;
|
||||
lmfc_edge <= 1'b1;
|
||||
end else begin
|
||||
lmfc_edge <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
jesd204_tx_ctrl i_tx_ctrl_a (
|
||||
.clk(clk),
|
||||
.reset(reset2),
|
||||
|
||||
.sync(a_sync),
|
||||
.lmfc_edge(lmfc_edge),
|
||||
|
||||
.lane_cgs_enable(a_lane_cgs_enable),
|
||||
|
||||
.tx_ready(a_tx_ready),
|
||||
|
||||
.ilas_data(a_ilas_data),
|
||||
.ilas_charisk(a_ilas_charisk),
|
||||
|
||||
.ilas_config_addr(a_ilas_config_addr),
|
||||
.ilas_config_rd(a_ilas_config_rd),
|
||||
.ilas_config_data('h00),
|
||||
|
||||
.ctrl_manual_sync_request(1'b0),
|
||||
|
||||
.cfg_continuous_cgs(1'b0),
|
||||
.cfg_continuous_ilas(1'b0),
|
||||
.cfg_skip_ilas(1'b0),
|
||||
.cfg_mframes_per_ilas(8'h3)
|
||||
);
|
||||
|
||||
jesd204_tx_ctrl i_tx_ctrl_b (
|
||||
.clk(clk),
|
||||
.reset(reset2),
|
||||
|
||||
.sync(b_sync),
|
||||
.lmfc_edge(lmfc_edge),
|
||||
|
||||
.lane_cgs_enable(b_lane_cgs_enable),
|
||||
|
||||
.tx_ready(b_tx_ready),
|
||||
|
||||
.ilas_data(b_ilas_data),
|
||||
.ilas_charisk(b_ilas_charisk),
|
||||
|
||||
.ilas_config_addr(b_ilas_config_addr),
|
||||
.ilas_config_rd(b_ilas_config_rd),
|
||||
.ilas_config_data('h00),
|
||||
|
||||
.ctrl_manual_sync_request(1'b0),
|
||||
|
||||
.cfg_continuous_cgs(1'b0),
|
||||
.cfg_continuous_ilas(1'b0),
|
||||
.cfg_skip_ilas(1'b0),
|
||||
.cfg_mframes_per_ilas(8'h3)
|
||||
);
|
||||
|
||||
reg status = 1'b1;
|
||||
|
||||
always @(*) begin
|
||||
if (reset2 == 1'b1) begin
|
||||
status <= 1'b1;
|
||||
end else if (a_ilas_data != b_ilas_data ||
|
||||
a_ilas_charisk != b_ilas_charisk ||
|
||||
a_ilas_config_addr != b_ilas_config_addr ||
|
||||
a_ilas_config_rd != b_ilas_config_rd ||
|
||||
a_lane_cgs_enable != b_lane_cgs_enable ||
|
||||
a_tx_ready != b_tx_ready) begin
|
||||
status <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
reg message_shown = 1'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (status == 1'b0 && message_shown == 1'b0 && b_offset < BEATS_PER_LMFC) begin
|
||||
$display("FAILED at offset %0d", b_offset);
|
||||
message_shown <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (b_offset == BEATS_PER_LMFC+1) begin
|
||||
if (message_shown == 1'b0)
|
||||
$display("SUCCESS");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,10 @@
|
||||
#!/bin/bash
|
||||
|
||||
SOURCE="tx_tb.v"
|
||||
SOURCE+=" ../jesd204_common/jesd204_lmfc.v ../jesd204_common/jesd204_scrambler.v ../jesd204_common/jesd204_eof_generator.v"
|
||||
SOURCE+=" ../jesd204_tx/jesd204_tx.v ../jesd204_tx/jesd204_tx_ctrl.v ../jesd204_tx/jesd204_tx_lane.v"
|
||||
SOURCE+=" ../jesd204_tx_static_config/jesd204_tx_static_config.v ../jesd204_tx_static_config/jesd204_ilas_cfg_static.v"
|
||||
SOURCE+=" ../../util_cdc/sync_bits.v"
|
||||
|
||||
cd `dirname $0`
|
||||
source run_tb.sh
|
||||
@@ -0,0 +1,175 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module tx_tb;
|
||||
parameter VCD_FILE = "tx_tb.vcd";
|
||||
parameter NUM_LANES = 4;
|
||||
parameter NUM_LINKS = 2;
|
||||
parameter OCTETS_PER_FRAME = 4;
|
||||
parameter FRAMES_PER_MULTIFRAME = 32;
|
||||
|
||||
`include "tb_base.v"
|
||||
|
||||
|
||||
reg [NUM_LINKS-1:0] sync = {NUM_LINKS{1'b1}};
|
||||
reg [31:0] counter = 'h00;
|
||||
reg [31:0] tx_data = 'h00000000;
|
||||
|
||||
wire tx_ready;
|
||||
wire tx_valid = 1'b1;
|
||||
wire [NUM_LANES-1:0] cfg_lanes_disable;
|
||||
wire [NUM_LINKS-1:0] cfg_links_disable;
|
||||
wire [7:0] cfg_beats_per_multiframe;
|
||||
wire [7:0] cfg_octets_per_frame;
|
||||
wire [7:0] cfg_lmfc_offset;
|
||||
wire cfg_sysref_oneshot;
|
||||
wire cfg_sysref_disable;
|
||||
wire cfg_continuous_cgs;
|
||||
wire cfg_continuous_ilas;
|
||||
wire cfg_skip_ilas;
|
||||
wire [7:0] cfg_mframes_per_ilas;
|
||||
wire cfg_disable_char_replacement;
|
||||
wire cfg_disable_scrambler;
|
||||
wire tx_ilas_config_rd;
|
||||
wire [1:0] tx_ilas_config_addr;
|
||||
wire [32*NUM_LANES-1:0] tx_ilas_config_data;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
tx_data <= 'h00000000;
|
||||
end else if (tx_ready == 1'b1) begin
|
||||
tx_data <= tx_data + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
/* Generate independent SYNCs
|
||||
*
|
||||
* Each SYNC will be asserted/deasserted at different clock edges.
|
||||
* The assertion/deassertion order: first SYNC[0], ..., last SYNC[NUM_LINKS-1]
|
||||
*/
|
||||
always @(posedge clk) begin
|
||||
counter <= counter + 1'b1;
|
||||
end
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i=1; i<=NUM_LINKS; i=i+1) begin: SYNC_GENERATOR
|
||||
always @(posedge clk) begin
|
||||
if (counter >= (32'h100 | (i << 4)) && counter <= (32'h300 | (i << 4))) begin
|
||||
sync[i-1] <= 1'b0;
|
||||
end else begin
|
||||
sync[i-1] <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// DUT with static configuration
|
||||
|
||||
jesd204_tx_static_config #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.NUM_LINKS(NUM_LINKS),
|
||||
.OCTETS_PER_FRAME(OCTETS_PER_FRAME),
|
||||
.FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME)
|
||||
) i_cfg (
|
||||
.clk(clk),
|
||||
|
||||
.cfg_lanes_disable(cfg_lanes_disable),
|
||||
.cfg_links_disable(cfg_links_disable),
|
||||
.cfg_beats_per_multiframe(cfg_beats_per_multiframe),
|
||||
.cfg_octets_per_frame(cfg_octets_per_frame),
|
||||
.cfg_lmfc_offset(cfg_lmfc_offset),
|
||||
.cfg_continuous_cgs(cfg_continuous_cgs),
|
||||
.cfg_continuous_ilas(cfg_continuous_ilas),
|
||||
.cfg_skip_ilas(cfg_skip_ilas),
|
||||
.cfg_mframes_per_ilas(cfg_mframes_per_ilas),
|
||||
.cfg_disable_char_replacement(cfg_disable_char_replacement),
|
||||
.cfg_disable_scrambler(cfg_disable_scrambler),
|
||||
.cfg_sysref_oneshot(cfg_sysref_oneshot),
|
||||
.cfg_sysref_disable(cfg_sysref_disable),
|
||||
|
||||
.ilas_config_rd(tx_ilas_config_rd),
|
||||
.ilas_config_addr(tx_ilas_config_addr),
|
||||
.ilas_config_data(tx_ilas_config_data)
|
||||
);
|
||||
|
||||
jesd204_tx #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.NUM_LINKS(NUM_LINKS)
|
||||
) i_tx (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
|
||||
.cfg_lanes_disable(cfg_lanes_disable),
|
||||
.cfg_links_disable(cfg_links_disable),
|
||||
.cfg_beats_per_multiframe(cfg_beats_per_multiframe),
|
||||
.cfg_octets_per_frame(cfg_octets_per_frame),
|
||||
.cfg_lmfc_offset(cfg_lmfc_offset),
|
||||
.cfg_continuous_cgs(cfg_continuous_cgs),
|
||||
.cfg_continuous_ilas(cfg_continuous_ilas),
|
||||
.cfg_skip_ilas(cfg_skip_ilas),
|
||||
.cfg_mframes_per_ilas(cfg_mframes_per_ilas),
|
||||
.cfg_disable_char_replacement(cfg_disable_char_replacement),
|
||||
.cfg_disable_scrambler(cfg_disable_scrambler),
|
||||
.cfg_sysref_oneshot(cfg_sysref_oneshot),
|
||||
.cfg_sysref_disable(cfg_sysref_disable),
|
||||
|
||||
.ilas_config_rd(tx_ilas_config_rd),
|
||||
.ilas_config_addr(tx_ilas_config_addr),
|
||||
.ilas_config_data(tx_ilas_config_data),
|
||||
|
||||
.ctrl_manual_sync_request (1'b0),
|
||||
|
||||
.tx_ready(tx_ready),
|
||||
.tx_valid(tx_valid),
|
||||
.tx_data({NUM_LANES{tx_data}}),
|
||||
|
||||
.sync(sync),
|
||||
.sysref(sysref)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user