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//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A pcsTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact [email protected] for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module soft_pcs_loopback_tb;
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parameter VCD_FILE = "soft_pcs_loopback_tb.vcd";
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parameter DATA_PATH_WIDTH = 4;
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parameter LANE_INVERT = 0;
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`include "tb_base.v"
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reg [7:0] tx_char = {3'd5,5'd28};
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reg tx_charisk = 1'b1;
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reg [8*DATA_PATH_WIDTH-1:0] tx_char_pcs = 'h00;
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reg [DATA_PATH_WIDTH-1:0] tx_charisk_pcs = 'h00;
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wire [7:0] rx_char;
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wire rx_charisk;
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wire rx_notintable;
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wire rx_disperr;
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wire [8*DATA_PATH_WIDTH-1:0] rx_char_pcs;
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wire [DATA_PATH_WIDTH-1:0] rx_charisk_pcs;
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wire [DATA_PATH_WIDTH-1:0] rx_notintable_pcs;
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wire [DATA_PATH_WIDTH-1:0] rx_disperr_pcs;
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reg rx_pattern_align_en = 1'b1;
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wire [10*DATA_PATH_WIDTH-1:0] data_aligned;
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wire [10*DATA_PATH_WIDTH+9:0] data_aligned_full;
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reg [8:0] data_aligned_d1 = 'h00;
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reg [10*DATA_PATH_WIDTH-1:0] data_unaligned = 'h00;
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reg [3:0] bitshift = 'h00;
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integer clk_div = 0;
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wire pcs_clk = clk_div < DATA_PATH_WIDTH / 2 ? 1'b1 : 1'b0;
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reg pcs_reset = 1'b1;
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always @(posedge pcs_clk) begin
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pcs_reset <= 1'b0;
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end
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always @(posedge clk) begin
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if (clk_div == DATA_PATH_WIDTH - 1) begin
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clk_div <= 0;
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end else begin
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clk_div <= clk_div + 1;
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end
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end
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always @(posedge pcs_clk) begin
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data_aligned_d1 <= data_aligned[DATA_PATH_WIDTH*10-1:DATA_PATH_WIDTH*10-9];
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end
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assign data_aligned_full = {data_aligned,data_aligned_d1};
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always @(*) begin
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data_unaligned <= data_aligned_full[bitshift+:DATA_PATH_WIDTH*10];
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end
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jesd204_soft_pcs_tx #(
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.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
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.INVERT_OUTPUTS(LANE_INVERT)
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) i_soft_pcs_tx (
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.clk(pcs_clk),
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.reset(pcs_reset),
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.char(tx_char_pcs),
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.charisk(tx_charisk_pcs),
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.data(data_aligned)
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);
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jesd204_soft_pcs_rx #(
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.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
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.INVERT_INPUTS(LANE_INVERT)
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) i_soft_pcs_rx (
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.clk(pcs_clk),
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.reset(pcs_reset),
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.patternalign_en(rx_pattern_align_en),
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.data(data_unaligned),
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.char(rx_char_pcs),
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.charisk(rx_charisk_pcs),
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.notintable(rx_notintable_pcs),
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.disperr(rx_disperr_pcs)
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);
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always @(posedge clk) begin
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tx_char_pcs <= {tx_char,tx_char_pcs[DATA_PATH_WIDTH*8-1:8]};
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tx_charisk_pcs <= {tx_charisk,tx_charisk_pcs[DATA_PATH_WIDTH-1:1]};
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end
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integer rx_mux_select = 0;
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always @(posedge clk) begin
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if (rx_mux_select == DATA_PATH_WIDTH - 1) begin
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rx_mux_select <= 0;
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end else begin
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rx_mux_select <= rx_mux_select + 1;
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end
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end
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assign rx_charisk = rx_charisk_pcs[rx_mux_select];
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assign rx_notintable = rx_notintable_pcs[rx_mux_select];
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assign rx_disperr = rx_disperr_pcs[rx_mux_select];
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generate
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genvar i;
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for (i = 0; i < 8; i = i + 1) begin
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assign rx_char[i] = rx_char_pcs[rx_mux_select*8+i];
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end
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endgenerate
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integer counter = 0;
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localparam STATE_SEND_ALIGN = 0;
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localparam STATE_SEND_DATA = 1;
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reg state = STATE_SEND_ALIGN;
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reg [7:0] rx_compare = 'h00;
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always @(posedge clk) begin
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case(state)
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STATE_SEND_ALIGN: begin
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tx_char <= {3'd5,5'd28};
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tx_charisk <= 1'b1;
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// Worst case alignment time is 40 * DATA_PATH_WIDTH
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if (counter < DATA_PATH_WIDTH * 60) begin
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rx_pattern_align_en <= 1'b1;
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end else begin
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rx_pattern_align_en <= 1'b0;
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end
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if (counter == DATA_PATH_WIDTH * 64) begin
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state <= STATE_SEND_DATA;
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counter <= 0;
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rx_compare <= 'h00;
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end else begin
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counter <= counter + 1'b1;
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end
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end
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STATE_SEND_DATA: begin
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if (tx_charisk == 1'b1) begin
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tx_char <= 'h00;
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end else begin
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tx_char <= tx_char + 1'b1;
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end
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tx_charisk <= 1'b0;
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if (rx_charisk == 1'b0) begin
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rx_compare <= rx_compare + 1'b1;
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if (rx_char != rx_compare || rx_disperr == 1'b1 || rx_notintable == 1'b1) begin
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failed <= 1'b1;
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end
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end else begin
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rx_compare <= 'h00;
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end
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if (rx_char == 'd255) begin
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state <= STATE_SEND_ALIGN;
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bitshift <= {$random} % 10;
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end
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end
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endcase
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end
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endmodule
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