Archived
initial commit
This commit is contained in:
@@ -0,0 +1,19 @@
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||||
####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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||||
## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := spi_engine_execution
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GENERIC_DEPS += spi_engine_execution.v
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XILINX_DEPS += spi_engine_execution_ip.tcl
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_master.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_master_rtl.xml
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INTEL_DEPS += spi_engine_execution_hw.tcl
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include ../../scripts/library.mk
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@@ -0,0 +1,802 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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||||
<spirit:vendor>analog.com</spirit:vendor>
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||||
<spirit:library>user</spirit:library>
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||||
<spirit:name>spi_engine_execution</spirit:name>
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||||
<spirit:version>1.0</spirit:version>
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||||
<spirit:busInterfaces>
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||||
<spirit:busInterface>
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||||
<spirit:name>ctrl</spirit:name>
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||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl_rtl" spirit:version="1.0"/>
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||||
<spirit:slave/>
|
||||
<spirit:portMaps>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>CMD_READY</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>cmd_ready</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>CMD_VALID</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>cmd_valid</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>CMD_DATA</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>cmd</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>SDO_READY</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>sdo_data_ready</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>SDO_VALID</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>sdo_data_valid</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>SDO_DATA</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>sdo_data</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>SDI_READY</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>sdi_data_ready</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
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||||
<spirit:name>SDI_VALID</spirit:name>
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||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data_valid</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>SDI_DATA</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>sdi_data</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>SYNC_READY</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>sync_ready</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_VALID</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
|
||||
<spirit:name>sync_valid</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
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||||
<spirit:name>SYNC_DATA</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>sync</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
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||||
<spirit:busInterface>
|
||||
<spirit:name>ctrl_signal_clock</spirit:name>
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||||
<spirit:displayName>ctrl_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
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||||
<spirit:portMaps>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>CLK</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>clk</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
</spirit:portMaps>
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||||
<spirit:parameters>
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||||
<spirit:parameter>
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||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
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||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.ASSOCIATED_BUSIF">ctrl</spirit:value>
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||||
</spirit:parameter>
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||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
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||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.ASSOCIATED_RESET">resetn</spirit:value>
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||||
</spirit:parameter>
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||||
</spirit:parameters>
|
||||
</spirit:busInterface>
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||||
<spirit:busInterface>
|
||||
<spirit:name>ctrl_signal_reset</spirit:name>
|
||||
<spirit:displayName>ctrl_signal_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>resetn</spirit:name>
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||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
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||||
</spirit:parameters>
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||||
</spirit:busInterface>
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||||
<spirit:busInterface>
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||||
<spirit:name>spi</spirit:name>
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||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_master" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_master_rtl" spirit:version="1.0"/>
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||||
<spirit:master/>
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||||
<spirit:portMaps>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>SCLK</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>sclk</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>SDI</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>sdi</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>SDO</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>sdo</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
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||||
<spirit:name>SDO_T</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>sdo_t</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>THREE_WIRE</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>three_wire</spirit:name>
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||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
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||||
<spirit:name>CS</spirit:name>
|
||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
|
||||
<spirit:name>cs</spirit:name>
|
||||
</spirit:physicalPort>
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||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_signal_clock</spirit:name>
|
||||
<spirit:displayName>spi_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.ASSOCIATED_BUSIF">spi</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.ASSOCIATED_RESET">resetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_signal_reset</spirit:name>
|
||||
<spirit:displayName>spi_signal_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>spi_engine_execution</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>537cc789</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>spi_engine_execution</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>537cc789</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>49a5a305</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>active</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cmd_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cmd_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cmd</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) * spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH'))) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sync_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sync_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sync</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_t</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) - 1)">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cs</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CS')) - 1)">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>three_wire</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>NUM_OF_CS</spirit:name>
|
||||
<spirit:displayName>Num Of Cs</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_OF_CS">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DEFAULT_SPI_CFG</spirit:name>
|
||||
<spirit:displayName>Default Spi Cfg</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DEFAULT_SPI_CFG">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DEFAULT_CLK_DIV</spirit:name>
|
||||
<spirit:displayName>Default Clk Div</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DEFAULT_CLK_DIV">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Data Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_WIDTH">8</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>NUM_OF_SDI</spirit:name>
|
||||
<spirit:displayName>Num Of Sdi</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_OF_SDI">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SDO_DEFAULT</spirit:name>
|
||||
<spirit:displayName>Sdo Default</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SDO_DEFAULT" spirit:bitStringLength="1">"0"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SDI_DELAY</spirit:name>
|
||||
<spirit:displayName>Sdi Delay</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SDI_DELAY">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_b71134be</spirit:name>
|
||||
<spirit:enumeration>"0"</spirit:enumeration>
|
||||
<spirit:enumeration>"1"</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_dd9ee503</spirit:name>
|
||||
<spirit:enumeration>0</spirit:enumeration>
|
||||
<spirit:enumeration>1</spirit:enumeration>
|
||||
<spirit:enumeration>2</spirit:enumeration>
|
||||
<spirit:enumeration>3</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>spi_engine_execution.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_537cc789</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>spi_engine_execution.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/spi_engine_execution_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_4d31af11</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>spi_engine_execution_v1_0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_OF_CS</spirit:name>
|
||||
<spirit:displayName>Number of CSN lines</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OF_CS" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DEFAULT_SPI_CFG</spirit:name>
|
||||
<spirit:displayName>Default SPI mode</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEFAULT_SPI_CFG" spirit:choiceRef="choice_list_dd9ee503">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DEFAULT_CLK_DIV</spirit:name>
|
||||
<spirit:displayName>Default SCLK divider</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEFAULT_CLK_DIV" spirit:minimum="0" spirit:maximum="255" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Parallel data width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH" spirit:minimum="8" spirit:maximum="256" spirit:rangeType="long">8</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_OF_SDI</spirit:name>
|
||||
<spirit:displayName>Number of MISO</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OF_SDI" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SDO_DEFAULT</spirit:name>
|
||||
<spirit:displayName>MOSI default level</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.SDO_DEFAULT" spirit:choiceRef="choice_list_b71134be" spirit:bitStringLength="1">"0"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SDI_DELAY</spirit:name>
|
||||
<spirit:displayName>Delay MISO latching</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.SDI_DELAY">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">spi_engine_execution_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">akintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus58g</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">azynquplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qkintexu</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qkintexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qrkintexu</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qvirtexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qzynquplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qzynquplusRFSOC</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynquplusRFSOC</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>spi_engine_execution_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
|
||||
<xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2021-12-09T07:07:50Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2019.1.3</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5778d7eb"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="5681b5a9"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="8b510ac0"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="6b1dd38c"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c42617463684d6f6465:1
|
||||
eof:
|
||||
+6
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
|
||||
@@ -0,0 +1,456 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module spi_engine_execution #(
|
||||
|
||||
parameter NUM_OF_CS = 1,
|
||||
parameter DEFAULT_SPI_CFG = 0,
|
||||
parameter DEFAULT_CLK_DIV = 0,
|
||||
parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
|
||||
parameter NUM_OF_SDI = 1,
|
||||
parameter [0:0] SDO_DEFAULT = 1'b0,
|
||||
parameter [1:0] SDI_DELAY = 2'b00) (
|
||||
|
||||
input clk,
|
||||
input resetn,
|
||||
|
||||
output reg active,
|
||||
|
||||
output cmd_ready,
|
||||
input cmd_valid,
|
||||
input [15:0] cmd,
|
||||
|
||||
input sdo_data_valid,
|
||||
output reg sdo_data_ready,
|
||||
input [(DATA_WIDTH-1):0] sdo_data,
|
||||
|
||||
|
||||
input sdi_data_ready,
|
||||
output reg sdi_data_valid,
|
||||
output [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data,
|
||||
|
||||
input sync_ready,
|
||||
output reg sync_valid,
|
||||
output [7:0] sync,
|
||||
|
||||
output reg sclk,
|
||||
output reg sdo,
|
||||
output reg sdo_t,
|
||||
input [NUM_OF_SDI-1:0] sdi,
|
||||
output reg [NUM_OF_CS-1:0] cs,
|
||||
output reg three_wire
|
||||
);
|
||||
|
||||
localparam CMD_TRANSFER = 2'b00;
|
||||
localparam CMD_CHIPSELECT = 2'b01;
|
||||
localparam CMD_WRITE = 2'b10;
|
||||
localparam CMD_MISC = 2'b11;
|
||||
|
||||
localparam MISC_SYNC = 1'b0;
|
||||
localparam MISC_SLEEP = 1'b1;
|
||||
|
||||
localparam REG_CLK_DIV = 2'b00;
|
||||
localparam REG_CONFIG = 2'b01;
|
||||
localparam REG_WORD_LENGTH = 2'b10;
|
||||
|
||||
localparam BIT_COUNTER_WIDTH = DATA_WIDTH > 16 ? 5 :
|
||||
DATA_WIDTH > 8 ? 4 : 3;
|
||||
|
||||
localparam BIT_COUNTER_CARRY = 2** (BIT_COUNTER_WIDTH + 1);
|
||||
localparam BIT_COUNTER_CLEAR = {{8{1'b1}}, {BIT_COUNTER_WIDTH{1'b0}}, 1'b1};
|
||||
|
||||
reg sclk_int = 1'b0;
|
||||
wire sdo_int_s;
|
||||
reg sdo_t_int = 1'b0;
|
||||
|
||||
reg idle;
|
||||
|
||||
reg [7:0] clk_div_counter = 'h00;
|
||||
reg [7:0] clk_div_counter_next = 'h00;
|
||||
reg clk_div_last;
|
||||
|
||||
reg [(BIT_COUNTER_WIDTH+8):0] counter = 'h00;
|
||||
|
||||
wire [7:0] sleep_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
|
||||
wire [1:0] cs_sleep_counter = counter[(BIT_COUNTER_WIDTH+2):(BIT_COUNTER_WIDTH+1)];
|
||||
wire [2:0] cs_sleep_counter2 = counter[(BIT_COUNTER_WIDTH+3):(BIT_COUNTER_WIDTH+1)];
|
||||
wire [(BIT_COUNTER_WIDTH-1):0] bit_counter = counter[BIT_COUNTER_WIDTH:1];
|
||||
wire [7:0] transfer_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
|
||||
wire ntx_rx = counter[0];
|
||||
|
||||
reg trigger = 1'b0;
|
||||
reg trigger_next = 1'b0;
|
||||
reg wait_for_io = 1'b0;
|
||||
reg transfer_active = 1'b0;
|
||||
|
||||
wire last_bit;
|
||||
wire first_bit;
|
||||
reg last_transfer;
|
||||
reg [7:0] word_length = DATA_WIDTH;
|
||||
reg [7:0] left_aligned = 8'b0;
|
||||
wire end_of_word;
|
||||
|
||||
reg [7:0] sdi_counter = 8'b0;
|
||||
|
||||
assign first_bit = ((bit_counter == 'h0) || (bit_counter == word_length));
|
||||
assign last_bit = bit_counter == word_length - 1;
|
||||
assign end_of_word = last_bit == 1'b1 && ntx_rx == 1'b1 && clk_div_last == 1'b1;
|
||||
|
||||
reg [15:0] cmd_d1;
|
||||
|
||||
reg cpha = DEFAULT_SPI_CFG[0];
|
||||
reg cpol = DEFAULT_SPI_CFG[1];
|
||||
reg [7:0] clk_div = DEFAULT_CLK_DIV;
|
||||
|
||||
reg sdo_enabled = 1'b0;
|
||||
reg sdi_enabled = 1'b0;
|
||||
|
||||
reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0;
|
||||
|
||||
reg [SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+2){1'b0}};
|
||||
|
||||
wire [1:0] inst = cmd[13:12];
|
||||
wire [1:0] inst_d1 = cmd_d1[13:12];
|
||||
|
||||
wire exec_cmd = cmd_ready && cmd_valid;
|
||||
wire exec_transfer_cmd = exec_cmd && inst == CMD_TRANSFER;
|
||||
|
||||
wire exec_write_cmd = exec_cmd && inst == CMD_WRITE;
|
||||
wire exec_chipselect_cmd = exec_cmd && inst == CMD_CHIPSELECT;
|
||||
wire exec_misc_cmd = exec_cmd && inst == CMD_MISC;
|
||||
wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC;
|
||||
|
||||
wire trigger_tx;
|
||||
wire trigger_rx;
|
||||
|
||||
wire sleep_counter_compare;
|
||||
wire cs_sleep_counter_compare;
|
||||
wire cs_sleep_counter_compare2;
|
||||
|
||||
wire io_ready1;
|
||||
wire io_ready2;
|
||||
wire trigger_rx_s;
|
||||
|
||||
wire last_sdi_bit;
|
||||
|
||||
assign cmd_ready = idle;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (exec_transfer_cmd) begin
|
||||
sdo_enabled <= cmd[8];
|
||||
sdi_enabled <= cmd[9];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cmd_ready & cmd_valid)
|
||||
cmd_d1 <= cmd;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
active <= 1'b0;
|
||||
end else begin
|
||||
if (exec_cmd == 1'b1)
|
||||
active <= 1'b1;
|
||||
else if (sync_ready == 1'b1 && sync_valid == 1'b1)
|
||||
active <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// Load the interface configurations from the 'Configuration Write'
|
||||
// instruction
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
cpha <= DEFAULT_SPI_CFG[0];
|
||||
cpol <= DEFAULT_SPI_CFG[1];
|
||||
three_wire <= DEFAULT_SPI_CFG[2];
|
||||
clk_div <= DEFAULT_CLK_DIV;
|
||||
word_length <= DATA_WIDTH;
|
||||
left_aligned <= 8'b0;
|
||||
end else if (exec_write_cmd == 1'b1) begin
|
||||
if (cmd[9:8] == REG_CONFIG) begin
|
||||
cpha <= cmd[0];
|
||||
cpol <= cmd[1];
|
||||
three_wire <= cmd[2];
|
||||
end else if (cmd[9:8] == REG_CLK_DIV) begin
|
||||
clk_div <= cmd[7:0];
|
||||
end else if (cmd[9:8] == REG_WORD_LENGTH) begin
|
||||
// the max value of this reg must be DATA_WIDTH
|
||||
word_length <= cmd[7:0];
|
||||
left_aligned <= DATA_WIDTH - cmd[7:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 &&
|
||||
clk_div_counter == 'h01) || clk_div == 'h00)
|
||||
clk_div_last <= 1'b1;
|
||||
else
|
||||
clk_div_last <= 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin
|
||||
clk_div_counter <= clk_div;
|
||||
trigger <= 1'b1;
|
||||
end else begin
|
||||
clk_div_counter <= clk_div_counter - 1'b1;
|
||||
trigger <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
assign trigger_tx = trigger == 1'b1 && ntx_rx == 1'b0;
|
||||
assign trigger_rx = trigger == 1'b1 && ntx_rx == 1'b1;
|
||||
|
||||
assign sleep_counter_compare = sleep_counter == cmd_d1[7:0] && clk_div_last == 1'b1;
|
||||
assign cs_sleep_counter_compare = cs_sleep_counter == cmd_d1[9:8] && clk_div_last == 1'b1;
|
||||
assign cs_sleep_counter_compare2 = cs_sleep_counter2 == {cmd_d1[9:8],1'b1} && clk_div_last == 1'b1;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (idle == 1'b1) begin
|
||||
counter <= 'h00;
|
||||
end else if (clk_div_last == 1'b1 && wait_for_io == 1'b0) begin
|
||||
if (bit_counter == word_length) begin
|
||||
counter <= (counter & BIT_COUNTER_CLEAR) + (transfer_active ? 'h1 : 'h10) + BIT_COUNTER_CARRY;
|
||||
end else begin
|
||||
counter <= counter + (transfer_active ? 'h1 : 'h10);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
idle <= 1'b1;
|
||||
end else begin
|
||||
if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin
|
||||
idle <= 1'b0;
|
||||
end else begin
|
||||
case (inst_d1)
|
||||
CMD_TRANSFER: begin
|
||||
if (transfer_active == 1'b0 && wait_for_io == 1'b0)
|
||||
idle <= 1'b1;
|
||||
end
|
||||
CMD_CHIPSELECT: begin
|
||||
if (cs_sleep_counter_compare2)
|
||||
idle <= 1'b1;
|
||||
end
|
||||
CMD_MISC: begin
|
||||
case (cmd_d1[8])
|
||||
MISC_SLEEP: begin
|
||||
if (sleep_counter_compare)
|
||||
idle <= 1'b1;
|
||||
end
|
||||
MISC_SYNC: begin
|
||||
if (sync_ready)
|
||||
idle <= 1'b1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
cs <= 'hff;
|
||||
end else if (inst_d1 == CMD_CHIPSELECT && cs_sleep_counter_compare == 1'b1) begin
|
||||
cs <= cmd_d1[NUM_OF_CS-1:0];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
sync_valid <= 1'b0;
|
||||
end else begin
|
||||
if (exec_sync_cmd == 1'b1) begin
|
||||
sync_valid <= 1'b1;
|
||||
end else if (sync_ready == 1'b1) begin
|
||||
sync_valid <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign sync = cmd_d1[7:0];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0)
|
||||
sdo_data_ready <= 1'b0;
|
||||
else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 && transfer_active == 1'b1)
|
||||
sdo_data_ready <= 1'b1;
|
||||
else if (sdo_data_valid == 1'b1)
|
||||
sdo_data_ready <= 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0)
|
||||
sdi_data_valid <= 1'b0;
|
||||
else if (sdi_enabled == 1'b1 && last_sdi_bit == 1'b1 && trigger_rx_s == 1'b1)
|
||||
sdi_data_valid <= 1'b1;
|
||||
else if (sdi_data_ready == 1'b1)
|
||||
sdi_data_valid <= 1'b0;
|
||||
end
|
||||
|
||||
assign io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) &&
|
||||
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
|
||||
assign io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) &&
|
||||
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (idle == 1'b1) begin
|
||||
last_transfer <= 1'b0;
|
||||
end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin
|
||||
if (transfer_counter == cmd_d1[7:0])
|
||||
last_transfer <= 1'b1;
|
||||
else
|
||||
last_transfer <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
transfer_active <= 1'b0;
|
||||
wait_for_io <= 1'b0;
|
||||
end else begin
|
||||
if (exec_transfer_cmd == 1'b1) begin
|
||||
wait_for_io <= 1'b1;
|
||||
transfer_active <= 1'b0;
|
||||
end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin
|
||||
wait_for_io <= 1'b0;
|
||||
if (last_transfer == 1'b0)
|
||||
transfer_active <= 1'b1;
|
||||
else
|
||||
transfer_active <= 1'b0;
|
||||
end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin
|
||||
if (last_transfer == 1'b1 || io_ready2 == 1'b0)
|
||||
transfer_active <= 1'b0;
|
||||
if (io_ready2 == 1'b0)
|
||||
wait_for_io <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (transfer_active == 1'b1 || wait_for_io == 1'b1)
|
||||
begin
|
||||
sdo_t_int <= ~sdo_enabled;
|
||||
end else begin
|
||||
sdo_t_int <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// Load the SDO parallel data into the SDO shift register. In case of a custom
|
||||
// data width, additional bit shifting must done at load.
|
||||
always @(posedge clk) begin
|
||||
if ((inst_d1 == CMD_TRANSFER) && (!sdo_enabled)) begin
|
||||
data_sdo_shift <= {DATA_WIDTH{SDO_DEFAULT}};
|
||||
end else if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
|
||||
if (first_bit == 1'b1)
|
||||
data_sdo_shift <= sdo_data << left_aligned;
|
||||
else
|
||||
data_sdo_shift <= {data_sdo_shift[(DATA_WIDTH-2):0], 1'b0};
|
||||
end
|
||||
end
|
||||
|
||||
assign sdo_int_s = data_sdo_shift[DATA_WIDTH-1];
|
||||
|
||||
// In case of an interface with high clock rate (SCLK > 50MHz), the latch of
|
||||
// the SDI line can be delayed with 1, 2 or 3 SPI core clock cycle.
|
||||
// Taking the fact that in high SCLK frequencies the pre-scaler most likely will
|
||||
// be set to 0, to reduce the core clock's speed, this delay will mean that SDI will
|
||||
// be latched at one of the next consecutive SCLK edge.
|
||||
|
||||
always @(posedge clk) begin
|
||||
trigger_rx_d <= {trigger_rx_d, trigger_rx};
|
||||
end
|
||||
|
||||
assign trigger_rx_s = trigger_rx_d[SDI_DELAY+1];
|
||||
|
||||
// Load the serial data into SDI shift register(s), then link it to the output
|
||||
// register of the module
|
||||
|
||||
wire cs_active_s = (inst_d1 == CMD_CHIPSELECT) & ~(&cmd_d1[NUM_OF_CS-1:0]);
|
||||
genvar i;
|
||||
generate
|
||||
for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
|
||||
|
||||
reg [DATA_WIDTH-1:0] data_sdi_shift;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs_active_s) begin
|
||||
data_sdi_shift <= 0;
|
||||
end else begin
|
||||
if (trigger_rx_s == 1'b1) begin
|
||||
data_sdi_shift <= {data_sdi_shift, sdi[i]};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign sdi_data[i*DATA_WIDTH+:DATA_WIDTH] = data_sdi_shift;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign last_sdi_bit = (sdi_counter == word_length-1);
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
sdi_counter <= 8'b0;
|
||||
end else begin
|
||||
if (trigger_rx_s == 1'b1) begin
|
||||
sdi_counter <= last_sdi_bit ? 8'b0 : sdi_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (transfer_active == 1'b1) begin
|
||||
sclk_int <= cpol ^ cpha ^ ntx_rx;
|
||||
end else begin
|
||||
sclk_int <= cpol;
|
||||
end
|
||||
end
|
||||
|
||||
// Additional register stage to improve timing
|
||||
always @(posedge clk) begin
|
||||
sclk <= sclk_int;
|
||||
sdo <= sdo_int_s;
|
||||
sdo_t <= sdo_t_int;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,376 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_execution/spi_engine_execution.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="9382a18e40ea4f1189e2420aebaa5905"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/spi_engine_execution.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="spi_engine_execution"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,86 @@
|
||||
|
||||
package require qsys
|
||||
source ../../scripts/adi_env.tcl
|
||||
source ../../scripts/adi_ip_intel.tcl
|
||||
|
||||
ad_ip_create spi_engine_execution {SPI Engine Execution}
|
||||
set_module_property ELABORATION_CALLBACK p_elaboration
|
||||
ad_ip_files spi_engine_execution [list\
|
||||
spi_engine_execution.v]
|
||||
|
||||
# parameters
|
||||
|
||||
ad_ip_parameter NUM_OF_CS INTEGER 1
|
||||
ad_ip_parameter DEFAULT_SPI_CFG INTEGER 0
|
||||
ad_ip_parameter DEFAULT_CLK_DIV INTEGER 0
|
||||
ad_ip_parameter DATA_WIDTH INTEGER 8
|
||||
ad_ip_parameter NUM_OF_SDI INTEGER 1
|
||||
ad_ip_parameter SDI_DELAY INTEGER 0
|
||||
ad_ip_parameter SDO_DEFAULT INTEGER 0
|
||||
|
||||
proc p_elaboration {} {
|
||||
|
||||
set data_width [get_parameter_value DATA_WIDTH]
|
||||
set num_of_sdi [get_parameter_value NUM_OF_SDI]
|
||||
set num_of_cs [get_parameter_value NUM_OF_CS]
|
||||
|
||||
# clock and reset interface
|
||||
|
||||
ad_interface clock clk input 1
|
||||
ad_interface reset resetn input 1 if_clk
|
||||
|
||||
ad_interface signal active output 1
|
||||
|
||||
# command interface
|
||||
|
||||
add_interface cmd axi4stream end
|
||||
add_interface_port cmd cmd_ready tready output 1
|
||||
add_interface_port cmd cmd_valid tvalid input 1
|
||||
add_interface_port cmd cmd tdata input 16
|
||||
|
||||
set_interface_property cmd associatedClock if_clk
|
||||
set_interface_property cmd associatedReset if_resetn
|
||||
|
||||
# SDO data interface
|
||||
|
||||
add_interface sdo_data axi4stream end
|
||||
add_interface_port sdo_data sdo_data_ready tready output 1
|
||||
add_interface_port sdo_data sdo_data_valid tvalid input 1
|
||||
add_interface_port sdo_data sdo_data tdata input $data_width
|
||||
|
||||
set_interface_property sdo_data associatedClock if_clk
|
||||
set_interface_property sdo_data associatedReset if_resetn
|
||||
|
||||
# SDI data interface
|
||||
|
||||
add_interface sdi_data axi4stream start
|
||||
add_interface_port sdi_data sdi_data_ready tready input 1
|
||||
add_interface_port sdi_data sdi_data_valid tvalid output 1
|
||||
add_interface_port sdi_data sdi_data tdata output [expr $num_of_sdi * $data_width]
|
||||
|
||||
set_interface_property sdi_data associatedClock if_clk
|
||||
set_interface_property sdi_data associatedReset if_resetn
|
||||
|
||||
# SYNC data interface
|
||||
|
||||
add_interface sync axi4stream start
|
||||
add_interface_port sync sync_valid tvalid output 1
|
||||
add_interface_port sync sync_ready tready input 1
|
||||
add_interface_port sync sync tdata output 8
|
||||
|
||||
set_interface_property sync associatedClock if_clk
|
||||
set_interface_property sync associatedReset if_resetn
|
||||
|
||||
# physical SPI interface
|
||||
|
||||
ad_interface clock sclk output 1
|
||||
|
||||
ad_interface signal sdo output 1
|
||||
ad_interface signal sdo_t output 1
|
||||
ad_interface signal sdi input $num_of_sdi
|
||||
|
||||
ad_interface signal cs output 1
|
||||
ad_interface signal three_wire output 1
|
||||
|
||||
}
|
||||
|
||||
@@ -0,0 +1,968 @@
|
||||
|
||||
****** Vivado v2019.1.3 (64-bit)
|
||||
**** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
**** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
source spi_engine_execution_ip.tcl
|
||||
# source ../../scripts/adi_env.tcl
|
||||
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
|
||||
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
|
||||
## if [info exists ::env(ADI_HDL_DIR)] {
|
||||
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
|
||||
## }
|
||||
## if [info exists ::env(ADI_GHDL_DIR)] {
|
||||
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
|
||||
## }
|
||||
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
|
||||
### variable auto_set_param_list
|
||||
### variable auto_set_param_list_overwritable
|
||||
### variable fpga_series_list
|
||||
### variable fpga_family_list
|
||||
### variable speed_grade_list
|
||||
### variable dev_package_list
|
||||
### variable xcvr_type_list
|
||||
### variable fpga_voltage_list
|
||||
### set auto_set_param_list { \
|
||||
### DEV_PACKAGE \
|
||||
### SPEED_GRADE \
|
||||
### FPGA_FAMILY \
|
||||
### FPGA_TECHNOLOGY }
|
||||
### set auto_set_param_list_overwritable { \
|
||||
### FPGA_VOLTAGE \
|
||||
### XCVR_TYPE }
|
||||
### set fpga_technology_list { \
|
||||
### { Unknown 0 } \
|
||||
### { 7series 1 } \
|
||||
### { ultrascale 2 } \
|
||||
### { ultrascale+ 3 }}
|
||||
### set fpga_family_list { \
|
||||
### { Unknown 0 } \
|
||||
### { artix 1 } \
|
||||
### { kintex 2 } \
|
||||
### { virtex 3 } \
|
||||
### { zynq 4 }}
|
||||
### set speed_grade_list { \
|
||||
### { Unknown 0 } \
|
||||
### { -1 10 } \
|
||||
### { -1L 11 } \
|
||||
### { -1H 12 } \
|
||||
### { -1HV 13 } \
|
||||
### { -1LV 14 } \
|
||||
### { -2 20 } \
|
||||
### { -2L 21 } \
|
||||
### { -2LV 22 } \
|
||||
### { -3 30 }}
|
||||
### set dev_package_list { \
|
||||
### { Unknown 0 } \
|
||||
### { rf 1 } \
|
||||
### { fl 2 } \
|
||||
### { ff 3 } \
|
||||
### { fb 4 } \
|
||||
### { hc 5 } \
|
||||
### { fh 6 } \
|
||||
### { cs 7 } \
|
||||
### { cp 8 } \
|
||||
### { ft 9 } \
|
||||
### { fg 10 } \
|
||||
### { sb 11 } \
|
||||
### { rb 12 } \
|
||||
### { rs 13 } \
|
||||
### { cl 14 } \
|
||||
### { sf 15 } \
|
||||
### { ba 16 } \
|
||||
### { fa 17 } \
|
||||
### { fs 18 } \
|
||||
### { fi 19 }}
|
||||
### set xcvr_type_list { \
|
||||
### { Unknown 0 } \
|
||||
### { GTPE2_NOT_SUPPORTED 1 } \
|
||||
### { GTXE2 2 } \
|
||||
### { GTHE2_NOT_SUPPORTED 3 } \
|
||||
### { GTZE2_NOT_SUPPORTED 4 } \
|
||||
### { GTHE3 5 } \
|
||||
### { GTYE3_NOT_SUPPORTED 6 } \
|
||||
### { GTRE4_NOT_SUPPORTED 7 } \
|
||||
### { GTHE4 8 } \
|
||||
### { GTYE4 9 } \
|
||||
### { GTME4_NOT_SUPPORTED 10}}
|
||||
### set fpga_voltage_list {0 5000} ;
|
||||
### proc adi_device_spec {cellpath param} {
|
||||
###
|
||||
### set list_pointer [string tolower $param]
|
||||
### set list_pointer [append list_pointer "_list"]
|
||||
###
|
||||
### upvar 1 $list_pointer $list_pointer
|
||||
###
|
||||
### set ip [get_bd_cells $cellpath]
|
||||
### set part [get_property PART [current_project]]
|
||||
###
|
||||
### switch -regexp -- $param {
|
||||
### FPGA_TECHNOLOGY {
|
||||
### switch -regexp -- $part {
|
||||
### ^xc7 {set series_name 7series}
|
||||
### ^xczu {set series_name ultrascale+}
|
||||
### ^xc.u.p {set series_name ultrascale+}
|
||||
### ^xc.u {set series_name ultrascale }
|
||||
### default {
|
||||
### puts "Undefined fpga technology for \"$part\"!"
|
||||
### exit -1
|
||||
### }
|
||||
### }
|
||||
### return "$series_name"
|
||||
### }
|
||||
### FPGA_FAMILY {
|
||||
### set fpga_family [get_property FAMILY $part]
|
||||
### foreach i $fpga_family_list {
|
||||
### regexp ^[lindex $i 0] $fpga_family matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### SPEED_GRADE {
|
||||
### set speed_grade [get_property SPEED $part]
|
||||
### return "$speed_grade"
|
||||
### }
|
||||
### DEV_PACKAGE {
|
||||
### set dev_package [get_property PACKAGE $part]
|
||||
### foreach i $dev_package_list {
|
||||
### regexp ^[lindex $i 0] $dev_package matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### XCVR_TYPE {
|
||||
### set matched ""
|
||||
### set dev_transcivers "none"
|
||||
### foreach x [list_property $part] {
|
||||
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
|
||||
### }
|
||||
### foreach i $xcvr_type_list {
|
||||
### regexp ^[lindex $i 0] $dev_transcivers matched
|
||||
### }
|
||||
### if { $matched eq "" } {
|
||||
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### FPGA_VOLTAGE {
|
||||
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
|
||||
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
|
||||
###
|
||||
### return "$fpga_voltage"
|
||||
### }
|
||||
### default {
|
||||
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
|
||||
### }
|
||||
### }
|
||||
### }
|
||||
## if {![info exists REQUIRED_VIVADO_VERSION]} {
|
||||
## set REQUIRED_VIVADO_VERSION "2019.1"
|
||||
## }
|
||||
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
|
||||
## set IGNORE_VERSION_CHECK 1
|
||||
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
|
||||
## set IGNORE_VERSION_CHECK 0
|
||||
## }
|
||||
## proc adi_ip_ttcl {ip_name ip_constr_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
|
||||
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_sim_ttcl {ip_name ip_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
|
||||
## set f [ipx::add_file $ip_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_bd {ip_name ip_bd_files} {
|
||||
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
|
||||
## if {$proj_filegroup == {}} {
|
||||
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
|
||||
## }
|
||||
##
|
||||
## foreach file $ip_bd_files {
|
||||
## set f [ipx::add_file $file $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type tclSource \
|
||||
## ] $f
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_infer_streaming_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_ip_infer_mm_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
|
||||
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency $port
|
||||
## if {$driver_value != {}} {
|
||||
## set_property DRIVER_VALUE $driver_value $port
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_set_bus_dependency {bus prefix dependency} {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
|
||||
## adi_set_ports_dependency $prefix $dependency 0
|
||||
## }
|
||||
## proc adi_add_port_map {bus phys logic} {
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## }
|
||||
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## adi_add_port_map $bus {*}$port_map
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
|
||||
## for {set i 0} {$i < $num} {incr i} {
|
||||
## set bus_name [format "%s%d" $bus_name_prefix $i]
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## if {$dependency ne ""} {
|
||||
## set bus_dependency [string map [list "{i}" $i] $dependency]
|
||||
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
|
||||
## }
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## lassign $port_map phys logic width width_dep
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
|
||||
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
|
||||
## if {$width_dep ne ""} {
|
||||
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
|
||||
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
|
||||
## set width_dep_r "(($width_dep) * $i)"
|
||||
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
|
||||
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
|
||||
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
|
||||
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
|
||||
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
|
||||
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
|
||||
## set_property display_name $clock_inf_name $clock_inf
|
||||
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
|
||||
## set_property physical_name $clock_signal_name $clock_map
|
||||
##
|
||||
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
|
||||
## set_property value $bus_inf_name $assoc_busif
|
||||
##
|
||||
## if { $reset_signal_name != "" } {
|
||||
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
|
||||
## set_property value $reset_signal_name $assoc_reset
|
||||
##
|
||||
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
|
||||
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
|
||||
## set_property display_name $reset_inf_name $reset_inf
|
||||
## set_property interface_mode $reset_signal_mode $reset_inf
|
||||
## set reset_map [ipx::add_port_map "RST" $reset_inf]
|
||||
## set_property physical_name $reset_signal_name $reset_map
|
||||
##
|
||||
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
|
||||
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
|
||||
## set_property value "ACTIVE_LOW" $reset_polarity
|
||||
## } else {
|
||||
## set_property value "ACTIVE_HIGH" $reset_polarity
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_add_core_dependencies {vlnvs} {
|
||||
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
|
||||
## foreach vlnv $vlnvs {
|
||||
## ipx::add_subcore $vlnv $file_group
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_create {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
## global ad_ghdl_dir
|
||||
## global REQUIRED_VIVADO_VERSION
|
||||
## global IGNORE_VERSION_CHECK
|
||||
##
|
||||
## set VIVADO_VERSION [version -short]
|
||||
## if {$IGNORE_VERSION_CHECK} {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## }
|
||||
## } else {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "ERROR: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
|
||||
## exit 2
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## create_project $ip_name . -force
|
||||
##
|
||||
## ## Load custom message severity definitions
|
||||
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
|
||||
##
|
||||
## set lib_dirs $ad_hdl_dir/library
|
||||
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
|
||||
## lappend lib_dirs $ad_ghdl_dir/library
|
||||
## }
|
||||
##
|
||||
## set_property ip_repo_paths $lib_dirs [current_fileset]
|
||||
## update_ip_catalog
|
||||
## }
|
||||
## proc adi_ip_files {ip_name ip_files} {
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## foreach m_file $ip_files {
|
||||
## if {[file extension $m_file] eq ".xdc"} {
|
||||
## add_files -norecurse -fileset constrs_1 $m_file
|
||||
## } else {
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
|
||||
## }
|
||||
## }
|
||||
## set_property "top" "$ip_name" $proj_fileset
|
||||
## }
|
||||
## proc adi_ip_properties_lite {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
##
|
||||
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
|
||||
##
|
||||
## set_property name $ip_name [ipx::current_core]
|
||||
##
|
||||
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
|
||||
## set_property company_url {http://www.analog.com} [ipx::current_core]
|
||||
##
|
||||
## set i_families ""
|
||||
## foreach i_part [get_parts] {
|
||||
## lappend i_families [get_property FAMILY $i_part]
|
||||
## }
|
||||
## set i_families [lsort -unique $i_families]
|
||||
## set s_families [get_property supported_families [ipx::current_core]]
|
||||
## foreach i_family $i_families {
|
||||
## set s_families "$s_families $i_family Production"
|
||||
## set s_families "$s_families $i_family Beta"
|
||||
## }
|
||||
## set_property supported_families $s_families [ipx::current_core]
|
||||
##
|
||||
## ipx::save_core [ipx::current_core]
|
||||
##
|
||||
## ipx::remove_all_bus_interface [ipx::current_core]
|
||||
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
|
||||
## foreach map $memory_maps {
|
||||
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
|
||||
## }
|
||||
##
|
||||
## ipx::update_checksums [ipx::current_core]
|
||||
## ipx::save_core [ipx::current_core]
|
||||
## }
|
||||
## proc adi_ip_properties {ip_name} {
|
||||
##
|
||||
## adi_ip_properties_lite $ip_name
|
||||
##
|
||||
## ipx::infer_bus_interface {\
|
||||
## s_axi_awvalid \
|
||||
## s_axi_awaddr \
|
||||
## s_axi_awprot \
|
||||
## s_axi_awready \
|
||||
## s_axi_wvalid \
|
||||
## s_axi_wdata \
|
||||
## s_axi_wstrb \
|
||||
## s_axi_wready \
|
||||
## s_axi_bvalid \
|
||||
## s_axi_bresp \
|
||||
##
|
||||
## s_axi_bready \
|
||||
## s_axi_arvalid \
|
||||
## s_axi_araddr \
|
||||
## s_axi_arprot \
|
||||
## s_axi_arready \
|
||||
## s_axi_rvalid \
|
||||
## s_axi_rdata \
|
||||
## s_axi_rresp \
|
||||
## s_axi_rready} \
|
||||
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
|
||||
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
|
||||
##
|
||||
## if {$raddr_width != $waddr_width} {
|
||||
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
|
||||
## set range 65536
|
||||
## } else {
|
||||
## if {$raddr_width >= 16} {
|
||||
## set range 65536
|
||||
## } else {
|
||||
## set range [expr 1 << $raddr_width]
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
## set_property range $range [ipx::get_address_blocks axi_lite \
|
||||
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
|
||||
## ipx::save_core
|
||||
## }
|
||||
## proc adi_init_bd_tcl {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## if { [file exists bd] } {
|
||||
## file delete -force bd
|
||||
## }
|
||||
## file mkdir bd
|
||||
##
|
||||
## set bd_tcl [open "bd/bd.tcl" w]
|
||||
##
|
||||
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
|
||||
## puts $bd_tcl "proc init {cellpath otherInfo} {"
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl ""
|
||||
## set auto_set_param ""
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
|
||||
## puts $bd_tcl $auto_set_param
|
||||
## }
|
||||
##
|
||||
## set auto_set_overwritable_param ""
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_overwritable_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_overwritable_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
|
||||
## puts $bd_tcl $auto_set_overwritable_param
|
||||
## }
|
||||
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
|
||||
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
|
||||
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set parent_dir \"../\""
|
||||
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
|
||||
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
|
||||
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " break"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " append parent_dir \"../\""
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## close $bd_tcl
|
||||
##
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
|
||||
##
|
||||
## set local_mk [open "temporary_case_dependencies.mk" w]
|
||||
## seek $local_mk 0 start
|
||||
## puts $local_mk "CLEAN_TARGET += bd"
|
||||
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
|
||||
## close $local_mk
|
||||
## }
|
||||
## proc adi_add_auto_fpga_spec_params {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_device_spec_param {ip_param} {
|
||||
##
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## set list_pointer [string tolower $ip_param]
|
||||
## set list_pointer [append list_pointer "_list"]
|
||||
##
|
||||
## global $list_pointer
|
||||
##
|
||||
## # set j 1D list from the original list
|
||||
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
|
||||
##
|
||||
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
|
||||
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "range_long" \
|
||||
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
|
||||
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## } else {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "pairs" \
|
||||
## "value_validation_pairs" $j ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## }
|
||||
##
|
||||
## # FPGA info grup
|
||||
## set info_group_name "FPGA info"
|
||||
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
|
||||
## if { [string trim $info_group] eq "" } {
|
||||
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
|
||||
## -parent $page0 -display_name $info_group_name]
|
||||
## }
|
||||
##
|
||||
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
|
||||
## set_property -dict [list "widget" "comboBox" ] $p
|
||||
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
|
||||
## }
|
||||
## proc adi_if_define {name} {
|
||||
##
|
||||
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
|
||||
## ipx::create_bus_definition analog.com interface $name 1.0
|
||||
##
|
||||
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
|
||||
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
|
||||
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
|
||||
##
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## }
|
||||
## proc adi_if_ports {dir width name {type none}} {
|
||||
##
|
||||
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
|
||||
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
|
||||
## set_property master_presence required $m_intf
|
||||
## set_property slave_presence required $m_intf
|
||||
## set_property master_width $width $m_intf
|
||||
## set_property slave_width $width $m_intf
|
||||
##
|
||||
## set m_dir "in"
|
||||
## set s_dir "out"
|
||||
## if {$dir eq "output"} {
|
||||
## set m_dir "out"
|
||||
## set s_dir "in"
|
||||
## }
|
||||
##
|
||||
## set_property master_direction $m_dir $m_intf
|
||||
## set_property slave_direction $s_dir $m_intf
|
||||
##
|
||||
## if {$type ne "none"} {
|
||||
## set_property is_${type} true $m_intf
|
||||
## }
|
||||
##
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## }
|
||||
## proc adi_if_infer_bus {if_name mode name maps} {
|
||||
##
|
||||
## ipx::add_bus_interface $name [ipx::current_core]
|
||||
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
|
||||
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
|
||||
## set_property interface_mode $mode $m_bus_if
|
||||
##
|
||||
## foreach map $maps {
|
||||
## set m_maps [regexp -all -inline {\S+} $map]
|
||||
## lassign $m_maps p_name p_map
|
||||
## ipx::add_port_map $p_name $m_bus_if
|
||||
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
|
||||
## }
|
||||
## }
|
||||
# adi_ip_create spi_engine_execution
|
||||
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
|
||||
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1343} -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1306} -new_severity WARNING
|
||||
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
|
||||
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
|
||||
## set_msg_config -id {Synth 8-3331} -new_severity INFO
|
||||
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
|
||||
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
|
||||
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
|
||||
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_execution'.)
|
||||
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
|
||||
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
|
||||
# adi_ip_files spi_engine_execution [list \
|
||||
# "spi_engine_execution.v" \
|
||||
# ]
|
||||
# adi_ip_properties_lite spi_engine_execution
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'sleep_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'sleep_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'cs_sleep_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'cs_sleep_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'cs_sleep_counter2' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'cs_sleep_counter2' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'bit_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'transfer_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'transfer_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'exec_transfer_cmd' has a dependency on the module local parameter or undefined parameter 'CMD_TRANSFER'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'exec_write_cmd' has a dependency on the module local parameter or undefined parameter 'CMD_WRITE'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'exec_chipselect_cmd' has a dependency on the module local parameter or undefined parameter 'CMD_CHIPSELECT'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'exec_misc_cmd' has a dependency on the module local parameter or undefined parameter 'CMD_MISC'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'exec_sync_cmd' has a dependency on the module local parameter or undefined parameter 'MISC_SYNC'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'cs_active_s' has a dependency on the module local parameter or undefined parameter 'CMD_CHIPSELECT'.
|
||||
INFO: [IP_Flow 19-4821] For module 'spi_engine_execution', parameter 'SDO_DEFAULT' is inferred to be bitString format.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_data' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_data' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'sync' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
|
||||
INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'interface_jesd204_tx_status'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_0' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_1' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_2' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_3' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_4' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_5' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_6' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_7' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_WR_EN on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_WR_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port ENABLE on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port MEM_RESET on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port ENABLED on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port SYNC_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_spi_engine_offload_ctrl' of definition 'analog.com:interface:spi_engine_offload_ctrl:1.0' (from User Repositories).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_spi_master' of definition 'analog.com:interface:spi_master:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_DATA on bus interface abstraction spi_engine_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port SDO_READY on bus interface abstraction spi_engine_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port SDO_VALID on bus interface abstraction spi_engine_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port SDI_READY on bus interface abstraction spi_engine_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port SDI_VALID on bus interface abstraction spi_engine_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port SYNC_DATA on bus interface abstraction spi_engine_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_spi_engine_ctrl' of definition 'analog.com:interface:spi_engine_ctrl:1.0' (from User Repositories).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data' and definition port 'DATA'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sdi': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data_valid' and definition port 'DATA'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sdo': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data_ready' and definition port 'DATA'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_valid' and definition port 'VALID'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'cmd': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'cmd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data_valid' and definition port 'VALID'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sync': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sync': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_0': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_1': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_2': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_3': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_4': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_5': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_6': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_7': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "CMD_WR_EN" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "CMD_WR_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "ENABLE" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "MEM_RESET" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "ENABLED" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "SYNC_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "CMD_DATA" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDO_READY" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDO_VALID" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDI_READY" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDI_VALID" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SYNC_DATA" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
# ipx::remove_all_bus_interface [ipx::current_core]
|
||||
# adi_add_bus "ctrl" "slave" \
|
||||
# "analog.com:interface:spi_engine_ctrl_rtl:1.0" \
|
||||
# "analog.com:interface:spi_engine_ctrl:1.0" \
|
||||
# {
|
||||
# {"cmd_ready" "CMD_READY"} \
|
||||
# {"cmd_valid" "CMD_VALID"} \
|
||||
# {"cmd" "CMD_DATA"} \
|
||||
# {"sdo_data_ready" "SDO_READY"} \
|
||||
# {"sdo_data_valid" "SDO_VALID"} \
|
||||
# {"sdo_data" "SDO_DATA"} \
|
||||
# {"sdi_data_ready" "SDI_READY"} \
|
||||
# {"sdi_data_valid" "SDI_VALID"} \
|
||||
# {"sdi_data" "SDI_DATA"} \
|
||||
# {"sync_ready" "SYNC_READY"} \
|
||||
# {"sync_valid" "SYNC_VALID"} \
|
||||
# {"sync" "SYNC_DATA"} \
|
||||
# }
|
||||
# adi_add_bus_clock "clk" "ctrl" "resetn"
|
||||
# adi_add_bus "spi" "master" \
|
||||
# "analog.com:interface:spi_master_rtl:1.0" \
|
||||
# "analog.com:interface:spi_master:1.0" \
|
||||
# {
|
||||
# {"sclk" "SCLK"} \
|
||||
# {"sdi" "SDI"} \
|
||||
# {"sdo" "SDO"} \
|
||||
# {"sdo_t" "SDO_T"} \
|
||||
# {"three_wire" "THREE_WIRE"} \
|
||||
# {"cs" "CS"} \
|
||||
# }
|
||||
# adi_add_bus_clock "clk" "spi" "resetn"
|
||||
# set cc [ipx::current_core]
|
||||
# set_property -dict [list \
|
||||
# "value_validation_type" "range_long" \
|
||||
# "value_validation_range_minimum" "8" \
|
||||
# "value_validation_range_maximum" "256" \
|
||||
# ] \
|
||||
# [ipx::get_user_parameters DATA_WIDTH -of_objects $cc]
|
||||
# set_property -dict [list \
|
||||
# "value_validation_type" "range_long" \
|
||||
# "value_validation_range_minimum" "1" \
|
||||
# "value_validation_range_maximum" "32" \
|
||||
# ] \
|
||||
# [ipx::get_user_parameters NUM_OF_CS -of_objects $cc]
|
||||
# set_property -dict [list \
|
||||
# "value_validation_type" "range_long" \
|
||||
# "value_validation_range_minimum" "1" \
|
||||
# "value_validation_range_maximum" "8" \
|
||||
# ] \
|
||||
# [ipx::get_user_parameters NUM_OF_SDI -of_objects $cc]
|
||||
# set_property -dict [list \
|
||||
# "value_validation_type" "list" \
|
||||
# "value_validation_list" "0 1 2 3" \
|
||||
# ] \
|
||||
# [ipx::get_user_parameters DEFAULT_SPI_CFG -of_objects $cc]
|
||||
# set_property -dict [list \
|
||||
# "value_validation_type" "list" \
|
||||
# "value_validation_range_minimum" "0" \
|
||||
# "value_validation_range_maximum" "255" \
|
||||
# ] \
|
||||
# [ipx::get_user_parameters DEFAULT_CLK_DIV -of_objects $cc]
|
||||
# set_property -dict [list \
|
||||
# "value_validation_type" "list" \
|
||||
# "value_validation_list" "0 1" \
|
||||
# ] \
|
||||
# [ipx::get_user_parameters SDO_DEFAULT -of_objects $cc]
|
||||
# set_property -dict [list \
|
||||
# "value_format" "bool" \
|
||||
# "value" "false" \
|
||||
# ] \
|
||||
# [ipx::get_user_parameters SDI_DELAY -of_objects $cc]
|
||||
# set_property -dict [list \
|
||||
# "value_format" "bool" \
|
||||
# "value" "false" \
|
||||
# ] \
|
||||
# [ipx::get_hdl_parameters SDI_DELAY -of_objects $cc]
|
||||
# ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
# ipx::save_core [ipx::current_core]
|
||||
# ipgui::add_page -name {SPI Engine execution} -component [ipx::current_core] -display_name {AXI SPI Engine execution}
|
||||
# set page0 [ipgui::get_pagespec -name "SPI Engine execution" -component $cc]
|
||||
# set general_group [ipgui::add_group -name "General Configuration" -component $cc \
|
||||
# -parent $page0 -display_name "General Configuration" ]
|
||||
# ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group
|
||||
# set_property -dict [list \
|
||||
# "display_name" "Parallel data width" \
|
||||
# "tooltip" "\[DATA_WIDTH\] Define the data interface width"
|
||||
# ] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc]
|
||||
# ipgui::add_param -name "NUM_OF_CS" -component $cc -parent $general_group
|
||||
# set_property -dict [list \
|
||||
# "display_name" "Number of CSN lines" \
|
||||
# "tooltip" "\[NUM_OF_CS\] Define the number of chip select lines" \
|
||||
# ] [ipgui::get_guiparamspec -name "NUM_OF_CS" -component $cc]
|
||||
# ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group
|
||||
# set_property -dict [list \
|
||||
# "display_name" "Number of MISO lines" \
|
||||
# "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \
|
||||
# ] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc]
|
||||
# set spi_config_group [ipgui::add_group -name "SPI Configuration" -component $cc \
|
||||
# -parent $page0 -display_name "SPI Configuration" ]
|
||||
# ipgui::add_param -name "DEFAULT_SPI_CFG" -component $cc -parent $spi_config_group
|
||||
# set_property -dict [list \
|
||||
# "widget" "comboBox" \
|
||||
# "display_name" "Default SPI mode" \
|
||||
# "tooltip" "\[DEFAULT_SPI_CFG\] Define the default SPI configuration, bit 1 defines CPOL, bit 0 defines CPHA"
|
||||
# ] [ipgui::get_guiparamspec -name "DEFAULT_SPI_CFG" -component $cc]
|
||||
# ipgui::add_param -name "DEFAULT_CLK_DIV" -component $cc -parent $spi_config_group
|
||||
# set_property -dict [list \
|
||||
# "display_name" "Default SCLK divider" \
|
||||
# "tooltip" "\[DEFAULT_CLK_DIV\] Define the default SCLK divider, fSCLK = fCoreClk / DEFAULT_CLK_DIV + 1"
|
||||
# ] [ipgui::get_guiparamspec -name "DEFAULT_CLK_DIV" -component $cc]
|
||||
# set mosi_miso_config_group [ipgui::add_group -name "MOSI/MISO Configuration" -component $cc \
|
||||
# -parent $page0 -display_name "MOSI/MISO Configuration" ]
|
||||
# ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $mosi_miso_config_group
|
||||
WARNING: [IP_Flow 19-465] param 'NUM_OF_SDI' already exists. Ignoring.
|
||||
# set_property -dict [list \
|
||||
# "display_name" "Number of MISO" \
|
||||
# "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines"
|
||||
# ] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc]
|
||||
# ipgui::add_param -name "SDI_DELAY" -component $cc -parent $mosi_miso_config_group
|
||||
# set_property -dict [list \
|
||||
# "display_name" "Delay MISO latching" \
|
||||
# "tooltip" "\[SDI_DELAY\] Delay the MISO latching to the next consecutive SCLK edge"
|
||||
# ] [ipgui::get_guiparamspec -name "SDI_DELAY" -component $cc]
|
||||
# ipgui::add_param -name "SDO_DEFAULT" -component $cc -parent $mosi_miso_config_group
|
||||
# set_property -dict [list \
|
||||
# "widget" "comboBox" \
|
||||
# "display_name" "MOSI default level" \
|
||||
# "tooltip" "\[SDO_DEFAULT\] Define the default voltage level on MOSI"
|
||||
# ] [ipgui::get_guiparamspec -name "SDO_DEFAULT" -component $cc]
|
||||
# ipx::create_xgui_files $cc
|
||||
# ipx::save_core [ipx::current_core]
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:07:50 2021...
|
||||
@@ -0,0 +1,182 @@
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create spi_engine_execution
|
||||
adi_ip_files spi_engine_execution [list \
|
||||
"spi_engine_execution.v" \
|
||||
]
|
||||
|
||||
adi_ip_properties_lite spi_engine_execution
|
||||
# Remove all inferred interfaces
|
||||
ipx::remove_all_bus_interface [ipx::current_core]
|
||||
|
||||
## Interface definitions
|
||||
|
||||
adi_add_bus "ctrl" "slave" \
|
||||
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:spi_engine_ctrl:1.0" \
|
||||
{
|
||||
{"cmd_ready" "CMD_READY"} \
|
||||
{"cmd_valid" "CMD_VALID"} \
|
||||
{"cmd" "CMD_DATA"} \
|
||||
{"sdo_data_ready" "SDO_READY"} \
|
||||
{"sdo_data_valid" "SDO_VALID"} \
|
||||
{"sdo_data" "SDO_DATA"} \
|
||||
{"sdi_data_ready" "SDI_READY"} \
|
||||
{"sdi_data_valid" "SDI_VALID"} \
|
||||
{"sdi_data" "SDI_DATA"} \
|
||||
{"sync_ready" "SYNC_READY"} \
|
||||
{"sync_valid" "SYNC_VALID"} \
|
||||
{"sync" "SYNC_DATA"} \
|
||||
}
|
||||
adi_add_bus_clock "clk" "ctrl" "resetn"
|
||||
|
||||
adi_add_bus "spi" "master" \
|
||||
"analog.com:interface:spi_master_rtl:1.0" \
|
||||
"analog.com:interface:spi_master:1.0" \
|
||||
{
|
||||
{"sclk" "SCLK"} \
|
||||
{"sdi" "SDI"} \
|
||||
{"sdo" "SDO"} \
|
||||
{"sdo_t" "SDO_T"} \
|
||||
{"three_wire" "THREE_WIRE"} \
|
||||
{"cs" "CS"} \
|
||||
}
|
||||
adi_add_bus_clock "clk" "spi" "resetn"
|
||||
|
||||
## Parameter validations
|
||||
|
||||
set cc [ipx::current_core]
|
||||
|
||||
## DATA_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "8" \
|
||||
"value_validation_range_maximum" "256" \
|
||||
] \
|
||||
[ipx::get_user_parameters DATA_WIDTH -of_objects $cc]
|
||||
|
||||
## NUM_OF_CS
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "32" \
|
||||
] \
|
||||
[ipx::get_user_parameters NUM_OF_CS -of_objects $cc]
|
||||
|
||||
## NUM_OF_SDI
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "8" \
|
||||
] \
|
||||
[ipx::get_user_parameters NUM_OF_SDI -of_objects $cc]
|
||||
|
||||
## DEFAULT_SPI_CFG
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "list" \
|
||||
"value_validation_list" "0 1 2 3" \
|
||||
] \
|
||||
[ipx::get_user_parameters DEFAULT_SPI_CFG -of_objects $cc]
|
||||
|
||||
## DEFAULT_CLK_DIV
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "list" \
|
||||
"value_validation_range_minimum" "0" \
|
||||
"value_validation_range_maximum" "255" \
|
||||
] \
|
||||
[ipx::get_user_parameters DEFAULT_CLK_DIV -of_objects $cc]
|
||||
|
||||
## SDO_DEFAULT
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "list" \
|
||||
"value_validation_list" "0 1" \
|
||||
] \
|
||||
[ipx::get_user_parameters SDO_DEFAULT -of_objects $cc]
|
||||
|
||||
## SDI_DELAY
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" "false" \
|
||||
] \
|
||||
[ipx::get_user_parameters SDI_DELAY -of_objects $cc]
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" "false" \
|
||||
] \
|
||||
[ipx::get_hdl_parameters SDI_DELAY -of_objects $cc]
|
||||
|
||||
## Customize IP Layout
|
||||
|
||||
## Remove the automatically generated GUI page
|
||||
ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
## Create general configuration page
|
||||
ipgui::add_page -name {SPI Engine execution} -component [ipx::current_core] -display_name {AXI SPI Engine execution}
|
||||
set page0 [ipgui::get_pagespec -name "SPI Engine execution" -component $cc]
|
||||
|
||||
set general_group [ipgui::add_group -name "General Configuration" -component $cc \
|
||||
-parent $page0 -display_name "General Configuration" ]
|
||||
|
||||
ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Parallel data width" \
|
||||
"tooltip" "\[DATA_WIDTH\] Define the data interface width"
|
||||
] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc]
|
||||
|
||||
ipgui::add_param -name "NUM_OF_CS" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Number of CSN lines" \
|
||||
"tooltip" "\[NUM_OF_CS\] Define the number of chip select lines" \
|
||||
] [ipgui::get_guiparamspec -name "NUM_OF_CS" -component $cc]
|
||||
|
||||
ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Number of MISO lines" \
|
||||
"tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \
|
||||
] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc]
|
||||
|
||||
set spi_config_group [ipgui::add_group -name "SPI Configuration" -component $cc \
|
||||
-parent $page0 -display_name "SPI Configuration" ]
|
||||
|
||||
ipgui::add_param -name "DEFAULT_SPI_CFG" -component $cc -parent $spi_config_group
|
||||
set_property -dict [list \
|
||||
"widget" "comboBox" \
|
||||
"display_name" "Default SPI mode" \
|
||||
"tooltip" "\[DEFAULT_SPI_CFG\] Define the default SPI configuration, bit 1 defines CPOL, bit 0 defines CPHA"
|
||||
] [ipgui::get_guiparamspec -name "DEFAULT_SPI_CFG" -component $cc]
|
||||
|
||||
ipgui::add_param -name "DEFAULT_CLK_DIV" -component $cc -parent $spi_config_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Default SCLK divider" \
|
||||
"tooltip" "\[DEFAULT_CLK_DIV\] Define the default SCLK divider, fSCLK = fCoreClk / DEFAULT_CLK_DIV + 1"
|
||||
] [ipgui::get_guiparamspec -name "DEFAULT_CLK_DIV" -component $cc]
|
||||
|
||||
set mosi_miso_config_group [ipgui::add_group -name "MOSI/MISO Configuration" -component $cc \
|
||||
-parent $page0 -display_name "MOSI/MISO Configuration" ]
|
||||
|
||||
ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $mosi_miso_config_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Number of MISO" \
|
||||
"tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines"
|
||||
] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc]
|
||||
|
||||
ipgui::add_param -name "SDI_DELAY" -component $cc -parent $mosi_miso_config_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Delay MISO latching" \
|
||||
"tooltip" "\[SDI_DELAY\] Delay the MISO latching to the next consecutive SCLK edge"
|
||||
] [ipgui::get_guiparamspec -name "SDI_DELAY" -component $cc]
|
||||
|
||||
ipgui::add_param -name "SDO_DEFAULT" -component $cc -parent $mosi_miso_config_group
|
||||
set_property -dict [list \
|
||||
"widget" "comboBox" \
|
||||
"display_name" "MOSI default level" \
|
||||
"tooltip" "\[SDO_DEFAULT\] Define the default voltage level on MOSI"
|
||||
] [ipgui::get_guiparamspec -name "SDO_DEFAULT" -component $cc]
|
||||
|
||||
## Create and save the XGUI file
|
||||
ipx::create_xgui_files $cc
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Thu Dec 9 15:07:43 2021
|
||||
# Process ID: 3259
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_execution
|
||||
# Command line: vivado -mode batch -source spi_engine_execution_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_execution/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_execution/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source spi_engine_execution_ip.tcl
|
||||
@@ -0,0 +1,973 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Thu Dec 9 15:07:43 2021
|
||||
# Process ID: 3259
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_execution
|
||||
# Command line: vivado -mode batch -source spi_engine_execution_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_execution/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_execution/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source spi_engine_execution_ip.tcl
|
||||
# source ../../scripts/adi_env.tcl
|
||||
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
|
||||
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
|
||||
## if [info exists ::env(ADI_HDL_DIR)] {
|
||||
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
|
||||
## }
|
||||
## if [info exists ::env(ADI_GHDL_DIR)] {
|
||||
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
|
||||
## }
|
||||
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
|
||||
### variable auto_set_param_list
|
||||
### variable auto_set_param_list_overwritable
|
||||
### variable fpga_series_list
|
||||
### variable fpga_family_list
|
||||
### variable speed_grade_list
|
||||
### variable dev_package_list
|
||||
### variable xcvr_type_list
|
||||
### variable fpga_voltage_list
|
||||
### set auto_set_param_list { \
|
||||
### DEV_PACKAGE \
|
||||
### SPEED_GRADE \
|
||||
### FPGA_FAMILY \
|
||||
### FPGA_TECHNOLOGY }
|
||||
### set auto_set_param_list_overwritable { \
|
||||
### FPGA_VOLTAGE \
|
||||
### XCVR_TYPE }
|
||||
### set fpga_technology_list { \
|
||||
### { Unknown 0 } \
|
||||
### { 7series 1 } \
|
||||
### { ultrascale 2 } \
|
||||
### { ultrascale+ 3 }}
|
||||
### set fpga_family_list { \
|
||||
### { Unknown 0 } \
|
||||
### { artix 1 } \
|
||||
### { kintex 2 } \
|
||||
### { virtex 3 } \
|
||||
### { zynq 4 }}
|
||||
### set speed_grade_list { \
|
||||
### { Unknown 0 } \
|
||||
### { -1 10 } \
|
||||
### { -1L 11 } \
|
||||
### { -1H 12 } \
|
||||
### { -1HV 13 } \
|
||||
### { -1LV 14 } \
|
||||
### { -2 20 } \
|
||||
### { -2L 21 } \
|
||||
### { -2LV 22 } \
|
||||
### { -3 30 }}
|
||||
### set dev_package_list { \
|
||||
### { Unknown 0 } \
|
||||
### { rf 1 } \
|
||||
### { fl 2 } \
|
||||
### { ff 3 } \
|
||||
### { fb 4 } \
|
||||
### { hc 5 } \
|
||||
### { fh 6 } \
|
||||
### { cs 7 } \
|
||||
### { cp 8 } \
|
||||
### { ft 9 } \
|
||||
### { fg 10 } \
|
||||
### { sb 11 } \
|
||||
### { rb 12 } \
|
||||
### { rs 13 } \
|
||||
### { cl 14 } \
|
||||
### { sf 15 } \
|
||||
### { ba 16 } \
|
||||
### { fa 17 } \
|
||||
### { fs 18 } \
|
||||
### { fi 19 }}
|
||||
### set xcvr_type_list { \
|
||||
### { Unknown 0 } \
|
||||
### { GTPE2_NOT_SUPPORTED 1 } \
|
||||
### { GTXE2 2 } \
|
||||
### { GTHE2_NOT_SUPPORTED 3 } \
|
||||
### { GTZE2_NOT_SUPPORTED 4 } \
|
||||
### { GTHE3 5 } \
|
||||
### { GTYE3_NOT_SUPPORTED 6 } \
|
||||
### { GTRE4_NOT_SUPPORTED 7 } \
|
||||
### { GTHE4 8 } \
|
||||
### { GTYE4 9 } \
|
||||
### { GTME4_NOT_SUPPORTED 10}}
|
||||
### set fpga_voltage_list {0 5000} ;
|
||||
### proc adi_device_spec {cellpath param} {
|
||||
###
|
||||
### set list_pointer [string tolower $param]
|
||||
### set list_pointer [append list_pointer "_list"]
|
||||
###
|
||||
### upvar 1 $list_pointer $list_pointer
|
||||
###
|
||||
### set ip [get_bd_cells $cellpath]
|
||||
### set part [get_property PART [current_project]]
|
||||
###
|
||||
### switch -regexp -- $param {
|
||||
### FPGA_TECHNOLOGY {
|
||||
### switch -regexp -- $part {
|
||||
### ^xc7 {set series_name 7series}
|
||||
### ^xczu {set series_name ultrascale+}
|
||||
### ^xc.u.p {set series_name ultrascale+}
|
||||
### ^xc.u {set series_name ultrascale }
|
||||
### default {
|
||||
### puts "Undefined fpga technology for \"$part\"!"
|
||||
### exit -1
|
||||
### }
|
||||
### }
|
||||
### return "$series_name"
|
||||
### }
|
||||
### FPGA_FAMILY {
|
||||
### set fpga_family [get_property FAMILY $part]
|
||||
### foreach i $fpga_family_list {
|
||||
### regexp ^[lindex $i 0] $fpga_family matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### SPEED_GRADE {
|
||||
### set speed_grade [get_property SPEED $part]
|
||||
### return "$speed_grade"
|
||||
### }
|
||||
### DEV_PACKAGE {
|
||||
### set dev_package [get_property PACKAGE $part]
|
||||
### foreach i $dev_package_list {
|
||||
### regexp ^[lindex $i 0] $dev_package matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### XCVR_TYPE {
|
||||
### set matched ""
|
||||
### set dev_transcivers "none"
|
||||
### foreach x [list_property $part] {
|
||||
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
|
||||
### }
|
||||
### foreach i $xcvr_type_list {
|
||||
### regexp ^[lindex $i 0] $dev_transcivers matched
|
||||
### }
|
||||
### if { $matched eq "" } {
|
||||
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### FPGA_VOLTAGE {
|
||||
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
|
||||
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
|
||||
###
|
||||
### return "$fpga_voltage"
|
||||
### }
|
||||
### default {
|
||||
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
|
||||
### }
|
||||
### }
|
||||
### }
|
||||
## if {![info exists REQUIRED_VIVADO_VERSION]} {
|
||||
## set REQUIRED_VIVADO_VERSION "2019.1"
|
||||
## }
|
||||
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
|
||||
## set IGNORE_VERSION_CHECK 1
|
||||
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
|
||||
## set IGNORE_VERSION_CHECK 0
|
||||
## }
|
||||
## proc adi_ip_ttcl {ip_name ip_constr_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
|
||||
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_sim_ttcl {ip_name ip_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
|
||||
## set f [ipx::add_file $ip_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_bd {ip_name ip_bd_files} {
|
||||
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
|
||||
## if {$proj_filegroup == {}} {
|
||||
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
|
||||
## }
|
||||
##
|
||||
## foreach file $ip_bd_files {
|
||||
## set f [ipx::add_file $file $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type tclSource \
|
||||
## ] $f
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_infer_streaming_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_ip_infer_mm_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
|
||||
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency $port
|
||||
## if {$driver_value != {}} {
|
||||
## set_property DRIVER_VALUE $driver_value $port
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_set_bus_dependency {bus prefix dependency} {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
|
||||
## adi_set_ports_dependency $prefix $dependency 0
|
||||
## }
|
||||
## proc adi_add_port_map {bus phys logic} {
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## }
|
||||
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## adi_add_port_map $bus {*}$port_map
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
|
||||
## for {set i 0} {$i < $num} {incr i} {
|
||||
## set bus_name [format "%s%d" $bus_name_prefix $i]
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## if {$dependency ne ""} {
|
||||
## set bus_dependency [string map [list "{i}" $i] $dependency]
|
||||
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
|
||||
## }
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## lassign $port_map phys logic width width_dep
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
|
||||
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
|
||||
## if {$width_dep ne ""} {
|
||||
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
|
||||
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
|
||||
## set width_dep_r "(($width_dep) * $i)"
|
||||
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
|
||||
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
|
||||
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
|
||||
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
|
||||
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
|
||||
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
|
||||
## set_property display_name $clock_inf_name $clock_inf
|
||||
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
|
||||
## set_property physical_name $clock_signal_name $clock_map
|
||||
##
|
||||
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
|
||||
## set_property value $bus_inf_name $assoc_busif
|
||||
##
|
||||
## if { $reset_signal_name != "" } {
|
||||
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
|
||||
## set_property value $reset_signal_name $assoc_reset
|
||||
##
|
||||
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
|
||||
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
|
||||
## set_property display_name $reset_inf_name $reset_inf
|
||||
## set_property interface_mode $reset_signal_mode $reset_inf
|
||||
## set reset_map [ipx::add_port_map "RST" $reset_inf]
|
||||
## set_property physical_name $reset_signal_name $reset_map
|
||||
##
|
||||
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
|
||||
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
|
||||
## set_property value "ACTIVE_LOW" $reset_polarity
|
||||
## } else {
|
||||
## set_property value "ACTIVE_HIGH" $reset_polarity
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_add_core_dependencies {vlnvs} {
|
||||
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
|
||||
## foreach vlnv $vlnvs {
|
||||
## ipx::add_subcore $vlnv $file_group
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_create {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
## global ad_ghdl_dir
|
||||
## global REQUIRED_VIVADO_VERSION
|
||||
## global IGNORE_VERSION_CHECK
|
||||
##
|
||||
## set VIVADO_VERSION [version -short]
|
||||
## if {$IGNORE_VERSION_CHECK} {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## }
|
||||
## } else {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "ERROR: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
|
||||
## exit 2
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## create_project $ip_name . -force
|
||||
##
|
||||
## ## Load custom message severity definitions
|
||||
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
|
||||
##
|
||||
## set lib_dirs $ad_hdl_dir/library
|
||||
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
|
||||
## lappend lib_dirs $ad_ghdl_dir/library
|
||||
## }
|
||||
##
|
||||
## set_property ip_repo_paths $lib_dirs [current_fileset]
|
||||
## update_ip_catalog
|
||||
## }
|
||||
## proc adi_ip_files {ip_name ip_files} {
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## foreach m_file $ip_files {
|
||||
## if {[file extension $m_file] eq ".xdc"} {
|
||||
## add_files -norecurse -fileset constrs_1 $m_file
|
||||
## } else {
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
|
||||
## }
|
||||
## }
|
||||
## set_property "top" "$ip_name" $proj_fileset
|
||||
## }
|
||||
## proc adi_ip_properties_lite {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
##
|
||||
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
|
||||
##
|
||||
## set_property name $ip_name [ipx::current_core]
|
||||
##
|
||||
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
|
||||
## set_property company_url {http://www.analog.com} [ipx::current_core]
|
||||
##
|
||||
## set i_families ""
|
||||
## foreach i_part [get_parts] {
|
||||
## lappend i_families [get_property FAMILY $i_part]
|
||||
## }
|
||||
## set i_families [lsort -unique $i_families]
|
||||
## set s_families [get_property supported_families [ipx::current_core]]
|
||||
## foreach i_family $i_families {
|
||||
## set s_families "$s_families $i_family Production"
|
||||
## set s_families "$s_families $i_family Beta"
|
||||
## }
|
||||
## set_property supported_families $s_families [ipx::current_core]
|
||||
##
|
||||
## ipx::save_core [ipx::current_core]
|
||||
##
|
||||
## ipx::remove_all_bus_interface [ipx::current_core]
|
||||
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
|
||||
## foreach map $memory_maps {
|
||||
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
|
||||
## }
|
||||
##
|
||||
## ipx::update_checksums [ipx::current_core]
|
||||
## ipx::save_core [ipx::current_core]
|
||||
## }
|
||||
## proc adi_ip_properties {ip_name} {
|
||||
##
|
||||
## adi_ip_properties_lite $ip_name
|
||||
##
|
||||
## ipx::infer_bus_interface {\
|
||||
## s_axi_awvalid \
|
||||
## s_axi_awaddr \
|
||||
## s_axi_awprot \
|
||||
## s_axi_awready \
|
||||
## s_axi_wvalid \
|
||||
## s_axi_wdata \
|
||||
## s_axi_wstrb \
|
||||
## s_axi_wready \
|
||||
## s_axi_bvalid \
|
||||
## s_axi_bresp \
|
||||
##
|
||||
## s_axi_bready \
|
||||
## s_axi_arvalid \
|
||||
## s_axi_araddr \
|
||||
## s_axi_arprot \
|
||||
## s_axi_arready \
|
||||
## s_axi_rvalid \
|
||||
## s_axi_rdata \
|
||||
## s_axi_rresp \
|
||||
## s_axi_rready} \
|
||||
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
|
||||
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
|
||||
##
|
||||
## if {$raddr_width != $waddr_width} {
|
||||
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
|
||||
## set range 65536
|
||||
## } else {
|
||||
## if {$raddr_width >= 16} {
|
||||
## set range 65536
|
||||
## } else {
|
||||
## set range [expr 1 << $raddr_width]
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
## set_property range $range [ipx::get_address_blocks axi_lite \
|
||||
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
|
||||
## ipx::save_core
|
||||
## }
|
||||
## proc adi_init_bd_tcl {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## if { [file exists bd] } {
|
||||
## file delete -force bd
|
||||
## }
|
||||
## file mkdir bd
|
||||
##
|
||||
## set bd_tcl [open "bd/bd.tcl" w]
|
||||
##
|
||||
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
|
||||
## puts $bd_tcl "proc init {cellpath otherInfo} {"
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl ""
|
||||
## set auto_set_param ""
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
|
||||
## puts $bd_tcl $auto_set_param
|
||||
## }
|
||||
##
|
||||
## set auto_set_overwritable_param ""
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_overwritable_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_overwritable_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
|
||||
## puts $bd_tcl $auto_set_overwritable_param
|
||||
## }
|
||||
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
|
||||
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
|
||||
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set parent_dir \"../\""
|
||||
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
|
||||
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
|
||||
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " break"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " append parent_dir \"../\""
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## close $bd_tcl
|
||||
##
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
|
||||
##
|
||||
## set local_mk [open "temporary_case_dependencies.mk" w]
|
||||
## seek $local_mk 0 start
|
||||
## puts $local_mk "CLEAN_TARGET += bd"
|
||||
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
|
||||
## close $local_mk
|
||||
## }
|
||||
## proc adi_add_auto_fpga_spec_params {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_device_spec_param {ip_param} {
|
||||
##
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## set list_pointer [string tolower $ip_param]
|
||||
## set list_pointer [append list_pointer "_list"]
|
||||
##
|
||||
## global $list_pointer
|
||||
##
|
||||
## # set j 1D list from the original list
|
||||
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
|
||||
##
|
||||
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
|
||||
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "range_long" \
|
||||
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
|
||||
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## } else {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "pairs" \
|
||||
## "value_validation_pairs" $j ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## }
|
||||
##
|
||||
## # FPGA info grup
|
||||
## set info_group_name "FPGA info"
|
||||
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
|
||||
## if { [string trim $info_group] eq "" } {
|
||||
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
|
||||
## -parent $page0 -display_name $info_group_name]
|
||||
## }
|
||||
##
|
||||
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
|
||||
## set_property -dict [list "widget" "comboBox" ] $p
|
||||
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
|
||||
## }
|
||||
## proc adi_if_define {name} {
|
||||
##
|
||||
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
|
||||
## ipx::create_bus_definition analog.com interface $name 1.0
|
||||
##
|
||||
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
|
||||
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
|
||||
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
|
||||
##
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## }
|
||||
## proc adi_if_ports {dir width name {type none}} {
|
||||
##
|
||||
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
|
||||
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
|
||||
## set_property master_presence required $m_intf
|
||||
## set_property slave_presence required $m_intf
|
||||
## set_property master_width $width $m_intf
|
||||
## set_property slave_width $width $m_intf
|
||||
##
|
||||
## set m_dir "in"
|
||||
## set s_dir "out"
|
||||
## if {$dir eq "output"} {
|
||||
## set m_dir "out"
|
||||
## set s_dir "in"
|
||||
## }
|
||||
##
|
||||
## set_property master_direction $m_dir $m_intf
|
||||
## set_property slave_direction $s_dir $m_intf
|
||||
##
|
||||
## if {$type ne "none"} {
|
||||
## set_property is_${type} true $m_intf
|
||||
## }
|
||||
##
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## }
|
||||
## proc adi_if_infer_bus {if_name mode name maps} {
|
||||
##
|
||||
## ipx::add_bus_interface $name [ipx::current_core]
|
||||
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
|
||||
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
|
||||
## set_property interface_mode $mode $m_bus_if
|
||||
##
|
||||
## foreach map $maps {
|
||||
## set m_maps [regexp -all -inline {\S+} $map]
|
||||
## lassign $m_maps p_name p_map
|
||||
## ipx::add_port_map $p_name $m_bus_if
|
||||
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
|
||||
## }
|
||||
## }
|
||||
# adi_ip_create spi_engine_execution
|
||||
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
|
||||
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1343} -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1306} -new_severity WARNING
|
||||
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
|
||||
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
|
||||
## set_msg_config -id {Synth 8-3331} -new_severity INFO
|
||||
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
|
||||
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
|
||||
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
|
||||
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/spi_engine/spi_engine_execution'.)
|
||||
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
|
||||
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
|
||||
# adi_ip_files spi_engine_execution [list \
|
||||
# "spi_engine_execution.v" \
|
||||
# ]
|
||||
# adi_ip_properties_lite spi_engine_execution
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'sleep_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'sleep_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'cs_sleep_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'cs_sleep_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'cs_sleep_counter2' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'cs_sleep_counter2' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'bit_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'transfer_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'transfer_counter' has a dependency on the module local parameter or undefined parameter 'BIT_COUNTER_WIDTH'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'exec_transfer_cmd' has a dependency on the module local parameter or undefined parameter 'CMD_TRANSFER'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'exec_write_cmd' has a dependency on the module local parameter or undefined parameter 'CMD_WRITE'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'exec_chipselect_cmd' has a dependency on the module local parameter or undefined parameter 'CMD_CHIPSELECT'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'exec_misc_cmd' has a dependency on the module local parameter or undefined parameter 'CMD_MISC'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'exec_sync_cmd' has a dependency on the module local parameter or undefined parameter 'MISC_SYNC'.
|
||||
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'cs_active_s' has a dependency on the module local parameter or undefined parameter 'CMD_CHIPSELECT'.
|
||||
INFO: [IP_Flow 19-4821] For module 'spi_engine_execution', parameter 'SDO_DEFAULT' is inferred to be bitString format.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_ready' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_valid' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'cmd' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'sdi_data' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'sdo_data' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'sync' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
|
||||
INFO: [IP_Flow 19-5151] The Range '7:0' is present in all ports of the interface 'interface_jesd204_tx_status'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_0' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_1' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_2' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_3' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_4' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_5' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_6' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port state on bus interface abstraction jesd204_tx_status_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_jesd204_tx_status_7' of definition 'analog.com:interface:jesd204_tx_status:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5150] The Range '((NUM_OF_SDI * DATA_WIDTH) - 1):0' is present in all ports of the interface 'sdi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5150] The Range '(DATA_WIDTH - 1):0' is present in all ports of the interface 'sdo'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_WR_EN on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_WR_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port ENABLE on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port MEM_RESET on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port ENABLED on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port SYNC_DATA on bus interface abstraction spi_engine_offload_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_spi_engine_offload_ctrl' of definition 'analog.com:interface:spi_engine_offload_ctrl:1.0' (from User Repositories).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_spi_master' of definition 'analog.com:interface:spi_master:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port CMD_DATA on bus interface abstraction spi_engine_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port SDO_READY on bus interface abstraction spi_engine_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port SDO_VALID on bus interface abstraction spi_engine_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port SDI_READY on bus interface abstraction spi_engine_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port SDI_VALID on bus interface abstraction spi_engine_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port SYNC_DATA on bus interface abstraction spi_engine_ctrl_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'interface_spi_engine_ctrl' of definition 'analog.com:interface:spi_engine_ctrl:1.0' (from User Repositories).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data' and definition port 'DATA'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sdi': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdi_data_valid' and definition port 'DATA'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sdo': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data_ready' and definition port 'DATA'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_ready': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'SYNC'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_valid': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'cmd_valid' and definition port 'VALID'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'cmd': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'cmd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sdi_data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sdo_data_valid' and definition port 'VALID'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_data': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sdo_data': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sync': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'sync': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_0': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_1': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_2': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_3': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_4': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_5': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_6': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'sync' and definition port 'sync'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_jesd204_tx_status_7': A port map to the required logical port "state" of the bus abstraction "analog.com:interface:jesd204_tx_status_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "CMD_WR_EN" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "CMD_WR_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "ENABLE" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "MEM_RESET" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "ENABLED" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_offload_ctrl': A port map to the required logical port "SYNC_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "CMD_DATA" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDO_READY" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDO_VALID" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDI_READY" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SDI_VALID" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'interface_spi_engine_ctrl': A port map to the required logical port "SYNC_DATA" of the bus abstraction "analog.com:interface:spi_engine_ctrl_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
# ipx::remove_all_bus_interface [ipx::current_core]
|
||||
# adi_add_bus "ctrl" "slave" \
|
||||
# "analog.com:interface:spi_engine_ctrl_rtl:1.0" \
|
||||
# "analog.com:interface:spi_engine_ctrl:1.0" \
|
||||
# {
|
||||
# {"cmd_ready" "CMD_READY"} \
|
||||
# {"cmd_valid" "CMD_VALID"} \
|
||||
# {"cmd" "CMD_DATA"} \
|
||||
# {"sdo_data_ready" "SDO_READY"} \
|
||||
# {"sdo_data_valid" "SDO_VALID"} \
|
||||
# {"sdo_data" "SDO_DATA"} \
|
||||
# {"sdi_data_ready" "SDI_READY"} \
|
||||
# {"sdi_data_valid" "SDI_VALID"} \
|
||||
# {"sdi_data" "SDI_DATA"} \
|
||||
# {"sync_ready" "SYNC_READY"} \
|
||||
# {"sync_valid" "SYNC_VALID"} \
|
||||
# {"sync" "SYNC_DATA"} \
|
||||
# }
|
||||
# adi_add_bus_clock "clk" "ctrl" "resetn"
|
||||
# adi_add_bus "spi" "master" \
|
||||
# "analog.com:interface:spi_master_rtl:1.0" \
|
||||
# "analog.com:interface:spi_master:1.0" \
|
||||
# {
|
||||
# {"sclk" "SCLK"} \
|
||||
# {"sdi" "SDI"} \
|
||||
# {"sdo" "SDO"} \
|
||||
# {"sdo_t" "SDO_T"} \
|
||||
# {"three_wire" "THREE_WIRE"} \
|
||||
# {"cs" "CS"} \
|
||||
# }
|
||||
# adi_add_bus_clock "clk" "spi" "resetn"
|
||||
# set cc [ipx::current_core]
|
||||
# set_property -dict [list \
|
||||
# "value_validation_type" "range_long" \
|
||||
# "value_validation_range_minimum" "8" \
|
||||
# "value_validation_range_maximum" "256" \
|
||||
# ] \
|
||||
# [ipx::get_user_parameters DATA_WIDTH -of_objects $cc]
|
||||
# set_property -dict [list \
|
||||
# "value_validation_type" "range_long" \
|
||||
# "value_validation_range_minimum" "1" \
|
||||
# "value_validation_range_maximum" "32" \
|
||||
# ] \
|
||||
# [ipx::get_user_parameters NUM_OF_CS -of_objects $cc]
|
||||
# set_property -dict [list \
|
||||
# "value_validation_type" "range_long" \
|
||||
# "value_validation_range_minimum" "1" \
|
||||
# "value_validation_range_maximum" "8" \
|
||||
# ] \
|
||||
# [ipx::get_user_parameters NUM_OF_SDI -of_objects $cc]
|
||||
# set_property -dict [list \
|
||||
# "value_validation_type" "list" \
|
||||
# "value_validation_list" "0 1 2 3" \
|
||||
# ] \
|
||||
# [ipx::get_user_parameters DEFAULT_SPI_CFG -of_objects $cc]
|
||||
# set_property -dict [list \
|
||||
# "value_validation_type" "list" \
|
||||
# "value_validation_range_minimum" "0" \
|
||||
# "value_validation_range_maximum" "255" \
|
||||
# ] \
|
||||
# [ipx::get_user_parameters DEFAULT_CLK_DIV -of_objects $cc]
|
||||
# set_property -dict [list \
|
||||
# "value_validation_type" "list" \
|
||||
# "value_validation_list" "0 1" \
|
||||
# ] \
|
||||
# [ipx::get_user_parameters SDO_DEFAULT -of_objects $cc]
|
||||
# set_property -dict [list \
|
||||
# "value_format" "bool" \
|
||||
# "value" "false" \
|
||||
# ] \
|
||||
# [ipx::get_user_parameters SDI_DELAY -of_objects $cc]
|
||||
# set_property -dict [list \
|
||||
# "value_format" "bool" \
|
||||
# "value" "false" \
|
||||
# ] \
|
||||
# [ipx::get_hdl_parameters SDI_DELAY -of_objects $cc]
|
||||
# ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
# ipx::save_core [ipx::current_core]
|
||||
# ipgui::add_page -name {SPI Engine execution} -component [ipx::current_core] -display_name {AXI SPI Engine execution}
|
||||
# set page0 [ipgui::get_pagespec -name "SPI Engine execution" -component $cc]
|
||||
# set general_group [ipgui::add_group -name "General Configuration" -component $cc \
|
||||
# -parent $page0 -display_name "General Configuration" ]
|
||||
# ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group
|
||||
# set_property -dict [list \
|
||||
# "display_name" "Parallel data width" \
|
||||
# "tooltip" "\[DATA_WIDTH\] Define the data interface width"
|
||||
# ] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc]
|
||||
# ipgui::add_param -name "NUM_OF_CS" -component $cc -parent $general_group
|
||||
# set_property -dict [list \
|
||||
# "display_name" "Number of CSN lines" \
|
||||
# "tooltip" "\[NUM_OF_CS\] Define the number of chip select lines" \
|
||||
# ] [ipgui::get_guiparamspec -name "NUM_OF_CS" -component $cc]
|
||||
# ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group
|
||||
# set_property -dict [list \
|
||||
# "display_name" "Number of MISO lines" \
|
||||
# "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \
|
||||
# ] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc]
|
||||
# set spi_config_group [ipgui::add_group -name "SPI Configuration" -component $cc \
|
||||
# -parent $page0 -display_name "SPI Configuration" ]
|
||||
# ipgui::add_param -name "DEFAULT_SPI_CFG" -component $cc -parent $spi_config_group
|
||||
# set_property -dict [list \
|
||||
# "widget" "comboBox" \
|
||||
# "display_name" "Default SPI mode" \
|
||||
# "tooltip" "\[DEFAULT_SPI_CFG\] Define the default SPI configuration, bit 1 defines CPOL, bit 0 defines CPHA"
|
||||
# ] [ipgui::get_guiparamspec -name "DEFAULT_SPI_CFG" -component $cc]
|
||||
# ipgui::add_param -name "DEFAULT_CLK_DIV" -component $cc -parent $spi_config_group
|
||||
# set_property -dict [list \
|
||||
# "display_name" "Default SCLK divider" \
|
||||
# "tooltip" "\[DEFAULT_CLK_DIV\] Define the default SCLK divider, fSCLK = fCoreClk / DEFAULT_CLK_DIV + 1"
|
||||
# ] [ipgui::get_guiparamspec -name "DEFAULT_CLK_DIV" -component $cc]
|
||||
# set mosi_miso_config_group [ipgui::add_group -name "MOSI/MISO Configuration" -component $cc \
|
||||
# -parent $page0 -display_name "MOSI/MISO Configuration" ]
|
||||
# ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $mosi_miso_config_group
|
||||
WARNING: [IP_Flow 19-465] param 'NUM_OF_SDI' already exists. Ignoring.
|
||||
# set_property -dict [list \
|
||||
# "display_name" "Number of MISO" \
|
||||
# "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines"
|
||||
# ] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc]
|
||||
# ipgui::add_param -name "SDI_DELAY" -component $cc -parent $mosi_miso_config_group
|
||||
# set_property -dict [list \
|
||||
# "display_name" "Delay MISO latching" \
|
||||
# "tooltip" "\[SDI_DELAY\] Delay the MISO latching to the next consecutive SCLK edge"
|
||||
# ] [ipgui::get_guiparamspec -name "SDI_DELAY" -component $cc]
|
||||
# ipgui::add_param -name "SDO_DEFAULT" -component $cc -parent $mosi_miso_config_group
|
||||
# set_property -dict [list \
|
||||
# "widget" "comboBox" \
|
||||
# "display_name" "MOSI default level" \
|
||||
# "tooltip" "\[SDO_DEFAULT\] Define the default voltage level on MOSI"
|
||||
# ] [ipgui::get_guiparamspec -name "SDO_DEFAULT" -component $cc]
|
||||
# ipx::create_xgui_files $cc
|
||||
# ipx::save_core [ipx::current_core]
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:07:50 2021...
|
||||
@@ -0,0 +1,131 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set SPI_Engine_execution [ipgui::add_page $IPINST -name "SPI Engine execution" -display_name {AXI SPI Engine execution}]
|
||||
#Adding Group
|
||||
set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${SPI_Engine_execution}]
|
||||
set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${General_Configuration}]
|
||||
set_property tooltip {[DATA_WIDTH] Define the data interface width} ${DATA_WIDTH}
|
||||
set NUM_OF_CS [ipgui::add_param $IPINST -name "NUM_OF_CS" -parent ${General_Configuration}]
|
||||
set_property tooltip {[NUM_OF_CS] Define the number of chip select lines} ${NUM_OF_CS}
|
||||
set NUM_OF_SDI [ipgui::add_param $IPINST -name "NUM_OF_SDI" -parent ${General_Configuration}]
|
||||
set_property tooltip {[NUM_OF_SDI] Define the number of MISO lines} ${NUM_OF_SDI}
|
||||
|
||||
#Adding Group
|
||||
set SPI_Configuration [ipgui::add_group $IPINST -name "SPI Configuration" -parent ${SPI_Engine_execution}]
|
||||
set DEFAULT_SPI_CFG [ipgui::add_param $IPINST -name "DEFAULT_SPI_CFG" -parent ${SPI_Configuration} -widget comboBox]
|
||||
set_property tooltip {[DEFAULT_SPI_CFG] Define the default SPI configuration, bit 1 defines CPOL, bit 0 defines CPHA} ${DEFAULT_SPI_CFG}
|
||||
set DEFAULT_CLK_DIV [ipgui::add_param $IPINST -name "DEFAULT_CLK_DIV" -parent ${SPI_Configuration}]
|
||||
set_property tooltip {[DEFAULT_CLK_DIV] Define the default SCLK divider, fSCLK = fCoreClk / DEFAULT_CLK_DIV + 1} ${DEFAULT_CLK_DIV}
|
||||
|
||||
#Adding Group
|
||||
set MOSI/MISO_Configuration [ipgui::add_group $IPINST -name "MOSI/MISO Configuration" -parent ${SPI_Engine_execution}]
|
||||
set SDI_DELAY [ipgui::add_param $IPINST -name "SDI_DELAY" -parent ${MOSI/MISO_Configuration}]
|
||||
set_property tooltip {[SDI_DELAY] Delay the MISO latching to the next consecutive SCLK edge} ${SDI_DELAY}
|
||||
set SDO_DEFAULT [ipgui::add_param $IPINST -name "SDO_DEFAULT" -parent ${MOSI/MISO_Configuration} -widget comboBox]
|
||||
set_property tooltip {[SDO_DEFAULT] Define the default voltage level on MOSI} ${SDO_DEFAULT}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to validate DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEFAULT_CLK_DIV { PARAM_VALUE.DEFAULT_CLK_DIV } {
|
||||
# Procedure called to update DEFAULT_CLK_DIV when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEFAULT_CLK_DIV { PARAM_VALUE.DEFAULT_CLK_DIV } {
|
||||
# Procedure called to validate DEFAULT_CLK_DIV
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEFAULT_SPI_CFG { PARAM_VALUE.DEFAULT_SPI_CFG } {
|
||||
# Procedure called to update DEFAULT_SPI_CFG when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEFAULT_SPI_CFG { PARAM_VALUE.DEFAULT_SPI_CFG } {
|
||||
# Procedure called to validate DEFAULT_SPI_CFG
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_CS { PARAM_VALUE.NUM_OF_CS } {
|
||||
# Procedure called to update NUM_OF_CS when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_CS { PARAM_VALUE.NUM_OF_CS } {
|
||||
# Procedure called to validate NUM_OF_CS
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to update NUM_OF_SDI when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to validate NUM_OF_SDI
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SDI_DELAY { PARAM_VALUE.SDI_DELAY } {
|
||||
# Procedure called to update SDI_DELAY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SDI_DELAY { PARAM_VALUE.SDI_DELAY } {
|
||||
# Procedure called to validate SDI_DELAY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SDO_DEFAULT { PARAM_VALUE.SDO_DEFAULT } {
|
||||
# Procedure called to update SDO_DEFAULT when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SDO_DEFAULT { PARAM_VALUE.SDO_DEFAULT } {
|
||||
# Procedure called to validate SDO_DEFAULT
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_CS { MODELPARAM_VALUE.NUM_OF_CS PARAM_VALUE.NUM_OF_CS } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_CS}] ${MODELPARAM_VALUE.NUM_OF_CS}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEFAULT_SPI_CFG { MODELPARAM_VALUE.DEFAULT_SPI_CFG PARAM_VALUE.DEFAULT_SPI_CFG } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEFAULT_SPI_CFG}] ${MODELPARAM_VALUE.DEFAULT_SPI_CFG}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEFAULT_CLK_DIV { MODELPARAM_VALUE.DEFAULT_CLK_DIV PARAM_VALUE.DEFAULT_CLK_DIV } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEFAULT_CLK_DIV}] ${MODELPARAM_VALUE.DEFAULT_CLK_DIV}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_SDI { MODELPARAM_VALUE.NUM_OF_SDI PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_SDI}] ${MODELPARAM_VALUE.NUM_OF_SDI}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SDO_DEFAULT { MODELPARAM_VALUE.SDO_DEFAULT PARAM_VALUE.SDO_DEFAULT } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SDO_DEFAULT}] ${MODELPARAM_VALUE.SDO_DEFAULT}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SDI_DELAY { MODELPARAM_VALUE.SDI_DELAY PARAM_VALUE.SDI_DELAY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SDI_DELAY}] ${MODELPARAM_VALUE.SDI_DELAY}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user