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josh
2023-03-18 15:35:53 +08:00
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adi_library/util_cic/Makefile
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := util_cic
GENERIC_DEPS += cic_comb.v
GENERIC_DEPS += cic_int.v
XILINX_DEPS += util_cic_ip.tcl
include ../scripts/library.mk
adi_library/util_cic/cic_comb.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cic_comb #(
parameter DATA_WIDTH = 32,
parameter SEQ = 1,
parameter STAGE_WIDTH = 1,
parameter NUM_STAGES = 1
) (
input clk,
input ce,
input [NUM_STAGES-1:0] enable,
input [DATA_WIDTH-1:0] data_in,
output [DATA_WIDTH-1:0] data_out
);
reg [SEQ-1:0] storage[0:DATA_WIDTH-1];
reg [DATA_WIDTH-1:0] state = 'h00;
reg [2:0] counter = 'h00;
reg active = 1'b0;
integer x;
initial begin
for (x = 0; x < DATA_WIDTH; x = x + 1) begin
storage[x] = 'h00;
end
end
generate if (SEQ != 1) begin
always @(posedge clk) begin
if (ce == 1'b1) begin
counter <= SEQ-1;
active <= 1'b1;
end else if (active == 1'b1) begin
counter <= counter - 1'b1;
if (counter == 'h1) begin
active <= 1'b0;
end
end
end
end
endgenerate
wire [DATA_WIDTH-1:0] mask;
reg [DATA_WIDTH-1:0] data_in_seq;
wire [DATA_WIDTH-1:0] storage_out;
wire [DATA_WIDTH-1:0] diff = (data_in_seq | ~mask) - (storage_out & mask);
always @(*) begin
if (ce == 1'b1) begin
data_in_seq <= data_in;
end else begin
data_in_seq <= SEQ != 1 ? state : 'h00;
end
end
generate
genvar i, j;
for (j = 0; j < NUM_STAGES; j = j + 1) begin
localparam k = NUM_STAGES - j - 1;
localparam H = DATA_WIDTH - STAGE_WIDTH * j - 1;
localparam L = k == 0 ? 0 : DATA_WIDTH - STAGE_WIDTH * (j+1);
assign mask[H:L] = {{H-L{1'b1}},k != 0 ? enable[k] : 1'b1};
for (i = L; i <= H; i = i + 1) begin: shift_r
always @(posedge clk) begin
if (enable[k] == 1'b1 && (ce == 1'b1 || active == 1'b1)) begin
if (SEQ > 1) begin
storage[i] <= {storage[i][SEQ-2:0],data_in_seq[i]};
end else begin
storage[i] <= data_in_seq[i];
end
end
end
assign storage_out[i] = storage[i][SEQ-1];
end
always @(posedge clk) begin
if (enable[k] == 1'b1 && (ce == 1'b1 || active == 1'b1)) begin
state[H:L] <= diff[H:L];
end
end
end
endgenerate
assign data_out = state;
endmodule
adi_library/util_cic/cic_int.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cic_int #(
parameter DATA_WIDTH = 12,
parameter STAGE_WIDTH = 1,
parameter NUM_STAGES = 1
) (
input clk,
input [NUM_STAGES-1:0] ce,
input [DATA_WIDTH-1:0] data_in,
output [DATA_WIDTH-1:0] data_out
);
reg [DATA_WIDTH-1:0] state = 'h00;
wire [DATA_WIDTH-1:0] sum;
wire [DATA_WIDTH-1:0] mask;
assign data_out = state;
assign sum = (data_in & mask) + (state & mask);
generate
genvar i;
for (i = 0; i < NUM_STAGES; i = i + 1) begin
localparam j = NUM_STAGES - i - 1;
localparam H = DATA_WIDTH - STAGE_WIDTH * i - 1;
localparam L = j == 0 ? 0 : DATA_WIDTH - STAGE_WIDTH * (i+1);
assign mask[H:L] = {{H-L{1'b1}},j != 0 ? ce[j] : 1'b1};
always @(posedge clk) begin
if (ce[j] == 1'b1) begin
state[H:L] <= sum[H:L];
end
end
end
endgenerate
endmodule
adi_library/util_cic/component.xml
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adi_library/util_cic/util_cic.cache/wt/project.wpc
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adi_library/util_cic/util_cic.hw/util_cic.lpr
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adi_library/util_cic/util_cic.xpr
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<?xml version="1.0" encoding="UTF-8"?>
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</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/cic_comb.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/cic_int.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="cic_comb"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="1"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
<MsgAttr Name="StringsToMatch" Val="features"/>
<MsgAttr Name="StringsToMatch" Val="should"/>
<MsgAttr Name="StringsToMatch" Val="NOT"/>
<MsgAttr Name="StringsToMatch" Val="be"/>
<MsgAttr Name="StringsToMatch" Val="used"/>
<MsgAttr Name="StringsToMatch" Val="in"/>
<MsgAttr Name="StringsToMatch" Val="production"/>
<MsgAttr Name="StringsToMatch" Val="systems."/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Place 30-73"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="10"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val=""/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="11"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1343"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="2"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1306"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="3"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ERROR"/>
<MsgAttr Name="Id" Val="BD 41-1276"/>
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="4"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="5"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="6"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="7"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Synth 8-3331"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
<BootPmcSettings Version="1" Minor="0">
<Parameters>
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
</Parameters>
</BootPmcSettings>
</Project>
adi_library/util_cic/util_cic_ip.log
+689
View File
@@ -0,0 +1,689 @@
****** Vivado v2019.1.3 (64-bit)
**** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
**** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
source util_cic_ip.tcl
# source ../scripts/adi_env.tcl
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
## if [info exists ::env(ADI_HDL_DIR)] {
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
## }
## if [info exists ::env(ADI_GHDL_DIR)] {
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
## }
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
### variable auto_set_param_list
### variable auto_set_param_list_overwritable
### variable fpga_series_list
### variable fpga_family_list
### variable speed_grade_list
### variable dev_package_list
### variable xcvr_type_list
### variable fpga_voltage_list
### set auto_set_param_list { \
### DEV_PACKAGE \
### SPEED_GRADE \
### FPGA_FAMILY \
### FPGA_TECHNOLOGY }
### set auto_set_param_list_overwritable { \
### FPGA_VOLTAGE \
### XCVR_TYPE }
### set fpga_technology_list { \
### { Unknown 0 } \
### { 7series 1 } \
### { ultrascale 2 } \
### { ultrascale+ 3 }}
### set fpga_family_list { \
### { Unknown 0 } \
### { artix 1 } \
### { kintex 2 } \
### { virtex 3 } \
### { zynq 4 }}
### set speed_grade_list { \
### { Unknown 0 } \
### { -1 10 } \
### { -1L 11 } \
### { -1H 12 } \
### { -1HV 13 } \
### { -1LV 14 } \
### { -2 20 } \
### { -2L 21 } \
### { -2LV 22 } \
### { -3 30 }}
### set dev_package_list { \
### { Unknown 0 } \
### { rf 1 } \
### { fl 2 } \
### { ff 3 } \
### { fb 4 } \
### { hc 5 } \
### { fh 6 } \
### { cs 7 } \
### { cp 8 } \
### { ft 9 } \
### { fg 10 } \
### { sb 11 } \
### { rb 12 } \
### { rs 13 } \
### { cl 14 } \
### { sf 15 } \
### { ba 16 } \
### { fa 17 } \
### { fs 18 } \
### { fi 19 }}
### set xcvr_type_list { \
### { Unknown 0 } \
### { GTPE2_NOT_SUPPORTED 1 } \
### { GTXE2 2 } \
### { GTHE2_NOT_SUPPORTED 3 } \
### { GTZE2_NOT_SUPPORTED 4 } \
### { GTHE3 5 } \
### { GTYE3_NOT_SUPPORTED 6 } \
### { GTRE4_NOT_SUPPORTED 7 } \
### { GTHE4 8 } \
### { GTYE4 9 } \
### { GTME4_NOT_SUPPORTED 10}}
### set fpga_voltage_list {0 5000} ;
### proc adi_device_spec {cellpath param} {
###
### set list_pointer [string tolower $param]
### set list_pointer [append list_pointer "_list"]
###
### upvar 1 $list_pointer $list_pointer
###
### set ip [get_bd_cells $cellpath]
### set part [get_property PART [current_project]]
###
### switch -regexp -- $param {
### FPGA_TECHNOLOGY {
### switch -regexp -- $part {
### ^xc7 {set series_name 7series}
### ^xczu {set series_name ultrascale+}
### ^xc.u.p {set series_name ultrascale+}
### ^xc.u {set series_name ultrascale }
### default {
### puts "Undefined fpga technology for \"$part\"!"
### exit -1
### }
### }
### return "$series_name"
### }
### FPGA_FAMILY {
### set fpga_family [get_property FAMILY $part]
### foreach i $fpga_family_list {
### regexp ^[lindex $i 0] $fpga_family matched
### }
### return "$matched"
### }
### SPEED_GRADE {
### set speed_grade [get_property SPEED $part]
### return "$speed_grade"
### }
### DEV_PACKAGE {
### set dev_package [get_property PACKAGE $part]
### foreach i $dev_package_list {
### regexp ^[lindex $i 0] $dev_package matched
### }
### return "$matched"
### }
### XCVR_TYPE {
### set matched ""
### set dev_transcivers "none"
### foreach x [list_property $part] {
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
### }
### foreach i $xcvr_type_list {
### regexp ^[lindex $i 0] $dev_transcivers matched
### }
### if { $matched eq "" } {
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
### }
### return "$matched"
### }
### FPGA_VOLTAGE {
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
###
### return "$fpga_voltage"
### }
### default {
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
### }
### }
### }
## if {![info exists REQUIRED_VIVADO_VERSION]} {
## set REQUIRED_VIVADO_VERSION "2019.1"
## }
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
## set IGNORE_VERSION_CHECK 1
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
## set IGNORE_VERSION_CHECK 0
## }
## proc adi_ip_ttcl {ip_name ip_constr_files} {
##
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
## set_property -dict [list \
## type ttcl \
## ] $f
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
## }
## proc adi_ip_sim_ttcl {ip_name ip_files} {
##
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
## set f [ipx::add_file $ip_files $proj_filegroup]
## set_property -dict [list \
## type ttcl \
## ] $f
## ipx::reorder_files -front $ip_files $proj_filegroup
## }
## proc adi_ip_bd {ip_name ip_bd_files} {
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
## if {$proj_filegroup == {}} {
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
## }
##
## foreach file $ip_bd_files {
## set f [ipx::add_file $file $proj_filegroup]
## set_property -dict [list \
## type tclSource \
## ] $f
## }
## }
## proc adi_ip_infer_streaming_interfaces {ip_name} {
##
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
##
## }
## proc adi_ip_infer_mm_interfaces {ip_name} {
##
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
##
## }
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
## set_property ENABLEMENT_DEPENDENCY $dependency $port
## if {$driver_value != {}} {
## set_property DRIVER_VALUE $driver_value $port
## }
## }
## }
## proc adi_set_bus_dependency {bus prefix dependency} {
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
## adi_set_ports_dependency $prefix $dependency 0
## }
## proc adi_add_port_map {bus phys logic} {
## set map [ipx::add_port_map $phys $bus]
## set_property "PHYSICAL_NAME" $phys $map
## set_property "LOGICAL_NAME" $logic $map
## }
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
##
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
## set_property "BUS_TYPE_VLNV" $bus_type $bus
## set_property "INTERFACE_MODE" $mode $bus
##
## foreach port_map $port_maps {
## adi_add_port_map $bus {*}$port_map
## }
## }
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
## for {set i 0} {$i < $num} {incr i} {
## set bus_name [format "%s%d" $bus_name_prefix $i]
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
##
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
## set_property "BUS_TYPE_VLNV" $bus_type $bus
## set_property "INTERFACE_MODE" $mode $bus
##
## if {$dependency ne ""} {
## set bus_dependency [string map [list "{i}" $i] $dependency]
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
## }
##
## foreach port_map $port_maps {
## lassign $port_map phys logic width width_dep
## set map [ipx::add_port_map $phys $bus]
## set_property "PHYSICAL_NAME" $phys $map
## set_property "LOGICAL_NAME" $logic $map
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
## if {$width_dep ne ""} {
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
## set width_dep_r "(($width_dep) * $i)"
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
## }
## }
## }
## }
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
## set_property display_name $clock_inf_name $clock_inf
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
## set_property physical_name $clock_signal_name $clock_map
##
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
## set_property value $bus_inf_name $assoc_busif
##
## if { $reset_signal_name != "" } {
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
## set_property value $reset_signal_name $assoc_reset
##
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
## set_property display_name $reset_inf_name $reset_inf
## set_property interface_mode $reset_signal_mode $reset_inf
## set reset_map [ipx::add_port_map "RST" $reset_inf]
## set_property physical_name $reset_signal_name $reset_map
##
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
## set_property value "ACTIVE_LOW" $reset_polarity
## } else {
## set_property value "ACTIVE_HIGH" $reset_polarity
## }
## }
## }
## proc adi_ip_add_core_dependencies {vlnvs} {
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
## foreach vlnv $vlnvs {
## ipx::add_subcore $vlnv $file_group
## }
## }
## }
## proc adi_ip_create {ip_name} {
##
## global ad_hdl_dir
## global ad_ghdl_dir
## global REQUIRED_VIVADO_VERSION
## global IGNORE_VERSION_CHECK
##
## set VIVADO_VERSION [version -short]
## if {$IGNORE_VERSION_CHECK} {
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
## puts -nonewline "got $VIVADO_VERSION.\n"
## }
## } else {
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
## puts -nonewline "ERROR: vivado version mismatch; "
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
## puts -nonewline "got $VIVADO_VERSION.\n"
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
## exit 2
## }
## }
##
## create_project $ip_name . -force
##
## ## Load custom message severity definitions
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
##
## set lib_dirs $ad_hdl_dir/library
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
## lappend lib_dirs $ad_ghdl_dir/library
## }
##
## set_property ip_repo_paths $lib_dirs [current_fileset]
## update_ip_catalog
## }
## proc adi_ip_files {ip_name ip_files} {
## set proj_fileset [get_filesets sources_1]
## foreach m_file $ip_files {
## if {[file extension $m_file] eq ".xdc"} {
## add_files -norecurse -fileset constrs_1 $m_file
## } else {
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
## }
## }
## set_property "top" "$ip_name" $proj_fileset
## }
## proc adi_ip_properties_lite {ip_name} {
##
## global ad_hdl_dir
##
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
##
## set_property name $ip_name [ipx::current_core]
##
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
## set_property company_url {http://www.analog.com} [ipx::current_core]
##
## set i_families ""
## foreach i_part [get_parts] {
## lappend i_families [get_property FAMILY $i_part]
## }
## set i_families [lsort -unique $i_families]
## set s_families [get_property supported_families [ipx::current_core]]
## foreach i_family $i_families {
## set s_families "$s_families $i_family Production"
## set s_families "$s_families $i_family Beta"
## }
## set_property supported_families $s_families [ipx::current_core]
##
## ipx::save_core [ipx::current_core]
##
## ipx::remove_all_bus_interface [ipx::current_core]
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
## foreach map $memory_maps {
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
## }
##
## ipx::update_checksums [ipx::current_core]
## ipx::save_core [ipx::current_core]
## }
## proc adi_ip_properties {ip_name} {
##
## adi_ip_properties_lite $ip_name
##
## ipx::infer_bus_interface {\
## s_axi_awvalid \
## s_axi_awaddr \
## s_axi_awprot \
## s_axi_awready \
## s_axi_wvalid \
## s_axi_wdata \
## s_axi_wstrb \
## s_axi_wready \
## s_axi_bvalid \
## s_axi_bresp \
##
## s_axi_bready \
## s_axi_arvalid \
## s_axi_araddr \
## s_axi_arprot \
## s_axi_arready \
## s_axi_rvalid \
## s_axi_rdata \
## s_axi_rresp \
## s_axi_rready} \
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
##
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
##
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
##
## if {$raddr_width != $waddr_width} {
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
## set range 65536
## } else {
## if {$raddr_width >= 16} {
## set range 65536
## } else {
## set range [expr 1 << $raddr_width]
## }
## }
##
## ipx::add_memory_map {s_axi} [ipx::current_core]
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
## set_property range $range [ipx::get_address_blocks axi_lite \
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
## ipx::save_core
## }
## proc adi_init_bd_tcl {} {
##
## global auto_set_param_list
## global auto_set_param_list_overwritable
## set cc [ipx::current_core]
##
## if { [file exists bd] } {
## file delete -force bd
## }
## file mkdir bd
##
## set bd_tcl [open "bd/bd.tcl" w]
##
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
## puts $bd_tcl "proc init {cellpath otherInfo} {"
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
## puts $bd_tcl ""
## set auto_set_param ""
## foreach i $auto_set_param_list {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
## append auto_set_param " $i \\\n"
## }
## }
## if { $auto_set_param ne "" } {
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
## puts $bd_tcl $auto_set_param
## }
##
## set auto_set_overwritable_param ""
## foreach i $auto_set_param_list_overwritable {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
## append auto_set_overwritable_param " $i \\\n"
## }
## }
## if { $auto_set_overwritable_param ne "" } {
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
## puts $bd_tcl $auto_set_overwritable_param
## }
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
## puts $bd_tcl "}"
## puts $bd_tcl ""
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
## puts $bd_tcl ""
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
## puts $bd_tcl ""
## puts $bd_tcl " set parent_dir \"../\""
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
## puts $bd_tcl " break"
## puts $bd_tcl " }"
## puts $bd_tcl " append parent_dir \"../\""
## puts $bd_tcl " }"
## puts $bd_tcl ""
## puts $bd_tcl " # Find predefindes auto assignable parameters"
## puts $bd_tcl " foreach i \$auto_set_param_list {"
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
## puts $bd_tcl " }"
## puts $bd_tcl " }"
## puts $bd_tcl ""
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
## puts $bd_tcl " }"
## puts $bd_tcl " }"
## puts $bd_tcl "}"
## puts $bd_tcl ""
## close $bd_tcl
##
## set proj_fileset [get_filesets sources_1]
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
##
## set local_mk [open "temporary_case_dependencies.mk" w]
## seek $local_mk 0 start
## puts $local_mk "CLEAN_TARGET += bd"
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
## close $local_mk
## }
## proc adi_add_auto_fpga_spec_params {} {
##
## global auto_set_param_list
## global auto_set_param_list_overwritable
## set cc [ipx::current_core]
##
## foreach i $auto_set_param_list {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
## adi_add_device_spec_param $i
## }
## }
## foreach i $auto_set_param_list_overwritable {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
## adi_add_device_spec_param $i
## }
## }
## }
## proc adi_add_device_spec_param {ip_param} {
##
## set cc [ipx::current_core]
##
## set list_pointer [string tolower $ip_param]
## set list_pointer [append list_pointer "_list"]
##
## global $list_pointer
##
## # set j 1D list from the original list
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
##
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
## set_property -dict [list \
## "value_validation_type" "range_long" \
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
## [ipx::get_user_parameters $ip_param -of_objects $cc]
## } else {
## set_property -dict [list \
## "value_validation_type" "pairs" \
## "value_validation_pairs" $j ] \
## [ipx::get_user_parameters $ip_param -of_objects $cc]
## }
##
## # FPGA info grup
## set info_group_name "FPGA info"
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
## if { [string trim $info_group] eq "" } {
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
## -parent $page0 -display_name $info_group_name]
## }
##
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
## set_property -dict [list "widget" "comboBox" ] $p
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
## }
## proc adi_if_define {name} {
##
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
## ipx::create_bus_definition analog.com interface $name 1.0
##
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
##
## ipx::save_abstraction_definition [ipx::current_busabs]
## ipx::save_bus_definition [ipx::current_busdef]
## }
## proc adi_if_ports {dir width name {type none}} {
##
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
## set_property master_presence required $m_intf
## set_property slave_presence required $m_intf
## set_property master_width $width $m_intf
## set_property slave_width $width $m_intf
##
## set m_dir "in"
## set s_dir "out"
## if {$dir eq "output"} {
## set m_dir "out"
## set s_dir "in"
## }
##
## set_property master_direction $m_dir $m_intf
## set_property slave_direction $s_dir $m_intf
##
## if {$type ne "none"} {
## set_property is_${type} true $m_intf
## }
##
## ipx::save_bus_definition [ipx::current_busdef]
## ipx::save_abstraction_definition [ipx::current_busabs]
## }
## proc adi_if_infer_bus {if_name mode name maps} {
##
## ipx::add_bus_interface $name [ipx::current_core]
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
## set_property interface_mode $mode $m_bus_if
##
## foreach map $maps {
## set m_maps [regexp -all -inline {\S+} $map]
## lassign $m_maps p_name p_map
## ipx::add_port_map $p_name $m_bus_if
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
## }
## }
# adi_ip_create util_cic
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
## set_msg_config -id {BD 41-1343} -new_severity WARNING
## set_msg_config -id {BD 41-1306} -new_severity WARNING
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
## set_msg_config -id {Synth 8-3331} -new_severity INFO
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cic'.)
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
# add_files -fileset [get_filesets sources_1] [list \
# "cic_int.v" \
# "cic_comb.v" \
# ]
# adi_ip_properties_lite util_cic
WARNING: [IP_Flow 19-5150] The Range '(NUM_STAGES - 1):0' is present in all ports of the interface 'interface_spi_engine_offload_ctrl'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
# set_property name "util_cic" [ipx::current_core]
# set_property display_name "CIC building blocks" [ipx::current_core]
# set_property description "CIC building blocks" [ipx::current_core]
# set_property hide_in_gui {1} [ipx::current_core]
# ipx::save_core [ipx::current_core]
INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:12:42 2021...
adi_library/util_cic/util_cic_ip.tcl
+18
View File
@@ -0,0 +1,18 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create util_cic
add_files -fileset [get_filesets sources_1] [list \
"cic_int.v" \
"cic_comb.v" \
]
adi_ip_properties_lite util_cic
set_property name "util_cic" [ipx::current_core]
set_property display_name "CIC building blocks" [ipx::current_core]
set_property description "CIC building blocks" [ipx::current_core]
set_property hide_in_gui {1} [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/util_cic/vivado.jou
+12
View File
@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Vivado v2019.1.3 (64-bit)
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
# Start of session at: Thu Dec 9 15:12:36 2021
# Process ID: 4912
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cic
# Command line: vivado -mode batch -source util_cic_ip.tcl
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cic/vivado.log
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cic/vivado.jou
#-----------------------------------------------------------
source util_cic_ip.tcl
adi_library/util_cic/vivado.log
+694
View File
@@ -0,0 +1,694 @@
#-----------------------------------------------------------
# Vivado v2019.1.3 (64-bit)
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
# Start of session at: Thu Dec 9 15:12:36 2021
# Process ID: 4912
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cic
# Command line: vivado -mode batch -source util_cic_ip.tcl
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cic/vivado.log
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cic/vivado.jou
#-----------------------------------------------------------
source util_cic_ip.tcl
# source ../scripts/adi_env.tcl
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
## if [info exists ::env(ADI_HDL_DIR)] {
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
## }
## if [info exists ::env(ADI_GHDL_DIR)] {
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
## }
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
### variable auto_set_param_list
### variable auto_set_param_list_overwritable
### variable fpga_series_list
### variable fpga_family_list
### variable speed_grade_list
### variable dev_package_list
### variable xcvr_type_list
### variable fpga_voltage_list
### set auto_set_param_list { \
### DEV_PACKAGE \
### SPEED_GRADE \
### FPGA_FAMILY \
### FPGA_TECHNOLOGY }
### set auto_set_param_list_overwritable { \
### FPGA_VOLTAGE \
### XCVR_TYPE }
### set fpga_technology_list { \
### { Unknown 0 } \
### { 7series 1 } \
### { ultrascale 2 } \
### { ultrascale+ 3 }}
### set fpga_family_list { \
### { Unknown 0 } \
### { artix 1 } \
### { kintex 2 } \
### { virtex 3 } \
### { zynq 4 }}
### set speed_grade_list { \
### { Unknown 0 } \
### { -1 10 } \
### { -1L 11 } \
### { -1H 12 } \
### { -1HV 13 } \
### { -1LV 14 } \
### { -2 20 } \
### { -2L 21 } \
### { -2LV 22 } \
### { -3 30 }}
### set dev_package_list { \
### { Unknown 0 } \
### { rf 1 } \
### { fl 2 } \
### { ff 3 } \
### { fb 4 } \
### { hc 5 } \
### { fh 6 } \
### { cs 7 } \
### { cp 8 } \
### { ft 9 } \
### { fg 10 } \
### { sb 11 } \
### { rb 12 } \
### { rs 13 } \
### { cl 14 } \
### { sf 15 } \
### { ba 16 } \
### { fa 17 } \
### { fs 18 } \
### { fi 19 }}
### set xcvr_type_list { \
### { Unknown 0 } \
### { GTPE2_NOT_SUPPORTED 1 } \
### { GTXE2 2 } \
### { GTHE2_NOT_SUPPORTED 3 } \
### { GTZE2_NOT_SUPPORTED 4 } \
### { GTHE3 5 } \
### { GTYE3_NOT_SUPPORTED 6 } \
### { GTRE4_NOT_SUPPORTED 7 } \
### { GTHE4 8 } \
### { GTYE4 9 } \
### { GTME4_NOT_SUPPORTED 10}}
### set fpga_voltage_list {0 5000} ;
### proc adi_device_spec {cellpath param} {
###
### set list_pointer [string tolower $param]
### set list_pointer [append list_pointer "_list"]
###
### upvar 1 $list_pointer $list_pointer
###
### set ip [get_bd_cells $cellpath]
### set part [get_property PART [current_project]]
###
### switch -regexp -- $param {
### FPGA_TECHNOLOGY {
### switch -regexp -- $part {
### ^xc7 {set series_name 7series}
### ^xczu {set series_name ultrascale+}
### ^xc.u.p {set series_name ultrascale+}
### ^xc.u {set series_name ultrascale }
### default {
### puts "Undefined fpga technology for \"$part\"!"
### exit -1
### }
### }
### return "$series_name"
### }
### FPGA_FAMILY {
### set fpga_family [get_property FAMILY $part]
### foreach i $fpga_family_list {
### regexp ^[lindex $i 0] $fpga_family matched
### }
### return "$matched"
### }
### SPEED_GRADE {
### set speed_grade [get_property SPEED $part]
### return "$speed_grade"
### }
### DEV_PACKAGE {
### set dev_package [get_property PACKAGE $part]
### foreach i $dev_package_list {
### regexp ^[lindex $i 0] $dev_package matched
### }
### return "$matched"
### }
### XCVR_TYPE {
### set matched ""
### set dev_transcivers "none"
### foreach x [list_property $part] {
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
### }
### foreach i $xcvr_type_list {
### regexp ^[lindex $i 0] $dev_transcivers matched
### }
### if { $matched eq "" } {
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
### }
### return "$matched"
### }
### FPGA_VOLTAGE {
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
###
### return "$fpga_voltage"
### }
### default {
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
### }
### }
### }
## if {![info exists REQUIRED_VIVADO_VERSION]} {
## set REQUIRED_VIVADO_VERSION "2019.1"
## }
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
## set IGNORE_VERSION_CHECK 1
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
## set IGNORE_VERSION_CHECK 0
## }
## proc adi_ip_ttcl {ip_name ip_constr_files} {
##
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
## set_property -dict [list \
## type ttcl \
## ] $f
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
## }
## proc adi_ip_sim_ttcl {ip_name ip_files} {
##
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
## set f [ipx::add_file $ip_files $proj_filegroup]
## set_property -dict [list \
## type ttcl \
## ] $f
## ipx::reorder_files -front $ip_files $proj_filegroup
## }
## proc adi_ip_bd {ip_name ip_bd_files} {
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
## if {$proj_filegroup == {}} {
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
## }
##
## foreach file $ip_bd_files {
## set f [ipx::add_file $file $proj_filegroup]
## set_property -dict [list \
## type tclSource \
## ] $f
## }
## }
## proc adi_ip_infer_streaming_interfaces {ip_name} {
##
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
##
## }
## proc adi_ip_infer_mm_interfaces {ip_name} {
##
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
##
## }
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
## set_property ENABLEMENT_DEPENDENCY $dependency $port
## if {$driver_value != {}} {
## set_property DRIVER_VALUE $driver_value $port
## }
## }
## }
## proc adi_set_bus_dependency {bus prefix dependency} {
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
## adi_set_ports_dependency $prefix $dependency 0
## }
## proc adi_add_port_map {bus phys logic} {
## set map [ipx::add_port_map $phys $bus]
## set_property "PHYSICAL_NAME" $phys $map
## set_property "LOGICAL_NAME" $logic $map
## }
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
##
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
## set_property "BUS_TYPE_VLNV" $bus_type $bus
## set_property "INTERFACE_MODE" $mode $bus
##
## foreach port_map $port_maps {
## adi_add_port_map $bus {*}$port_map
## }
## }
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
## for {set i 0} {$i < $num} {incr i} {
## set bus_name [format "%s%d" $bus_name_prefix $i]
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
##
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
## set_property "BUS_TYPE_VLNV" $bus_type $bus
## set_property "INTERFACE_MODE" $mode $bus
##
## if {$dependency ne ""} {
## set bus_dependency [string map [list "{i}" $i] $dependency]
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
## }
##
## foreach port_map $port_maps {
## lassign $port_map phys logic width width_dep
## set map [ipx::add_port_map $phys $bus]
## set_property "PHYSICAL_NAME" $phys $map
## set_property "LOGICAL_NAME" $logic $map
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
## if {$width_dep ne ""} {
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
## set width_dep_r "(($width_dep) * $i)"
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
## }
## }
## }
## }
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
## set_property display_name $clock_inf_name $clock_inf
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
## set_property physical_name $clock_signal_name $clock_map
##
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
## set_property value $bus_inf_name $assoc_busif
##
## if { $reset_signal_name != "" } {
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
## set_property value $reset_signal_name $assoc_reset
##
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
## set_property display_name $reset_inf_name $reset_inf
## set_property interface_mode $reset_signal_mode $reset_inf
## set reset_map [ipx::add_port_map "RST" $reset_inf]
## set_property physical_name $reset_signal_name $reset_map
##
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
## set_property value "ACTIVE_LOW" $reset_polarity
## } else {
## set_property value "ACTIVE_HIGH" $reset_polarity
## }
## }
## }
## proc adi_ip_add_core_dependencies {vlnvs} {
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
## foreach vlnv $vlnvs {
## ipx::add_subcore $vlnv $file_group
## }
## }
## }
## proc adi_ip_create {ip_name} {
##
## global ad_hdl_dir
## global ad_ghdl_dir
## global REQUIRED_VIVADO_VERSION
## global IGNORE_VERSION_CHECK
##
## set VIVADO_VERSION [version -short]
## if {$IGNORE_VERSION_CHECK} {
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
## puts -nonewline "got $VIVADO_VERSION.\n"
## }
## } else {
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
## puts -nonewline "ERROR: vivado version mismatch; "
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
## puts -nonewline "got $VIVADO_VERSION.\n"
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
## exit 2
## }
## }
##
## create_project $ip_name . -force
##
## ## Load custom message severity definitions
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
##
## set lib_dirs $ad_hdl_dir/library
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
## lappend lib_dirs $ad_ghdl_dir/library
## }
##
## set_property ip_repo_paths $lib_dirs [current_fileset]
## update_ip_catalog
## }
## proc adi_ip_files {ip_name ip_files} {
## set proj_fileset [get_filesets sources_1]
## foreach m_file $ip_files {
## if {[file extension $m_file] eq ".xdc"} {
## add_files -norecurse -fileset constrs_1 $m_file
## } else {
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
## }
## }
## set_property "top" "$ip_name" $proj_fileset
## }
## proc adi_ip_properties_lite {ip_name} {
##
## global ad_hdl_dir
##
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
##
## set_property name $ip_name [ipx::current_core]
##
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
## set_property company_url {http://www.analog.com} [ipx::current_core]
##
## set i_families ""
## foreach i_part [get_parts] {
## lappend i_families [get_property FAMILY $i_part]
## }
## set i_families [lsort -unique $i_families]
## set s_families [get_property supported_families [ipx::current_core]]
## foreach i_family $i_families {
## set s_families "$s_families $i_family Production"
## set s_families "$s_families $i_family Beta"
## }
## set_property supported_families $s_families [ipx::current_core]
##
## ipx::save_core [ipx::current_core]
##
## ipx::remove_all_bus_interface [ipx::current_core]
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
## foreach map $memory_maps {
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
## }
##
## ipx::update_checksums [ipx::current_core]
## ipx::save_core [ipx::current_core]
## }
## proc adi_ip_properties {ip_name} {
##
## adi_ip_properties_lite $ip_name
##
## ipx::infer_bus_interface {\
## s_axi_awvalid \
## s_axi_awaddr \
## s_axi_awprot \
## s_axi_awready \
## s_axi_wvalid \
## s_axi_wdata \
## s_axi_wstrb \
## s_axi_wready \
## s_axi_bvalid \
## s_axi_bresp \
##
## s_axi_bready \
## s_axi_arvalid \
## s_axi_araddr \
## s_axi_arprot \
## s_axi_arready \
## s_axi_rvalid \
## s_axi_rdata \
## s_axi_rresp \
## s_axi_rready} \
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
##
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
##
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
##
## if {$raddr_width != $waddr_width} {
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
## set range 65536
## } else {
## if {$raddr_width >= 16} {
## set range 65536
## } else {
## set range [expr 1 << $raddr_width]
## }
## }
##
## ipx::add_memory_map {s_axi} [ipx::current_core]
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
## set_property range $range [ipx::get_address_blocks axi_lite \
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
## ipx::save_core
## }
## proc adi_init_bd_tcl {} {
##
## global auto_set_param_list
## global auto_set_param_list_overwritable
## set cc [ipx::current_core]
##
## if { [file exists bd] } {
## file delete -force bd
## }
## file mkdir bd
##
## set bd_tcl [open "bd/bd.tcl" w]
##
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
## puts $bd_tcl "proc init {cellpath otherInfo} {"
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
## puts $bd_tcl ""
## set auto_set_param ""
## foreach i $auto_set_param_list {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
## append auto_set_param " $i \\\n"
## }
## }
## if { $auto_set_param ne "" } {
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
## puts $bd_tcl $auto_set_param
## }
##
## set auto_set_overwritable_param ""
## foreach i $auto_set_param_list_overwritable {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
## append auto_set_overwritable_param " $i \\\n"
## }
## }
## if { $auto_set_overwritable_param ne "" } {
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
## puts $bd_tcl $auto_set_overwritable_param
## }
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
## puts $bd_tcl "}"
## puts $bd_tcl ""
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
## puts $bd_tcl ""
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
## puts $bd_tcl ""
## puts $bd_tcl " set parent_dir \"../\""
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
## puts $bd_tcl " break"
## puts $bd_tcl " }"
## puts $bd_tcl " append parent_dir \"../\""
## puts $bd_tcl " }"
## puts $bd_tcl ""
## puts $bd_tcl " # Find predefindes auto assignable parameters"
## puts $bd_tcl " foreach i \$auto_set_param_list {"
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
## puts $bd_tcl " }"
## puts $bd_tcl " }"
## puts $bd_tcl ""
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
## puts $bd_tcl " }"
## puts $bd_tcl " }"
## puts $bd_tcl "}"
## puts $bd_tcl ""
## close $bd_tcl
##
## set proj_fileset [get_filesets sources_1]
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
##
## set local_mk [open "temporary_case_dependencies.mk" w]
## seek $local_mk 0 start
## puts $local_mk "CLEAN_TARGET += bd"
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
## close $local_mk
## }
## proc adi_add_auto_fpga_spec_params {} {
##
## global auto_set_param_list
## global auto_set_param_list_overwritable
## set cc [ipx::current_core]
##
## foreach i $auto_set_param_list {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
## adi_add_device_spec_param $i
## }
## }
## foreach i $auto_set_param_list_overwritable {
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
## adi_add_device_spec_param $i
## }
## }
## }
## proc adi_add_device_spec_param {ip_param} {
##
## set cc [ipx::current_core]
##
## set list_pointer [string tolower $ip_param]
## set list_pointer [append list_pointer "_list"]
##
## global $list_pointer
##
## # set j 1D list from the original list
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
##
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
## set_property -dict [list \
## "value_validation_type" "range_long" \
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
## [ipx::get_user_parameters $ip_param -of_objects $cc]
## } else {
## set_property -dict [list \
## "value_validation_type" "pairs" \
## "value_validation_pairs" $j ] \
## [ipx::get_user_parameters $ip_param -of_objects $cc]
## }
##
## # FPGA info grup
## set info_group_name "FPGA info"
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
## if { [string trim $info_group] eq "" } {
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
## -parent $page0 -display_name $info_group_name]
## }
##
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
## set_property -dict [list "widget" "comboBox" ] $p
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
## }
## proc adi_if_define {name} {
##
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
## ipx::create_bus_definition analog.com interface $name 1.0
##
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
##
## ipx::save_abstraction_definition [ipx::current_busabs]
## ipx::save_bus_definition [ipx::current_busdef]
## }
## proc adi_if_ports {dir width name {type none}} {
##
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
## set_property master_presence required $m_intf
## set_property slave_presence required $m_intf
## set_property master_width $width $m_intf
## set_property slave_width $width $m_intf
##
## set m_dir "in"
## set s_dir "out"
## if {$dir eq "output"} {
## set m_dir "out"
## set s_dir "in"
## }
##
## set_property master_direction $m_dir $m_intf
## set_property slave_direction $s_dir $m_intf
##
## if {$type ne "none"} {
## set_property is_${type} true $m_intf
## }
##
## ipx::save_bus_definition [ipx::current_busdef]
## ipx::save_abstraction_definition [ipx::current_busabs]
## }
## proc adi_if_infer_bus {if_name mode name maps} {
##
## ipx::add_bus_interface $name [ipx::current_core]
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
## set_property interface_mode $mode $m_bus_if
##
## foreach map $maps {
## set m_maps [regexp -all -inline {\S+} $map]
## lassign $m_maps p_name p_map
## ipx::add_port_map $p_name $m_bus_if
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
## }
## }
# adi_ip_create util_cic
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
## set_msg_config -id {BD 41-1343} -new_severity WARNING
## set_msg_config -id {BD 41-1306} -new_severity WARNING
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
## set_msg_config -id {Synth 8-3331} -new_severity INFO
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_cic'.)
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
# add_files -fileset [get_filesets sources_1] [list \
# "cic_int.v" \
# "cic_comb.v" \
# ]
# adi_ip_properties_lite util_cic
WARNING: [IP_Flow 19-5150] The Range '(NUM_STAGES - 1):0' is present in all ports of the interface 'interface_spi_engine_offload_ctrl'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
# set_property name "util_cic" [ipx::current_core]
# set_property display_name "CIC building blocks" [ipx::current_core]
# set_property description "CIC building blocks" [ipx::current_core]
# set_property hide_in_gui {1} [ipx::current_core]
# ipx::save_core [ipx::current_core]
INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:12:42 2021...
adi_library/util_cic/xgui/cic_comb_v1_0.tcl
+70
View File
@@ -0,0 +1,70 @@
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "NUM_STAGES" -parent ${Page_0}
ipgui::add_param $IPINST -name "SEQ" -parent ${Page_0}
ipgui::add_param $IPINST -name "STAGE_WIDTH" -parent ${Page_0}
}
proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
# Procedure called to validate DATA_WIDTH
return true
}
proc update_PARAM_VALUE.NUM_STAGES { PARAM_VALUE.NUM_STAGES } {
# Procedure called to update NUM_STAGES when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_STAGES { PARAM_VALUE.NUM_STAGES } {
# Procedure called to validate NUM_STAGES
return true
}
proc update_PARAM_VALUE.SEQ { PARAM_VALUE.SEQ } {
# Procedure called to update SEQ when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SEQ { PARAM_VALUE.SEQ } {
# Procedure called to validate SEQ
return true
}
proc update_PARAM_VALUE.STAGE_WIDTH { PARAM_VALUE.STAGE_WIDTH } {
# Procedure called to update STAGE_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.STAGE_WIDTH { PARAM_VALUE.STAGE_WIDTH } {
# Procedure called to validate STAGE_WIDTH
return true
}
proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.SEQ { MODELPARAM_VALUE.SEQ PARAM_VALUE.SEQ } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SEQ}] ${MODELPARAM_VALUE.SEQ}
}
proc update_MODELPARAM_VALUE.STAGE_WIDTH { MODELPARAM_VALUE.STAGE_WIDTH PARAM_VALUE.STAGE_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.STAGE_WIDTH}] ${MODELPARAM_VALUE.STAGE_WIDTH}
}
proc update_MODELPARAM_VALUE.NUM_STAGES { MODELPARAM_VALUE.NUM_STAGES PARAM_VALUE.NUM_STAGES } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_STAGES}] ${MODELPARAM_VALUE.NUM_STAGES}
}