Archived
initial commit
This commit is contained in:
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := util_upack2
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GENERIC_DEPS += ../../common/ad_perfect_shuffle.v
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GENERIC_DEPS += ../util_pack_common/pack_ctrl.v
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GENERIC_DEPS += ../util_pack_common/pack_interconnect.v
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GENERIC_DEPS += ../util_pack_common/pack_network.v
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GENERIC_DEPS += ../util_pack_common/pack_shell.v
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GENERIC_DEPS += util_upack2_impl.v
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XILINX_DEPS += util_upack2.v
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XILINX_DEPS += util_upack2_ip.tcl
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INTEL_DEPS += util_upack2_hw.tcl
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include ../../scripts/library.mk
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File diff suppressed because it is too large
Load Diff
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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eof:
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@@ -0,0 +1,6 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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<labtools version="1" minor="0"/>
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@@ -0,0 +1,302 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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||||
// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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||||
// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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||||
//
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||||
// 1. The GNU General Public License version 2 as published by the
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||||
// Free Software Foundation, which can be found in the top level directory
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||||
// of this repository (LICENSE_GPL2), and also online at:
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||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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||||
// OR
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||||
//
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||||
// 2. An ADI specific BSD license, which can be found in the top level directory
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||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
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||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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||||
// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_upack2 #(
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parameter NUM_OF_CHANNELS = 4,
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parameter SAMPLES_PER_CHANNEL = 1,
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parameter SAMPLE_DATA_WIDTH = 16
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) (
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input clk,
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input reset,
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input enable_0,
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input enable_1,
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input enable_2,
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input enable_3,
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input enable_4,
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input enable_5,
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input enable_6,
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input enable_7,
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input enable_8,
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input enable_9,
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input enable_10,
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input enable_11,
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input enable_12,
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input enable_13,
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input enable_14,
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input enable_15,
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input enable_16,
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input enable_17,
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input enable_18,
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input enable_19,
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input enable_20,
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input enable_21,
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input enable_22,
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input enable_23,
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input enable_24,
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input enable_25,
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input enable_26,
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input enable_27,
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input enable_28,
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input enable_29,
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input enable_30,
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input enable_31,
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input enable_32,
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input enable_33,
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input enable_34,
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input enable_35,
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input enable_36,
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input enable_37,
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input enable_38,
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input enable_39,
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input enable_40,
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input enable_41,
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input enable_42,
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input enable_43,
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input enable_44,
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input enable_45,
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input enable_46,
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input enable_47,
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input enable_48,
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input enable_49,
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input enable_50,
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input enable_51,
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input enable_52,
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input enable_53,
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input enable_54,
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input enable_55,
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input enable_56,
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input enable_57,
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input enable_58,
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input enable_59,
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input enable_60,
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input enable_61,
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input enable_62,
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input enable_63,
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input fifo_rd_en,
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output fifo_rd_valid,
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output fifo_rd_underflow,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_0,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_1,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_2,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_3,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_4,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_5,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_6,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_7,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_8,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_9,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_10,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_11,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_12,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_13,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_14,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_15,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_16,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_17,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_18,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_19,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_20,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_21,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_22,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_23,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_24,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_25,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_26,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_27,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_28,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_29,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_30,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_31,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_32,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_33,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_34,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_35,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_36,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_37,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_38,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_39,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_40,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_41,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_42,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_43,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_44,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_45,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_46,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_47,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_48,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_49,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_50,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_51,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_52,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_53,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_54,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_55,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_56,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_57,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_58,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_59,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_60,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_61,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_62,
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output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_63,
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input s_axis_valid,
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output s_axis_ready,
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input [2**$clog2(NUM_OF_CHANNELS)*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] s_axis_data
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);
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localparam CHANNEL_DATA_WIDTH = SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL;
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/*
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* Round up to the next power of two and zero out the additional channels
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* internally.
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*/
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localparam REAL_NUM_OF_CHANNELS = NUM_OF_CHANNELS > 32 ? 64 :
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NUM_OF_CHANNELS > 16 ? 32 :
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NUM_OF_CHANNELS > 8 ? 16 :
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NUM_OF_CHANNELS > 4 ? 8 :
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NUM_OF_CHANNELS > 2 ? 4 :
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NUM_OF_CHANNELS > 1 ? 2 : 1;
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/* FIXME: Find out how to do this in the IP-XACT */
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wire [63:0] enable_s;
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wire [CHANNEL_DATA_WIDTH*REAL_NUM_OF_CHANNELS-1:0] fifo_rd_data;
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wire [CHANNEL_DATA_WIDTH*64-1:0] fifo_rd_data_s;
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util_upack2_impl #(
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.NUM_OF_CHANNELS(REAL_NUM_OF_CHANNELS),
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.SAMPLE_DATA_WIDTH(SAMPLE_DATA_WIDTH),
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.SAMPLES_PER_CHANNEL(SAMPLES_PER_CHANNEL)
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) i_upack (
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.clk (clk),
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.reset (reset),
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.enable (enable_s[REAL_NUM_OF_CHANNELS-1:0]),
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.fifo_rd_en ({REAL_NUM_OF_CHANNELS{fifo_rd_en}}),
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.fifo_rd_valid (fifo_rd_valid),
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.fifo_rd_underflow (fifo_rd_underflow),
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.fifo_rd_data (fifo_rd_data),
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.s_axis_valid (s_axis_valid),
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.s_axis_ready (s_axis_ready),
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.s_axis_data (s_axis_data)
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);
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assign enable_s = {
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enable_63,enable_62,enable_61,enable_60,enable_59,enable_58,enable_57,enable_56,
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enable_55,enable_54,enable_53,enable_52,enable_51,enable_50,enable_49,enable_48,
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enable_47,enable_46,enable_45,enable_44,enable_43,enable_42,enable_41,enable_40,
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enable_39,enable_38,enable_37,enable_36,enable_35,enable_34,enable_33,enable_32,
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enable_31,enable_30,enable_29,enable_28,enable_27,enable_26,enable_25,enable_24,
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enable_23,enable_22,enable_21,enable_20,enable_19,enable_18,enable_17,enable_16,
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enable_15,enable_14,enable_13,enable_12,enable_11,enable_10,enable_9,enable_8,
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enable_7,enable_6,enable_5,enable_4,enable_3,enable_2,enable_1,enable_0
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};
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assign fifo_rd_data_s = {{(64-NUM_OF_CHANNELS)*CHANNEL_DATA_WIDTH{1'b0}},fifo_rd_data};
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assign fifo_rd_data_0 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*0+:CHANNEL_DATA_WIDTH];
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assign fifo_rd_data_1 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*1+:CHANNEL_DATA_WIDTH];
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assign fifo_rd_data_2 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*2+:CHANNEL_DATA_WIDTH];
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assign fifo_rd_data_3 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*3+:CHANNEL_DATA_WIDTH];
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assign fifo_rd_data_4 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*4+:CHANNEL_DATA_WIDTH];
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assign fifo_rd_data_5 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*5+:CHANNEL_DATA_WIDTH];
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assign fifo_rd_data_6 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*6+:CHANNEL_DATA_WIDTH];
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assign fifo_rd_data_7 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*7+:CHANNEL_DATA_WIDTH];
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assign fifo_rd_data_8 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*8+:CHANNEL_DATA_WIDTH];
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assign fifo_rd_data_9 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*9+:CHANNEL_DATA_WIDTH];
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assign fifo_rd_data_10 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*10+:CHANNEL_DATA_WIDTH];
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||||
assign fifo_rd_data_11 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*11+:CHANNEL_DATA_WIDTH];
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||||
assign fifo_rd_data_12 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*12+:CHANNEL_DATA_WIDTH];
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||||
assign fifo_rd_data_13 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*13+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_14 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*14+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_15 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*15+:CHANNEL_DATA_WIDTH];
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||||
assign fifo_rd_data_16 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*16+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_17 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*17+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_18 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*18+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_19 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*19+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_20 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*20+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_21 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*21+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_22 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*22+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_23 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*23+:CHANNEL_DATA_WIDTH];
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||||
assign fifo_rd_data_24 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*24+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_25 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*25+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_26 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*26+:CHANNEL_DATA_WIDTH];
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||||
assign fifo_rd_data_27 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*27+:CHANNEL_DATA_WIDTH];
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||||
assign fifo_rd_data_28 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*28+:CHANNEL_DATA_WIDTH];
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||||
assign fifo_rd_data_29 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*29+:CHANNEL_DATA_WIDTH];
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||||
assign fifo_rd_data_30 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*30+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_31 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*31+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_32 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*32+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_33 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*33+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_34 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*34+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_35 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*35+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_36 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*36+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_37 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*37+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_38 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*38+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_39 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*39+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_40 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*40+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_41 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*41+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_42 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*42+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_43 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*43+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_44 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*44+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_45 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*45+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_46 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*46+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_47 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*47+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_48 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*48+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_49 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*49+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_50 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*50+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_51 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*51+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_52 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*52+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_53 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*53+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_54 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*54+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_55 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*55+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_56 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*56+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_57 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*57+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_58 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*58+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_59 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*59+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_60 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*60+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_61 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*61+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_62 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*62+:CHANNEL_DATA_WIDTH];
|
||||
assign fifo_rd_data_63 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*63+:CHANNEL_DATA_WIDTH];
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,418 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2/util_upack2.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="cb67ff69cb52428197de4c111ef47f0a"/>
|
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<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
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<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
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<Option Name="CompiledLibDirXSim" Val=""/>
|
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<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
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<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
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<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
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||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
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||||
<Option Name="DSANumComputeUnits" Val="60"/>
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<Option Name="WTXSimLaunchSim" Val="0"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
|
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<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
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<Option Name="WTVcsLaunchSim" Val="0"/>
|
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<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
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<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../common/ad_perfect_shuffle.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
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||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../util_pack_common/pack_ctrl.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
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<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../util_pack_common/pack_interconnect.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
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<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../util_pack_common/pack_network.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../util_pack_common/pack_shell.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
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<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/util_upack2_impl.v">
|
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<FileInfo>
|
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<Attr Name="UsedIn" Val="synthesis"/>
|
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<Attr Name="UsedIn" Val="implementation"/>
|
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<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/util_upack2.v">
|
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<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="util_upack2"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
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<Filter Type="Utils"/>
|
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<Config>
|
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<Option Name="TopAutoSet" Val="TRUE"/>
|
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</Config>
|
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</FileSet>
|
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</FileSets>
|
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<Simulators>
|
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<Simulator Name="XSim">
|
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<Option Name="Description" Val="Vivado Simulator"/>
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<Option Name="CompiledLib" Val="0"/>
|
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</Simulator>
|
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<Simulator Name="ModelSim">
|
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<Option Name="Description" Val="ModelSim Simulator"/>
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</Simulator>
|
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<Simulator Name="Questa">
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<Option Name="Description" Val="Questa Advanced Simulator"/>
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</Simulator>
|
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<Simulator Name="IES">
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<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
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</Simulator>
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<Simulator Name="Xcelium">
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<Option Name="Description" Val="Xcelium Parallel Simulator"/>
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</Simulator>
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<Simulator Name="VCS">
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<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
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</Simulator>
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<Simulator Name="Riviera">
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<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
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</Simulator>
|
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</Simulators>
|
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<Runs Version="1" Minor="10">
|
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
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</StratHandle>
|
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<Step Id="synth_design"/>
|
||||
</Strategy>
|
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
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</Run>
|
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
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<Desc>Default settings for Implementation.</Desc>
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</StratHandle>
|
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<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
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</Runs>
|
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<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
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<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
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<MsgAttr Name="Severity" Val="ANY"/>
|
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<MsgAttr Name="ShowRule" Val="1"/>
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||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
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<MsgAttr Name="RuleId" Val="1"/>
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<MsgAttr Name="Note" Val=""/>
|
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<MsgAttr Name="Author" Val=""/>
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<MsgAttr Name="CreatedTimestamp" Val=""/>
|
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<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
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<MsgAttr Name="StringsToMatch" Val="features"/>
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<MsgAttr Name="StringsToMatch" Val="should"/>
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<MsgAttr Name="StringsToMatch" Val="NOT"/>
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<MsgAttr Name="StringsToMatch" Val="be"/>
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<MsgAttr Name="StringsToMatch" Val="used"/>
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<MsgAttr Name="StringsToMatch" Val="in"/>
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<MsgAttr Name="StringsToMatch" Val="production"/>
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<MsgAttr Name="StringsToMatch" Val="systems."/>
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</MsgRule>
|
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<MsgRule>
|
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<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
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<MsgAttr Name="Id" Val="Place 30-73"/>
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<MsgAttr Name="Severity" Val="ANY"/>
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<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="RuleSource" Val="2"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
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<MsgAttr Name="RuleId" Val="10"/>
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<MsgAttr Name="Note" Val=""/>
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<MsgAttr Name="Author" Val=""/>
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<MsgAttr Name="CreatedTimestamp" Val=""/>
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<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
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</MsgRule>
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<MsgRule>
|
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<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="Limit" Val="-1"/>
|
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
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<MsgAttr Name="Id" Val=""/>
|
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<MsgAttr Name="Severity" Val="ANY"/>
|
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<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
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<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
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<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
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</MsgRule>
|
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<MsgRule>
|
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<MsgAttr Name="RuleType" Val="1"/>
|
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<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
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<MsgAttr Name="Id" Val="BD 41-1343"/>
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<MsgAttr Name="Severity" Val="ANY"/>
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<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="RuleSource" Val="2"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
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<MsgAttr Name="RuleId" Val="2"/>
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<MsgAttr Name="Note" Val=""/>
|
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<MsgAttr Name="Author" Val=""/>
|
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<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
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<MsgAttr Name="RuleType" Val="1"/>
|
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<MsgAttr Name="Limit" Val="-1"/>
|
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
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<MsgAttr Name="Id" Val="BD 41-1306"/>
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<MsgAttr Name="Severity" Val="ANY"/>
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<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="RuleSource" Val="2"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
|
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<MsgAttr Name="RuleId" Val="3"/>
|
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<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,112 @@
|
||||
# ***************************************************************************
|
||||
# ***************************************************************************
|
||||
# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
|
||||
#
|
||||
# Each core or library found in this collection may have its own licensing terms.
|
||||
# The user should keep this in in mind while exploring these cores.
|
||||
#
|
||||
# Redistribution and use in source and binary forms,
|
||||
# with or without modification of this file, are permitted under the terms of either
|
||||
# (at the option of the user):
|
||||
#
|
||||
# 1. The GNU General Public License version 2 as published by the
|
||||
# Free Software Foundation, which can be found in the top level directory, or at:
|
||||
# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
|
||||
#
|
||||
# OR
|
||||
#
|
||||
# 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
|
||||
# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
|
||||
#
|
||||
# ***************************************************************************
|
||||
# ***************************************************************************
|
||||
|
||||
package require qsys
|
||||
source ../../scripts/adi_env.tcl
|
||||
source ../../scripts/adi_ip_intel.tcl
|
||||
|
||||
ad_ip_create util_upack2 {Channel Unpack Utility v2} util_upack_elab
|
||||
ad_ip_files util_upack2_impl [list \
|
||||
$ad_hdl_dir/library/common/ad_perfect_shuffle.v \
|
||||
../util_pack_common/pack_ctrl.v \
|
||||
../util_pack_common/pack_interconnect.v \
|
||||
../util_pack_common/pack_network.v \
|
||||
../util_pack_common/pack_shell.v \
|
||||
util_upack2_impl.v ]
|
||||
|
||||
# parameters
|
||||
|
||||
ad_ip_parameter NUM_OF_CHANNELS INTEGER 4 true [list \
|
||||
DISPLAY_NAME "Number of Channels"
|
||||
]
|
||||
|
||||
ad_ip_parameter SAMPLES_PER_CHANNEL INTEGER 1 true [list \
|
||||
DISPLAY_NAME "Samples per Channel"
|
||||
]
|
||||
|
||||
ad_ip_parameter SAMPLE_DATA_WIDTH INTEGER 16 true [list \
|
||||
DISPLAY_NAME "Sample Data Width"
|
||||
]
|
||||
|
||||
ad_ip_parameter INTERFACE_TYPE INTEGER 0 false [list \
|
||||
DISPLAY_NAME "Interface Type" \
|
||||
ALLOWED_RANGES {"0:AXIS" "1:FIFO"} \
|
||||
]
|
||||
|
||||
|
||||
# defaults
|
||||
|
||||
proc util_upack_elab {} {
|
||||
set num_channels [get_parameter_value NUM_OF_CHANNELS]
|
||||
set samples_per_channel [get_parameter_value SAMPLES_PER_CHANNEL]
|
||||
set sample_data_width [get_parameter_value SAMPLE_DATA_WIDTH]
|
||||
set interface_type [get_parameter_value INTERFACE_TYPE]
|
||||
|
||||
set channel_data_width [expr $sample_data_width * $samples_per_channel]
|
||||
set total_data_width [expr $num_channels * $channel_data_width]
|
||||
|
||||
add_interface clk clock end
|
||||
add_interface_port clk clk clk Input 1
|
||||
add_interface reset reset end
|
||||
add_interface_port reset reset reset Input 1
|
||||
set_interface_property reset associatedClock clk
|
||||
|
||||
# This is a temporary hack and should be removed once all projects have been
|
||||
# updated to use the AXI streaming interface to connect the the upack
|
||||
if {$interface_type == 0} {
|
||||
add_interface s_axis axi4stream end
|
||||
set_interface_property s_axis associatedClock clk
|
||||
set_interface_property s_axis associatedReset reset
|
||||
add_interface_port s_axis s_axis_valid tvalid Input 1
|
||||
add_interface_port s_axis s_axis_ready tready Output 1
|
||||
add_interface_port s_axis s_axis_data tdata Input $total_data_width
|
||||
} else {
|
||||
ad_interface signal packed_fifo_rd_en output 1 valid
|
||||
set_port_property packed_fifo_rd_en fragment_list "s_axis_ready"
|
||||
ad_interface signal packed_fifo_rd_data input $total_data_width data
|
||||
set_port_property packed_fifo_rd_data fragment_list \
|
||||
[format "s_axis_data(%d:0)" [expr $total_data_width - 1]]
|
||||
ad_interface signal s_axis_valid input 1 valid
|
||||
set_port_property s_axis_valid TERMINATION TRUE
|
||||
set_port_property s_axis_valid TERMINATION_VALUE 1
|
||||
}
|
||||
|
||||
ad_interface signal fifo_rd_underflow output 1 unf
|
||||
|
||||
for {set n 0} {$n < $num_channels} {incr n} {
|
||||
add_interface dac_ch_${n} conduit end
|
||||
add_interface_port dac_ch_${n} enable_${n} enable Input 1
|
||||
set_port_property enable_${n} fragment_list "enable(${n}:${n})"
|
||||
|
||||
add_interface_port dac_ch_${n} fifo_rd_en_${n} valid Input 1
|
||||
set_port_property fifo_rd_en_${n} fragment_list "fifo_rd_en(${n})"
|
||||
add_interface_port dac_ch_${n} fifo_rd_valid_${n} data_valid Output 1
|
||||
set_port_property fifo_rd_valid_${n} fragment_list "fifo_rd_valid(0)"
|
||||
add_interface_port dac_ch_${n} fifo_rd_data_${n} data Output $channel_data_width
|
||||
set_port_property fifo_rd_data_${n} fragment_list [format "fifo_rd_data(%d:%d)" \
|
||||
[expr ($n+1) * $channel_data_width - 1] [expr $n * $channel_data_width]]
|
||||
set_interface_property dac_ch_${n} associatedClock clk
|
||||
set_interface_property dac_ch_${n} associatedReset ""
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,146 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsabilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module util_upack2_impl #(
|
||||
parameter NUM_OF_CHANNELS = 4,
|
||||
parameter SAMPLES_PER_CHANNEL = 1,
|
||||
parameter SAMPLE_DATA_WIDTH = 16
|
||||
) (
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
input [NUM_OF_CHANNELS-1:0] enable,
|
||||
|
||||
input [NUM_OF_CHANNELS-1:0] fifo_rd_en,
|
||||
output reg fifo_rd_valid,
|
||||
output reg fifo_rd_underflow,
|
||||
output reg [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data,
|
||||
|
||||
input s_axis_valid,
|
||||
output s_axis_ready,
|
||||
input [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] s_axis_data
|
||||
);
|
||||
|
||||
/*
|
||||
* Final output data of the routing network that will be written to
|
||||
* `fifo_rd_data` after being deinterleaved.
|
||||
*/
|
||||
wire [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] out_data;
|
||||
|
||||
/*
|
||||
* Deinterleaved version of `out_data`
|
||||
*/
|
||||
wire [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] deinterleaved_data;
|
||||
|
||||
/*
|
||||
* Internal read signal.
|
||||
*/
|
||||
wire data_rd_en;
|
||||
|
||||
/*
|
||||
* Control signals from/to the pack shell.
|
||||
*/
|
||||
wire ce;
|
||||
wire ready;
|
||||
wire reset_data;
|
||||
|
||||
/*
|
||||
* Only the first signal of fifo_rd_en is used. All others are ignored. The
|
||||
* only reason why fifo_rd_en has multiple entries is to keep the interface
|
||||
* somewhat backwards compatible to the previous upack.
|
||||
*/
|
||||
assign data_rd_en = fifo_rd_en[0];
|
||||
|
||||
assign ce = s_axis_valid & data_rd_en;
|
||||
assign s_axis_ready = ready & ce;
|
||||
|
||||
pack_shell #(
|
||||
.NUM_OF_CHANNELS (NUM_OF_CHANNELS),
|
||||
.SAMPLES_PER_CHANNEL (SAMPLES_PER_CHANNEL),
|
||||
.SAMPLE_DATA_WIDTH (SAMPLE_DATA_WIDTH),
|
||||
.PACK (0)
|
||||
) i_pack_shell (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
|
||||
.reset_data (reset_data),
|
||||
|
||||
.enable (enable),
|
||||
.ce (ce),
|
||||
.ready (ready),
|
||||
.in_data (s_axis_data),
|
||||
.out_data (out_data),
|
||||
|
||||
.out_valid (),
|
||||
.out_sync ()
|
||||
);
|
||||
|
||||
/*
|
||||
* Data at the output of the routing network is interleaved. The upack
|
||||
* core is supposed to produce deinterleaved data. This just rearrange the
|
||||
* bits in the data vector and does not consume any FPGA resources.
|
||||
*/
|
||||
ad_perfect_shuffle #(
|
||||
.NUM_GROUPS (SAMPLES_PER_CHANNEL),
|
||||
.WORDS_PER_GROUP (NUM_OF_CHANNELS),
|
||||
.WORD_WIDTH (SAMPLE_DATA_WIDTH)
|
||||
) i_deinterleave (
|
||||
.data_in (out_data),
|
||||
.data_out (deinterleaved_data)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
/* In case of an underflow the output vector should be zeroed */
|
||||
if (reset_data == 1'b1 ||
|
||||
(data_rd_en == 1'b1 && s_axis_valid == 1'b0)) begin
|
||||
fifo_rd_data <= 'h00;
|
||||
end else if (data_rd_en == 1'b1) begin
|
||||
fifo_rd_data <= deinterleaved_data;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (data_rd_en == 1'b1) begin
|
||||
fifo_rd_valid <= s_axis_valid & ~reset_data;
|
||||
fifo_rd_underflow <= ~(s_axis_valid & ~reset_data);
|
||||
end else begin
|
||||
fifo_rd_valid <= 1'b0;
|
||||
fifo_rd_underflow <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,68 @@
|
||||
# ***************************************************************************
|
||||
# ***************************************************************************
|
||||
# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
|
||||
#
|
||||
# Each core or library found in this collection may have its own licensing terms.
|
||||
# The user should keep this in in mind while exploring these cores.
|
||||
#
|
||||
# Redistribution and use in source and binary forms,
|
||||
# with or without modification of this file, are permitted under the terms of either
|
||||
# (at the option of the user):
|
||||
#
|
||||
# 1. The GNU General Public License version 2 as published by the
|
||||
# Free Software Foundation, which can be found in the top level directory, or at:
|
||||
# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
|
||||
#
|
||||
# OR
|
||||
#
|
||||
# 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
|
||||
# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
|
||||
#
|
||||
# ***************************************************************************
|
||||
# ***************************************************************************
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create util_upack2
|
||||
adi_ip_files util_upack2 [list \
|
||||
"../../common/ad_perfect_shuffle.v" \
|
||||
"../util_pack_common/pack_ctrl.v" \
|
||||
"../util_pack_common/pack_interconnect.v" \
|
||||
"../util_pack_common/pack_network.v" \
|
||||
"../util_pack_common/pack_shell.v" \
|
||||
"util_upack2_impl.v" \
|
||||
"util_upack2.v" ]
|
||||
|
||||
adi_ip_properties_lite util_upack2
|
||||
|
||||
adi_add_bus "s_axis" "slave" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
[list {"s_axis_ready" "TREADY"} \
|
||||
{"s_axis_valid" "TVALID"} \
|
||||
{"s_axis_data" "TDATA"} \
|
||||
]
|
||||
adi_add_bus_clock "clk" "s_axis" "reset"
|
||||
|
||||
set cc [ipx::current_core]
|
||||
|
||||
for {set i 1} {$i < 64} {incr i} {
|
||||
set_property enablement_dependency "spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > $i" \
|
||||
[ipx::get_ports *_$i -of_objects $cc]
|
||||
}
|
||||
|
||||
foreach {k v} { \
|
||||
"NUM_OF_CHANNELS" "Number of Channels" \
|
||||
"SAMPLES_PER_CHANNEL" "Samples per Channel" \
|
||||
"SAMPLE_DATA_WIDTH" "Sample Width" \
|
||||
} { \
|
||||
set p [ipgui::get_guiparamspec -name $k -component $cc]
|
||||
# ipgui::move_param -component $cc -order $i $p -parent $
|
||||
set_property -dict [list \
|
||||
DISPLAY_NAME $v \
|
||||
] $p
|
||||
incr i
|
||||
}
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Wed Dec 8 10:23:55 2021
|
||||
# Process ID: 67008
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2
|
||||
# Command line: vivado -mode batch -source util_upack2_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_pack/util_upack2/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source util_upack2_ip.tcl
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,55 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "NUM_OF_CHANNELS" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "SAMPLES_PER_CHANNEL" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "SAMPLE_DATA_WIDTH" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } {
|
||||
# Procedure called to update NUM_OF_CHANNELS when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } {
|
||||
# Procedure called to validate NUM_OF_CHANNELS
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SAMPLES_PER_CHANNEL { PARAM_VALUE.SAMPLES_PER_CHANNEL } {
|
||||
# Procedure called to update SAMPLES_PER_CHANNEL when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SAMPLES_PER_CHANNEL { PARAM_VALUE.SAMPLES_PER_CHANNEL } {
|
||||
# Procedure called to validate SAMPLES_PER_CHANNEL
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SAMPLE_DATA_WIDTH { PARAM_VALUE.SAMPLE_DATA_WIDTH } {
|
||||
# Procedure called to update SAMPLE_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SAMPLE_DATA_WIDTH { PARAM_VALUE.SAMPLE_DATA_WIDTH } {
|
||||
# Procedure called to validate SAMPLE_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_CHANNELS { MODELPARAM_VALUE.NUM_OF_CHANNELS PARAM_VALUE.NUM_OF_CHANNELS } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_CHANNELS}] ${MODELPARAM_VALUE.NUM_OF_CHANNELS}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SAMPLES_PER_CHANNEL { MODELPARAM_VALUE.SAMPLES_PER_CHANNEL PARAM_VALUE.SAMPLES_PER_CHANNEL } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SAMPLES_PER_CHANNEL}] ${MODELPARAM_VALUE.SAMPLES_PER_CHANNEL}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SAMPLE_DATA_WIDTH { MODELPARAM_VALUE.SAMPLE_DATA_WIDTH PARAM_VALUE.SAMPLE_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SAMPLE_DATA_WIDTH}] ${MODELPARAM_VALUE.SAMPLE_DATA_WIDTH}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user