Archived
initial commit
This commit is contained in:
@@ -0,0 +1,20 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_adcfifo
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XILINX_DEPS += ../../common/ad_axis_inf_rx.v
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XILINX_DEPS += ../../common/ad_mem.v
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XILINX_DEPS += ../../common/ad_mem_asym.v
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XILINX_DEPS += ../../common/up_xfer_status.v
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XILINX_DEPS += axi_adcfifo.v
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XILINX_DEPS += axi_adcfifo_adc.v
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XILINX_DEPS += axi_adcfifo_constr.xdc
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XILINX_DEPS += axi_adcfifo_dma.v
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XILINX_DEPS += axi_adcfifo_ip.tcl
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XILINX_DEPS += axi_adcfifo_rd.v
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XILINX_DEPS += axi_adcfifo_wr.v
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include ../../scripts/library.mk
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@@ -0,0 +1,3 @@
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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eof:
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@@ -0,0 +1,6 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
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||||
<!-- -->
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<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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<labtools version="1" minor="0"/>
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@@ -0,0 +1,244 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
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||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
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||||
//
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||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
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||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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||||
//
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||||
// OR
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||||
//
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||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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||||
// This will allow to generate bit files and not release the source code,
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||||
// as long as it attaches to an ADI device.
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||||
//
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||||
// ***************************************************************************
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||||
// ***************************************************************************
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`timescale 1ns/100ps
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module axi_adcfifo #(
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parameter ADC_DATA_WIDTH = 128,
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parameter DMA_DATA_WIDTH = 64,
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parameter AXI_DATA_WIDTH = 512,
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parameter DMA_READY_ENABLE = 1,
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parameter AXI_SIZE = 2,
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parameter AXI_LENGTH = 16,
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parameter AXI_ADDRESS = 32'h00000000,
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parameter AXI_ADDRESS_LIMIT = 32'hffffffff) (
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// fifo interface
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input adc_rst,
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input adc_clk,
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input adc_wr,
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input [ADC_DATA_WIDTH-1:0] adc_wdata,
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output adc_wovf,
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// dma interface
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input dma_clk,
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output dma_wr,
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output [DMA_DATA_WIDTH-1:0] dma_wdata,
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input dma_wready,
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input dma_xfer_req,
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output [ 3:0] dma_xfer_status,
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// axi interface
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input axi_clk,
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input axi_resetn,
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output axi_awvalid,
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output [ 3:0] axi_awid,
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output [ 1:0] axi_awburst,
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output axi_awlock,
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output [ 3:0] axi_awcache,
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output [ 2:0] axi_awprot,
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output [ 3:0] axi_awqos,
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output [ 3:0] axi_awuser,
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output [ 7:0] axi_awlen,
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output [ 2:0] axi_awsize,
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output [ 31:0] axi_awaddr,
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input axi_awready,
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output axi_wvalid,
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output [AXI_DATA_WIDTH-1:0] axi_wdata,
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output [(AXI_DATA_WIDTH/8)-1:0] axi_wstrb,
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output axi_wlast,
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output [ 3:0] axi_wuser,
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input axi_wready,
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input axi_bvalid,
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input [ 3:0] axi_bid,
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input [ 1:0] axi_bresp,
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input [ 3:0] axi_buser,
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output axi_bready,
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output axi_arvalid,
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output [ 3:0] axi_arid,
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output [ 1:0] axi_arburst,
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output axi_arlock,
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output [ 3:0] axi_arcache,
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output [ 2:0] axi_arprot,
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output [ 3:0] axi_arqos,
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output [ 3:0] axi_aruser,
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output [ 7:0] axi_arlen,
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output [ 2:0] axi_arsize,
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output [ 31:0] axi_araddr,
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input axi_arready,
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input axi_rvalid,
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input [ 3:0] axi_rid,
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input [ 3:0] axi_ruser,
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input [ 1:0] axi_rresp,
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input axi_rlast,
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input [AXI_DATA_WIDTH-1:0] axi_rdata,
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output axi_rready);
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// internal signals
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wire adc_dwr_s;
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wire [AXI_DATA_WIDTH-1:0] adc_ddata_s;
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wire axi_rd_req_s;
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wire [ 31:0] axi_rd_addr_s;
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wire [ 3:0] axi_xfer_status_s;
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wire axi_drst_s;
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wire axi_dvalid_s;
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wire [AXI_DATA_WIDTH-1:0] axi_ddata_s;
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wire axi_dready_s;
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// instantiations
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axi_adcfifo_adc #(
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.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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.ADC_DATA_WIDTH (ADC_DATA_WIDTH))
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i_adc_if (
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||||
.adc_rst (adc_rst),
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.adc_clk (adc_clk),
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.adc_wr (adc_wr),
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.adc_wdata (adc_wdata),
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.adc_wovf (adc_wovf),
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.adc_dwr (adc_dwr_s),
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||||
.adc_ddata (adc_ddata_s),
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||||
.axi_drst (axi_drst_s),
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||||
.axi_clk (axi_clk),
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||||
.axi_xfer_status (axi_xfer_status_s));
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||||
axi_adcfifo_wr #(
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||||
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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||||
.AXI_SIZE (AXI_SIZE),
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||||
.AXI_LENGTH (AXI_LENGTH),
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||||
.AXI_ADDRESS (AXI_ADDRESS),
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||||
.AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT))
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||||
i_wr (
|
||||
.dma_xfer_req (dma_xfer_req),
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||||
.axi_rd_req (axi_rd_req_s),
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||||
.axi_rd_addr (axi_rd_addr_s),
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||||
.adc_rst (adc_rst),
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||||
.adc_clk (adc_clk),
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||||
.adc_wr (adc_dwr_s),
|
||||
.adc_wdata (adc_ddata_s),
|
||||
.axi_clk (axi_clk),
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||||
.axi_resetn (axi_resetn),
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||||
.axi_awvalid (axi_awvalid),
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||||
.axi_awid (axi_awid),
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||||
.axi_awburst (axi_awburst),
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||||
.axi_awlock (axi_awlock),
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||||
.axi_awcache (axi_awcache),
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||||
.axi_awprot (axi_awprot),
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||||
.axi_awqos (axi_awqos),
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||||
.axi_awuser (axi_awuser),
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||||
.axi_awlen (axi_awlen),
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||||
.axi_awsize (axi_awsize),
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||||
.axi_awaddr (axi_awaddr),
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||||
.axi_awready (axi_awready),
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||||
.axi_wvalid (axi_wvalid),
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||||
.axi_wdata (axi_wdata),
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||||
.axi_wstrb (axi_wstrb),
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||||
.axi_wlast (axi_wlast),
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.axi_wuser (axi_wuser),
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.axi_wready (axi_wready),
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.axi_bvalid (axi_bvalid),
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||||
.axi_bid (axi_bid),
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||||
.axi_bresp (axi_bresp),
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.axi_buser (axi_buser),
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.axi_bready (axi_bready),
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.axi_dwovf (axi_xfer_status_s[0]),
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.axi_dwunf (axi_xfer_status_s[1]),
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.axi_werror (axi_xfer_status_s[2]));
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axi_adcfifo_rd #(
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.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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.AXI_SIZE (AXI_SIZE),
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.AXI_LENGTH (AXI_LENGTH),
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||||
.AXI_ADDRESS (AXI_ADDRESS),
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||||
.AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT))
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i_rd (
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||||
.dma_xfer_req (dma_xfer_req),
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||||
.axi_rd_req (axi_rd_req_s),
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||||
.axi_rd_addr (axi_rd_addr_s),
|
||||
.axi_clk (axi_clk),
|
||||
.axi_resetn (axi_resetn),
|
||||
.axi_arvalid (axi_arvalid),
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||||
.axi_arid (axi_arid),
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||||
.axi_arburst (axi_arburst),
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||||
.axi_arlock (axi_arlock),
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||||
.axi_arcache (axi_arcache),
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||||
.axi_arprot (axi_arprot),
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||||
.axi_arqos (axi_arqos),
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||||
.axi_aruser (axi_aruser),
|
||||
.axi_arlen (axi_arlen),
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||||
.axi_arsize (axi_arsize),
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||||
.axi_araddr (axi_araddr),
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||||
.axi_arready (axi_arready),
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||||
.axi_rvalid (axi_rvalid),
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||||
.axi_rid (axi_rid),
|
||||
.axi_ruser (axi_ruser),
|
||||
.axi_rresp (axi_rresp),
|
||||
.axi_rlast (axi_rlast),
|
||||
.axi_rdata (axi_rdata),
|
||||
.axi_rready (axi_rready),
|
||||
.axi_rerror (axi_xfer_status_s[3]),
|
||||
.axi_drst (axi_drst_s),
|
||||
.axi_dvalid (axi_dvalid_s),
|
||||
.axi_ddata (axi_ddata_s),
|
||||
.axi_dready (axi_dready_s));
|
||||
|
||||
axi_adcfifo_dma #(
|
||||
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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||||
.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
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||||
.DMA_READY_ENABLE (DMA_READY_ENABLE))
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||||
i_dma_if (
|
||||
.axi_clk (axi_clk),
|
||||
.axi_drst (axi_drst_s),
|
||||
.axi_dvalid (axi_dvalid_s),
|
||||
.axi_ddata (axi_ddata_s),
|
||||
.axi_dready (axi_dready_s),
|
||||
.axi_xfer_status (axi_xfer_status_s),
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||||
.dma_clk (dma_clk),
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||||
.dma_wr (dma_wr),
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||||
.dma_wdata (dma_wdata),
|
||||
.dma_wready (dma_wready),
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||||
.dma_xfer_req (dma_xfer_req),
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||||
.dma_xfer_status (dma_xfer_status));
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endmodule
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||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,438 @@
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||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo/axi_adcfifo.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="91011c143373403ab5d16aaef6932b59"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
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<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
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<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
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||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
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<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
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<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
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||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
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<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../../ghdl/library"/>
|
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<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
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<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../common/ad_axis_inf_rx.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../common/ad_mem.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
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|
||||
</FileInfo>
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||||
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|
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<FileInfo>
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
<FileInfo>
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<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_adcfifo"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/axi_adcfifo_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,125 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_adcfifo_adc #(
|
||||
|
||||
parameter ADC_DATA_WIDTH = 128,
|
||||
parameter AXI_DATA_WIDTH = 512) (
|
||||
|
||||
// fifo interface
|
||||
|
||||
input adc_rst,
|
||||
input adc_clk,
|
||||
input adc_wr,
|
||||
input [ADC_DATA_WIDTH-1:0] adc_wdata,
|
||||
output reg adc_wovf,
|
||||
output reg adc_dwr,
|
||||
output reg [AXI_DATA_WIDTH-1:0] adc_ddata,
|
||||
|
||||
// axi interface
|
||||
|
||||
input axi_drst,
|
||||
input axi_clk,
|
||||
input [ 3:0] axi_xfer_status);
|
||||
|
||||
localparam ADC_MEM_RATIO = AXI_DATA_WIDTH/ADC_DATA_WIDTH;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [ 2:0] adc_wcnt_int = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [ 3:0] adc_xfer_status_s;
|
||||
|
||||
// write interface: supports only 64, 128, 256 and 512 against 512
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
if (adc_rst == 1'b1) begin
|
||||
adc_wovf <= 'd0;
|
||||
adc_wcnt_int <= 'd0;
|
||||
adc_dwr <= 'd0;
|
||||
adc_ddata <= 'd0;
|
||||
end else begin
|
||||
adc_wovf <= | adc_xfer_status_s;
|
||||
adc_dwr <= (ADC_MEM_RATIO == 8) ? adc_wr & adc_wcnt_int[0] & adc_wcnt_int[1] & adc_wcnt_int[2] :
|
||||
(ADC_MEM_RATIO == 4) ? adc_wr & adc_wcnt_int[0] & adc_wcnt_int[1] :
|
||||
(ADC_MEM_RATIO == 2) ? adc_wr & adc_wcnt_int[0] :
|
||||
(ADC_MEM_RATIO == 1) ? adc_wr : 'd0;
|
||||
if (adc_wr == 1'b1) begin
|
||||
adc_wcnt_int <= adc_wcnt_int + 1'b1;
|
||||
case (ADC_MEM_RATIO)
|
||||
8: begin
|
||||
adc_ddata[((ADC_DATA_WIDTH*8)-1):(ADC_DATA_WIDTH*7)] <= adc_wdata;
|
||||
adc_ddata[((ADC_DATA_WIDTH*7)-1):(ADC_DATA_WIDTH*0)] <=
|
||||
adc_ddata[((ADC_DATA_WIDTH*8)-1):(ADC_DATA_WIDTH*1)];
|
||||
end
|
||||
4: begin
|
||||
adc_ddata[((ADC_DATA_WIDTH*4)-1):(ADC_DATA_WIDTH*3)] <= adc_wdata;
|
||||
adc_ddata[((ADC_DATA_WIDTH*3)-1):(ADC_DATA_WIDTH*0)] <=
|
||||
adc_ddata[((ADC_DATA_WIDTH*4)-1):(ADC_DATA_WIDTH*1)];
|
||||
end
|
||||
2: begin
|
||||
adc_ddata[((ADC_DATA_WIDTH*2)-1):(ADC_DATA_WIDTH*1)] <= adc_wdata;
|
||||
adc_ddata[((ADC_DATA_WIDTH*1)-1):(ADC_DATA_WIDTH*0)] <=
|
||||
adc_ddata[((ADC_DATA_WIDTH*2)-1):(ADC_DATA_WIDTH*1)];
|
||||
end
|
||||
1: begin
|
||||
adc_ddata <= adc_wdata;
|
||||
end
|
||||
default: begin
|
||||
adc_ddata <= 'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// instantiations
|
||||
|
||||
up_xfer_status #(.DATA_WIDTH(4)) i_xfer_status (
|
||||
.up_rstn (~adc_rst),
|
||||
.up_clk (adc_clk),
|
||||
.up_data_status (adc_xfer_status_s),
|
||||
.d_rst (axi_drst),
|
||||
.d_clk (axi_clk),
|
||||
.d_data_status (axi_xfer_status));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,30 @@
|
||||
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -hier *axi_waddr_m1_reg*] \
|
||||
[get_cells -hier *axi_waddr_m2_reg*] \
|
||||
[get_cells -hier *adc_xfer_req_m_reg[0]*] \
|
||||
[get_cells -hier *axi_xfer_req_m_reg[0]*]
|
||||
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *dma_* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ *axi_*_m* && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *axi_* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ *dma_*_m* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *adc_* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ *axi_*_m* && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *axi_* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ *adc_*_m* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ *up_* && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ *d_xfer_* && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *adc_rel_waddr* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ *axi_rel_waddr* && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *axi_waddr_rel_reg* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ *dma_waddr_rel_reg* && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *dma_raddr_rel_reg* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ *axi_raddr_rel_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *adc_xfer_req_m_reg[0]* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *axi_xfer_req_m_reg[0]* && IS_SEQUENTIAL}]
|
||||
@@ -0,0 +1,227 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_adcfifo_dma #(
|
||||
|
||||
parameter AXI_DATA_WIDTH = 512,
|
||||
parameter DMA_DATA_WIDTH = 64,
|
||||
parameter DMA_READY_ENABLE = 1) (
|
||||
|
||||
input axi_clk,
|
||||
input axi_drst,
|
||||
input axi_dvalid,
|
||||
input [AXI_DATA_WIDTH-1:0] axi_ddata,
|
||||
output reg axi_dready,
|
||||
input [ 3:0] axi_xfer_status,
|
||||
|
||||
input dma_clk,
|
||||
output dma_wr,
|
||||
output [DMA_DATA_WIDTH-1:0] dma_wdata,
|
||||
input dma_wready,
|
||||
input dma_xfer_req,
|
||||
output [ 3:0] dma_xfer_status);
|
||||
|
||||
|
||||
localparam DMA_MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH;
|
||||
localparam DMA_ADDRESS_WIDTH = 8;
|
||||
localparam AXI_ADDRESS_WIDTH = (DMA_MEM_RATIO == 2) ? (DMA_ADDRESS_WIDTH - 1) :
|
||||
((DMA_MEM_RATIO == 4) ? (DMA_ADDRESS_WIDTH - 2) : (DMA_ADDRESS_WIDTH - 3));
|
||||
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [AXI_ADDRESS_WIDTH-1:0] axi_waddr = 'd0;
|
||||
reg [ 2:0] axi_waddr_rel_count = 'd0;
|
||||
reg axi_waddr_rel_t = 'd0;
|
||||
reg [AXI_ADDRESS_WIDTH-1:0] axi_waddr_rel = 'd0;
|
||||
reg [ 2:0] axi_raddr_rel_t_m = 'd0;
|
||||
reg [DMA_ADDRESS_WIDTH-1:0] axi_raddr_rel = 'd0;
|
||||
reg [DMA_ADDRESS_WIDTH-1:0] axi_addr_diff = 'd0;
|
||||
reg dma_rst = 'd0;
|
||||
reg [ 2:0] dma_waddr_rel_t_m = 'd0;
|
||||
reg [AXI_ADDRESS_WIDTH-1:0] dma_waddr_rel = 'd0;
|
||||
reg dma_rd = 'd0;
|
||||
reg dma_rd_d = 'd0;
|
||||
reg [DMA_DATA_WIDTH-1:0] dma_rdata_d = 'd0;
|
||||
reg [DMA_ADDRESS_WIDTH-1:0] dma_raddr = 'd0;
|
||||
reg [ 2:0] dma_raddr_rel_count = 'd0;
|
||||
reg dma_raddr_rel_t = 'd0;
|
||||
reg [DMA_ADDRESS_WIDTH-1:0] dma_raddr_rel = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [DMA_ADDRESS_WIDTH:0] axi_addr_diff_s;
|
||||
wire axi_raddr_rel_t_s;
|
||||
wire [DMA_ADDRESS_WIDTH-1:0] axi_waddr_s;
|
||||
wire dma_waddr_rel_t_s;
|
||||
wire [DMA_ADDRESS_WIDTH-1:0] dma_waddr_rel_s;
|
||||
wire dma_wready_s;
|
||||
wire dma_rd_s;
|
||||
wire [DMA_DATA_WIDTH-1:0] dma_rdata_s;
|
||||
|
||||
// write interface
|
||||
|
||||
always @(posedge axi_clk) begin
|
||||
if (axi_drst == 1'b1) begin
|
||||
axi_waddr <= 'd0;
|
||||
axi_waddr_rel_count <= 'd0;
|
||||
axi_waddr_rel_t <= 'd0;
|
||||
axi_waddr_rel <= 'd0;
|
||||
end else begin
|
||||
if (axi_dvalid == 1'b1) begin
|
||||
axi_waddr <= axi_waddr + 1'b1;
|
||||
end
|
||||
axi_waddr_rel_count <= axi_waddr_rel_count + 1'b1;
|
||||
if (axi_waddr_rel_count == 3'd7) begin
|
||||
axi_waddr_rel_t <= ~axi_waddr_rel_t;
|
||||
axi_waddr_rel <= axi_waddr;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign axi_addr_diff_s = {1'b1, axi_waddr_s} - axi_raddr_rel;
|
||||
assign axi_raddr_rel_t_s = axi_raddr_rel_t_m[2] ^ axi_raddr_rel_t_m[1];
|
||||
assign axi_waddr_s = (DMA_MEM_RATIO == 2) ? {axi_waddr, 1'd0} :
|
||||
((DMA_MEM_RATIO == 4) ? {axi_waddr, 2'd0} : {axi_waddr, 3'd0});
|
||||
|
||||
always @(posedge axi_clk) begin
|
||||
if (axi_drst == 1'b1) begin
|
||||
axi_raddr_rel_t_m <= 'd0;
|
||||
axi_raddr_rel <= 'd0;
|
||||
axi_addr_diff <= 'd0;
|
||||
axi_dready <= 'd0;
|
||||
end else begin
|
||||
axi_raddr_rel_t_m <= {axi_raddr_rel_t_m[1:0], dma_raddr_rel_t};
|
||||
if (axi_raddr_rel_t_s == 1'b1) begin
|
||||
axi_raddr_rel <= dma_raddr_rel;
|
||||
end
|
||||
axi_addr_diff <= axi_addr_diff_s[DMA_ADDRESS_WIDTH-1:0];
|
||||
if (axi_addr_diff >= 180) begin
|
||||
axi_dready <= 1'b0;
|
||||
end else if (axi_addr_diff <= 8) begin
|
||||
axi_dready <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// read interface
|
||||
|
||||
assign dma_waddr_rel_t_s = dma_waddr_rel_t_m[2] ^ dma_waddr_rel_t_m[1];
|
||||
assign dma_waddr_rel_s = (DMA_MEM_RATIO == 2) ? {dma_waddr_rel, 1'd0} :
|
||||
((DMA_MEM_RATIO == 4) ? {dma_waddr_rel, 2'd0} : {dma_waddr_rel, 3'd0});
|
||||
|
||||
always @(posedge dma_clk) begin
|
||||
if (dma_xfer_req == 1'b0) begin
|
||||
dma_rst <= 1'b1;
|
||||
dma_waddr_rel_t_m <= 'd0;
|
||||
dma_waddr_rel <= 'd0;
|
||||
end else begin
|
||||
dma_rst <= 1'b0;
|
||||
dma_waddr_rel_t_m <= {dma_waddr_rel_t_m[1:0], axi_waddr_rel_t};
|
||||
if (dma_waddr_rel_t_s == 1'b1) begin
|
||||
dma_waddr_rel <= axi_waddr_rel;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign dma_wready_s = (DMA_READY_ENABLE == 0) ? 1'b1 : dma_wready;
|
||||
assign dma_rd_s = (dma_raddr == dma_waddr_rel_s) ? 1'b0 : dma_wready_s;
|
||||
|
||||
always @(posedge dma_clk) begin
|
||||
if (dma_xfer_req == 1'b0) begin
|
||||
dma_rd <= 'd0;
|
||||
dma_rd_d <= 'd0;
|
||||
dma_rdata_d <= 'd0;
|
||||
dma_raddr <= 'd0;
|
||||
dma_raddr_rel_count <= 'd0;
|
||||
dma_raddr_rel_t <= 'd0;
|
||||
dma_raddr_rel <= 'd0;
|
||||
end else begin
|
||||
dma_rd <= dma_rd_s;
|
||||
dma_rd_d <= dma_rd;
|
||||
dma_rdata_d <= dma_rdata_s;
|
||||
if (dma_rd_s == 1'b1) begin
|
||||
dma_raddr <= dma_raddr + 1'b1;
|
||||
end
|
||||
dma_raddr_rel_count <= dma_raddr_rel_count + 1'b1;
|
||||
if (dma_raddr_rel_count == 3'd7) begin
|
||||
dma_raddr_rel_t <= ~dma_raddr_rel_t;
|
||||
dma_raddr_rel <= dma_raddr;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// instantiations
|
||||
|
||||
ad_mem_asym #(
|
||||
.A_ADDRESS_WIDTH (AXI_ADDRESS_WIDTH),
|
||||
.A_DATA_WIDTH (AXI_DATA_WIDTH),
|
||||
.B_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH),
|
||||
.B_DATA_WIDTH (DMA_DATA_WIDTH))
|
||||
i_mem_asym (
|
||||
.clka (axi_clk),
|
||||
.wea (axi_dvalid),
|
||||
.addra (axi_waddr),
|
||||
.dina (axi_ddata),
|
||||
.clkb (dma_clk),
|
||||
.reb (1'b1),
|
||||
.addrb (dma_raddr),
|
||||
.doutb (dma_rdata_s));
|
||||
|
||||
ad_axis_inf_rx #(.DATA_WIDTH(DMA_DATA_WIDTH)) i_axis_inf (
|
||||
.clk (dma_clk),
|
||||
.rst (dma_rst),
|
||||
.valid (dma_rd_d),
|
||||
.last (1'd0),
|
||||
.data (dma_rdata_d),
|
||||
.inf_valid (dma_wr),
|
||||
.inf_last (),
|
||||
.inf_data (dma_wdata),
|
||||
.inf_ready (dma_wready));
|
||||
|
||||
up_xfer_status #(.DATA_WIDTH(4)) i_xfer_status (
|
||||
.up_rstn (~dma_rst),
|
||||
.up_clk (dma_clk),
|
||||
.up_data_status (dma_xfer_status),
|
||||
.d_rst (axi_drst),
|
||||
.d_clk (axi_clk),
|
||||
.d_data_status (axi_xfer_status));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,811 @@
|
||||
|
||||
****** Vivado v2019.1.3 (64-bit)
|
||||
**** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
**** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
source axi_adcfifo_ip.tcl
|
||||
# source ../../scripts/adi_env.tcl
|
||||
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
|
||||
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
|
||||
## if [info exists ::env(ADI_HDL_DIR)] {
|
||||
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
|
||||
## }
|
||||
## if [info exists ::env(ADI_GHDL_DIR)] {
|
||||
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
|
||||
## }
|
||||
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
|
||||
### variable auto_set_param_list
|
||||
### variable auto_set_param_list_overwritable
|
||||
### variable fpga_series_list
|
||||
### variable fpga_family_list
|
||||
### variable speed_grade_list
|
||||
### variable dev_package_list
|
||||
### variable xcvr_type_list
|
||||
### variable fpga_voltage_list
|
||||
### set auto_set_param_list { \
|
||||
### DEV_PACKAGE \
|
||||
### SPEED_GRADE \
|
||||
### FPGA_FAMILY \
|
||||
### FPGA_TECHNOLOGY }
|
||||
### set auto_set_param_list_overwritable { \
|
||||
### FPGA_VOLTAGE \
|
||||
### XCVR_TYPE }
|
||||
### set fpga_technology_list { \
|
||||
### { Unknown 0 } \
|
||||
### { 7series 1 } \
|
||||
### { ultrascale 2 } \
|
||||
### { ultrascale+ 3 }}
|
||||
### set fpga_family_list { \
|
||||
### { Unknown 0 } \
|
||||
### { artix 1 } \
|
||||
### { kintex 2 } \
|
||||
### { virtex 3 } \
|
||||
### { zynq 4 }}
|
||||
### set speed_grade_list { \
|
||||
### { Unknown 0 } \
|
||||
### { -1 10 } \
|
||||
### { -1L 11 } \
|
||||
### { -1H 12 } \
|
||||
### { -1HV 13 } \
|
||||
### { -1LV 14 } \
|
||||
### { -2 20 } \
|
||||
### { -2L 21 } \
|
||||
### { -2LV 22 } \
|
||||
### { -3 30 }}
|
||||
### set dev_package_list { \
|
||||
### { Unknown 0 } \
|
||||
### { rf 1 } \
|
||||
### { fl 2 } \
|
||||
### { ff 3 } \
|
||||
### { fb 4 } \
|
||||
### { hc 5 } \
|
||||
### { fh 6 } \
|
||||
### { cs 7 } \
|
||||
### { cp 8 } \
|
||||
### { ft 9 } \
|
||||
### { fg 10 } \
|
||||
### { sb 11 } \
|
||||
### { rb 12 } \
|
||||
### { rs 13 } \
|
||||
### { cl 14 } \
|
||||
### { sf 15 } \
|
||||
### { ba 16 } \
|
||||
### { fa 17 } \
|
||||
### { fs 18 } \
|
||||
### { fi 19 }}
|
||||
### set xcvr_type_list { \
|
||||
### { Unknown 0 } \
|
||||
### { GTPE2_NOT_SUPPORTED 1 } \
|
||||
### { GTXE2 2 } \
|
||||
### { GTHE2_NOT_SUPPORTED 3 } \
|
||||
### { GTZE2_NOT_SUPPORTED 4 } \
|
||||
### { GTHE3 5 } \
|
||||
### { GTYE3_NOT_SUPPORTED 6 } \
|
||||
### { GTRE4_NOT_SUPPORTED 7 } \
|
||||
### { GTHE4 8 } \
|
||||
### { GTYE4 9 } \
|
||||
### { GTME4_NOT_SUPPORTED 10}}
|
||||
### set fpga_voltage_list {0 5000} ;
|
||||
### proc adi_device_spec {cellpath param} {
|
||||
###
|
||||
### set list_pointer [string tolower $param]
|
||||
### set list_pointer [append list_pointer "_list"]
|
||||
###
|
||||
### upvar 1 $list_pointer $list_pointer
|
||||
###
|
||||
### set ip [get_bd_cells $cellpath]
|
||||
### set part [get_property PART [current_project]]
|
||||
###
|
||||
### switch -regexp -- $param {
|
||||
### FPGA_TECHNOLOGY {
|
||||
### switch -regexp -- $part {
|
||||
### ^xc7 {set series_name 7series}
|
||||
### ^xczu {set series_name ultrascale+}
|
||||
### ^xc.u.p {set series_name ultrascale+}
|
||||
### ^xc.u {set series_name ultrascale }
|
||||
### default {
|
||||
### puts "Undefined fpga technology for \"$part\"!"
|
||||
### exit -1
|
||||
### }
|
||||
### }
|
||||
### return "$series_name"
|
||||
### }
|
||||
### FPGA_FAMILY {
|
||||
### set fpga_family [get_property FAMILY $part]
|
||||
### foreach i $fpga_family_list {
|
||||
### regexp ^[lindex $i 0] $fpga_family matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### SPEED_GRADE {
|
||||
### set speed_grade [get_property SPEED $part]
|
||||
### return "$speed_grade"
|
||||
### }
|
||||
### DEV_PACKAGE {
|
||||
### set dev_package [get_property PACKAGE $part]
|
||||
### foreach i $dev_package_list {
|
||||
### regexp ^[lindex $i 0] $dev_package matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### XCVR_TYPE {
|
||||
### set matched ""
|
||||
### set dev_transcivers "none"
|
||||
### foreach x [list_property $part] {
|
||||
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
|
||||
### }
|
||||
### foreach i $xcvr_type_list {
|
||||
### regexp ^[lindex $i 0] $dev_transcivers matched
|
||||
### }
|
||||
### if { $matched eq "" } {
|
||||
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### FPGA_VOLTAGE {
|
||||
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
|
||||
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
|
||||
###
|
||||
### return "$fpga_voltage"
|
||||
### }
|
||||
### default {
|
||||
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
|
||||
### }
|
||||
### }
|
||||
### }
|
||||
## if {![info exists REQUIRED_VIVADO_VERSION]} {
|
||||
## set REQUIRED_VIVADO_VERSION "2019.1"
|
||||
## }
|
||||
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
|
||||
## set IGNORE_VERSION_CHECK 1
|
||||
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
|
||||
## set IGNORE_VERSION_CHECK 0
|
||||
## }
|
||||
## proc adi_ip_ttcl {ip_name ip_constr_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
|
||||
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_sim_ttcl {ip_name ip_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
|
||||
## set f [ipx::add_file $ip_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_bd {ip_name ip_bd_files} {
|
||||
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
|
||||
## if {$proj_filegroup == {}} {
|
||||
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
|
||||
## }
|
||||
##
|
||||
## foreach file $ip_bd_files {
|
||||
## set f [ipx::add_file $file $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type tclSource \
|
||||
## ] $f
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_infer_streaming_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_ip_infer_mm_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
|
||||
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency $port
|
||||
## if {$driver_value != {}} {
|
||||
## set_property DRIVER_VALUE $driver_value $port
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_set_bus_dependency {bus prefix dependency} {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
|
||||
## adi_set_ports_dependency $prefix $dependency 0
|
||||
## }
|
||||
## proc adi_add_port_map {bus phys logic} {
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## }
|
||||
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## adi_add_port_map $bus {*}$port_map
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
|
||||
## for {set i 0} {$i < $num} {incr i} {
|
||||
## set bus_name [format "%s%d" $bus_name_prefix $i]
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## if {$dependency ne ""} {
|
||||
## set bus_dependency [string map [list "{i}" $i] $dependency]
|
||||
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
|
||||
## }
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## lassign $port_map phys logic width width_dep
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
|
||||
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
|
||||
## if {$width_dep ne ""} {
|
||||
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
|
||||
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
|
||||
## set width_dep_r "(($width_dep) * $i)"
|
||||
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
|
||||
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
|
||||
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
|
||||
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
|
||||
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
|
||||
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
|
||||
## set_property display_name $clock_inf_name $clock_inf
|
||||
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
|
||||
## set_property physical_name $clock_signal_name $clock_map
|
||||
##
|
||||
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
|
||||
## set_property value $bus_inf_name $assoc_busif
|
||||
##
|
||||
## if { $reset_signal_name != "" } {
|
||||
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
|
||||
## set_property value $reset_signal_name $assoc_reset
|
||||
##
|
||||
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
|
||||
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
|
||||
## set_property display_name $reset_inf_name $reset_inf
|
||||
## set_property interface_mode $reset_signal_mode $reset_inf
|
||||
## set reset_map [ipx::add_port_map "RST" $reset_inf]
|
||||
## set_property physical_name $reset_signal_name $reset_map
|
||||
##
|
||||
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
|
||||
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
|
||||
## set_property value "ACTIVE_LOW" $reset_polarity
|
||||
## } else {
|
||||
## set_property value "ACTIVE_HIGH" $reset_polarity
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_add_core_dependencies {vlnvs} {
|
||||
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
|
||||
## foreach vlnv $vlnvs {
|
||||
## ipx::add_subcore $vlnv $file_group
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_create {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
## global ad_ghdl_dir
|
||||
## global REQUIRED_VIVADO_VERSION
|
||||
## global IGNORE_VERSION_CHECK
|
||||
##
|
||||
## set VIVADO_VERSION [version -short]
|
||||
## if {$IGNORE_VERSION_CHECK} {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## }
|
||||
## } else {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "ERROR: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
|
||||
## exit 2
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## create_project $ip_name . -force
|
||||
##
|
||||
## ## Load custom message severity definitions
|
||||
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
|
||||
##
|
||||
## set lib_dirs $ad_hdl_dir/library
|
||||
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
|
||||
## lappend lib_dirs $ad_ghdl_dir/library
|
||||
## }
|
||||
##
|
||||
## set_property ip_repo_paths $lib_dirs [current_fileset]
|
||||
## update_ip_catalog
|
||||
## }
|
||||
## proc adi_ip_files {ip_name ip_files} {
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## foreach m_file $ip_files {
|
||||
## if {[file extension $m_file] eq ".xdc"} {
|
||||
## add_files -norecurse -fileset constrs_1 $m_file
|
||||
## } else {
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
|
||||
## }
|
||||
## }
|
||||
## set_property "top" "$ip_name" $proj_fileset
|
||||
## }
|
||||
## proc adi_ip_properties_lite {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
##
|
||||
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
|
||||
##
|
||||
## set_property name $ip_name [ipx::current_core]
|
||||
##
|
||||
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
|
||||
## set_property company_url {http://www.analog.com} [ipx::current_core]
|
||||
##
|
||||
## set i_families ""
|
||||
## foreach i_part [get_parts] {
|
||||
## lappend i_families [get_property FAMILY $i_part]
|
||||
## }
|
||||
## set i_families [lsort -unique $i_families]
|
||||
## set s_families [get_property supported_families [ipx::current_core]]
|
||||
## foreach i_family $i_families {
|
||||
## set s_families "$s_families $i_family Production"
|
||||
## set s_families "$s_families $i_family Beta"
|
||||
## }
|
||||
## set_property supported_families $s_families [ipx::current_core]
|
||||
##
|
||||
## ipx::save_core [ipx::current_core]
|
||||
##
|
||||
## ipx::remove_all_bus_interface [ipx::current_core]
|
||||
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
|
||||
## foreach map $memory_maps {
|
||||
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
|
||||
## }
|
||||
##
|
||||
## ipx::update_checksums [ipx::current_core]
|
||||
## ipx::save_core [ipx::current_core]
|
||||
## }
|
||||
## proc adi_ip_properties {ip_name} {
|
||||
##
|
||||
## adi_ip_properties_lite $ip_name
|
||||
##
|
||||
## ipx::infer_bus_interface {\
|
||||
## s_axi_awvalid \
|
||||
## s_axi_awaddr \
|
||||
## s_axi_awprot \
|
||||
## s_axi_awready \
|
||||
## s_axi_wvalid \
|
||||
## s_axi_wdata \
|
||||
## s_axi_wstrb \
|
||||
## s_axi_wready \
|
||||
## s_axi_bvalid \
|
||||
## s_axi_bresp \
|
||||
##
|
||||
## s_axi_bready \
|
||||
## s_axi_arvalid \
|
||||
## s_axi_araddr \
|
||||
## s_axi_arprot \
|
||||
## s_axi_arready \
|
||||
## s_axi_rvalid \
|
||||
## s_axi_rdata \
|
||||
## s_axi_rresp \
|
||||
## s_axi_rready} \
|
||||
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
|
||||
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
|
||||
##
|
||||
## if {$raddr_width != $waddr_width} {
|
||||
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
|
||||
## set range 65536
|
||||
## } else {
|
||||
## if {$raddr_width >= 16} {
|
||||
## set range 65536
|
||||
## } else {
|
||||
## set range [expr 1 << $raddr_width]
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
## set_property range $range [ipx::get_address_blocks axi_lite \
|
||||
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
|
||||
## ipx::save_core
|
||||
## }
|
||||
## proc adi_init_bd_tcl {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## if { [file exists bd] } {
|
||||
## file delete -force bd
|
||||
## }
|
||||
## file mkdir bd
|
||||
##
|
||||
## set bd_tcl [open "bd/bd.tcl" w]
|
||||
##
|
||||
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
|
||||
## puts $bd_tcl "proc init {cellpath otherInfo} {"
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl ""
|
||||
## set auto_set_param ""
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
|
||||
## puts $bd_tcl $auto_set_param
|
||||
## }
|
||||
##
|
||||
## set auto_set_overwritable_param ""
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_overwritable_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_overwritable_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
|
||||
## puts $bd_tcl $auto_set_overwritable_param
|
||||
## }
|
||||
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
|
||||
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
|
||||
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set parent_dir \"../\""
|
||||
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
|
||||
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
|
||||
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " break"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " append parent_dir \"../\""
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## close $bd_tcl
|
||||
##
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
|
||||
##
|
||||
## set local_mk [open "temporary_case_dependencies.mk" w]
|
||||
## seek $local_mk 0 start
|
||||
## puts $local_mk "CLEAN_TARGET += bd"
|
||||
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
|
||||
## close $local_mk
|
||||
## }
|
||||
## proc adi_add_auto_fpga_spec_params {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_device_spec_param {ip_param} {
|
||||
##
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## set list_pointer [string tolower $ip_param]
|
||||
## set list_pointer [append list_pointer "_list"]
|
||||
##
|
||||
## global $list_pointer
|
||||
##
|
||||
## # set j 1D list from the original list
|
||||
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
|
||||
##
|
||||
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
|
||||
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "range_long" \
|
||||
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
|
||||
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## } else {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "pairs" \
|
||||
## "value_validation_pairs" $j ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## }
|
||||
##
|
||||
## # FPGA info grup
|
||||
## set info_group_name "FPGA info"
|
||||
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
|
||||
## if { [string trim $info_group] eq "" } {
|
||||
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
|
||||
## -parent $page0 -display_name $info_group_name]
|
||||
## }
|
||||
##
|
||||
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
|
||||
## set_property -dict [list "widget" "comboBox" ] $p
|
||||
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
|
||||
## }
|
||||
## proc adi_if_define {name} {
|
||||
##
|
||||
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
|
||||
## ipx::create_bus_definition analog.com interface $name 1.0
|
||||
##
|
||||
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
|
||||
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
|
||||
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
|
||||
##
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## }
|
||||
## proc adi_if_ports {dir width name {type none}} {
|
||||
##
|
||||
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
|
||||
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
|
||||
## set_property master_presence required $m_intf
|
||||
## set_property slave_presence required $m_intf
|
||||
## set_property master_width $width $m_intf
|
||||
## set_property slave_width $width $m_intf
|
||||
##
|
||||
## set m_dir "in"
|
||||
## set s_dir "out"
|
||||
## if {$dir eq "output"} {
|
||||
## set m_dir "out"
|
||||
## set s_dir "in"
|
||||
## }
|
||||
##
|
||||
## set_property master_direction $m_dir $m_intf
|
||||
## set_property slave_direction $s_dir $m_intf
|
||||
##
|
||||
## if {$type ne "none"} {
|
||||
## set_property is_${type} true $m_intf
|
||||
## }
|
||||
##
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## }
|
||||
## proc adi_if_infer_bus {if_name mode name maps} {
|
||||
##
|
||||
## ipx::add_bus_interface $name [ipx::current_core]
|
||||
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
|
||||
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
|
||||
## set_property interface_mode $mode $m_bus_if
|
||||
##
|
||||
## foreach map $maps {
|
||||
## set m_maps [regexp -all -inline {\S+} $map]
|
||||
## lassign $m_maps p_name p_map
|
||||
## ipx::add_port_map $p_name $m_bus_if
|
||||
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
|
||||
## }
|
||||
## }
|
||||
# adi_ip_create axi_adcfifo
|
||||
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
|
||||
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1343} -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1306} -new_severity WARNING
|
||||
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
|
||||
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
|
||||
## set_msg_config -id {Synth 8-3331} -new_severity INFO
|
||||
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
|
||||
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
|
||||
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
|
||||
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'.)
|
||||
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
|
||||
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
|
||||
# adi_ip_files axi_adcfifo [list \
|
||||
# "$ad_hdl_dir/library/common/ad_mem.v" \
|
||||
# "$ad_hdl_dir/library/common/ad_mem_asym.v" \
|
||||
# "$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
# "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
|
||||
# "axi_adcfifo_adc.v" \
|
||||
# "axi_adcfifo_dma.v" \
|
||||
# "axi_adcfifo_wr.v" \
|
||||
# "axi_adcfifo_rd.v" \
|
||||
# "axi_adcfifo.v" \
|
||||
# "axi_adcfifo_constr.xdc" ]
|
||||
# adi_ip_properties_lite axi_adcfifo
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_axis_inf_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_axis_inf_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5150] The Range '(AXI_DATA_WIDTH - 1):0' is present in all ports of the interface 'axi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port rdata on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'adc' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5150] The Range '(AXI_DATA_WIDTH - 1):0' is present in all ports of the interface 'axi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5150] The Range '(ADC_DATA_WIDTH - 1):0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'axi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'axi_resetn'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_xfer_req' and definition port 'XFER_REQ'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'dma': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'dma': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "rdata" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'axi_wdata' and definition port 'wdata'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'axi_rdata' and definition port 'rdata'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'axi_clk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'dma_clk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
# ipx::infer_bus_interface {\
|
||||
# axi_awvalid \
|
||||
# axi_awid \
|
||||
# axi_awburst \
|
||||
# axi_awlock \
|
||||
# axi_awcache \
|
||||
# axi_awprot \
|
||||
# axi_awqos \
|
||||
# axi_awuser \
|
||||
# axi_awlen \
|
||||
# axi_awsize \
|
||||
# axi_awaddr \
|
||||
# axi_awready \
|
||||
# axi_wvalid \
|
||||
# axi_wdata \
|
||||
# axi_wstrb \
|
||||
# axi_wlast \
|
||||
# axi_wuser \
|
||||
# axi_wready \
|
||||
# axi_bvalid \
|
||||
# axi_bid \
|
||||
# axi_bresp \
|
||||
# axi_buser \
|
||||
# axi_bready \
|
||||
# axi_arvalid \
|
||||
# axi_arid \
|
||||
# axi_arburst \
|
||||
# axi_arlock \
|
||||
# axi_arcache \
|
||||
# axi_arprot \
|
||||
# axi_arqos \
|
||||
# axi_aruser \
|
||||
# axi_arlen \
|
||||
# axi_arsize \
|
||||
# axi_araddr \
|
||||
# axi_arready \
|
||||
# axi_rvalid \
|
||||
# axi_rid \
|
||||
# axi_ruser \
|
||||
# axi_rresp \
|
||||
# axi_rlast \
|
||||
# axi_rdata \
|
||||
# axi_rready} \
|
||||
# xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument).
|
||||
# ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'axi'.
|
||||
# ipx::infer_bus_interface axi_resetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_resetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'axi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'axi_resetn'.
|
||||
# ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \
|
||||
# -of_objects [ipx::current_core]]
|
||||
# set_property value axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
|
||||
# -of_objects [ipx::get_bus_interfaces axi_clk \
|
||||
# -of_objects [ipx::current_core]]]
|
||||
# ipx::add_address_space axi [ipx::current_core]
|
||||
# set_property master_address_space_ref axi [ipx::get_bus_interfaces axi \
|
||||
# -of_objects [ipx::current_core]]
|
||||
# set_property range 4294967296 [ipx::get_address_spaces axi \
|
||||
# -of_objects [ipx::current_core]]
|
||||
# set_property width 512 [ipx::get_address_spaces axi \
|
||||
# -of_objects [ipx::current_core]]
|
||||
# ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
# ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'.
|
||||
# ipx::save_core [ipx::current_core]
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:20:07 2021...
|
||||
@@ -0,0 +1,87 @@
|
||||
# ip
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_adcfifo
|
||||
adi_ip_files axi_adcfifo [list \
|
||||
"$ad_hdl_dir/library/common/ad_mem.v" \
|
||||
"$ad_hdl_dir/library/common/ad_mem_asym.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
"$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
|
||||
"axi_adcfifo_adc.v" \
|
||||
"axi_adcfifo_dma.v" \
|
||||
"axi_adcfifo_wr.v" \
|
||||
"axi_adcfifo_rd.v" \
|
||||
"axi_adcfifo.v" \
|
||||
"axi_adcfifo_constr.xdc" ]
|
||||
|
||||
adi_ip_properties_lite axi_adcfifo
|
||||
|
||||
ipx::infer_bus_interface {\
|
||||
axi_awvalid \
|
||||
axi_awid \
|
||||
axi_awburst \
|
||||
axi_awlock \
|
||||
axi_awcache \
|
||||
axi_awprot \
|
||||
axi_awqos \
|
||||
axi_awuser \
|
||||
axi_awlen \
|
||||
axi_awsize \
|
||||
axi_awaddr \
|
||||
axi_awready \
|
||||
axi_wvalid \
|
||||
axi_wdata \
|
||||
axi_wstrb \
|
||||
axi_wlast \
|
||||
axi_wuser \
|
||||
axi_wready \
|
||||
axi_bvalid \
|
||||
axi_bid \
|
||||
axi_bresp \
|
||||
axi_buser \
|
||||
axi_bready \
|
||||
axi_arvalid \
|
||||
axi_arid \
|
||||
axi_arburst \
|
||||
axi_arlock \
|
||||
axi_arcache \
|
||||
axi_arprot \
|
||||
axi_arqos \
|
||||
axi_aruser \
|
||||
axi_arlen \
|
||||
axi_arsize \
|
||||
axi_araddr \
|
||||
axi_arready \
|
||||
axi_rvalid \
|
||||
axi_rid \
|
||||
axi_ruser \
|
||||
axi_rresp \
|
||||
axi_rlast \
|
||||
axi_rdata \
|
||||
axi_rready} \
|
||||
xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
|
||||
ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface axi_resetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \
|
||||
-of_objects [ipx::current_core]]
|
||||
set_property value axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
|
||||
-of_objects [ipx::get_bus_interfaces axi_clk \
|
||||
-of_objects [ipx::current_core]]]
|
||||
|
||||
ipx::add_address_space axi [ipx::current_core]
|
||||
set_property master_address_space_ref axi [ipx::get_bus_interfaces axi \
|
||||
-of_objects [ipx::current_core]]
|
||||
set_property range 4294967296 [ipx::get_address_spaces axi \
|
||||
-of_objects [ipx::current_core]]
|
||||
set_property width 512 [ipx::get_address_spaces axi \
|
||||
-of_objects [ipx::current_core]]
|
||||
|
||||
ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
@@ -0,0 +1,202 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_adcfifo_rd #(
|
||||
|
||||
parameter AXI_DATA_WIDTH = 512,
|
||||
parameter AXI_SIZE = 2,
|
||||
parameter AXI_LENGTH = 16,
|
||||
parameter AXI_ADDRESS = 32'h00000000,
|
||||
parameter AXI_ADDRESS_LIMIT = 32'h00000000) (
|
||||
|
||||
// request and synchronization
|
||||
|
||||
input dma_xfer_req,
|
||||
|
||||
// read interface
|
||||
|
||||
input axi_rd_req,
|
||||
input [ 31:0] axi_rd_addr,
|
||||
|
||||
// axi interface
|
||||
|
||||
input axi_clk,
|
||||
input axi_resetn,
|
||||
output reg axi_arvalid,
|
||||
output [ 3:0] axi_arid,
|
||||
output [ 1:0] axi_arburst,
|
||||
output axi_arlock,
|
||||
output [ 3:0] axi_arcache,
|
||||
output [ 2:0] axi_arprot,
|
||||
output [ 3:0] axi_arqos,
|
||||
output [ 3:0] axi_aruser,
|
||||
output [ 7:0] axi_arlen,
|
||||
output [ 2:0] axi_arsize,
|
||||
output reg [ 31:0] axi_araddr,
|
||||
input axi_arready,
|
||||
input axi_rvalid,
|
||||
input [ 3:0] axi_rid,
|
||||
input [ 3:0] axi_ruser,
|
||||
input [ 1:0] axi_rresp,
|
||||
input axi_rlast,
|
||||
input [AXI_DATA_WIDTH-1:0] axi_rdata,
|
||||
output reg axi_rready,
|
||||
|
||||
// axi status
|
||||
|
||||
output reg axi_rerror,
|
||||
|
||||
// fifo interface
|
||||
|
||||
output reg axi_drst,
|
||||
output reg axi_dvalid,
|
||||
output reg [AXI_DATA_WIDTH-1:0] axi_ddata,
|
||||
input axi_dready);
|
||||
|
||||
localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
|
||||
localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH;
|
||||
localparam BUF_THRESHOLD_LO = 6'd3;
|
||||
localparam BUF_THRESHOLD_HI = 6'd60;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [ 31:0] axi_rd_addr_h = 'd0;
|
||||
reg axi_rd = 'd0;
|
||||
reg axi_rd_active = 'd0;
|
||||
reg [ 2:0] axi_xfer_req_m = 'd0;
|
||||
reg axi_xfer_init = 'd0;
|
||||
reg axi_xfer_enable = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire axi_ready_s;
|
||||
|
||||
// read is way too slow- buffer mode
|
||||
|
||||
assign axi_ready_s = (~axi_arvalid | axi_arready) & axi_dready;
|
||||
|
||||
always @(posedge axi_clk or negedge axi_resetn) begin
|
||||
if (axi_resetn == 1'b0) begin
|
||||
axi_rd_addr_h <= 'd0;
|
||||
axi_rd <= 'd0;
|
||||
axi_rd_active <= 'd0;
|
||||
axi_xfer_req_m <= 'd0;
|
||||
axi_xfer_init <= 'd0;
|
||||
axi_xfer_enable <= 'd0;
|
||||
end else begin
|
||||
if (axi_xfer_init == 1'b1) begin
|
||||
axi_rd_addr_h <= AXI_ADDRESS;
|
||||
end else if (axi_rd_req == 1'b1) begin
|
||||
axi_rd_addr_h <= axi_rd_addr;
|
||||
end
|
||||
if (axi_rd_active == 1'b1) begin
|
||||
axi_rd <= 1'b0;
|
||||
if ((axi_rvalid == 1'b1) && (axi_rlast == 1'b1)) begin
|
||||
axi_rd_active <= 1'b0;
|
||||
end
|
||||
end else if ((axi_ready_s == 1'b1) && (axi_araddr < axi_rd_addr_h)) begin
|
||||
axi_rd <= axi_xfer_enable;
|
||||
axi_rd_active <= axi_xfer_enable;
|
||||
end
|
||||
axi_xfer_req_m <= {axi_xfer_req_m[1:0], dma_xfer_req};
|
||||
axi_xfer_init <= axi_xfer_req_m[1] & ~axi_xfer_req_m[2];
|
||||
axi_xfer_enable <= axi_xfer_req_m[2];
|
||||
end
|
||||
end
|
||||
|
||||
// address channel
|
||||
|
||||
assign axi_arid = 4'b0000;
|
||||
assign axi_arburst = 2'b01;
|
||||
assign axi_arlock = 1'b0;
|
||||
assign axi_arcache = 4'b0010;
|
||||
assign axi_arprot = 3'b000;
|
||||
assign axi_arqos = 4'b0000;
|
||||
assign axi_aruser = 4'b0001;
|
||||
assign axi_arlen = AXI_LENGTH - 1;
|
||||
assign axi_arsize = AXI_SIZE;
|
||||
|
||||
always @(posedge axi_clk or negedge axi_resetn) begin
|
||||
if (axi_resetn == 1'b0) begin
|
||||
axi_arvalid <= 'd0;
|
||||
axi_araddr <= 'd0;
|
||||
end else begin
|
||||
if (axi_arvalid == 1'b1) begin
|
||||
if (axi_arready == 1'b1) begin
|
||||
axi_arvalid <= 1'b0;
|
||||
end
|
||||
end else begin
|
||||
if (axi_rd == 1'b1) begin
|
||||
axi_arvalid <= 1'b1;
|
||||
end
|
||||
end
|
||||
if (axi_xfer_init == 1'b1) begin
|
||||
axi_araddr <= AXI_ADDRESS;
|
||||
end else if ((axi_arvalid == 1'b1) && (axi_arready == 1'b1)) begin
|
||||
axi_araddr <= axi_araddr + AXI_AWINCR;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// read data channel
|
||||
|
||||
always @(posedge axi_clk or negedge axi_resetn) begin
|
||||
if (axi_resetn == 1'b0) begin
|
||||
axi_drst <= 'd1;
|
||||
axi_dvalid <= 'd0;
|
||||
axi_ddata <= 'd0;
|
||||
axi_rready <= 'd0;
|
||||
end else begin
|
||||
axi_drst <= ~axi_xfer_req_m[1];
|
||||
axi_dvalid <= axi_rvalid;
|
||||
axi_ddata <= axi_rdata;
|
||||
axi_rready <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge axi_clk or negedge axi_resetn) begin
|
||||
if (axi_resetn == 1'b0) begin
|
||||
axi_rerror <= 'd0;
|
||||
end else begin
|
||||
axi_rerror <= axi_rvalid & axi_rresp[1];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,418 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_adcfifo_wr #(
|
||||
|
||||
parameter AXI_DATA_WIDTH = 512,
|
||||
parameter AXI_SIZE = 2,
|
||||
parameter AXI_LENGTH = 16,
|
||||
parameter AXI_ADDRESS = 32'h00000000,
|
||||
parameter AXI_ADDRESS_LIMIT = 32'h00000000) (
|
||||
|
||||
// request and synchronization
|
||||
|
||||
input dma_xfer_req,
|
||||
|
||||
// read interface
|
||||
|
||||
output reg axi_rd_req,
|
||||
output reg [ 31:0] axi_rd_addr,
|
||||
|
||||
// fifo interface
|
||||
|
||||
input adc_rst,
|
||||
input adc_clk,
|
||||
input adc_wr,
|
||||
input [AXI_DATA_WIDTH-1:0] adc_wdata,
|
||||
|
||||
// axi interface
|
||||
|
||||
input axi_clk,
|
||||
input axi_resetn,
|
||||
output reg axi_awvalid,
|
||||
output [ 3:0] axi_awid,
|
||||
output [ 1:0] axi_awburst,
|
||||
output axi_awlock,
|
||||
output [ 3:0] axi_awcache,
|
||||
output [ 2:0] axi_awprot,
|
||||
output [ 3:0] axi_awqos,
|
||||
output [ 3:0] axi_awuser,
|
||||
output [ 7:0] axi_awlen,
|
||||
output [ 2:0] axi_awsize,
|
||||
output reg [ 31:0] axi_awaddr,
|
||||
input axi_awready,
|
||||
output axi_wvalid,
|
||||
output [AXI_DATA_WIDTH-1:0] axi_wdata,
|
||||
output [AXI_BYTE_WIDTH-1:0] axi_wstrb,
|
||||
output axi_wlast,
|
||||
output [ 3:0] axi_wuser,
|
||||
input axi_wready,
|
||||
input axi_bvalid,
|
||||
input [ 3:0] axi_bid,
|
||||
input [ 1:0] axi_bresp,
|
||||
input [ 3:0] axi_buser,
|
||||
output axi_bready,
|
||||
|
||||
// axi status
|
||||
|
||||
output reg axi_dwovf,
|
||||
output reg axi_dwunf,
|
||||
output reg axi_werror);
|
||||
|
||||
localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
|
||||
localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH;
|
||||
localparam BUF_THRESHOLD_LO = 8'd6;
|
||||
localparam BUF_THRESHOLD_HI = 8'd250;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [ 2:0] adc_xfer_req_m = 'd0;
|
||||
reg adc_xfer_init = 'd0;
|
||||
reg adc_xfer_limit = 'd0;
|
||||
reg adc_xfer_enable = 'd0;
|
||||
reg [ 31:0] adc_xfer_addr = 'd0;
|
||||
reg [ 7:0] adc_waddr = 'd0;
|
||||
reg [ 7:0] adc_waddr_g = 'd0;
|
||||
reg adc_rel_enable = 'd0;
|
||||
reg adc_rel_toggle = 'd0;
|
||||
reg [ 7:0] adc_rel_waddr = 'd0;
|
||||
reg [ 2:0] axi_rel_toggle_m = 'd0;
|
||||
reg [ 7:0] axi_rel_waddr = 'd0;
|
||||
reg [ 7:0] axi_waddr_m1 = 'd0;
|
||||
reg [ 7:0] axi_waddr_m2 = 'd0;
|
||||
reg [ 7:0] axi_waddr = 'd0;
|
||||
reg [ 7:0] axi_addr_diff = 'd0;
|
||||
reg axi_almost_full = 'd0;
|
||||
reg axi_almost_empty = 'd0;
|
||||
reg [ 2:0] axi_xfer_req_m = 'd0;
|
||||
reg axi_xfer_init = 'd0;
|
||||
reg [ 7:0] axi_raddr = 'd0;
|
||||
reg axi_rd = 'd0;
|
||||
reg axi_rlast = 'd0;
|
||||
reg axi_rd_d = 'd0;
|
||||
reg axi_rlast_d = 'd0;
|
||||
reg [AXI_DATA_WIDTH-1:0] axi_rdata_d = 'd0;
|
||||
reg axi_reset = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire axi_rel_toggle_s;
|
||||
wire [ 8:0] axi_addr_diff_s;
|
||||
wire axi_wready_s;
|
||||
wire axi_rd_s;
|
||||
wire axi_req_s;
|
||||
wire axi_rlast_s;
|
||||
wire [AXI_DATA_WIDTH-1:0] axi_rdata_s;
|
||||
|
||||
// binary to grey conversion
|
||||
|
||||
function [7:0] b2g;
|
||||
input [7:0] b;
|
||||
reg [7:0] g;
|
||||
begin
|
||||
g[7] = b[7];
|
||||
g[6] = b[7] ^ b[6];
|
||||
g[5] = b[6] ^ b[5];
|
||||
g[4] = b[5] ^ b[4];
|
||||
g[3] = b[4] ^ b[3];
|
||||
g[2] = b[3] ^ b[2];
|
||||
g[1] = b[2] ^ b[1];
|
||||
g[0] = b[1] ^ b[0];
|
||||
b2g = g;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// grey to binary conversion
|
||||
|
||||
function [7:0] g2b;
|
||||
input [7:0] g;
|
||||
reg [7:0] b;
|
||||
begin
|
||||
b[7] = g[7];
|
||||
b[6] = b[7] ^ g[6];
|
||||
b[5] = b[6] ^ g[5];
|
||||
b[4] = b[5] ^ g[4];
|
||||
b[3] = b[4] ^ g[3];
|
||||
b[2] = b[3] ^ g[2];
|
||||
b[1] = b[2] ^ g[1];
|
||||
b[0] = b[1] ^ g[0];
|
||||
g2b = b;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// fifo interface
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
if (adc_rst == 1'b1) begin
|
||||
adc_waddr <= 'd0;
|
||||
adc_waddr_g <= 'd0;
|
||||
adc_xfer_req_m <= 'd0;
|
||||
adc_xfer_init <= 'd0;
|
||||
adc_xfer_limit <= 'd0;
|
||||
adc_xfer_enable <= 'd0;
|
||||
adc_xfer_addr <= 'd0;
|
||||
adc_rel_enable <= 'd0;
|
||||
adc_rel_toggle <= 'd0;
|
||||
adc_rel_waddr <= 'd0;
|
||||
end else begin
|
||||
if ((adc_wr == 1'b1) && (adc_xfer_enable == 1'b1)) begin
|
||||
adc_waddr <= adc_waddr + 1'b1;
|
||||
end
|
||||
adc_waddr_g <= b2g(adc_waddr);
|
||||
adc_xfer_req_m <= {adc_xfer_req_m[1:0], dma_xfer_req};
|
||||
adc_xfer_init <= adc_xfer_req_m[1] & ~adc_xfer_req_m[2];
|
||||
if (adc_xfer_init == 1'b1) begin
|
||||
adc_xfer_limit <= 1'd1;
|
||||
end else if ((adc_xfer_addr >= AXI_ADDRESS_LIMIT) || (adc_xfer_enable == 1'b0)) begin
|
||||
adc_xfer_limit <= 1'd0;
|
||||
end
|
||||
if (adc_xfer_init == 1'b1) begin
|
||||
adc_xfer_enable <= 1'b1;
|
||||
adc_xfer_addr <= AXI_ADDRESS;
|
||||
end else if ((adc_waddr[1:0] == 2'h3) && (adc_wr == 1'b1)) begin
|
||||
adc_xfer_enable <= adc_xfer_req_m[2] & adc_xfer_limit;
|
||||
adc_xfer_addr <= adc_xfer_addr + AXI_AWINCR;
|
||||
end
|
||||
if (adc_waddr[1:0] == 2'h3) begin
|
||||
adc_rel_enable <= adc_wr;
|
||||
end else begin
|
||||
adc_rel_enable <= 1'd0;
|
||||
end
|
||||
if (adc_rel_enable == 1'b1) begin
|
||||
adc_rel_toggle <= ~adc_rel_toggle;
|
||||
adc_rel_waddr <= adc_waddr;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// fifo signals on axi side
|
||||
|
||||
assign axi_rel_toggle_s = axi_rel_toggle_m[2] ^ axi_rel_toggle_m[1];
|
||||
|
||||
always @(posedge axi_clk or negedge axi_resetn) begin
|
||||
if (axi_resetn == 1'b0) begin
|
||||
axi_rel_toggle_m <= 'd0;
|
||||
axi_rel_waddr <= 'd0;
|
||||
axi_waddr_m1 <= 'd0;
|
||||
axi_waddr_m2 <= 'd0;
|
||||
axi_waddr <= 'd0;
|
||||
end else begin
|
||||
axi_rel_toggle_m <= {axi_rel_toggle_m[1:0], adc_rel_toggle};
|
||||
if (axi_rel_toggle_s == 1'b1) begin
|
||||
axi_rel_waddr <= adc_rel_waddr;
|
||||
end
|
||||
axi_waddr_m1 <= adc_waddr_g;
|
||||
axi_waddr_m2 <= axi_waddr_m1;
|
||||
axi_waddr <= g2b(axi_waddr_m2);
|
||||
end
|
||||
end
|
||||
|
||||
// overflow (no underflow possible)
|
||||
|
||||
assign axi_addr_diff_s = {1'b1, axi_waddr} - axi_raddr;
|
||||
|
||||
always @(posedge axi_clk or negedge axi_resetn) begin
|
||||
if (axi_resetn == 1'b0) begin
|
||||
axi_addr_diff <= 'd0;
|
||||
axi_almost_full <= 'd0;
|
||||
axi_dwunf <= 'd0;
|
||||
axi_almost_empty <= 'd0;
|
||||
axi_dwovf <= 'd0;
|
||||
end else begin
|
||||
axi_addr_diff <= axi_addr_diff_s[7:0];
|
||||
if (axi_addr_diff > BUF_THRESHOLD_HI) begin
|
||||
axi_almost_full <= 1'b1;
|
||||
axi_dwunf <= axi_almost_empty;
|
||||
end else begin
|
||||
axi_almost_full <= 1'b0;
|
||||
axi_dwunf <= 1'b0;
|
||||
end
|
||||
if (axi_addr_diff < BUF_THRESHOLD_LO) begin
|
||||
axi_almost_empty <= 1'b1;
|
||||
axi_dwovf <= axi_almost_full;
|
||||
end else begin
|
||||
axi_almost_empty <= 1'b0;
|
||||
axi_dwovf <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// transfer request is required to keep things in sync
|
||||
|
||||
always @(posedge axi_clk or negedge axi_resetn) begin
|
||||
if (axi_resetn == 1'b0) begin
|
||||
axi_xfer_req_m <= 'd0;
|
||||
axi_xfer_init <= 'd0;
|
||||
end else begin
|
||||
axi_xfer_req_m <= {axi_xfer_req_m[1:0], dma_xfer_req};
|
||||
axi_xfer_init <= axi_xfer_req_m[1] & ~axi_xfer_req_m[2];
|
||||
end
|
||||
end
|
||||
|
||||
// read is initiated if xfer enabled
|
||||
|
||||
assign axi_wready_s = ~axi_wvalid | axi_wready;
|
||||
assign axi_rd_s = (axi_rel_waddr == axi_raddr) ? 1'b0 : axi_wready_s;
|
||||
assign axi_req_s = (axi_raddr[1:0] == 2'h0) ? axi_rd_s : 1'b0;
|
||||
assign axi_rlast_s = (axi_raddr[1:0] == 2'h3) ? axi_rd_s : 1'b0;
|
||||
|
||||
always @(posedge axi_clk or negedge axi_resetn) begin
|
||||
if (axi_resetn == 1'b0) begin
|
||||
axi_raddr <= 'd0;
|
||||
axi_rd <= 'd0;
|
||||
axi_rlast <= 'd0;
|
||||
axi_rd_d <= 'd0;
|
||||
axi_rlast_d <= 'd0;
|
||||
axi_rdata_d <= 'd0;
|
||||
end else begin
|
||||
if (axi_rd_s == 1'b1) begin
|
||||
axi_raddr <= axi_raddr + 1'b1;
|
||||
end
|
||||
axi_rd <= axi_rd_s;
|
||||
axi_rlast <= axi_rlast_s;
|
||||
axi_rd_d <= axi_rd;
|
||||
axi_rlast_d <= axi_rlast;
|
||||
axi_rdata_d <= axi_rdata_s;
|
||||
end
|
||||
end
|
||||
|
||||
// send read request for every burst about to be completed
|
||||
|
||||
always @(posedge axi_clk or negedge axi_resetn) begin
|
||||
if (axi_resetn == 1'b0) begin
|
||||
axi_rd_req <= 'd0;
|
||||
axi_rd_addr <= 'd0;
|
||||
end else begin
|
||||
axi_rd_req <= axi_rlast_s;
|
||||
if (axi_xfer_init == 1'b1) begin
|
||||
axi_rd_addr <= AXI_ADDRESS;
|
||||
end else if (axi_rd_req == 1'b1) begin
|
||||
axi_rd_addr <= axi_rd_addr + AXI_AWINCR;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// address channel
|
||||
|
||||
assign axi_awid = 4'b0000;
|
||||
assign axi_awburst = 2'b01;
|
||||
assign axi_awlock = 1'b0;
|
||||
assign axi_awcache = 4'b0010;
|
||||
assign axi_awprot = 3'b000;
|
||||
assign axi_awqos = 4'b0000;
|
||||
assign axi_awuser = 4'b0001;
|
||||
assign axi_awlen = AXI_LENGTH - 1;
|
||||
assign axi_awsize = AXI_SIZE;
|
||||
|
||||
always @(posedge axi_clk or negedge axi_resetn) begin
|
||||
if (axi_resetn == 1'b0) begin
|
||||
axi_awvalid <= 'd0;
|
||||
axi_awaddr <= 'd0;
|
||||
end else begin
|
||||
if (axi_awvalid == 1'b1) begin
|
||||
if (axi_awready == 1'b1) begin
|
||||
axi_awvalid <= 1'b0;
|
||||
end
|
||||
end else begin
|
||||
if (axi_req_s == 1'b1) begin
|
||||
axi_awvalid <= 1'b1;
|
||||
end
|
||||
end
|
||||
if (axi_xfer_init == 1'b1) begin
|
||||
axi_awaddr <= AXI_ADDRESS;
|
||||
end else if ((axi_awvalid == 1'b1) && (axi_awready == 1'b1)) begin
|
||||
axi_awaddr <= axi_awaddr + AXI_AWINCR;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// write channel
|
||||
|
||||
assign axi_wstrb = {AXI_BYTE_WIDTH{1'b1}};
|
||||
assign axi_wuser = 4'b0000;
|
||||
|
||||
// response channel
|
||||
|
||||
assign axi_bready = 1'b1;
|
||||
|
||||
always @(posedge axi_clk or negedge axi_resetn) begin
|
||||
if (axi_resetn == 1'b0) begin
|
||||
axi_werror <= 'd0;
|
||||
end else begin
|
||||
axi_werror <= axi_bvalid & axi_bready & axi_bresp[1];
|
||||
end
|
||||
end
|
||||
|
||||
// fifo needs a reset
|
||||
|
||||
always @(posedge axi_clk or negedge axi_resetn) begin
|
||||
if (axi_resetn == 1'b0) begin
|
||||
axi_reset <= 1'b1;
|
||||
end else begin
|
||||
axi_reset <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// interface handler
|
||||
|
||||
ad_axis_inf_rx #(.DATA_WIDTH(AXI_DATA_WIDTH)) i_axis_inf (
|
||||
.clk (axi_clk),
|
||||
.rst (axi_reset),
|
||||
.valid (axi_rd_d),
|
||||
.last (axi_rlast_d),
|
||||
.data (axi_rdata_d),
|
||||
.inf_valid (axi_wvalid),
|
||||
.inf_last (axi_wlast),
|
||||
.inf_data (axi_wdata),
|
||||
.inf_ready (axi_wready));
|
||||
|
||||
// buffer
|
||||
|
||||
ad_mem #(.DATA_WIDTH(AXI_DATA_WIDTH), .ADDRESS_WIDTH(8)) i_mem (
|
||||
.clka (adc_clk),
|
||||
.wea (adc_wr),
|
||||
.addra (adc_waddr),
|
||||
.dina (adc_wdata),
|
||||
.clkb (axi_clk),
|
||||
.reb (1'b1),
|
||||
.addrb (axi_raddr),
|
||||
.doutb (axi_rdata_s));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Thu Dec 9 15:19:55 2021
|
||||
# Process ID: 7949
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo
|
||||
# Command line: vivado -mode batch -source axi_adcfifo_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source axi_adcfifo_ip.tcl
|
||||
@@ -0,0 +1,816 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Thu Dec 9 15:19:55 2021
|
||||
# Process ID: 7949
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo
|
||||
# Command line: vivado -mode batch -source axi_adcfifo_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source axi_adcfifo_ip.tcl
|
||||
# source ../../scripts/adi_env.tcl
|
||||
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
|
||||
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
|
||||
## if [info exists ::env(ADI_HDL_DIR)] {
|
||||
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
|
||||
## }
|
||||
## if [info exists ::env(ADI_GHDL_DIR)] {
|
||||
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
|
||||
## }
|
||||
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
|
||||
### variable auto_set_param_list
|
||||
### variable auto_set_param_list_overwritable
|
||||
### variable fpga_series_list
|
||||
### variable fpga_family_list
|
||||
### variable speed_grade_list
|
||||
### variable dev_package_list
|
||||
### variable xcvr_type_list
|
||||
### variable fpga_voltage_list
|
||||
### set auto_set_param_list { \
|
||||
### DEV_PACKAGE \
|
||||
### SPEED_GRADE \
|
||||
### FPGA_FAMILY \
|
||||
### FPGA_TECHNOLOGY }
|
||||
### set auto_set_param_list_overwritable { \
|
||||
### FPGA_VOLTAGE \
|
||||
### XCVR_TYPE }
|
||||
### set fpga_technology_list { \
|
||||
### { Unknown 0 } \
|
||||
### { 7series 1 } \
|
||||
### { ultrascale 2 } \
|
||||
### { ultrascale+ 3 }}
|
||||
### set fpga_family_list { \
|
||||
### { Unknown 0 } \
|
||||
### { artix 1 } \
|
||||
### { kintex 2 } \
|
||||
### { virtex 3 } \
|
||||
### { zynq 4 }}
|
||||
### set speed_grade_list { \
|
||||
### { Unknown 0 } \
|
||||
### { -1 10 } \
|
||||
### { -1L 11 } \
|
||||
### { -1H 12 } \
|
||||
### { -1HV 13 } \
|
||||
### { -1LV 14 } \
|
||||
### { -2 20 } \
|
||||
### { -2L 21 } \
|
||||
### { -2LV 22 } \
|
||||
### { -3 30 }}
|
||||
### set dev_package_list { \
|
||||
### { Unknown 0 } \
|
||||
### { rf 1 } \
|
||||
### { fl 2 } \
|
||||
### { ff 3 } \
|
||||
### { fb 4 } \
|
||||
### { hc 5 } \
|
||||
### { fh 6 } \
|
||||
### { cs 7 } \
|
||||
### { cp 8 } \
|
||||
### { ft 9 } \
|
||||
### { fg 10 } \
|
||||
### { sb 11 } \
|
||||
### { rb 12 } \
|
||||
### { rs 13 } \
|
||||
### { cl 14 } \
|
||||
### { sf 15 } \
|
||||
### { ba 16 } \
|
||||
### { fa 17 } \
|
||||
### { fs 18 } \
|
||||
### { fi 19 }}
|
||||
### set xcvr_type_list { \
|
||||
### { Unknown 0 } \
|
||||
### { GTPE2_NOT_SUPPORTED 1 } \
|
||||
### { GTXE2 2 } \
|
||||
### { GTHE2_NOT_SUPPORTED 3 } \
|
||||
### { GTZE2_NOT_SUPPORTED 4 } \
|
||||
### { GTHE3 5 } \
|
||||
### { GTYE3_NOT_SUPPORTED 6 } \
|
||||
### { GTRE4_NOT_SUPPORTED 7 } \
|
||||
### { GTHE4 8 } \
|
||||
### { GTYE4 9 } \
|
||||
### { GTME4_NOT_SUPPORTED 10}}
|
||||
### set fpga_voltage_list {0 5000} ;
|
||||
### proc adi_device_spec {cellpath param} {
|
||||
###
|
||||
### set list_pointer [string tolower $param]
|
||||
### set list_pointer [append list_pointer "_list"]
|
||||
###
|
||||
### upvar 1 $list_pointer $list_pointer
|
||||
###
|
||||
### set ip [get_bd_cells $cellpath]
|
||||
### set part [get_property PART [current_project]]
|
||||
###
|
||||
### switch -regexp -- $param {
|
||||
### FPGA_TECHNOLOGY {
|
||||
### switch -regexp -- $part {
|
||||
### ^xc7 {set series_name 7series}
|
||||
### ^xczu {set series_name ultrascale+}
|
||||
### ^xc.u.p {set series_name ultrascale+}
|
||||
### ^xc.u {set series_name ultrascale }
|
||||
### default {
|
||||
### puts "Undefined fpga technology for \"$part\"!"
|
||||
### exit -1
|
||||
### }
|
||||
### }
|
||||
### return "$series_name"
|
||||
### }
|
||||
### FPGA_FAMILY {
|
||||
### set fpga_family [get_property FAMILY $part]
|
||||
### foreach i $fpga_family_list {
|
||||
### regexp ^[lindex $i 0] $fpga_family matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### SPEED_GRADE {
|
||||
### set speed_grade [get_property SPEED $part]
|
||||
### return "$speed_grade"
|
||||
### }
|
||||
### DEV_PACKAGE {
|
||||
### set dev_package [get_property PACKAGE $part]
|
||||
### foreach i $dev_package_list {
|
||||
### regexp ^[lindex $i 0] $dev_package matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### XCVR_TYPE {
|
||||
### set matched ""
|
||||
### set dev_transcivers "none"
|
||||
### foreach x [list_property $part] {
|
||||
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
|
||||
### }
|
||||
### foreach i $xcvr_type_list {
|
||||
### regexp ^[lindex $i 0] $dev_transcivers matched
|
||||
### }
|
||||
### if { $matched eq "" } {
|
||||
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### FPGA_VOLTAGE {
|
||||
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
|
||||
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
|
||||
###
|
||||
### return "$fpga_voltage"
|
||||
### }
|
||||
### default {
|
||||
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
|
||||
### }
|
||||
### }
|
||||
### }
|
||||
## if {![info exists REQUIRED_VIVADO_VERSION]} {
|
||||
## set REQUIRED_VIVADO_VERSION "2019.1"
|
||||
## }
|
||||
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
|
||||
## set IGNORE_VERSION_CHECK 1
|
||||
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
|
||||
## set IGNORE_VERSION_CHECK 0
|
||||
## }
|
||||
## proc adi_ip_ttcl {ip_name ip_constr_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
|
||||
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_sim_ttcl {ip_name ip_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
|
||||
## set f [ipx::add_file $ip_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_bd {ip_name ip_bd_files} {
|
||||
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
|
||||
## if {$proj_filegroup == {}} {
|
||||
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
|
||||
## }
|
||||
##
|
||||
## foreach file $ip_bd_files {
|
||||
## set f [ipx::add_file $file $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type tclSource \
|
||||
## ] $f
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_infer_streaming_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_ip_infer_mm_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
|
||||
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency $port
|
||||
## if {$driver_value != {}} {
|
||||
## set_property DRIVER_VALUE $driver_value $port
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_set_bus_dependency {bus prefix dependency} {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
|
||||
## adi_set_ports_dependency $prefix $dependency 0
|
||||
## }
|
||||
## proc adi_add_port_map {bus phys logic} {
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## }
|
||||
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## adi_add_port_map $bus {*}$port_map
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
|
||||
## for {set i 0} {$i < $num} {incr i} {
|
||||
## set bus_name [format "%s%d" $bus_name_prefix $i]
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## if {$dependency ne ""} {
|
||||
## set bus_dependency [string map [list "{i}" $i] $dependency]
|
||||
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
|
||||
## }
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## lassign $port_map phys logic width width_dep
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
|
||||
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
|
||||
## if {$width_dep ne ""} {
|
||||
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
|
||||
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
|
||||
## set width_dep_r "(($width_dep) * $i)"
|
||||
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
|
||||
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
|
||||
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
|
||||
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
|
||||
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
|
||||
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
|
||||
## set_property display_name $clock_inf_name $clock_inf
|
||||
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
|
||||
## set_property physical_name $clock_signal_name $clock_map
|
||||
##
|
||||
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
|
||||
## set_property value $bus_inf_name $assoc_busif
|
||||
##
|
||||
## if { $reset_signal_name != "" } {
|
||||
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
|
||||
## set_property value $reset_signal_name $assoc_reset
|
||||
##
|
||||
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
|
||||
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
|
||||
## set_property display_name $reset_inf_name $reset_inf
|
||||
## set_property interface_mode $reset_signal_mode $reset_inf
|
||||
## set reset_map [ipx::add_port_map "RST" $reset_inf]
|
||||
## set_property physical_name $reset_signal_name $reset_map
|
||||
##
|
||||
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
|
||||
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
|
||||
## set_property value "ACTIVE_LOW" $reset_polarity
|
||||
## } else {
|
||||
## set_property value "ACTIVE_HIGH" $reset_polarity
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_add_core_dependencies {vlnvs} {
|
||||
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
|
||||
## foreach vlnv $vlnvs {
|
||||
## ipx::add_subcore $vlnv $file_group
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_create {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
## global ad_ghdl_dir
|
||||
## global REQUIRED_VIVADO_VERSION
|
||||
## global IGNORE_VERSION_CHECK
|
||||
##
|
||||
## set VIVADO_VERSION [version -short]
|
||||
## if {$IGNORE_VERSION_CHECK} {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## }
|
||||
## } else {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "ERROR: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
|
||||
## exit 2
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## create_project $ip_name . -force
|
||||
##
|
||||
## ## Load custom message severity definitions
|
||||
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
|
||||
##
|
||||
## set lib_dirs $ad_hdl_dir/library
|
||||
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
|
||||
## lappend lib_dirs $ad_ghdl_dir/library
|
||||
## }
|
||||
##
|
||||
## set_property ip_repo_paths $lib_dirs [current_fileset]
|
||||
## update_ip_catalog
|
||||
## }
|
||||
## proc adi_ip_files {ip_name ip_files} {
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## foreach m_file $ip_files {
|
||||
## if {[file extension $m_file] eq ".xdc"} {
|
||||
## add_files -norecurse -fileset constrs_1 $m_file
|
||||
## } else {
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
|
||||
## }
|
||||
## }
|
||||
## set_property "top" "$ip_name" $proj_fileset
|
||||
## }
|
||||
## proc adi_ip_properties_lite {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
##
|
||||
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
|
||||
##
|
||||
## set_property name $ip_name [ipx::current_core]
|
||||
##
|
||||
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
|
||||
## set_property company_url {http://www.analog.com} [ipx::current_core]
|
||||
##
|
||||
## set i_families ""
|
||||
## foreach i_part [get_parts] {
|
||||
## lappend i_families [get_property FAMILY $i_part]
|
||||
## }
|
||||
## set i_families [lsort -unique $i_families]
|
||||
## set s_families [get_property supported_families [ipx::current_core]]
|
||||
## foreach i_family $i_families {
|
||||
## set s_families "$s_families $i_family Production"
|
||||
## set s_families "$s_families $i_family Beta"
|
||||
## }
|
||||
## set_property supported_families $s_families [ipx::current_core]
|
||||
##
|
||||
## ipx::save_core [ipx::current_core]
|
||||
##
|
||||
## ipx::remove_all_bus_interface [ipx::current_core]
|
||||
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
|
||||
## foreach map $memory_maps {
|
||||
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
|
||||
## }
|
||||
##
|
||||
## ipx::update_checksums [ipx::current_core]
|
||||
## ipx::save_core [ipx::current_core]
|
||||
## }
|
||||
## proc adi_ip_properties {ip_name} {
|
||||
##
|
||||
## adi_ip_properties_lite $ip_name
|
||||
##
|
||||
## ipx::infer_bus_interface {\
|
||||
## s_axi_awvalid \
|
||||
## s_axi_awaddr \
|
||||
## s_axi_awprot \
|
||||
## s_axi_awready \
|
||||
## s_axi_wvalid \
|
||||
## s_axi_wdata \
|
||||
## s_axi_wstrb \
|
||||
## s_axi_wready \
|
||||
## s_axi_bvalid \
|
||||
## s_axi_bresp \
|
||||
##
|
||||
## s_axi_bready \
|
||||
## s_axi_arvalid \
|
||||
## s_axi_araddr \
|
||||
## s_axi_arprot \
|
||||
## s_axi_arready \
|
||||
## s_axi_rvalid \
|
||||
## s_axi_rdata \
|
||||
## s_axi_rresp \
|
||||
## s_axi_rready} \
|
||||
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
|
||||
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
|
||||
##
|
||||
## if {$raddr_width != $waddr_width} {
|
||||
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
|
||||
## set range 65536
|
||||
## } else {
|
||||
## if {$raddr_width >= 16} {
|
||||
## set range 65536
|
||||
## } else {
|
||||
## set range [expr 1 << $raddr_width]
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
## set_property range $range [ipx::get_address_blocks axi_lite \
|
||||
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
|
||||
## ipx::save_core
|
||||
## }
|
||||
## proc adi_init_bd_tcl {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## if { [file exists bd] } {
|
||||
## file delete -force bd
|
||||
## }
|
||||
## file mkdir bd
|
||||
##
|
||||
## set bd_tcl [open "bd/bd.tcl" w]
|
||||
##
|
||||
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
|
||||
## puts $bd_tcl "proc init {cellpath otherInfo} {"
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl ""
|
||||
## set auto_set_param ""
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
|
||||
## puts $bd_tcl $auto_set_param
|
||||
## }
|
||||
##
|
||||
## set auto_set_overwritable_param ""
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_overwritable_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_overwritable_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
|
||||
## puts $bd_tcl $auto_set_overwritable_param
|
||||
## }
|
||||
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
|
||||
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
|
||||
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set parent_dir \"../\""
|
||||
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
|
||||
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
|
||||
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " break"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " append parent_dir \"../\""
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## close $bd_tcl
|
||||
##
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
|
||||
##
|
||||
## set local_mk [open "temporary_case_dependencies.mk" w]
|
||||
## seek $local_mk 0 start
|
||||
## puts $local_mk "CLEAN_TARGET += bd"
|
||||
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
|
||||
## close $local_mk
|
||||
## }
|
||||
## proc adi_add_auto_fpga_spec_params {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_device_spec_param {ip_param} {
|
||||
##
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## set list_pointer [string tolower $ip_param]
|
||||
## set list_pointer [append list_pointer "_list"]
|
||||
##
|
||||
## global $list_pointer
|
||||
##
|
||||
## # set j 1D list from the original list
|
||||
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
|
||||
##
|
||||
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
|
||||
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "range_long" \
|
||||
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
|
||||
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## } else {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "pairs" \
|
||||
## "value_validation_pairs" $j ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## }
|
||||
##
|
||||
## # FPGA info grup
|
||||
## set info_group_name "FPGA info"
|
||||
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
|
||||
## if { [string trim $info_group] eq "" } {
|
||||
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
|
||||
## -parent $page0 -display_name $info_group_name]
|
||||
## }
|
||||
##
|
||||
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
|
||||
## set_property -dict [list "widget" "comboBox" ] $p
|
||||
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
|
||||
## }
|
||||
## proc adi_if_define {name} {
|
||||
##
|
||||
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
|
||||
## ipx::create_bus_definition analog.com interface $name 1.0
|
||||
##
|
||||
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
|
||||
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
|
||||
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
|
||||
##
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## }
|
||||
## proc adi_if_ports {dir width name {type none}} {
|
||||
##
|
||||
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
|
||||
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
|
||||
## set_property master_presence required $m_intf
|
||||
## set_property slave_presence required $m_intf
|
||||
## set_property master_width $width $m_intf
|
||||
## set_property slave_width $width $m_intf
|
||||
##
|
||||
## set m_dir "in"
|
||||
## set s_dir "out"
|
||||
## if {$dir eq "output"} {
|
||||
## set m_dir "out"
|
||||
## set s_dir "in"
|
||||
## }
|
||||
##
|
||||
## set_property master_direction $m_dir $m_intf
|
||||
## set_property slave_direction $s_dir $m_intf
|
||||
##
|
||||
## if {$type ne "none"} {
|
||||
## set_property is_${type} true $m_intf
|
||||
## }
|
||||
##
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## }
|
||||
## proc adi_if_infer_bus {if_name mode name maps} {
|
||||
##
|
||||
## ipx::add_bus_interface $name [ipx::current_core]
|
||||
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
|
||||
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
|
||||
## set_property interface_mode $mode $m_bus_if
|
||||
##
|
||||
## foreach map $maps {
|
||||
## set m_maps [regexp -all -inline {\S+} $map]
|
||||
## lassign $m_maps p_name p_map
|
||||
## ipx::add_port_map $p_name $m_bus_if
|
||||
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
|
||||
## }
|
||||
## }
|
||||
# adi_ip_create axi_adcfifo
|
||||
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
|
||||
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1343} -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1306} -new_severity WARNING
|
||||
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
|
||||
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
|
||||
## set_msg_config -id {Synth 8-3331} -new_severity INFO
|
||||
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
|
||||
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
|
||||
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
|
||||
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'.)
|
||||
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
|
||||
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
|
||||
# adi_ip_files axi_adcfifo [list \
|
||||
# "$ad_hdl_dir/library/common/ad_mem.v" \
|
||||
# "$ad_hdl_dir/library/common/ad_mem_asym.v" \
|
||||
# "$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
# "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
|
||||
# "axi_adcfifo_adc.v" \
|
||||
# "axi_adcfifo_dma.v" \
|
||||
# "axi_adcfifo_wr.v" \
|
||||
# "axi_adcfifo_rd.v" \
|
||||
# "axi_adcfifo.v" \
|
||||
# "axi_adcfifo_constr.xdc" ]
|
||||
# adi_ip_properties_lite axi_adcfifo
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_axis_inf_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_axis_inf_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_xfer_status.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adcfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5150] The Range '(AXI_DATA_WIDTH - 1):0' is present in all ports of the interface 'axi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port rdata on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'adc' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5150] The Range '(AXI_DATA_WIDTH - 1):0' is present in all ports of the interface 'axi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5150] The Range '(ADC_DATA_WIDTH - 1):0' is present in all ports of the interface 'adc'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'axi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'axi_resetn'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_xfer_req' and definition port 'XFER_REQ'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'dma': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'dma': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "rdata" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'adc': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'axi_wdata' and definition port 'wdata'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'axi_rdata' and definition port 'rdata'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'adc_clk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'axi_clk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'dma_clk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
# ipx::infer_bus_interface {\
|
||||
# axi_awvalid \
|
||||
# axi_awid \
|
||||
# axi_awburst \
|
||||
# axi_awlock \
|
||||
# axi_awcache \
|
||||
# axi_awprot \
|
||||
# axi_awqos \
|
||||
# axi_awuser \
|
||||
# axi_awlen \
|
||||
# axi_awsize \
|
||||
# axi_awaddr \
|
||||
# axi_awready \
|
||||
# axi_wvalid \
|
||||
# axi_wdata \
|
||||
# axi_wstrb \
|
||||
# axi_wlast \
|
||||
# axi_wuser \
|
||||
# axi_wready \
|
||||
# axi_bvalid \
|
||||
# axi_bid \
|
||||
# axi_bresp \
|
||||
# axi_buser \
|
||||
# axi_bready \
|
||||
# axi_arvalid \
|
||||
# axi_arid \
|
||||
# axi_arburst \
|
||||
# axi_arlock \
|
||||
# axi_arcache \
|
||||
# axi_arprot \
|
||||
# axi_arqos \
|
||||
# axi_aruser \
|
||||
# axi_arlen \
|
||||
# axi_arsize \
|
||||
# axi_araddr \
|
||||
# axi_arready \
|
||||
# axi_rvalid \
|
||||
# axi_rid \
|
||||
# axi_ruser \
|
||||
# axi_rresp \
|
||||
# axi_rlast \
|
||||
# axi_rdata \
|
||||
# axi_rready} \
|
||||
# xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument).
|
||||
# ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'axi'.
|
||||
# ipx::infer_bus_interface axi_resetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_resetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'axi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'axi_resetn'.
|
||||
# ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \
|
||||
# -of_objects [ipx::current_core]]
|
||||
# set_property value axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
|
||||
# -of_objects [ipx::get_bus_interfaces axi_clk \
|
||||
# -of_objects [ipx::current_core]]]
|
||||
# ipx::add_address_space axi [ipx::current_core]
|
||||
# set_property master_address_space_ref axi [ipx::get_bus_interfaces axi \
|
||||
# -of_objects [ipx::current_core]]
|
||||
# set_property range 4294967296 [ipx::get_address_spaces axi \
|
||||
# -of_objects [ipx::current_core]]
|
||||
# set_property width 512 [ipx::get_address_spaces axi \
|
||||
# -of_objects [ipx::current_core]]
|
||||
# ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
# ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
# ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'adc_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'adc_rst'.
|
||||
# ipx::save_core [ipx::current_core]
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:20:07 2021...
|
||||
@@ -0,0 +1,130 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "ADC_DATA_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "AXI_ADDRESS" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "AXI_ADDRESS_LIMIT" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "AXI_DATA_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "AXI_LENGTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "AXI_SIZE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DMA_DATA_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DMA_READY_ENABLE" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ADC_DATA_WIDTH { PARAM_VALUE.ADC_DATA_WIDTH } {
|
||||
# Procedure called to update ADC_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ADC_DATA_WIDTH { PARAM_VALUE.ADC_DATA_WIDTH } {
|
||||
# Procedure called to validate ADC_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.AXI_ADDRESS { PARAM_VALUE.AXI_ADDRESS } {
|
||||
# Procedure called to update AXI_ADDRESS when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.AXI_ADDRESS { PARAM_VALUE.AXI_ADDRESS } {
|
||||
# Procedure called to validate AXI_ADDRESS
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.AXI_ADDRESS_LIMIT { PARAM_VALUE.AXI_ADDRESS_LIMIT } {
|
||||
# Procedure called to update AXI_ADDRESS_LIMIT when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.AXI_ADDRESS_LIMIT { PARAM_VALUE.AXI_ADDRESS_LIMIT } {
|
||||
# Procedure called to validate AXI_ADDRESS_LIMIT
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH } {
|
||||
# Procedure called to update AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH } {
|
||||
# Procedure called to validate AXI_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.AXI_LENGTH { PARAM_VALUE.AXI_LENGTH } {
|
||||
# Procedure called to update AXI_LENGTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.AXI_LENGTH { PARAM_VALUE.AXI_LENGTH } {
|
||||
# Procedure called to validate AXI_LENGTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.AXI_SIZE { PARAM_VALUE.AXI_SIZE } {
|
||||
# Procedure called to update AXI_SIZE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.AXI_SIZE { PARAM_VALUE.AXI_SIZE } {
|
||||
# Procedure called to validate AXI_SIZE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DMA_DATA_WIDTH { PARAM_VALUE.DMA_DATA_WIDTH } {
|
||||
# Procedure called to update DMA_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DMA_DATA_WIDTH { PARAM_VALUE.DMA_DATA_WIDTH } {
|
||||
# Procedure called to validate DMA_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DMA_READY_ENABLE { PARAM_VALUE.DMA_READY_ENABLE } {
|
||||
# Procedure called to update DMA_READY_ENABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DMA_READY_ENABLE { PARAM_VALUE.DMA_READY_ENABLE } {
|
||||
# Procedure called to validate DMA_READY_ENABLE
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ADC_DATA_WIDTH { MODELPARAM_VALUE.ADC_DATA_WIDTH PARAM_VALUE.ADC_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ADC_DATA_WIDTH}] ${MODELPARAM_VALUE.ADC_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DMA_DATA_WIDTH { MODELPARAM_VALUE.DMA_DATA_WIDTH PARAM_VALUE.DMA_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DMA_DATA_WIDTH}] ${MODELPARAM_VALUE.DMA_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.AXI_DATA_WIDTH { MODELPARAM_VALUE.AXI_DATA_WIDTH PARAM_VALUE.AXI_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.AXI_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DMA_READY_ENABLE { MODELPARAM_VALUE.DMA_READY_ENABLE PARAM_VALUE.DMA_READY_ENABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DMA_READY_ENABLE}] ${MODELPARAM_VALUE.DMA_READY_ENABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.AXI_SIZE { MODELPARAM_VALUE.AXI_SIZE PARAM_VALUE.AXI_SIZE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.AXI_SIZE}] ${MODELPARAM_VALUE.AXI_SIZE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.AXI_LENGTH { MODELPARAM_VALUE.AXI_LENGTH PARAM_VALUE.AXI_LENGTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.AXI_LENGTH}] ${MODELPARAM_VALUE.AXI_LENGTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.AXI_ADDRESS { MODELPARAM_VALUE.AXI_ADDRESS PARAM_VALUE.AXI_ADDRESS } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.AXI_ADDRESS}] ${MODELPARAM_VALUE.AXI_ADDRESS}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.AXI_ADDRESS_LIMIT { MODELPARAM_VALUE.AXI_ADDRESS_LIMIT PARAM_VALUE.AXI_ADDRESS_LIMIT } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.AXI_ADDRESS_LIMIT}] ${MODELPARAM_VALUE.AXI_ADDRESS_LIMIT}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user