Archived
initial commit
This commit is contained in:
@@ -0,0 +1,21 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_dacfifo
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XILINX_DEPS += ../../common/ad_axis_inf_rx.v
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XILINX_DEPS += ../../common/ad_b2g.v
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XILINX_DEPS += ../../common/ad_g2b.v
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XILINX_DEPS += ../../common/ad_mem.v
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XILINX_DEPS += ../../common/ad_mem_asym.v
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XILINX_DEPS += ../../util_dacfifo/util_dacfifo_bypass.v
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XILINX_DEPS += axi_dacfifo.v
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XILINX_DEPS += axi_dacfifo_address_buffer.v
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XILINX_DEPS += axi_dacfifo_constr.xdc
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XILINX_DEPS += axi_dacfifo_ip.tcl
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XILINX_DEPS += axi_dacfifo_rd.v
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XILINX_DEPS += axi_dacfifo_wr.v
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include ../../scripts/library.mk
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@@ -0,0 +1,3 @@
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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eof:
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@@ -0,0 +1,6 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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<labtools version="1" minor="0"/>
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@@ -0,0 +1,282 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
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||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
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||||
//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
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||||
//
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||||
// Redistribution and use of source or resulting binaries, with or without modification
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||||
// of this file, are permitted under one of the following two license terms:
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||||
//
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||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
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||||
// of this repository (LICENSE_GPL2), and also online at:
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||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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||||
//
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||||
// OR
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||||
//
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||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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||||
// This will allow to generate bit files and not release the source code,
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||||
// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dacfifo #(
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parameter DAC_DATA_WIDTH = 64,
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parameter DMA_DATA_WIDTH = 64,
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parameter AXI_DATA_WIDTH = 512,
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parameter AXI_SIZE = 2,
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parameter AXI_LENGTH = 15,
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parameter AXI_ADDRESS = 32'h00000000,
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parameter AXI_ADDRESS_LIMIT = 32'hffffffff) (
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// dma interface (AXI Stream)
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input dma_clk,
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input dma_rst,
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input dma_valid,
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input [(DMA_DATA_WIDTH-1):0] dma_data,
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output reg dma_ready,
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input dma_xfer_req,
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input dma_xfer_last,
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// dac interface
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input dac_clk,
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input dac_rst,
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input dac_valid,
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output reg [(DAC_DATA_WIDTH-1):0] dac_data,
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output reg dac_dunf,
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output reg dac_xfer_out,
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input bypass,
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// axi interface
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input axi_clk,
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input axi_resetn,
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output axi_awvalid,
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output [ 3:0] axi_awid,
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output [ 1:0] axi_awburst,
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output axi_awlock,
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output [ 3:0] axi_awcache,
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output [ 2:0] axi_awprot,
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output [ 3:0] axi_awqos,
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output [ 7:0] axi_awlen,
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output [ 2:0] axi_awsize,
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output [ 31:0] axi_awaddr,
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input axi_awready,
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output axi_wvalid,
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output [(AXI_DATA_WIDTH-1):0] axi_wdata,
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output [(AXI_DATA_WIDTH/8-1):0] axi_wstrb,
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output axi_wlast,
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input axi_wready,
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input axi_bvalid,
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input [ 3:0] axi_bid,
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input [ 1:0] axi_bresp,
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output axi_bready,
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output axi_arvalid,
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output [ 3:0] axi_arid,
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output [ 1:0] axi_arburst,
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output axi_arlock,
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output [ 3:0] axi_arcache,
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output [ 2:0] axi_arprot,
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output [ 3:0] axi_arqos,
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output [ 7:0] axi_arlen,
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output [ 2:0] axi_arsize,
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output [ 31:0] axi_araddr,
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input axi_arready,
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input axi_rvalid,
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input [ 3:0] axi_rid,
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input [ 1:0] axi_rresp,
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input axi_rlast,
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input [(AXI_DATA_WIDTH-1):0] axi_rdata,
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output axi_rready);
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localparam FIFO_BYPASS = (DAC_DATA_WIDTH == DMA_DATA_WIDTH) ? 1 : 0;
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reg dma_bypass_m1 = 1'b0;
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reg dma_bypass = 1'b0;
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reg dac_bypass_m1 = 1'b0;
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reg dac_bypass = 1'b0;
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reg dac_xfer_out_m1 = 1'b0;
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reg dac_xfer_out_bypass = 1'b0;
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wire axi_xfer_req_s;
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(* dont_touch = "true" *) wire [31:0] axi_last_addr_s;
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(* dont_touch = "true" *) wire [ 7:0] axi_last_beats_s;
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wire [ 3:0] dma_last_beats_s;
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wire [(DAC_DATA_WIDTH-1):0] dac_data_fifo_s;
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wire [(DAC_DATA_WIDTH-1):0] dac_data_bypass_s;
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wire dac_xfer_fifo_out_s;
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wire dac_dunf_fifo_s;
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wire dac_dunf_bypass_s;
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wire dma_ready_wr_s;
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axi_dacfifo_wr #(
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.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
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.AXI_SIZE (AXI_SIZE),
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.AXI_LENGTH (AXI_LENGTH),
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.AXI_ADDRESS (AXI_ADDRESS),
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.AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT),
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.DMA_MEM_ADDRESS_WIDTH (12)
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) i_wr (
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.dma_clk (dma_clk),
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.dma_rst (dma_rst),
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.dma_data (dma_data),
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.dma_ready (dma_ready),
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.dma_ready_out (dma_ready_wr_s),
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||||
.dma_valid (dma_valid),
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.dma_xfer_req (dma_xfer_req),
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.dma_xfer_last (dma_xfer_last),
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.dma_last_beats (dma_last_beats_s),
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.axi_last_addr (axi_last_addr_s),
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.axi_last_beats (axi_last_beats_s),
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.axi_xfer_out (axi_xfer_req_s),
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.axi_clk (axi_clk),
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.axi_resetn (axi_resetn),
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.axi_awvalid (axi_awvalid),
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.axi_awid (axi_awid),
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.axi_awburst (axi_awburst),
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.axi_awlock (axi_awlock),
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.axi_awcache (axi_awcache),
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.axi_awprot (axi_awprot),
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.axi_awqos (axi_awqos),
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.axi_awlen (axi_awlen),
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.axi_awsize (axi_awsize),
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.axi_awaddr (axi_awaddr),
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.axi_awready (axi_awready),
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.axi_wvalid (axi_wvalid),
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.axi_wdata (axi_wdata),
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.axi_wstrb (axi_wstrb),
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||||
.axi_wlast (axi_wlast),
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.axi_wready (axi_wready),
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.axi_bvalid (axi_bvalid),
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.axi_bid (axi_bid),
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||||
.axi_bresp (axi_bresp),
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.axi_bready (axi_bready),
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.axi_werror (axi_werror));
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axi_dacfifo_rd #(
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.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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.AXI_SIZE (AXI_SIZE),
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.AXI_LENGTH (AXI_LENGTH),
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.AXI_ADDRESS (AXI_ADDRESS),
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.DAC_DATA_WIDTH (DAC_DATA_WIDTH),
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.DAC_MEM_ADDRESS_WIDTH (12)
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) i_rd (
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.axi_xfer_req (axi_xfer_req_s),
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.axi_last_raddr (axi_last_addr_s),
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.axi_last_beats (axi_last_beats_s),
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.axi_clk (axi_clk),
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.axi_resetn (axi_resetn),
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||||
.axi_arvalid (axi_arvalid),
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.axi_arid (axi_arid),
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||||
.axi_arburst (axi_arburst),
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||||
.axi_arlock (axi_arlock),
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||||
.axi_arcache (axi_arcache),
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.axi_arprot (axi_arprot),
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||||
.axi_arqos (axi_arqos),
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||||
.axi_arlen (axi_arlen),
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||||
.axi_arsize (axi_arsize),
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||||
.axi_araddr (axi_araddr),
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||||
.axi_arready (axi_arready),
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||||
.axi_rvalid (axi_rvalid),
|
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.axi_rid (axi_rid),
|
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.axi_rresp (axi_rresp),
|
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.axi_rlast (axi_rlast),
|
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.axi_rdata (axi_rdata),
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.axi_rready (axi_rready),
|
||||
.axi_rerror (axi_rerror),
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||||
.dma_last_beats (dma_last_beats_s),
|
||||
.dac_clk (dac_clk),
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||||
.dac_rst (dac_rst),
|
||||
.dac_valid (dac_valid),
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||||
.dac_data (dac_data_fifo_s),
|
||||
.dac_xfer_out (dac_xfer_fifo_out_s),
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.dac_dunf (dac_dunf_fifo_s));
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// bypass logic -- supported if DAC_DATA_WIDTH == DMA_DATA_WIDTH
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generate
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if (FIFO_BYPASS) begin
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util_dacfifo_bypass #(
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.DAC_DATA_WIDTH (DAC_DATA_WIDTH),
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.DMA_DATA_WIDTH (DMA_DATA_WIDTH)
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) i_dacfifo_bypass (
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.dma_clk(dma_clk),
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.dma_data(dma_data),
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.dma_ready(dma_ready),
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||||
.dma_ready_out(dma_ready_bypass_s),
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.dma_valid(dma_valid),
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.dma_xfer_req(dma_xfer_req),
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.dac_clk(dac_clk),
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.dac_rst(dac_rst),
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.dac_valid(dac_valid),
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.dac_data(dac_data_bypass_s),
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.dac_dunf(dac_dunf_bypass_s)
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);
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always @(posedge dma_clk) begin
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dma_bypass_m1 <= bypass;
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dma_bypass <= dma_bypass_m1;
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end
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always @(posedge dac_clk) begin
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dac_bypass_m1 <= bypass;
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dac_bypass <= dac_bypass_m1;
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dac_xfer_out_m1 <= dma_xfer_req;
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dac_xfer_out_bypass <= dac_xfer_out_m1;
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end
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||||
// mux for the dma_ready
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always @(posedge dma_clk) begin
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dma_ready <= (dma_bypass) ? dma_ready_bypass_s : dma_ready_wr_s;
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end
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// mux for dac data
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always @(posedge dac_clk) begin
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if (dac_valid) begin
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dac_data <= (dac_bypass) ? dac_data_bypass_s : dac_data_fifo_s;
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end
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dac_xfer_out <= (dac_bypass) ? dac_xfer_out_bypass : dac_xfer_fifo_out_s;
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dac_dunf <= (dac_bypass) ? dac_dunf_bypass_s : dac_dunf_fifo_s;
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end
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end else begin /* if (~FIFO_BYPASS) */
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always @(posedge dma_clk) begin
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dma_ready <= dma_ready_wr_s;
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end
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always @(posedge dac_clk) begin
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if (dac_valid) begin
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dac_data <= dac_data_fifo_s;
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end
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dac_xfer_out <= dac_xfer_fifo_out_s;
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dac_dunf <= dac_dunf_fifo_s;
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end
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end
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endgenerate
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endmodule
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@@ -0,0 +1,445 @@
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||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo/axi_dacfifo.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="252fbf588687403fb6a397d8604efe32"/>
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<Option Name="Part" Val="xc7vx485tffg1157-1"/>
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<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
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<Option Name="CompiledLibDirXSim" Val=""/>
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<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
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<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
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||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
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||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
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||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
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<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
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||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
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||||
<Option Name="BoardPart" Val=""/>
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||||
<Option Name="ActiveSimSet" Val="sim_1"/>
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||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
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||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
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||||
<Option Name="DSAVendor" Val="xilinx"/>
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||||
<Option Name="DSANumComputeUnits" Val="60"/>
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<Option Name="WTXSimLaunchSim" Val="0"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
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||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
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||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
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<Option Name="WTActivehdlLaunchSim" Val="0"/>
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<Option Name="WTXSimExportSim" Val="0"/>
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<Option Name="WTModelSimExportSim" Val="0"/>
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||||
<Option Name="WTQuestaExportSim" Val="0"/>
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||||
<Option Name="WTIesExportSim" Val="0"/>
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||||
<Option Name="WTVcsExportSim" Val="0"/>
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||||
<Option Name="WTRivieraExportSim" Val="0"/>
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||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
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||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
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||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
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||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
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||||
<Filter Type="Srcs"/>
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||||
<File Path="$PPRDIR/../../common/ad_axis_inf_rx.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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||||
<Attr Name="UsedIn" Val="implementation"/>
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||||
<Attr Name="UsedIn" Val="simulation"/>
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||||
</FileInfo>
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||||
</File>
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||||
<File Path="$PPRDIR/../../common/ad_b2g.v">
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||||
<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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<File Path="$PPRDIR/../../common/ad_mem.v">
|
||||
<FileInfo>
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||||
<Attr Name="UsedIn" Val="synthesis"/>
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||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../common/ad_mem_asym.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_dacfifo_address_buffer.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_dacfifo_rd.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_dacfifo_wr.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../util_dacfifo/util_dacfifo_bypass.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_dacfifo.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_dacfifo"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/axi_dacfifo_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,79 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_dacfifo_address_buffer #(
|
||||
|
||||
parameter ADDRESS_WIDTH = 4,
|
||||
parameter DATA_WIDTH = 16)(
|
||||
|
||||
input clk,
|
||||
input rst,
|
||||
input wea,
|
||||
input [DATA_WIDTH-1:0] din,
|
||||
|
||||
input rea,
|
||||
output [DATA_WIDTH-1:0] dout);
|
||||
|
||||
reg [ADDRESS_WIDTH-1:0] waddr;
|
||||
reg [ADDRESS_WIDTH-1:0] raddr;
|
||||
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst == 1'b1) begin
|
||||
waddr <= 0;
|
||||
raddr <= 0;
|
||||
end else begin
|
||||
waddr <= (wea == 1'b1) ? waddr + 1'b1 : waddr;
|
||||
raddr <= (rea == 1'b1) ? raddr + 1'b1 : raddr;
|
||||
end
|
||||
end
|
||||
|
||||
ad_mem #(
|
||||
.DATA_WIDTH (DATA_WIDTH),
|
||||
.ADDRESS_WIDTH (ADDRESS_WIDTH))
|
||||
i_mem (
|
||||
.clka (clk),
|
||||
.wea (wea),
|
||||
.addra (waddr),
|
||||
.dina (din),
|
||||
.clkb (clk),
|
||||
.reb (1'b1),
|
||||
.addrb (raddr),
|
||||
.doutb (dout));
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,52 @@
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -hier *dma_mem_*_m*] \
|
||||
[get_cells -hier *axi_xfer_*_m*] \
|
||||
[get_cells -hier *axi_mem_*_m*] \
|
||||
[get_cells -hier *axi_dma_*_m*] \
|
||||
[get_cells -hier *dac_mem_*_m*] \
|
||||
[get_cells -hier *dac_xfer_*_m*] \
|
||||
[get_cells -hier *dac_last_*_m*] \
|
||||
[get_cells -hier *dac_bypass_m*]
|
||||
|
||||
# AXI clk to DMA clk
|
||||
set_false_path -from [get_cells -hier -filter {name =~ */axi_mem_raddr_g* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ */dma_mem_raddr_m1* && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ */axi_mem_last_read_toggle* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ */dma_mem_last_read_toggle_m_* && IS_SEQUENTIAL}]
|
||||
|
||||
# DAC clk to DMA clk
|
||||
set_false_path -from [get_cells -hier -filter {name =~ */dac_mem_raddr_g* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ */dma_mem_raddr_m1_* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ */dma_rst_m1_reg && IS_SEQUENTIAL}]
|
||||
|
||||
|
||||
# DMA clk to AXI clk
|
||||
set_false_path -from [get_cells -hier -filter {name =~ */dma_last_beats* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ */axi_dma_last_beats_m1* && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ */dma_mem_waddr_g* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ */axi_mem_waddr_m1* && IS_SEQUENTIAL}]
|
||||
#ignore timing only on the data, the synchronous reset of the FF is connected to the same clock domain
|
||||
set_false_path -through [get_pins -hier -filter {name =~ */axi_xfer_req_m_reg[0]/D}]
|
||||
|
||||
# DAC clk to AXI clk
|
||||
set_false_path -from [get_cells -hier -filter {name =~ */dac_mem_raddr_g* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ */axi_mem_raddr_m1* && IS_SEQUENTIAL}]
|
||||
|
||||
# DMA clk to DAC clk
|
||||
set_false_path -from [get_cells -hier -filter {name =~ */dma_mem_waddr_g* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ */dac_mem_waddr_m1* && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ */dma_last_beats* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ */dac_last_beats_m* && IS_SEQUENTIAL}]
|
||||
#ignore timing only on the data, the synchronous reset of the FF is connected to the same clock domain
|
||||
set_false_path -through [get_pins -hier -filter {name =~ */dac_xfer_out_m1_reg*/D}]
|
||||
|
||||
# AXI clk to DAC clk
|
||||
set_false_path -from [get_cells -hier -filter {name =~ */axi_mem_laddr* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ */dac_mem_laddr* && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ */axi_mem_laddr_toggle* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ */dac_mem_laddr_toggle_m* && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ */axi_mem_waddr_g* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ */dac_mem_waddr_m1* && IS_SEQUENTIAL}]
|
||||
#ignore timing only on the data, the synchronous reset of the FF is connected to the same clock domain
|
||||
set_false_path -through [get_pins -hier -filter {name =~ */dac_xfer_req_m_reg[0]/D}]
|
||||
|
||||
@@ -0,0 +1,811 @@
|
||||
|
||||
****** Vivado v2019.1.3 (64-bit)
|
||||
**** SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
**** IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
source axi_dacfifo_ip.tcl
|
||||
# source ../../scripts/adi_env.tcl
|
||||
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
|
||||
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
|
||||
## if [info exists ::env(ADI_HDL_DIR)] {
|
||||
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
|
||||
## }
|
||||
## if [info exists ::env(ADI_GHDL_DIR)] {
|
||||
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
|
||||
## }
|
||||
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
|
||||
### variable auto_set_param_list
|
||||
### variable auto_set_param_list_overwritable
|
||||
### variable fpga_series_list
|
||||
### variable fpga_family_list
|
||||
### variable speed_grade_list
|
||||
### variable dev_package_list
|
||||
### variable xcvr_type_list
|
||||
### variable fpga_voltage_list
|
||||
### set auto_set_param_list { \
|
||||
### DEV_PACKAGE \
|
||||
### SPEED_GRADE \
|
||||
### FPGA_FAMILY \
|
||||
### FPGA_TECHNOLOGY }
|
||||
### set auto_set_param_list_overwritable { \
|
||||
### FPGA_VOLTAGE \
|
||||
### XCVR_TYPE }
|
||||
### set fpga_technology_list { \
|
||||
### { Unknown 0 } \
|
||||
### { 7series 1 } \
|
||||
### { ultrascale 2 } \
|
||||
### { ultrascale+ 3 }}
|
||||
### set fpga_family_list { \
|
||||
### { Unknown 0 } \
|
||||
### { artix 1 } \
|
||||
### { kintex 2 } \
|
||||
### { virtex 3 } \
|
||||
### { zynq 4 }}
|
||||
### set speed_grade_list { \
|
||||
### { Unknown 0 } \
|
||||
### { -1 10 } \
|
||||
### { -1L 11 } \
|
||||
### { -1H 12 } \
|
||||
### { -1HV 13 } \
|
||||
### { -1LV 14 } \
|
||||
### { -2 20 } \
|
||||
### { -2L 21 } \
|
||||
### { -2LV 22 } \
|
||||
### { -3 30 }}
|
||||
### set dev_package_list { \
|
||||
### { Unknown 0 } \
|
||||
### { rf 1 } \
|
||||
### { fl 2 } \
|
||||
### { ff 3 } \
|
||||
### { fb 4 } \
|
||||
### { hc 5 } \
|
||||
### { fh 6 } \
|
||||
### { cs 7 } \
|
||||
### { cp 8 } \
|
||||
### { ft 9 } \
|
||||
### { fg 10 } \
|
||||
### { sb 11 } \
|
||||
### { rb 12 } \
|
||||
### { rs 13 } \
|
||||
### { cl 14 } \
|
||||
### { sf 15 } \
|
||||
### { ba 16 } \
|
||||
### { fa 17 } \
|
||||
### { fs 18 } \
|
||||
### { fi 19 }}
|
||||
### set xcvr_type_list { \
|
||||
### { Unknown 0 } \
|
||||
### { GTPE2_NOT_SUPPORTED 1 } \
|
||||
### { GTXE2 2 } \
|
||||
### { GTHE2_NOT_SUPPORTED 3 } \
|
||||
### { GTZE2_NOT_SUPPORTED 4 } \
|
||||
### { GTHE3 5 } \
|
||||
### { GTYE3_NOT_SUPPORTED 6 } \
|
||||
### { GTRE4_NOT_SUPPORTED 7 } \
|
||||
### { GTHE4 8 } \
|
||||
### { GTYE4 9 } \
|
||||
### { GTME4_NOT_SUPPORTED 10}}
|
||||
### set fpga_voltage_list {0 5000} ;
|
||||
### proc adi_device_spec {cellpath param} {
|
||||
###
|
||||
### set list_pointer [string tolower $param]
|
||||
### set list_pointer [append list_pointer "_list"]
|
||||
###
|
||||
### upvar 1 $list_pointer $list_pointer
|
||||
###
|
||||
### set ip [get_bd_cells $cellpath]
|
||||
### set part [get_property PART [current_project]]
|
||||
###
|
||||
### switch -regexp -- $param {
|
||||
### FPGA_TECHNOLOGY {
|
||||
### switch -regexp -- $part {
|
||||
### ^xc7 {set series_name 7series}
|
||||
### ^xczu {set series_name ultrascale+}
|
||||
### ^xc.u.p {set series_name ultrascale+}
|
||||
### ^xc.u {set series_name ultrascale }
|
||||
### default {
|
||||
### puts "Undefined fpga technology for \"$part\"!"
|
||||
### exit -1
|
||||
### }
|
||||
### }
|
||||
### return "$series_name"
|
||||
### }
|
||||
### FPGA_FAMILY {
|
||||
### set fpga_family [get_property FAMILY $part]
|
||||
### foreach i $fpga_family_list {
|
||||
### regexp ^[lindex $i 0] $fpga_family matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### SPEED_GRADE {
|
||||
### set speed_grade [get_property SPEED $part]
|
||||
### return "$speed_grade"
|
||||
### }
|
||||
### DEV_PACKAGE {
|
||||
### set dev_package [get_property PACKAGE $part]
|
||||
### foreach i $dev_package_list {
|
||||
### regexp ^[lindex $i 0] $dev_package matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### XCVR_TYPE {
|
||||
### set matched ""
|
||||
### set dev_transcivers "none"
|
||||
### foreach x [list_property $part] {
|
||||
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
|
||||
### }
|
||||
### foreach i $xcvr_type_list {
|
||||
### regexp ^[lindex $i 0] $dev_transcivers matched
|
||||
### }
|
||||
### if { $matched eq "" } {
|
||||
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### FPGA_VOLTAGE {
|
||||
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
|
||||
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
|
||||
###
|
||||
### return "$fpga_voltage"
|
||||
### }
|
||||
### default {
|
||||
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
|
||||
### }
|
||||
### }
|
||||
### }
|
||||
## if {![info exists REQUIRED_VIVADO_VERSION]} {
|
||||
## set REQUIRED_VIVADO_VERSION "2019.1"
|
||||
## }
|
||||
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
|
||||
## set IGNORE_VERSION_CHECK 1
|
||||
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
|
||||
## set IGNORE_VERSION_CHECK 0
|
||||
## }
|
||||
## proc adi_ip_ttcl {ip_name ip_constr_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
|
||||
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_sim_ttcl {ip_name ip_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
|
||||
## set f [ipx::add_file $ip_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_bd {ip_name ip_bd_files} {
|
||||
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
|
||||
## if {$proj_filegroup == {}} {
|
||||
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
|
||||
## }
|
||||
##
|
||||
## foreach file $ip_bd_files {
|
||||
## set f [ipx::add_file $file $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type tclSource \
|
||||
## ] $f
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_infer_streaming_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_ip_infer_mm_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
|
||||
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency $port
|
||||
## if {$driver_value != {}} {
|
||||
## set_property DRIVER_VALUE $driver_value $port
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_set_bus_dependency {bus prefix dependency} {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
|
||||
## adi_set_ports_dependency $prefix $dependency 0
|
||||
## }
|
||||
## proc adi_add_port_map {bus phys logic} {
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## }
|
||||
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## adi_add_port_map $bus {*}$port_map
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
|
||||
## for {set i 0} {$i < $num} {incr i} {
|
||||
## set bus_name [format "%s%d" $bus_name_prefix $i]
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## if {$dependency ne ""} {
|
||||
## set bus_dependency [string map [list "{i}" $i] $dependency]
|
||||
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
|
||||
## }
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## lassign $port_map phys logic width width_dep
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
|
||||
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
|
||||
## if {$width_dep ne ""} {
|
||||
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
|
||||
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
|
||||
## set width_dep_r "(($width_dep) * $i)"
|
||||
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
|
||||
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
|
||||
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
|
||||
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
|
||||
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
|
||||
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
|
||||
## set_property display_name $clock_inf_name $clock_inf
|
||||
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
|
||||
## set_property physical_name $clock_signal_name $clock_map
|
||||
##
|
||||
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
|
||||
## set_property value $bus_inf_name $assoc_busif
|
||||
##
|
||||
## if { $reset_signal_name != "" } {
|
||||
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
|
||||
## set_property value $reset_signal_name $assoc_reset
|
||||
##
|
||||
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
|
||||
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
|
||||
## set_property display_name $reset_inf_name $reset_inf
|
||||
## set_property interface_mode $reset_signal_mode $reset_inf
|
||||
## set reset_map [ipx::add_port_map "RST" $reset_inf]
|
||||
## set_property physical_name $reset_signal_name $reset_map
|
||||
##
|
||||
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
|
||||
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
|
||||
## set_property value "ACTIVE_LOW" $reset_polarity
|
||||
## } else {
|
||||
## set_property value "ACTIVE_HIGH" $reset_polarity
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_add_core_dependencies {vlnvs} {
|
||||
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
|
||||
## foreach vlnv $vlnvs {
|
||||
## ipx::add_subcore $vlnv $file_group
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_create {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
## global ad_ghdl_dir
|
||||
## global REQUIRED_VIVADO_VERSION
|
||||
## global IGNORE_VERSION_CHECK
|
||||
##
|
||||
## set VIVADO_VERSION [version -short]
|
||||
## if {$IGNORE_VERSION_CHECK} {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## }
|
||||
## } else {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "ERROR: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
|
||||
## exit 2
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## create_project $ip_name . -force
|
||||
##
|
||||
## ## Load custom message severity definitions
|
||||
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
|
||||
##
|
||||
## set lib_dirs $ad_hdl_dir/library
|
||||
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
|
||||
## lappend lib_dirs $ad_ghdl_dir/library
|
||||
## }
|
||||
##
|
||||
## set_property ip_repo_paths $lib_dirs [current_fileset]
|
||||
## update_ip_catalog
|
||||
## }
|
||||
## proc adi_ip_files {ip_name ip_files} {
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## foreach m_file $ip_files {
|
||||
## if {[file extension $m_file] eq ".xdc"} {
|
||||
## add_files -norecurse -fileset constrs_1 $m_file
|
||||
## } else {
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
|
||||
## }
|
||||
## }
|
||||
## set_property "top" "$ip_name" $proj_fileset
|
||||
## }
|
||||
## proc adi_ip_properties_lite {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
##
|
||||
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
|
||||
##
|
||||
## set_property name $ip_name [ipx::current_core]
|
||||
##
|
||||
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
|
||||
## set_property company_url {http://www.analog.com} [ipx::current_core]
|
||||
##
|
||||
## set i_families ""
|
||||
## foreach i_part [get_parts] {
|
||||
## lappend i_families [get_property FAMILY $i_part]
|
||||
## }
|
||||
## set i_families [lsort -unique $i_families]
|
||||
## set s_families [get_property supported_families [ipx::current_core]]
|
||||
## foreach i_family $i_families {
|
||||
## set s_families "$s_families $i_family Production"
|
||||
## set s_families "$s_families $i_family Beta"
|
||||
## }
|
||||
## set_property supported_families $s_families [ipx::current_core]
|
||||
##
|
||||
## ipx::save_core [ipx::current_core]
|
||||
##
|
||||
## ipx::remove_all_bus_interface [ipx::current_core]
|
||||
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
|
||||
## foreach map $memory_maps {
|
||||
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
|
||||
## }
|
||||
##
|
||||
## ipx::update_checksums [ipx::current_core]
|
||||
## ipx::save_core [ipx::current_core]
|
||||
## }
|
||||
## proc adi_ip_properties {ip_name} {
|
||||
##
|
||||
## adi_ip_properties_lite $ip_name
|
||||
##
|
||||
## ipx::infer_bus_interface {\
|
||||
## s_axi_awvalid \
|
||||
## s_axi_awaddr \
|
||||
## s_axi_awprot \
|
||||
## s_axi_awready \
|
||||
## s_axi_wvalid \
|
||||
## s_axi_wdata \
|
||||
## s_axi_wstrb \
|
||||
## s_axi_wready \
|
||||
## s_axi_bvalid \
|
||||
## s_axi_bresp \
|
||||
##
|
||||
## s_axi_bready \
|
||||
## s_axi_arvalid \
|
||||
## s_axi_araddr \
|
||||
## s_axi_arprot \
|
||||
## s_axi_arready \
|
||||
## s_axi_rvalid \
|
||||
## s_axi_rdata \
|
||||
## s_axi_rresp \
|
||||
## s_axi_rready} \
|
||||
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
|
||||
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
|
||||
##
|
||||
## if {$raddr_width != $waddr_width} {
|
||||
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
|
||||
## set range 65536
|
||||
## } else {
|
||||
## if {$raddr_width >= 16} {
|
||||
## set range 65536
|
||||
## } else {
|
||||
## set range [expr 1 << $raddr_width]
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
## set_property range $range [ipx::get_address_blocks axi_lite \
|
||||
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
|
||||
## ipx::save_core
|
||||
## }
|
||||
## proc adi_init_bd_tcl {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## if { [file exists bd] } {
|
||||
## file delete -force bd
|
||||
## }
|
||||
## file mkdir bd
|
||||
##
|
||||
## set bd_tcl [open "bd/bd.tcl" w]
|
||||
##
|
||||
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
|
||||
## puts $bd_tcl "proc init {cellpath otherInfo} {"
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl ""
|
||||
## set auto_set_param ""
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
|
||||
## puts $bd_tcl $auto_set_param
|
||||
## }
|
||||
##
|
||||
## set auto_set_overwritable_param ""
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_overwritable_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_overwritable_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
|
||||
## puts $bd_tcl $auto_set_overwritable_param
|
||||
## }
|
||||
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
|
||||
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
|
||||
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set parent_dir \"../\""
|
||||
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
|
||||
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
|
||||
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " break"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " append parent_dir \"../\""
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## close $bd_tcl
|
||||
##
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
|
||||
##
|
||||
## set local_mk [open "temporary_case_dependencies.mk" w]
|
||||
## seek $local_mk 0 start
|
||||
## puts $local_mk "CLEAN_TARGET += bd"
|
||||
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
|
||||
## close $local_mk
|
||||
## }
|
||||
## proc adi_add_auto_fpga_spec_params {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_device_spec_param {ip_param} {
|
||||
##
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## set list_pointer [string tolower $ip_param]
|
||||
## set list_pointer [append list_pointer "_list"]
|
||||
##
|
||||
## global $list_pointer
|
||||
##
|
||||
## # set j 1D list from the original list
|
||||
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
|
||||
##
|
||||
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
|
||||
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "range_long" \
|
||||
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
|
||||
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## } else {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "pairs" \
|
||||
## "value_validation_pairs" $j ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## }
|
||||
##
|
||||
## # FPGA info grup
|
||||
## set info_group_name "FPGA info"
|
||||
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
|
||||
## if { [string trim $info_group] eq "" } {
|
||||
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
|
||||
## -parent $page0 -display_name $info_group_name]
|
||||
## }
|
||||
##
|
||||
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
|
||||
## set_property -dict [list "widget" "comboBox" ] $p
|
||||
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
|
||||
## }
|
||||
## proc adi_if_define {name} {
|
||||
##
|
||||
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
|
||||
## ipx::create_bus_definition analog.com interface $name 1.0
|
||||
##
|
||||
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
|
||||
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
|
||||
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
|
||||
##
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## }
|
||||
## proc adi_if_ports {dir width name {type none}} {
|
||||
##
|
||||
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
|
||||
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
|
||||
## set_property master_presence required $m_intf
|
||||
## set_property slave_presence required $m_intf
|
||||
## set_property master_width $width $m_intf
|
||||
## set_property slave_width $width $m_intf
|
||||
##
|
||||
## set m_dir "in"
|
||||
## set s_dir "out"
|
||||
## if {$dir eq "output"} {
|
||||
## set m_dir "out"
|
||||
## set s_dir "in"
|
||||
## }
|
||||
##
|
||||
## set_property master_direction $m_dir $m_intf
|
||||
## set_property slave_direction $s_dir $m_intf
|
||||
##
|
||||
## if {$type ne "none"} {
|
||||
## set_property is_${type} true $m_intf
|
||||
## }
|
||||
##
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## }
|
||||
## proc adi_if_infer_bus {if_name mode name maps} {
|
||||
##
|
||||
## ipx::add_bus_interface $name [ipx::current_core]
|
||||
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
|
||||
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
|
||||
## set_property interface_mode $mode $m_bus_if
|
||||
##
|
||||
## foreach map $maps {
|
||||
## set m_maps [regexp -all -inline {\S+} $map]
|
||||
## lassign $m_maps p_name p_map
|
||||
## ipx::add_port_map $p_name $m_bus_if
|
||||
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
|
||||
## }
|
||||
## }
|
||||
# adi_ip_create axi_dacfifo
|
||||
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
|
||||
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1343} -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1306} -new_severity WARNING
|
||||
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
|
||||
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
|
||||
## set_msg_config -id {Synth 8-3331} -new_severity INFO
|
||||
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
|
||||
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
|
||||
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
|
||||
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'.)
|
||||
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
|
||||
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
|
||||
# adi_ip_files axi_dacfifo [list \
|
||||
# "$ad_hdl_dir/library/common/ad_g2b.v" \
|
||||
# "$ad_hdl_dir/library/common/ad_b2g.v" \
|
||||
# "$ad_hdl_dir/library/common/ad_mem_asym.v" \
|
||||
# "$ad_hdl_dir/library/common/ad_mem.v" \
|
||||
# "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
|
||||
# "$ad_hdl_dir/library/util_dacfifo/util_dacfifo_bypass.v" \
|
||||
# "axi_dacfifo_constr.xdc" \
|
||||
# "axi_dacfifo_wr.v" \
|
||||
# "axi_dacfifo_rd.v" \
|
||||
# "axi_dacfifo_address_buffer.v" \
|
||||
# "axi_dacfifo.v"]
|
||||
# adi_ip_properties_lite axi_dacfifo
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_axis_inf_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_b2g.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_g2b.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo/util_dacfifo_bypass.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_axis_inf_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_b2g.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_g2b.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo/util_dacfifo_bypass.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
WARNING: [IP_Flow 19-5150] The Range '(DAC_DATA_WIDTH - 1):0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dac' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5150] The Range '(AXI_DATA_WIDTH - 1):0' is present in all ports of the interface 'axi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5150] The Range '(AXI_DATA_WIDTH - 1):0' is present in all ports of the interface 'axi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5150] The Range '(DAC_DATA_WIDTH - 1):0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5150] The Range '(DMA_DATA_WIDTH - 1):0' is present in all ports of the interface 'dma'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'axi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'axi_resetn'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dac_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_rst'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dma_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_rst'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data' and definition port 'DATA'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_xfer_req' and definition port 'XFER_REQ'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'dma': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'axi_wdata' and definition port 'wdata'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'axi_rdata' and definition port 'rdata'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'axi_clk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'dac_clk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'dma_clk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
# ipx::infer_bus_interface {\
|
||||
# axi_awvalid \
|
||||
# axi_awid \
|
||||
# axi_awburst \
|
||||
# axi_awlock \
|
||||
# axi_awcache \
|
||||
# axi_awprot \
|
||||
# axi_awqos \
|
||||
# axi_awlen \
|
||||
# axi_awsize \
|
||||
# axi_awaddr \
|
||||
# axi_awready \
|
||||
# axi_wvalid \
|
||||
# axi_wdata \
|
||||
# axi_wstrb \
|
||||
# axi_wlast \
|
||||
# axi_wready \
|
||||
# axi_bvalid \
|
||||
# axi_bid \
|
||||
# axi_bresp \
|
||||
# axi_bready \
|
||||
# axi_arvalid \
|
||||
# axi_arid \
|
||||
# axi_arburst \
|
||||
# axi_arlock \
|
||||
# axi_arcache \
|
||||
# axi_arprot \
|
||||
# axi_arqos \
|
||||
# axi_arlen \
|
||||
# axi_arsize \
|
||||
# axi_araddr \
|
||||
# axi_arready \
|
||||
# axi_rvalid \
|
||||
# axi_rid \
|
||||
# axi_rresp \
|
||||
# axi_rlast \
|
||||
# axi_rdata \
|
||||
# axi_rready} \
|
||||
# xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument).
|
||||
# ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'axi'.
|
||||
# ipx::infer_bus_interface axi_resetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_resetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'axi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'axi_resetn'.
|
||||
# ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \
|
||||
# -of_objects [ipx::current_core]]
|
||||
# set_property value axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
|
||||
# -of_objects [ipx::get_bus_interfaces axi_clk \
|
||||
# -of_objects [ipx::current_core]]]
|
||||
# ipx::add_address_space axi [ipx::current_core]
|
||||
# set_property master_address_space_ref axi [ipx::get_bus_interfaces axi \
|
||||
# -of_objects [ipx::current_core]]
|
||||
# set_property range 4294967296 [ipx::get_address_spaces axi \
|
||||
# -of_objects [ipx::current_core]]
|
||||
# set_property width 512 [ipx::get_address_spaces axi \
|
||||
# -of_objects [ipx::current_core]]
|
||||
# ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
# ipx::infer_bus_interface dma_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dma_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_rst'.
|
||||
# ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
# ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dac_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_rst'.
|
||||
# ipx::save_core [ipx::current_core]
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:20:20 2021...
|
||||
@@ -0,0 +1,85 @@
|
||||
# ip
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_dacfifo
|
||||
|
||||
adi_ip_files axi_dacfifo [list \
|
||||
"$ad_hdl_dir/library/common/ad_g2b.v" \
|
||||
"$ad_hdl_dir/library/common/ad_b2g.v" \
|
||||
"$ad_hdl_dir/library/common/ad_mem_asym.v" \
|
||||
"$ad_hdl_dir/library/common/ad_mem.v" \
|
||||
"$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
|
||||
"$ad_hdl_dir/library/util_dacfifo/util_dacfifo_bypass.v" \
|
||||
"axi_dacfifo_constr.xdc" \
|
||||
"axi_dacfifo_wr.v" \
|
||||
"axi_dacfifo_rd.v" \
|
||||
"axi_dacfifo_address_buffer.v" \
|
||||
"axi_dacfifo.v"]
|
||||
|
||||
adi_ip_properties_lite axi_dacfifo
|
||||
|
||||
ipx::infer_bus_interface {\
|
||||
axi_awvalid \
|
||||
axi_awid \
|
||||
axi_awburst \
|
||||
axi_awlock \
|
||||
axi_awcache \
|
||||
axi_awprot \
|
||||
axi_awqos \
|
||||
axi_awlen \
|
||||
axi_awsize \
|
||||
axi_awaddr \
|
||||
axi_awready \
|
||||
axi_wvalid \
|
||||
axi_wdata \
|
||||
axi_wstrb \
|
||||
axi_wlast \
|
||||
axi_wready \
|
||||
axi_bvalid \
|
||||
axi_bid \
|
||||
axi_bresp \
|
||||
axi_bready \
|
||||
axi_arvalid \
|
||||
axi_arid \
|
||||
axi_arburst \
|
||||
axi_arlock \
|
||||
axi_arcache \
|
||||
axi_arprot \
|
||||
axi_arqos \
|
||||
axi_arlen \
|
||||
axi_arsize \
|
||||
axi_araddr \
|
||||
axi_arready \
|
||||
axi_rvalid \
|
||||
axi_rid \
|
||||
axi_rresp \
|
||||
axi_rlast \
|
||||
axi_rdata \
|
||||
axi_rready} \
|
||||
xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
|
||||
ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface axi_resetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \
|
||||
-of_objects [ipx::current_core]]
|
||||
set_property value axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
|
||||
-of_objects [ipx::get_bus_interfaces axi_clk \
|
||||
-of_objects [ipx::current_core]]]
|
||||
|
||||
ipx::add_address_space axi [ipx::current_core]
|
||||
set_property master_address_space_ref axi [ipx::get_bus_interfaces axi \
|
||||
-of_objects [ipx::current_core]]
|
||||
set_property range 4294967296 [ipx::get_address_spaces axi \
|
||||
-of_objects [ipx::current_core]]
|
||||
set_property width 512 [ipx::get_address_spaces axi \
|
||||
-of_objects [ipx::current_core]]
|
||||
|
||||
ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface dma_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
@@ -0,0 +1,485 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_dacfifo_rd #(
|
||||
|
||||
parameter AXI_DATA_WIDTH = 512,
|
||||
parameter AXI_SIZE = 2,
|
||||
parameter AXI_LENGTH = 15,
|
||||
parameter AXI_ADDRESS = 32'h00000000,
|
||||
parameter DAC_DATA_WIDTH = 64,
|
||||
parameter DAC_MEM_ADDRESS_WIDTH = 8) (
|
||||
|
||||
// xfer last for read/write synchronization
|
||||
|
||||
input axi_xfer_req,
|
||||
input [31:0] axi_last_raddr,
|
||||
input [ 7:0] axi_last_beats,
|
||||
|
||||
// axi read address and read data channels
|
||||
|
||||
input axi_clk,
|
||||
input axi_resetn,
|
||||
output reg axi_arvalid,
|
||||
output [ 3:0] axi_arid,
|
||||
output [ 1:0] axi_arburst,
|
||||
output axi_arlock,
|
||||
output [ 3:0] axi_arcache,
|
||||
output [ 2:0] axi_arprot,
|
||||
output [ 3:0] axi_arqos,
|
||||
output [ 7:0] axi_arlen,
|
||||
output [ 2:0] axi_arsize,
|
||||
output reg [31:0] axi_araddr,
|
||||
input axi_arready,
|
||||
input axi_rvalid,
|
||||
input [ 3:0] axi_rid,
|
||||
input [ 1:0] axi_rresp,
|
||||
input axi_rlast,
|
||||
input [(AXI_DATA_WIDTH-1):0] axi_rdata,
|
||||
output reg axi_rready,
|
||||
|
||||
// axi status
|
||||
|
||||
output reg axi_rerror,
|
||||
|
||||
// DAC interface
|
||||
|
||||
input [ 3:0] dma_last_beats,
|
||||
|
||||
input dac_clk,
|
||||
input dac_rst,
|
||||
input dac_valid,
|
||||
output [(DAC_DATA_WIDTH-1):0] dac_data,
|
||||
output dac_xfer_out,
|
||||
output reg dac_dunf);
|
||||
|
||||
`define max(a,b) {(a) > (b) ? (a) : (b)}
|
||||
`define min(a,b) {(a) < (b) ? (a) : (b)}
|
||||
|
||||
|
||||
localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
|
||||
localparam AXI_ARINCR = (AXI_LENGTH + 1) * AXI_BYTE_WIDTH;
|
||||
|
||||
localparam MIN_WIDTH = `min(AXI_DATA_WIDTH, DAC_DATA_WIDTH);
|
||||
localparam MAX_WIDTH = `max(AXI_DATA_WIDTH, DAC_DATA_WIDTH);
|
||||
localparam MEM_RATIO = MAX_WIDTH/MIN_WIDTH;
|
||||
localparam AXI_BIGGER = (MAX_WIDTH == AXI_DATA_WIDTH) ? 1 : 0;
|
||||
|
||||
localparam AXI_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_MEM_ADDRESS_WIDTH :
|
||||
(MEM_RATIO == 2) ? (DAC_MEM_ADDRESS_WIDTH + ((AXI_BIGGER == 1) ? (-1) : 1)) :
|
||||
(MEM_RATIO == 4) ? (DAC_MEM_ADDRESS_WIDTH + ((AXI_BIGGER == 1) ? (-2) : 2)) :
|
||||
(MEM_RATIO == 8) ? (DAC_MEM_ADDRESS_WIDTH + ((AXI_BIGGER == 1) ? (-3) : 3)) :
|
||||
(DAC_MEM_ADDRESS_WIDTH + ((AXI_BIGGER == 1) ? (-4) : 4));
|
||||
|
||||
localparam AXI_BUF_THRESHOLD_HI = (AXI_BIGGER) ? (2 * (AXI_LENGTH+1)) : (2 * (AXI_LENGTH+1) * MEM_RATIO);
|
||||
localparam DAC_BUF_THRESHOLD_HI = (AXI_BIGGER) ? (2 * (AXI_LENGTH+1) * MEM_RATIO) : (2 * (AXI_LENGTH+1));
|
||||
|
||||
localparam IDLE = 5'b00001;
|
||||
localparam XFER_STAGING = 5'b00010;
|
||||
localparam XFER_FULL_BURST = 5'b00100;
|
||||
localparam XFER_PARTIAL_BURST = 5'b01000;
|
||||
localparam XFER_END = 5'b10000;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg axi_data_req = 1'b0;
|
||||
reg [ 4:0] axi_read_state = 5'b0;
|
||||
reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr = 'd0;
|
||||
(* dont_touch = "true" *) reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_laddr = 'd0;
|
||||
reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_g = 'd0;
|
||||
(* dont_touch = "true" *) reg axi_mem_laddr_toggle = 1'b0;
|
||||
reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr = 'd0;
|
||||
reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m1 = 'd0;
|
||||
reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m2 = 'd0;
|
||||
reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_addr_diff = 'd0;
|
||||
reg [31:0] axi_araddr_prev = 'd0;
|
||||
|
||||
reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_raddr = 'd0;
|
||||
reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_raddr_g = 'd0;
|
||||
reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_waddr = 'd0;
|
||||
reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_waddr_m1 = 'd0;
|
||||
reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2 = 'd0;
|
||||
reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_laddr = 'd0;
|
||||
reg [ 3:0] dac_mem_laddr_toggle_m = 4'd0;
|
||||
reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_laddr_b = 'd0;
|
||||
reg dac_mem_valid = 1'b0;
|
||||
reg dac_mem_enable = 1'b0;
|
||||
reg [ 2:0] dac_xfer_req_m = 3'b0;
|
||||
reg [ 3:0] dac_last_beats = 4'b0;
|
||||
reg [ 3:0] dac_last_beats_m = 4'b0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire axi_fifo_reset_s;
|
||||
wire axi_dvalid_s;
|
||||
wire axi_dlast_s;
|
||||
wire [ AXI_MEM_ADDRESS_WIDTH:0] axi_mem_addr_diff_s;
|
||||
wire [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_s;
|
||||
wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_s;
|
||||
wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_laddr_s;
|
||||
wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_b2g_s;
|
||||
wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m2_g2b_s;
|
||||
|
||||
wire [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_raddr_b2g_s;
|
||||
wire [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2_g2b_s;
|
||||
wire [ DAC_MEM_ADDRESS_WIDTH:0] dac_mem_addr_diff_s;
|
||||
wire [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_laddr_s;
|
||||
|
||||
// Asymmetric memory to transfer data from AXI_MM interface to DAC FIFO
|
||||
// interface
|
||||
|
||||
ad_mem_asym #(
|
||||
.A_ADDRESS_WIDTH (AXI_MEM_ADDRESS_WIDTH),
|
||||
.A_DATA_WIDTH (AXI_DATA_WIDTH),
|
||||
.B_ADDRESS_WIDTH (DAC_MEM_ADDRESS_WIDTH),
|
||||
.B_DATA_WIDTH (DAC_DATA_WIDTH))
|
||||
i_mem_asym (
|
||||
.clka (axi_clk),
|
||||
.wea (axi_dvalid_s),
|
||||
.addra (axi_mem_waddr),
|
||||
.dina (axi_rdata),
|
||||
.clkb (dac_clk),
|
||||
.reb (1'b1),
|
||||
.addrb (dac_mem_raddr),
|
||||
.doutb (dac_data));
|
||||
|
||||
// reset signals
|
||||
|
||||
assign axi_fifo_reset_s = (axi_resetn == 1'b0) || (axi_xfer_req == 1'b0);
|
||||
assign dac_fifo_reset_s = (dac_rst == 1'b1) || (dac_xfer_req_m[2] == 1'b0);
|
||||
|
||||
// FSM to generate the all the AXI Read transactions
|
||||
|
||||
always @(posedge axi_clk) begin
|
||||
if (axi_fifo_reset_s == 1'b1) begin
|
||||
axi_read_state <= IDLE;
|
||||
end else begin
|
||||
case (axi_read_state)
|
||||
IDLE : begin
|
||||
if (axi_data_req == 1'b1) begin
|
||||
axi_read_state <= XFER_STAGING;
|
||||
end else begin
|
||||
axi_read_state <= IDLE;
|
||||
end
|
||||
end
|
||||
XFER_STAGING : begin
|
||||
if (axi_araddr + AXI_ARINCR <= axi_last_raddr) begin
|
||||
axi_read_state <= XFER_FULL_BURST;
|
||||
end else begin
|
||||
axi_read_state <= XFER_PARTIAL_BURST;
|
||||
end
|
||||
end
|
||||
XFER_FULL_BURST : begin
|
||||
if (axi_rready && axi_rvalid && axi_rlast) begin
|
||||
if (axi_araddr_prev == axi_last_raddr) begin
|
||||
axi_read_state <= XFER_END;
|
||||
end else begin
|
||||
axi_read_state <= IDLE;
|
||||
end
|
||||
end else begin
|
||||
axi_read_state <= XFER_FULL_BURST;
|
||||
end
|
||||
end
|
||||
XFER_PARTIAL_BURST : begin
|
||||
if (axi_rready && axi_rvalid && axi_rlast) begin
|
||||
axi_read_state <= XFER_END;
|
||||
end else begin
|
||||
axi_read_state <= XFER_PARTIAL_BURST;
|
||||
end
|
||||
end
|
||||
XFER_END : begin
|
||||
axi_read_state <= IDLE;
|
||||
end
|
||||
default : begin
|
||||
axi_read_state <= IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// AXI read address channel
|
||||
|
||||
always @(posedge axi_clk) begin
|
||||
if (axi_fifo_reset_s == 1'b1) begin
|
||||
axi_arvalid <= 'd0;
|
||||
axi_araddr <= AXI_ADDRESS;
|
||||
axi_araddr_prev <= AXI_ADDRESS;
|
||||
end else begin
|
||||
if (axi_arvalid == 1'b1) begin
|
||||
if (axi_arready == 1'b1) begin
|
||||
axi_arvalid <= 1'b0;
|
||||
end
|
||||
end else begin
|
||||
if (axi_read_state == XFER_STAGING) begin
|
||||
axi_arvalid <= 1'b1;
|
||||
end
|
||||
end
|
||||
// AXI read address generation
|
||||
if ((axi_arvalid == 1'b1) && (axi_arready == 1'b1)) begin
|
||||
axi_araddr <= (axi_read_state == XFER_FULL_BURST) ? (axi_araddr + AXI_ARINCR) :
|
||||
(axi_read_state == XFER_PARTIAL_BURST) ? AXI_ADDRESS : axi_araddr;
|
||||
axi_araddr_prev <= axi_araddr;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign axi_arid = 4'b0000;
|
||||
assign axi_arburst = 2'b01;
|
||||
assign axi_arlock = 1'b0;
|
||||
assign axi_arcache = 4'b0010;
|
||||
assign axi_arprot = 3'b000;
|
||||
assign axi_arqos = 4'b0000;
|
||||
assign axi_arlen = (axi_read_state == XFER_FULL_BURST) ? AXI_LENGTH :
|
||||
(axi_read_state == XFER_PARTIAL_BURST) ? axi_last_beats : AXI_LENGTH;
|
||||
assign axi_arsize = AXI_SIZE;
|
||||
|
||||
// AXI read data channel
|
||||
|
||||
assign axi_dvalid_s = axi_rvalid & axi_rready & axi_xfer_req;
|
||||
assign axi_dlast_s = (axi_araddr_prev == axi_last_raddr) ? axi_rlast : 0;
|
||||
|
||||
always @(posedge axi_clk) begin
|
||||
if (axi_fifo_reset_s == 1'b1) begin
|
||||
axi_rready <= 1'b0;
|
||||
axi_rerror <= 'd0;
|
||||
end else begin
|
||||
axi_rready <= axi_rvalid;
|
||||
axi_rerror <= axi_rvalid & axi_rresp[1];
|
||||
end
|
||||
end
|
||||
|
||||
// ASYNC MEM write control
|
||||
|
||||
always @(posedge axi_clk) begin
|
||||
if (axi_fifo_reset_s == 1'b1) begin
|
||||
axi_mem_waddr <= 'd0;
|
||||
axi_mem_waddr_g <= 'd0;
|
||||
axi_mem_laddr <= {AXI_MEM_ADDRESS_WIDTH{1'b1}};
|
||||
axi_mem_laddr_toggle <= 0;
|
||||
end else begin
|
||||
if (axi_dvalid_s == 1'b1) begin
|
||||
axi_mem_waddr <= axi_mem_waddr + 1'b1;
|
||||
if (axi_dlast_s == 1'b1) begin
|
||||
axi_mem_laddr <= axi_mem_waddr;
|
||||
axi_mem_laddr_toggle <= ~axi_mem_laddr_toggle;
|
||||
end
|
||||
end
|
||||
axi_mem_waddr_g <= axi_mem_waddr_b2g_s;
|
||||
end
|
||||
end
|
||||
|
||||
ad_b2g # (
|
||||
.DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
|
||||
) i_axi_mem_waddr_b2g (
|
||||
.din (axi_mem_waddr_s),
|
||||
.dout (axi_mem_waddr_b2g_s));
|
||||
|
||||
assign axi_mem_raddr_s = (MEM_RATIO == 1) ? axi_mem_raddr :
|
||||
(MEM_RATIO == 2) ? ((AXI_BIGGER == 1) ? axi_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):1] : {axi_mem_raddr, 1'b0}) :
|
||||
(MEM_RATIO == 4) ? ((AXI_BIGGER == 1) ? axi_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):2] : {axi_mem_raddr, 2'b0}) :
|
||||
(MEM_RATIO == 8) ? ((AXI_BIGGER == 1) ? axi_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):3] : {axi_mem_raddr, 3'b0}) :
|
||||
((AXI_BIGGER == 1) ? axi_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):4] : {axi_mem_raddr, 4'b0});
|
||||
assign axi_mem_waddr_s = (MEM_RATIO == 1) ? axi_mem_waddr :
|
||||
(MEM_RATIO == 2) ? ((AXI_BIGGER == 1) ? {axi_mem_waddr, 1'b0} : axi_mem_waddr[AXI_MEM_ADDRESS_WIDTH-1:1]) :
|
||||
(MEM_RATIO == 4) ? ((AXI_BIGGER == 1) ? {axi_mem_waddr, 2'b0} : axi_mem_waddr[AXI_MEM_ADDRESS_WIDTH-1:2]) :
|
||||
(MEM_RATIO == 8) ? ((AXI_BIGGER == 1) ? {axi_mem_waddr, 3'b0} : axi_mem_waddr[AXI_MEM_ADDRESS_WIDTH-1:3]) :
|
||||
((AXI_BIGGER == 1) ? {axi_mem_waddr, 4'b0} : axi_mem_waddr[AXI_MEM_ADDRESS_WIDTH-1:4]);
|
||||
|
||||
assign axi_mem_laddr_s = (MEM_RATIO == 1) ? axi_mem_laddr :
|
||||
(MEM_RATIO == 2) ? ((AXI_BIGGER == 1) ? {axi_mem_laddr, 1'b0} : axi_mem_laddr[AXI_MEM_ADDRESS_WIDTH-1:1]) :
|
||||
(MEM_RATIO == 4) ? ((AXI_BIGGER == 1) ? {axi_mem_laddr, 2'b0} : axi_mem_laddr[AXI_MEM_ADDRESS_WIDTH-1:2]) :
|
||||
(MEM_RATIO == 8) ? ((AXI_BIGGER == 1) ? {axi_mem_laddr, 3'b0} : axi_mem_laddr[AXI_MEM_ADDRESS_WIDTH-1:3]) :
|
||||
((AXI_BIGGER == 1) ? {axi_mem_laddr, 4'b0} : axi_mem_laddr[AXI_MEM_ADDRESS_WIDTH-1:4]);
|
||||
|
||||
assign axi_mem_addr_diff_s = {1'b1, axi_mem_waddr} - axi_mem_raddr_s;
|
||||
|
||||
always @(posedge axi_clk) begin
|
||||
if (axi_fifo_reset_s == 1'b1) begin
|
||||
axi_mem_addr_diff <= 'd0;
|
||||
axi_mem_raddr <= 'd0;
|
||||
axi_mem_raddr_m1 <= 'd0;
|
||||
axi_mem_raddr_m2 <= 'd0;
|
||||
axi_data_req <= 'd0;
|
||||
end else begin
|
||||
axi_mem_raddr_m1 <= dac_mem_raddr_g;
|
||||
axi_mem_raddr_m2 <= axi_mem_raddr_m1;
|
||||
axi_mem_raddr <= axi_mem_raddr_m2_g2b_s;
|
||||
axi_mem_addr_diff <= axi_mem_addr_diff_s[AXI_MEM_ADDRESS_WIDTH-1:0];
|
||||
// requesting AXI read access from the memory, if there is enough space
|
||||
// for a full burst in the async buffer
|
||||
if (axi_mem_addr_diff >= AXI_BUF_THRESHOLD_HI) begin
|
||||
axi_data_req <= 1'b0;
|
||||
end else begin
|
||||
axi_data_req <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
ad_g2b #(
|
||||
.DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
|
||||
) i_axi_mem_raddr_m2_g2b (
|
||||
.din (axi_mem_raddr_m2),
|
||||
.dout (axi_mem_raddr_m2_g2b_s));
|
||||
|
||||
// CDC for xfer_req signal
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_rst == 1'b1) begin
|
||||
dac_xfer_req_m <= 3'b0;
|
||||
end else begin
|
||||
dac_xfer_req_m <= {dac_xfer_req_m[1:0], axi_xfer_req};
|
||||
end
|
||||
end
|
||||
|
||||
assign dac_xfer_out = dac_xfer_req_m[2] & dac_mem_valid;
|
||||
|
||||
// CDC for write addresses from the DDRx clock domain
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_fifo_reset_s == 1'b1) begin
|
||||
dac_mem_waddr <= 'b0;
|
||||
dac_mem_waddr_m1 <= 'b0;
|
||||
dac_mem_waddr_m2 <= 'b0;
|
||||
dac_mem_laddr_toggle_m <= 4'b0;
|
||||
dac_mem_laddr <= 'b0;
|
||||
end else begin
|
||||
dac_mem_waddr_m1 <= axi_mem_waddr_g;
|
||||
dac_mem_waddr_m2 <= dac_mem_waddr_m1;
|
||||
dac_mem_waddr <= dac_mem_waddr_m2_g2b_s;
|
||||
dac_mem_laddr_toggle_m <= {dac_mem_laddr_toggle_m[2:0], axi_mem_laddr_toggle};
|
||||
dac_mem_laddr <= (dac_mem_laddr_toggle_m[2] ^ dac_mem_laddr_toggle_m[1]) ?
|
||||
axi_mem_laddr_s :
|
||||
dac_mem_laddr;
|
||||
end
|
||||
end
|
||||
|
||||
assign dac_laddr_wea = dac_mem_laddr_toggle_m[3] ^ dac_mem_laddr_toggle_m[2];
|
||||
assign dac_laddr_rea = ((dac_mem_raddr == dac_mem_laddr_b) &&
|
||||
(dac_xfer_out == 1'b1)) ? 1'b1 :1'b0;
|
||||
|
||||
axi_dacfifo_address_buffer #(
|
||||
.ADDRESS_WIDTH (4),
|
||||
.DATA_WIDTH (DAC_MEM_ADDRESS_WIDTH))
|
||||
i_laddress_buffer (
|
||||
.clk (dac_clk),
|
||||
.rst (dac_fifo_reset_s),
|
||||
.wea (dac_laddr_wea),
|
||||
.din (dac_mem_laddr),
|
||||
.rea (dac_laddr_rea),
|
||||
.dout (dac_mem_laddr_s));
|
||||
|
||||
ad_g2b #(
|
||||
.DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
|
||||
) i_dac_mem_waddr_m2_g2b (
|
||||
.din (dac_mem_waddr_m2),
|
||||
.dout (dac_mem_waddr_m2_g2b_s));
|
||||
|
||||
assign dac_mem_addr_diff_s = {1'b1, dac_mem_waddr} - dac_mem_raddr;
|
||||
|
||||
// ASYNC MEM read control
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_fifo_reset_s == 1'b1) begin
|
||||
dac_mem_enable <= 1'b0;
|
||||
dac_mem_valid <= 1'b0;
|
||||
end else begin
|
||||
if (dac_mem_dunf_s == 1'b1) begin
|
||||
dac_mem_enable <= 1'b0;
|
||||
end else if (dac_mem_addr_diff_s[(DAC_MEM_ADDRESS_WIDTH-1):0] >= DAC_BUF_THRESHOLD_HI) begin
|
||||
dac_mem_enable <= 1'b1;
|
||||
end
|
||||
dac_mem_valid <= (dac_mem_enable) ? dac_valid : 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// CDC for the dma_last_beats
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_fifo_reset_s == 1'b1) begin
|
||||
dac_last_beats <= 4'b0;
|
||||
dac_last_beats_m <= 4'b0;
|
||||
end else begin
|
||||
dac_last_beats_m <= dma_last_beats;
|
||||
dac_last_beats <= dac_last_beats_m;
|
||||
end
|
||||
end
|
||||
|
||||
// If the MEM_RATIO is grater than one, it can happen that not all the DAC beats from
|
||||
// an AXI beat are valid. In this case the invalid data is dropped.
|
||||
// The axi_dlast indicates the last AXI beat. The valid number of DAC beats on the last AXI beat
|
||||
// commes from the AXI write module. (axi_dacfifo_wr.v)
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_fifo_reset_s == 1'b1) begin
|
||||
dac_mem_raddr <= 'd0;
|
||||
dac_mem_laddr_b <= 'd0;
|
||||
dac_mem_raddr_g <= 'd0;
|
||||
end else begin
|
||||
dac_mem_laddr_b <= dac_mem_laddr_s;
|
||||
if (dac_mem_valid == 1'b1) begin
|
||||
if ((dac_last_beats != 0) &&
|
||||
(dac_mem_raddr == (dac_mem_laddr_b + dac_last_beats - 1))) begin
|
||||
dac_mem_raddr <= dac_mem_raddr + (MEM_RATIO - (dac_last_beats - 1));
|
||||
end else begin
|
||||
dac_mem_raddr <= dac_mem_raddr + 1'b1;
|
||||
end
|
||||
end
|
||||
dac_mem_raddr_g <= dac_mem_raddr_b2g_s;
|
||||
end
|
||||
end
|
||||
|
||||
ad_b2g # (
|
||||
.DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
|
||||
) i_dac_mem_raddr_b2g (
|
||||
.din (dac_mem_raddr),
|
||||
.dout (dac_mem_raddr_b2g_s));
|
||||
|
||||
// underflow generation, there is no overflow
|
||||
|
||||
assign dac_mem_dunf_s = (dac_mem_addr_diff_s[(DAC_MEM_ADDRESS_WIDTH-1):0] == 0) ? 1'b1 : 1'b0;
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if(dac_fifo_reset_s == 1'b1) begin
|
||||
dac_dunf <= 1'b0;
|
||||
end else begin
|
||||
dac_dunf <= dac_mem_dunf_s;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,564 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_dacfifo_wr #(
|
||||
|
||||
parameter AXI_DATA_WIDTH = 512,
|
||||
parameter DMA_DATA_WIDTH = 64,
|
||||
parameter AXI_SIZE = 6,
|
||||
parameter AXI_LENGTH = 15,
|
||||
parameter AXI_ADDRESS = 32'h00000000,
|
||||
parameter AXI_ADDRESS_LIMIT = 32'h00000000,
|
||||
parameter DMA_MEM_ADDRESS_WIDTH = 8) (
|
||||
|
||||
// dma fifo interface
|
||||
|
||||
input dma_clk,
|
||||
input dma_rst,
|
||||
input [(DMA_DATA_WIDTH-1):0] dma_data,
|
||||
input dma_ready,
|
||||
output reg dma_ready_out,
|
||||
input dma_valid,
|
||||
|
||||
// request and syncronizaiton
|
||||
|
||||
input dma_xfer_req,
|
||||
input dma_xfer_last,
|
||||
(* dont_touch = "true" *) output reg [ 3:0] dma_last_beats,
|
||||
|
||||
// last address for read side
|
||||
|
||||
output reg [31:0] axi_last_addr,
|
||||
output reg [ 7:0] axi_last_beats,
|
||||
output reg axi_xfer_out,
|
||||
|
||||
// axi write address, write data and write response channels
|
||||
|
||||
input axi_clk,
|
||||
input axi_resetn,
|
||||
output reg axi_awvalid,
|
||||
output [ 3:0] axi_awid,
|
||||
output [ 1:0] axi_awburst,
|
||||
output axi_awlock,
|
||||
output [ 3:0] axi_awcache,
|
||||
output [ 2:0] axi_awprot,
|
||||
output [ 3:0] axi_awqos,
|
||||
output [ 7:0] axi_awlen,
|
||||
output [ 2:0] axi_awsize,
|
||||
output reg [31:0] axi_awaddr,
|
||||
input axi_awready,
|
||||
output axi_wvalid,
|
||||
output [(AXI_DATA_WIDTH-1):0] axi_wdata,
|
||||
output [((AXI_DATA_WIDTH/8)-1):0] axi_wstrb,
|
||||
output axi_wlast,
|
||||
input axi_wready,
|
||||
input axi_bvalid,
|
||||
input [ 3:0] axi_bid,
|
||||
input [ 1:0] axi_bresp,
|
||||
output axi_bready,
|
||||
|
||||
output reg axi_werror);
|
||||
|
||||
`define max(a,b) {(a) > (b) ? (a) : (b)}
|
||||
`define min(a,b) {(a) < (b) ? (a) : (b)}
|
||||
|
||||
localparam MIN_WIDTH = `min(AXI_DATA_WIDTH, DMA_DATA_WIDTH);
|
||||
localparam MAX_WIDTH = `max(AXI_DATA_WIDTH, DMA_DATA_WIDTH);
|
||||
localparam MEM_RATIO = MAX_WIDTH/MIN_WIDTH;
|
||||
localparam AXI_BIGGER = (MAX_WIDTH == AXI_DATA_WIDTH) ? 1 : 0;
|
||||
|
||||
localparam AXI_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DMA_MEM_ADDRESS_WIDTH :
|
||||
(MEM_RATIO == 2) ? (DMA_MEM_ADDRESS_WIDTH + ((AXI_BIGGER == 1) ? (-1) : 1)) :
|
||||
(MEM_RATIO == 4) ? (DMA_MEM_ADDRESS_WIDTH + ((AXI_BIGGER == 1) ? (-2) : 2)) :
|
||||
(MEM_RATIO == 8) ? (DMA_MEM_ADDRESS_WIDTH + ((AXI_BIGGER == 1) ? (-3) : 3)) :
|
||||
(DMA_MEM_ADDRESS_WIDTH + ((AXI_BIGGER == 1) ? (-4) : 4));
|
||||
|
||||
localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
|
||||
localparam AXI_AWINCR = (AXI_LENGTH + 1) * AXI_BYTE_WIDTH;
|
||||
localparam DMA_BUF_THRESHOLD_HI = {(DMA_MEM_ADDRESS_WIDTH){1'b1}} - 4;
|
||||
|
||||
// FSM state definition
|
||||
|
||||
localparam IDLE = 9'b000000001;
|
||||
localparam XFER_STAGING = 9'b000000010;
|
||||
localparam XFER_FULL_BURST = 9'b000000100;
|
||||
localparam XFER_FB_WLAST = 9'b000001000;
|
||||
localparam XFER_PARTIAL_BURST = 9'b000010000;
|
||||
localparam XFER_PB_WLAST = 9'b000100000;
|
||||
localparam XFER_LAST_BURST = 9'b001000000;
|
||||
localparam XFER_LB_WLAST = 9'b010000000;
|
||||
localparam XFER_END = 9'b100000000;
|
||||
|
||||
// registers
|
||||
|
||||
reg [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_waddr = 'd0;
|
||||
reg [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_waddr_g = 'd0;
|
||||
reg [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_addr_diff = 'd0;
|
||||
reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_m1 = 'd0;
|
||||
reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2 = 'd0;
|
||||
reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr = 'd0;
|
||||
reg [ 2:0] dma_mem_last_read_toggle_m = 3'b0;
|
||||
reg [ 1:0] dma_xfer_req_d = 2'b0;
|
||||
|
||||
reg [(DMA_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_m1 = 'd0;
|
||||
reg [(DMA_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_m2 = 'd0;
|
||||
reg [(DMA_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr = 'd0;
|
||||
reg axi_mem_rvalid = 1'b0;
|
||||
reg axi_mem_rvalid_d = 1'b0;
|
||||
reg axi_mem_last = 1'b0;
|
||||
reg axi_mem_last_d = 1'b0;
|
||||
reg [(AXI_DATA_WIDTH-1):0] axi_mem_rdata = 'd0;
|
||||
reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr = 'd0;
|
||||
reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_g = 'd0;
|
||||
reg axi_mem_read_en_d = 1'b0;
|
||||
reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_addr_diff = 'd0;
|
||||
reg axi_mem_last_read_toggle = 1'b0;
|
||||
reg [ 2:0] axi_xfer_req_m = 3'b0;
|
||||
reg axi_xfer_posedge = 1'b0;
|
||||
reg [ 7:0] axi_wvalid_counter = 8'b0;
|
||||
reg [ 7:0] axi_last_burst_length = 8'b0;
|
||||
(* dont_touch = "true" *)reg [ 8:0] axi_writer_state = 9'b0;
|
||||
reg [ 3:0] axi_dma_last_beats_m1 = 4'b0;
|
||||
reg [ 3:0] axi_dma_last_beats_m2 = 4'b0;
|
||||
reg axi_xlast;
|
||||
reg [ 3:0] axi_xfer_pburst_offset = 4'b1111;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire dma_fifo_reset_s;
|
||||
wire [(DMA_MEM_ADDRESS_WIDTH):0] dma_mem_addr_diff_s;
|
||||
wire [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_s;
|
||||
wire dma_mem_last_read_s;
|
||||
wire dma_xfer_posedge_s;
|
||||
wire dma_mem_wea_s;
|
||||
wire [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_waddr_b2g_s;
|
||||
wire [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2_g2b_s;
|
||||
wire axi_mem_read_en_s;
|
||||
wire [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_s;
|
||||
wire [AXI_MEM_ADDRESS_WIDTH:0] axi_mem_addr_diff_s;
|
||||
wire [(AXI_DATA_WIDTH-1):0] axi_mem_rdata_s;
|
||||
wire axi_mem_rvalid_s;
|
||||
wire axi_mem_last_s;
|
||||
wire [(DMA_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_m2_g2b_s;
|
||||
wire [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_b2g_s;
|
||||
wire axi_fifo_reset_s;
|
||||
wire axi_waddr_ready_s;
|
||||
wire axi_wready_s;
|
||||
wire axi_partial_burst_s;
|
||||
wire axi_xlast_s;
|
||||
wire axi_reset_s;
|
||||
|
||||
// Asymmetric memory to transfer data from DMAC interface to AXI Memory Map
|
||||
// interface
|
||||
|
||||
ad_mem_asym #(
|
||||
.A_ADDRESS_WIDTH (DMA_MEM_ADDRESS_WIDTH),
|
||||
.A_DATA_WIDTH (DMA_DATA_WIDTH),
|
||||
.B_ADDRESS_WIDTH (AXI_MEM_ADDRESS_WIDTH),
|
||||
.B_DATA_WIDTH (AXI_DATA_WIDTH))
|
||||
i_mem_asym (
|
||||
.clka (dma_clk),
|
||||
.wea (dma_mem_wea_s),
|
||||
.addra (dma_mem_waddr),
|
||||
.dina (dma_data),
|
||||
.clkb (axi_clk),
|
||||
.reb (1'b1),
|
||||
.addrb (axi_mem_raddr),
|
||||
.doutb (axi_mem_rdata_s));
|
||||
|
||||
assign axi_reset_s = ~axi_resetn;
|
||||
ad_axis_inf_rx #(.DATA_WIDTH(AXI_DATA_WIDTH)) i_axis_inf (
|
||||
.clk (axi_clk),
|
||||
.rst (axi_reset_s),
|
||||
.valid (axi_mem_rvalid_d),
|
||||
.last (axi_mem_last_d),
|
||||
.data (axi_mem_rdata),
|
||||
.inf_valid (axi_wvalid),
|
||||
.inf_last (axi_wlast),
|
||||
.inf_data (axi_wdata),
|
||||
.inf_ready (axi_wready));
|
||||
|
||||
// reset signals - all the registers reset at the positive edge of
|
||||
// dma_xfer_req
|
||||
|
||||
assign dma_xfer_posedge_s = ~dma_xfer_req_d[1] & dma_xfer_req_d[0];
|
||||
assign dma_fifo_reset_s = (dma_rst == 1'b1) || (dma_xfer_posedge_s == 1'b1);
|
||||
assign axi_fifo_reset_s = (axi_resetn == 1'b0) || (axi_xfer_posedge == 1'b1);
|
||||
|
||||
// DMA beat counter
|
||||
|
||||
always @(posedge dma_clk) begin
|
||||
dma_xfer_req_d <= {dma_xfer_req_d[0], dma_xfer_req};
|
||||
if (dma_fifo_reset_s == 1'b1) begin
|
||||
dma_last_beats <= 4'b0;
|
||||
end else begin
|
||||
if (dma_mem_wea_s == 1'b1) begin
|
||||
dma_last_beats <= (AXI_BIGGER == 1) ? ((dma_last_beats < MEM_RATIO-1) ? dma_last_beats + 4'b1 : 4'b0) : 4'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// ASYNC MEM write control
|
||||
|
||||
assign dma_mem_addr_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s;
|
||||
assign dma_mem_raddr_s = (MEM_RATIO == 1) ? dma_mem_raddr :
|
||||
(MEM_RATIO == 2) ? ((AXI_BIGGER == 1) ? {dma_mem_raddr, 1'b0} : dma_mem_raddr[AXI_MEM_ADDRESS_WIDTH-1:1]) :
|
||||
(MEM_RATIO == 4) ? ((AXI_BIGGER == 1) ? {dma_mem_raddr, 2'b0} : dma_mem_raddr[AXI_MEM_ADDRESS_WIDTH-1:2]) :
|
||||
(MEM_RATIO == 8) ? ((AXI_BIGGER == 1) ? {dma_mem_raddr, 3'b0} : dma_mem_raddr[AXI_MEM_ADDRESS_WIDTH-1:3]) :
|
||||
((AXI_BIGGER == 1) ? {dma_mem_raddr, 4'b0} : dma_mem_raddr[AXI_MEM_ADDRESS_WIDTH-1:4]);
|
||||
assign dma_mem_last_read_s = dma_mem_last_read_toggle_m[2] ^ dma_mem_last_read_toggle_m[1];
|
||||
assign dma_mem_wea_s = dma_xfer_req & dma_valid & dma_ready;
|
||||
|
||||
always @(posedge dma_clk) begin
|
||||
if (dma_fifo_reset_s == 1'b1) begin
|
||||
dma_mem_waddr <= 'h0;
|
||||
dma_mem_waddr_g <= 'h0;
|
||||
dma_mem_last_read_toggle_m <= 3'b0;
|
||||
end else begin
|
||||
dma_mem_last_read_toggle_m = {dma_mem_last_read_toggle_m[1:0], axi_mem_last_read_toggle};
|
||||
if (dma_mem_wea_s == 1'b1) begin
|
||||
dma_mem_waddr <= dma_mem_waddr + 1;
|
||||
end
|
||||
if (dma_mem_last_read_s == 1'b1) begin
|
||||
dma_mem_waddr <= 'h0;
|
||||
end
|
||||
dma_mem_waddr_g <= dma_mem_waddr_b2g_s;
|
||||
end
|
||||
end
|
||||
|
||||
ad_b2g # (
|
||||
.DATA_WIDTH(DMA_MEM_ADDRESS_WIDTH)
|
||||
) i_dma_mem_waddr_b2g (
|
||||
.din (dma_mem_waddr),
|
||||
.dout (dma_mem_waddr_b2g_s));
|
||||
|
||||
// The memory module request data until reaches the high threshold
|
||||
|
||||
always @(posedge dma_clk) begin
|
||||
if (dma_fifo_reset_s == 1'b1) begin
|
||||
dma_mem_addr_diff <= 'b0;
|
||||
dma_mem_raddr_m1 <= 'b0;
|
||||
dma_mem_raddr_m2 <= 'b0;
|
||||
dma_mem_raddr <= 'b0;
|
||||
dma_ready_out <= 1'b1;
|
||||
end else begin
|
||||
dma_mem_raddr_m1 <= axi_mem_raddr_g;
|
||||
dma_mem_raddr_m2 <= dma_mem_raddr_m1;
|
||||
dma_mem_raddr <= dma_mem_raddr_m2_g2b_s;
|
||||
dma_mem_addr_diff <= dma_mem_addr_diff_s[DMA_MEM_ADDRESS_WIDTH-1:0];
|
||||
if (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) begin
|
||||
dma_ready_out <= 1'b0;
|
||||
end else begin
|
||||
dma_ready_out <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
ad_g2b # (
|
||||
.DATA_WIDTH(AXI_MEM_ADDRESS_WIDTH)
|
||||
) i_dma_mem_raddr_g2b (
|
||||
.din (dma_mem_raddr_m2),
|
||||
.dout (dma_mem_raddr_m2_g2b_s));
|
||||
|
||||
assign axi_xlast_s = axi_wready & axi_wvalid & axi_wlast;
|
||||
|
||||
// FSM to generate the necessary AXI Write transactions
|
||||
|
||||
always @(posedge axi_clk) begin
|
||||
if (axi_fifo_reset_s == 1'b1) begin
|
||||
axi_writer_state <= IDLE;
|
||||
axi_xlast <= 1'b0;
|
||||
end
|
||||
else
|
||||
axi_xlast <= axi_xlast_s;
|
||||
case (axi_writer_state)
|
||||
IDLE : begin
|
||||
if (axi_xfer_req_m[2] == 1'b1) begin
|
||||
axi_writer_state <= XFER_STAGING;
|
||||
end else begin
|
||||
axi_writer_state <= IDLE;
|
||||
end
|
||||
end
|
||||
XFER_STAGING : begin
|
||||
if (axi_xfer_req_m[2] == 1'b1) begin
|
||||
// there are enough data for one transaction
|
||||
if (axi_mem_addr_diff >= AXI_LENGTH) begin
|
||||
axi_writer_state <= XFER_FULL_BURST;
|
||||
end else begin
|
||||
axi_writer_state <= XFER_STAGING;
|
||||
end
|
||||
end else if (axi_xfer_pburst_offset == 4'b0) begin // DMA transfer was finished
|
||||
if ((axi_mem_addr_diff > 0) ||
|
||||
(axi_dma_last_beats_m2 > 0)) begin
|
||||
axi_writer_state <= XFER_PARTIAL_BURST;
|
||||
end else begin
|
||||
axi_writer_state <= XFER_END;
|
||||
end
|
||||
end else begin
|
||||
axi_writer_state <= XFER_STAGING;
|
||||
end
|
||||
end
|
||||
// AXI transaction with full burst length
|
||||
XFER_FULL_BURST : begin
|
||||
if ((axi_wvalid_counter == axi_awlen) && (axi_mem_rvalid_s == 1'b1)) begin
|
||||
axi_writer_state <= XFER_FB_WLAST;
|
||||
end else begin
|
||||
axi_writer_state <= XFER_FULL_BURST;
|
||||
end
|
||||
end
|
||||
// Wait for the end of the transaction
|
||||
XFER_FB_WLAST : begin
|
||||
if (axi_xlast == 1'b1) begin
|
||||
axi_writer_state <= XFER_STAGING;
|
||||
end else begin
|
||||
axi_writer_state <= XFER_FB_WLAST;
|
||||
end
|
||||
end
|
||||
// AXI transaction with the remaining data, burst length is less than
|
||||
// the maximum supported burst length
|
||||
XFER_PARTIAL_BURST : begin
|
||||
if ((axi_wvalid_counter == axi_awlen) && (axi_mem_rvalid_s == 1'b1)) begin
|
||||
axi_writer_state <= XFER_PB_WLAST;
|
||||
end else begin
|
||||
axi_writer_state <= XFER_PARTIAL_BURST;
|
||||
end
|
||||
end
|
||||
// Wait for the end of the transaction
|
||||
XFER_PB_WLAST : begin
|
||||
if (axi_xlast == 1'b1) begin
|
||||
axi_writer_state <= XFER_END;
|
||||
end else begin
|
||||
axi_writer_state <= XFER_PB_WLAST;
|
||||
end
|
||||
end
|
||||
XFER_END : begin
|
||||
axi_writer_state <= IDLE;
|
||||
end
|
||||
default : begin
|
||||
axi_writer_state <= IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// FSM outputs
|
||||
|
||||
assign axi_mem_read_en_s = ((axi_writer_state == XFER_FULL_BURST) ||
|
||||
(axi_writer_state == XFER_PARTIAL_BURST)) ? 1 : 0;
|
||||
assign axi_partial_burst_s = ((axi_writer_state == XFER_PARTIAL_BURST) ||
|
||||
(axi_writer_state == XFER_PB_WLAST)) ? 1 : 0;
|
||||
|
||||
// CDC for the memory write address, xfer_req and xfer_last
|
||||
|
||||
always @(posedge axi_clk) begin
|
||||
if (axi_resetn == 1'b0) begin
|
||||
axi_xfer_req_m <= 3'b0;
|
||||
axi_xfer_posedge <= 1'b0;
|
||||
end else begin
|
||||
axi_xfer_req_m <= {axi_xfer_req_m[1:0], dma_xfer_req};
|
||||
axi_xfer_posedge <= ~axi_xfer_req_m[2] & axi_xfer_req_m[1];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge axi_clk) begin
|
||||
if (axi_fifo_reset_s == 1'b1) begin
|
||||
axi_mem_waddr_m1 <= 'b0;
|
||||
axi_mem_waddr_m2 <= 'b0;
|
||||
axi_mem_waddr <= 'b0;
|
||||
axi_xfer_pburst_offset <= 4'b1111;
|
||||
end else begin
|
||||
axi_mem_waddr_m1 <= dma_mem_waddr_g;
|
||||
axi_mem_waddr_m2 <= axi_mem_waddr_m1;
|
||||
axi_mem_waddr <= axi_mem_waddr_m2_g2b_s;
|
||||
if ((axi_xfer_req_m[2] == 0) && (axi_xfer_pburst_offset > 0)) begin
|
||||
axi_xfer_pburst_offset <= axi_xfer_pburst_offset - 4'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
ad_g2b # (
|
||||
.DATA_WIDTH(DMA_MEM_ADDRESS_WIDTH)
|
||||
) i_axi_mem_waddr_g2b (
|
||||
.din (axi_mem_waddr_m2),
|
||||
.dout (axi_mem_waddr_m2_g2b_s));
|
||||
|
||||
// ASYNC MEM read control
|
||||
|
||||
assign axi_mem_waddr_s = (MEM_RATIO == 1) ? axi_mem_waddr :
|
||||
(MEM_RATIO == 2) ? ((AXI_BIGGER == 1) ? axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):1] : {axi_mem_waddr, 1'b0}) :
|
||||
(MEM_RATIO == 4) ? ((AXI_BIGGER == 1) ? axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):2] : {axi_mem_waddr, 2'b0}) :
|
||||
(MEM_RATIO == 8) ? ((AXI_BIGGER == 1) ? axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):3] : {axi_mem_waddr, 3'b0}) :
|
||||
((AXI_BIGGER == 1) ? axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):4] : {axi_mem_waddr, 4'b0});
|
||||
assign axi_mem_addr_diff_s = {1'b1, axi_mem_waddr_s} - axi_mem_raddr;
|
||||
|
||||
|
||||
always @(posedge axi_clk) begin
|
||||
if (axi_fifo_reset_s == 1'b1) begin
|
||||
axi_mem_addr_diff <= 'b0;
|
||||
axi_mem_read_en_d <= 1'b0;
|
||||
end else begin
|
||||
axi_mem_addr_diff <= axi_mem_addr_diff_s[(AXI_MEM_ADDRESS_WIDTH-1):0];
|
||||
axi_mem_read_en_d <= axi_mem_read_en_s;
|
||||
end
|
||||
end
|
||||
|
||||
assign axi_wready_s = ~axi_wvalid | axi_wready;
|
||||
assign axi_mem_rvalid_s = axi_mem_read_en_s & axi_wready_s;
|
||||
assign axi_mem_last_s = (axi_wvalid_counter == axi_awlen) ? axi_mem_rvalid_s : 1'b0;
|
||||
|
||||
always @(posedge axi_clk) begin
|
||||
if (axi_fifo_reset_s == 1'b1) begin
|
||||
axi_mem_rvalid <= 1'b0;
|
||||
axi_mem_rvalid_d <= 1'b0;
|
||||
axi_mem_last <= 1'b0;
|
||||
axi_mem_last_d <= 1'b0;
|
||||
axi_mem_rdata <= 'b0;
|
||||
axi_mem_raddr <= 'b0;
|
||||
axi_wvalid_counter <= 8'b0;
|
||||
axi_mem_last_read_toggle <= 1'b0;
|
||||
axi_mem_raddr_g <= 'b0;
|
||||
end else begin
|
||||
axi_mem_rvalid <= axi_mem_rvalid_s;
|
||||
axi_mem_rvalid_d <= axi_mem_rvalid;
|
||||
axi_mem_last <= axi_mem_last_s;
|
||||
axi_mem_last_d <= axi_mem_last;
|
||||
axi_mem_rdata <= axi_mem_rdata_s;
|
||||
if (axi_mem_rvalid_s == 1'b1) begin
|
||||
axi_mem_raddr <= axi_mem_raddr + 1;
|
||||
axi_wvalid_counter <= (axi_wvalid_counter == axi_awlen) ? 0 : axi_wvalid_counter + 1;
|
||||
end
|
||||
if (axi_writer_state == XFER_END) begin
|
||||
axi_mem_raddr <= 'b0;
|
||||
axi_mem_last_read_toggle <= ~axi_mem_last_read_toggle;
|
||||
end
|
||||
axi_mem_raddr_g <= axi_mem_raddr_b2g_s;
|
||||
end
|
||||
end
|
||||
|
||||
ad_b2g # (
|
||||
.DATA_WIDTH(AXI_MEM_ADDRESS_WIDTH)
|
||||
) i_axi_mem_raddr_b2g (
|
||||
.din (axi_mem_raddr),
|
||||
.dout (axi_mem_raddr_b2g_s));
|
||||
|
||||
// AXI Memory Map interface write address channel
|
||||
|
||||
assign axi_awid = 4'b0000;
|
||||
assign axi_awburst = 2'b01; // INCR (Incrementing address burst)
|
||||
assign axi_awlock = 1'b0; // Normal access
|
||||
assign axi_awcache = 4'b0010; // Cacheable, but not allocate
|
||||
assign axi_awprot = 3'b000; // Normal, secure, data access
|
||||
assign axi_awqos = 4'b0000; // Not used
|
||||
assign axi_awlen = (axi_partial_burst_s == 1'b1) ? axi_last_burst_length : AXI_LENGTH;
|
||||
assign axi_awsize = AXI_SIZE;
|
||||
|
||||
assign axi_waddr_ready_s = axi_mem_read_en_s & ~axi_mem_read_en_d;
|
||||
|
||||
always @(posedge axi_clk) begin
|
||||
if (axi_fifo_reset_s == 1'b1) begin
|
||||
axi_awvalid <= 'd0;
|
||||
axi_awaddr <= AXI_ADDRESS;
|
||||
axi_xfer_out <= 1'b0;
|
||||
end else begin
|
||||
if (axi_awvalid == 1'b1) begin
|
||||
if (axi_awready == 1'b1) begin
|
||||
axi_awvalid <= 1'b0;
|
||||
end
|
||||
end else begin
|
||||
if (axi_waddr_ready_s == 1'b1) begin
|
||||
axi_awvalid <= 1'b1;
|
||||
end
|
||||
end
|
||||
if ((axi_awvalid == 1'b1) && (axi_awready == 1'b1)) begin
|
||||
axi_awaddr <= (axi_writer_state == XFER_FULL_BURST) ? (axi_awaddr + AXI_AWINCR) :
|
||||
(axi_writer_state == XFER_PARTIAL_BURST) ? (axi_awaddr + axi_last_burst_length * AXI_BYTE_WIDTH) :
|
||||
(axi_awaddr + AXI_AWINCR);
|
||||
end
|
||||
if (axi_writer_state == XFER_END) begin
|
||||
axi_xfer_out <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// write data channel controls
|
||||
|
||||
assign axi_wstrb = {AXI_BYTE_WIDTH{1'b1}};
|
||||
|
||||
// response channel
|
||||
|
||||
assign axi_bready = 1'b1;
|
||||
|
||||
always @(posedge axi_clk) begin
|
||||
if (axi_fifo_reset_s == 1'b1) begin
|
||||
axi_werror <= 'd0;
|
||||
end else begin
|
||||
axi_werror <= axi_bvalid & axi_bresp[1];
|
||||
end
|
||||
end
|
||||
|
||||
// AXI last address and last burst length
|
||||
|
||||
assign axi_dma_last_beats_active_s = (axi_dma_last_beats_m2 > 0) ? 1'b1 : 1'b0;
|
||||
always @(posedge axi_clk) begin
|
||||
if (axi_fifo_reset_s == 1'b1) begin
|
||||
axi_dma_last_beats_m1 <= 0;
|
||||
axi_dma_last_beats_m2 <= 0;
|
||||
axi_last_burst_length <= AXI_LENGTH;
|
||||
end else begin
|
||||
axi_dma_last_beats_m1 <= dma_last_beats;
|
||||
axi_dma_last_beats_m2 <= axi_dma_last_beats_m1;
|
||||
axi_last_burst_length <= ((axi_partial_burst_s) &&
|
||||
(axi_waddr_ready_s) &&
|
||||
(axi_dma_last_beats_active_s)) ? axi_mem_addr_diff :
|
||||
((axi_partial_burst_s) &&
|
||||
(axi_waddr_ready_s) &&
|
||||
(~axi_dma_last_beats_active_s)) ? (axi_mem_addr_diff-1) :
|
||||
axi_last_burst_length;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge axi_clk) begin
|
||||
if(axi_fifo_reset_s == 1'b1) begin
|
||||
axi_last_addr <= AXI_ADDRESS;
|
||||
axi_last_beats <= 8'b0;
|
||||
end else begin
|
||||
if ((axi_awready == 1'b1) && (axi_awvalid == 1'b1)) begin
|
||||
axi_last_addr <= axi_awaddr & (~AXI_AWINCR+1);
|
||||
axi_last_beats <= axi_last_burst_length;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Thu Dec 9 15:20:08 2021
|
||||
# Process ID: 8023
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo
|
||||
# Command line: vivado -mode batch -source axi_dacfifo_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source axi_dacfifo_ip.tcl
|
||||
@@ -0,0 +1,816 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Thu Dec 9 15:20:08 2021
|
||||
# Process ID: 8023
|
||||
# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo
|
||||
# Command line: vivado -mode batch -source axi_dacfifo_ip.tcl
|
||||
# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo/vivado.log
|
||||
# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source axi_dacfifo_ip.tcl
|
||||
# source ../../scripts/adi_env.tcl
|
||||
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
|
||||
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
|
||||
## if [info exists ::env(ADI_HDL_DIR)] {
|
||||
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
|
||||
## }
|
||||
## if [info exists ::env(ADI_GHDL_DIR)] {
|
||||
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
|
||||
## }
|
||||
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
|
||||
### variable auto_set_param_list
|
||||
### variable auto_set_param_list_overwritable
|
||||
### variable fpga_series_list
|
||||
### variable fpga_family_list
|
||||
### variable speed_grade_list
|
||||
### variable dev_package_list
|
||||
### variable xcvr_type_list
|
||||
### variable fpga_voltage_list
|
||||
### set auto_set_param_list { \
|
||||
### DEV_PACKAGE \
|
||||
### SPEED_GRADE \
|
||||
### FPGA_FAMILY \
|
||||
### FPGA_TECHNOLOGY }
|
||||
### set auto_set_param_list_overwritable { \
|
||||
### FPGA_VOLTAGE \
|
||||
### XCVR_TYPE }
|
||||
### set fpga_technology_list { \
|
||||
### { Unknown 0 } \
|
||||
### { 7series 1 } \
|
||||
### { ultrascale 2 } \
|
||||
### { ultrascale+ 3 }}
|
||||
### set fpga_family_list { \
|
||||
### { Unknown 0 } \
|
||||
### { artix 1 } \
|
||||
### { kintex 2 } \
|
||||
### { virtex 3 } \
|
||||
### { zynq 4 }}
|
||||
### set speed_grade_list { \
|
||||
### { Unknown 0 } \
|
||||
### { -1 10 } \
|
||||
### { -1L 11 } \
|
||||
### { -1H 12 } \
|
||||
### { -1HV 13 } \
|
||||
### { -1LV 14 } \
|
||||
### { -2 20 } \
|
||||
### { -2L 21 } \
|
||||
### { -2LV 22 } \
|
||||
### { -3 30 }}
|
||||
### set dev_package_list { \
|
||||
### { Unknown 0 } \
|
||||
### { rf 1 } \
|
||||
### { fl 2 } \
|
||||
### { ff 3 } \
|
||||
### { fb 4 } \
|
||||
### { hc 5 } \
|
||||
### { fh 6 } \
|
||||
### { cs 7 } \
|
||||
### { cp 8 } \
|
||||
### { ft 9 } \
|
||||
### { fg 10 } \
|
||||
### { sb 11 } \
|
||||
### { rb 12 } \
|
||||
### { rs 13 } \
|
||||
### { cl 14 } \
|
||||
### { sf 15 } \
|
||||
### { ba 16 } \
|
||||
### { fa 17 } \
|
||||
### { fs 18 } \
|
||||
### { fi 19 }}
|
||||
### set xcvr_type_list { \
|
||||
### { Unknown 0 } \
|
||||
### { GTPE2_NOT_SUPPORTED 1 } \
|
||||
### { GTXE2 2 } \
|
||||
### { GTHE2_NOT_SUPPORTED 3 } \
|
||||
### { GTZE2_NOT_SUPPORTED 4 } \
|
||||
### { GTHE3 5 } \
|
||||
### { GTYE3_NOT_SUPPORTED 6 } \
|
||||
### { GTRE4_NOT_SUPPORTED 7 } \
|
||||
### { GTHE4 8 } \
|
||||
### { GTYE4 9 } \
|
||||
### { GTME4_NOT_SUPPORTED 10}}
|
||||
### set fpga_voltage_list {0 5000} ;
|
||||
### proc adi_device_spec {cellpath param} {
|
||||
###
|
||||
### set list_pointer [string tolower $param]
|
||||
### set list_pointer [append list_pointer "_list"]
|
||||
###
|
||||
### upvar 1 $list_pointer $list_pointer
|
||||
###
|
||||
### set ip [get_bd_cells $cellpath]
|
||||
### set part [get_property PART [current_project]]
|
||||
###
|
||||
### switch -regexp -- $param {
|
||||
### FPGA_TECHNOLOGY {
|
||||
### switch -regexp -- $part {
|
||||
### ^xc7 {set series_name 7series}
|
||||
### ^xczu {set series_name ultrascale+}
|
||||
### ^xc.u.p {set series_name ultrascale+}
|
||||
### ^xc.u {set series_name ultrascale }
|
||||
### default {
|
||||
### puts "Undefined fpga technology for \"$part\"!"
|
||||
### exit -1
|
||||
### }
|
||||
### }
|
||||
### return "$series_name"
|
||||
### }
|
||||
### FPGA_FAMILY {
|
||||
### set fpga_family [get_property FAMILY $part]
|
||||
### foreach i $fpga_family_list {
|
||||
### regexp ^[lindex $i 0] $fpga_family matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### SPEED_GRADE {
|
||||
### set speed_grade [get_property SPEED $part]
|
||||
### return "$speed_grade"
|
||||
### }
|
||||
### DEV_PACKAGE {
|
||||
### set dev_package [get_property PACKAGE $part]
|
||||
### foreach i $dev_package_list {
|
||||
### regexp ^[lindex $i 0] $dev_package matched
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### XCVR_TYPE {
|
||||
### set matched ""
|
||||
### set dev_transcivers "none"
|
||||
### foreach x [list_property $part] {
|
||||
### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
|
||||
### }
|
||||
### foreach i $xcvr_type_list {
|
||||
### regexp ^[lindex $i 0] $dev_transcivers matched
|
||||
### }
|
||||
### if { $matched eq "" } {
|
||||
### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
|
||||
### }
|
||||
### return "$matched"
|
||||
### }
|
||||
### FPGA_VOLTAGE {
|
||||
### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
|
||||
### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
|
||||
###
|
||||
### return "$fpga_voltage"
|
||||
### }
|
||||
### default {
|
||||
### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
|
||||
### }
|
||||
### }
|
||||
### }
|
||||
## if {![info exists REQUIRED_VIVADO_VERSION]} {
|
||||
## set REQUIRED_VIVADO_VERSION "2019.1"
|
||||
## }
|
||||
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
|
||||
## set IGNORE_VERSION_CHECK 1
|
||||
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
|
||||
## set IGNORE_VERSION_CHECK 0
|
||||
## }
|
||||
## proc adi_ip_ttcl {ip_name ip_constr_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
|
||||
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_constr_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_sim_ttcl {ip_name ip_files} {
|
||||
##
|
||||
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
|
||||
## set f [ipx::add_file $ip_files $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type ttcl \
|
||||
## ] $f
|
||||
## ipx::reorder_files -front $ip_files $proj_filegroup
|
||||
## }
|
||||
## proc adi_ip_bd {ip_name ip_bd_files} {
|
||||
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
|
||||
## if {$proj_filegroup == {}} {
|
||||
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
|
||||
## }
|
||||
##
|
||||
## foreach file $ip_bd_files {
|
||||
## set f [ipx::add_file $file $proj_filegroup]
|
||||
## set_property -dict [list \
|
||||
## type tclSource \
|
||||
## ] $f
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_infer_streaming_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_ip_infer_mm_interfaces {ip_name} {
|
||||
##
|
||||
## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## }
|
||||
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
|
||||
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency $port
|
||||
## if {$driver_value != {}} {
|
||||
## set_property DRIVER_VALUE $driver_value $port
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_set_bus_dependency {bus prefix dependency} {
|
||||
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
|
||||
## adi_set_ports_dependency $prefix $dependency 0
|
||||
## }
|
||||
## proc adi_add_port_map {bus phys logic} {
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## }
|
||||
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## adi_add_port_map $bus {*}$port_map
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
|
||||
## for {set i 0} {$i < $num} {incr i} {
|
||||
## set bus_name [format "%s%d" $bus_name_prefix $i]
|
||||
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
|
||||
##
|
||||
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
|
||||
## set_property "BUS_TYPE_VLNV" $bus_type $bus
|
||||
## set_property "INTERFACE_MODE" $mode $bus
|
||||
##
|
||||
## if {$dependency ne ""} {
|
||||
## set bus_dependency [string map [list "{i}" $i] $dependency]
|
||||
## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
|
||||
## }
|
||||
##
|
||||
## foreach port_map $port_maps {
|
||||
## lassign $port_map phys logic width width_dep
|
||||
## set map [ipx::add_port_map $phys $bus]
|
||||
## set_property "PHYSICAL_NAME" $phys $map
|
||||
## set_property "LOGICAL_NAME" $logic $map
|
||||
## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
|
||||
## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
|
||||
## if {$width_dep ne ""} {
|
||||
## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
|
||||
## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
|
||||
## set width_dep_r "(($width_dep) * $i)"
|
||||
## set width_dep_l "(($width_dep) * ($i + 1)-1)"
|
||||
## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
|
||||
## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
|
||||
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
|
||||
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
|
||||
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
|
||||
## set_property display_name $clock_inf_name $clock_inf
|
||||
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
|
||||
## set_property physical_name $clock_signal_name $clock_map
|
||||
##
|
||||
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
|
||||
## set_property value $bus_inf_name $assoc_busif
|
||||
##
|
||||
## if { $reset_signal_name != "" } {
|
||||
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
|
||||
## set_property value $reset_signal_name $assoc_reset
|
||||
##
|
||||
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
|
||||
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
|
||||
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
|
||||
## set_property display_name $reset_inf_name $reset_inf
|
||||
## set_property interface_mode $reset_signal_mode $reset_inf
|
||||
## set reset_map [ipx::add_port_map "RST" $reset_inf]
|
||||
## set_property physical_name $reset_signal_name $reset_map
|
||||
##
|
||||
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
|
||||
## if {[string match {*[Nn]} $reset_signal_name] == 1} {
|
||||
## set_property value "ACTIVE_LOW" $reset_polarity
|
||||
## } else {
|
||||
## set_property value "ACTIVE_HIGH" $reset_polarity
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_add_core_dependencies {vlnvs} {
|
||||
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
|
||||
## foreach vlnv $vlnvs {
|
||||
## ipx::add_subcore $vlnv $file_group
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_ip_create {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
## global ad_ghdl_dir
|
||||
## global REQUIRED_VIVADO_VERSION
|
||||
## global IGNORE_VERSION_CHECK
|
||||
##
|
||||
## set VIVADO_VERSION [version -short]
|
||||
## if {$IGNORE_VERSION_CHECK} {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## }
|
||||
## } else {
|
||||
## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
|
||||
## puts -nonewline "ERROR: vivado version mismatch; "
|
||||
## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
|
||||
## puts -nonewline "got $VIVADO_VERSION.\n"
|
||||
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
|
||||
## exit 2
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## create_project $ip_name . -force
|
||||
##
|
||||
## ## Load custom message severity definitions
|
||||
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
|
||||
##
|
||||
## set lib_dirs $ad_hdl_dir/library
|
||||
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
|
||||
## lappend lib_dirs $ad_ghdl_dir/library
|
||||
## }
|
||||
##
|
||||
## set_property ip_repo_paths $lib_dirs [current_fileset]
|
||||
## update_ip_catalog
|
||||
## }
|
||||
## proc adi_ip_files {ip_name ip_files} {
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## foreach m_file $ip_files {
|
||||
## if {[file extension $m_file] eq ".xdc"} {
|
||||
## add_files -norecurse -fileset constrs_1 $m_file
|
||||
## } else {
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
|
||||
## }
|
||||
## }
|
||||
## set_property "top" "$ip_name" $proj_fileset
|
||||
## }
|
||||
## proc adi_ip_properties_lite {ip_name} {
|
||||
##
|
||||
## global ad_hdl_dir
|
||||
##
|
||||
## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
|
||||
##
|
||||
## set_property name $ip_name [ipx::current_core]
|
||||
##
|
||||
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
|
||||
## set_property company_url {http://www.analog.com} [ipx::current_core]
|
||||
##
|
||||
## set i_families ""
|
||||
## foreach i_part [get_parts] {
|
||||
## lappend i_families [get_property FAMILY $i_part]
|
||||
## }
|
||||
## set i_families [lsort -unique $i_families]
|
||||
## set s_families [get_property supported_families [ipx::current_core]]
|
||||
## foreach i_family $i_families {
|
||||
## set s_families "$s_families $i_family Production"
|
||||
## set s_families "$s_families $i_family Beta"
|
||||
## }
|
||||
## set_property supported_families $s_families [ipx::current_core]
|
||||
##
|
||||
## ipx::save_core [ipx::current_core]
|
||||
##
|
||||
## ipx::remove_all_bus_interface [ipx::current_core]
|
||||
## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
|
||||
## foreach map $memory_maps {
|
||||
## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
|
||||
## }
|
||||
##
|
||||
## ipx::update_checksums [ipx::current_core]
|
||||
## ipx::save_core [ipx::current_core]
|
||||
## }
|
||||
## proc adi_ip_properties {ip_name} {
|
||||
##
|
||||
## adi_ip_properties_lite $ip_name
|
||||
##
|
||||
## ipx::infer_bus_interface {\
|
||||
## s_axi_awvalid \
|
||||
## s_axi_awaddr \
|
||||
## s_axi_awprot \
|
||||
## s_axi_awready \
|
||||
## s_axi_wvalid \
|
||||
## s_axi_wdata \
|
||||
## s_axi_wstrb \
|
||||
## s_axi_wready \
|
||||
## s_axi_bvalid \
|
||||
## s_axi_bresp \
|
||||
##
|
||||
## s_axi_bready \
|
||||
## s_axi_arvalid \
|
||||
## s_axi_araddr \
|
||||
## s_axi_arprot \
|
||||
## s_axi_arready \
|
||||
## s_axi_rvalid \
|
||||
## s_axi_rdata \
|
||||
## s_axi_rresp \
|
||||
## s_axi_rready} \
|
||||
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
##
|
||||
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
|
||||
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
|
||||
##
|
||||
## if {$raddr_width != $waddr_width} {
|
||||
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
|
||||
## set range 65536
|
||||
## } else {
|
||||
## if {$raddr_width >= 16} {
|
||||
## set range 65536
|
||||
## } else {
|
||||
## set range [expr 1 << $raddr_width]
|
||||
## }
|
||||
## }
|
||||
##
|
||||
## ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
## set_property range $range [ipx::get_address_blocks axi_lite \
|
||||
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
|
||||
## ipx::save_core
|
||||
## }
|
||||
## proc adi_init_bd_tcl {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## if { [file exists bd] } {
|
||||
## file delete -force bd
|
||||
## }
|
||||
## file mkdir bd
|
||||
##
|
||||
## set bd_tcl [open "bd/bd.tcl" w]
|
||||
##
|
||||
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
|
||||
## puts $bd_tcl "proc init {cellpath otherInfo} {"
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl ""
|
||||
## set auto_set_param ""
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
|
||||
## puts $bd_tcl $auto_set_param
|
||||
## }
|
||||
##
|
||||
## set auto_set_overwritable_param ""
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
||||
## append auto_set_overwritable_param " $i \\\n"
|
||||
## }
|
||||
## }
|
||||
## if { $auto_set_overwritable_param ne "" } {
|
||||
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
|
||||
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
|
||||
## puts $bd_tcl $auto_set_overwritable_param
|
||||
## }
|
||||
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
|
||||
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
||||
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
|
||||
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " set parent_dir \"../\""
|
||||
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
|
||||
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
|
||||
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
|
||||
## puts $bd_tcl " break"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " append parent_dir \"../\""
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl ""
|
||||
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
|
||||
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
|
||||
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
||||
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
||||
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl " }"
|
||||
## puts $bd_tcl "}"
|
||||
## puts $bd_tcl ""
|
||||
## close $bd_tcl
|
||||
##
|
||||
## set proj_fileset [get_filesets sources_1]
|
||||
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
|
||||
##
|
||||
## set local_mk [open "temporary_case_dependencies.mk" w]
|
||||
## seek $local_mk 0 start
|
||||
## puts $local_mk "CLEAN_TARGET += bd"
|
||||
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
|
||||
## close $local_mk
|
||||
## }
|
||||
## proc adi_add_auto_fpga_spec_params {} {
|
||||
##
|
||||
## global auto_set_param_list
|
||||
## global auto_set_param_list_overwritable
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## foreach i $auto_set_param_list {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## foreach i $auto_set_param_list_overwritable {
|
||||
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
||||
## adi_add_device_spec_param $i
|
||||
## }
|
||||
## }
|
||||
## }
|
||||
## proc adi_add_device_spec_param {ip_param} {
|
||||
##
|
||||
## set cc [ipx::current_core]
|
||||
##
|
||||
## set list_pointer [string tolower $ip_param]
|
||||
## set list_pointer [append list_pointer "_list"]
|
||||
##
|
||||
## global $list_pointer
|
||||
##
|
||||
## # set j 1D list from the original list
|
||||
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
|
||||
##
|
||||
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
|
||||
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "range_long" \
|
||||
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
|
||||
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## } else {
|
||||
## set_property -dict [list \
|
||||
## "value_validation_type" "pairs" \
|
||||
## "value_validation_pairs" $j ] \
|
||||
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
||||
## }
|
||||
##
|
||||
## # FPGA info grup
|
||||
## set info_group_name "FPGA info"
|
||||
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
|
||||
## if { [string trim $info_group] eq "" } {
|
||||
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
|
||||
## -parent $page0 -display_name $info_group_name]
|
||||
## }
|
||||
##
|
||||
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
|
||||
## set_property -dict [list "widget" "comboBox" ] $p
|
||||
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
|
||||
## }
|
||||
## proc adi_if_define {name} {
|
||||
##
|
||||
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
|
||||
## ipx::create_bus_definition analog.com interface $name 1.0
|
||||
##
|
||||
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
|
||||
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
|
||||
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
|
||||
##
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## }
|
||||
## proc adi_if_ports {dir width name {type none}} {
|
||||
##
|
||||
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
|
||||
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
|
||||
## set_property master_presence required $m_intf
|
||||
## set_property slave_presence required $m_intf
|
||||
## set_property master_width $width $m_intf
|
||||
## set_property slave_width $width $m_intf
|
||||
##
|
||||
## set m_dir "in"
|
||||
## set s_dir "out"
|
||||
## if {$dir eq "output"} {
|
||||
## set m_dir "out"
|
||||
## set s_dir "in"
|
||||
## }
|
||||
##
|
||||
## set_property master_direction $m_dir $m_intf
|
||||
## set_property slave_direction $s_dir $m_intf
|
||||
##
|
||||
## if {$type ne "none"} {
|
||||
## set_property is_${type} true $m_intf
|
||||
## }
|
||||
##
|
||||
## ipx::save_bus_definition [ipx::current_busdef]
|
||||
## ipx::save_abstraction_definition [ipx::current_busabs]
|
||||
## }
|
||||
## proc adi_if_infer_bus {if_name mode name maps} {
|
||||
##
|
||||
## ipx::add_bus_interface $name [ipx::current_core]
|
||||
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
|
||||
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
|
||||
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
|
||||
## set_property interface_mode $mode $m_bus_if
|
||||
##
|
||||
## foreach map $maps {
|
||||
## set m_maps [regexp -all -inline {\S+} $map]
|
||||
## lassign $m_maps p_name p_map
|
||||
## ipx::add_port_map $p_name $m_bus_if
|
||||
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
|
||||
## }
|
||||
## }
|
||||
# adi_ip_create axi_dacfifo
|
||||
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
|
||||
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1343} -new_severity WARNING
|
||||
## set_msg_config -id {BD 41-1306} -new_severity WARNING
|
||||
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
|
||||
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
|
||||
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
|
||||
## set_msg_config -id {Synth 8-3331} -new_severity INFO
|
||||
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
|
||||
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
|
||||
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
|
||||
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'.)
|
||||
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
|
||||
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
|
||||
# adi_ip_files axi_dacfifo [list \
|
||||
# "$ad_hdl_dir/library/common/ad_g2b.v" \
|
||||
# "$ad_hdl_dir/library/common/ad_b2g.v" \
|
||||
# "$ad_hdl_dir/library/common/ad_mem_asym.v" \
|
||||
# "$ad_hdl_dir/library/common/ad_mem.v" \
|
||||
# "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
|
||||
# "$ad_hdl_dir/library/util_dacfifo/util_dacfifo_bypass.v" \
|
||||
# "axi_dacfifo_constr.xdc" \
|
||||
# "axi_dacfifo_wr.v" \
|
||||
# "axi_dacfifo_rd.v" \
|
||||
# "axi_dacfifo_address_buffer.v" \
|
||||
# "axi_dacfifo.v"]
|
||||
# adi_ip_properties_lite axi_dacfifo
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_axis_inf_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_b2g.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_g2b.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo/util_dacfifo_bypass.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_axis_inf_rx.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_b2g.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_g2b.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_dacfifo/util_dacfifo_bypass.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_dacfifo'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
||||
WARNING: [IP_Flow 19-5150] The Range '(DAC_DATA_WIDTH - 1):0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dac' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5150] The Range '(AXI_DATA_WIDTH - 1):0' is present in all ports of the interface 'axi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
||||
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
||||
WARNING: [IP_Flow 19-5150] The Range '(AXI_DATA_WIDTH - 1):0' is present in all ports of the interface 'axi'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5150] The Range '(DAC_DATA_WIDTH - 1):0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
WARNING: [IP_Flow 19-5150] The Range '(DMA_DATA_WIDTH - 1):0' is present in all ports of the interface 'dma'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'axi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'axi_resetn'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dac_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_rst'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dma_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_rst'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data' and definition port 'DATA'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dma_xfer_req' and definition port 'XFER_REQ'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'dma': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'axi_wdata' and definition port 'wdata'.
|
||||
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'axi_rdata' and definition port 'rdata'.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-1965] Bus Interface 'axi': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'axi_clk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'dac_clk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
WARNING: [IP_Flow 19-3153] Bus Interface 'dma_clk': ASSOCIATED_BUSIF bus parameter is missing.
|
||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
||||
# ipx::infer_bus_interface {\
|
||||
# axi_awvalid \
|
||||
# axi_awid \
|
||||
# axi_awburst \
|
||||
# axi_awlock \
|
||||
# axi_awcache \
|
||||
# axi_awprot \
|
||||
# axi_awqos \
|
||||
# axi_awlen \
|
||||
# axi_awsize \
|
||||
# axi_awaddr \
|
||||
# axi_awready \
|
||||
# axi_wvalid \
|
||||
# axi_wdata \
|
||||
# axi_wstrb \
|
||||
# axi_wlast \
|
||||
# axi_wready \
|
||||
# axi_bvalid \
|
||||
# axi_bid \
|
||||
# axi_bresp \
|
||||
# axi_bready \
|
||||
# axi_arvalid \
|
||||
# axi_arid \
|
||||
# axi_arburst \
|
||||
# axi_arlock \
|
||||
# axi_arcache \
|
||||
# axi_arprot \
|
||||
# axi_arqos \
|
||||
# axi_arlen \
|
||||
# axi_arsize \
|
||||
# axi_araddr \
|
||||
# axi_arready \
|
||||
# axi_rvalid \
|
||||
# axi_rid \
|
||||
# axi_rresp \
|
||||
# axi_rlast \
|
||||
# axi_rdata \
|
||||
# axi_rready} \
|
||||
# xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument).
|
||||
# ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'axi'.
|
||||
# ipx::infer_bus_interface axi_resetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axi_resetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'axi_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'axi_resetn'.
|
||||
# ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \
|
||||
# -of_objects [ipx::current_core]]
|
||||
# set_property value axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
|
||||
# -of_objects [ipx::get_bus_interfaces axi_clk \
|
||||
# -of_objects [ipx::current_core]]]
|
||||
# ipx::add_address_space axi [ipx::current_core]
|
||||
# set_property master_address_space_ref axi [ipx::get_bus_interfaces axi \
|
||||
# -of_objects [ipx::current_core]]
|
||||
# set_property range 4294967296 [ipx::get_address_spaces axi \
|
||||
# -of_objects [ipx::current_core]]
|
||||
# set_property width 512 [ipx::get_address_spaces axi \
|
||||
# -of_objects [ipx::current_core]]
|
||||
# ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
# ipx::infer_bus_interface dma_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dma_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dma_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dma_rst'.
|
||||
# ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
||||
# ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_rst' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
||||
INFO: [IP_Flow 19-4728] Bus Interface 'dac_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dac_rst'.
|
||||
# ipx::save_core [ipx::current_core]
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 15:20:20 2021...
|
||||
@@ -0,0 +1,115 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "AXI_ADDRESS" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "AXI_ADDRESS_LIMIT" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "AXI_DATA_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "AXI_LENGTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "AXI_SIZE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DATA_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DMA_DATA_WIDTH" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.AXI_ADDRESS { PARAM_VALUE.AXI_ADDRESS } {
|
||||
# Procedure called to update AXI_ADDRESS when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.AXI_ADDRESS { PARAM_VALUE.AXI_ADDRESS } {
|
||||
# Procedure called to validate AXI_ADDRESS
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.AXI_ADDRESS_LIMIT { PARAM_VALUE.AXI_ADDRESS_LIMIT } {
|
||||
# Procedure called to update AXI_ADDRESS_LIMIT when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.AXI_ADDRESS_LIMIT { PARAM_VALUE.AXI_ADDRESS_LIMIT } {
|
||||
# Procedure called to validate AXI_ADDRESS_LIMIT
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH } {
|
||||
# Procedure called to update AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH } {
|
||||
# Procedure called to validate AXI_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.AXI_LENGTH { PARAM_VALUE.AXI_LENGTH } {
|
||||
# Procedure called to update AXI_LENGTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.AXI_LENGTH { PARAM_VALUE.AXI_LENGTH } {
|
||||
# Procedure called to validate AXI_LENGTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.AXI_SIZE { PARAM_VALUE.AXI_SIZE } {
|
||||
# Procedure called to update AXI_SIZE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.AXI_SIZE { PARAM_VALUE.AXI_SIZE } {
|
||||
# Procedure called to validate AXI_SIZE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DATA_WIDTH { PARAM_VALUE.DAC_DATA_WIDTH } {
|
||||
# Procedure called to update DAC_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DATA_WIDTH { PARAM_VALUE.DAC_DATA_WIDTH } {
|
||||
# Procedure called to validate DAC_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DMA_DATA_WIDTH { PARAM_VALUE.DMA_DATA_WIDTH } {
|
||||
# Procedure called to update DMA_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DMA_DATA_WIDTH { PARAM_VALUE.DMA_DATA_WIDTH } {
|
||||
# Procedure called to validate DMA_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DATA_WIDTH { MODELPARAM_VALUE.DAC_DATA_WIDTH PARAM_VALUE.DAC_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DATA_WIDTH}] ${MODELPARAM_VALUE.DAC_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DMA_DATA_WIDTH { MODELPARAM_VALUE.DMA_DATA_WIDTH PARAM_VALUE.DMA_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DMA_DATA_WIDTH}] ${MODELPARAM_VALUE.DMA_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.AXI_DATA_WIDTH { MODELPARAM_VALUE.AXI_DATA_WIDTH PARAM_VALUE.AXI_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.AXI_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.AXI_SIZE { MODELPARAM_VALUE.AXI_SIZE PARAM_VALUE.AXI_SIZE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.AXI_SIZE}] ${MODELPARAM_VALUE.AXI_SIZE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.AXI_LENGTH { MODELPARAM_VALUE.AXI_LENGTH PARAM_VALUE.AXI_LENGTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.AXI_LENGTH}] ${MODELPARAM_VALUE.AXI_LENGTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.AXI_ADDRESS { MODELPARAM_VALUE.AXI_ADDRESS PARAM_VALUE.AXI_ADDRESS } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.AXI_ADDRESS}] ${MODELPARAM_VALUE.AXI_ADDRESS}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.AXI_ADDRESS_LIMIT { MODELPARAM_VALUE.AXI_ADDRESS_LIMIT PARAM_VALUE.AXI_ADDRESS_LIMIT } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.AXI_ADDRESS_LIMIT}] ${MODELPARAM_VALUE.AXI_ADDRESS_LIMIT}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user