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josh
2023-03-18 15:35:53 +08:00
commit 5965eba577
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common/ApproxAbs.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/11/15 20:02:47
// Design Name:
// Module Name: ApproxAbs
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ApproxAbs(
input clk,
input Nd,
input [27:0] Dini,
input [27:0] Dinq,
output reg Abs_Rdy = 1'b0,
output reg [28:0] Abs_Dout= 29'd0
);
// 第一级延迟：把输入变负值：
//===============================================================
reg [27:0] Din_I_neg;
always @(posedge clk)begin
if(Dini==28'b1000_0000_0000_0000_0000_0000_0000)begin
Din_I_neg <= 28'b0111_1111_1111_1111_1111_1111_1111;
end else begin
Din_I_neg <= -Dini;
end
end
reg [27:0] Din_Q_neg;
always @(posedge clk)begin
if(Dinq==28'b1000_0000_0000_0000_0000_0000_0000)begin
Din_Q_neg <= 28'b0111_1111_1111_1111_1111_1111_1111;
end else begin
Din_Q_neg <= -Dinq;
end
end
// 第二级延迟：求绝对值：
//===============================================================
reg [27:0] Din_I_D1;
reg [27:0] Din_Q_D1;
always @(posedge clk)begin
Din_I_D1 <= Dini;
Din_Q_D1 <= Dinq;
end
reg [27:0] Abs_Din_I;
reg [27:0] Abs_Din_Q;
always @(posedge clk)begin
if(Din_I_D1[27]==1'b1)
Abs_Din_I <= Din_I_neg;
else
Abs_Din_I <= Din_I_D1;
if(Din_Q_D1[27]==1'b1)
Abs_Din_Q <= Din_Q_neg;
else
Abs_Din_Q <= Din_Q_D1;
end
// 第三级延迟：确定I/Q两路绝对值的大小关系：
//===============================================================
reg [27:0] AbsIQ_max;
reg [27:0] AbsIQ_min;
always @(posedge clk)begin
if (Abs_Din_I>=Abs_Din_Q) begin
AbsIQ_max <= Abs_Din_I;
AbsIQ_min <= Abs_Din_Q;
end else begin
AbsIQ_max <= Abs_Din_Q;
AbsIQ_min <= Abs_Din_I;
end
end
// 第四级延迟：MXQ选择的系数：7/8和1/2：
//===============================================================
reg [27:0] AbsIQ_max_7by8;
reg [27:0] AbsIQ_min_1by2;
always @ (posedge clk) begin
AbsIQ_max_7by8[27:0] <= AbsIQ_max[27:0]-{3'b000,AbsIQ_max[27:3]};
AbsIQ_min_1by2[27:0] <= {AbsIQ_min[27],AbsIQ_min[27:1]};
end
// 第五级延迟：1bit位扩展求和：
// (MXQ)中间将最大延迟一个clk赋给 Dout_Temp2,使 Dout_Temp2与 Dout_Temp在同一个clk下进行比较。
//===============================================================
reg [28:0] Dout_Temp;
reg [28:0] Dout_Temp1;
reg [28:0] Dout_Temp2;
always @(posedge clk) begin
Dout_Temp <= {1'b0,AbsIQ_max_7by8[27:0]}+{1'b0,AbsIQ_min_1by2[27:0]};
Dout_Temp1 <= {1'b0,AbsIQ_max[27:0]};
Dout_Temp2 <= Dout_Temp1[28:0];
end
// (MXQ)第六级延迟：输出求和值与I/Q两路绝对值最大值比较之后的最大值：
reg [28:0] Dout;
always @(posedge clk) begin
if(Dout_Temp[28:0]>=Dout_Temp2[27:0])
Dout[28:0] <= Dout_Temp[28:0];
else
Dout[28:0] <= Dout_Temp2[28:0];
end
// 产生Dout_valid，与Din_valid有七级延迟：
reg Dout_valid_b6;
reg Dout_valid_b5;
reg Dout_valid_b4;
reg Dout_valid_b3;
reg Dout_valid_b2;
reg Dout_valid_b1;
always@(posedge clk) begin //(MXQ)必须加 posedge clk ,否则仿真有问题，内存溢出
Dout_valid_b6 <= Nd;
Dout_valid_b5 <= Dout_valid_b6;
Dout_valid_b4 <= Dout_valid_b5;
Dout_valid_b3 <= Dout_valid_b4;
Dout_valid_b2 <= Dout_valid_b3;
Dout_valid_b1 <= Dout_valid_b2;
Abs_Rdy <= Dout_valid_b1;
end
always @ (posedge clk) begin
if(Dout_valid_b1)
Abs_Dout <= Dout;
else
Abs_Dout <= 29'd0;
end
endmodule
common/ApproxModuli_26bit.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2020/12/16 14:26:28
// Design Name:
// Module Name: ApproxModuli_26bit
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ApproxModuli_26bit(
input clk,
input din_valid,
input [25:0] din_I,
input [25:0] din_Q,
output reg dout_valid = 0,
output reg [25:0] dout = 0
);
reg [25:0] din_I_D1 = 0, din_Q_D1 = 0, din_I_D2 = 0, din_Q_D2 = 0;
reg [25:0] Sub1_s = 0;
reg [25:0] Xmax = 0, Xmin = 0;
always @(posedge clk)
begin
if(din_valid)
din_I_D1[25:0] <= (din_I[25]==1'b0)? din_I[25:0]:-din_I[25:0];
else
din_I_D1[25:0] <= 26'd0;
din_I_D2[25:0] <= din_I_D1[25:0];
if(din_valid)
din_Q_D1[25:0] <= (din_Q[25]==1'b0)? din_Q[25:0]:-din_Q[25:0];
else
din_Q_D1[25:0] <= 26'd0;
din_Q_D2[25:0] <= din_Q_D1[25:0];
Sub1_s[25:0] <= din_I_D1[25:0] - din_Q_D1[25:0];
if(Sub1_s[25])
Xmax[25:0] <= din_Q_D2[25:0];
else
Xmax[25:0] <= din_I_D2[25:0];
if(Sub1_s[25])
Xmin[25:0] <= din_I_D2[25:0];
else
Xmin[25:0] <= din_Q_D2[25:0];
end
reg [25:0] Xmax_D1 = 0, Xmax_31by32 = 0, Xmax_13by16 = 0;
reg [25:0] Xmin_9by32 = 0, Xmin_19by32 = 0;
always @(posedge clk)
begin
Xmax_D1[25:0] <= Xmax[25:0];
Xmax_31by32[25:0] <= Xmax[25:0] - {5'd0, Xmax[25:5]};
Xmax_13by16[25:0] <= Xmax[25:0] - {3'd0, Xmax[25:3]} - {4'd0, Xmax[25:4]};
Xmin_9by32[25:0] <= {2'd0, Xmin[25:2]} + {5'd0, Xmin[25:5]};
Xmin_19by32[25:0] <= {1'd0, Xmin[25:1]} + {4'd0, Xmin[25:4]} + {5'd0, Xmin[25:5]};
end
reg [25:0] t1 = 0, t2 = 0, t3 = 0;
always @(posedge clk)
begin
t1[25:0] <= Xmax_D1[25:0];
t2[25:0] <= Xmax_31by32[25:0] + Xmin_9by32[25:0];
t3[25:0] <= Xmax_13by16[25:0] + Xmin_19by32[25:0];
end
reg [25:0] sub2_s = 0;
reg [25:0] sub3_a = 0, sub3_b = 0, sub3_s = 0;
reg [25:0] sub3_a_D1 = 0, sub3_b_D1 = 0;
reg [25:0] t1_D1 = 0, t2_D1 = 0, t3_D1 = 0;
always @(posedge clk)
begin
t1_D1[25:0] <= t1[25:0];
t2_D1[25:0] <= t2[25:0];
t3_D1[25:0] <= t3[25:0];
sub2_s[25:0] <= t1[25:0] - t2[25:0];
if(sub2_s[25])
sub3_a[25:0] <= t2_D1[25:0];
else
sub3_a[25:0] <= t1_D1[25:0];
sub3_b[25:0] <= t3_D1[25:0];
sub3_a_D1[25:0] <= sub3_a[25:0];
sub3_b_D1[25:0] <= sub3_b[25:0];
sub3_s[25:0] <= sub3_a[25:0] - sub3_b[25:0];
if(sub3_s[25])
dout[25:0] <= sub3_b_D1[25:0];
else
dout[25:0] <= sub3_a_D1[25:0];
end
reg din_valid_D1 = 0, din_valid_D2 = 0, din_valid_D3 = 0, din_valid_D4 = 0;
reg din_valid_D5 = 0, din_valid_D6 = 0, din_valid_D7 = 0, din_valid_D8 = 0;
always @(posedge clk)
begin
din_valid_D1 <= din_valid;
din_valid_D2 <= din_valid_D1;
din_valid_D3 <= din_valid_D2;
din_valid_D4 <= din_valid_D3;
din_valid_D5 <= din_valid_D4;
din_valid_D6 <= din_valid_D5;
din_valid_D7 <= din_valid_D6;
din_valid_D8 <= din_valid_D7;
dout_valid <= din_valid_D8;
end
endmodule