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//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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//--------------------------------------------------------------------------------
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//Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
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//Date : Fri Mar 17 23:21:41 2023
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//Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
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//Command : generate_target system_bd.bd
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//Design : system_bd
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//Purpose : IP block netlist
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//--------------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
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module jesd204b_imp_1AG4O5J
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(core_clk,
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jesd_reset,
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m_axis_rx_tdata,
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m_axis_rx_tvalid,
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refclk_n,
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refclk_p,
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rx_rstn,
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rx_sync_n,
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rx_sync_p,
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rxn_in,
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rxp_in,
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s_axi_aclk,
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s_axi_aresetn,
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s_axi_phy_araddr,
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s_axi_phy_arready,
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s_axi_phy_arvalid,
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s_axi_phy_awaddr,
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s_axi_phy_awready,
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s_axi_phy_awvalid,
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s_axi_phy_bready,
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s_axi_phy_bresp,
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s_axi_phy_bvalid,
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s_axi_phy_rdata,
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s_axi_phy_rready,
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s_axi_phy_rresp,
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s_axi_phy_rvalid,
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s_axi_phy_wdata,
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s_axi_phy_wready,
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s_axi_phy_wvalid,
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s_axi_rx_araddr,
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s_axi_rx_arready,
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s_axi_rx_arvalid,
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s_axi_rx_awaddr,
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s_axi_rx_awready,
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s_axi_rx_awvalid,
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s_axi_rx_bready,
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s_axi_rx_bresp,
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s_axi_rx_bvalid,
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s_axi_rx_rdata,
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s_axi_rx_rready,
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s_axi_rx_rresp,
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s_axi_rx_rvalid,
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s_axi_rx_wdata,
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s_axi_rx_wready,
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s_axi_rx_wstrb,
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s_axi_rx_wvalid,
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s_axi_tx_araddr,
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s_axi_tx_arready,
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s_axi_tx_arvalid,
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s_axi_tx_awaddr,
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s_axi_tx_awready,
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s_axi_tx_awvalid,
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s_axi_tx_bready,
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s_axi_tx_bresp,
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s_axi_tx_bvalid,
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s_axi_tx_rdata,
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s_axi_tx_rready,
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s_axi_tx_rresp,
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s_axi_tx_rvalid,
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s_axi_tx_wdata,
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s_axi_tx_wready,
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s_axi_tx_wstrb,
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s_axi_tx_wvalid,
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s_axis_tx_tdata,
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s_axis_tx_tready,
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sysref_n,
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sysref_p,
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tx_rstn,
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tx_sync_n,
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tx_sync_p,
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txn_out,
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txp_out);
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input core_clk;
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input jesd_reset;
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output [63:0]m_axis_rx_tdata;
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output m_axis_rx_tvalid;
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input [0:0]refclk_n;
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input [0:0]refclk_p;
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output rx_rstn;
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output [0:0]rx_sync_n;
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output [0:0]rx_sync_p;
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input [1:0]rxn_in;
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input [1:0]rxp_in;
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input s_axi_aclk;
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input s_axi_aresetn;
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input [11:0]s_axi_phy_araddr;
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output s_axi_phy_arready;
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input s_axi_phy_arvalid;
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input [11:0]s_axi_phy_awaddr;
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output s_axi_phy_awready;
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input s_axi_phy_awvalid;
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input s_axi_phy_bready;
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output [1:0]s_axi_phy_bresp;
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output s_axi_phy_bvalid;
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output [31:0]s_axi_phy_rdata;
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input s_axi_phy_rready;
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output [1:0]s_axi_phy_rresp;
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output s_axi_phy_rvalid;
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input [31:0]s_axi_phy_wdata;
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output s_axi_phy_wready;
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input s_axi_phy_wvalid;
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input [11:0]s_axi_rx_araddr;
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output s_axi_rx_arready;
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input s_axi_rx_arvalid;
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input [11:0]s_axi_rx_awaddr;
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output s_axi_rx_awready;
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input s_axi_rx_awvalid;
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input s_axi_rx_bready;
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output [1:0]s_axi_rx_bresp;
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output s_axi_rx_bvalid;
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output [31:0]s_axi_rx_rdata;
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input s_axi_rx_rready;
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output [1:0]s_axi_rx_rresp;
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output s_axi_rx_rvalid;
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input [31:0]s_axi_rx_wdata;
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output s_axi_rx_wready;
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input [3:0]s_axi_rx_wstrb;
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input s_axi_rx_wvalid;
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input [11:0]s_axi_tx_araddr;
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output s_axi_tx_arready;
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input s_axi_tx_arvalid;
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input [11:0]s_axi_tx_awaddr;
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output s_axi_tx_awready;
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input s_axi_tx_awvalid;
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input s_axi_tx_bready;
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output [1:0]s_axi_tx_bresp;
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output s_axi_tx_bvalid;
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output [31:0]s_axi_tx_rdata;
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input s_axi_tx_rready;
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output [1:0]s_axi_tx_rresp;
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output s_axi_tx_rvalid;
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input [31:0]s_axi_tx_wdata;
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output s_axi_tx_wready;
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input [3:0]s_axi_tx_wstrb;
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input s_axi_tx_wvalid;
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input [63:0]s_axis_tx_tdata;
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output s_axis_tx_tready;
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input [0:0]sysref_n;
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input [0:0]sysref_p;
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output tx_rstn;
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input [0:0]tx_sync_n;
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input [0:0]tx_sync_p;
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output [1:0]txn_out;
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output [1:0]txp_out;
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wire [11:0]Conn1_ARADDR;
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wire Conn1_ARREADY;
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wire Conn1_ARVALID;
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wire [11:0]Conn1_AWADDR;
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wire Conn1_AWREADY;
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wire Conn1_AWVALID;
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wire Conn1_BREADY;
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wire [1:0]Conn1_BRESP;
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wire Conn1_BVALID;
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wire [31:0]Conn1_RDATA;
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wire Conn1_RREADY;
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wire [1:0]Conn1_RRESP;
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wire Conn1_RVALID;
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wire [31:0]Conn1_WDATA;
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wire Conn1_WREADY;
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wire [3:0]Conn1_WSTRB;
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wire Conn1_WVALID;
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wire [11:0]Conn2_ARADDR;
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wire Conn2_ARREADY;
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wire Conn2_ARVALID;
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wire [11:0]Conn2_AWADDR;
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wire Conn2_AWREADY;
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wire Conn2_AWVALID;
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wire Conn2_BREADY;
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wire [1:0]Conn2_BRESP;
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wire Conn2_BVALID;
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wire [31:0]Conn2_RDATA;
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wire Conn2_RREADY;
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wire [1:0]Conn2_RRESP;
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wire Conn2_RVALID;
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wire [31:0]Conn2_WDATA;
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wire Conn2_WREADY;
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wire Conn2_WVALID;
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wire [11:0]Conn3_ARADDR;
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wire Conn3_ARREADY;
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wire Conn3_ARVALID;
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wire [11:0]Conn3_AWADDR;
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wire Conn3_AWREADY;
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wire Conn3_AWVALID;
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wire Conn3_BREADY;
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wire [1:0]Conn3_BRESP;
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wire Conn3_BVALID;
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wire [31:0]Conn3_RDATA;
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wire Conn3_RREADY;
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wire [1:0]Conn3_RRESP;
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wire Conn3_RVALID;
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wire [31:0]Conn3_WDATA;
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wire Conn3_WREADY;
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wire [3:0]Conn3_WSTRB;
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wire Conn3_WVALID;
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wire [63:0]Conn4_TDATA;
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wire Conn4_TREADY;
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wire [63:0]Conn5_TDATA;
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wire Conn5_TVALID;
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wire [0:0]IBUF_DS_N_0_1;
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wire [0:0]IBUF_DS_N_1_1;
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wire [0:0]IBUF_DS_N_2_1;
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wire [0:0]IBUF_DS_P_0_1;
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wire [0:0]IBUF_DS_P_1_1;
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wire [0:0]IBUF_DS_P_2_1;
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wire [0:0]ibufds_refclk_IBUF_OUT;
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wire [3:0]jesd204_phy_gt0_rx_rxcharisk;
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wire [31:0]jesd204_phy_gt0_rx_rxdata;
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wire [3:0]jesd204_phy_gt0_rx_rxdisperr;
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wire [3:0]jesd204_phy_gt0_rx_rxnotintable;
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wire [3:0]jesd204_phy_gt1_rx_rxcharisk;
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wire [31:0]jesd204_phy_gt1_rx_rxdata;
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wire [3:0]jesd204_phy_gt1_rx_rxdisperr;
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wire [3:0]jesd204_phy_gt1_rx_rxnotintable;
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wire jesd204_phy_rx_reset_done;
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wire jesd204_phy_tx_reset_done;
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wire [1:0]jesd204_phy_txn_out;
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wire [1:0]jesd204_phy_txp_out;
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wire jesd204_rx_rx_aresetn;
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wire jesd204_rx_rx_reset_gt;
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wire jesd204_rx_rxencommaalign_out;
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wire [3:0]jesd204_tx_gt0_tx_txcharisk;
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wire [31:0]jesd204_tx_gt0_tx_txdata;
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wire [3:0]jesd204_tx_gt1_tx_txcharisk;
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wire [31:0]jesd204_tx_gt1_tx_txdata;
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wire [2:0]jesd204_tx_gt_prbssel_out;
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wire jesd204_tx_tx_aresetn;
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wire jesd204_tx_tx_reset_gt;
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wire [0:0]obufds_rx_sync_OBUF_DS_N;
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wire [0:0]obufds_rx_sync_OBUF_DS_P;
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wire rx_sync;
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wire [1:0]rxn_in_0_1;
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wire [1:0]rxp_in_0_1;
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wire s_axi_aclk_0_1;
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wire s_axi_aresetn_0_1;
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wire sys_clk_0_1;
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wire [0:0]sysref;
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wire tx_reset_0_1;
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wire [0:0]tx_sync;
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assign Conn1_ARADDR = s_axi_tx_araddr[11:0];
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assign Conn1_ARVALID = s_axi_tx_arvalid;
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assign Conn1_AWADDR = s_axi_tx_awaddr[11:0];
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assign Conn1_AWVALID = s_axi_tx_awvalid;
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assign Conn1_BREADY = s_axi_tx_bready;
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assign Conn1_RREADY = s_axi_tx_rready;
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assign Conn1_WDATA = s_axi_tx_wdata[31:0];
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assign Conn1_WSTRB = s_axi_tx_wstrb[3:0];
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assign Conn1_WVALID = s_axi_tx_wvalid;
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assign Conn2_ARADDR = s_axi_phy_araddr[11:0];
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assign Conn2_ARVALID = s_axi_phy_arvalid;
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assign Conn2_AWADDR = s_axi_phy_awaddr[11:0];
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assign Conn2_AWVALID = s_axi_phy_awvalid;
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assign Conn2_BREADY = s_axi_phy_bready;
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assign Conn2_RREADY = s_axi_phy_rready;
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assign Conn2_WDATA = s_axi_phy_wdata[31:0];
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assign Conn2_WVALID = s_axi_phy_wvalid;
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assign Conn3_ARADDR = s_axi_rx_araddr[11:0];
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assign Conn3_ARVALID = s_axi_rx_arvalid;
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assign Conn3_AWADDR = s_axi_rx_awaddr[11:0];
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assign Conn3_AWVALID = s_axi_rx_awvalid;
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assign Conn3_BREADY = s_axi_rx_bready;
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assign Conn3_RREADY = s_axi_rx_rready;
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assign Conn3_WDATA = s_axi_rx_wdata[31:0];
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assign Conn3_WSTRB = s_axi_rx_wstrb[3:0];
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assign Conn3_WVALID = s_axi_rx_wvalid;
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assign Conn4_TDATA = s_axis_tx_tdata[63:0];
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assign IBUF_DS_N_0_1 = refclk_n[0];
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assign IBUF_DS_N_1_1 = sysref_n[0];
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assign IBUF_DS_N_2_1 = tx_sync_n[0];
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assign IBUF_DS_P_0_1 = refclk_p[0];
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assign IBUF_DS_P_1_1 = sysref_p[0];
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assign IBUF_DS_P_2_1 = tx_sync_p[0];
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assign m_axis_rx_tdata[63:0] = Conn5_TDATA;
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assign m_axis_rx_tvalid = Conn5_TVALID;
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assign rx_rstn = jesd204_rx_rx_aresetn;
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assign rx_sync_n[0] = obufds_rx_sync_OBUF_DS_N;
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assign rx_sync_p[0] = obufds_rx_sync_OBUF_DS_P;
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assign rxn_in_0_1 = rxn_in[1:0];
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assign rxp_in_0_1 = rxp_in[1:0];
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assign s_axi_aclk_0_1 = s_axi_aclk;
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assign s_axi_aresetn_0_1 = s_axi_aresetn;
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assign s_axi_phy_arready = Conn2_ARREADY;
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assign s_axi_phy_awready = Conn2_AWREADY;
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assign s_axi_phy_bresp[1:0] = Conn2_BRESP;
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assign s_axi_phy_bvalid = Conn2_BVALID;
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assign s_axi_phy_rdata[31:0] = Conn2_RDATA;
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assign s_axi_phy_rresp[1:0] = Conn2_RRESP;
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assign s_axi_phy_rvalid = Conn2_RVALID;
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assign s_axi_phy_wready = Conn2_WREADY;
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assign s_axi_rx_arready = Conn3_ARREADY;
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assign s_axi_rx_awready = Conn3_AWREADY;
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assign s_axi_rx_bresp[1:0] = Conn3_BRESP;
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assign s_axi_rx_bvalid = Conn3_BVALID;
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assign s_axi_rx_rdata[31:0] = Conn3_RDATA;
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assign s_axi_rx_rresp[1:0] = Conn3_RRESP;
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assign s_axi_rx_rvalid = Conn3_RVALID;
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assign s_axi_rx_wready = Conn3_WREADY;
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assign s_axi_tx_arready = Conn1_ARREADY;
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assign s_axi_tx_awready = Conn1_AWREADY;
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assign s_axi_tx_bresp[1:0] = Conn1_BRESP;
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assign s_axi_tx_bvalid = Conn1_BVALID;
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assign s_axi_tx_rdata[31:0] = Conn1_RDATA;
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assign s_axi_tx_rresp[1:0] = Conn1_RRESP;
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assign s_axi_tx_rvalid = Conn1_RVALID;
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assign s_axi_tx_wready = Conn1_WREADY;
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assign s_axis_tx_tready = Conn4_TREADY;
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assign sys_clk_0_1 = core_clk;
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assign tx_reset_0_1 = jesd_reset;
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assign tx_rstn = jesd204_tx_tx_aresetn;
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assign txn_out[1:0] = jesd204_phy_txn_out;
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assign txp_out[1:0] = jesd204_phy_txp_out;
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system_bd_ibufds_refclk_0 ibufds_refclk
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(.IBUF_DS_N(IBUF_DS_N_0_1),
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.IBUF_DS_P(IBUF_DS_P_0_1),
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.IBUF_OUT(ibufds_refclk_IBUF_OUT));
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system_bd_ibufds_sysref_0 ibufds_sysref
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(.IBUF_DS_N(IBUF_DS_N_1_1),
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.IBUF_DS_P(IBUF_DS_P_1_1),
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.IBUF_OUT(sysref));
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system_bd_ibufds_tx_sync_0 ibufds_tx_sync
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(.IBUF_DS_N(IBUF_DS_N_2_1),
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.IBUF_DS_P(IBUF_DS_P_2_1),
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.IBUF_OUT(tx_sync));
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system_bd_jesd204_phy_0 jesd204_phy
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(.cpll_refclk(ibufds_refclk_IBUF_OUT),
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.drpclk(s_axi_aclk_0_1),
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.gt0_rxcharisk(jesd204_phy_gt0_rx_rxcharisk),
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.gt0_rxdata(jesd204_phy_gt0_rx_rxdata),
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.gt0_rxdisperr(jesd204_phy_gt0_rx_rxdisperr),
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.gt0_rxnotintable(jesd204_phy_gt0_rx_rxnotintable),
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.gt0_txcharisk(jesd204_tx_gt0_tx_txcharisk),
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.gt0_txdata(jesd204_tx_gt0_tx_txdata),
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.gt1_rxcharisk(jesd204_phy_gt1_rx_rxcharisk),
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.gt1_rxdata(jesd204_phy_gt1_rx_rxdata),
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.gt1_rxdisperr(jesd204_phy_gt1_rx_rxdisperr),
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.gt1_rxnotintable(jesd204_phy_gt1_rx_rxnotintable),
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.gt1_txcharisk(jesd204_tx_gt1_tx_txcharisk),
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.gt1_txdata(jesd204_tx_gt1_tx_txdata),
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.gt_prbssel(jesd204_tx_gt_prbssel_out),
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.rx_core_clk(sys_clk_0_1),
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.rx_reset_done(jesd204_phy_rx_reset_done),
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.rx_reset_gt(jesd204_rx_rx_reset_gt),
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.rx_sys_reset(tx_reset_0_1),
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.rxencommaalign(jesd204_rx_rxencommaalign_out),
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.rxn_in(rxn_in_0_1),
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.rxp_in(rxp_in_0_1),
|
||||
.s_axi_aclk(s_axi_aclk_0_1),
|
||||
.s_axi_araddr(Conn2_ARADDR),
|
||||
.s_axi_aresetn(s_axi_aresetn_0_1),
|
||||
.s_axi_arready(Conn2_ARREADY),
|
||||
.s_axi_arvalid(Conn2_ARVALID),
|
||||
.s_axi_awaddr(Conn2_AWADDR),
|
||||
.s_axi_awready(Conn2_AWREADY),
|
||||
.s_axi_awvalid(Conn2_AWVALID),
|
||||
.s_axi_bready(Conn2_BREADY),
|
||||
.s_axi_bresp(Conn2_BRESP),
|
||||
.s_axi_bvalid(Conn2_BVALID),
|
||||
.s_axi_rdata(Conn2_RDATA),
|
||||
.s_axi_rready(Conn2_RREADY),
|
||||
.s_axi_rresp(Conn2_RRESP),
|
||||
.s_axi_rvalid(Conn2_RVALID),
|
||||
.s_axi_wdata(Conn2_WDATA),
|
||||
.s_axi_wready(Conn2_WREADY),
|
||||
.s_axi_wvalid(Conn2_WVALID),
|
||||
.tx_core_clk(sys_clk_0_1),
|
||||
.tx_reset_done(jesd204_phy_tx_reset_done),
|
||||
.tx_reset_gt(jesd204_tx_tx_reset_gt),
|
||||
.tx_sys_reset(tx_reset_0_1),
|
||||
.txn_out(jesd204_phy_txn_out),
|
||||
.txp_out(jesd204_phy_txp_out));
|
||||
system_bd_jesd204_rx_0 jesd204_rx
|
||||
(.gt0_rxcharisk(jesd204_phy_gt0_rx_rxcharisk),
|
||||
.gt0_rxdata(jesd204_phy_gt0_rx_rxdata),
|
||||
.gt0_rxdisperr(jesd204_phy_gt0_rx_rxdisperr),
|
||||
.gt0_rxnotintable(jesd204_phy_gt0_rx_rxnotintable),
|
||||
.gt1_rxcharisk(jesd204_phy_gt1_rx_rxcharisk),
|
||||
.gt1_rxdata(jesd204_phy_gt1_rx_rxdata),
|
||||
.gt1_rxdisperr(jesd204_phy_gt1_rx_rxdisperr),
|
||||
.gt1_rxnotintable(jesd204_phy_gt1_rx_rxnotintable),
|
||||
.rx_aresetn(jesd204_rx_rx_aresetn),
|
||||
.rx_core_clk(sys_clk_0_1),
|
||||
.rx_reset(tx_reset_0_1),
|
||||
.rx_reset_done(jesd204_phy_rx_reset_done),
|
||||
.rx_reset_gt(jesd204_rx_rx_reset_gt),
|
||||
.rx_sync(rx_sync),
|
||||
.rx_sysref(sysref),
|
||||
.rx_tdata(Conn5_TDATA),
|
||||
.rx_tvalid(Conn5_TVALID),
|
||||
.rxencommaalign_out(jesd204_rx_rxencommaalign_out),
|
||||
.s_axi_aclk(s_axi_aclk_0_1),
|
||||
.s_axi_araddr(Conn3_ARADDR),
|
||||
.s_axi_aresetn(s_axi_aresetn_0_1),
|
||||
.s_axi_arready(Conn3_ARREADY),
|
||||
.s_axi_arvalid(Conn3_ARVALID),
|
||||
.s_axi_awaddr(Conn3_AWADDR),
|
||||
.s_axi_awready(Conn3_AWREADY),
|
||||
.s_axi_awvalid(Conn3_AWVALID),
|
||||
.s_axi_bready(Conn3_BREADY),
|
||||
.s_axi_bresp(Conn3_BRESP),
|
||||
.s_axi_bvalid(Conn3_BVALID),
|
||||
.s_axi_rdata(Conn3_RDATA),
|
||||
.s_axi_rready(Conn3_RREADY),
|
||||
.s_axi_rresp(Conn3_RRESP),
|
||||
.s_axi_rvalid(Conn3_RVALID),
|
||||
.s_axi_wdata(Conn3_WDATA),
|
||||
.s_axi_wready(Conn3_WREADY),
|
||||
.s_axi_wstrb(Conn3_WSTRB),
|
||||
.s_axi_wvalid(Conn3_WVALID));
|
||||
system_bd_jesd204_tx_0 jesd204_tx
|
||||
(.gt0_txcharisk(jesd204_tx_gt0_tx_txcharisk),
|
||||
.gt0_txdata(jesd204_tx_gt0_tx_txdata),
|
||||
.gt1_txcharisk(jesd204_tx_gt1_tx_txcharisk),
|
||||
.gt1_txdata(jesd204_tx_gt1_tx_txdata),
|
||||
.gt_prbssel_out(jesd204_tx_gt_prbssel_out),
|
||||
.s_axi_aclk(s_axi_aclk_0_1),
|
||||
.s_axi_araddr(Conn1_ARADDR),
|
||||
.s_axi_aresetn(s_axi_aresetn_0_1),
|
||||
.s_axi_arready(Conn1_ARREADY),
|
||||
.s_axi_arvalid(Conn1_ARVALID),
|
||||
.s_axi_awaddr(Conn1_AWADDR),
|
||||
.s_axi_awready(Conn1_AWREADY),
|
||||
.s_axi_awvalid(Conn1_AWVALID),
|
||||
.s_axi_bready(Conn1_BREADY),
|
||||
.s_axi_bresp(Conn1_BRESP),
|
||||
.s_axi_bvalid(Conn1_BVALID),
|
||||
.s_axi_rdata(Conn1_RDATA),
|
||||
.s_axi_rready(Conn1_RREADY),
|
||||
.s_axi_rresp(Conn1_RRESP),
|
||||
.s_axi_rvalid(Conn1_RVALID),
|
||||
.s_axi_wdata(Conn1_WDATA),
|
||||
.s_axi_wready(Conn1_WREADY),
|
||||
.s_axi_wstrb(Conn1_WSTRB),
|
||||
.s_axi_wvalid(Conn1_WVALID),
|
||||
.tx_aresetn(jesd204_tx_tx_aresetn),
|
||||
.tx_core_clk(sys_clk_0_1),
|
||||
.tx_reset(tx_reset_0_1),
|
||||
.tx_reset_done(jesd204_phy_tx_reset_done),
|
||||
.tx_reset_gt(jesd204_tx_tx_reset_gt),
|
||||
.tx_sync(tx_sync),
|
||||
.tx_sysref(sysref),
|
||||
.tx_tdata(Conn4_TDATA),
|
||||
.tx_tready(Conn4_TREADY));
|
||||
system_bd_obufds_rx_sync_0 obufds_rx_sync
|
||||
(.OBUF_DS_N(obufds_rx_sync_OBUF_DS_N),
|
||||
.OBUF_DS_P(obufds_rx_sync_OBUF_DS_P),
|
||||
.OBUF_IN(rx_sync));
|
||||
endmodule
|
||||
|
||||
(* CORE_GENERATION_INFO = "system_bd,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system_bd,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=14,numReposBlks=13,numNonXlnxBlks=0,numHierBlks=1,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "system_bd.hwdef" *)
|
||||
module system_bd
|
||||
(ddr_addr,
|
||||
ddr_ba,
|
||||
ddr_cas_n,
|
||||
ddr_ck_n,
|
||||
ddr_ck_p,
|
||||
ddr_cke,
|
||||
ddr_cs_n,
|
||||
ddr_dm,
|
||||
ddr_dq,
|
||||
ddr_dqs_n,
|
||||
ddr_dqs_p,
|
||||
ddr_odt,
|
||||
ddr_ras_n,
|
||||
ddr_reset_n,
|
||||
ddr_we_n,
|
||||
fixed_io_ddr_vrn,
|
||||
fixed_io_ddr_vrp,
|
||||
fixed_io_mio,
|
||||
fixed_io_ps_clk,
|
||||
fixed_io_ps_porb,
|
||||
fixed_io_ps_srstb,
|
||||
gpio_i,
|
||||
gpio_o,
|
||||
refclk_n,
|
||||
refclk_p,
|
||||
rx_rstn,
|
||||
rx_sync_n,
|
||||
rx_sync_p,
|
||||
rx_tdata,
|
||||
rx_tvalid,
|
||||
rxn_in,
|
||||
rxp_in,
|
||||
spi_miso,
|
||||
spi_mosi,
|
||||
spi_sclk,
|
||||
spi_ss_0,
|
||||
spi_ss_1,
|
||||
spi_ss_2,
|
||||
sys_clk,
|
||||
sys_rst,
|
||||
sysclk_n,
|
||||
sysclk_p,
|
||||
sysref_n,
|
||||
sysref_p,
|
||||
tx_rstn,
|
||||
tx_sync_n,
|
||||
tx_sync_p,
|
||||
tx_tdata,
|
||||
tx_tready,
|
||||
txn_out,
|
||||
txp_out);
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ddr, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) inout [14:0]ddr_addr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr BA" *) inout [2:0]ddr_ba;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr CAS_N" *) inout ddr_cas_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr CK_N" *) inout ddr_ck_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr CK_P" *) inout ddr_ck_p;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr CKE" *) inout ddr_cke;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr CS_N" *) inout ddr_cs_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr DM" *) inout [3:0]ddr_dm;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr DQ" *) inout [31:0]ddr_dq;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr DQS_N" *) inout [3:0]ddr_dqs_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr DQS_P" *) inout [3:0]ddr_dqs_p;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr ODT" *) inout ddr_odt;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr RAS_N" *) inout ddr_ras_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr RESET_N" *) inout ddr_reset_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 ddr WE_N" *) inout ddr_we_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 fixed_io DDR_VRN" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME fixed_io, CAN_DEBUG false" *) inout fixed_io_ddr_vrn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 fixed_io DDR_VRP" *) inout fixed_io_ddr_vrp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 fixed_io MIO" *) inout [53:0]fixed_io_mio;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 fixed_io PS_CLK" *) inout fixed_io_ps_clk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 fixed_io PS_PORB" *) inout fixed_io_ps_porb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 fixed_io PS_SRSTB" *) inout fixed_io_ps_srstb;
|
||||
input [15:0]gpio_i;
|
||||
output [15:0]gpio_o;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.REFCLK_N CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.REFCLK_N, CLK_DOMAIN system_bd_refclk_n, FREQ_HZ 122880000, INSERT_VIP 0, PHASE 0.000" *) input [0:0]refclk_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.REFCLK_P CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.REFCLK_P, CLK_DOMAIN system_bd_refclk_p, FREQ_HZ 122880000, INSERT_VIP 0, PHASE 0.000" *) input [0:0]refclk_p;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.RX_RSTN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.RX_RSTN, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) output rx_rstn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.RX_SYNC_N CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.RX_SYNC_N, CLK_DOMAIN system_bd_obufds_rx_sync_0_OBUF_DS_N, FREQ_HZ 100000000, INSERT_VIP 0, PHASE 0.000" *) output [0:0]rx_sync_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.RX_SYNC_P CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.RX_SYNC_P, CLK_DOMAIN system_bd_obufds_rx_sync_0_OBUF_DS_P, FREQ_HZ 100000000, INSERT_VIP 0, PHASE 0.000" *) output [0:0]rx_sync_p;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 rx TDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME rx, FREQ_HZ 122880000, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 0, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.000, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0" *) output [63:0]rx_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 rx TVALID" *) output rx_tvalid;
|
||||
input [1:0]rxn_in;
|
||||
input [1:0]rxp_in;
|
||||
input spi_miso;
|
||||
output spi_mosi;
|
||||
output spi_sclk;
|
||||
output spi_ss_0;
|
||||
output spi_ss_1;
|
||||
output spi_ss_2;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.SYS_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.SYS_CLK, CLK_DOMAIN system_bd_sys_clk_gen_0_clk_out1, FREQ_HZ 122880000, INSERT_VIP 0, PHASE 0.0" *) output sys_clk;
|
||||
output [0:0]sys_rst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.SYSCLK_N CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.SYSCLK_N, CLK_DOMAIN system_bd_sysclk_n, FREQ_HZ 122880000, INSERT_VIP 0, PHASE 0.000" *) input [0:0]sysclk_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.SYSCLK_P CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.SYSCLK_P, CLK_DOMAIN system_bd_sysclk_p, FREQ_HZ 122880000, INSERT_VIP 0, PHASE 0.000" *) input [0:0]sysclk_p;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.SYSREF_N CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.SYSREF_N, CLK_DOMAIN system_bd_sysref_n, FREQ_HZ 122880000, INSERT_VIP 0, PHASE 0.000" *) input [0:0]sysref_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.SYSREF_P CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.SYSREF_P, CLK_DOMAIN system_bd_sysref_p, FREQ_HZ 122880000, INSERT_VIP 0, PHASE 0.000" *) input [0:0]sysref_p;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.TX_RSTN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.TX_RSTN, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) output tx_rstn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.TX_SYNC_N CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.TX_SYNC_N, CLK_DOMAIN system_bd_tx_sync_n, FREQ_HZ 100000000, INSERT_VIP 0, PHASE 0.000" *) input [0:0]tx_sync_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.TX_SYNC_P CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.TX_SYNC_P, CLK_DOMAIN system_bd_tx_sync_p, FREQ_HZ 100000000, INSERT_VIP 0, PHASE 0.000" *) input [0:0]tx_sync_p;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 tx TDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME tx, FREQ_HZ 122880000, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.000, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0" *) input [63:0]tx_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 tx TREADY" *) output tx_tready;
|
||||
output [1:0]txn_out;
|
||||
output [1:0]txp_out;
|
||||
|
||||
wire [15:0]GPIO_I_0_1;
|
||||
wire [0:0]IBUF_DS_N_0_1;
|
||||
wire [0:0]IBUF_DS_N_1_2;
|
||||
wire [0:0]IBUF_DS_N_2_1;
|
||||
wire [0:0]IBUF_DS_P_0_1;
|
||||
wire [0:0]IBUF_DS_P_1_2;
|
||||
wire [0:0]IBUF_DS_P_2_1;
|
||||
wire SPI0_MISO_I_0_1;
|
||||
wire [11:0]axi_smc_M00_AXI_ARADDR;
|
||||
wire axi_smc_M00_AXI_ARREADY;
|
||||
wire axi_smc_M00_AXI_ARVALID;
|
||||
wire [11:0]axi_smc_M00_AXI_AWADDR;
|
||||
wire axi_smc_M00_AXI_AWREADY;
|
||||
wire axi_smc_M00_AXI_AWVALID;
|
||||
wire axi_smc_M00_AXI_BREADY;
|
||||
wire [1:0]axi_smc_M00_AXI_BRESP;
|
||||
wire axi_smc_M00_AXI_BVALID;
|
||||
wire [31:0]axi_smc_M00_AXI_RDATA;
|
||||
wire axi_smc_M00_AXI_RREADY;
|
||||
wire [1:0]axi_smc_M00_AXI_RRESP;
|
||||
wire axi_smc_M00_AXI_RVALID;
|
||||
wire [31:0]axi_smc_M00_AXI_WDATA;
|
||||
wire axi_smc_M00_AXI_WREADY;
|
||||
wire [3:0]axi_smc_M00_AXI_WSTRB;
|
||||
wire axi_smc_M00_AXI_WVALID;
|
||||
wire [11:0]axi_smc_M01_AXI_ARADDR;
|
||||
wire axi_smc_M01_AXI_ARREADY;
|
||||
wire axi_smc_M01_AXI_ARVALID;
|
||||
wire [11:0]axi_smc_M01_AXI_AWADDR;
|
||||
wire axi_smc_M01_AXI_AWREADY;
|
||||
wire axi_smc_M01_AXI_AWVALID;
|
||||
wire axi_smc_M01_AXI_BREADY;
|
||||
wire [1:0]axi_smc_M01_AXI_BRESP;
|
||||
wire axi_smc_M01_AXI_BVALID;
|
||||
wire [31:0]axi_smc_M01_AXI_RDATA;
|
||||
wire axi_smc_M01_AXI_RREADY;
|
||||
wire [1:0]axi_smc_M01_AXI_RRESP;
|
||||
wire axi_smc_M01_AXI_RVALID;
|
||||
wire [31:0]axi_smc_M01_AXI_WDATA;
|
||||
wire axi_smc_M01_AXI_WREADY;
|
||||
wire axi_smc_M01_AXI_WVALID;
|
||||
wire [11:0]axi_smc_M02_AXI_ARADDR;
|
||||
wire axi_smc_M02_AXI_ARREADY;
|
||||
wire axi_smc_M02_AXI_ARVALID;
|
||||
wire [11:0]axi_smc_M02_AXI_AWADDR;
|
||||
wire axi_smc_M02_AXI_AWREADY;
|
||||
wire axi_smc_M02_AXI_AWVALID;
|
||||
wire axi_smc_M02_AXI_BREADY;
|
||||
wire [1:0]axi_smc_M02_AXI_BRESP;
|
||||
wire axi_smc_M02_AXI_BVALID;
|
||||
wire [31:0]axi_smc_M02_AXI_RDATA;
|
||||
wire axi_smc_M02_AXI_RREADY;
|
||||
wire [1:0]axi_smc_M02_AXI_RRESP;
|
||||
wire axi_smc_M02_AXI_RVALID;
|
||||
wire [31:0]axi_smc_M02_AXI_WDATA;
|
||||
wire axi_smc_M02_AXI_WREADY;
|
||||
wire [3:0]axi_smc_M02_AXI_WSTRB;
|
||||
wire axi_smc_M02_AXI_WVALID;
|
||||
wire [0:0]jesd204b_OBUF_DS_N_0;
|
||||
wire [0:0]jesd204b_OBUF_DS_P_0;
|
||||
wire [63:0]jesd204b_m_axis_rx_0_TDATA;
|
||||
wire jesd204b_m_axis_rx_0_TVALID;
|
||||
wire jesd204b_rx_rstn;
|
||||
wire jesd204b_tx_rstn;
|
||||
wire [1:0]jesd204b_txn_out_0;
|
||||
wire [1:0]jesd204b_txp_out_0;
|
||||
wire [14:0]processing_system7_DDR_ADDR;
|
||||
wire [2:0]processing_system7_DDR_BA;
|
||||
wire processing_system7_DDR_CAS_N;
|
||||
wire processing_system7_DDR_CKE;
|
||||
wire processing_system7_DDR_CK_N;
|
||||
wire processing_system7_DDR_CK_P;
|
||||
wire processing_system7_DDR_CS_N;
|
||||
wire [3:0]processing_system7_DDR_DM;
|
||||
wire [31:0]processing_system7_DDR_DQ;
|
||||
wire [3:0]processing_system7_DDR_DQS_N;
|
||||
wire [3:0]processing_system7_DDR_DQS_P;
|
||||
wire processing_system7_DDR_ODT;
|
||||
wire processing_system7_DDR_RAS_N;
|
||||
wire processing_system7_DDR_RESET_N;
|
||||
wire processing_system7_DDR_WE_N;
|
||||
wire processing_system7_FCLK_CLK0;
|
||||
wire processing_system7_FCLK_RESET0_N;
|
||||
wire processing_system7_FIXED_IO_DDR_VRN;
|
||||
wire processing_system7_FIXED_IO_DDR_VRP;
|
||||
wire [53:0]processing_system7_FIXED_IO_MIO;
|
||||
wire processing_system7_FIXED_IO_PS_CLK;
|
||||
wire processing_system7_FIXED_IO_PS_PORB;
|
||||
wire processing_system7_FIXED_IO_PS_SRSTB;
|
||||
wire [15:0]processing_system7_GPIO_O;
|
||||
wire [31:0]processing_system7_M_AXI_GP0_ARADDR;
|
||||
wire [1:0]processing_system7_M_AXI_GP0_ARBURST;
|
||||
wire [3:0]processing_system7_M_AXI_GP0_ARCACHE;
|
||||
wire [11:0]processing_system7_M_AXI_GP0_ARID;
|
||||
wire [3:0]processing_system7_M_AXI_GP0_ARLEN;
|
||||
wire [1:0]processing_system7_M_AXI_GP0_ARLOCK;
|
||||
wire [2:0]processing_system7_M_AXI_GP0_ARPROT;
|
||||
wire [3:0]processing_system7_M_AXI_GP0_ARQOS;
|
||||
wire processing_system7_M_AXI_GP0_ARREADY;
|
||||
wire [2:0]processing_system7_M_AXI_GP0_ARSIZE;
|
||||
wire processing_system7_M_AXI_GP0_ARVALID;
|
||||
wire [31:0]processing_system7_M_AXI_GP0_AWADDR;
|
||||
wire [1:0]processing_system7_M_AXI_GP0_AWBURST;
|
||||
wire [3:0]processing_system7_M_AXI_GP0_AWCACHE;
|
||||
wire [11:0]processing_system7_M_AXI_GP0_AWID;
|
||||
wire [3:0]processing_system7_M_AXI_GP0_AWLEN;
|
||||
wire [1:0]processing_system7_M_AXI_GP0_AWLOCK;
|
||||
wire [2:0]processing_system7_M_AXI_GP0_AWPROT;
|
||||
wire [3:0]processing_system7_M_AXI_GP0_AWQOS;
|
||||
wire processing_system7_M_AXI_GP0_AWREADY;
|
||||
wire [2:0]processing_system7_M_AXI_GP0_AWSIZE;
|
||||
wire processing_system7_M_AXI_GP0_AWVALID;
|
||||
wire [11:0]processing_system7_M_AXI_GP0_BID;
|
||||
wire processing_system7_M_AXI_GP0_BREADY;
|
||||
wire [1:0]processing_system7_M_AXI_GP0_BRESP;
|
||||
wire processing_system7_M_AXI_GP0_BVALID;
|
||||
wire [31:0]processing_system7_M_AXI_GP0_RDATA;
|
||||
wire [11:0]processing_system7_M_AXI_GP0_RID;
|
||||
wire processing_system7_M_AXI_GP0_RLAST;
|
||||
wire processing_system7_M_AXI_GP0_RREADY;
|
||||
wire [1:0]processing_system7_M_AXI_GP0_RRESP;
|
||||
wire processing_system7_M_AXI_GP0_RVALID;
|
||||
wire [31:0]processing_system7_M_AXI_GP0_WDATA;
|
||||
wire [11:0]processing_system7_M_AXI_GP0_WID;
|
||||
wire processing_system7_M_AXI_GP0_WLAST;
|
||||
wire processing_system7_M_AXI_GP0_WREADY;
|
||||
wire [3:0]processing_system7_M_AXI_GP0_WSTRB;
|
||||
wire processing_system7_M_AXI_GP0_WVALID;
|
||||
wire processing_system7_SPI0_MOSI_O;
|
||||
wire processing_system7_SPI0_SCLK_O;
|
||||
wire processing_system7_SPI0_SS1_O;
|
||||
wire processing_system7_SPI0_SS2_O;
|
||||
wire processing_system7_SPI0_SS_O;
|
||||
wire [0:0]rst_ps7_100M_peripheral_aresetn;
|
||||
wire [1:0]rxn_in_0_1;
|
||||
wire [1:0]rxp_in_0_1;
|
||||
wire [63:0]s_axis_tx_0_1_TDATA;
|
||||
wire s_axis_tx_0_1_TREADY;
|
||||
wire sys_clk_gen_clk_out1;
|
||||
wire sys_clk_gen_locked;
|
||||
wire [0:0]sysclk_n_1;
|
||||
wire [0:0]sysclk_p_1;
|
||||
wire [0:0]sysrst_or_Res;
|
||||
wire [0:0]xlconstant_vcc_dout;
|
||||
|
||||
assign GPIO_I_0_1 = gpio_i[15:0];
|
||||
assign IBUF_DS_N_0_1 = refclk_n[0];
|
||||
assign IBUF_DS_N_1_2 = sysref_n[0];
|
||||
assign IBUF_DS_N_2_1 = tx_sync_n[0];
|
||||
assign IBUF_DS_P_0_1 = refclk_p[0];
|
||||
assign IBUF_DS_P_1_2 = sysref_p[0];
|
||||
assign IBUF_DS_P_2_1 = tx_sync_p[0];
|
||||
assign SPI0_MISO_I_0_1 = spi_miso;
|
||||
assign gpio_o[15:0] = processing_system7_GPIO_O;
|
||||
assign rx_rstn = jesd204b_rx_rstn;
|
||||
assign rx_sync_n[0] = jesd204b_OBUF_DS_N_0;
|
||||
assign rx_sync_p[0] = jesd204b_OBUF_DS_P_0;
|
||||
assign rx_tdata[63:0] = jesd204b_m_axis_rx_0_TDATA;
|
||||
assign rx_tvalid = jesd204b_m_axis_rx_0_TVALID;
|
||||
assign rxn_in_0_1 = rxn_in[1:0];
|
||||
assign rxp_in_0_1 = rxp_in[1:0];
|
||||
assign s_axis_tx_0_1_TDATA = tx_tdata[63:0];
|
||||
assign spi_mosi = processing_system7_SPI0_MOSI_O;
|
||||
assign spi_sclk = processing_system7_SPI0_SCLK_O;
|
||||
assign spi_ss_0 = processing_system7_SPI0_SS_O;
|
||||
assign spi_ss_1 = processing_system7_SPI0_SS1_O;
|
||||
assign spi_ss_2 = processing_system7_SPI0_SS2_O;
|
||||
assign sys_clk = sys_clk_gen_clk_out1;
|
||||
assign sys_rst[0] = sysrst_or_Res;
|
||||
assign sysclk_n_1 = sysclk_n[0];
|
||||
assign sysclk_p_1 = sysclk_p[0];
|
||||
assign tx_rstn = jesd204b_tx_rstn;
|
||||
assign tx_tready = s_axis_tx_0_1_TREADY;
|
||||
assign txn_out[1:0] = jesd204b_txn_out_0;
|
||||
assign txp_out[1:0] = jesd204b_txp_out_0;
|
||||
system_bd_axi_smc_0 axi_smc
|
||||
(.M00_AXI_araddr(axi_smc_M00_AXI_ARADDR),
|
||||
.M00_AXI_arready(axi_smc_M00_AXI_ARREADY),
|
||||
.M00_AXI_arvalid(axi_smc_M00_AXI_ARVALID),
|
||||
.M00_AXI_awaddr(axi_smc_M00_AXI_AWADDR),
|
||||
.M00_AXI_awready(axi_smc_M00_AXI_AWREADY),
|
||||
.M00_AXI_awvalid(axi_smc_M00_AXI_AWVALID),
|
||||
.M00_AXI_bready(axi_smc_M00_AXI_BREADY),
|
||||
.M00_AXI_bresp(axi_smc_M00_AXI_BRESP),
|
||||
.M00_AXI_bvalid(axi_smc_M00_AXI_BVALID),
|
||||
.M00_AXI_rdata(axi_smc_M00_AXI_RDATA),
|
||||
.M00_AXI_rready(axi_smc_M00_AXI_RREADY),
|
||||
.M00_AXI_rresp(axi_smc_M00_AXI_RRESP),
|
||||
.M00_AXI_rvalid(axi_smc_M00_AXI_RVALID),
|
||||
.M00_AXI_wdata(axi_smc_M00_AXI_WDATA),
|
||||
.M00_AXI_wready(axi_smc_M00_AXI_WREADY),
|
||||
.M00_AXI_wstrb(axi_smc_M00_AXI_WSTRB),
|
||||
.M00_AXI_wvalid(axi_smc_M00_AXI_WVALID),
|
||||
.M01_AXI_araddr(axi_smc_M01_AXI_ARADDR),
|
||||
.M01_AXI_arready(axi_smc_M01_AXI_ARREADY),
|
||||
.M01_AXI_arvalid(axi_smc_M01_AXI_ARVALID),
|
||||
.M01_AXI_awaddr(axi_smc_M01_AXI_AWADDR),
|
||||
.M01_AXI_awready(axi_smc_M01_AXI_AWREADY),
|
||||
.M01_AXI_awvalid(axi_smc_M01_AXI_AWVALID),
|
||||
.M01_AXI_bready(axi_smc_M01_AXI_BREADY),
|
||||
.M01_AXI_bresp(axi_smc_M01_AXI_BRESP),
|
||||
.M01_AXI_bvalid(axi_smc_M01_AXI_BVALID),
|
||||
.M01_AXI_rdata(axi_smc_M01_AXI_RDATA),
|
||||
.M01_AXI_rready(axi_smc_M01_AXI_RREADY),
|
||||
.M01_AXI_rresp(axi_smc_M01_AXI_RRESP),
|
||||
.M01_AXI_rvalid(axi_smc_M01_AXI_RVALID),
|
||||
.M01_AXI_wdata(axi_smc_M01_AXI_WDATA),
|
||||
.M01_AXI_wready(axi_smc_M01_AXI_WREADY),
|
||||
.M01_AXI_wvalid(axi_smc_M01_AXI_WVALID),
|
||||
.M02_AXI_araddr(axi_smc_M02_AXI_ARADDR),
|
||||
.M02_AXI_arready(axi_smc_M02_AXI_ARREADY),
|
||||
.M02_AXI_arvalid(axi_smc_M02_AXI_ARVALID),
|
||||
.M02_AXI_awaddr(axi_smc_M02_AXI_AWADDR),
|
||||
.M02_AXI_awready(axi_smc_M02_AXI_AWREADY),
|
||||
.M02_AXI_awvalid(axi_smc_M02_AXI_AWVALID),
|
||||
.M02_AXI_bready(axi_smc_M02_AXI_BREADY),
|
||||
.M02_AXI_bresp(axi_smc_M02_AXI_BRESP),
|
||||
.M02_AXI_bvalid(axi_smc_M02_AXI_BVALID),
|
||||
.M02_AXI_rdata(axi_smc_M02_AXI_RDATA),
|
||||
.M02_AXI_rready(axi_smc_M02_AXI_RREADY),
|
||||
.M02_AXI_rresp(axi_smc_M02_AXI_RRESP),
|
||||
.M02_AXI_rvalid(axi_smc_M02_AXI_RVALID),
|
||||
.M02_AXI_wdata(axi_smc_M02_AXI_WDATA),
|
||||
.M02_AXI_wready(axi_smc_M02_AXI_WREADY),
|
||||
.M02_AXI_wstrb(axi_smc_M02_AXI_WSTRB),
|
||||
.M02_AXI_wvalid(axi_smc_M02_AXI_WVALID),
|
||||
.S00_AXI_araddr(processing_system7_M_AXI_GP0_ARADDR),
|
||||
.S00_AXI_arburst(processing_system7_M_AXI_GP0_ARBURST),
|
||||
.S00_AXI_arcache(processing_system7_M_AXI_GP0_ARCACHE),
|
||||
.S00_AXI_arid(processing_system7_M_AXI_GP0_ARID),
|
||||
.S00_AXI_arlen(processing_system7_M_AXI_GP0_ARLEN),
|
||||
.S00_AXI_arlock(processing_system7_M_AXI_GP0_ARLOCK),
|
||||
.S00_AXI_arprot(processing_system7_M_AXI_GP0_ARPROT),
|
||||
.S00_AXI_arqos(processing_system7_M_AXI_GP0_ARQOS),
|
||||
.S00_AXI_arready(processing_system7_M_AXI_GP0_ARREADY),
|
||||
.S00_AXI_arsize(processing_system7_M_AXI_GP0_ARSIZE),
|
||||
.S00_AXI_arvalid(processing_system7_M_AXI_GP0_ARVALID),
|
||||
.S00_AXI_awaddr(processing_system7_M_AXI_GP0_AWADDR),
|
||||
.S00_AXI_awburst(processing_system7_M_AXI_GP0_AWBURST),
|
||||
.S00_AXI_awcache(processing_system7_M_AXI_GP0_AWCACHE),
|
||||
.S00_AXI_awid(processing_system7_M_AXI_GP0_AWID),
|
||||
.S00_AXI_awlen(processing_system7_M_AXI_GP0_AWLEN),
|
||||
.S00_AXI_awlock(processing_system7_M_AXI_GP0_AWLOCK),
|
||||
.S00_AXI_awprot(processing_system7_M_AXI_GP0_AWPROT),
|
||||
.S00_AXI_awqos(processing_system7_M_AXI_GP0_AWQOS),
|
||||
.S00_AXI_awready(processing_system7_M_AXI_GP0_AWREADY),
|
||||
.S00_AXI_awsize(processing_system7_M_AXI_GP0_AWSIZE),
|
||||
.S00_AXI_awvalid(processing_system7_M_AXI_GP0_AWVALID),
|
||||
.S00_AXI_bid(processing_system7_M_AXI_GP0_BID),
|
||||
.S00_AXI_bready(processing_system7_M_AXI_GP0_BREADY),
|
||||
.S00_AXI_bresp(processing_system7_M_AXI_GP0_BRESP),
|
||||
.S00_AXI_bvalid(processing_system7_M_AXI_GP0_BVALID),
|
||||
.S00_AXI_rdata(processing_system7_M_AXI_GP0_RDATA),
|
||||
.S00_AXI_rid(processing_system7_M_AXI_GP0_RID),
|
||||
.S00_AXI_rlast(processing_system7_M_AXI_GP0_RLAST),
|
||||
.S00_AXI_rready(processing_system7_M_AXI_GP0_RREADY),
|
||||
.S00_AXI_rresp(processing_system7_M_AXI_GP0_RRESP),
|
||||
.S00_AXI_rvalid(processing_system7_M_AXI_GP0_RVALID),
|
||||
.S00_AXI_wdata(processing_system7_M_AXI_GP0_WDATA),
|
||||
.S00_AXI_wid(processing_system7_M_AXI_GP0_WID),
|
||||
.S00_AXI_wlast(processing_system7_M_AXI_GP0_WLAST),
|
||||
.S00_AXI_wready(processing_system7_M_AXI_GP0_WREADY),
|
||||
.S00_AXI_wstrb(processing_system7_M_AXI_GP0_WSTRB),
|
||||
.S00_AXI_wvalid(processing_system7_M_AXI_GP0_WVALID),
|
||||
.aclk(processing_system7_FCLK_CLK0),
|
||||
.aresetn(rst_ps7_100M_peripheral_aresetn));
|
||||
jesd204b_imp_1AG4O5J jesd204b
|
||||
(.core_clk(sys_clk_gen_clk_out1),
|
||||
.jesd_reset(sysrst_or_Res),
|
||||
.m_axis_rx_tdata(jesd204b_m_axis_rx_0_TDATA),
|
||||
.m_axis_rx_tvalid(jesd204b_m_axis_rx_0_TVALID),
|
||||
.refclk_n(IBUF_DS_N_0_1),
|
||||
.refclk_p(IBUF_DS_P_0_1),
|
||||
.rx_rstn(jesd204b_rx_rstn),
|
||||
.rx_sync_n(jesd204b_OBUF_DS_N_0),
|
||||
.rx_sync_p(jesd204b_OBUF_DS_P_0),
|
||||
.rxn_in(rxn_in_0_1),
|
||||
.rxp_in(rxp_in_0_1),
|
||||
.s_axi_aclk(processing_system7_FCLK_CLK0),
|
||||
.s_axi_aresetn(rst_ps7_100M_peripheral_aresetn),
|
||||
.s_axi_phy_araddr(axi_smc_M01_AXI_ARADDR),
|
||||
.s_axi_phy_arready(axi_smc_M01_AXI_ARREADY),
|
||||
.s_axi_phy_arvalid(axi_smc_M01_AXI_ARVALID),
|
||||
.s_axi_phy_awaddr(axi_smc_M01_AXI_AWADDR),
|
||||
.s_axi_phy_awready(axi_smc_M01_AXI_AWREADY),
|
||||
.s_axi_phy_awvalid(axi_smc_M01_AXI_AWVALID),
|
||||
.s_axi_phy_bready(axi_smc_M01_AXI_BREADY),
|
||||
.s_axi_phy_bresp(axi_smc_M01_AXI_BRESP),
|
||||
.s_axi_phy_bvalid(axi_smc_M01_AXI_BVALID),
|
||||
.s_axi_phy_rdata(axi_smc_M01_AXI_RDATA),
|
||||
.s_axi_phy_rready(axi_smc_M01_AXI_RREADY),
|
||||
.s_axi_phy_rresp(axi_smc_M01_AXI_RRESP),
|
||||
.s_axi_phy_rvalid(axi_smc_M01_AXI_RVALID),
|
||||
.s_axi_phy_wdata(axi_smc_M01_AXI_WDATA),
|
||||
.s_axi_phy_wready(axi_smc_M01_AXI_WREADY),
|
||||
.s_axi_phy_wvalid(axi_smc_M01_AXI_WVALID),
|
||||
.s_axi_rx_araddr(axi_smc_M02_AXI_ARADDR),
|
||||
.s_axi_rx_arready(axi_smc_M02_AXI_ARREADY),
|
||||
.s_axi_rx_arvalid(axi_smc_M02_AXI_ARVALID),
|
||||
.s_axi_rx_awaddr(axi_smc_M02_AXI_AWADDR),
|
||||
.s_axi_rx_awready(axi_smc_M02_AXI_AWREADY),
|
||||
.s_axi_rx_awvalid(axi_smc_M02_AXI_AWVALID),
|
||||
.s_axi_rx_bready(axi_smc_M02_AXI_BREADY),
|
||||
.s_axi_rx_bresp(axi_smc_M02_AXI_BRESP),
|
||||
.s_axi_rx_bvalid(axi_smc_M02_AXI_BVALID),
|
||||
.s_axi_rx_rdata(axi_smc_M02_AXI_RDATA),
|
||||
.s_axi_rx_rready(axi_smc_M02_AXI_RREADY),
|
||||
.s_axi_rx_rresp(axi_smc_M02_AXI_RRESP),
|
||||
.s_axi_rx_rvalid(axi_smc_M02_AXI_RVALID),
|
||||
.s_axi_rx_wdata(axi_smc_M02_AXI_WDATA),
|
||||
.s_axi_rx_wready(axi_smc_M02_AXI_WREADY),
|
||||
.s_axi_rx_wstrb(axi_smc_M02_AXI_WSTRB),
|
||||
.s_axi_rx_wvalid(axi_smc_M02_AXI_WVALID),
|
||||
.s_axi_tx_araddr(axi_smc_M00_AXI_ARADDR),
|
||||
.s_axi_tx_arready(axi_smc_M00_AXI_ARREADY),
|
||||
.s_axi_tx_arvalid(axi_smc_M00_AXI_ARVALID),
|
||||
.s_axi_tx_awaddr(axi_smc_M00_AXI_AWADDR),
|
||||
.s_axi_tx_awready(axi_smc_M00_AXI_AWREADY),
|
||||
.s_axi_tx_awvalid(axi_smc_M00_AXI_AWVALID),
|
||||
.s_axi_tx_bready(axi_smc_M00_AXI_BREADY),
|
||||
.s_axi_tx_bresp(axi_smc_M00_AXI_BRESP),
|
||||
.s_axi_tx_bvalid(axi_smc_M00_AXI_BVALID),
|
||||
.s_axi_tx_rdata(axi_smc_M00_AXI_RDATA),
|
||||
.s_axi_tx_rready(axi_smc_M00_AXI_RREADY),
|
||||
.s_axi_tx_rresp(axi_smc_M00_AXI_RRESP),
|
||||
.s_axi_tx_rvalid(axi_smc_M00_AXI_RVALID),
|
||||
.s_axi_tx_wdata(axi_smc_M00_AXI_WDATA),
|
||||
.s_axi_tx_wready(axi_smc_M00_AXI_WREADY),
|
||||
.s_axi_tx_wstrb(axi_smc_M00_AXI_WSTRB),
|
||||
.s_axi_tx_wvalid(axi_smc_M00_AXI_WVALID),
|
||||
.s_axis_tx_tdata(s_axis_tx_0_1_TDATA),
|
||||
.s_axis_tx_tready(s_axis_tx_0_1_TREADY),
|
||||
.sysref_n(IBUF_DS_N_1_2),
|
||||
.sysref_p(IBUF_DS_P_1_2),
|
||||
.tx_rstn(jesd204b_tx_rstn),
|
||||
.tx_sync_n(IBUF_DS_N_2_1),
|
||||
.tx_sync_p(IBUF_DS_P_2_1),
|
||||
.txn_out(jesd204b_txn_out_0),
|
||||
.txp_out(jesd204b_txp_out_0));
|
||||
system_bd_ld_2_rst_0 ld_2_rst
|
||||
(.Op1(sys_clk_gen_locked),
|
||||
.Res(sysrst_or_Res));
|
||||
system_bd_processing_system7_0 processing_system7
|
||||
(.DDR_Addr(ddr_addr[14:0]),
|
||||
.DDR_BankAddr(ddr_ba[2:0]),
|
||||
.DDR_CAS_n(ddr_cas_n),
|
||||
.DDR_CKE(ddr_cke),
|
||||
.DDR_CS_n(ddr_cs_n),
|
||||
.DDR_Clk(ddr_ck_p),
|
||||
.DDR_Clk_n(ddr_ck_n),
|
||||
.DDR_DM(ddr_dm[3:0]),
|
||||
.DDR_DQ(ddr_dq[31:0]),
|
||||
.DDR_DQS(ddr_dqs_p[3:0]),
|
||||
.DDR_DQS_n(ddr_dqs_n[3:0]),
|
||||
.DDR_DRSTB(ddr_reset_n),
|
||||
.DDR_ODT(ddr_odt),
|
||||
.DDR_RAS_n(ddr_ras_n),
|
||||
.DDR_VRN(fixed_io_ddr_vrn),
|
||||
.DDR_VRP(fixed_io_ddr_vrp),
|
||||
.DDR_WEB(ddr_we_n),
|
||||
.FCLK_CLK0(processing_system7_FCLK_CLK0),
|
||||
.FCLK_RESET0_N(processing_system7_FCLK_RESET0_N),
|
||||
.GPIO_I(GPIO_I_0_1),
|
||||
.GPIO_O(processing_system7_GPIO_O),
|
||||
.MIO(fixed_io_mio[53:0]),
|
||||
.M_AXI_GP0_ACLK(processing_system7_FCLK_CLK0),
|
||||
.M_AXI_GP0_ARADDR(processing_system7_M_AXI_GP0_ARADDR),
|
||||
.M_AXI_GP0_ARBURST(processing_system7_M_AXI_GP0_ARBURST),
|
||||
.M_AXI_GP0_ARCACHE(processing_system7_M_AXI_GP0_ARCACHE),
|
||||
.M_AXI_GP0_ARID(processing_system7_M_AXI_GP0_ARID),
|
||||
.M_AXI_GP0_ARLEN(processing_system7_M_AXI_GP0_ARLEN),
|
||||
.M_AXI_GP0_ARLOCK(processing_system7_M_AXI_GP0_ARLOCK),
|
||||
.M_AXI_GP0_ARPROT(processing_system7_M_AXI_GP0_ARPROT),
|
||||
.M_AXI_GP0_ARQOS(processing_system7_M_AXI_GP0_ARQOS),
|
||||
.M_AXI_GP0_ARREADY(processing_system7_M_AXI_GP0_ARREADY),
|
||||
.M_AXI_GP0_ARSIZE(processing_system7_M_AXI_GP0_ARSIZE),
|
||||
.M_AXI_GP0_ARVALID(processing_system7_M_AXI_GP0_ARVALID),
|
||||
.M_AXI_GP0_AWADDR(processing_system7_M_AXI_GP0_AWADDR),
|
||||
.M_AXI_GP0_AWBURST(processing_system7_M_AXI_GP0_AWBURST),
|
||||
.M_AXI_GP0_AWCACHE(processing_system7_M_AXI_GP0_AWCACHE),
|
||||
.M_AXI_GP0_AWID(processing_system7_M_AXI_GP0_AWID),
|
||||
.M_AXI_GP0_AWLEN(processing_system7_M_AXI_GP0_AWLEN),
|
||||
.M_AXI_GP0_AWLOCK(processing_system7_M_AXI_GP0_AWLOCK),
|
||||
.M_AXI_GP0_AWPROT(processing_system7_M_AXI_GP0_AWPROT),
|
||||
.M_AXI_GP0_AWQOS(processing_system7_M_AXI_GP0_AWQOS),
|
||||
.M_AXI_GP0_AWREADY(processing_system7_M_AXI_GP0_AWREADY),
|
||||
.M_AXI_GP0_AWSIZE(processing_system7_M_AXI_GP0_AWSIZE),
|
||||
.M_AXI_GP0_AWVALID(processing_system7_M_AXI_GP0_AWVALID),
|
||||
.M_AXI_GP0_BID(processing_system7_M_AXI_GP0_BID),
|
||||
.M_AXI_GP0_BREADY(processing_system7_M_AXI_GP0_BREADY),
|
||||
.M_AXI_GP0_BRESP(processing_system7_M_AXI_GP0_BRESP),
|
||||
.M_AXI_GP0_BVALID(processing_system7_M_AXI_GP0_BVALID),
|
||||
.M_AXI_GP0_RDATA(processing_system7_M_AXI_GP0_RDATA),
|
||||
.M_AXI_GP0_RID(processing_system7_M_AXI_GP0_RID),
|
||||
.M_AXI_GP0_RLAST(processing_system7_M_AXI_GP0_RLAST),
|
||||
.M_AXI_GP0_RREADY(processing_system7_M_AXI_GP0_RREADY),
|
||||
.M_AXI_GP0_RRESP(processing_system7_M_AXI_GP0_RRESP),
|
||||
.M_AXI_GP0_RVALID(processing_system7_M_AXI_GP0_RVALID),
|
||||
.M_AXI_GP0_WDATA(processing_system7_M_AXI_GP0_WDATA),
|
||||
.M_AXI_GP0_WID(processing_system7_M_AXI_GP0_WID),
|
||||
.M_AXI_GP0_WLAST(processing_system7_M_AXI_GP0_WLAST),
|
||||
.M_AXI_GP0_WREADY(processing_system7_M_AXI_GP0_WREADY),
|
||||
.M_AXI_GP0_WSTRB(processing_system7_M_AXI_GP0_WSTRB),
|
||||
.M_AXI_GP0_WVALID(processing_system7_M_AXI_GP0_WVALID),
|
||||
.PS_CLK(fixed_io_ps_clk),
|
||||
.PS_PORB(fixed_io_ps_porb),
|
||||
.PS_SRSTB(fixed_io_ps_srstb),
|
||||
.SPI0_MISO_I(SPI0_MISO_I_0_1),
|
||||
.SPI0_MOSI_I(processing_system7_SPI0_MOSI_O),
|
||||
.SPI0_MOSI_O(processing_system7_SPI0_MOSI_O),
|
||||
.SPI0_SCLK_I(processing_system7_SPI0_SCLK_O),
|
||||
.SPI0_SCLK_O(processing_system7_SPI0_SCLK_O),
|
||||
.SPI0_SS1_O(processing_system7_SPI0_SS1_O),
|
||||
.SPI0_SS2_O(processing_system7_SPI0_SS2_O),
|
||||
.SPI0_SS_I(xlconstant_vcc_dout),
|
||||
.SPI0_SS_O(processing_system7_SPI0_SS_O));
|
||||
system_bd_rst_ps7_100M_0 rst_ps7_100M
|
||||
(.aux_reset_in(1'b1),
|
||||
.dcm_locked(1'b1),
|
||||
.ext_reset_in(processing_system7_FCLK_RESET0_N),
|
||||
.mb_debug_sys_rst(1'b0),
|
||||
.peripheral_aresetn(rst_ps7_100M_peripheral_aresetn),
|
||||
.slowest_sync_clk(processing_system7_FCLK_CLK0));
|
||||
system_bd_sys_clk_gen_0 sys_clk_gen
|
||||
(.clk_in1_n(sysclk_n_1),
|
||||
.clk_in1_p(sysclk_p_1),
|
||||
.clk_out1(sys_clk_gen_clk_out1),
|
||||
.locked(sys_clk_gen_locked));
|
||||
system_bd_xlconstant_vcc_0 xlconstant_vcc
|
||||
(.dout(xlconstant_vcc_dout));
|
||||
endmodule
|
||||
Reference in New Issue
Block a user