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josh
2023-03-18 15:35:53 +08:00
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projects/datalink_814/dl814_dj/rtl/rf_control.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/01/13 12:04:17
// Design Name:
// Module Name: rf_control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rf_control(
input clk , //192Mclk
input rst ,
input [5:0] tx_gain_manual , //发射增益输入
input [5:0] rx_gain_manual , //接收增益输入
input gain_on_vio , //vio设置参数or自动切换
input [1:0] rf_txrx_vio , //发射通道或者接收通道
input [1:0] rf_txrx_net , //受网络层控制
input rf_vio_set , //vio设置参数or自动切换
input [10:0] tx_freq_hop_words , //tx跳频频率控制字
input tx_hop_words_valid , //tx跳频频率控制字有效脉冲
input tx_freq_hop_switch , //tx频点切换脉冲
input [10:0] rx_freq_hop_words , //rx跳频频率控制字
input rx_hop_words_valid , //rx跳频频率控制字有效脉冲
input rx_freq_hop_switch , //rx频点切换脉冲
input [10:0] freq_hop_words_vio , //vio设置跳频频率控制字
input hop_words_valid_vio , //vio设置跳频频率控制字有效脉冲
input freq_hop_switch_vio , //vio设置频点切换脉冲
output reg [11:0] tx_gain = 12'd0 , //发射通道增益
output reg tx_gain_on = 1'd0 , //发射通道开关
output reg [9:0] rx_gain = 10'd0 , //接收通道增益
output reg rx_gain_on = 1'd0 , //发射通道开关
output reg [10:0] freq_hop_words = 11'd0 , //跳频频率控制字
output reg hop_words_valid = 1'd0 , //跳频频率控制字有效脉冲
output reg freq_hop_switch = 1'd0 , //频点切换脉冲
output reg freq_hop_switch_out = 1'd0
);
reg rst_D1_1 = 1'd0;
reg rst_D1_2 = 1'd0;
reg rst_D1_3 = 1'd0;
always @(posedge clk) begin
rst_D1_1 <= rst ;
rst_D1_2 <= rst ;
rst_D1_3 <= rst ;
end
//--------------------------------------------------------------------------------------------------
//发射通道增益、开关设置
always @(posedge clk) begin
if(rst_D1_1)
tx_gain_on <= 1'b0 ;
else if(gain_on_vio)
tx_gain_on <= (rf_txrx_vio[1:0] == 2'd1) ? 1'd1 :1'd0 ;
else
tx_gain_on <= (rf_txrx_net[1:0] == 2'd1) ? 1'd1 :1'd0 ;
if(rst_D1_1)
tx_gain[11:0] <= 12'b111111111111 ;
else
tx_gain[11:0] <= {5'b0,tx_gain_manual[5:0],1'b0};
end
//--------------------------------------------------------------------------------------------------
//接收通道增益、开关设置
reg [5:0] rx_gain_div2 = 5'd0;
always @(posedge clk) begin
if(rst_D1_2)
rx_gain_on <= 1'b0 ;
else if(gain_on_vio)
rx_gain_on <= (rf_txrx_vio[1:0] == 2'd2) ? 1'd1 :1'd0 ;
else
rx_gain_on <= (rf_txrx_net[1:0] == 2'd2) ? 1'd1 :1'd0 ;
if(rst_D1_2)
rx_gain[9:0] <= 10'b1111111111 ;
else
rx_gain[9:0] <= {4'b0,rx_gain_manual[5:0]} ;
end
//--------------------------------------------------------------------------------------------------
//跳频设置vio控制or网络层设置
reg [10:0] freq_hop_words_net = 11'd0 ;
reg hop_words_valid_net = 1'd0 ;
reg freq_hop_switch_net = 1'd0 ;
always @(posedge clk) begin
if(rst_D1_3)begin
freq_hop_words_net [10:0] <= 11'd0 ;
hop_words_valid_net <= 1'd0 ;
freq_hop_switch_net <= 1'd0 ;
end
else if(rf_txrx_net[1:0] == 2'd1)begin
freq_hop_words_net [10:0] <= tx_freq_hop_words[10:0] ;
hop_words_valid_net <= tx_hop_words_valid ;
freq_hop_switch_net <= tx_freq_hop_switch ;
end
else if(rf_txrx_net[1:0] == 2'd2)begin
freq_hop_words_net [10:0] <= rx_freq_hop_words[10:0] ;
hop_words_valid_net <= rx_hop_words_valid ;
freq_hop_switch_net <= rx_freq_hop_switch ;
end
else begin
freq_hop_words_net [10:0] <= freq_hop_words_net [10:0] ;
hop_words_valid_net <= 1'd0 ;
freq_hop_switch_net <= 1'd0 ;
end
end
always @(posedge clk) begin
if(rst_D1_3)begin
freq_hop_words [10:0] <= 11'd0 ;
hop_words_valid <= 1'd0 ;
freq_hop_switch <= 1'd0 ;
freq_hop_switch_out <= 1'd0 ;
end
else if(rf_vio_set)begin
freq_hop_words [10:0] <= freq_hop_words_vio[10:0] ;
hop_words_valid <= hop_words_valid_vio ;
freq_hop_switch <= freq_hop_switch_vio ;
freq_hop_switch_out <= freq_hop_switch_vio ;
end
else begin
freq_hop_words [10:0] <= freq_hop_words_net[10:0] ;
hop_words_valid <= hop_words_valid_net ;
freq_hop_switch <= freq_hop_switch_net ;
freq_hop_switch_out <= freq_hop_switch_net ;
end
end
// ila_RF ila_RF (
// .clk (clk ), // input wire clk
// .probe0 (tx_gain[11:0] ), // input wire [11:0] probe0
// .probe1 (tx_gain_on ), // input wire [0:0] probe1
// .probe2 (rx_gain[9:0] ), // input wire [9:0] probe2
// .probe3 (rx_gain_on ), // input wire [0:0] probe3
// .probe4 (freq_hop_words[10:0] ), // input wire [10:0] probe4
// .probe5 (hop_words_valid ), // input wire [0:0] probe5
// .probe6 (freq_hop_switch ) // input wire [0:0] probe6
// );
endmodule
projects/datalink_814/dl814_dj/rtl/system_top.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2022/06/07 21:17:23
// Design Name:
// Module Name: system_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module system_top
(
// *************************************************************************
// *************************** Clocks and Resets ***************************
// *************************************************************************
input sysclk_p , // FPGA_LOGIC_CLK_IN, derived from ad9528, 122.88mhz
input sysclk_n ,
input refclk_p , // FPGA_JESD204B_CLK_IN_1, derived from ad9528, 122.88mhz
input refclk_n ,
input sysref_p ,
input sysref_n ,
// *************************************************************************
// *************************** AD9528 Interface ****************************
// *************************************************************************
// spi interface
output spi_csn_ad9528 ,
output spi_clk_ad9528 ,
output spi_mosi_ad9528 ,
input spi_miso_ad9528 ,
// control signals
output ad9528_reset_b ,
output ad9528_sysref_req ,
// *************************************************************************
// *************************** AD9371 Interface ****************************
// *************************************************************************
// 204b interface, only lane 0 and lane 1 are used
output rx_sync_p ,
output rx_sync_n ,
input tx_sync_p ,
input tx_sync_n ,
input [ 1:0] rx_data_p ,
input [ 1:0] rx_data_n ,
output [ 1:0] tx_data_p ,
output [ 1:0] tx_data_n ,
// spi interface
output spi_csn_ad9371 ,
output spi_clk_ad9371 ,
output spi_mosi_ad9371 ,
input spi_miso_ad9371 ,
// control signals
output ad9371_test ,
output ad9371_reset_b ,
input ad9371_gpint ,
// *************************************************************************
// ****************************** RF Control *******************************
// *************************************************************************
output tx_gain_5bit ,
output tx_gain_6bit ,
output rx_gain_3bit ,
output rx_gain_4bit ,
output rx_gain_5bit ,
output tx_gain_on ,
output rx_gain_on ,
output [10:0] freq_hop_words ,
output hop_words_valid ,
output freq_hop_switch ,
// *************************************************************************
// ******************* DDR and Fixed-io (Do NOT Modify) ********************
// *************************************************************************
// ddr
inout [14:0] ddr_addr ,
inout [ 2:0] ddr_ba ,
inout ddr_cas_n ,
inout ddr_ck_n ,
inout ddr_ck_p ,
inout ddr_cke ,
inout ddr_cs_n ,
inout [ 3:0] ddr_dm ,
inout [31:0] ddr_dq ,
inout [ 3:0] ddr_dqs_n ,
inout [ 3:0] ddr_dqs_p ,
inout ddr_odt ,
inout ddr_ras_n ,
inout ddr_reset_n ,
inout ddr_we_n ,
// fixed-io
inout fixed_io_ddr_vrn ,
inout fixed_io_ddr_vrp ,
inout [53:0] fixed_io_mio ,
inout fixed_io_ps_clk ,
inout fixed_io_ps_porb ,
inout fixed_io_ps_srstb
);
////////////////////////////////////////////////////////////////////////////////
/////////////////////////// System Clock Generation ////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// system main clock, mmcm is included in block design
wire sys_clk ; // 122.88mhz
wire sys_rst ;
// optional siganl clock, can be changed to whatever frequency you want
wire sig_clk ; // 245.76mhz
wire sig_clk_ld ;
wire sig_rst ;
assign sig_rst = ~sig_clk_ld;
sig_clk_gen u_sig_clk_gen
(
// Clock out ports
.clk_out1 (sig_clk ), // output clk_out1
// Status and control signals
.reset (sys_rst ), // input reset
.locked (sig_clk_ld ), // output locked
// Clock in ports
.clk_in1 (sys_clk ) // input clk_in1
);
////////////////////////////////////////////////////////////////////////////////
//////////////////////////// Block Design Interface ////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// gpio
wire [15:0] gpio_i ;
wire [15:0] gpio_o ;
assign gpio_i[15:5] = gpio_o[15:5];
assign ad9528_reset_b = gpio_o[4]; // ad9528 reset pin
assign ad9528_sysref_req = gpio_o[3]; // ad9528 sysref requset pin
assign ad9371_test = gpio_o[2];
assign ad9371_reset_b = gpio_o[1];
assign gpio_i[0] = ad9371_gpint ; // ad9371 gpio interrupt pin
// ad9371 jesd204b signals
wire rx_rstn ;
wire [63:0] rx_tdata ;
wire rx_tvalid ;
wire tx_rstn ;
wire [63:0] tx_tdata ;
wire tx_tready ;
// spi interface
wire spi_clk ;
wire spi_mosi ;
reg spi_miso ;
assign spi_clk_ad9528 = spi_clk ;
assign spi_clk_ad9371 = spi_clk ;
assign spi_mosi_ad9528 = spi_mosi ;
assign spi_mosi_ad9371 = spi_mosi ;
always @(*) begin
if (~spi_csn_ad9528)
spi_miso = spi_miso_ad9528;
else if (~spi_csn_ad9371)
spi_miso = spi_miso_ad9371;
else
spi_miso = 1'bz;
end
system_bd_wrapper u_system_bd
(
// ddr
.ddr_addr (ddr_addr ), // inout [14:0]ddr_addr
.ddr_ba (ddr_ba ), // inout [2:0]ddr_ba
.ddr_cas_n (ddr_cas_n ), // inout ddr_cas_n
.ddr_ck_n (ddr_ck_n ), // inout ddr_ck_n
.ddr_ck_p (ddr_ck_p ), // inout ddr_ck_p
.ddr_cke (ddr_cke ), // inout ddr_cke
.ddr_cs_n (ddr_cs_n ), // inout ddr_cs_n
.ddr_dm (ddr_dm ), // inout [3:0]ddr_dm
.ddr_dq (ddr_dq ), // inout [31:0]ddr_dq
.ddr_dqs_n (ddr_dqs_n ), // inout [3:0]ddr_dqs_n
.ddr_dqs_p (ddr_dqs_p ), // inout [3:0]ddr_dqs_p
.ddr_odt (ddr_odt ), // inout ddr_odt
.ddr_ras_n (ddr_ras_n ), // inout ddr_ras_n
.ddr_reset_n (ddr_reset_n ), // inout ddr_reset_n
.ddr_we_n (ddr_we_n ), // inout ddr_we_n
// fixed io
.fixed_io_ddr_vrn (fixed_io_ddr_vrn ), // inout fixed_io_ddr_vrn
.fixed_io_ddr_vrp (fixed_io_ddr_vrp ), // inout fixed_io_ddr_vrp
.fixed_io_mio (fixed_io_mio ), // inout [53:0]fixed_io_mio
.fixed_io_ps_clk (fixed_io_ps_clk ), // inout fixed_io_ps_clk
.fixed_io_ps_porb (fixed_io_ps_porb ), // inout fixed_io_ps_porb
.fixed_io_ps_srstb (fixed_io_ps_srstb ), // inout fixed_io_ps_srstb
// gpio, for control signals
.gpio_i (gpio_i[15:0] ), // input [15:0]gpio_i
.gpio_o (gpio_o[15:0] ), // output [15:0]gpio_o
// spi interface
.spi_miso (spi_miso ), // input spi_miso
.spi_mosi (spi_mosi ), // output spi_mosi
.spi_sclk (spi_clk ), // output spi_sclk
.spi_ss_0 (spi_csn_ad9528 ), // output spi_ss_0
.spi_ss_1 (spi_csn_ad9371 ), // output spi_ss_1
.spi_ss_2 ( ), // output spi_ss_2
// system main clock
.sysclk_p (sysclk_p ), // input sysclk_p
.sysclk_n (sysclk_n ), // input sysclk_n
.sys_clk (sys_clk ), // output sys_clk
.sys_rst (sys_rst ), // output sys_rst
// jesd 204b interface
.refclk_p (refclk_p ), // input refclk_p
.refclk_n (refclk_n ), // input refclk_n
.sysref_p (sysref_p ), // input sysref_p
.sysref_n (sysref_n ), // input sysref_n
.rxp_in (rx_data_p[1:0] ), // input [1:0]rxp_in
.rxn_in (rx_data_n[1:0] ), // input [1:0]rxn_in
.rx_sync_p (rx_sync_p ), // output rx_sync_p
.rx_sync_n (rx_sync_n ), // output rx_sync_n
.rx_rstn (rx_rstn ), // output rx_rstn
.rx_tdata (rx_tdata[63:0] ), // output [63:0]rx_tdata
.rx_tvalid (rx_tvalid ), // output rx_tvalid
.txp_out (tx_data_p[1:0] ), // output [1:0]txp_out
.txn_out (tx_data_n[1:0] ), // output [1:0]txn_out
.tx_sync_p (tx_sync_p ), // input tx_sync_p
.tx_sync_n (tx_sync_n ), // input tx_sync_n
.tx_rstn (tx_rstn ), // output tx_rstn
.tx_tdata (tx_tdata[63:0] ), // input [63:0]tx_tdata
.tx_tready (tx_tready ) // output tx_tready
);
////////////////////////////////////////////////////////////////////////////////
//////////////////////////// RF Control Interface //////////////////////////////
////////////////////////////////////////////////////////////////////////////////
wire gain_on_vio ;
wire [1:0] rf_txrx_vio ;
wire rf_vio_set ;
wire [5:0] tx_gain_manual ;
wire [5:0] rx_gain_manual ;
wire [10:0] freq_hop_words_vio ;
wire hop_words_valid_vio ;
wire freq_hop_switch_vio ;
wire freq_hop_switch_out ;
wire [11:0] tx_gain;
wire [11:0] rx_gain;
assign tx_gain_5bit = tx_gain[5];
assign tx_gain_6bit = tx_gain[6];
assign rx_gain_5bit = rx_gain[5];
assign rx_gain_4bit = rx_gain[4];
assign rx_gain_3bit = rx_gain[3];
rf_control u_rf_control(
.clk (sys_clk ),
.rst (sys_rst ),
//input
.gain_on_vio (gain_on_vio ),
.rf_txrx_vio (rf_txrx_vio[1:0] ),
.rf_txrx_net (2'd0 ),
.tx_gain_manual (tx_gain_manual[5:0] ),
.rx_gain_manual (rx_gain_manual[5:0] ),
//0:net->control 1:vio->control
.rf_vio_set (rf_vio_set ),
//vio hop control
.freq_hop_words_vio (freq_hop_words_vio[10:0] ),
.hop_words_valid_vio (hop_words_valid_vio ),
.freq_hop_switch_vio (freq_hop_switch_vio ),
//tx hop control
.tx_freq_hop_words (11'b0 ),
.tx_hop_words_valid (1'b0 ),
.tx_freq_hop_switch (1'b0 ),
//rx hop control
.rx_freq_hop_words (11'b0 ),
.rx_hop_words_valid (1'b0 ),
.rx_freq_hop_switch (1'b0 ),
//output
.tx_gain (tx_gain[11:0] ),
.tx_gain_on (tx_gain_on ),
.rx_gain (rx_gain[9:0] ),
.rx_gain_on (rx_gain_on ),
.freq_hop_words (freq_hop_words[10:0] ),
.hop_words_valid (hop_words_valid ),
.freq_hop_switch (freq_hop_switch ),
.freq_hop_switch_out (freq_hop_switch_out )
);
////////////////////////////////////////////////////////////////////////////////
///////////////////////////// Tx Baseband Signals //////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// baseband signal
wire [15:0] tx_1_i;
wire [15:0] tx_1_q;
wire [15:0] tx_2_i;
wire [15:0] tx_2_q;
assign tx_tdata =
{
tx_2_q[7:0], tx_2_q[15:8], tx_2_i[7:0], tx_2_i[15:8],
tx_1_q[7:0], tx_1_q[15:8], tx_1_i[7:0], tx_1_i[15:8]
};
wire [15:0] tx_data_i;
wire [15:0] tx_data_q;
assign tx_1_i = tx_data_i;
assign tx_1_q = tx_data_q;
assign tx_2_i = tx_data_i;
assign tx_2_q = tx_data_q;
// <--------------------------------------------------------------------------->
// <--------------------- insert transmitter logic below ---------------------->
// <--------------------------------------------------------------------------->
wire [ 1:0] waveform_sel;
wire sweep_on ;
wire [31:0] freq_set ;
wire [ 1:0] iq_sel ;
wire [ 3:0] bb_rshift ;
tx_qpsk #(
.DATA_WIDTH (16 ),
.CLK_FREQ (122880000 )
) u_tx_qpsk
(
.clk (sys_clk ), // input clk
.rst (sys_rst ), // input rst
.tx_data_i (tx_data_i ), // output [15:0] tx_data_i
.tx_data_q (tx_data_q ), // output [15:0] tx_data_q
// debug ports
.waveform_sel (waveform_sel ), // input [ 1:0] waveform_sel
.sweep_on (sweep_on ), // input sweep_on
.freq_set (freq_set ), // input [31:0] freq_set
.iq_sel (iq_sel ), // input [ 1:0] iq_sel
.bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift
);
////////////////////////////////////////////////////////////////////////////////
///////////////////////////// Rx Baseband Signals //////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// rx signal
wire [15:0] rx_1_i;
wire [15:0] rx_1_q;
wire [15:0] rx_2_i;
wire [15:0] rx_2_q;
assign rx_1_i = { rx_tdata[ 7: 0] , rx_tdata[15: 8]};
assign rx_1_q = { rx_tdata[23:16] , rx_tdata[31:24]};
assign rx_2_i = { rx_tdata[39:32] , rx_tdata[47:40]};
assign rx_2_q = { rx_tdata[55:48] , rx_tdata[63:56]};
// <--------------------------------------------------------------------------->
// <----------------------- insert receiver logic below ----------------------->
// <--------------------------------------------------------------------------->
////////////////////////////////////////////////////////////////////////////////
//////////////////////////////// ILAs and VIOs /////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
ila_tx_rx u_ila_tx_rx
(
.clk (sys_clk ), // input wire clk
.probe0 (rx_1_i ), // input wire [15:0] probe0
.probe1 (rx_1_q ), // input wire [15:0] probe1
.probe2 (rx_2_i ), // input wire [15:0] probe2
.probe3 (rx_2_q ), // input wire [15:0] probe3
.probe4 (tx_data_i ), // input wire [15:0] probe4
.probe5 (tx_data_q ), // input wire [15:0] probe5
.probe6 (rx_tvalid ), // input wire [0:0] probe6
.probe7 (tx_tready ) // input wire [0:0] probe7
);
ila_ctrl_signal u_ila_ctrl_signal
(
.clk (sys_clk ), // input wire clk
.probe0 (u_system_bd.system_bd_i.jesd204b.jesd_reset ), // input wire [0:0] probe0
.probe1 (u_system_bd.system_bd_i.jesd204b.rx_sync ), // input wire [0:0] probe1
.probe2 (rx_rstn ), // input wire [0:0] probe2
.probe3 (u_system_bd.system_bd_i.jesd204b.tx_sync ), // input wire [0:0] probe3
.probe4 (tx_rstn ), // input wire [0:0] probe4
.probe5 (u_system_bd.system_bd_i.jesd204b.sysref ) // input wire [0:0] probe5
);
vio_manual_ctrl u_vio_manual_ctrl
(
.clk (sys_clk ), // input wire clk
.probe_out0 (waveform_sel ), // output wire [1 : 0] probe_out0
.probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1
.probe_out2 (freq_set ), // output wire [31 : 0] probe_out2
.probe_out3 (iq_sel ), // output wire [1 : 0] probe_out3
.probe_out4 (bb_rshift ) // output wire [3 : 0] probe_out4
);
vio_rf_control u_vio_rf_control
(
.clk (sys_clk ), // input wire clk
.probe_out0 (gain_on_vio ), // output wire [0 : 0] probe_out0
.probe_out1 (rf_txrx_vio[1:0] ), // output wire [1 : 0] probe_out1
.probe_out2 (rf_vio_set ), // output wire [0 : 0] probe_out2
.probe_out3 (tx_gain_manual[5:0] ), // output wire [5 : 0] probe_out3
.probe_out4 (rx_gain_manual[5:0] ), // output wire [5 : 0] probe_out4
.probe_out5 (freq_hop_words_vio[10:0] ), // output wire [10 : 0] probe_out5
.probe_out6 (hop_words_valid_vio ), // output wire [0 : 0] probe_out6
.probe_out7 (freq_hop_switch_vio ), // output wire [0 : 0] probe_out7
.probe_out8 (self_check_dout ) // output wire [0 : 0] probe_out8
);
endmodule
projects/datalink_814/dl814_dj/rtl/tx_qpsk.v
+412
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2022/03/23 20:17:56
// Last Modified Date: 2023/03/10 15:41
// Design Name:
// Module Name: tx_qpsk
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// 20230228-1541 - 修改不扫频、无基带频偏时 [baseband_i/q] 的数据输出，原来从
// 乘法器引出，会导致频率为 0 时输出数据错误，现在直接从基带数据引出。
// 20230310-1542 - 增加输入参数，发送数据更改为直接由参数输入，发送方波改为 8
// 倍过采样，发送双音信号中 1MHz 信号的频率控制字可以根据参数中的时钟频率计
// 算得出。
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tx_qpsk
#(
parameter DATA_WIDTH = 12, // need to be <= 16
parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
parameter BIT_DATA_LEN = 128,
parameter SQUARE_INTERP = 8,
parameter CLK_FREQ = 245760000 // in Hertz
)
(
input clk ,
input rst ,
output [DATA_WIDTH-1:0] tx_data_i ,
output [DATA_WIDTH-1:0] tx_data_q ,
// debug ports
input [ 1:0] waveform_sel ,
input sweep_on ,
input [31:0] freq_set ,
input [ 1:0] iq_sel ,
input [ 3:0] bb_rshift
);
localparam RCOS_INTERP = 64;
localparam INTERP = (RCOS_INTERP > SQUARE_INTERP) ? RCOS_INTERP : SQUARE_INTERP;
localparam FREQ_WORD_1M = 64'd2**64'd32*64'd1000000/CLK_FREQ;
////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// Data Counter /////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// symbol & interpolation counter
reg [$clog2(INTERP*BIT_DATA_LEN)-1 : 0] cnt = 'b0;
always @(posedge clk) begin
if (rst) begin
cnt <= 'b0;
end
else begin
cnt <= (cnt == INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1;
end
end
////////////////////////////////////////////////////////////////////////////////
////////////////////// Root-Rasied Cosine Shaping Filter ///////////////////////
////////////////////////////////////////////////////////////////////////////////
// address
reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_i = 'b0;
reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_q = 'b1;
always @(posedge clk) begin
if (rst) begin
hrc_data_addr_i <= 'b0;
hrc_data_addr_q <= 'b1;
end
else begin
hrc_data_addr_i <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b0};
hrc_data_addr_q <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b1};
end
end
// bit data
reg hrc_data_i = 'b0;
reg hrc_data_q = 'b0;
always @(posedge clk) begin
if (rst) begin
hrc_data_i <= 'b0;
hrc_data_q <= 'b0;
end
else begin
hrc_data_i <= BIT_DATA[hrc_data_addr_i];
hrc_data_q <= BIT_DATA[hrc_data_addr_q];
end
end
// polarization
wire [ 7:0] hrc_data_polar_i;
wire [ 7:0] hrc_data_polar_q;
assign hrc_data_polar_i = {{7{hrc_data_i}},1'b1};
assign hrc_data_polar_q = {{7{hrc_data_q}},1'b1};
// root raised cosine shaping-filter
wire [23:0] hrc_wave_i;
wire [23:0] hrc_wave_q;
hrc_64_12_025 u_hrc_i (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_i ) // output wire [23 : 0] m_axis_data_tdata
);
hrc_64_12_025 u_hrc_q (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_q ) // output wire [23 : 0] m_axis_data_tdata
);
////////////////////////////////////////////////////////////////////////////////
//////////////////////////// Square Shaping Filter /////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// address
reg [$clog2(BIT_DATA_LEN)-2 : 0] hsq_data_addr = 'b0;
always @(posedge clk) begin
if (rst) begin
hsq_data_addr <= 'b0;
end
else
hsq_data_addr <= {cnt[$clog2(SQUARE_INTERP) +: ($clog2(BIT_DATA_LEN)-2)]};
end
// bit data
reg hsq_data = 'b0;
always @(posedge clk) begin
if (rst) begin
hsq_data <= 'b0;
end
else begin
hsq_data <= BIT_DATA[hsq_data_addr];
end
end
// square shaping-filter
reg [17:0] hsq_wave_i ='b0;
reg [17:0] hsq_wave_q ='b0;
always @(posedge clk) begin
if (rst) begin
hsq_wave_i <= 'b0;
hsq_wave_q <= 'b0;
end
else begin
hsq_wave_i <= hsq_data ? 18'b01_1111_1111_1111_1111 : 18'b10_0000_0000_0000_0001;
hsq_wave_q <= hsq_data ? 18'b10_0000_0000_0000_0001 : 18'b01_1111_1111_1111_1111;
end
end
////////////////////////////////////////////////////////////////////////////////
/////////////////////////////// Two Tone Siganl ////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// cosine wave with freq of 1 MHz
wire signed [7:0] cos_1m;
wire signed [7:0] sin_1m;
dds_32b_8b u_dds_1m
(
.aclk (clk ), // input wire aclk
.s_axis_config_tvalid (1'b1 ), // input wire s_axis_config_tvalid
.s_axis_config_tdata (FREQ_WORD_1M[31:0] ), // input wire [31 : 0] s_axis_config_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata ({sin_1m,cos_1m} ) // output wire [15 : 0] m_axis_data_tdata
);
// two-tone signal
reg signed [16:0] two_tone_wave_i = 'b0;
reg signed [16:0] two_tone_wave_q = 'b0;
always @(posedge clk) begin
if (rst) begin
two_tone_wave_i <= 'b0;
two_tone_wave_q <= 'b0;
end
else begin
two_tone_wave_i <= 17'b0_0111_1111_1111_1111 + {cos_1m[7],cos_1m,8'd0};
two_tone_wave_q <= 17'b0 + {sin_1m[7],sin_1m,8'd0};
end
end
////////////////////////////////////////////////////////////////////////////////
///////////////////// Waveform Selection & Hopping Control /////////////////////
////////////////////////////////////////////////////////////////////////////////
// baseband signal select
reg [17:0] baseband_sel_i = 'b0;
reg [17:0] baseband_sel_q = 'b0;
always @(posedge clk) begin
if (rst) begin
baseband_sel_i <= 'b0;
baseband_sel_q <= 'b0;
end
else begin
case (waveform_sel[1:0])
2'd0: begin
baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
end
2'd1: begin
baseband_sel_i <= hsq_wave_i[17:0];
baseband_sel_q <= hsq_wave_q[17:0];
end
2'd2: begin
baseband_sel_i <= 18'b01_1111_1111_1111_1111;
baseband_sel_q <= 18'b0;
end
2'd3: begin
baseband_sel_i <= {two_tone_wave_i[16:0],1'b0};
baseband_sel_q <= {two_tone_wave_q[16:0],1'b0};
end
default: begin
baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
end
endcase
end
end
// hopping control, 3750hop/s
reg [23:0] sweep_rom_addr = 'b0;
wire [31:0] freq_sweep;
always @(posedge clk) begin
if (rst) begin
sweep_rom_addr <= 'b0;
end
else if (sweep_on) begin
sweep_rom_addr <= sweep_rom_addr + 24'b1;
end
else begin
sweep_rom_addr <= 'b0;
end
end
hop_rom u_sweep_rom
(
.clka (clk ), // input wire clka
.addra (sweep_rom_addr[23:16] ), // input wire [7 : 0] addra
.douta (freq_sweep ) // output wire [31 : 0] douta
);
// choose the actual frequency word
reg [31:0] freq_word = 'b0;
always @(posedge clk) begin
if (rst) begin
freq_word <= 'b0;
end
else if (sweep_on) begin
// frequency sweep
freq_word <= freq_sweep;
end
else begin
// normal operation
freq_word <= freq_set;
end
end
// baseband frequency shift carrier generation
wire [ 7:0] cos_dds;
wire [ 7:0] sin_dds;
reg [ 7:0] cos = 'b0;
reg [ 7:0] sin = 'b0;
dds_32b_8b u_dds_bb_shift (
.aclk (clk ), // input wire aclk
.s_axis_config_tvalid (~rst ), // input wire s_axis_config_tvalid
.s_axis_config_tdata (freq_word ), // input wire [31 : 0] s_axis_config_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata ({sin_dds,cos_dds}) // output wire [31 : 0] m_axis_data_tdata
);
always @(posedge clk) begin
if (rst) begin
cos <= 'b0;
sin <= 'b0;
end
else if (freq_word == 'b0) begin
// to make sure the carriers stay at the right position when freq = 0
cos <= 8'b0111_1111;
sin <= 8'b0111_1111;
end
else begin
cos <= cos_dds;
sin <= sin_dds;
end
end
// baseband frequency shift modulation
wire [47:0] mod_cmpy_a;
wire [15:0] mod_cmpy_b;
wire [63:0] mod_cmpy_out;
wire [26:0] baseband_mult_i;
wire [26:0] baseband_mult_q;
assign mod_cmpy_a = {6'b0,baseband_sel_q,6'b0,baseband_sel_i};
assign mod_cmpy_b = {-sin,cos};
assign baseband_mult_i = mod_cmpy_out[58:32];
assign baseband_mult_q = mod_cmpy_out[26: 0];
cmpy_18x8 u_cmpy_18x8
(
.aclk (clk ), // input wire aclk
.s_axis_a_tvalid (1'b1 ), // input wire s_axis_a_tvalid
.s_axis_a_tdata (mod_cmpy_a ), // input wire [47 : 0] s_axis_a_tdata
.s_axis_b_tvalid (1'b1 ), // input wire s_axis_b_tvalid
.s_axis_b_tdata (mod_cmpy_b ), // input wire [15 : 0] s_axis_b_tdata
.m_axis_dout_tvalid ( ), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata (mod_cmpy_out ) // output wire [63 : 0] m_axis_dout_tdata
);
// truncate to 16-bit
reg signed [15:0] baseband_i = 'b0;
reg signed [15:0] baseband_q = 'b0;
always @(posedge clk) begin
if (rst) begin
baseband_i <= 'b0;
baseband_q <= 'b0;
end
else begin
case (waveform_sel[1:0])
2'd0: begin
// scale rasied-cosine-shaped bpsk signal by 1.125 or 1.625
baseband_i <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_i[17 -: 16] + {{3{baseband_sel_i[17]}},baseband_sel_i[17 -: 13]}) : (baseband_mult_i[25:10] + {baseband_mult_i[25],baseband_mult_i[25:11]} + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]});
baseband_q <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_q[17 -: 16] + {{3{baseband_sel_q[17]}},baseband_sel_q[17 -: 13]}) : (baseband_mult_q[25:10] + {baseband_mult_q[25],baseband_mult_q[25:11]} + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]});
end
2'd1: begin
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : (baseband_mult_i[25:10] + {{2{baseband_mult_i[25]}},baseband_mult_i[25:12]});
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : (baseband_mult_q[25:10] + {{2{baseband_mult_q[25]}},baseband_mult_q[25:12]});
end
2'd2: begin
baseband_i <= baseband_mult_i[24:9];
baseband_q <= baseband_mult_q[24:9];
end
2'd3: begin
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[24:9];
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[24:9];
end
default: begin
// scale rasied-cosine-shaped bpsk signal by 1.125
baseband_i <= baseband_mult_i[25:10] + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]};
baseband_q <= baseband_mult_q[25:10] + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]};
end
endcase
end
end
// iq selection & baseband right shift
reg signed [15:0] baseband_data_i = 'b0;
reg signed [15:0] baseband_data_q = 'b0;
always @(posedge clk) begin
if (rst) begin
baseband_data_i <= 'b0;
baseband_data_q <= 'b0;
end
else begin
// inphase selection
if (iq_sel[1]) begin
baseband_data_i <= baseband_i >>> bb_rshift;
end
else begin
baseband_data_i <= 'b0;
end
// quadrature selection
if (iq_sel[0]) begin
baseband_data_q <= baseband_q >>> bb_rshift;
end
else begin
baseband_data_q <= 'b0;
end
end
end
// output data to ports
assign tx_data_i = baseband_data_i[15 -: DATA_WIDTH];
assign tx_data_q = baseband_data_q[15 -: DATA_WIDTH];
endmodule