Archived
add dl817_k7_beam
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# smq7k410t_b9361
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## Timing Assertions Section
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## Physical Constraints Section
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# Clocks
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set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS33} [get_ports clk_25m ] ;# CLK_25M
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set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25 } [get_ports clk_250m_p ] ;# CLK_250M_P
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set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_buffer_clk ] ;# B9361_1_CLK_OUT
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set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_buffer_clk ] ;# B9361_2_CLK_OUT
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# HMC7044-1 Interface
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set_property -dict {PACKAGE_PIN J23 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_clk ] ;# GM4526C_SPI_SCLK
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set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_csn ] ;# GM4526C_SPI_CSB
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set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_mosi ] ;# GM4526C_SPI_SDIO
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set_property -dict {PACKAGE_PIN K23 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_miso ] ;# GM4526C_SPI_SDO
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set_property -dict {PACKAGE_PIN L23 IOSTANDARD LVCMOS33} [get_ports ad9516_refmon ] ;# GM4526C_REFMON
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set_property -dict {PACKAGE_PIN K24 IOSTANDARD LVCMOS33} [get_ports ad9516_ld ] ;# GM4526C_LD
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set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS33} [get_ports ad9516_status ] ;# GM4526C_STATUS
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set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS33} [get_ports ad9516_pd_b ] ;# GM4526C_PDB
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set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS33} [get_ports ad9516_reset_b ] ;# GM4526C_RESETB
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set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS33} [get_ports ad9516_sync_b ] ;# GM4526C_SYNCB
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# AD9361-1 Interface
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set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data_clk ] ;# B9361_1_DATA_CLK
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set_property -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_frame ] ;# B9361_1_RX_FRAME
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set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[0] ] ;# B9361_1_P0_00_TX0_N
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set_property -dict {PACKAGE_PIN B23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[1] ] ;# B9361_1_P0_01_TX0_P
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set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[2] ] ;# B9361_1_P0_02_TX1_N
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set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[3] ] ;# B9361_1_P0_03_TX1_P
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set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[4] ] ;# B9361_1_P0_04_TX2_N
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set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[5] ] ;# B9361_1_P0_05_TX2_P
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set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[6] ] ;# B9361_1_P0_06_TX3_N
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set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[7] ] ;# B9361_1_P0_07_TX3_P
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set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[8] ] ;# B9361_1_P0_08_TX4_N
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set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[9] ] ;# B9361_1_P0_09_TX4_P
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set_property -dict {PACKAGE_PIN G24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[10] ] ;# B9361_1_P0_10_TX5_N
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set_property -dict {PACKAGE_PIN G23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[11] ] ;# B9361_1_P0_11_TX5_P
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set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_fb_clk ] ;# B9361_1_FB_CLK
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set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_frame ] ;# B9361_1_TX_FRAME
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set_property -dict {PACKAGE_PIN E30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[0] ] ;# B9361_1_P1_00_RX0_N
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set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[1] ] ;# B9361_1_P1_01_RX0_P
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set_property -dict {PACKAGE_PIN C30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[2] ] ;# B9361_1_P1_02_RX1_N
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set_property -dict {PACKAGE_PIN D29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[3] ] ;# B9361_1_P1_03_RX1_P
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set_property -dict {PACKAGE_PIN A30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[4] ] ;# B9361_1_P1_04_RX2_N
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set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[5] ] ;# B9361_1_P1_05_RX2_P
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set_property -dict {PACKAGE_PIN B29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[6] ] ;# B9361_1_P1_06_RX3_N
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set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[7] ] ;# B9361_1_P1_07_RX3_P
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set_property -dict {PACKAGE_PIN F28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[8] ] ;# B9361_1_P1_08_RX4_N
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set_property -dict {PACKAGE_PIN G28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[9] ] ;# B9361_1_P1_09_RX4_P
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set_property -dict {PACKAGE_PIN H25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[10] ] ;# B9361_1_P1_10_RX5_N
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set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[11] ] ;# B9361_1_P1_11_RX5_P
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set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_clk ] ;# B9361_1_SPI_CLK
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set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_csn ] ;# B9361_1_SPI_ENB
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set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_mosi ] ;# B9361_1_SPI_DI
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set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_miso ] ;# B9361_1_SPI_DO
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set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_reset_b ] ;# B9361_1_RESETB
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set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_en_agc ] ;# B9361_1_EN_AGC
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set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_enable ] ;# B9361_1_ENABLE
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set_property -dict {PACKAGE_PIN A27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_txnrx ] ;# B9361_1_TXNRX
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set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[0] ] ;# B9361_1_CTRL_IN0
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set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[1] ] ;# B9361_1_CTRL_IN1
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set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[2] ] ;# B9361_1_CTRL_IN2
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set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[3] ] ;# B9361_1_CTRL_IN3
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set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[0] ] ;# B9361_1_CTRL_OUT0
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set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[1] ] ;# B9361_1_CTRL_OUT1
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set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[2] ] ;# B9361_1_CTRL_OUT2
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set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[3] ] ;# B9361_1_CTRL_OUT3
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set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[4] ] ;# B9361_1_CTRL_OUT4
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set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[5] ] ;# B9361_1_CTRL_OUT5
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set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[6] ] ;# B9361_1_CTRL_OUT6
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set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[7] ] ;# B9361_1_CTRL_OUT7
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set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS18} [get_ports ad9361_sync ] ;# B9361_SYNC
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# AD9361-2 Interface
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set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data_clk ] ;# B9361_2_DATA_CLK
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set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_frame ] ;# B9361_2_RX_FRAME
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set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[0] ] ;# B9361_2_P0_00_TX0_N
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set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[1] ] ;# B9361_2_P0_01_TX0_P
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set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[2] ] ;# B9361_2_P0_02_TX1_N
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set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[3] ] ;# B9361_2_P0_03_TX1_P
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set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[4] ] ;# B9361_2_P0_04_TX2_N
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set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[5] ] ;# B9361_2_P0_05_TX2_P
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set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[6] ] ;# B9361_2_P0_06_TX3_N
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set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[7] ] ;# B9361_2_P0_07_TX3_P
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set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[8] ] ;# B9361_2_P0_08_TX4_N
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set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[9] ] ;# B9361_2_P0_09_TX4_P
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set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[10] ] ;# B9361_2_P0_10_TX5_N
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set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[11] ] ;# B9361_2_P0_11_TX5_P
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set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_fb_clk ] ;# B9361_2_FB_CLK
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set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_frame ] ;# B9361_2_TX_FRAME
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set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[0] ] ;# B9361_2_P1_00_RX0_N
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set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[1] ] ;# B9361_2_P1_01_RX0_P
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set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[2] ] ;# B9361_2_P1_02_RX1_N
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set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[3] ] ;# B9361_2_P1_03_RX1_P
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set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[4] ] ;# B9361_2_P1_04_RX2_N
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set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[5] ] ;# B9361_2_P1_05_RX2_P
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set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[6] ] ;# B9361_2_P1_06_RX3_N
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set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[7] ] ;# B9361_2_P1_07_RX3_P
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set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[8] ] ;# B9361_2_P1_08_RX4_N
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set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[9] ] ;# B9361_2_P1_09_RX4_P
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set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[10] ] ;# B9361_2_P1_10_RX5_N
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set_property -dict {PACKAGE_PIN F11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[11] ] ;# B9361_2_P1_11_RX5_P
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set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_clk ] ;# B9361_2_SPI_CLK
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set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_csn ] ;# B9361_2_SPI_ENB
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set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_mosi ] ;# B9361_2_SPI_DI
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set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_miso ] ;# B9361_2_SPI_DO
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set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_reset_b ] ;# B9361_2_RESETB
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set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS18} [get_ports ad9361_2_en_agc ] ;# B9361_2_EN_AGC
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set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports ad9361_2_enable ] ;# B9361_2_ENABLE
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set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_txnrx ] ;# B9361_2_TXNRX
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set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[0] ] ;# B9361_2_CTRL_IN0
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set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[1] ] ;# B9361_2_CTRL_IN1
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set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[2] ] ;# B9361_2_CTRL_IN2
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set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[3] ] ;# B9361_2_CTRL_IN3
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set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[0] ] ;# B9361_2_CTRL_OUT0
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set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[1] ] ;# B9361_2_CTRL_OUT1
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set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[2] ] ;# B9361_2_CTRL_OUT2
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set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[3] ] ;# B9361_2_CTRL_OUT3
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set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[4] ] ;# B9361_2_CTRL_OUT4
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set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[5] ] ;# B9361_2_CTRL_OUT5
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set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[6] ] ;# B9361_2_CTRL_OUT6
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set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[7] ] ;# B9361_2_CTRL_OUT7
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# Phased-Array Control
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set_property -dict {PACKAGE_PIN T26 IOSTANDARD LVTTL } [get_ports ant_cin ] ;# ANT_CIN0
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set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVTTL } [get_ports ant_din0 ] ;# ANT_DIN0
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set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVTTL } [get_ports ant_din1 ] ;# ANT_DIN1
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set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVTTL } [get_ports ant_cout ] ;# ANT_COUT0
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set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVTTL } [get_ports ant_dout0 ] ;# ANT_DOUT0
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set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVTTL } [get_ports ant_dout1 ] ;# ANT_DOUT1
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set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVTTL } [get_ports ant_tr ] ;# ANT_TR_IN
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set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVTTL } [get_ports ant_dary ] ;# ANT_DARY_IN
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# RF Synthesizer Control
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set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVTTL } [get_ports rf_standby ] ;# RF_STANDBY
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set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVTTL } [get_ports rf_sw_pll ] ;# RF_SW_PLL
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set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVTTL } [get_ports rf_t ] ;# RF_T
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set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVTTL } [get_ports rf_r ] ;# RF_R
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set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVTTL } [get_ports rf_sw_bpf ] ;# RF_SW_BPF
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set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVTTL } [get_ports rf_sclk1 ] ;# RF_SCLK1
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set_property -dict {PACKAGE_PIN AA26 IOSTANDARD LVTTL } [get_ports rf_sdio1 ] ;# RF_SDIO1
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set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVTTL } [get_ports rf_cs1 ] ;# RF_CS1
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set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVTTL } [get_ports rf_ld1 ] ;# RF_LD1
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set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVTTL } [get_ports rf_sclk2 ] ;# RF_SCLK2
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set_property -dict {PACKAGE_PIN AD27 IOSTANDARD LVTTL } [get_ports rf_sdio2 ] ;# RF_SDIO2
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set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVTTL } [get_ports rf_cs2 ] ;# RF_CS2
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set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVTTL } [get_ports rf_ld2 ] ;# RF_LD2
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set_property -dict {PACKAGE_PIN AC30 IOSTANDARD LVTTL } [get_ports rf_sclk3 ] ;# RF_SCLK3
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set_property -dict {PACKAGE_PIN AE29 IOSTANDARD LVTTL } [get_ports rf_sdio3 ] ;# RF_SDIO3
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set_property -dict {PACKAGE_PIN AB28 IOSTANDARD LVTTL } [get_ports rf_cs3 ] ;# RF_CS3
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set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVTTL } [get_ports rf_ld3 ] ;# RF_LD3
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set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVTTL } [get_ports rf_tmgc_16 ] ;# RF_TMGC_16
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set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVTTL } [get_ports rf_tmgc_8 ] ;# RF_TMGC_8
|
||||
set_property -dict {PACKAGE_PIN AA27 IOSTANDARD LVTTL } [get_ports rf_tmgc_4 ] ;# RF_TMGC_4
|
||||
set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVTTL } [get_ports rf_tmgc_2 ] ;# RF_TMGC_2
|
||||
set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVTTL } [get_ports rf_tmgc_1 ] ;# RF_TMGC_1
|
||||
set_property -dict {PACKAGE_PIN AA28 IOSTANDARD LVTTL } [get_ports rf_rmgc_16 ] ;# RF_RMGC_16
|
||||
set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVTTL } [get_ports rf_rmgc_8 ] ;# RF_RMGC_8
|
||||
set_property -dict {PACKAGE_PIN Y29 IOSTANDARD LVTTL } [get_ports rf_rmgc_4 ] ;# RF_RMGC_4
|
||||
set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVTTL } [get_ports rf_rmgc_2 ] ;# RF_RMGC_2
|
||||
set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVTTL } [get_ports rf_rmgc_1 ] ;# RF_RMGC_1
|
||||
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVTTL } [get_ports rf_enable ] ;# RF_ENABLE
|
||||
set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVTTL } [get_ports rf_sc ] ;# RF_SC
|
||||
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVTTL } [get_ports rf_sd ] ;# RF_SD
|
||||
set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVTTL } [get_ports rf_endsyn ] ;# RF_END_SYN
|
||||
set_property -dict {PACKAGE_PIN W27 IOSTANDARD LVTTL } [get_ports rf_sdout ] ;# RF_SDOUT
|
||||
set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVTTL } [get_ports rf_dq_wd ] ;# RF_DQ_WD
|
||||
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVTTL } [get_ports rf_sw_rx ] ;# RF_SW_RX
|
||||
|
||||
# LVDS for Time Synchronization
|
||||
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS33} [get_ports lvds_in_1 ] ;# LVDS_IN1
|
||||
set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS33} [get_ports lvds_out_1 ] ;# LVDS_OUT1
|
||||
|
||||
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports lvds_in_2 ] ;# LVDS_IN2
|
||||
set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS33} [get_ports lvds_out_2 ] ;# LVDS_OUT2
|
||||
|
||||
# Debug IO
|
||||
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports uart1_txd ] ;# UART_1_TXD
|
||||
set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports uart1_rxd ] ;# UART_1_RXD
|
||||
set_property -dict {PACKAGE_PIN U23 IOSTANDARD LVCMOS33} [get_ports uart2_txd ] ;# UART_2_TXD
|
||||
set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports uart2_rxd ] ;# UART_2_RXD
|
||||
set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS33} [get_ports uart3_txd ] ;# UART_3_TXD
|
||||
set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS33} [get_ports uart3_rxd ] ;# UART_3_RXD
|
||||
|
||||
set_property -dict {PACKAGE_PIN V25 IOSTANDARD LVCMOS33} [get_ports debug_io_1 ] ;# DEBUG_IO_1
|
||||
set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports debug_io_2 ] ;# DEBUG_IO_2
|
||||
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# DEBUG_IO_3
|
||||
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# DEBUG_IO_4
|
||||
set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# DEBUG_IO_5
|
||||
set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports debug_io_6 ] ;# DEBUG_IO_6
|
||||
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS33} [get_ports debug_io_7 ] ;# DEBUG_IO_7
|
||||
set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports debug_io_8 ] ;# DEBUG_IO_8
|
||||
|
||||
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVDS_25 } [get_ports debug_io_00_p ] ;# DEBUG_IO_00_P
|
||||
set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVDS_25 } [get_ports debug_io_01_p ] ;# DEBUG_IO_01_P
|
||||
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVDS_25 } [get_ports debug_io_02_p ] ;# DEBUG_IO_02_P
|
||||
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS_25 } [get_ports debug_io_03_p ] ;# DEBUG_IO_03_P
|
||||
set_property -dict {PACKAGE_PIN AC20 IOSTANDARD LVDS_25 } [get_ports debug_io_04_p ] ;# DEBUG_IO_04_P
|
||||
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 } [get_ports debug_io_05_p ] ;# DEBUG_IO_05_P
|
||||
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVDS_25 } [get_ports debug_io_06_p ] ;# DEBUG_IO_06_P
|
||||
set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVDS_25 } [get_ports debug_io_07_p ] ;# DEBUG_IO_07_P
|
||||
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVDS_25 } [get_ports debug_io_08_p ] ;# DEBUG_IO_08_P
|
||||
|
||||
# FLASH
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
@@ -0,0 +1,4 @@
|
||||
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[8]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_recal_d1_reg/D]
|
||||
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[10]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_1_cal_start_d1_reg/D]
|
||||
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[7]/C}] -to [get_pins u_tx_pre_process/ad9361_tx_switch_d1_reg/D]
|
||||
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[9]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_2_cal_start_d1_reg/D]
|
||||
Binary file not shown.
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@@ -0,0 +1,20 @@
|
||||
Radix=10;
|
||||
Coefficient_Width=16;
|
||||
CoefData=
|
||||
3
|
||||
19
|
||||
97
|
||||
366
|
||||
1052
|
||||
2321
|
||||
3999
|
||||
5485
|
||||
6082
|
||||
5485
|
||||
3999
|
||||
2321
|
||||
1052
|
||||
366
|
||||
97
|
||||
19
|
||||
3
|
||||
@@ -0,0 +1,132 @@
|
||||
Radix=10;
|
||||
Coefficient_Width=16;
|
||||
CoefData=
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
2
|
||||
2
|
||||
2
|
||||
3
|
||||
4
|
||||
5
|
||||
6
|
||||
7
|
||||
8
|
||||
10
|
||||
12
|
||||
14
|
||||
17
|
||||
21
|
||||
24
|
||||
29
|
||||
34
|
||||
39
|
||||
46
|
||||
53
|
||||
61
|
||||
70
|
||||
80
|
||||
91
|
||||
104
|
||||
117
|
||||
132
|
||||
147
|
||||
164
|
||||
182
|
||||
202
|
||||
222
|
||||
244
|
||||
267
|
||||
290
|
||||
315
|
||||
340
|
||||
366
|
||||
392
|
||||
419
|
||||
446
|
||||
473
|
||||
500
|
||||
526
|
||||
552
|
||||
577
|
||||
602
|
||||
625
|
||||
647
|
||||
667
|
||||
686
|
||||
702
|
||||
717
|
||||
730
|
||||
741
|
||||
749
|
||||
755
|
||||
759
|
||||
760
|
||||
759
|
||||
755
|
||||
749
|
||||
741
|
||||
730
|
||||
717
|
||||
702
|
||||
686
|
||||
667
|
||||
647
|
||||
625
|
||||
602
|
||||
577
|
||||
552
|
||||
526
|
||||
500
|
||||
473
|
||||
446
|
||||
419
|
||||
392
|
||||
366
|
||||
340
|
||||
315
|
||||
290
|
||||
267
|
||||
244
|
||||
222
|
||||
202
|
||||
182
|
||||
164
|
||||
147
|
||||
132
|
||||
117
|
||||
104
|
||||
91
|
||||
80
|
||||
70
|
||||
61
|
||||
53
|
||||
46
|
||||
39
|
||||
34
|
||||
29
|
||||
24
|
||||
21
|
||||
17
|
||||
14
|
||||
12
|
||||
10
|
||||
8
|
||||
7
|
||||
6
|
||||
5
|
||||
4
|
||||
3
|
||||
2
|
||||
2
|
||||
2
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@@ -0,0 +1,77 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module ad_rst (
|
||||
|
||||
// clock reset
|
||||
|
||||
input rst_async,
|
||||
input clk,
|
||||
output rstn,
|
||||
output reg rst);
|
||||
|
||||
// internal registers
|
||||
reg rst_async_d1 = 1'd1;
|
||||
reg rst_async_d2 = 1'd1;
|
||||
reg rst_sync = 1'd1;
|
||||
reg rst_sync_d = 1'd1;
|
||||
|
||||
// simple reset synchronizer
|
||||
always @(posedge clk or posedge rst_async) begin
|
||||
if (rst_async) begin
|
||||
rst_async_d1 <= 1'b1;
|
||||
rst_async_d2 <= 1'b1;
|
||||
rst_sync <= 1'b1;
|
||||
end else begin
|
||||
rst_async_d1 <= 1'b0;
|
||||
rst_async_d2 <= rst_async_d1;
|
||||
rst_sync <= rst_async_d2;
|
||||
end
|
||||
end
|
||||
|
||||
// two-stage synchronizer to prevent metastability on the falling edge
|
||||
always @(posedge clk) begin
|
||||
rst_sync_d <= rst_sync;
|
||||
rst <= rst_sync_d;
|
||||
end
|
||||
|
||||
assign rstn = ~rst;
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,239 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module up_axi #(
|
||||
|
||||
parameter AXI_ADDRESS_WIDTH = 16) (
|
||||
|
||||
// reset and clocks
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
|
||||
// axi4 interface
|
||||
|
||||
input up_axi_awvalid,
|
||||
input [(AXI_ADDRESS_WIDTH-1):0] up_axi_awaddr,
|
||||
output up_axi_awready,
|
||||
input up_axi_wvalid,
|
||||
input [31:0] up_axi_wdata,
|
||||
input [ 3:0] up_axi_wstrb,
|
||||
output up_axi_wready,
|
||||
output up_axi_bvalid,
|
||||
output [ 1:0] up_axi_bresp,
|
||||
input up_axi_bready,
|
||||
input up_axi_arvalid,
|
||||
input [(AXI_ADDRESS_WIDTH-1):0] up_axi_araddr,
|
||||
output up_axi_arready,
|
||||
output up_axi_rvalid,
|
||||
output [ 1:0] up_axi_rresp,
|
||||
output [31:0] up_axi_rdata,
|
||||
input up_axi_rready,
|
||||
|
||||
// pcore interface
|
||||
|
||||
output up_wreq,
|
||||
output [(AXI_ADDRESS_WIDTH-3):0] up_waddr,
|
||||
output [31:0] up_wdata,
|
||||
input up_wack,
|
||||
output up_rreq,
|
||||
output [(AXI_ADDRESS_WIDTH-3):0] up_raddr,
|
||||
input [31:0] up_rdata,
|
||||
input up_rack);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg up_axi_awready_int = 'd0;
|
||||
reg up_axi_wready_int = 'd0;
|
||||
reg up_axi_bvalid_int = 'd0;
|
||||
reg up_wack_d = 'd0;
|
||||
reg up_wsel = 'd0;
|
||||
reg up_wreq_int = 'd0;
|
||||
reg [(AXI_ADDRESS_WIDTH-3):0] up_waddr_int = 'd0;
|
||||
reg [31:0] up_wdata_int = 'd0;
|
||||
reg [ 4:0] up_wcount = 'd0;
|
||||
reg up_axi_arready_int = 'd0;
|
||||
reg up_axi_rvalid_int = 'd0;
|
||||
reg [31:0] up_axi_rdata_int = 'd0;
|
||||
reg up_rack_d = 'd0;
|
||||
reg [31:0] up_rdata_d = 'd0;
|
||||
reg up_rsel = 'd0;
|
||||
reg up_rreq_int = 'd0;
|
||||
reg [(AXI_ADDRESS_WIDTH-3):0] up_raddr_int = 'd0;
|
||||
reg [ 4:0] up_rcount = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire up_wack_s;
|
||||
wire up_rack_s;
|
||||
wire [31:0] up_rdata_s;
|
||||
|
||||
// write channel interface
|
||||
|
||||
assign up_axi_awready = up_axi_awready_int;
|
||||
assign up_axi_wready = up_axi_wready_int;
|
||||
assign up_axi_bvalid = up_axi_bvalid_int;
|
||||
assign up_axi_bresp = 2'd0;
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_axi_awready_int <= 'd0;
|
||||
up_axi_wready_int <= 'd0;
|
||||
up_axi_bvalid_int <= 'd0;
|
||||
end else begin
|
||||
if (up_axi_awready_int == 1'b1) begin
|
||||
up_axi_awready_int <= 1'b0;
|
||||
end else if (up_wack_s == 1'b1) begin
|
||||
up_axi_awready_int <= 1'b1;
|
||||
end
|
||||
if (up_axi_wready_int == 1'b1) begin
|
||||
up_axi_wready_int <= 1'b0;
|
||||
end else if (up_wack_s == 1'b1) begin
|
||||
up_axi_wready_int <= 1'b1;
|
||||
end
|
||||
if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin
|
||||
up_axi_bvalid_int <= 1'b0;
|
||||
end else if (up_wack_d == 1'b1) begin
|
||||
up_axi_bvalid_int <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign up_wreq = up_wreq_int;
|
||||
assign up_waddr = up_waddr_int;
|
||||
assign up_wdata = up_wdata_int;
|
||||
assign up_wack_s = (up_wcount == 5'h1f) ? 1'b1 : (up_wcount[4] & up_wack);
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_wack_d <= 'd0;
|
||||
up_wsel <= 'd0;
|
||||
up_wreq_int <= 'd0;
|
||||
up_waddr_int <= 'd0;
|
||||
up_wdata_int <= 'd0;
|
||||
up_wcount <= 'd0;
|
||||
end else begin
|
||||
up_wack_d <= up_wack_s;
|
||||
if (up_wsel == 1'b1) begin
|
||||
if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin
|
||||
up_wsel <= 1'b0;
|
||||
end
|
||||
up_wreq_int <= 1'b0;
|
||||
end else begin
|
||||
up_wsel <= up_axi_awvalid & up_axi_wvalid;
|
||||
up_wreq_int <= up_axi_awvalid & up_axi_wvalid;
|
||||
up_waddr_int <= up_axi_awaddr[(AXI_ADDRESS_WIDTH-1):2];
|
||||
up_wdata_int <= up_axi_wdata;
|
||||
end
|
||||
if (up_wack_s == 1'b1) begin
|
||||
up_wcount <= 5'h00;
|
||||
end else if (up_wcount[4] == 1'b1) begin
|
||||
up_wcount <= up_wcount + 1'b1;
|
||||
end else if (up_wreq_int == 1'b1) begin
|
||||
up_wcount <= 5'h10;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// read channel interface
|
||||
|
||||
assign up_axi_arready = up_axi_arready_int;
|
||||
assign up_axi_rvalid = up_axi_rvalid_int;
|
||||
assign up_axi_rdata = up_axi_rdata_int;
|
||||
assign up_axi_rresp = 2'd0;
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_axi_arready_int <= 'd0;
|
||||
up_axi_rvalid_int <= 'd0;
|
||||
up_axi_rdata_int <= 'd0;
|
||||
end else begin
|
||||
if (up_axi_arready_int == 1'b1) begin
|
||||
up_axi_arready_int <= 1'b0;
|
||||
end else if (up_rack_s == 1'b1) begin
|
||||
up_axi_arready_int <= 1'b1;
|
||||
end
|
||||
if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin
|
||||
up_axi_rvalid_int <= 1'b0;
|
||||
up_axi_rdata_int <= 32'd0;
|
||||
end else if (up_rack_d == 1'b1) begin
|
||||
up_axi_rvalid_int <= 1'b1;
|
||||
up_axi_rdata_int <= up_rdata_d;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign up_rreq = up_rreq_int;
|
||||
assign up_raddr = up_raddr_int;
|
||||
assign up_rack_s = (up_rcount == 5'h1f) ? 1'b1 : (up_rcount[4] & up_rack);
|
||||
assign up_rdata_s = (up_rcount == 5'h1f) ? {2{16'hdead}} : up_rdata;
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_rack_d <= 'd0;
|
||||
up_rdata_d <= 'd0;
|
||||
up_rsel <= 'd0;
|
||||
up_rreq_int <= 'd0;
|
||||
up_raddr_int <= 'd0;
|
||||
up_rcount <= 'd0;
|
||||
end else begin
|
||||
up_rack_d <= up_rack_s;
|
||||
up_rdata_d <= up_rdata_s;
|
||||
if (up_rsel == 1'b1) begin
|
||||
if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin
|
||||
up_rsel <= 1'b0;
|
||||
end
|
||||
up_rreq_int <= 1'b0;
|
||||
end else begin
|
||||
up_rsel <= up_axi_arvalid;
|
||||
up_rreq_int <= up_axi_arvalid;
|
||||
up_raddr_int <= up_axi_araddr[(AXI_ADDRESS_WIDTH-1):2];
|
||||
end
|
||||
if (up_rack_s == 1'b1) begin
|
||||
up_rcount <= 5'h00;
|
||||
end else if (up_rcount[4] == 1'b1) begin
|
||||
up_rcount <= up_rcount + 1'b1;
|
||||
end else if (up_rreq_int == 1'b1) begin
|
||||
up_rcount <= 5'h10;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,60 @@
|
||||
//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
//Date : Sun Mar 19 00:32:52 2023
|
||||
//Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
//Command : generate_target system_bd_wrapper.bd
|
||||
//Design : system_bd_wrapper
|
||||
//Purpose : IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module system_bd_wrapper
|
||||
(clk_25MHz,
|
||||
gpio_i,
|
||||
gpio_o,
|
||||
ps_clk_25M,
|
||||
spi_active,
|
||||
spi_cs,
|
||||
spi_sclk,
|
||||
spi_sdi,
|
||||
spi_sdo,
|
||||
spi_sdo_t,
|
||||
spi_three_wire);
|
||||
input clk_25MHz;
|
||||
input [31:0]gpio_i;
|
||||
output [31:0]gpio_o;
|
||||
output ps_clk_25M;
|
||||
output spi_active;
|
||||
output [2:0]spi_cs;
|
||||
output spi_sclk;
|
||||
input [0:0]spi_sdi;
|
||||
output spi_sdo;
|
||||
output spi_sdo_t;
|
||||
output spi_three_wire;
|
||||
|
||||
wire clk_25MHz;
|
||||
wire [31:0]gpio_i;
|
||||
wire [31:0]gpio_o;
|
||||
wire ps_clk_25M;
|
||||
wire spi_active;
|
||||
wire [2:0]spi_cs;
|
||||
wire spi_sclk;
|
||||
wire [0:0]spi_sdi;
|
||||
wire spi_sdo;
|
||||
wire spi_sdo_t;
|
||||
wire spi_three_wire;
|
||||
|
||||
system_bd system_bd_i
|
||||
(.clk_25MHz(clk_25MHz),
|
||||
.gpio_i(gpio_i),
|
||||
.gpio_o(gpio_o),
|
||||
.ps_clk_25M(ps_clk_25M),
|
||||
.spi_active(spi_active),
|
||||
.spi_cs(spi_cs),
|
||||
.spi_sclk(spi_sclk),
|
||||
.spi_sdi(spi_sdi),
|
||||
.spi_sdo(spi_sdo),
|
||||
.spi_sdo_t(spi_sdo_t),
|
||||
.spi_three_wire(spi_three_wire));
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,427 @@
|
||||
|
||||
################################################################
|
||||
# This is a generated script based on design: system_bd
|
||||
#
|
||||
# Though there are limitations about the generated script,
|
||||
# the main purpose of this utility is to make learning
|
||||
# IP Integrator Tcl commands easier.
|
||||
################################################################
|
||||
|
||||
namespace eval _tcl {
|
||||
proc get_script_folder {} {
|
||||
set script_path [file normalize [info script]]
|
||||
set script_folder [file dirname $script_path]
|
||||
return $script_folder
|
||||
}
|
||||
}
|
||||
variable script_folder
|
||||
set script_folder [_tcl::get_script_folder]
|
||||
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2019.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
################################################################
|
||||
# START
|
||||
################################################################
|
||||
|
||||
# To test this script, run the following commands from Vivado Tcl console:
|
||||
# source system_bd_script.tcl
|
||||
|
||||
# If there is no project opened, this script will create a
|
||||
# project, but make sure you do not have an existing project
|
||||
# <./myproj/project_1.xpr> in the current working folder.
|
||||
|
||||
set list_projs [get_projects -quiet]
|
||||
if { $list_projs eq "" } {
|
||||
create_project project_1 myproj -part xc7k410tffg900-2
|
||||
}
|
||||
|
||||
|
||||
# CHANGE DESIGN NAME HERE
|
||||
variable design_name
|
||||
set design_name system_bd
|
||||
|
||||
# This script was generated for a remote BD. To create a non-remote design,
|
||||
# change the variable <run_remote_bd_flow> to <0>.
|
||||
|
||||
set run_remote_bd_flow 1
|
||||
if { $run_remote_bd_flow == 1 } {
|
||||
# Set the reference directory for source file relative paths (by default
|
||||
# the value is script directory path)
|
||||
set origin_dir ./ipi-bds
|
||||
|
||||
# Use origin directory path location variable, if specified in the tcl shell
|
||||
if { [info exists ::origin_dir_loc] } {
|
||||
set origin_dir $::origin_dir_loc
|
||||
}
|
||||
|
||||
set str_bd_folder [file normalize ${origin_dir}]
|
||||
set str_bd_filepath ${str_bd_folder}/${design_name}/${design_name}.bd
|
||||
|
||||
# Check if remote design exists on disk
|
||||
if { [file exists $str_bd_filepath ] == 1 } {
|
||||
catch {common::send_msg_id "BD_TCL-110" "ERROR" "The remote BD file path <$str_bd_filepath> already exists!"}
|
||||
common::send_msg_id "BD_TCL-008" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0>."
|
||||
common::send_msg_id "BD_TCL-009" "INFO" "Also make sure there is no design <$design_name> existing in your current project."
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
# Check if design exists in memory
|
||||
set list_existing_designs [get_bd_designs -quiet $design_name]
|
||||
if { $list_existing_designs ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-111" "ERROR" "The design <$design_name> already exists in this project! Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
|
||||
|
||||
common::send_msg_id "BD_TCL-010" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
# Check if design exists on disk within project
|
||||
set list_existing_designs [get_files -quiet */${design_name}.bd]
|
||||
if { $list_existing_designs ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-112" "ERROR" "The design <$design_name> already exists in this project at location:
|
||||
$list_existing_designs"}
|
||||
catch {common::send_msg_id "BD_TCL-113" "ERROR" "Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
|
||||
|
||||
common::send_msg_id "BD_TCL-011" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
# Now can create the remote BD
|
||||
# NOTE - usage of <-dir> will create <$str_bd_folder/$design_name/$design_name.bd>
|
||||
create_bd_design -dir $str_bd_folder $design_name
|
||||
} else {
|
||||
|
||||
# Create regular design
|
||||
if { [catch {create_bd_design $design_name} errmsg] } {
|
||||
common::send_msg_id "BD_TCL-012" "INFO" "Please set a different value to variable <design_name>."
|
||||
|
||||
return 1
|
||||
}
|
||||
}
|
||||
|
||||
current_bd_design $design_name
|
||||
|
||||
##################################################################
|
||||
# DESIGN PROCs
|
||||
##################################################################
|
||||
|
||||
|
||||
# Hierarchical cell: microblaze_ps_local_memory
|
||||
proc create_hier_cell_microblaze_ps_local_memory { parentCell nameHier } {
|
||||
|
||||
variable script_folder
|
||||
|
||||
if { $parentCell eq "" || $nameHier eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_microblaze_ps_local_memory() - Empty argument(s)!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
# Create cell and set as current instance
|
||||
set hier_obj [create_bd_cell -type hier $nameHier]
|
||||
current_bd_instance $hier_obj
|
||||
|
||||
# Create interface pins
|
||||
create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB
|
||||
|
||||
create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB
|
||||
|
||||
|
||||
# Create pins
|
||||
create_bd_pin -dir I -type clk LMB_Clk
|
||||
create_bd_pin -dir I -type rst SYS_Rst
|
||||
|
||||
# Create instance: dlmb_bram_if_cntlr, and set properties
|
||||
set dlmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_bram_if_cntlr ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_ECC {0} \
|
||||
] $dlmb_bram_if_cntlr
|
||||
|
||||
# Create instance: dlmb_v10, and set properties
|
||||
set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ]
|
||||
|
||||
# Create instance: ilmb_bram_if_cntlr, and set properties
|
||||
set ilmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_bram_if_cntlr ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_ECC {0} \
|
||||
] $ilmb_bram_if_cntlr
|
||||
|
||||
# Create instance: ilmb_v10, and set properties
|
||||
set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ]
|
||||
|
||||
# Create instance: lmb_bram, and set properties
|
||||
set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 lmb_bram ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.Memory_Type {True_Dual_Port_RAM} \
|
||||
CONFIG.use_bram_block {BRAM_Controller} \
|
||||
] $lmb_bram
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net microblaze_ps_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M]
|
||||
connect_bd_intf_net -intf_net microblaze_ps_dlmb_bus [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB] [get_bd_intf_pins dlmb_v10/LMB_Sl_0]
|
||||
connect_bd_intf_net -intf_net microblaze_ps_dlmb_cntlr [get_bd_intf_pins dlmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA]
|
||||
connect_bd_intf_net -intf_net microblaze_ps_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M]
|
||||
connect_bd_intf_net -intf_net microblaze_ps_ilmb_bus [get_bd_intf_pins ilmb_bram_if_cntlr/SLMB] [get_bd_intf_pins ilmb_v10/LMB_Sl_0]
|
||||
connect_bd_intf_net -intf_net microblaze_ps_ilmb_cntlr [get_bd_intf_pins ilmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net SYS_Rst_1 [get_bd_pins SYS_Rst] [get_bd_pins dlmb_bram_if_cntlr/LMB_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_bram_if_cntlr/LMB_Rst] [get_bd_pins ilmb_v10/SYS_Rst]
|
||||
connect_bd_net -net microblaze_ps_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_bram_if_cntlr/LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_bram_if_cntlr/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk]
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
}
|
||||
|
||||
# Hierarchical cell: axi_spi_engine
|
||||
proc create_hier_cell_axi_spi_engine { parentCell nameHier } {
|
||||
|
||||
variable script_folder
|
||||
|
||||
if { $parentCell eq "" || $nameHier eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_axi_spi_engine() - Empty argument(s)!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
# Create cell and set as current instance
|
||||
set hier_obj [create_bd_cell -type hier $nameHier]
|
||||
current_bd_instance $hier_obj
|
||||
|
||||
# Create interface pins
|
||||
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
|
||||
|
||||
create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi
|
||||
|
||||
|
||||
# Create pins
|
||||
create_bd_pin -dir O active
|
||||
create_bd_pin -dir O irq
|
||||
create_bd_pin -dir I -type clk s_axi_aclk
|
||||
create_bd_pin -dir I -type rst s_axi_aresetn
|
||||
create_bd_pin -dir I -type clk spi_clk
|
||||
|
||||
# Create instance: axi_spi_engine, and set properties
|
||||
set axi_spi_engine [ create_bd_cell -type ip -vlnv analog.com:user:axi_spi_engine:1.0 axi_spi_engine ]
|
||||
|
||||
# Create instance: spi_engine_execution, and set properties
|
||||
set spi_engine_execution [ create_bd_cell -type ip -vlnv analog.com:user:spi_engine_execution:1.0 spi_engine_execution ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.NUM_OF_CS {3} \
|
||||
] $spi_engine_execution
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins s_axi] [get_bd_intf_pins axi_spi_engine/s_axi]
|
||||
connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins spi] [get_bd_intf_pins spi_engine_execution/spi]
|
||||
connect_bd_intf_net -intf_net axi_spi_engine_0_spi_engine_ctrl [get_bd_intf_pins axi_spi_engine/spi_engine_ctrl] [get_bd_intf_pins spi_engine_execution/ctrl]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net axi_spi_engine_0_spi_resetn [get_bd_pins axi_spi_engine/spi_resetn] [get_bd_pins spi_engine_execution/resetn]
|
||||
connect_bd_net -net axi_spi_engine_irq [get_bd_pins irq] [get_bd_pins axi_spi_engine/irq]
|
||||
connect_bd_net -net s_axi_aclk_0_1 [get_bd_pins s_axi_aclk] [get_bd_pins axi_spi_engine/s_axi_aclk]
|
||||
connect_bd_net -net s_axi_aresetn_0_1 [get_bd_pins s_axi_aresetn] [get_bd_pins axi_spi_engine/s_axi_aresetn]
|
||||
connect_bd_net -net spi_clk_0_1 [get_bd_pins spi_clk] [get_bd_pins axi_spi_engine/spi_clk] [get_bd_pins spi_engine_execution/clk]
|
||||
connect_bd_net -net spi_engine_execution_active [get_bd_pins active] [get_bd_pins spi_engine_execution/active]
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
}
|
||||
|
||||
|
||||
# Procedure to create entire design; Provide argument to make
|
||||
# procedure reusable. If parentCell is "", will use root.
|
||||
proc create_root_design { parentCell } {
|
||||
|
||||
variable script_folder
|
||||
variable design_name
|
||||
|
||||
if { $parentCell eq "" } {
|
||||
set parentCell [get_bd_cells /]
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
|
||||
# Create interface ports
|
||||
set spi [ create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi ]
|
||||
|
||||
|
||||
# Create ports
|
||||
set clk_25MHz [ create_bd_port -dir I -type clk clk_25MHz ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {25000000} \
|
||||
] $clk_25MHz
|
||||
set gpio_i [ create_bd_port -dir I -from 31 -to 0 gpio_i ]
|
||||
set gpio_o [ create_bd_port -dir O -from 31 -to 0 gpio_o ]
|
||||
set ps_clk_25M [ create_bd_port -dir O -type clk ps_clk_25M ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {25000000} \
|
||||
] $ps_clk_25M
|
||||
set spi_active [ create_bd_port -dir O spi_active ]
|
||||
|
||||
# Create instance: axi_gpio, and set properties
|
||||
set axi_gpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_ALL_INPUTS_2 {1} \
|
||||
CONFIG.C_ALL_OUTPUTS {1} \
|
||||
CONFIG.C_DOUT_DEFAULT {0xFFFFFFFF} \
|
||||
CONFIG.C_INTERRUPT_PRESENT {0} \
|
||||
CONFIG.C_IS_DUAL {1} \
|
||||
] $axi_gpio
|
||||
|
||||
# Create instance: axi_interconnect, and set properties
|
||||
set axi_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.NUM_MI {3} \
|
||||
] $axi_interconnect
|
||||
|
||||
# Create instance: axi_spi_engine
|
||||
create_hier_cell_axi_spi_engine [current_bd_instance .] axi_spi_engine
|
||||
|
||||
# Create instance: clk_wiz_25M, and set properties
|
||||
set clk_wiz_25M [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_25M ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.CLKIN1_JITTER_PS {400.0} \
|
||||
CONFIG.CLKOUT1_JITTER {401.466} \
|
||||
CONFIG.CLKOUT1_PHASE_ERROR {245.713} \
|
||||
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {25} \
|
||||
CONFIG.MMCM_CLKFBOUT_MULT_F {36.500} \
|
||||
CONFIG.MMCM_CLKIN1_PERIOD {40.000} \
|
||||
CONFIG.MMCM_CLKIN2_PERIOD {10.0} \
|
||||
CONFIG.MMCM_CLKOUT0_DIVIDE_F {36.500} \
|
||||
CONFIG.PRIM_IN_FREQ {25} \
|
||||
CONFIG.PRIM_SOURCE {Single_ended_clock_capable_pin} \
|
||||
CONFIG.USE_LOCKED {true} \
|
||||
CONFIG.USE_RESET {false} \
|
||||
] $clk_wiz_25M
|
||||
|
||||
# Create instance: mdm, and set properties
|
||||
set mdm [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm ]
|
||||
|
||||
# Create instance: microblaze_ps, and set properties
|
||||
set microblaze_ps [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:11.0 microblaze_ps ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_DEBUG_ENABLED {1} \
|
||||
CONFIG.C_D_AXI {1} \
|
||||
CONFIG.C_D_LMB {1} \
|
||||
CONFIG.C_I_LMB {1} \
|
||||
] $microblaze_ps
|
||||
|
||||
# Create instance: microblaze_ps_local_memory
|
||||
create_hier_cell_microblaze_ps_local_memory [current_bd_instance .] microblaze_ps_local_memory
|
||||
|
||||
# Create instance: rst_clk_wiz_25M, and set properties
|
||||
set rst_clk_wiz_25M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_clk_wiz_25M ]
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net axi_interconnect_M00_AXI [get_bd_intf_pins axi_interconnect/M00_AXI] [get_bd_intf_pins axi_spi_engine/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_M02_AXI [get_bd_intf_pins axi_gpio/S_AXI] [get_bd_intf_pins axi_interconnect/M02_AXI]
|
||||
connect_bd_intf_net -intf_net axi_spi_engine_spi_0 [get_bd_intf_ports spi] [get_bd_intf_pins axi_spi_engine/spi]
|
||||
connect_bd_intf_net -intf_net microblaze_ps_M_AXI_DP [get_bd_intf_pins axi_interconnect/S00_AXI] [get_bd_intf_pins microblaze_ps/M_AXI_DP]
|
||||
connect_bd_intf_net -intf_net microblaze_ps_debug [get_bd_intf_pins mdm/MBDEBUG_0] [get_bd_intf_pins microblaze_ps/DEBUG]
|
||||
connect_bd_intf_net -intf_net microblaze_ps_dlmb_1 [get_bd_intf_pins microblaze_ps/DLMB] [get_bd_intf_pins microblaze_ps_local_memory/DLMB]
|
||||
connect_bd_intf_net -intf_net microblaze_ps_ilmb_1 [get_bd_intf_pins microblaze_ps/ILMB] [get_bd_intf_pins microblaze_ps_local_memory/ILMB]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net ARESETN_1 [get_bd_pins axi_gpio/s_axi_aresetn] [get_bd_pins axi_interconnect/ARESETN] [get_bd_pins axi_interconnect/M00_ARESETN] [get_bd_pins axi_interconnect/M01_ARESETN] [get_bd_pins axi_interconnect/M02_ARESETN] [get_bd_pins axi_interconnect/S00_ARESETN] [get_bd_pins axi_spi_engine/s_axi_aresetn] [get_bd_pins rst_clk_wiz_25M/peripheral_aresetn]
|
||||
connect_bd_net -net axi_gpio_gpio_io_o [get_bd_ports gpio_o] [get_bd_pins axi_gpio/gpio_io_o]
|
||||
connect_bd_net -net axi_spi_engine_active_0 [get_bd_ports spi_active] [get_bd_pins axi_spi_engine/active]
|
||||
connect_bd_net -net clk_100MHz_1 [get_bd_ports clk_25MHz] [get_bd_pins clk_wiz_25M/clk_in1]
|
||||
connect_bd_net -net clk_wiz_1_locked [get_bd_pins clk_wiz_25M/locked] [get_bd_pins rst_clk_wiz_25M/dcm_locked] [get_bd_pins rst_clk_wiz_25M/ext_reset_in]
|
||||
connect_bd_net -net clk_wiz_25M_clk_out1 [get_bd_ports ps_clk_25M] [get_bd_pins axi_gpio/s_axi_aclk] [get_bd_pins axi_interconnect/ACLK] [get_bd_pins axi_interconnect/M00_ACLK] [get_bd_pins axi_interconnect/M01_ACLK] [get_bd_pins axi_interconnect/M02_ACLK] [get_bd_pins axi_interconnect/S00_ACLK] [get_bd_pins axi_spi_engine/s_axi_aclk] [get_bd_pins axi_spi_engine/spi_clk] [get_bd_pins clk_wiz_25M/clk_out1] [get_bd_pins microblaze_ps/Clk] [get_bd_pins microblaze_ps_local_memory/LMB_Clk] [get_bd_pins rst_clk_wiz_25M/slowest_sync_clk]
|
||||
connect_bd_net -net gpio_i_1 [get_bd_ports gpio_i] [get_bd_pins axi_gpio/gpio2_io_i]
|
||||
connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mdm/Debug_SYS_Rst] [get_bd_pins rst_clk_wiz_25M/mb_debug_sys_rst]
|
||||
connect_bd_net -net rst_clk_wiz_1_100M_bus_struct_reset [get_bd_pins microblaze_ps_local_memory/SYS_Rst] [get_bd_pins rst_clk_wiz_25M/bus_struct_reset]
|
||||
connect_bd_net -net rst_clk_wiz_1_100M_mb_reset [get_bd_pins microblaze_ps/Reset] [get_bd_pins rst_clk_wiz_25M/mb_reset]
|
||||
|
||||
# Create address segments
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x40000000 [get_bd_addr_spaces microblaze_ps/Data] [get_bd_addr_segs axi_gpio/S_AXI/Reg] SEG_axi_gpio_Reg
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces microblaze_ps/Data] [get_bd_addr_segs axi_spi_engine/axi_spi_engine/s_axi/axi_lite] SEG_axi_spi_engine_axi_lite
|
||||
create_bd_addr_seg -range 0x00040000 -offset 0x00000000 [get_bd_addr_spaces microblaze_ps/Data] [get_bd_addr_segs microblaze_ps_local_memory/dlmb_bram_if_cntlr/SLMB/Mem] SEG_dlmb_bram_if_cntlr_Mem
|
||||
create_bd_addr_seg -range 0x00040000 -offset 0x00000000 [get_bd_addr_spaces microblaze_ps/Instruction] [get_bd_addr_segs microblaze_ps_local_memory/ilmb_bram_if_cntlr/SLMB/Mem] SEG_ilmb_bram_if_cntlr_Mem
|
||||
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design ""
|
||||
|
||||
|
||||
+207
@@ -0,0 +1,207 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 21
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_21;
|
||||
USE axi_gpio_v2_0_21.axi_gpio;
|
||||
|
||||
ENTITY system_bd_axi_gpio_0 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END system_bd_axi_gpio_0;
|
||||
|
||||
ARCHITECTURE system_bd_axi_gpio_0_arch OF system_bd_axi_gpio_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_axi_gpio_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_gpio IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_GPIO_WIDTH : INTEGER;
|
||||
C_GPIO2_WIDTH : INTEGER;
|
||||
C_ALL_INPUTS : INTEGER;
|
||||
C_ALL_INPUTS_2 : INTEGER;
|
||||
C_ALL_OUTPUTS : INTEGER;
|
||||
C_ALL_OUTPUTS_2 : INTEGER;
|
||||
C_INTERRUPT_PRESENT : INTEGER;
|
||||
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_IS_DUAL : INTEGER;
|
||||
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio2_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_o: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1" &
|
||||
", RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
|
||||
BEGIN
|
||||
U0 : axi_gpio
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "kintex7",
|
||||
C_S_AXI_ADDR_WIDTH => 9,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_GPIO_WIDTH => 32,
|
||||
C_GPIO2_WIDTH => 32,
|
||||
C_ALL_INPUTS => 0,
|
||||
C_ALL_INPUTS_2 => 1,
|
||||
C_ALL_OUTPUTS => 1,
|
||||
C_ALL_OUTPUTS_2 => 0,
|
||||
C_INTERRUPT_PRESENT => 0,
|
||||
C_DOUT_DEFAULT => X"FFFFFFFF",
|
||||
C_TRI_DEFAULT => X"FFFFFFFF",
|
||||
C_IS_DUAL => 1,
|
||||
C_DOUT_DEFAULT_2 => X"00000000",
|
||||
C_TRI_DEFAULT_2 => X"FFFFFFFF"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
gpio_io_o => gpio_io_o,
|
||||
gpio2_io_i => gpio2_io_i
|
||||
);
|
||||
END system_bd_axi_gpio_0_arch;
|
||||
+213
@@ -0,0 +1,213 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 21
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_21;
|
||||
USE axi_gpio_v2_0_21.axi_gpio;
|
||||
|
||||
ENTITY system_bd_axi_gpio_0 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END system_bd_axi_gpio_0;
|
||||
|
||||
ARCHITECTURE system_bd_axi_gpio_0_arch OF system_bd_axi_gpio_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_axi_gpio_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_gpio IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_GPIO_WIDTH : INTEGER;
|
||||
C_GPIO2_WIDTH : INTEGER;
|
||||
C_ALL_INPUTS : INTEGER;
|
||||
C_ALL_INPUTS_2 : INTEGER;
|
||||
C_ALL_OUTPUTS : INTEGER;
|
||||
C_ALL_OUTPUTS_2 : INTEGER;
|
||||
C_INTERRUPT_PRESENT : INTEGER;
|
||||
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_IS_DUAL : INTEGER;
|
||||
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_bd_axi_gpio_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2019.1.3";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_bd_axi_gpio_0_arch : ARCHITECTURE IS "system_bd_axi_gpio_0,axi_gpio,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_bd_axi_gpio_0_arch: ARCHITECTURE IS "system_bd_axi_gpio_0,axi_gpio,{x_ipProduct=Vivado 2019.1.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=21,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=kintex7,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=32,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=1,C_ALL_OUTPUTS=1,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0xFFFFFFFF,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=1,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio2_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_o: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1" &
|
||||
", RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
|
||||
BEGIN
|
||||
U0 : axi_gpio
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "kintex7",
|
||||
C_S_AXI_ADDR_WIDTH => 9,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_GPIO_WIDTH => 32,
|
||||
C_GPIO2_WIDTH => 32,
|
||||
C_ALL_INPUTS => 0,
|
||||
C_ALL_INPUTS_2 => 1,
|
||||
C_ALL_OUTPUTS => 1,
|
||||
C_ALL_OUTPUTS_2 => 0,
|
||||
C_INTERRUPT_PRESENT => 0,
|
||||
C_DOUT_DEFAULT => X"FFFFFFFF",
|
||||
C_TRI_DEFAULT => X"FFFFFFFF",
|
||||
C_IS_DUAL => 1,
|
||||
C_DOUT_DEFAULT_2 => X"00000000",
|
||||
C_TRI_DEFAULT_2 => X"FFFFFFFF"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
gpio_io_o => gpio_io_o,
|
||||
gpio2_io_i => gpio2_io_i
|
||||
);
|
||||
END system_bd_axi_gpio_0_arch;
|
||||
BIN
Binary file not shown.
+142
@@ -0,0 +1,142 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_axi_gpio_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_gpio" spirit:version="2.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.IP2INTC_IRQ.PortWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">/clk_wiz_25M_clk_out1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">25000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN">/clk_wiz_25M_clk_out1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">25000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALL_INPUTS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALL_INPUTS_2">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALL_OUTPUTS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALL_OUTPUTS_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_DEFAULT">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_DEFAULT_2">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GPIO2_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GPIO_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERRUPT_PRESENT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IS_DUAL">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRI_DEFAULT">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRI_DEFAULT_2">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_INPUTS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_INPUTS_2">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_OUTPUTS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_OUTPUTS_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DOUT_DEFAULT">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DOUT_DEFAULT_2">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPIO2_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPIO_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTERRUPT_PRESENT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_IS_DUAL">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRI_DEFAULT">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRI_DEFAULT_2">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_axi_gpio_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">21</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ALL_INPUTS_2" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ALL_OUTPUTS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_DOUT_DEFAULT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTERRUPT_PRESENT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IS_DUAL" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+48
@@ -0,0 +1,48 @@
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
set_false_path -to [get_pins -hier *cdc_to*/D]
|
||||
|
||||
+2085
File diff suppressed because it is too large
Load Diff
+2
@@ -0,0 +1,2 @@
|
||||
#--------------------Physical Constraints-----------------
|
||||
|
||||
+62
@@ -0,0 +1,62 @@
|
||||
|
||||
################################################################################
|
||||
# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# User should update the correct clock period before proceeding further
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# For best results the frequencies should be modified# to match the target
|
||||
# frequencies.
|
||||
|
||||
|
||||
create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk]
|
||||
## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
|
||||
|
||||
################################################################################
|
||||
+6602
File diff suppressed because it is too large
Load Diff
+7529
File diff suppressed because it is too large
Load Diff
+43
@@ -0,0 +1,43 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:57:11 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top system_bd_axi_gpio_0 -prefix
|
||||
// system_bd_axi_gpio_0_ system_bd_axi_gpio_0_stub.v
|
||||
// Design : system_bd_axi_gpio_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_gpio,Vivado 2019.1.3" *)
|
||||
module system_bd_axi_gpio_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
|
||||
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
|
||||
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
|
||||
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_o, gpio2_io_i)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_o[31:0],gpio2_io_i[31:0]" */;
|
||||
input s_axi_aclk;
|
||||
input s_axi_aresetn;
|
||||
input [8:0]s_axi_awaddr;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [8:0]s_axi_araddr;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output [31:0]gpio_io_o;
|
||||
input [31:0]gpio2_io_i;
|
||||
endmodule
|
||||
+50
@@ -0,0 +1,50 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:57:11 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_axi_gpio_0 -prefix
|
||||
-- system_bd_axi_gpio_0_ system_bd_axi_gpio_0_stub.vhdl
|
||||
-- Design : system_bd_axi_gpio_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_bd_axi_gpio_0 is
|
||||
Port (
|
||||
s_axi_aclk : in STD_LOGIC;
|
||||
s_axi_aresetn : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
gpio_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end system_bd_axi_gpio_0;
|
||||
|
||||
architecture stub of system_bd_axi_gpio_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_o[31:0],gpio2_io_i[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+358
@@ -0,0 +1,358 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
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|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_axi_interconnect_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_interconnect" spirit:version="2.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_axi_interconnect_0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_PROTOCOL_CHECKERS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M00_HAS_DATA_FIFO">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S07_ARB_PRIORITY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S07_HAS_DATA_FIFO">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S07_HAS_REGSLICE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S08_ARB_PRIORITY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S08_HAS_DATA_FIFO">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S08_HAS_REGSLICE">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S09_ARB_PRIORITY">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S09_HAS_DATA_FIFO">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S09_HAS_REGSLICE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S10_ARB_PRIORITY">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S10_HAS_DATA_FIFO">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S10_HAS_REGSLICE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S11_ARB_PRIORITY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S11_HAS_DATA_FIFO">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S11_HAS_REGSLICE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S12_ARB_PRIORITY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S12_HAS_DATA_FIFO">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S12_HAS_REGSLICE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S13_ARB_PRIORITY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S13_HAS_DATA_FIFO">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S13_HAS_REGSLICE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S14_ARB_PRIORITY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S14_HAS_DATA_FIFO">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S14_HAS_REGSLICE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S15_ARB_PRIORITY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S15_HAS_DATA_FIFO">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S15_HAS_REGSLICE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STRATEGY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.XBAR_DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator_AppCore</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">20</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_MI" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+1642
File diff suppressed because it is too large
Load Diff
+245
@@ -0,0 +1,245 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: analog.com:user:axi_spi_engine:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* IP_DEFINITION_SOURCE = "package_project" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_bd_axi_spi_engine_0 (
|
||||
s_axi_aclk,
|
||||
s_axi_aresetn,
|
||||
s_axi_awvalid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awready,
|
||||
s_axi_awprot,
|
||||
s_axi_wvalid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wready,
|
||||
s_axi_bvalid,
|
||||
s_axi_bresp,
|
||||
s_axi_bready,
|
||||
s_axi_arvalid,
|
||||
s_axi_araddr,
|
||||
s_axi_arready,
|
||||
s_axi_arprot,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
s_axi_rresp,
|
||||
s_axi_rdata,
|
||||
irq,
|
||||
spi_clk,
|
||||
spi_resetn,
|
||||
cmd_ready,
|
||||
cmd_valid,
|
||||
cmd_data,
|
||||
sdo_data_ready,
|
||||
sdo_data_valid,
|
||||
sdo_data,
|
||||
sdi_data_ready,
|
||||
sdi_data_valid,
|
||||
sdi_data,
|
||||
sync_ready,
|
||||
sync_valid,
|
||||
sync_data
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_clock, ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK, xilinx.com:signal:clock:1.0 spi_engine_offload_ctrl0_s_axi_signal_clock CLK" *)
|
||||
input wire s_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST, xilinx.com:signal:reset:1.0 spi_engine_offload_ctrl0_s_axi_signal_reset RST" *)
|
||||
input wire s_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *)
|
||||
input wire [15 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *)
|
||||
input wire [15 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS \
|
||||
1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
output wire irq;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_clock, ASSOCIATED_BUSIF spi_engine_ctrl, ASSOCIATED_RESET spi_resetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 spi_engine_ctrl_signal_clock CLK" *)
|
||||
input wire spi_clk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 spi_engine_ctrl_signal_reset RST" *)
|
||||
output wire spi_resetn;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_READY" *)
|
||||
input wire cmd_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_VALID" *)
|
||||
output wire cmd_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_DATA" *)
|
||||
output wire [15 : 0] cmd_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_READY" *)
|
||||
input wire sdo_data_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_VALID" *)
|
||||
output wire sdo_data_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_DATA" *)
|
||||
output wire [7 : 0] sdo_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_READY" *)
|
||||
output wire sdi_data_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_VALID" *)
|
||||
input wire sdi_data_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_DATA" *)
|
||||
input wire [7 : 0] sdi_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_READY" *)
|
||||
output wire sync_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_VALID" *)
|
||||
input wire sync_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_DATA" *)
|
||||
input wire [7 : 0] sync_data;
|
||||
|
||||
axi_spi_engine #(
|
||||
.CMD_FIFO_ADDRESS_WIDTH(4),
|
||||
.SYNC_FIFO_ADDRESS_WIDTH(4),
|
||||
.SDO_FIFO_ADDRESS_WIDTH(5),
|
||||
.SDI_FIFO_ADDRESS_WIDTH(5),
|
||||
.MM_IF_TYPE(0),
|
||||
.ASYNC_SPI_CLK(1'B0),
|
||||
.NUM_OFFLOAD(0),
|
||||
.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH(4),
|
||||
.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH(4),
|
||||
.ID(0),
|
||||
.DATA_WIDTH(8),
|
||||
.NUM_OF_SDI(1)
|
||||
) inst (
|
||||
.s_axi_aclk(s_axi_aclk),
|
||||
.s_axi_aresetn(s_axi_aresetn),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.up_clk(1'B0),
|
||||
.up_rstn(1'B0),
|
||||
.up_wreq(1'B0),
|
||||
.up_waddr(14'B0),
|
||||
.up_wdata(32'B0),
|
||||
.up_wack(),
|
||||
.up_rreq(1'B0),
|
||||
.up_raddr(14'B0),
|
||||
.up_rdata(),
|
||||
.up_rack(),
|
||||
.irq(irq),
|
||||
.spi_clk(spi_clk),
|
||||
.spi_resetn(spi_resetn),
|
||||
.cmd_ready(cmd_ready),
|
||||
.cmd_valid(cmd_valid),
|
||||
.cmd_data(cmd_data),
|
||||
.sdo_data_ready(sdo_data_ready),
|
||||
.sdo_data_valid(sdo_data_valid),
|
||||
.sdo_data(sdo_data),
|
||||
.sdi_data_ready(sdi_data_ready),
|
||||
.sdi_data_valid(sdi_data_valid),
|
||||
.sdi_data(sdi_data),
|
||||
.sync_ready(sync_ready),
|
||||
.sync_valid(sync_valid),
|
||||
.sync_data(sync_data),
|
||||
.offload0_cmd_wr_en(),
|
||||
.offload0_cmd_wr_data(),
|
||||
.offload0_sdo_wr_en(),
|
||||
.offload0_sdo_wr_data(),
|
||||
.offload0_mem_reset(),
|
||||
.offload0_enable(),
|
||||
.offload0_enabled(1'B0),
|
||||
.offload_sync_ready(),
|
||||
.offload_sync_valid(1'B0),
|
||||
.offload_sync_data(8'B0)
|
||||
);
|
||||
endmodule
|
||||
+245
@@ -0,0 +1,245 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: analog.com:user:axi_spi_engine:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
(* X_CORE_INFO = "axi_spi_engine,Vivado 2019.1.3" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_bd_axi_spi_engine_0,axi_spi_engine,{}" *)
|
||||
(* IP_DEFINITION_SOURCE = "package_project" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_bd_axi_spi_engine_0 (
|
||||
s_axi_aclk,
|
||||
s_axi_aresetn,
|
||||
s_axi_awvalid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awready,
|
||||
s_axi_awprot,
|
||||
s_axi_wvalid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wready,
|
||||
s_axi_bvalid,
|
||||
s_axi_bresp,
|
||||
s_axi_bready,
|
||||
s_axi_arvalid,
|
||||
s_axi_araddr,
|
||||
s_axi_arready,
|
||||
s_axi_arprot,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
s_axi_rresp,
|
||||
s_axi_rdata,
|
||||
irq,
|
||||
spi_clk,
|
||||
spi_resetn,
|
||||
cmd_ready,
|
||||
cmd_valid,
|
||||
cmd_data,
|
||||
sdo_data_ready,
|
||||
sdo_data_valid,
|
||||
sdo_data,
|
||||
sdi_data_ready,
|
||||
sdi_data_valid,
|
||||
sdi_data,
|
||||
sync_ready,
|
||||
sync_valid,
|
||||
sync_data
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_clock, ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK, xilinx.com:signal:clock:1.0 spi_engine_offload_ctrl0_s_axi_signal_clock CLK" *)
|
||||
input wire s_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST, xilinx.com:signal:reset:1.0 spi_engine_offload_ctrl0_s_axi_signal_reset RST" *)
|
||||
input wire s_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *)
|
||||
input wire [15 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *)
|
||||
input wire [15 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS \
|
||||
1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
output wire irq;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_clock, ASSOCIATED_BUSIF spi_engine_ctrl, ASSOCIATED_RESET spi_resetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 spi_engine_ctrl_signal_clock CLK" *)
|
||||
input wire spi_clk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 spi_engine_ctrl_signal_reset RST" *)
|
||||
output wire spi_resetn;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_READY" *)
|
||||
input wire cmd_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_VALID" *)
|
||||
output wire cmd_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_DATA" *)
|
||||
output wire [15 : 0] cmd_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_READY" *)
|
||||
input wire sdo_data_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_VALID" *)
|
||||
output wire sdo_data_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_DATA" *)
|
||||
output wire [7 : 0] sdo_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_READY" *)
|
||||
output wire sdi_data_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_VALID" *)
|
||||
input wire sdi_data_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_DATA" *)
|
||||
input wire [7 : 0] sdi_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_READY" *)
|
||||
output wire sync_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_VALID" *)
|
||||
input wire sync_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_DATA" *)
|
||||
input wire [7 : 0] sync_data;
|
||||
|
||||
axi_spi_engine #(
|
||||
.CMD_FIFO_ADDRESS_WIDTH(4),
|
||||
.SYNC_FIFO_ADDRESS_WIDTH(4),
|
||||
.SDO_FIFO_ADDRESS_WIDTH(5),
|
||||
.SDI_FIFO_ADDRESS_WIDTH(5),
|
||||
.MM_IF_TYPE(0),
|
||||
.ASYNC_SPI_CLK(1'B0),
|
||||
.NUM_OFFLOAD(0),
|
||||
.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH(4),
|
||||
.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH(4),
|
||||
.ID(0),
|
||||
.DATA_WIDTH(8),
|
||||
.NUM_OF_SDI(1)
|
||||
) inst (
|
||||
.s_axi_aclk(s_axi_aclk),
|
||||
.s_axi_aresetn(s_axi_aresetn),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.up_clk(1'B0),
|
||||
.up_rstn(1'B0),
|
||||
.up_wreq(1'B0),
|
||||
.up_waddr(14'B0),
|
||||
.up_wdata(32'B0),
|
||||
.up_wack(),
|
||||
.up_rreq(1'B0),
|
||||
.up_raddr(14'B0),
|
||||
.up_rdata(),
|
||||
.up_rack(),
|
||||
.irq(irq),
|
||||
.spi_clk(spi_clk),
|
||||
.spi_resetn(spi_resetn),
|
||||
.cmd_ready(cmd_ready),
|
||||
.cmd_valid(cmd_valid),
|
||||
.cmd_data(cmd_data),
|
||||
.sdo_data_ready(sdo_data_ready),
|
||||
.sdo_data_valid(sdo_data_valid),
|
||||
.sdo_data(sdo_data),
|
||||
.sdi_data_ready(sdi_data_ready),
|
||||
.sdi_data_valid(sdi_data_valid),
|
||||
.sdi_data(sdi_data),
|
||||
.sync_ready(sync_ready),
|
||||
.sync_valid(sync_valid),
|
||||
.sync_data(sync_data),
|
||||
.offload0_cmd_wr_en(),
|
||||
.offload0_cmd_wr_data(),
|
||||
.offload0_sdo_wr_en(),
|
||||
.offload0_sdo_wr_data(),
|
||||
.offload0_mem_reset(),
|
||||
.offload0_enable(),
|
||||
.offload0_enabled(1'B0),
|
||||
.offload_sync_ready(),
|
||||
.offload_sync_valid(1'B0),
|
||||
.offload_sync_data(8'B0)
|
||||
);
|
||||
endmodule
|
||||
BIN
Binary file not shown.
+147
@@ -0,0 +1,147 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_axi_spi_engine_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="analog.com" spirit:library="user" spirit:name="axi_spi_engine" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.CLK_DOMAIN">/clk_wiz_25M_clk_out1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.FREQ_HZ">25000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.CLK_DOMAIN">/clk_wiz_25M_clk_out1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.FREQ_HZ">25000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">/clk_wiz_25M_clk_out1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">25000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ASYNC_SPI_CLK">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DATA_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MM_IF_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.NUM_OFFLOAD">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.NUM_OF_SDI">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASYNC_SPI_CLK">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_axi_spi_engine_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MM_IF_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OFFLOAD">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OF_SDI">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+2691
File diff suppressed because it is too large
Load Diff
+1
@@ -0,0 +1 @@
|
||||
|
||||
+6407
File diff suppressed because it is too large
Load Diff
+7945
File diff suppressed because it is too large
Load Diff
+60
@@ -0,0 +1,60 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:57:11 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top system_bd_axi_spi_engine_0 -prefix
|
||||
// system_bd_axi_spi_engine_0_ system_bd_axi_spi_engine_0_stub.v
|
||||
// Design : system_bd_axi_spi_engine_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_spi_engine,Vivado 2019.1.3" *)
|
||||
module system_bd_axi_spi_engine_0(s_axi_aclk, s_axi_aresetn, s_axi_awvalid,
|
||||
s_axi_awaddr, s_axi_awready, s_axi_awprot, s_axi_wvalid, s_axi_wdata, s_axi_wstrb,
|
||||
s_axi_wready, s_axi_bvalid, s_axi_bresp, s_axi_bready, s_axi_arvalid, s_axi_araddr,
|
||||
s_axi_arready, s_axi_arprot, s_axi_rvalid, s_axi_rready, s_axi_rresp, s_axi_rdata, irq,
|
||||
spi_clk, spi_resetn, cmd_ready, cmd_valid, cmd_data, sdo_data_ready, sdo_data_valid, sdo_data,
|
||||
sdi_data_ready, sdi_data_valid, sdi_data, sync_ready, sync_valid, sync_data)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awvalid,s_axi_awaddr[15:0],s_axi_awready,s_axi_awprot[2:0],s_axi_wvalid,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wready,s_axi_bvalid,s_axi_bresp[1:0],s_axi_bready,s_axi_arvalid,s_axi_araddr[15:0],s_axi_arready,s_axi_arprot[2:0],s_axi_rvalid,s_axi_rready,s_axi_rresp[1:0],s_axi_rdata[31:0],irq,spi_clk,spi_resetn,cmd_ready,cmd_valid,cmd_data[15:0],sdo_data_ready,sdo_data_valid,sdo_data[7:0],sdi_data_ready,sdi_data_valid,sdi_data[7:0],sync_ready,sync_valid,sync_data[7:0]" */;
|
||||
input s_axi_aclk;
|
||||
input s_axi_aresetn;
|
||||
input s_axi_awvalid;
|
||||
input [15:0]s_axi_awaddr;
|
||||
output s_axi_awready;
|
||||
input [2:0]s_axi_awprot;
|
||||
input s_axi_wvalid;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
output s_axi_wready;
|
||||
output s_axi_bvalid;
|
||||
output [1:0]s_axi_bresp;
|
||||
input s_axi_bready;
|
||||
input s_axi_arvalid;
|
||||
input [15:0]s_axi_araddr;
|
||||
output s_axi_arready;
|
||||
input [2:0]s_axi_arprot;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output [1:0]s_axi_rresp;
|
||||
output [31:0]s_axi_rdata;
|
||||
output irq;
|
||||
input spi_clk;
|
||||
output spi_resetn;
|
||||
input cmd_ready;
|
||||
output cmd_valid;
|
||||
output [15:0]cmd_data;
|
||||
input sdo_data_ready;
|
||||
output sdo_data_valid;
|
||||
output [7:0]sdo_data;
|
||||
output sdi_data_ready;
|
||||
input sdi_data_valid;
|
||||
input [7:0]sdi_data;
|
||||
output sync_ready;
|
||||
input sync_valid;
|
||||
input [7:0]sync_data;
|
||||
endmodule
|
||||
+65
@@ -0,0 +1,65 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:57:11 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_axi_spi_engine_0 -prefix
|
||||
-- system_bd_axi_spi_engine_0_ system_bd_axi_spi_engine_0_stub.vhdl
|
||||
-- Design : system_bd_axi_spi_engine_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_bd_axi_spi_engine_0 is
|
||||
Port (
|
||||
s_axi_aclk : in STD_LOGIC;
|
||||
s_axi_aresetn : in STD_LOGIC;
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
irq : out STD_LOGIC;
|
||||
spi_clk : in STD_LOGIC;
|
||||
spi_resetn : out STD_LOGIC;
|
||||
cmd_ready : in STD_LOGIC;
|
||||
cmd_valid : out STD_LOGIC;
|
||||
cmd_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
sdo_data_ready : in STD_LOGIC;
|
||||
sdo_data_valid : out STD_LOGIC;
|
||||
sdo_data : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
sdi_data_ready : out STD_LOGIC;
|
||||
sdi_data_valid : in STD_LOGIC;
|
||||
sdi_data : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
sync_ready : out STD_LOGIC;
|
||||
sync_valid : in STD_LOGIC;
|
||||
sync_data : in STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
|
||||
end system_bd_axi_spi_engine_0;
|
||||
|
||||
architecture stub of system_bd_axi_spi_engine_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awvalid,s_axi_awaddr[15:0],s_axi_awready,s_axi_awprot[2:0],s_axi_wvalid,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wready,s_axi_bvalid,s_axi_bresp[1:0],s_axi_bready,s_axi_arvalid,s_axi_araddr[15:0],s_axi_arready,s_axi_arprot[2:0],s_axi_rvalid,s_axi_rready,s_axi_rresp[1:0],s_axi_rdata[31:0],irq,spi_clk,spi_resetn,cmd_ready,cmd_valid,cmd_data[15:0],sdo_data_ready,sdo_data_valid,sdo_data[7:0],sdi_data_ready,sdi_data_valid,sdi_data[7:0],sync_ready,sync_valid,sync_data[7:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axi_spi_engine,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
BIN
Binary file not shown.
+90
@@ -0,0 +1,90 @@
|
||||
|
||||
// file: system_bd_clk_wiz_25M_0.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____25.000______0.000______50.0______401.466____245.713
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary______________25____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "system_bd_clk_wiz_25M_0,clk_wiz_v6_0_3_0_0,{component_name=system_bd_clk_wiz_25M_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=40.000,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
|
||||
|
||||
module system_bd_clk_wiz_25M_0
|
||||
(
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
// Status and control signals
|
||||
output locked,
|
||||
// Clock in ports
|
||||
input clk_in1
|
||||
);
|
||||
|
||||
system_bd_clk_wiz_25M_0_clk_wiz inst
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1),
|
||||
// Status and control signals
|
||||
.locked(locked),
|
||||
// Clock in ports
|
||||
.clk_in1(clk_in1)
|
||||
);
|
||||
|
||||
endmodule
|
||||
+692
@@ -0,0 +1,692 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_clk_wiz_25M_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="6.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_IN_D.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_IN_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_OUT_D.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_OUT_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN1_D.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN1_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN2_D.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN2_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.CLK_DOMAIN">system_bd_clk_25MHz</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_HZ">25000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.CLK_DOMAIN">/clk_wiz_25M_clk_out1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_HZ">25000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTR.PortWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTR.SENSITIVITY">LEVEL_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.MAX_BURST_LENGTH">256</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL">AXI4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.SUPPORTS_NARROW_BURST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_RESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFBOUT_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFBOUT_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS">400.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ">25.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">25.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVCLK">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE1_AUTO">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">0.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE3_AUTO">0.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE4_AUTO">0.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">0.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE6_AUTO">0.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE7_AUTO">0.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK3">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary______________25____________0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_3">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV3">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV4">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV5">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">36.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">40.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">36.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">clk_out1____25.000______0.000______50.0______401.466____245.713</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">no_CLK_OUT2_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV3">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV4">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_REG">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRECISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REF_CLK_FREQ">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">system_bd_clk_wiz_25M_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">400.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">401.466</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">245.713</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_clk_wiz_25M_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK0">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK3">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL0">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">36.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">40.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">36.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRECISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_HZ" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.CLK_DOMAIN" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_HZ" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.PHASE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_IN_FREQ" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_SOURCE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_LOCKED" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_RESET" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+60
@@ -0,0 +1,60 @@
|
||||
|
||||
# file: system_bd_clk_wiz_25M_0.xdc
|
||||
#
|
||||
# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system. If required
|
||||
# commented constraints can be used in the top level xdc
|
||||
#----------------------------------------------------------------
|
||||
# Connect to input port when clock capable pin is selected for input
|
||||
create_clock -period 40.000 [get_ports clk_in1]
|
||||
set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.4
|
||||
|
||||
|
||||
set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*]
|
||||
+4843
File diff suppressed because it is too large
Load Diff
+2
@@ -0,0 +1,2 @@
|
||||
#--------------------Physical Constraints-----------------
|
||||
|
||||
+201
@@ -0,0 +1,201 @@
|
||||
|
||||
// file: system_bd_clk_wiz_25M_0.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____25.000______0.000______50.0______401.466____245.713
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary______________25____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module system_bd_clk_wiz_25M_0_clk_wiz
|
||||
|
||||
(// Clock in ports
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
// Status and control signals
|
||||
output locked,
|
||||
input clk_in1
|
||||
);
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
wire clk_in1_system_bd_clk_wiz_25M_0;
|
||||
wire clk_in2_system_bd_clk_wiz_25M_0;
|
||||
IBUF clkin1_ibufg
|
||||
(.O (clk_in1_system_bd_clk_wiz_25M_0),
|
||||
.I (clk_in1));
|
||||
|
||||
|
||||
|
||||
|
||||
// Clocking PRIMITIVE
|
||||
//------------------------------------
|
||||
|
||||
// Instantiation of the MMCM PRIMITIVE
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
|
||||
wire clk_out1_system_bd_clk_wiz_25M_0;
|
||||
wire clk_out2_system_bd_clk_wiz_25M_0;
|
||||
wire clk_out3_system_bd_clk_wiz_25M_0;
|
||||
wire clk_out4_system_bd_clk_wiz_25M_0;
|
||||
wire clk_out5_system_bd_clk_wiz_25M_0;
|
||||
wire clk_out6_system_bd_clk_wiz_25M_0;
|
||||
wire clk_out7_system_bd_clk_wiz_25M_0;
|
||||
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire psdone_unused;
|
||||
wire locked_int;
|
||||
wire clkfbout_system_bd_clk_wiz_25M_0;
|
||||
wire clkfbout_buf_system_bd_clk_wiz_25M_0;
|
||||
wire clkfboutb_unused;
|
||||
wire clkout0b_unused;
|
||||
wire clkout1_unused;
|
||||
wire clkout1b_unused;
|
||||
wire clkout2_unused;
|
||||
wire clkout2b_unused;
|
||||
wire clkout3_unused;
|
||||
wire clkout3b_unused;
|
||||
wire clkout4_unused;
|
||||
wire clkout5_unused;
|
||||
wire clkout6_unused;
|
||||
wire clkfbstopped_unused;
|
||||
wire clkinstopped_unused;
|
||||
|
||||
MMCME2_ADV
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.CLKOUT4_CASCADE ("FALSE"),
|
||||
.COMPENSATION ("ZHOLD"),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (1),
|
||||
.CLKFBOUT_MULT_F (36.500),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKFBOUT_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT0_DIVIDE_F (36.500),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT0_USE_FINE_PS ("FALSE"),
|
||||
.CLKIN1_PERIOD (40.000))
|
||||
mmcm_adv_inst
|
||||
// Output clocks
|
||||
(
|
||||
.CLKFBOUT (clkfbout_system_bd_clk_wiz_25M_0),
|
||||
.CLKFBOUTB (clkfboutb_unused),
|
||||
.CLKOUT0 (clk_out1_system_bd_clk_wiz_25M_0),
|
||||
.CLKOUT0B (clkout0b_unused),
|
||||
.CLKOUT1 (clkout1_unused),
|
||||
.CLKOUT1B (clkout1b_unused),
|
||||
.CLKOUT2 (clkout2_unused),
|
||||
.CLKOUT2B (clkout2b_unused),
|
||||
.CLKOUT3 (clkout3_unused),
|
||||
.CLKOUT3B (clkout3b_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
.CLKOUT6 (clkout6_unused),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout_buf_system_bd_clk_wiz_25M_0),
|
||||
.CLKIN1 (clk_in1_system_bd_clk_wiz_25M_0),
|
||||
.CLKIN2 (1'b0),
|
||||
// Tied to always select the primary input clock
|
||||
.CLKINSEL (1'b1),
|
||||
// Ports for dynamic reconfiguration
|
||||
.DADDR (7'h0),
|
||||
.DCLK (1'b0),
|
||||
.DEN (1'b0),
|
||||
.DI (16'h0),
|
||||
.DO (do_unused),
|
||||
.DRDY (drdy_unused),
|
||||
.DWE (1'b0),
|
||||
// Ports for dynamic phase shift
|
||||
.PSCLK (1'b0),
|
||||
.PSEN (1'b0),
|
||||
.PSINCDEC (1'b0),
|
||||
.PSDONE (psdone_unused),
|
||||
// Other control and status signals
|
||||
.LOCKED (locked_int),
|
||||
.CLKINSTOPPED (clkinstopped_unused),
|
||||
.CLKFBSTOPPED (clkfbstopped_unused),
|
||||
.PWRDWN (1'b0),
|
||||
.RST (1'b0));
|
||||
|
||||
assign locked = locked_int;
|
||||
// Clock Monitor clock assigning
|
||||
//--------------------------------------
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
|
||||
BUFG clkf_buf
|
||||
(.O (clkfbout_buf_system_bd_clk_wiz_25M_0),
|
||||
.I (clkfbout_system_bd_clk_wiz_25M_0));
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (clk_out1),
|
||||
.I (clk_out1_system_bd_clk_wiz_25M_0));
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+58
@@ -0,0 +1,58 @@
|
||||
|
||||
# file: system_bd_clk_wiz_25M_0_ooc.xdc
|
||||
#
|
||||
# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
#################
|
||||
#DEFAULT CLOCK CONSTRAINTS
|
||||
|
||||
############################################################
|
||||
# Clock Period Constraints #
|
||||
############################################################
|
||||
#create_clock -period 40.000 [get_ports clk_in1]
|
||||
|
||||
+237
@@ -0,0 +1,237 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:57:10 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top system_bd_clk_wiz_25M_0 -prefix
|
||||
// system_bd_clk_wiz_25M_0_ system_bd_clk_wiz_25M_0_sim_netlist.v
|
||||
// Design : system_bd_clk_wiz_25M_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* NotValidForBitStream *)
|
||||
module system_bd_clk_wiz_25M_0
|
||||
(clk_out1,
|
||||
locked,
|
||||
clk_in1);
|
||||
output clk_out1;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
|
||||
(* IBUF_LOW_PWR *) wire clk_in1;
|
||||
wire clk_out1;
|
||||
wire locked;
|
||||
|
||||
system_bd_clk_wiz_25M_0_system_bd_clk_wiz_25M_0_clk_wiz inst
|
||||
(.clk_in1(clk_in1),
|
||||
.clk_out1(clk_out1),
|
||||
.locked(locked));
|
||||
endmodule
|
||||
|
||||
module system_bd_clk_wiz_25M_0_system_bd_clk_wiz_25M_0_clk_wiz
|
||||
(clk_out1,
|
||||
locked,
|
||||
clk_in1);
|
||||
output clk_out1;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
|
||||
wire clk_in1;
|
||||
wire clk_in1_system_bd_clk_wiz_25M_0;
|
||||
wire clk_out1;
|
||||
wire clk_out1_system_bd_clk_wiz_25M_0;
|
||||
wire clkfbout_buf_system_bd_clk_wiz_25M_0;
|
||||
wire clkfbout_system_bd_clk_wiz_25M_0;
|
||||
wire locked;
|
||||
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
|
||||
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
|
||||
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkf_buf
|
||||
(.I(clkfbout_system_bd_clk_wiz_25M_0),
|
||||
.O(clkfbout_buf_system_bd_clk_wiz_25M_0));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
IBUF #(
|
||||
.IOSTANDARD("DEFAULT"))
|
||||
clkin1_ibufg
|
||||
(.I(clk_in1),
|
||||
.O(clk_in1_system_bd_clk_wiz_25M_0));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkout1_buf
|
||||
(.I(clk_out1_system_bd_clk_wiz_25M_0),
|
||||
.O(clk_out1));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
MMCME2_ADV #(
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
.CLKFBOUT_MULT_F(36.500000),
|
||||
.CLKFBOUT_PHASE(0.000000),
|
||||
.CLKFBOUT_USE_FINE_PS("FALSE"),
|
||||
.CLKIN1_PERIOD(40.000000),
|
||||
.CLKIN2_PERIOD(0.000000),
|
||||
.CLKOUT0_DIVIDE_F(36.500000),
|
||||
.CLKOUT0_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT0_PHASE(0.000000),
|
||||
.CLKOUT0_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT1_PHASE(0.000000),
|
||||
.CLKOUT1_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT2_PHASE(0.000000),
|
||||
.CLKOUT2_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT3_PHASE(0.000000),
|
||||
.CLKOUT3_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT4_PHASE(0.000000),
|
||||
.CLKOUT4_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT5_PHASE(0.000000),
|
||||
.CLKOUT5_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT6_PHASE(0.000000),
|
||||
.CLKOUT6_USE_FINE_PS("FALSE"),
|
||||
.COMPENSATION("ZHOLD"),
|
||||
.DIVCLK_DIVIDE(1),
|
||||
.IS_CLKINSEL_INVERTED(1'b0),
|
||||
.IS_PSEN_INVERTED(1'b0),
|
||||
.IS_PSINCDEC_INVERTED(1'b0),
|
||||
.IS_PWRDWN_INVERTED(1'b0),
|
||||
.IS_RST_INVERTED(1'b0),
|
||||
.REF_JITTER1(0.010000),
|
||||
.REF_JITTER2(0.010000),
|
||||
.SS_EN("FALSE"),
|
||||
.SS_MODE("CENTER_HIGH"),
|
||||
.SS_MOD_PERIOD(10000),
|
||||
.STARTUP_WAIT("FALSE"))
|
||||
mmcm_adv_inst
|
||||
(.CLKFBIN(clkfbout_buf_system_bd_clk_wiz_25M_0),
|
||||
.CLKFBOUT(clkfbout_system_bd_clk_wiz_25M_0),
|
||||
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
|
||||
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
|
||||
.CLKIN1(clk_in1_system_bd_clk_wiz_25M_0),
|
||||
.CLKIN2(1'b0),
|
||||
.CLKINSEL(1'b1),
|
||||
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
|
||||
.CLKOUT0(clk_out1_system_bd_clk_wiz_25M_0),
|
||||
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
|
||||
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
|
||||
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
|
||||
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
|
||||
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
|
||||
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
|
||||
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
|
||||
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
|
||||
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
|
||||
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
|
||||
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DCLK(1'b0),
|
||||
.DEN(1'b0),
|
||||
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
|
||||
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
|
||||
.DWE(1'b0),
|
||||
.LOCKED(locked),
|
||||
.PSCLK(1'b0),
|
||||
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
|
||||
.PSEN(1'b0),
|
||||
.PSINCDEC(1'b0),
|
||||
.PWRDWN(1'b0),
|
||||
.RST(1'b0));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+185
@@ -0,0 +1,185 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:57:10 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top system_bd_clk_wiz_25M_0 -prefix
|
||||
-- system_bd_clk_wiz_25M_0_ system_bd_clk_wiz_25M_0_sim_netlist.vhdl
|
||||
-- Design : system_bd_clk_wiz_25M_0
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity system_bd_clk_wiz_25M_0_system_bd_clk_wiz_25M_0_clk_wiz is
|
||||
port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
end system_bd_clk_wiz_25M_0_system_bd_clk_wiz_25M_0_clk_wiz;
|
||||
|
||||
architecture STRUCTURE of system_bd_clk_wiz_25M_0_system_bd_clk_wiz_25M_0_clk_wiz is
|
||||
signal clk_in1_system_bd_clk_wiz_25M_0 : STD_LOGIC;
|
||||
signal clk_out1_system_bd_clk_wiz_25M_0 : STD_LOGIC;
|
||||
signal clkfbout_buf_system_bd_clk_wiz_25M_0 : STD_LOGIC;
|
||||
signal clkfbout_system_bd_clk_wiz_25M_0 : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
attribute BOX_TYPE : string;
|
||||
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE : string;
|
||||
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE : string;
|
||||
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
|
||||
attribute IFD_DELAY_VALUE : string;
|
||||
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
|
||||
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
|
||||
begin
|
||||
clkf_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clkfbout_system_bd_clk_wiz_25M_0,
|
||||
O => clkfbout_buf_system_bd_clk_wiz_25M_0
|
||||
);
|
||||
clkin1_ibufg: unisim.vcomponents.IBUF
|
||||
generic map(
|
||||
IOSTANDARD => "DEFAULT"
|
||||
)
|
||||
port map (
|
||||
I => clk_in1,
|
||||
O => clk_in1_system_bd_clk_wiz_25M_0
|
||||
);
|
||||
clkout1_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clk_out1_system_bd_clk_wiz_25M_0,
|
||||
O => clk_out1
|
||||
);
|
||||
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
|
||||
generic map(
|
||||
BANDWIDTH => "OPTIMIZED",
|
||||
CLKFBOUT_MULT_F => 36.500000,
|
||||
CLKFBOUT_PHASE => 0.000000,
|
||||
CLKFBOUT_USE_FINE_PS => false,
|
||||
CLKIN1_PERIOD => 40.000000,
|
||||
CLKIN2_PERIOD => 0.000000,
|
||||
CLKOUT0_DIVIDE_F => 36.500000,
|
||||
CLKOUT0_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT0_PHASE => 0.000000,
|
||||
CLKOUT0_USE_FINE_PS => false,
|
||||
CLKOUT1_DIVIDE => 1,
|
||||
CLKOUT1_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT1_PHASE => 0.000000,
|
||||
CLKOUT1_USE_FINE_PS => false,
|
||||
CLKOUT2_DIVIDE => 1,
|
||||
CLKOUT2_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT2_PHASE => 0.000000,
|
||||
CLKOUT2_USE_FINE_PS => false,
|
||||
CLKOUT3_DIVIDE => 1,
|
||||
CLKOUT3_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT3_PHASE => 0.000000,
|
||||
CLKOUT3_USE_FINE_PS => false,
|
||||
CLKOUT4_CASCADE => false,
|
||||
CLKOUT4_DIVIDE => 1,
|
||||
CLKOUT4_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT4_PHASE => 0.000000,
|
||||
CLKOUT4_USE_FINE_PS => false,
|
||||
CLKOUT5_DIVIDE => 1,
|
||||
CLKOUT5_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT5_PHASE => 0.000000,
|
||||
CLKOUT5_USE_FINE_PS => false,
|
||||
CLKOUT6_DIVIDE => 1,
|
||||
CLKOUT6_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT6_PHASE => 0.000000,
|
||||
CLKOUT6_USE_FINE_PS => false,
|
||||
COMPENSATION => "ZHOLD",
|
||||
DIVCLK_DIVIDE => 1,
|
||||
IS_CLKINSEL_INVERTED => '0',
|
||||
IS_PSEN_INVERTED => '0',
|
||||
IS_PSINCDEC_INVERTED => '0',
|
||||
IS_PWRDWN_INVERTED => '0',
|
||||
IS_RST_INVERTED => '0',
|
||||
REF_JITTER1 => 0.010000,
|
||||
REF_JITTER2 => 0.010000,
|
||||
SS_EN => "FALSE",
|
||||
SS_MODE => "CENTER_HIGH",
|
||||
SS_MOD_PERIOD => 10000,
|
||||
STARTUP_WAIT => false
|
||||
)
|
||||
port map (
|
||||
CLKFBIN => clkfbout_buf_system_bd_clk_wiz_25M_0,
|
||||
CLKFBOUT => clkfbout_system_bd_clk_wiz_25M_0,
|
||||
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
|
||||
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
|
||||
CLKIN1 => clk_in1_system_bd_clk_wiz_25M_0,
|
||||
CLKIN2 => '0',
|
||||
CLKINSEL => '1',
|
||||
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
|
||||
CLKOUT0 => clk_out1_system_bd_clk_wiz_25M_0,
|
||||
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
|
||||
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
|
||||
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
|
||||
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
|
||||
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
|
||||
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
|
||||
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
|
||||
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
|
||||
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
|
||||
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
|
||||
DADDR(6 downto 0) => B"0000000",
|
||||
DCLK => '0',
|
||||
DEN => '0',
|
||||
DI(15 downto 0) => B"0000000000000000",
|
||||
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
|
||||
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
|
||||
DWE => '0',
|
||||
LOCKED => locked,
|
||||
PSCLK => '0',
|
||||
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
|
||||
PSEN => '0',
|
||||
PSINCDEC => '0',
|
||||
PWRDWN => '0',
|
||||
RST => '0'
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity system_bd_clk_wiz_25M_0 is
|
||||
port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of system_bd_clk_wiz_25M_0 : entity is true;
|
||||
end system_bd_clk_wiz_25M_0;
|
||||
|
||||
architecture STRUCTURE of system_bd_clk_wiz_25M_0 is
|
||||
begin
|
||||
inst: entity work.system_bd_clk_wiz_25M_0_system_bd_clk_wiz_25M_0_clk_wiz
|
||||
port map (
|
||||
clk_in1 => clk_in1,
|
||||
clk_out1 => clk_out1,
|
||||
locked => locked
|
||||
);
|
||||
end STRUCTURE;
|
||||
+21
@@ -0,0 +1,21 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:57:10 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top system_bd_clk_wiz_25M_0 -prefix
|
||||
// system_bd_clk_wiz_25M_0_ system_bd_clk_wiz_25M_0_stub.v
|
||||
// Design : system_bd_clk_wiz_25M_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
module system_bd_clk_wiz_25M_0(clk_out1, locked, clk_in1)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1" */;
|
||||
output clk_out1;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
endmodule
|
||||
+30
@@ -0,0 +1,30 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:57:10 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_clk_wiz_25M_0 -prefix
|
||||
-- system_bd_clk_wiz_25M_0_ system_bd_clk_wiz_25M_0_stub.vhdl
|
||||
-- Design : system_bd_clk_wiz_25M_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_bd_clk_wiz_25M_0 is
|
||||
Port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
|
||||
end system_bd_clk_wiz_25M_0;
|
||||
|
||||
architecture stub of system_bd_clk_wiz_25M_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1";
|
||||
begin
|
||||
end;
|
||||
+295
@@ -0,0 +1,295 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
|
||||
-- IP Revision: 16
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY lmb_bram_if_cntlr_v4_0_16;
|
||||
USE lmb_bram_if_cntlr_v4_0_16.lmb_bram_if_cntlr;
|
||||
|
||||
ENTITY system_bd_dlmb_bram_if_cntlr_0 IS
|
||||
PORT (
|
||||
LMB_Clk : IN STD_LOGIC;
|
||||
LMB_Rst : IN STD_LOGIC;
|
||||
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_AddrStrobe : IN STD_LOGIC;
|
||||
LMB_ReadStrobe : IN STD_LOGIC;
|
||||
LMB_WriteStrobe : IN STD_LOGIC;
|
||||
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl_Ready : OUT STD_LOGIC;
|
||||
Sl_Wait : OUT STD_LOGIC;
|
||||
Sl_UE : OUT STD_LOGIC;
|
||||
Sl_CE : OUT STD_LOGIC;
|
||||
BRAM_Rst_A : OUT STD_LOGIC;
|
||||
BRAM_Clk_A : OUT STD_LOGIC;
|
||||
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
BRAM_EN_A : OUT STD_LOGIC;
|
||||
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
|
||||
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
|
||||
);
|
||||
END system_bd_dlmb_bram_if_cntlr_0;
|
||||
|
||||
ARCHITECTURE system_bd_dlmb_bram_if_cntlr_0_arch OF system_bd_dlmb_bram_if_cntlr_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT lmb_bram_if_cntlr IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_HIGHADDR : STD_LOGIC_VECTOR;
|
||||
C_BASEADDR : STD_LOGIC_VECTOR;
|
||||
C_NUM_LMB : INTEGER;
|
||||
C_MASK : STD_LOGIC_VECTOR;
|
||||
C_MASK1 : STD_LOGIC_VECTOR;
|
||||
C_MASK2 : STD_LOGIC_VECTOR;
|
||||
C_MASK3 : STD_LOGIC_VECTOR;
|
||||
C_LMB_AWIDTH : INTEGER;
|
||||
C_LMB_DWIDTH : INTEGER;
|
||||
C_ECC : INTEGER;
|
||||
C_INTERCONNECT : INTEGER;
|
||||
C_FAULT_INJECT : INTEGER;
|
||||
C_CE_FAILING_REGISTERS : INTEGER;
|
||||
C_UE_FAILING_REGISTERS : INTEGER;
|
||||
C_ECC_STATUS_REGISTERS : INTEGER;
|
||||
C_ECC_ONOFF_REGISTER : INTEGER;
|
||||
C_ECC_ONOFF_RESET_VALUE : INTEGER;
|
||||
C_CE_COUNTER_WIDTH : INTEGER;
|
||||
C_WRITE_ACCESS : INTEGER;
|
||||
C_BRAM_AWIDTH : INTEGER;
|
||||
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
LMB_Clk : IN STD_LOGIC;
|
||||
LMB_Rst : IN STD_LOGIC;
|
||||
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_AddrStrobe : IN STD_LOGIC;
|
||||
LMB_ReadStrobe : IN STD_LOGIC;
|
||||
LMB_WriteStrobe : IN STD_LOGIC;
|
||||
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl_Ready : OUT STD_LOGIC;
|
||||
Sl_Wait : OUT STD_LOGIC;
|
||||
Sl_UE : OUT STD_LOGIC;
|
||||
Sl_CE : OUT STD_LOGIC;
|
||||
LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB1_AddrStrobe : IN STD_LOGIC;
|
||||
LMB1_ReadStrobe : IN STD_LOGIC;
|
||||
LMB1_WriteStrobe : IN STD_LOGIC;
|
||||
LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl1_Ready : OUT STD_LOGIC;
|
||||
Sl1_Wait : OUT STD_LOGIC;
|
||||
Sl1_UE : OUT STD_LOGIC;
|
||||
Sl1_CE : OUT STD_LOGIC;
|
||||
LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB2_AddrStrobe : IN STD_LOGIC;
|
||||
LMB2_ReadStrobe : IN STD_LOGIC;
|
||||
LMB2_WriteStrobe : IN STD_LOGIC;
|
||||
LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl2_Ready : OUT STD_LOGIC;
|
||||
Sl2_Wait : OUT STD_LOGIC;
|
||||
Sl2_UE : OUT STD_LOGIC;
|
||||
Sl2_CE : OUT STD_LOGIC;
|
||||
LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB3_AddrStrobe : IN STD_LOGIC;
|
||||
LMB3_ReadStrobe : IN STD_LOGIC;
|
||||
LMB3_WriteStrobe : IN STD_LOGIC;
|
||||
LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl3_Ready : OUT STD_LOGIC;
|
||||
Sl3_Wait : OUT STD_LOGIC;
|
||||
Sl3_UE : OUT STD_LOGIC;
|
||||
Sl3_CE : OUT STD_LOGIC;
|
||||
BRAM_Rst_A : OUT STD_LOGIC;
|
||||
BRAM_Clk_A : OUT STD_LOGIC;
|
||||
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
BRAM_EN_A : OUT STD_LOGIC;
|
||||
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
|
||||
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
S_AXI_CTRL_ACLK : IN STD_LOGIC;
|
||||
S_AXI_CTRL_ARESETN : IN STD_LOGIC;
|
||||
S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_CTRL_AWVALID : IN STD_LOGIC;
|
||||
S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXI_CTRL_WVALID : IN STD_LOGIC;
|
||||
S_AXI_CTRL_WREADY : OUT STD_LOGIC;
|
||||
S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_CTRL_BVALID : OUT STD_LOGIC;
|
||||
S_AXI_CTRL_BREADY : IN STD_LOGIC;
|
||||
S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_CTRL_ARVALID : IN STD_LOGIC;
|
||||
S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_CTRL_RVALID : OUT STD_LOGIC;
|
||||
S_AXI_CTRL_RREADY : IN STD_LOGIC;
|
||||
UE : OUT STD_LOGIC;
|
||||
CE : OUT STD_LOGIC;
|
||||
Interrupt : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT lmb_bram_if_cntlr;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF BRAM_Rst_A: SIGNAL IS "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 262144, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_ABus: SIGNAL IS "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Rst: SIGNAL IS "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Clk: SIGNAL IS "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
|
||||
BEGIN
|
||||
U0 : lmb_bram_if_cntlr
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "kintex7",
|
||||
C_HIGHADDR => X"000000000003FFFF",
|
||||
C_BASEADDR => X"0000000000000000",
|
||||
C_NUM_LMB => 1,
|
||||
C_MASK => X"0000000040000000",
|
||||
C_MASK1 => X"0000000000800000",
|
||||
C_MASK2 => X"0000000000800000",
|
||||
C_MASK3 => X"0000000000800000",
|
||||
C_LMB_AWIDTH => 32,
|
||||
C_LMB_DWIDTH => 32,
|
||||
C_ECC => 0,
|
||||
C_INTERCONNECT => 0,
|
||||
C_FAULT_INJECT => 0,
|
||||
C_CE_FAILING_REGISTERS => 0,
|
||||
C_UE_FAILING_REGISTERS => 0,
|
||||
C_ECC_STATUS_REGISTERS => 0,
|
||||
C_ECC_ONOFF_REGISTER => 0,
|
||||
C_ECC_ONOFF_RESET_VALUE => 1,
|
||||
C_CE_COUNTER_WIDTH => 0,
|
||||
C_WRITE_ACCESS => 2,
|
||||
C_BRAM_AWIDTH => 32,
|
||||
C_S_AXI_CTRL_ADDR_WIDTH => 32,
|
||||
C_S_AXI_CTRL_DATA_WIDTH => 32
|
||||
)
|
||||
PORT MAP (
|
||||
LMB_Clk => LMB_Clk,
|
||||
LMB_Rst => LMB_Rst,
|
||||
LMB_ABus => LMB_ABus,
|
||||
LMB_WriteDBus => LMB_WriteDBus,
|
||||
LMB_AddrStrobe => LMB_AddrStrobe,
|
||||
LMB_ReadStrobe => LMB_ReadStrobe,
|
||||
LMB_WriteStrobe => LMB_WriteStrobe,
|
||||
LMB_BE => LMB_BE,
|
||||
Sl_DBus => Sl_DBus,
|
||||
Sl_Ready => Sl_Ready,
|
||||
Sl_Wait => Sl_Wait,
|
||||
Sl_UE => Sl_UE,
|
||||
Sl_CE => Sl_CE,
|
||||
LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB1_AddrStrobe => '0',
|
||||
LMB1_ReadStrobe => '0',
|
||||
LMB1_WriteStrobe => '0',
|
||||
LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB2_AddrStrobe => '0',
|
||||
LMB2_ReadStrobe => '0',
|
||||
LMB2_WriteStrobe => '0',
|
||||
LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB3_AddrStrobe => '0',
|
||||
LMB3_ReadStrobe => '0',
|
||||
LMB3_WriteStrobe => '0',
|
||||
LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
BRAM_Rst_A => BRAM_Rst_A,
|
||||
BRAM_Clk_A => BRAM_Clk_A,
|
||||
BRAM_Addr_A => BRAM_Addr_A,
|
||||
BRAM_EN_A => BRAM_EN_A,
|
||||
BRAM_WEN_A => BRAM_WEN_A,
|
||||
BRAM_Dout_A => BRAM_Dout_A,
|
||||
BRAM_Din_A => BRAM_Din_A,
|
||||
S_AXI_CTRL_ACLK => '0',
|
||||
S_AXI_CTRL_ARESETN => '0',
|
||||
S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
S_AXI_CTRL_AWVALID => '0',
|
||||
S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
S_AXI_CTRL_WVALID => '0',
|
||||
S_AXI_CTRL_BREADY => '0',
|
||||
S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
S_AXI_CTRL_ARVALID => '0',
|
||||
S_AXI_CTRL_RREADY => '0'
|
||||
);
|
||||
END system_bd_dlmb_bram_if_cntlr_0_arch;
|
||||
+302
@@ -0,0 +1,302 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
|
||||
-- IP Revision: 16
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY lmb_bram_if_cntlr_v4_0_16;
|
||||
USE lmb_bram_if_cntlr_v4_0_16.lmb_bram_if_cntlr;
|
||||
|
||||
ENTITY system_bd_dlmb_bram_if_cntlr_0 IS
|
||||
PORT (
|
||||
LMB_Clk : IN STD_LOGIC;
|
||||
LMB_Rst : IN STD_LOGIC;
|
||||
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_AddrStrobe : IN STD_LOGIC;
|
||||
LMB_ReadStrobe : IN STD_LOGIC;
|
||||
LMB_WriteStrobe : IN STD_LOGIC;
|
||||
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl_Ready : OUT STD_LOGIC;
|
||||
Sl_Wait : OUT STD_LOGIC;
|
||||
Sl_UE : OUT STD_LOGIC;
|
||||
Sl_CE : OUT STD_LOGIC;
|
||||
BRAM_Rst_A : OUT STD_LOGIC;
|
||||
BRAM_Clk_A : OUT STD_LOGIC;
|
||||
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
BRAM_EN_A : OUT STD_LOGIC;
|
||||
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
|
||||
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
|
||||
);
|
||||
END system_bd_dlmb_bram_if_cntlr_0;
|
||||
|
||||
ARCHITECTURE system_bd_dlmb_bram_if_cntlr_0_arch OF system_bd_dlmb_bram_if_cntlr_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT lmb_bram_if_cntlr IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_HIGHADDR : STD_LOGIC_VECTOR;
|
||||
C_BASEADDR : STD_LOGIC_VECTOR;
|
||||
C_NUM_LMB : INTEGER;
|
||||
C_MASK : STD_LOGIC_VECTOR;
|
||||
C_MASK1 : STD_LOGIC_VECTOR;
|
||||
C_MASK2 : STD_LOGIC_VECTOR;
|
||||
C_MASK3 : STD_LOGIC_VECTOR;
|
||||
C_LMB_AWIDTH : INTEGER;
|
||||
C_LMB_DWIDTH : INTEGER;
|
||||
C_ECC : INTEGER;
|
||||
C_INTERCONNECT : INTEGER;
|
||||
C_FAULT_INJECT : INTEGER;
|
||||
C_CE_FAILING_REGISTERS : INTEGER;
|
||||
C_UE_FAILING_REGISTERS : INTEGER;
|
||||
C_ECC_STATUS_REGISTERS : INTEGER;
|
||||
C_ECC_ONOFF_REGISTER : INTEGER;
|
||||
C_ECC_ONOFF_RESET_VALUE : INTEGER;
|
||||
C_CE_COUNTER_WIDTH : INTEGER;
|
||||
C_WRITE_ACCESS : INTEGER;
|
||||
C_BRAM_AWIDTH : INTEGER;
|
||||
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
LMB_Clk : IN STD_LOGIC;
|
||||
LMB_Rst : IN STD_LOGIC;
|
||||
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_AddrStrobe : IN STD_LOGIC;
|
||||
LMB_ReadStrobe : IN STD_LOGIC;
|
||||
LMB_WriteStrobe : IN STD_LOGIC;
|
||||
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl_Ready : OUT STD_LOGIC;
|
||||
Sl_Wait : OUT STD_LOGIC;
|
||||
Sl_UE : OUT STD_LOGIC;
|
||||
Sl_CE : OUT STD_LOGIC;
|
||||
LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB1_AddrStrobe : IN STD_LOGIC;
|
||||
LMB1_ReadStrobe : IN STD_LOGIC;
|
||||
LMB1_WriteStrobe : IN STD_LOGIC;
|
||||
LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl1_Ready : OUT STD_LOGIC;
|
||||
Sl1_Wait : OUT STD_LOGIC;
|
||||
Sl1_UE : OUT STD_LOGIC;
|
||||
Sl1_CE : OUT STD_LOGIC;
|
||||
LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB2_AddrStrobe : IN STD_LOGIC;
|
||||
LMB2_ReadStrobe : IN STD_LOGIC;
|
||||
LMB2_WriteStrobe : IN STD_LOGIC;
|
||||
LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl2_Ready : OUT STD_LOGIC;
|
||||
Sl2_Wait : OUT STD_LOGIC;
|
||||
Sl2_UE : OUT STD_LOGIC;
|
||||
Sl2_CE : OUT STD_LOGIC;
|
||||
LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB3_AddrStrobe : IN STD_LOGIC;
|
||||
LMB3_ReadStrobe : IN STD_LOGIC;
|
||||
LMB3_WriteStrobe : IN STD_LOGIC;
|
||||
LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl3_Ready : OUT STD_LOGIC;
|
||||
Sl3_Wait : OUT STD_LOGIC;
|
||||
Sl3_UE : OUT STD_LOGIC;
|
||||
Sl3_CE : OUT STD_LOGIC;
|
||||
BRAM_Rst_A : OUT STD_LOGIC;
|
||||
BRAM_Clk_A : OUT STD_LOGIC;
|
||||
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
BRAM_EN_A : OUT STD_LOGIC;
|
||||
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
|
||||
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
S_AXI_CTRL_ACLK : IN STD_LOGIC;
|
||||
S_AXI_CTRL_ARESETN : IN STD_LOGIC;
|
||||
S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_CTRL_AWVALID : IN STD_LOGIC;
|
||||
S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXI_CTRL_WVALID : IN STD_LOGIC;
|
||||
S_AXI_CTRL_WREADY : OUT STD_LOGIC;
|
||||
S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_CTRL_BVALID : OUT STD_LOGIC;
|
||||
S_AXI_CTRL_BREADY : IN STD_LOGIC;
|
||||
S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_CTRL_ARVALID : IN STD_LOGIC;
|
||||
S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_CTRL_RVALID : OUT STD_LOGIC;
|
||||
S_AXI_CTRL_RREADY : IN STD_LOGIC;
|
||||
UE : OUT STD_LOGIC;
|
||||
CE : OUT STD_LOGIC;
|
||||
Interrupt : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT lmb_bram_if_cntlr;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_bd_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "lmb_bram_if_cntlr,Vivado 2019.1.3";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_bd_dlmb_bram_if_cntlr_0_arch : ARCHITECTURE IS "system_bd_dlmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_bd_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "system_bd_dlmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{x_ipProduct=Vivado 2019.1.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_bram_if_cntlr,x_ipVersion=4.0,x_ipCoreRevision=16,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=kintex7,C_HIGHADDR=0x000000000003FFFF,C_BASEADDR=0x0000000000000000,C_NUM_LMB=1,C_MASK=0x0000000040000000,C_MASK1=0x0000000000800000,C_MASK2=0x0000000000800000,C_MASK3=0x0000000000800000,C_LMB_AWIDTH=32,C_LMB_DWIDTH=32,C_ECC=0,C_INTERCONNECT=0,C_FAULT_INJECT=0,C_CE_FAIL" &
|
||||
"ING_REGISTERS=0,C_UE_FAILING_REGISTERS=0,C_ECC_STATUS_REGISTERS=0,C_ECC_ONOFF_REGISTER=0,C_ECC_ONOFF_RESET_VALUE=1,C_CE_COUNTER_WIDTH=0,C_WRITE_ACCESS=2,C_BRAM_AWIDTH=32,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF BRAM_Rst_A: SIGNAL IS "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 262144, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_ABus: SIGNAL IS "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Rst: SIGNAL IS "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Clk: SIGNAL IS "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
|
||||
BEGIN
|
||||
U0 : lmb_bram_if_cntlr
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "kintex7",
|
||||
C_HIGHADDR => X"000000000003FFFF",
|
||||
C_BASEADDR => X"0000000000000000",
|
||||
C_NUM_LMB => 1,
|
||||
C_MASK => X"0000000040000000",
|
||||
C_MASK1 => X"0000000000800000",
|
||||
C_MASK2 => X"0000000000800000",
|
||||
C_MASK3 => X"0000000000800000",
|
||||
C_LMB_AWIDTH => 32,
|
||||
C_LMB_DWIDTH => 32,
|
||||
C_ECC => 0,
|
||||
C_INTERCONNECT => 0,
|
||||
C_FAULT_INJECT => 0,
|
||||
C_CE_FAILING_REGISTERS => 0,
|
||||
C_UE_FAILING_REGISTERS => 0,
|
||||
C_ECC_STATUS_REGISTERS => 0,
|
||||
C_ECC_ONOFF_REGISTER => 0,
|
||||
C_ECC_ONOFF_RESET_VALUE => 1,
|
||||
C_CE_COUNTER_WIDTH => 0,
|
||||
C_WRITE_ACCESS => 2,
|
||||
C_BRAM_AWIDTH => 32,
|
||||
C_S_AXI_CTRL_ADDR_WIDTH => 32,
|
||||
C_S_AXI_CTRL_DATA_WIDTH => 32
|
||||
)
|
||||
PORT MAP (
|
||||
LMB_Clk => LMB_Clk,
|
||||
LMB_Rst => LMB_Rst,
|
||||
LMB_ABus => LMB_ABus,
|
||||
LMB_WriteDBus => LMB_WriteDBus,
|
||||
LMB_AddrStrobe => LMB_AddrStrobe,
|
||||
LMB_ReadStrobe => LMB_ReadStrobe,
|
||||
LMB_WriteStrobe => LMB_WriteStrobe,
|
||||
LMB_BE => LMB_BE,
|
||||
Sl_DBus => Sl_DBus,
|
||||
Sl_Ready => Sl_Ready,
|
||||
Sl_Wait => Sl_Wait,
|
||||
Sl_UE => Sl_UE,
|
||||
Sl_CE => Sl_CE,
|
||||
LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB1_AddrStrobe => '0',
|
||||
LMB1_ReadStrobe => '0',
|
||||
LMB1_WriteStrobe => '0',
|
||||
LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB2_AddrStrobe => '0',
|
||||
LMB2_ReadStrobe => '0',
|
||||
LMB2_WriteStrobe => '0',
|
||||
LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB3_AddrStrobe => '0',
|
||||
LMB3_ReadStrobe => '0',
|
||||
LMB3_WriteStrobe => '0',
|
||||
LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
BRAM_Rst_A => BRAM_Rst_A,
|
||||
BRAM_Clk_A => BRAM_Clk_A,
|
||||
BRAM_Addr_A => BRAM_Addr_A,
|
||||
BRAM_EN_A => BRAM_EN_A,
|
||||
BRAM_WEN_A => BRAM_WEN_A,
|
||||
BRAM_Dout_A => BRAM_Dout_A,
|
||||
BRAM_Din_A => BRAM_Din_A,
|
||||
S_AXI_CTRL_ACLK => '0',
|
||||
S_AXI_CTRL_ARESETN => '0',
|
||||
S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
S_AXI_CTRL_AWVALID => '0',
|
||||
S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
S_AXI_CTRL_WVALID => '0',
|
||||
S_AXI_CTRL_BREADY => '0',
|
||||
S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
S_AXI_CTRL_ARVALID => '0',
|
||||
S_AXI_CTRL_RREADY => '0'
|
||||
);
|
||||
END system_bd_dlmb_bram_if_cntlr_0_arch;
|
||||
BIN
Binary file not shown.
+164
@@ -0,0 +1,164 @@
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||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+4206
File diff suppressed because it is too large
Load Diff
+57
@@ -0,0 +1,57 @@
|
||||
# (c) Copyright 2012-2023 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 40 -name LMB_Clk [get_ports LMB_Clk]
|
||||
|
||||
|
||||
+683
@@ -0,0 +1,683 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:57:09 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top system_bd_dlmb_bram_if_cntlr_0 -prefix
|
||||
// system_bd_dlmb_bram_if_cntlr_0_ system_bd_dlmb_bram_if_cntlr_0_sim_netlist.v
|
||||
// Design : system_bd_dlmb_bram_if_cntlr_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* C_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_BRAM_AWIDTH = "32" *) (* C_CE_COUNTER_WIDTH = "0" *)
|
||||
(* C_CE_FAILING_REGISTERS = "0" *) (* C_ECC = "0" *) (* C_ECC_ONOFF_REGISTER = "0" *)
|
||||
(* C_ECC_ONOFF_RESET_VALUE = "1" *) (* C_ECC_STATUS_REGISTERS = "0" *) (* C_FAMILY = "kintex7" *)
|
||||
(* C_FAULT_INJECT = "0" *) (* C_HIGHADDR = "64'b0000000000000000000000000000000000000000000000111111111111111111" *) (* C_INTERCONNECT = "0" *)
|
||||
(* C_LMB_AWIDTH = "32" *) (* C_LMB_DWIDTH = "32" *) (* C_MASK = "64'b0000000000000000000000000000000001000000000000000000000000000000" *)
|
||||
(* C_MASK1 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_MASK2 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_MASK3 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
|
||||
(* C_NUM_LMB = "1" *) (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *) (* C_S_AXI_CTRL_BASEADDR = "32'b11111111111111111111111111111111" *)
|
||||
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *) (* C_S_AXI_CTRL_HIGHADDR = "32'b00000000000000000000000000000000" *) (* C_UE_FAILING_REGISTERS = "0" *)
|
||||
(* C_WRITE_ACCESS = "2" *)
|
||||
module system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr
|
||||
(LMB_Clk,
|
||||
LMB_Rst,
|
||||
LMB_ABus,
|
||||
LMB_WriteDBus,
|
||||
LMB_AddrStrobe,
|
||||
LMB_ReadStrobe,
|
||||
LMB_WriteStrobe,
|
||||
LMB_BE,
|
||||
Sl_DBus,
|
||||
Sl_Ready,
|
||||
Sl_Wait,
|
||||
Sl_UE,
|
||||
Sl_CE,
|
||||
LMB1_ABus,
|
||||
LMB1_WriteDBus,
|
||||
LMB1_AddrStrobe,
|
||||
LMB1_ReadStrobe,
|
||||
LMB1_WriteStrobe,
|
||||
LMB1_BE,
|
||||
Sl1_DBus,
|
||||
Sl1_Ready,
|
||||
Sl1_Wait,
|
||||
Sl1_UE,
|
||||
Sl1_CE,
|
||||
LMB2_ABus,
|
||||
LMB2_WriteDBus,
|
||||
LMB2_AddrStrobe,
|
||||
LMB2_ReadStrobe,
|
||||
LMB2_WriteStrobe,
|
||||
LMB2_BE,
|
||||
Sl2_DBus,
|
||||
Sl2_Ready,
|
||||
Sl2_Wait,
|
||||
Sl2_UE,
|
||||
Sl2_CE,
|
||||
LMB3_ABus,
|
||||
LMB3_WriteDBus,
|
||||
LMB3_AddrStrobe,
|
||||
LMB3_ReadStrobe,
|
||||
LMB3_WriteStrobe,
|
||||
LMB3_BE,
|
||||
Sl3_DBus,
|
||||
Sl3_Ready,
|
||||
Sl3_Wait,
|
||||
Sl3_UE,
|
||||
Sl3_CE,
|
||||
BRAM_Rst_A,
|
||||
BRAM_Clk_A,
|
||||
BRAM_Addr_A,
|
||||
BRAM_EN_A,
|
||||
BRAM_WEN_A,
|
||||
BRAM_Dout_A,
|
||||
BRAM_Din_A,
|
||||
S_AXI_CTRL_ACLK,
|
||||
S_AXI_CTRL_ARESETN,
|
||||
S_AXI_CTRL_AWADDR,
|
||||
S_AXI_CTRL_AWVALID,
|
||||
S_AXI_CTRL_AWREADY,
|
||||
S_AXI_CTRL_WDATA,
|
||||
S_AXI_CTRL_WSTRB,
|
||||
S_AXI_CTRL_WVALID,
|
||||
S_AXI_CTRL_WREADY,
|
||||
S_AXI_CTRL_BRESP,
|
||||
S_AXI_CTRL_BVALID,
|
||||
S_AXI_CTRL_BREADY,
|
||||
S_AXI_CTRL_ARADDR,
|
||||
S_AXI_CTRL_ARVALID,
|
||||
S_AXI_CTRL_ARREADY,
|
||||
S_AXI_CTRL_RDATA,
|
||||
S_AXI_CTRL_RRESP,
|
||||
S_AXI_CTRL_RVALID,
|
||||
S_AXI_CTRL_RREADY,
|
||||
UE,
|
||||
CE,
|
||||
Interrupt);
|
||||
input LMB_Clk;
|
||||
input LMB_Rst;
|
||||
input [0:31]LMB_ABus;
|
||||
input [0:31]LMB_WriteDBus;
|
||||
input LMB_AddrStrobe;
|
||||
input LMB_ReadStrobe;
|
||||
input LMB_WriteStrobe;
|
||||
input [0:3]LMB_BE;
|
||||
output [0:31]Sl_DBus;
|
||||
output Sl_Ready;
|
||||
output Sl_Wait;
|
||||
output Sl_UE;
|
||||
output Sl_CE;
|
||||
input [0:31]LMB1_ABus;
|
||||
input [0:31]LMB1_WriteDBus;
|
||||
input LMB1_AddrStrobe;
|
||||
input LMB1_ReadStrobe;
|
||||
input LMB1_WriteStrobe;
|
||||
input [0:3]LMB1_BE;
|
||||
output [0:31]Sl1_DBus;
|
||||
output Sl1_Ready;
|
||||
output Sl1_Wait;
|
||||
output Sl1_UE;
|
||||
output Sl1_CE;
|
||||
input [0:31]LMB2_ABus;
|
||||
input [0:31]LMB2_WriteDBus;
|
||||
input LMB2_AddrStrobe;
|
||||
input LMB2_ReadStrobe;
|
||||
input LMB2_WriteStrobe;
|
||||
input [0:3]LMB2_BE;
|
||||
output [0:31]Sl2_DBus;
|
||||
output Sl2_Ready;
|
||||
output Sl2_Wait;
|
||||
output Sl2_UE;
|
||||
output Sl2_CE;
|
||||
input [0:31]LMB3_ABus;
|
||||
input [0:31]LMB3_WriteDBus;
|
||||
input LMB3_AddrStrobe;
|
||||
input LMB3_ReadStrobe;
|
||||
input LMB3_WriteStrobe;
|
||||
input [0:3]LMB3_BE;
|
||||
output [0:31]Sl3_DBus;
|
||||
output Sl3_Ready;
|
||||
output Sl3_Wait;
|
||||
output Sl3_UE;
|
||||
output Sl3_CE;
|
||||
output BRAM_Rst_A;
|
||||
output BRAM_Clk_A;
|
||||
output [0:31]BRAM_Addr_A;
|
||||
output BRAM_EN_A;
|
||||
output [0:3]BRAM_WEN_A;
|
||||
output [0:31]BRAM_Dout_A;
|
||||
input [0:31]BRAM_Din_A;
|
||||
input S_AXI_CTRL_ACLK;
|
||||
input S_AXI_CTRL_ARESETN;
|
||||
input [31:0]S_AXI_CTRL_AWADDR;
|
||||
input S_AXI_CTRL_AWVALID;
|
||||
output S_AXI_CTRL_AWREADY;
|
||||
input [31:0]S_AXI_CTRL_WDATA;
|
||||
input [3:0]S_AXI_CTRL_WSTRB;
|
||||
input S_AXI_CTRL_WVALID;
|
||||
output S_AXI_CTRL_WREADY;
|
||||
output [1:0]S_AXI_CTRL_BRESP;
|
||||
output S_AXI_CTRL_BVALID;
|
||||
input S_AXI_CTRL_BREADY;
|
||||
input [31:0]S_AXI_CTRL_ARADDR;
|
||||
input S_AXI_CTRL_ARVALID;
|
||||
output S_AXI_CTRL_ARREADY;
|
||||
output [31:0]S_AXI_CTRL_RDATA;
|
||||
output [1:0]S_AXI_CTRL_RRESP;
|
||||
output S_AXI_CTRL_RVALID;
|
||||
input S_AXI_CTRL_RREADY;
|
||||
output UE;
|
||||
output CE;
|
||||
output Interrupt;
|
||||
|
||||
wire \<const0> ;
|
||||
wire [0:31]BRAM_Din_A;
|
||||
wire [0:3]BRAM_WEN_A;
|
||||
wire [0:31]LMB_ABus;
|
||||
wire LMB_AddrStrobe;
|
||||
wire [0:3]LMB_BE;
|
||||
wire LMB_Clk;
|
||||
wire LMB_Rst;
|
||||
wire [0:31]LMB_WriteDBus;
|
||||
wire LMB_WriteStrobe;
|
||||
wire \No_ECC.Sl_Rdy_i_1_n_0 ;
|
||||
wire \No_ECC.lmb_as_i_1_n_0 ;
|
||||
wire Sl_Rdy;
|
||||
wire Sl_Ready;
|
||||
wire lmb_as;
|
||||
|
||||
assign BRAM_Addr_A[0:31] = LMB_ABus;
|
||||
assign BRAM_Clk_A = LMB_Clk;
|
||||
assign BRAM_Dout_A[0:31] = LMB_WriteDBus;
|
||||
assign BRAM_EN_A = LMB_AddrStrobe;
|
||||
assign BRAM_Rst_A = \<const0> ;
|
||||
assign CE = \<const0> ;
|
||||
assign Interrupt = \<const0> ;
|
||||
assign S_AXI_CTRL_ARREADY = \<const0> ;
|
||||
assign S_AXI_CTRL_AWREADY = \<const0> ;
|
||||
assign S_AXI_CTRL_BRESP[1] = \<const0> ;
|
||||
assign S_AXI_CTRL_BRESP[0] = \<const0> ;
|
||||
assign S_AXI_CTRL_BVALID = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[31] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[30] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[29] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[28] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[27] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[26] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[25] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[24] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[23] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[22] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[21] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[20] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[19] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[18] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[17] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[16] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[15] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[14] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[13] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[12] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[11] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[10] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[9] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[8] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[7] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[6] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[5] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[4] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[3] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[2] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[1] = \<const0> ;
|
||||
assign S_AXI_CTRL_RDATA[0] = \<const0> ;
|
||||
assign S_AXI_CTRL_RRESP[1] = \<const0> ;
|
||||
assign S_AXI_CTRL_RRESP[0] = \<const0> ;
|
||||
assign S_AXI_CTRL_RVALID = \<const0> ;
|
||||
assign S_AXI_CTRL_WREADY = \<const0> ;
|
||||
assign Sl1_CE = \<const0> ;
|
||||
assign Sl1_DBus[0] = \<const0> ;
|
||||
assign Sl1_DBus[1] = \<const0> ;
|
||||
assign Sl1_DBus[2] = \<const0> ;
|
||||
assign Sl1_DBus[3] = \<const0> ;
|
||||
assign Sl1_DBus[4] = \<const0> ;
|
||||
assign Sl1_DBus[5] = \<const0> ;
|
||||
assign Sl1_DBus[6] = \<const0> ;
|
||||
assign Sl1_DBus[7] = \<const0> ;
|
||||
assign Sl1_DBus[8] = \<const0> ;
|
||||
assign Sl1_DBus[9] = \<const0> ;
|
||||
assign Sl1_DBus[10] = \<const0> ;
|
||||
assign Sl1_DBus[11] = \<const0> ;
|
||||
assign Sl1_DBus[12] = \<const0> ;
|
||||
assign Sl1_DBus[13] = \<const0> ;
|
||||
assign Sl1_DBus[14] = \<const0> ;
|
||||
assign Sl1_DBus[15] = \<const0> ;
|
||||
assign Sl1_DBus[16] = \<const0> ;
|
||||
assign Sl1_DBus[17] = \<const0> ;
|
||||
assign Sl1_DBus[18] = \<const0> ;
|
||||
assign Sl1_DBus[19] = \<const0> ;
|
||||
assign Sl1_DBus[20] = \<const0> ;
|
||||
assign Sl1_DBus[21] = \<const0> ;
|
||||
assign Sl1_DBus[22] = \<const0> ;
|
||||
assign Sl1_DBus[23] = \<const0> ;
|
||||
assign Sl1_DBus[24] = \<const0> ;
|
||||
assign Sl1_DBus[25] = \<const0> ;
|
||||
assign Sl1_DBus[26] = \<const0> ;
|
||||
assign Sl1_DBus[27] = \<const0> ;
|
||||
assign Sl1_DBus[28] = \<const0> ;
|
||||
assign Sl1_DBus[29] = \<const0> ;
|
||||
assign Sl1_DBus[30] = \<const0> ;
|
||||
assign Sl1_DBus[31] = \<const0> ;
|
||||
assign Sl1_Ready = \<const0> ;
|
||||
assign Sl1_UE = \<const0> ;
|
||||
assign Sl1_Wait = \<const0> ;
|
||||
assign Sl2_CE = \<const0> ;
|
||||
assign Sl2_DBus[0] = \<const0> ;
|
||||
assign Sl2_DBus[1] = \<const0> ;
|
||||
assign Sl2_DBus[2] = \<const0> ;
|
||||
assign Sl2_DBus[3] = \<const0> ;
|
||||
assign Sl2_DBus[4] = \<const0> ;
|
||||
assign Sl2_DBus[5] = \<const0> ;
|
||||
assign Sl2_DBus[6] = \<const0> ;
|
||||
assign Sl2_DBus[7] = \<const0> ;
|
||||
assign Sl2_DBus[8] = \<const0> ;
|
||||
assign Sl2_DBus[9] = \<const0> ;
|
||||
assign Sl2_DBus[10] = \<const0> ;
|
||||
assign Sl2_DBus[11] = \<const0> ;
|
||||
assign Sl2_DBus[12] = \<const0> ;
|
||||
assign Sl2_DBus[13] = \<const0> ;
|
||||
assign Sl2_DBus[14] = \<const0> ;
|
||||
assign Sl2_DBus[15] = \<const0> ;
|
||||
assign Sl2_DBus[16] = \<const0> ;
|
||||
assign Sl2_DBus[17] = \<const0> ;
|
||||
assign Sl2_DBus[18] = \<const0> ;
|
||||
assign Sl2_DBus[19] = \<const0> ;
|
||||
assign Sl2_DBus[20] = \<const0> ;
|
||||
assign Sl2_DBus[21] = \<const0> ;
|
||||
assign Sl2_DBus[22] = \<const0> ;
|
||||
assign Sl2_DBus[23] = \<const0> ;
|
||||
assign Sl2_DBus[24] = \<const0> ;
|
||||
assign Sl2_DBus[25] = \<const0> ;
|
||||
assign Sl2_DBus[26] = \<const0> ;
|
||||
assign Sl2_DBus[27] = \<const0> ;
|
||||
assign Sl2_DBus[28] = \<const0> ;
|
||||
assign Sl2_DBus[29] = \<const0> ;
|
||||
assign Sl2_DBus[30] = \<const0> ;
|
||||
assign Sl2_DBus[31] = \<const0> ;
|
||||
assign Sl2_Ready = \<const0> ;
|
||||
assign Sl2_UE = \<const0> ;
|
||||
assign Sl2_Wait = \<const0> ;
|
||||
assign Sl3_CE = \<const0> ;
|
||||
assign Sl3_DBus[0] = \<const0> ;
|
||||
assign Sl3_DBus[1] = \<const0> ;
|
||||
assign Sl3_DBus[2] = \<const0> ;
|
||||
assign Sl3_DBus[3] = \<const0> ;
|
||||
assign Sl3_DBus[4] = \<const0> ;
|
||||
assign Sl3_DBus[5] = \<const0> ;
|
||||
assign Sl3_DBus[6] = \<const0> ;
|
||||
assign Sl3_DBus[7] = \<const0> ;
|
||||
assign Sl3_DBus[8] = \<const0> ;
|
||||
assign Sl3_DBus[9] = \<const0> ;
|
||||
assign Sl3_DBus[10] = \<const0> ;
|
||||
assign Sl3_DBus[11] = \<const0> ;
|
||||
assign Sl3_DBus[12] = \<const0> ;
|
||||
assign Sl3_DBus[13] = \<const0> ;
|
||||
assign Sl3_DBus[14] = \<const0> ;
|
||||
assign Sl3_DBus[15] = \<const0> ;
|
||||
assign Sl3_DBus[16] = \<const0> ;
|
||||
assign Sl3_DBus[17] = \<const0> ;
|
||||
assign Sl3_DBus[18] = \<const0> ;
|
||||
assign Sl3_DBus[19] = \<const0> ;
|
||||
assign Sl3_DBus[20] = \<const0> ;
|
||||
assign Sl3_DBus[21] = \<const0> ;
|
||||
assign Sl3_DBus[22] = \<const0> ;
|
||||
assign Sl3_DBus[23] = \<const0> ;
|
||||
assign Sl3_DBus[24] = \<const0> ;
|
||||
assign Sl3_DBus[25] = \<const0> ;
|
||||
assign Sl3_DBus[26] = \<const0> ;
|
||||
assign Sl3_DBus[27] = \<const0> ;
|
||||
assign Sl3_DBus[28] = \<const0> ;
|
||||
assign Sl3_DBus[29] = \<const0> ;
|
||||
assign Sl3_DBus[30] = \<const0> ;
|
||||
assign Sl3_DBus[31] = \<const0> ;
|
||||
assign Sl3_Ready = \<const0> ;
|
||||
assign Sl3_UE = \<const0> ;
|
||||
assign Sl3_Wait = \<const0> ;
|
||||
assign Sl_CE = \<const0> ;
|
||||
assign Sl_DBus[0:31] = BRAM_Din_A;
|
||||
assign Sl_UE = \<const0> ;
|
||||
assign Sl_Wait = \<const0> ;
|
||||
assign UE = \<const0> ;
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT3 #(
|
||||
.INIT(8'h20))
|
||||
\BRAM_WEN_A[0]_INST_0
|
||||
(.I0(LMB_BE[0]),
|
||||
.I1(LMB_ABus[1]),
|
||||
.I2(LMB_WriteStrobe),
|
||||
.O(BRAM_WEN_A[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT3 #(
|
||||
.INIT(8'h40))
|
||||
\BRAM_WEN_A[1]_INST_0
|
||||
(.I0(LMB_ABus[1]),
|
||||
.I1(LMB_WriteStrobe),
|
||||
.I2(LMB_BE[1]),
|
||||
.O(BRAM_WEN_A[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT3 #(
|
||||
.INIT(8'h40))
|
||||
\BRAM_WEN_A[2]_INST_0
|
||||
(.I0(LMB_ABus[1]),
|
||||
.I1(LMB_WriteStrobe),
|
||||
.I2(LMB_BE[2]),
|
||||
.O(BRAM_WEN_A[2]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT3 #(
|
||||
.INIT(8'h40))
|
||||
\BRAM_WEN_A[3]_INST_0
|
||||
(.I0(LMB_ABus[1]),
|
||||
.I1(LMB_WriteStrobe),
|
||||
.I2(LMB_BE[3]),
|
||||
.O(BRAM_WEN_A[3]));
|
||||
GND GND
|
||||
(.G(\<const0> ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h1))
|
||||
\No_ECC.Sl_Rdy_i_1
|
||||
(.I0(LMB_ABus[1]),
|
||||
.I1(LMB_Rst),
|
||||
.O(\No_ECC.Sl_Rdy_i_1_n_0 ));
|
||||
FDRE \No_ECC.Sl_Rdy_reg
|
||||
(.C(LMB_Clk),
|
||||
.CE(1'b1),
|
||||
.D(\No_ECC.Sl_Rdy_i_1_n_0 ),
|
||||
.Q(Sl_Rdy),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
\No_ECC.lmb_as_i_1
|
||||
(.I0(LMB_AddrStrobe),
|
||||
.I1(LMB_Rst),
|
||||
.O(\No_ECC.lmb_as_i_1_n_0 ));
|
||||
FDRE \No_ECC.lmb_as_reg
|
||||
(.C(LMB_Clk),
|
||||
.CE(1'b1),
|
||||
.D(\No_ECC.lmb_as_i_1_n_0 ),
|
||||
.Q(lmb_as),
|
||||
.R(1'b0));
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
Sl_Ready_INST_0
|
||||
(.I0(Sl_Rdy),
|
||||
.I1(lmb_as),
|
||||
.O(Sl_Ready));
|
||||
endmodule
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "system_bd_dlmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "lmb_bram_if_cntlr,Vivado 2019.1.3" *)
|
||||
(* NotValidForBitStream *)
|
||||
module system_bd_dlmb_bram_if_cntlr_0
|
||||
(LMB_Clk,
|
||||
LMB_Rst,
|
||||
LMB_ABus,
|
||||
LMB_WriteDBus,
|
||||
LMB_AddrStrobe,
|
||||
LMB_ReadStrobe,
|
||||
LMB_WriteStrobe,
|
||||
LMB_BE,
|
||||
Sl_DBus,
|
||||
Sl_Ready,
|
||||
Sl_Wait,
|
||||
Sl_UE,
|
||||
Sl_CE,
|
||||
BRAM_Rst_A,
|
||||
BRAM_Clk_A,
|
||||
BRAM_Addr_A,
|
||||
BRAM_EN_A,
|
||||
BRAM_WEN_A,
|
||||
BRAM_Dout_A,
|
||||
BRAM_Din_A);
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input LMB_Clk;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) input LMB_Rst;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ABUS" *) (* x_interface_parameter = "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE" *) input [0:31]LMB_ABus;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS" *) input [0:31]LMB_WriteDBus;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE" *) input LMB_AddrStrobe;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READSTROBE" *) input LMB_ReadStrobe;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE" *) input LMB_WriteStrobe;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB BE" *) input [0:3]LMB_BE;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READDBUS" *) output [0:31]Sl_DBus;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READY" *) output Sl_Ready;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WAIT" *) output Sl_Wait;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB UE" *) output Sl_UE;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB CE" *) output Sl_CE;
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT RST" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 262144, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1" *) output BRAM_Rst_A;
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT CLK" *) output BRAM_Clk_A;
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR" *) output [0:31]BRAM_Addr_A;
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT EN" *) output BRAM_EN_A;
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT WE" *) output [0:3]BRAM_WEN_A;
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DIN" *) output [0:31]BRAM_Dout_A;
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT" *) input [0:31]BRAM_Din_A;
|
||||
|
||||
wire [0:31]BRAM_Addr_A;
|
||||
wire BRAM_Clk_A;
|
||||
wire [0:31]BRAM_Din_A;
|
||||
wire [0:31]BRAM_Dout_A;
|
||||
wire BRAM_EN_A;
|
||||
wire BRAM_Rst_A;
|
||||
wire [0:3]BRAM_WEN_A;
|
||||
wire [0:31]LMB_ABus;
|
||||
wire LMB_AddrStrobe;
|
||||
wire [0:3]LMB_BE;
|
||||
wire LMB_Clk;
|
||||
wire LMB_ReadStrobe;
|
||||
wire LMB_Rst;
|
||||
wire [0:31]LMB_WriteDBus;
|
||||
wire LMB_WriteStrobe;
|
||||
wire Sl_CE;
|
||||
wire [0:31]Sl_DBus;
|
||||
wire Sl_Ready;
|
||||
wire Sl_UE;
|
||||
wire Sl_Wait;
|
||||
wire NLW_U0_CE_UNCONNECTED;
|
||||
wire NLW_U0_Interrupt_UNCONNECTED;
|
||||
wire NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED;
|
||||
wire NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED;
|
||||
wire NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED;
|
||||
wire NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED;
|
||||
wire NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED;
|
||||
wire NLW_U0_Sl1_CE_UNCONNECTED;
|
||||
wire NLW_U0_Sl1_Ready_UNCONNECTED;
|
||||
wire NLW_U0_Sl1_UE_UNCONNECTED;
|
||||
wire NLW_U0_Sl1_Wait_UNCONNECTED;
|
||||
wire NLW_U0_Sl2_CE_UNCONNECTED;
|
||||
wire NLW_U0_Sl2_Ready_UNCONNECTED;
|
||||
wire NLW_U0_Sl2_UE_UNCONNECTED;
|
||||
wire NLW_U0_Sl2_Wait_UNCONNECTED;
|
||||
wire NLW_U0_Sl3_CE_UNCONNECTED;
|
||||
wire NLW_U0_Sl3_Ready_UNCONNECTED;
|
||||
wire NLW_U0_Sl3_UE_UNCONNECTED;
|
||||
wire NLW_U0_Sl3_Wait_UNCONNECTED;
|
||||
wire NLW_U0_UE_UNCONNECTED;
|
||||
wire [1:0]NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED;
|
||||
wire [31:0]NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED;
|
||||
wire [1:0]NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED;
|
||||
wire [0:31]NLW_U0_Sl1_DBus_UNCONNECTED;
|
||||
wire [0:31]NLW_U0_Sl2_DBus_UNCONNECTED;
|
||||
wire [0:31]NLW_U0_Sl3_DBus_UNCONNECTED;
|
||||
|
||||
(* C_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
|
||||
(* C_BRAM_AWIDTH = "32" *)
|
||||
(* C_CE_COUNTER_WIDTH = "0" *)
|
||||
(* C_CE_FAILING_REGISTERS = "0" *)
|
||||
(* C_ECC = "0" *)
|
||||
(* C_ECC_ONOFF_REGISTER = "0" *)
|
||||
(* C_ECC_ONOFF_RESET_VALUE = "1" *)
|
||||
(* C_ECC_STATUS_REGISTERS = "0" *)
|
||||
(* C_FAMILY = "kintex7" *)
|
||||
(* C_FAULT_INJECT = "0" *)
|
||||
(* C_HIGHADDR = "64'b0000000000000000000000000000000000000000000000111111111111111111" *)
|
||||
(* C_INTERCONNECT = "0" *)
|
||||
(* C_LMB_AWIDTH = "32" *)
|
||||
(* C_LMB_DWIDTH = "32" *)
|
||||
(* C_MASK = "64'b0000000000000000000000000000000001000000000000000000000000000000" *)
|
||||
(* C_MASK1 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
|
||||
(* C_MASK2 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
|
||||
(* C_MASK3 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
|
||||
(* C_NUM_LMB = "1" *)
|
||||
(* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
|
||||
(* C_S_AXI_CTRL_BASEADDR = "32'b11111111111111111111111111111111" *)
|
||||
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *)
|
||||
(* C_S_AXI_CTRL_HIGHADDR = "32'b00000000000000000000000000000000" *)
|
||||
(* C_UE_FAILING_REGISTERS = "0" *)
|
||||
(* C_WRITE_ACCESS = "2" *)
|
||||
system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr U0
|
||||
(.BRAM_Addr_A(BRAM_Addr_A),
|
||||
.BRAM_Clk_A(BRAM_Clk_A),
|
||||
.BRAM_Din_A(BRAM_Din_A),
|
||||
.BRAM_Dout_A(BRAM_Dout_A),
|
||||
.BRAM_EN_A(BRAM_EN_A),
|
||||
.BRAM_Rst_A(BRAM_Rst_A),
|
||||
.BRAM_WEN_A(BRAM_WEN_A),
|
||||
.CE(NLW_U0_CE_UNCONNECTED),
|
||||
.Interrupt(NLW_U0_Interrupt_UNCONNECTED),
|
||||
.LMB1_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.LMB1_AddrStrobe(1'b0),
|
||||
.LMB1_BE({1'b0,1'b0,1'b0,1'b0}),
|
||||
.LMB1_ReadStrobe(1'b0),
|
||||
.LMB1_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.LMB1_WriteStrobe(1'b0),
|
||||
.LMB2_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.LMB2_AddrStrobe(1'b0),
|
||||
.LMB2_BE({1'b0,1'b0,1'b0,1'b0}),
|
||||
.LMB2_ReadStrobe(1'b0),
|
||||
.LMB2_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.LMB2_WriteStrobe(1'b0),
|
||||
.LMB3_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.LMB3_AddrStrobe(1'b0),
|
||||
.LMB3_BE({1'b0,1'b0,1'b0,1'b0}),
|
||||
.LMB3_ReadStrobe(1'b0),
|
||||
.LMB3_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.LMB3_WriteStrobe(1'b0),
|
||||
.LMB_ABus(LMB_ABus),
|
||||
.LMB_AddrStrobe(LMB_AddrStrobe),
|
||||
.LMB_BE(LMB_BE),
|
||||
.LMB_Clk(LMB_Clk),
|
||||
.LMB_ReadStrobe(LMB_ReadStrobe),
|
||||
.LMB_Rst(LMB_Rst),
|
||||
.LMB_WriteDBus(LMB_WriteDBus),
|
||||
.LMB_WriteStrobe(LMB_WriteStrobe),
|
||||
.S_AXI_CTRL_ACLK(1'b0),
|
||||
.S_AXI_CTRL_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.S_AXI_CTRL_ARESETN(1'b0),
|
||||
.S_AXI_CTRL_ARREADY(NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED),
|
||||
.S_AXI_CTRL_ARVALID(1'b0),
|
||||
.S_AXI_CTRL_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.S_AXI_CTRL_AWREADY(NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED),
|
||||
.S_AXI_CTRL_AWVALID(1'b0),
|
||||
.S_AXI_CTRL_BREADY(1'b0),
|
||||
.S_AXI_CTRL_BRESP(NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED[1:0]),
|
||||
.S_AXI_CTRL_BVALID(NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED),
|
||||
.S_AXI_CTRL_RDATA(NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED[31:0]),
|
||||
.S_AXI_CTRL_RREADY(1'b0),
|
||||
.S_AXI_CTRL_RRESP(NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED[1:0]),
|
||||
.S_AXI_CTRL_RVALID(NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED),
|
||||
.S_AXI_CTRL_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.S_AXI_CTRL_WREADY(NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED),
|
||||
.S_AXI_CTRL_WSTRB({1'b0,1'b0,1'b0,1'b0}),
|
||||
.S_AXI_CTRL_WVALID(1'b0),
|
||||
.Sl1_CE(NLW_U0_Sl1_CE_UNCONNECTED),
|
||||
.Sl1_DBus(NLW_U0_Sl1_DBus_UNCONNECTED[0:31]),
|
||||
.Sl1_Ready(NLW_U0_Sl1_Ready_UNCONNECTED),
|
||||
.Sl1_UE(NLW_U0_Sl1_UE_UNCONNECTED),
|
||||
.Sl1_Wait(NLW_U0_Sl1_Wait_UNCONNECTED),
|
||||
.Sl2_CE(NLW_U0_Sl2_CE_UNCONNECTED),
|
||||
.Sl2_DBus(NLW_U0_Sl2_DBus_UNCONNECTED[0:31]),
|
||||
.Sl2_Ready(NLW_U0_Sl2_Ready_UNCONNECTED),
|
||||
.Sl2_UE(NLW_U0_Sl2_UE_UNCONNECTED),
|
||||
.Sl2_Wait(NLW_U0_Sl2_Wait_UNCONNECTED),
|
||||
.Sl3_CE(NLW_U0_Sl3_CE_UNCONNECTED),
|
||||
.Sl3_DBus(NLW_U0_Sl3_DBus_UNCONNECTED[0:31]),
|
||||
.Sl3_Ready(NLW_U0_Sl3_Ready_UNCONNECTED),
|
||||
.Sl3_UE(NLW_U0_Sl3_UE_UNCONNECTED),
|
||||
.Sl3_Wait(NLW_U0_Sl3_Wait_UNCONNECTED),
|
||||
.Sl_CE(Sl_CE),
|
||||
.Sl_DBus(Sl_DBus),
|
||||
.Sl_Ready(Sl_Ready),
|
||||
.Sl_UE(Sl_UE),
|
||||
.Sl_Wait(Sl_Wait),
|
||||
.UE(NLW_U0_UE_UNCONNECTED));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+639
@@ -0,0 +1,639 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:57:09 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top system_bd_dlmb_bram_if_cntlr_0 -prefix
|
||||
-- system_bd_dlmb_bram_if_cntlr_0_ system_bd_dlmb_bram_if_cntlr_0_sim_netlist.vhdl
|
||||
-- Design : system_bd_dlmb_bram_if_cntlr_0
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr is
|
||||
port (
|
||||
LMB_Clk : in STD_LOGIC;
|
||||
LMB_Rst : in STD_LOGIC;
|
||||
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB_AddrStrobe : in STD_LOGIC;
|
||||
LMB_ReadStrobe : in STD_LOGIC;
|
||||
LMB_WriteStrobe : in STD_LOGIC;
|
||||
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
|
||||
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
Sl_Ready : out STD_LOGIC;
|
||||
Sl_Wait : out STD_LOGIC;
|
||||
Sl_UE : out STD_LOGIC;
|
||||
Sl_CE : out STD_LOGIC;
|
||||
LMB1_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB1_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB1_AddrStrobe : in STD_LOGIC;
|
||||
LMB1_ReadStrobe : in STD_LOGIC;
|
||||
LMB1_WriteStrobe : in STD_LOGIC;
|
||||
LMB1_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
|
||||
Sl1_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
Sl1_Ready : out STD_LOGIC;
|
||||
Sl1_Wait : out STD_LOGIC;
|
||||
Sl1_UE : out STD_LOGIC;
|
||||
Sl1_CE : out STD_LOGIC;
|
||||
LMB2_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB2_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB2_AddrStrobe : in STD_LOGIC;
|
||||
LMB2_ReadStrobe : in STD_LOGIC;
|
||||
LMB2_WriteStrobe : in STD_LOGIC;
|
||||
LMB2_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
|
||||
Sl2_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
Sl2_Ready : out STD_LOGIC;
|
||||
Sl2_Wait : out STD_LOGIC;
|
||||
Sl2_UE : out STD_LOGIC;
|
||||
Sl2_CE : out STD_LOGIC;
|
||||
LMB3_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB3_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB3_AddrStrobe : in STD_LOGIC;
|
||||
LMB3_ReadStrobe : in STD_LOGIC;
|
||||
LMB3_WriteStrobe : in STD_LOGIC;
|
||||
LMB3_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
|
||||
Sl3_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
Sl3_Ready : out STD_LOGIC;
|
||||
Sl3_Wait : out STD_LOGIC;
|
||||
Sl3_UE : out STD_LOGIC;
|
||||
Sl3_CE : out STD_LOGIC;
|
||||
BRAM_Rst_A : out STD_LOGIC;
|
||||
BRAM_Clk_A : out STD_LOGIC;
|
||||
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
BRAM_EN_A : out STD_LOGIC;
|
||||
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
|
||||
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
S_AXI_CTRL_ACLK : in STD_LOGIC;
|
||||
S_AXI_CTRL_ARESETN : in STD_LOGIC;
|
||||
S_AXI_CTRL_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_CTRL_AWVALID : in STD_LOGIC;
|
||||
S_AXI_CTRL_AWREADY : out STD_LOGIC;
|
||||
S_AXI_CTRL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_CTRL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_CTRL_WVALID : in STD_LOGIC;
|
||||
S_AXI_CTRL_WREADY : out STD_LOGIC;
|
||||
S_AXI_CTRL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_CTRL_BVALID : out STD_LOGIC;
|
||||
S_AXI_CTRL_BREADY : in STD_LOGIC;
|
||||
S_AXI_CTRL_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_CTRL_ARVALID : in STD_LOGIC;
|
||||
S_AXI_CTRL_ARREADY : out STD_LOGIC;
|
||||
S_AXI_CTRL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_CTRL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_CTRL_RVALID : out STD_LOGIC;
|
||||
S_AXI_CTRL_RREADY : in STD_LOGIC;
|
||||
UE : out STD_LOGIC;
|
||||
CE : out STD_LOGIC;
|
||||
Interrupt : out STD_LOGIC
|
||||
);
|
||||
attribute C_BASEADDR : string;
|
||||
attribute C_BASEADDR of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute C_BRAM_AWIDTH : integer;
|
||||
attribute C_BRAM_AWIDTH of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 32;
|
||||
attribute C_CE_COUNTER_WIDTH : integer;
|
||||
attribute C_CE_COUNTER_WIDTH of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
|
||||
attribute C_CE_FAILING_REGISTERS : integer;
|
||||
attribute C_CE_FAILING_REGISTERS of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
|
||||
attribute C_ECC : integer;
|
||||
attribute C_ECC of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
|
||||
attribute C_ECC_ONOFF_REGISTER : integer;
|
||||
attribute C_ECC_ONOFF_REGISTER of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
|
||||
attribute C_ECC_ONOFF_RESET_VALUE : integer;
|
||||
attribute C_ECC_ONOFF_RESET_VALUE of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 1;
|
||||
attribute C_ECC_STATUS_REGISTERS : integer;
|
||||
attribute C_ECC_STATUS_REGISTERS of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
|
||||
attribute C_FAMILY : string;
|
||||
attribute C_FAMILY of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "kintex7";
|
||||
attribute C_FAULT_INJECT : integer;
|
||||
attribute C_FAULT_INJECT of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
|
||||
attribute C_HIGHADDR : string;
|
||||
attribute C_HIGHADDR of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000000000111111111111111111";
|
||||
attribute C_INTERCONNECT : integer;
|
||||
attribute C_INTERCONNECT of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
|
||||
attribute C_LMB_AWIDTH : integer;
|
||||
attribute C_LMB_AWIDTH of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 32;
|
||||
attribute C_LMB_DWIDTH : integer;
|
||||
attribute C_LMB_DWIDTH of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 32;
|
||||
attribute C_MASK : string;
|
||||
attribute C_MASK of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000001000000000000000000000000000000";
|
||||
attribute C_MASK1 : string;
|
||||
attribute C_MASK1 of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000100000000000000000000000";
|
||||
attribute C_MASK2 : string;
|
||||
attribute C_MASK2 of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000100000000000000000000000";
|
||||
attribute C_MASK3 : string;
|
||||
attribute C_MASK3 of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000100000000000000000000000";
|
||||
attribute C_NUM_LMB : integer;
|
||||
attribute C_NUM_LMB of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 1;
|
||||
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
|
||||
attribute C_S_AXI_CTRL_ADDR_WIDTH of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 32;
|
||||
attribute C_S_AXI_CTRL_BASEADDR : string;
|
||||
attribute C_S_AXI_CTRL_BASEADDR of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "32'b11111111111111111111111111111111";
|
||||
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
|
||||
attribute C_S_AXI_CTRL_DATA_WIDTH of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 32;
|
||||
attribute C_S_AXI_CTRL_HIGHADDR : string;
|
||||
attribute C_S_AXI_CTRL_HIGHADDR of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "32'b00000000000000000000000000000000";
|
||||
attribute C_UE_FAILING_REGISTERS : integer;
|
||||
attribute C_UE_FAILING_REGISTERS of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
|
||||
attribute C_WRITE_ACCESS : integer;
|
||||
attribute C_WRITE_ACCESS of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 2;
|
||||
end system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr;
|
||||
|
||||
architecture STRUCTURE of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr is
|
||||
signal \<const0>\ : STD_LOGIC;
|
||||
signal \^bram_din_a\ : STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
signal \^lmb_abus\ : STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
signal \^lmb_addrstrobe\ : STD_LOGIC;
|
||||
signal \^lmb_clk\ : STD_LOGIC;
|
||||
signal \^lmb_writedbus\ : STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
signal \No_ECC.Sl_Rdy_i_1_n_0\ : STD_LOGIC;
|
||||
signal \No_ECC.lmb_as_i_1_n_0\ : STD_LOGIC;
|
||||
signal Sl_Rdy : STD_LOGIC;
|
||||
signal lmb_as : STD_LOGIC;
|
||||
attribute SOFT_HLUTNM : string;
|
||||
attribute SOFT_HLUTNM of \BRAM_WEN_A[0]_INST_0\ : label is "soft_lutpair1";
|
||||
attribute SOFT_HLUTNM of \BRAM_WEN_A[1]_INST_0\ : label is "soft_lutpair1";
|
||||
attribute SOFT_HLUTNM of \BRAM_WEN_A[2]_INST_0\ : label is "soft_lutpair0";
|
||||
attribute SOFT_HLUTNM of \BRAM_WEN_A[3]_INST_0\ : label is "soft_lutpair0";
|
||||
attribute SOFT_HLUTNM of \No_ECC.Sl_Rdy_i_1\ : label is "soft_lutpair2";
|
||||
attribute SOFT_HLUTNM of \No_ECC.lmb_as_i_1\ : label is "soft_lutpair2";
|
||||
begin
|
||||
BRAM_Addr_A(0 to 31) <= \^lmb_abus\(0 to 31);
|
||||
BRAM_Clk_A <= \^lmb_clk\;
|
||||
BRAM_Dout_A(0 to 31) <= \^lmb_writedbus\(0 to 31);
|
||||
BRAM_EN_A <= \^lmb_addrstrobe\;
|
||||
BRAM_Rst_A <= \<const0>\;
|
||||
CE <= \<const0>\;
|
||||
Interrupt <= \<const0>\;
|
||||
S_AXI_CTRL_ARREADY <= \<const0>\;
|
||||
S_AXI_CTRL_AWREADY <= \<const0>\;
|
||||
S_AXI_CTRL_BRESP(1) <= \<const0>\;
|
||||
S_AXI_CTRL_BRESP(0) <= \<const0>\;
|
||||
S_AXI_CTRL_BVALID <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(31) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(30) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(29) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(28) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(27) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(26) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(25) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(24) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(23) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(22) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(21) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(20) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(19) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(18) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(17) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(16) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(15) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(14) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(13) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(12) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(11) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(10) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(9) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(8) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(7) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(6) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(5) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(4) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(3) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(2) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(1) <= \<const0>\;
|
||||
S_AXI_CTRL_RDATA(0) <= \<const0>\;
|
||||
S_AXI_CTRL_RRESP(1) <= \<const0>\;
|
||||
S_AXI_CTRL_RRESP(0) <= \<const0>\;
|
||||
S_AXI_CTRL_RVALID <= \<const0>\;
|
||||
S_AXI_CTRL_WREADY <= \<const0>\;
|
||||
Sl1_CE <= \<const0>\;
|
||||
Sl1_DBus(0) <= \<const0>\;
|
||||
Sl1_DBus(1) <= \<const0>\;
|
||||
Sl1_DBus(2) <= \<const0>\;
|
||||
Sl1_DBus(3) <= \<const0>\;
|
||||
Sl1_DBus(4) <= \<const0>\;
|
||||
Sl1_DBus(5) <= \<const0>\;
|
||||
Sl1_DBus(6) <= \<const0>\;
|
||||
Sl1_DBus(7) <= \<const0>\;
|
||||
Sl1_DBus(8) <= \<const0>\;
|
||||
Sl1_DBus(9) <= \<const0>\;
|
||||
Sl1_DBus(10) <= \<const0>\;
|
||||
Sl1_DBus(11) <= \<const0>\;
|
||||
Sl1_DBus(12) <= \<const0>\;
|
||||
Sl1_DBus(13) <= \<const0>\;
|
||||
Sl1_DBus(14) <= \<const0>\;
|
||||
Sl1_DBus(15) <= \<const0>\;
|
||||
Sl1_DBus(16) <= \<const0>\;
|
||||
Sl1_DBus(17) <= \<const0>\;
|
||||
Sl1_DBus(18) <= \<const0>\;
|
||||
Sl1_DBus(19) <= \<const0>\;
|
||||
Sl1_DBus(20) <= \<const0>\;
|
||||
Sl1_DBus(21) <= \<const0>\;
|
||||
Sl1_DBus(22) <= \<const0>\;
|
||||
Sl1_DBus(23) <= \<const0>\;
|
||||
Sl1_DBus(24) <= \<const0>\;
|
||||
Sl1_DBus(25) <= \<const0>\;
|
||||
Sl1_DBus(26) <= \<const0>\;
|
||||
Sl1_DBus(27) <= \<const0>\;
|
||||
Sl1_DBus(28) <= \<const0>\;
|
||||
Sl1_DBus(29) <= \<const0>\;
|
||||
Sl1_DBus(30) <= \<const0>\;
|
||||
Sl1_DBus(31) <= \<const0>\;
|
||||
Sl1_Ready <= \<const0>\;
|
||||
Sl1_UE <= \<const0>\;
|
||||
Sl1_Wait <= \<const0>\;
|
||||
Sl2_CE <= \<const0>\;
|
||||
Sl2_DBus(0) <= \<const0>\;
|
||||
Sl2_DBus(1) <= \<const0>\;
|
||||
Sl2_DBus(2) <= \<const0>\;
|
||||
Sl2_DBus(3) <= \<const0>\;
|
||||
Sl2_DBus(4) <= \<const0>\;
|
||||
Sl2_DBus(5) <= \<const0>\;
|
||||
Sl2_DBus(6) <= \<const0>\;
|
||||
Sl2_DBus(7) <= \<const0>\;
|
||||
Sl2_DBus(8) <= \<const0>\;
|
||||
Sl2_DBus(9) <= \<const0>\;
|
||||
Sl2_DBus(10) <= \<const0>\;
|
||||
Sl2_DBus(11) <= \<const0>\;
|
||||
Sl2_DBus(12) <= \<const0>\;
|
||||
Sl2_DBus(13) <= \<const0>\;
|
||||
Sl2_DBus(14) <= \<const0>\;
|
||||
Sl2_DBus(15) <= \<const0>\;
|
||||
Sl2_DBus(16) <= \<const0>\;
|
||||
Sl2_DBus(17) <= \<const0>\;
|
||||
Sl2_DBus(18) <= \<const0>\;
|
||||
Sl2_DBus(19) <= \<const0>\;
|
||||
Sl2_DBus(20) <= \<const0>\;
|
||||
Sl2_DBus(21) <= \<const0>\;
|
||||
Sl2_DBus(22) <= \<const0>\;
|
||||
Sl2_DBus(23) <= \<const0>\;
|
||||
Sl2_DBus(24) <= \<const0>\;
|
||||
Sl2_DBus(25) <= \<const0>\;
|
||||
Sl2_DBus(26) <= \<const0>\;
|
||||
Sl2_DBus(27) <= \<const0>\;
|
||||
Sl2_DBus(28) <= \<const0>\;
|
||||
Sl2_DBus(29) <= \<const0>\;
|
||||
Sl2_DBus(30) <= \<const0>\;
|
||||
Sl2_DBus(31) <= \<const0>\;
|
||||
Sl2_Ready <= \<const0>\;
|
||||
Sl2_UE <= \<const0>\;
|
||||
Sl2_Wait <= \<const0>\;
|
||||
Sl3_CE <= \<const0>\;
|
||||
Sl3_DBus(0) <= \<const0>\;
|
||||
Sl3_DBus(1) <= \<const0>\;
|
||||
Sl3_DBus(2) <= \<const0>\;
|
||||
Sl3_DBus(3) <= \<const0>\;
|
||||
Sl3_DBus(4) <= \<const0>\;
|
||||
Sl3_DBus(5) <= \<const0>\;
|
||||
Sl3_DBus(6) <= \<const0>\;
|
||||
Sl3_DBus(7) <= \<const0>\;
|
||||
Sl3_DBus(8) <= \<const0>\;
|
||||
Sl3_DBus(9) <= \<const0>\;
|
||||
Sl3_DBus(10) <= \<const0>\;
|
||||
Sl3_DBus(11) <= \<const0>\;
|
||||
Sl3_DBus(12) <= \<const0>\;
|
||||
Sl3_DBus(13) <= \<const0>\;
|
||||
Sl3_DBus(14) <= \<const0>\;
|
||||
Sl3_DBus(15) <= \<const0>\;
|
||||
Sl3_DBus(16) <= \<const0>\;
|
||||
Sl3_DBus(17) <= \<const0>\;
|
||||
Sl3_DBus(18) <= \<const0>\;
|
||||
Sl3_DBus(19) <= \<const0>\;
|
||||
Sl3_DBus(20) <= \<const0>\;
|
||||
Sl3_DBus(21) <= \<const0>\;
|
||||
Sl3_DBus(22) <= \<const0>\;
|
||||
Sl3_DBus(23) <= \<const0>\;
|
||||
Sl3_DBus(24) <= \<const0>\;
|
||||
Sl3_DBus(25) <= \<const0>\;
|
||||
Sl3_DBus(26) <= \<const0>\;
|
||||
Sl3_DBus(27) <= \<const0>\;
|
||||
Sl3_DBus(28) <= \<const0>\;
|
||||
Sl3_DBus(29) <= \<const0>\;
|
||||
Sl3_DBus(30) <= \<const0>\;
|
||||
Sl3_DBus(31) <= \<const0>\;
|
||||
Sl3_Ready <= \<const0>\;
|
||||
Sl3_UE <= \<const0>\;
|
||||
Sl3_Wait <= \<const0>\;
|
||||
Sl_CE <= \<const0>\;
|
||||
Sl_DBus(0 to 31) <= \^bram_din_a\(0 to 31);
|
||||
Sl_UE <= \<const0>\;
|
||||
Sl_Wait <= \<const0>\;
|
||||
UE <= \<const0>\;
|
||||
\^bram_din_a\(0 to 31) <= BRAM_Din_A(0 to 31);
|
||||
\^lmb_abus\(0 to 31) <= LMB_ABus(0 to 31);
|
||||
\^lmb_addrstrobe\ <= LMB_AddrStrobe;
|
||||
\^lmb_clk\ <= LMB_Clk;
|
||||
\^lmb_writedbus\(0 to 31) <= LMB_WriteDBus(0 to 31);
|
||||
\BRAM_WEN_A[0]_INST_0\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"20"
|
||||
)
|
||||
port map (
|
||||
I0 => LMB_BE(0),
|
||||
I1 => \^lmb_abus\(1),
|
||||
I2 => LMB_WriteStrobe,
|
||||
O => BRAM_WEN_A(0)
|
||||
);
|
||||
\BRAM_WEN_A[1]_INST_0\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"40"
|
||||
)
|
||||
port map (
|
||||
I0 => \^lmb_abus\(1),
|
||||
I1 => LMB_WriteStrobe,
|
||||
I2 => LMB_BE(1),
|
||||
O => BRAM_WEN_A(1)
|
||||
);
|
||||
\BRAM_WEN_A[2]_INST_0\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"40"
|
||||
)
|
||||
port map (
|
||||
I0 => \^lmb_abus\(1),
|
||||
I1 => LMB_WriteStrobe,
|
||||
I2 => LMB_BE(2),
|
||||
O => BRAM_WEN_A(2)
|
||||
);
|
||||
\BRAM_WEN_A[3]_INST_0\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"40"
|
||||
)
|
||||
port map (
|
||||
I0 => \^lmb_abus\(1),
|
||||
I1 => LMB_WriteStrobe,
|
||||
I2 => LMB_BE(3),
|
||||
O => BRAM_WEN_A(3)
|
||||
);
|
||||
GND: unisim.vcomponents.GND
|
||||
port map (
|
||||
G => \<const0>\
|
||||
);
|
||||
\No_ECC.Sl_Rdy_i_1\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"1"
|
||||
)
|
||||
port map (
|
||||
I0 => \^lmb_abus\(1),
|
||||
I1 => LMB_Rst,
|
||||
O => \No_ECC.Sl_Rdy_i_1_n_0\
|
||||
);
|
||||
\No_ECC.Sl_Rdy_reg\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => \^lmb_clk\,
|
||||
CE => '1',
|
||||
D => \No_ECC.Sl_Rdy_i_1_n_0\,
|
||||
Q => Sl_Rdy,
|
||||
R => '0'
|
||||
);
|
||||
\No_ECC.lmb_as_i_1\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"2"
|
||||
)
|
||||
port map (
|
||||
I0 => \^lmb_addrstrobe\,
|
||||
I1 => LMB_Rst,
|
||||
O => \No_ECC.lmb_as_i_1_n_0\
|
||||
);
|
||||
\No_ECC.lmb_as_reg\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => \^lmb_clk\,
|
||||
CE => '1',
|
||||
D => \No_ECC.lmb_as_i_1_n_0\,
|
||||
Q => lmb_as,
|
||||
R => '0'
|
||||
);
|
||||
Sl_Ready_INST_0: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"8"
|
||||
)
|
||||
port map (
|
||||
I0 => Sl_Rdy,
|
||||
I1 => lmb_as,
|
||||
O => Sl_Ready
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity system_bd_dlmb_bram_if_cntlr_0 is
|
||||
port (
|
||||
LMB_Clk : in STD_LOGIC;
|
||||
LMB_Rst : in STD_LOGIC;
|
||||
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB_AddrStrobe : in STD_LOGIC;
|
||||
LMB_ReadStrobe : in STD_LOGIC;
|
||||
LMB_WriteStrobe : in STD_LOGIC;
|
||||
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
|
||||
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
Sl_Ready : out STD_LOGIC;
|
||||
Sl_Wait : out STD_LOGIC;
|
||||
Sl_UE : out STD_LOGIC;
|
||||
Sl_CE : out STD_LOGIC;
|
||||
BRAM_Rst_A : out STD_LOGIC;
|
||||
BRAM_Clk_A : out STD_LOGIC;
|
||||
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
BRAM_EN_A : out STD_LOGIC;
|
||||
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
|
||||
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of system_bd_dlmb_bram_if_cntlr_0 : entity is true;
|
||||
attribute CHECK_LICENSE_TYPE : string;
|
||||
attribute CHECK_LICENSE_TYPE of system_bd_dlmb_bram_if_cntlr_0 : entity is "system_bd_dlmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}";
|
||||
attribute downgradeipidentifiedwarnings : string;
|
||||
attribute downgradeipidentifiedwarnings of system_bd_dlmb_bram_if_cntlr_0 : entity is "yes";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of system_bd_dlmb_bram_if_cntlr_0 : entity is "lmb_bram_if_cntlr,Vivado 2019.1.3";
|
||||
end system_bd_dlmb_bram_if_cntlr_0;
|
||||
|
||||
architecture STRUCTURE of system_bd_dlmb_bram_if_cntlr_0 is
|
||||
signal NLW_U0_CE_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_Interrupt_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_Sl1_CE_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_Sl1_Ready_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_Sl1_UE_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_Sl1_Wait_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_Sl2_CE_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_Sl2_Ready_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_Sl2_UE_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_Sl2_Wait_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_Sl3_CE_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_Sl3_Ready_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_Sl3_UE_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_Sl3_Wait_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_UE_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal NLW_U0_Sl1_DBus_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
signal NLW_U0_Sl2_DBus_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
signal NLW_U0_Sl3_DBus_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
attribute C_BASEADDR : string;
|
||||
attribute C_BASEADDR of U0 : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute C_BRAM_AWIDTH : integer;
|
||||
attribute C_BRAM_AWIDTH of U0 : label is 32;
|
||||
attribute C_CE_COUNTER_WIDTH : integer;
|
||||
attribute C_CE_COUNTER_WIDTH of U0 : label is 0;
|
||||
attribute C_CE_FAILING_REGISTERS : integer;
|
||||
attribute C_CE_FAILING_REGISTERS of U0 : label is 0;
|
||||
attribute C_ECC : integer;
|
||||
attribute C_ECC of U0 : label is 0;
|
||||
attribute C_ECC_ONOFF_REGISTER : integer;
|
||||
attribute C_ECC_ONOFF_REGISTER of U0 : label is 0;
|
||||
attribute C_ECC_ONOFF_RESET_VALUE : integer;
|
||||
attribute C_ECC_ONOFF_RESET_VALUE of U0 : label is 1;
|
||||
attribute C_ECC_STATUS_REGISTERS : integer;
|
||||
attribute C_ECC_STATUS_REGISTERS of U0 : label is 0;
|
||||
attribute C_FAMILY : string;
|
||||
attribute C_FAMILY of U0 : label is "kintex7";
|
||||
attribute C_FAULT_INJECT : integer;
|
||||
attribute C_FAULT_INJECT of U0 : label is 0;
|
||||
attribute C_HIGHADDR : string;
|
||||
attribute C_HIGHADDR of U0 : label is "64'b0000000000000000000000000000000000000000000000111111111111111111";
|
||||
attribute C_INTERCONNECT : integer;
|
||||
attribute C_INTERCONNECT of U0 : label is 0;
|
||||
attribute C_LMB_AWIDTH : integer;
|
||||
attribute C_LMB_AWIDTH of U0 : label is 32;
|
||||
attribute C_LMB_DWIDTH : integer;
|
||||
attribute C_LMB_DWIDTH of U0 : label is 32;
|
||||
attribute C_MASK : string;
|
||||
attribute C_MASK of U0 : label is "64'b0000000000000000000000000000000001000000000000000000000000000000";
|
||||
attribute C_MASK1 : string;
|
||||
attribute C_MASK1 of U0 : label is "64'b0000000000000000000000000000000000000000100000000000000000000000";
|
||||
attribute C_MASK2 : string;
|
||||
attribute C_MASK2 of U0 : label is "64'b0000000000000000000000000000000000000000100000000000000000000000";
|
||||
attribute C_MASK3 : string;
|
||||
attribute C_MASK3 of U0 : label is "64'b0000000000000000000000000000000000000000100000000000000000000000";
|
||||
attribute C_NUM_LMB : integer;
|
||||
attribute C_NUM_LMB of U0 : label is 1;
|
||||
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
|
||||
attribute C_S_AXI_CTRL_ADDR_WIDTH of U0 : label is 32;
|
||||
attribute C_S_AXI_CTRL_BASEADDR : string;
|
||||
attribute C_S_AXI_CTRL_BASEADDR of U0 : label is "32'b11111111111111111111111111111111";
|
||||
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
|
||||
attribute C_S_AXI_CTRL_DATA_WIDTH of U0 : label is 32;
|
||||
attribute C_S_AXI_CTRL_HIGHADDR : string;
|
||||
attribute C_S_AXI_CTRL_HIGHADDR of U0 : label is "32'b00000000000000000000000000000000";
|
||||
attribute C_UE_FAILING_REGISTERS : integer;
|
||||
attribute C_UE_FAILING_REGISTERS of U0 : label is 0;
|
||||
attribute C_WRITE_ACCESS : integer;
|
||||
attribute C_WRITE_ACCESS of U0 : label is 2;
|
||||
attribute x_interface_info : string;
|
||||
attribute x_interface_info of BRAM_Clk_A : signal is "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
|
||||
attribute x_interface_info of BRAM_EN_A : signal is "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
|
||||
attribute x_interface_info of BRAM_Rst_A : signal is "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
|
||||
attribute x_interface_parameter : string;
|
||||
attribute x_interface_parameter of BRAM_Rst_A : signal is "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 262144, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1";
|
||||
attribute x_interface_info of LMB_AddrStrobe : signal is "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
|
||||
attribute x_interface_info of LMB_Clk : signal is "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
|
||||
attribute x_interface_parameter of LMB_Clk : signal is "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0";
|
||||
attribute x_interface_info of LMB_ReadStrobe : signal is "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
|
||||
attribute x_interface_info of LMB_Rst : signal is "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
|
||||
attribute x_interface_parameter of LMB_Rst : signal is "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
attribute x_interface_info of LMB_WriteStrobe : signal is "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
|
||||
attribute x_interface_info of Sl_CE : signal is "xilinx.com:interface:lmb:1.0 SLMB CE";
|
||||
attribute x_interface_info of Sl_Ready : signal is "xilinx.com:interface:lmb:1.0 SLMB READY";
|
||||
attribute x_interface_info of Sl_UE : signal is "xilinx.com:interface:lmb:1.0 SLMB UE";
|
||||
attribute x_interface_info of Sl_Wait : signal is "xilinx.com:interface:lmb:1.0 SLMB WAIT";
|
||||
attribute x_interface_info of BRAM_Addr_A : signal is "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
|
||||
attribute x_interface_info of BRAM_Din_A : signal is "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
|
||||
attribute x_interface_info of BRAM_Dout_A : signal is "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
|
||||
attribute x_interface_info of BRAM_WEN_A : signal is "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
|
||||
attribute x_interface_info of LMB_ABus : signal is "xilinx.com:interface:lmb:1.0 SLMB ABUS";
|
||||
attribute x_interface_parameter of LMB_ABus : signal is "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE";
|
||||
attribute x_interface_info of LMB_BE : signal is "xilinx.com:interface:lmb:1.0 SLMB BE";
|
||||
attribute x_interface_info of LMB_WriteDBus : signal is "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
|
||||
attribute x_interface_info of Sl_DBus : signal is "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
|
||||
begin
|
||||
U0: entity work.system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr
|
||||
port map (
|
||||
BRAM_Addr_A(0 to 31) => BRAM_Addr_A(0 to 31),
|
||||
BRAM_Clk_A => BRAM_Clk_A,
|
||||
BRAM_Din_A(0 to 31) => BRAM_Din_A(0 to 31),
|
||||
BRAM_Dout_A(0 to 31) => BRAM_Dout_A(0 to 31),
|
||||
BRAM_EN_A => BRAM_EN_A,
|
||||
BRAM_Rst_A => BRAM_Rst_A,
|
||||
BRAM_WEN_A(0 to 3) => BRAM_WEN_A(0 to 3),
|
||||
CE => NLW_U0_CE_UNCONNECTED,
|
||||
Interrupt => NLW_U0_Interrupt_UNCONNECTED,
|
||||
LMB1_ABus(0 to 31) => B"00000000000000000000000000000000",
|
||||
LMB1_AddrStrobe => '0',
|
||||
LMB1_BE(0 to 3) => B"0000",
|
||||
LMB1_ReadStrobe => '0',
|
||||
LMB1_WriteDBus(0 to 31) => B"00000000000000000000000000000000",
|
||||
LMB1_WriteStrobe => '0',
|
||||
LMB2_ABus(0 to 31) => B"00000000000000000000000000000000",
|
||||
LMB2_AddrStrobe => '0',
|
||||
LMB2_BE(0 to 3) => B"0000",
|
||||
LMB2_ReadStrobe => '0',
|
||||
LMB2_WriteDBus(0 to 31) => B"00000000000000000000000000000000",
|
||||
LMB2_WriteStrobe => '0',
|
||||
LMB3_ABus(0 to 31) => B"00000000000000000000000000000000",
|
||||
LMB3_AddrStrobe => '0',
|
||||
LMB3_BE(0 to 3) => B"0000",
|
||||
LMB3_ReadStrobe => '0',
|
||||
LMB3_WriteDBus(0 to 31) => B"00000000000000000000000000000000",
|
||||
LMB3_WriteStrobe => '0',
|
||||
LMB_ABus(0 to 31) => LMB_ABus(0 to 31),
|
||||
LMB_AddrStrobe => LMB_AddrStrobe,
|
||||
LMB_BE(0 to 3) => LMB_BE(0 to 3),
|
||||
LMB_Clk => LMB_Clk,
|
||||
LMB_ReadStrobe => LMB_ReadStrobe,
|
||||
LMB_Rst => LMB_Rst,
|
||||
LMB_WriteDBus(0 to 31) => LMB_WriteDBus(0 to 31),
|
||||
LMB_WriteStrobe => LMB_WriteStrobe,
|
||||
S_AXI_CTRL_ACLK => '0',
|
||||
S_AXI_CTRL_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
|
||||
S_AXI_CTRL_ARESETN => '0',
|
||||
S_AXI_CTRL_ARREADY => NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED,
|
||||
S_AXI_CTRL_ARVALID => '0',
|
||||
S_AXI_CTRL_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
|
||||
S_AXI_CTRL_AWREADY => NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED,
|
||||
S_AXI_CTRL_AWVALID => '0',
|
||||
S_AXI_CTRL_BREADY => '0',
|
||||
S_AXI_CTRL_BRESP(1 downto 0) => NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED(1 downto 0),
|
||||
S_AXI_CTRL_BVALID => NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED,
|
||||
S_AXI_CTRL_RDATA(31 downto 0) => NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED(31 downto 0),
|
||||
S_AXI_CTRL_RREADY => '0',
|
||||
S_AXI_CTRL_RRESP(1 downto 0) => NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED(1 downto 0),
|
||||
S_AXI_CTRL_RVALID => NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED,
|
||||
S_AXI_CTRL_WDATA(31 downto 0) => B"00000000000000000000000000000000",
|
||||
S_AXI_CTRL_WREADY => NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED,
|
||||
S_AXI_CTRL_WSTRB(3 downto 0) => B"0000",
|
||||
S_AXI_CTRL_WVALID => '0',
|
||||
Sl1_CE => NLW_U0_Sl1_CE_UNCONNECTED,
|
||||
Sl1_DBus(0 to 31) => NLW_U0_Sl1_DBus_UNCONNECTED(0 to 31),
|
||||
Sl1_Ready => NLW_U0_Sl1_Ready_UNCONNECTED,
|
||||
Sl1_UE => NLW_U0_Sl1_UE_UNCONNECTED,
|
||||
Sl1_Wait => NLW_U0_Sl1_Wait_UNCONNECTED,
|
||||
Sl2_CE => NLW_U0_Sl2_CE_UNCONNECTED,
|
||||
Sl2_DBus(0 to 31) => NLW_U0_Sl2_DBus_UNCONNECTED(0 to 31),
|
||||
Sl2_Ready => NLW_U0_Sl2_Ready_UNCONNECTED,
|
||||
Sl2_UE => NLW_U0_Sl2_UE_UNCONNECTED,
|
||||
Sl2_Wait => NLW_U0_Sl2_Wait_UNCONNECTED,
|
||||
Sl3_CE => NLW_U0_Sl3_CE_UNCONNECTED,
|
||||
Sl3_DBus(0 to 31) => NLW_U0_Sl3_DBus_UNCONNECTED(0 to 31),
|
||||
Sl3_Ready => NLW_U0_Sl3_Ready_UNCONNECTED,
|
||||
Sl3_UE => NLW_U0_Sl3_UE_UNCONNECTED,
|
||||
Sl3_Wait => NLW_U0_Sl3_Wait_UNCONNECTED,
|
||||
Sl_CE => Sl_CE,
|
||||
Sl_DBus(0 to 31) => Sl_DBus(0 to 31),
|
||||
Sl_Ready => Sl_Ready,
|
||||
Sl_UE => Sl_UE,
|
||||
Sl_Wait => Sl_Wait,
|
||||
UE => NLW_U0_UE_UNCONNECTED
|
||||
);
|
||||
end STRUCTURE;
|
||||
+41
@@ -0,0 +1,41 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:57:09 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top system_bd_dlmb_bram_if_cntlr_0 -prefix
|
||||
// system_bd_dlmb_bram_if_cntlr_0_ system_bd_dlmb_bram_if_cntlr_0_stub.v
|
||||
// Design : system_bd_dlmb_bram_if_cntlr_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "lmb_bram_if_cntlr,Vivado 2019.1.3" *)
|
||||
module system_bd_dlmb_bram_if_cntlr_0(LMB_Clk, LMB_Rst, LMB_ABus, LMB_WriteDBus,
|
||||
LMB_AddrStrobe, LMB_ReadStrobe, LMB_WriteStrobe, LMB_BE, Sl_DBus, Sl_Ready, Sl_Wait, Sl_UE,
|
||||
Sl_CE, BRAM_Rst_A, BRAM_Clk_A, BRAM_Addr_A, BRAM_EN_A, BRAM_WEN_A, BRAM_Dout_A, BRAM_Din_A)
|
||||
/* synthesis syn_black_box black_box_pad_pin="LMB_Clk,LMB_Rst,LMB_ABus[0:31],LMB_WriteDBus[0:31],LMB_AddrStrobe,LMB_ReadStrobe,LMB_WriteStrobe,LMB_BE[0:3],Sl_DBus[0:31],Sl_Ready,Sl_Wait,Sl_UE,Sl_CE,BRAM_Rst_A,BRAM_Clk_A,BRAM_Addr_A[0:31],BRAM_EN_A,BRAM_WEN_A[0:3],BRAM_Dout_A[0:31],BRAM_Din_A[0:31]" */;
|
||||
input LMB_Clk;
|
||||
input LMB_Rst;
|
||||
input [0:31]LMB_ABus;
|
||||
input [0:31]LMB_WriteDBus;
|
||||
input LMB_AddrStrobe;
|
||||
input LMB_ReadStrobe;
|
||||
input LMB_WriteStrobe;
|
||||
input [0:3]LMB_BE;
|
||||
output [0:31]Sl_DBus;
|
||||
output Sl_Ready;
|
||||
output Sl_Wait;
|
||||
output Sl_UE;
|
||||
output Sl_CE;
|
||||
output BRAM_Rst_A;
|
||||
output BRAM_Clk_A;
|
||||
output [0:31]BRAM_Addr_A;
|
||||
output BRAM_EN_A;
|
||||
output [0:3]BRAM_WEN_A;
|
||||
output [0:31]BRAM_Dout_A;
|
||||
input [0:31]BRAM_Din_A;
|
||||
endmodule
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:57:09 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_dlmb_bram_if_cntlr_0 -prefix
|
||||
-- system_bd_dlmb_bram_if_cntlr_0_ system_bd_dlmb_bram_if_cntlr_0_stub.vhdl
|
||||
-- Design : system_bd_dlmb_bram_if_cntlr_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_bd_dlmb_bram_if_cntlr_0 is
|
||||
Port (
|
||||
LMB_Clk : in STD_LOGIC;
|
||||
LMB_Rst : in STD_LOGIC;
|
||||
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB_AddrStrobe : in STD_LOGIC;
|
||||
LMB_ReadStrobe : in STD_LOGIC;
|
||||
LMB_WriteStrobe : in STD_LOGIC;
|
||||
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
|
||||
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
Sl_Ready : out STD_LOGIC;
|
||||
Sl_Wait : out STD_LOGIC;
|
||||
Sl_UE : out STD_LOGIC;
|
||||
Sl_CE : out STD_LOGIC;
|
||||
BRAM_Rst_A : out STD_LOGIC;
|
||||
BRAM_Clk_A : out STD_LOGIC;
|
||||
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
BRAM_EN_A : out STD_LOGIC;
|
||||
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
|
||||
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
|
||||
);
|
||||
|
||||
end system_bd_dlmb_bram_if_cntlr_0;
|
||||
|
||||
architecture stub of system_bd_dlmb_bram_if_cntlr_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "LMB_Clk,LMB_Rst,LMB_ABus[0:31],LMB_WriteDBus[0:31],LMB_AddrStrobe,LMB_ReadStrobe,LMB_WriteStrobe,LMB_BE[0:3],Sl_DBus[0:31],Sl_Ready,Sl_Wait,Sl_UE,Sl_CE,BRAM_Rst_A,BRAM_Clk_A,BRAM_Addr_A[0:31],BRAM_EN_A,BRAM_WEN_A[0:3],BRAM_Dout_A[0:31],BRAM_Din_A[0:31]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "lmb_bram_if_cntlr,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+192
@@ -0,0 +1,192 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:lmb_v10:3.0
|
||||
-- IP Revision: 9
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY lmb_v10_v3_0_9;
|
||||
USE lmb_v10_v3_0_9.lmb_v10;
|
||||
|
||||
ENTITY system_bd_dlmb_v10_0 IS
|
||||
PORT (
|
||||
LMB_Clk : IN STD_LOGIC;
|
||||
SYS_Rst : IN STD_LOGIC;
|
||||
LMB_Rst : OUT STD_LOGIC;
|
||||
M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
M_ReadStrobe : IN STD_LOGIC;
|
||||
M_WriteStrobe : IN STD_LOGIC;
|
||||
M_AddrStrobe : IN STD_LOGIC;
|
||||
M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_ReadStrobe : OUT STD_LOGIC;
|
||||
LMB_WriteStrobe : OUT STD_LOGIC;
|
||||
LMB_AddrStrobe : OUT STD_LOGIC;
|
||||
LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_Ready : OUT STD_LOGIC;
|
||||
LMB_Wait : OUT STD_LOGIC;
|
||||
LMB_UE : OUT STD_LOGIC;
|
||||
LMB_CE : OUT STD_LOGIC;
|
||||
LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
|
||||
);
|
||||
END system_bd_dlmb_v10_0;
|
||||
|
||||
ARCHITECTURE system_bd_dlmb_v10_0_arch OF system_bd_dlmb_v10_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_dlmb_v10_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT lmb_v10 IS
|
||||
GENERIC (
|
||||
C_LMB_NUM_SLAVES : INTEGER;
|
||||
C_LMB_DWIDTH : INTEGER;
|
||||
C_LMB_AWIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
LMB_Clk : IN STD_LOGIC;
|
||||
SYS_Rst : IN STD_LOGIC;
|
||||
LMB_Rst : OUT STD_LOGIC;
|
||||
M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
M_ReadStrobe : IN STD_LOGIC;
|
||||
M_WriteStrobe : IN STD_LOGIC;
|
||||
M_AddrStrobe : IN STD_LOGIC;
|
||||
M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_ReadStrobe : OUT STD_LOGIC;
|
||||
LMB_WriteStrobe : OUT STD_LOGIC;
|
||||
LMB_AddrStrobe : OUT STD_LOGIC;
|
||||
LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_Ready : OUT STD_LOGIC;
|
||||
LMB_Wait : OUT STD_LOGIC;
|
||||
LMB_UE : OUT STD_LOGIC;
|
||||
LMB_CE : OUT STD_LOGIC;
|
||||
LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
|
||||
);
|
||||
END COMPONENT lmb_v10;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M CE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M UE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WAIT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READDBUS";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M BE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ABUS";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Rst: SIGNAL IS "XIL_INTERFACENAME LMB_Sl_0, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, XIL_INTERFACENAME LMB_M, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_M RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF SYS_Rst: SIGNAL IS "XIL_INTERFACENAME RST.SYS_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Clk: SIGNAL IS "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M, ASSOCIATED_RESET SYS_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
|
||||
BEGIN
|
||||
U0 : lmb_v10
|
||||
GENERIC MAP (
|
||||
C_LMB_NUM_SLAVES => 1,
|
||||
C_LMB_DWIDTH => 32,
|
||||
C_LMB_AWIDTH => 32,
|
||||
C_EXT_RESET_HIGH => 1
|
||||
)
|
||||
PORT MAP (
|
||||
LMB_Clk => LMB_Clk,
|
||||
SYS_Rst => SYS_Rst,
|
||||
LMB_Rst => LMB_Rst,
|
||||
M_ABus => M_ABus,
|
||||
M_ReadStrobe => M_ReadStrobe,
|
||||
M_WriteStrobe => M_WriteStrobe,
|
||||
M_AddrStrobe => M_AddrStrobe,
|
||||
M_DBus => M_DBus,
|
||||
M_BE => M_BE,
|
||||
Sl_DBus => Sl_DBus,
|
||||
Sl_Ready => Sl_Ready,
|
||||
Sl_Wait => Sl_Wait,
|
||||
Sl_UE => Sl_UE,
|
||||
Sl_CE => Sl_CE,
|
||||
LMB_ABus => LMB_ABus,
|
||||
LMB_ReadStrobe => LMB_ReadStrobe,
|
||||
LMB_WriteStrobe => LMB_WriteStrobe,
|
||||
LMB_AddrStrobe => LMB_AddrStrobe,
|
||||
LMB_ReadDBus => LMB_ReadDBus,
|
||||
LMB_WriteDBus => LMB_WriteDBus,
|
||||
LMB_Ready => LMB_Ready,
|
||||
LMB_Wait => LMB_Wait,
|
||||
LMB_UE => LMB_UE,
|
||||
LMB_CE => LMB_CE,
|
||||
LMB_BE => LMB_BE
|
||||
);
|
||||
END system_bd_dlmb_v10_0_arch;
|
||||
+198
@@ -0,0 +1,198 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:lmb_v10:3.0
|
||||
-- IP Revision: 9
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY lmb_v10_v3_0_9;
|
||||
USE lmb_v10_v3_0_9.lmb_v10;
|
||||
|
||||
ENTITY system_bd_dlmb_v10_0 IS
|
||||
PORT (
|
||||
LMB_Clk : IN STD_LOGIC;
|
||||
SYS_Rst : IN STD_LOGIC;
|
||||
LMB_Rst : OUT STD_LOGIC;
|
||||
M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
M_ReadStrobe : IN STD_LOGIC;
|
||||
M_WriteStrobe : IN STD_LOGIC;
|
||||
M_AddrStrobe : IN STD_LOGIC;
|
||||
M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_ReadStrobe : OUT STD_LOGIC;
|
||||
LMB_WriteStrobe : OUT STD_LOGIC;
|
||||
LMB_AddrStrobe : OUT STD_LOGIC;
|
||||
LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_Ready : OUT STD_LOGIC;
|
||||
LMB_Wait : OUT STD_LOGIC;
|
||||
LMB_UE : OUT STD_LOGIC;
|
||||
LMB_CE : OUT STD_LOGIC;
|
||||
LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
|
||||
);
|
||||
END system_bd_dlmb_v10_0;
|
||||
|
||||
ARCHITECTURE system_bd_dlmb_v10_0_arch OF system_bd_dlmb_v10_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_dlmb_v10_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT lmb_v10 IS
|
||||
GENERIC (
|
||||
C_LMB_NUM_SLAVES : INTEGER;
|
||||
C_LMB_DWIDTH : INTEGER;
|
||||
C_LMB_AWIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
LMB_Clk : IN STD_LOGIC;
|
||||
SYS_Rst : IN STD_LOGIC;
|
||||
LMB_Rst : OUT STD_LOGIC;
|
||||
M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
M_ReadStrobe : IN STD_LOGIC;
|
||||
M_WriteStrobe : IN STD_LOGIC;
|
||||
M_AddrStrobe : IN STD_LOGIC;
|
||||
M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_ReadStrobe : OUT STD_LOGIC;
|
||||
LMB_WriteStrobe : OUT STD_LOGIC;
|
||||
LMB_AddrStrobe : OUT STD_LOGIC;
|
||||
LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_Ready : OUT STD_LOGIC;
|
||||
LMB_Wait : OUT STD_LOGIC;
|
||||
LMB_UE : OUT STD_LOGIC;
|
||||
LMB_CE : OUT STD_LOGIC;
|
||||
LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
|
||||
);
|
||||
END COMPONENT lmb_v10;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_bd_dlmb_v10_0_arch: ARCHITECTURE IS "lmb_v10,Vivado 2019.1.3";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_bd_dlmb_v10_0_arch : ARCHITECTURE IS "system_bd_dlmb_v10_0,lmb_v10,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_bd_dlmb_v10_0_arch: ARCHITECTURE IS "system_bd_dlmb_v10_0,lmb_v10,{x_ipProduct=Vivado 2019.1.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_v10,x_ipVersion=3.0,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_LMB_NUM_SLAVES=1,C_LMB_DWIDTH=32,C_LMB_AWIDTH=32,C_EXT_RESET_HIGH=1}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M CE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M UE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WAIT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READDBUS";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M BE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ABUS";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Rst: SIGNAL IS "XIL_INTERFACENAME LMB_Sl_0, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, XIL_INTERFACENAME LMB_M, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_M RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF SYS_Rst: SIGNAL IS "XIL_INTERFACENAME RST.SYS_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Clk: SIGNAL IS "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M, ASSOCIATED_RESET SYS_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
|
||||
BEGIN
|
||||
U0 : lmb_v10
|
||||
GENERIC MAP (
|
||||
C_LMB_NUM_SLAVES => 1,
|
||||
C_LMB_DWIDTH => 32,
|
||||
C_LMB_AWIDTH => 32,
|
||||
C_EXT_RESET_HIGH => 1
|
||||
)
|
||||
PORT MAP (
|
||||
LMB_Clk => LMB_Clk,
|
||||
SYS_Rst => SYS_Rst,
|
||||
LMB_Rst => LMB_Rst,
|
||||
M_ABus => M_ABus,
|
||||
M_ReadStrobe => M_ReadStrobe,
|
||||
M_WriteStrobe => M_WriteStrobe,
|
||||
M_AddrStrobe => M_AddrStrobe,
|
||||
M_DBus => M_DBus,
|
||||
M_BE => M_BE,
|
||||
Sl_DBus => Sl_DBus,
|
||||
Sl_Ready => Sl_Ready,
|
||||
Sl_Wait => Sl_Wait,
|
||||
Sl_UE => Sl_UE,
|
||||
Sl_CE => Sl_CE,
|
||||
LMB_ABus => LMB_ABus,
|
||||
LMB_ReadStrobe => LMB_ReadStrobe,
|
||||
LMB_WriteStrobe => LMB_WriteStrobe,
|
||||
LMB_AddrStrobe => LMB_AddrStrobe,
|
||||
LMB_ReadDBus => LMB_ReadDBus,
|
||||
LMB_WriteDBus => LMB_WriteDBus,
|
||||
LMB_Ready => LMB_Ready,
|
||||
LMB_Wait => LMB_Wait,
|
||||
LMB_UE => LMB_UE,
|
||||
LMB_CE => LMB_CE,
|
||||
LMB_BE => LMB_BE
|
||||
);
|
||||
END system_bd_dlmb_v10_0_arch;
|
||||
BIN
Binary file not shown.
+116
@@ -0,0 +1,116 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_dlmb_v10_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="lmb_v10" spirit:version="3.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">/clk_wiz_25M_clk_out1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">25000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.SYS_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_NUM_SLAVES">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_NUM_SLAVES">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_dlmb_v10_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+1
@@ -0,0 +1 @@
|
||||
set_false_path -through [get_ports "SYS_Rst"]
|
||||
+3568
File diff suppressed because it is too large
Load Diff
+57
@@ -0,0 +1,57 @@
|
||||
# (c) Copyright 2012-2023 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 40 -name LMB_Clk [get_ports LMB_Clk]
|
||||
|
||||
|
||||
+287
@@ -0,0 +1,287 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:57:10 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top system_bd_dlmb_v10_0 -prefix
|
||||
// system_bd_dlmb_v10_0_ system_bd_dlmb_v10_0_sim_netlist.v
|
||||
// Design : system_bd_dlmb_v10_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* C_EXT_RESET_HIGH = "1" *) (* C_LMB_AWIDTH = "32" *) (* C_LMB_DWIDTH = "32" *)
|
||||
(* C_LMB_NUM_SLAVES = "1" *)
|
||||
module system_bd_dlmb_v10_0_lmb_v10
|
||||
(LMB_Clk,
|
||||
SYS_Rst,
|
||||
LMB_Rst,
|
||||
M_ABus,
|
||||
M_ReadStrobe,
|
||||
M_WriteStrobe,
|
||||
M_AddrStrobe,
|
||||
M_DBus,
|
||||
M_BE,
|
||||
Sl_DBus,
|
||||
Sl_Ready,
|
||||
Sl_Wait,
|
||||
Sl_UE,
|
||||
Sl_CE,
|
||||
LMB_ABus,
|
||||
LMB_ReadStrobe,
|
||||
LMB_WriteStrobe,
|
||||
LMB_AddrStrobe,
|
||||
LMB_ReadDBus,
|
||||
LMB_WriteDBus,
|
||||
LMB_Ready,
|
||||
LMB_Wait,
|
||||
LMB_UE,
|
||||
LMB_CE,
|
||||
LMB_BE);
|
||||
input LMB_Clk;
|
||||
input SYS_Rst;
|
||||
output LMB_Rst;
|
||||
input [0:31]M_ABus;
|
||||
input M_ReadStrobe;
|
||||
input M_WriteStrobe;
|
||||
input M_AddrStrobe;
|
||||
input [0:31]M_DBus;
|
||||
input [0:3]M_BE;
|
||||
input [0:31]Sl_DBus;
|
||||
input [0:0]Sl_Ready;
|
||||
input [0:0]Sl_Wait;
|
||||
input [0:0]Sl_UE;
|
||||
input [0:0]Sl_CE;
|
||||
output [0:31]LMB_ABus;
|
||||
output LMB_ReadStrobe;
|
||||
output LMB_WriteStrobe;
|
||||
output LMB_AddrStrobe;
|
||||
output [0:31]LMB_ReadDBus;
|
||||
output [0:31]LMB_WriteDBus;
|
||||
output LMB_Ready;
|
||||
output LMB_Wait;
|
||||
output LMB_UE;
|
||||
output LMB_CE;
|
||||
output [0:3]LMB_BE;
|
||||
|
||||
wire LMB_Clk;
|
||||
wire LMB_Rst;
|
||||
wire [0:31]M_ABus;
|
||||
wire M_AddrStrobe;
|
||||
wire [0:3]M_BE;
|
||||
wire [0:31]M_DBus;
|
||||
wire M_ReadStrobe;
|
||||
wire M_WriteStrobe;
|
||||
wire SYS_Rst;
|
||||
wire [0:0]Sl_CE;
|
||||
wire [0:31]Sl_DBus;
|
||||
wire [0:0]Sl_Ready;
|
||||
wire [0:0]Sl_UE;
|
||||
wire [0:0]Sl_Wait;
|
||||
|
||||
assign LMB_ABus[0:31] = M_ABus;
|
||||
assign LMB_AddrStrobe = M_AddrStrobe;
|
||||
assign LMB_BE[0:3] = M_BE;
|
||||
assign LMB_CE = Sl_CE;
|
||||
assign LMB_ReadDBus[0:31] = Sl_DBus;
|
||||
assign LMB_ReadStrobe = M_ReadStrobe;
|
||||
assign LMB_Ready = Sl_Ready;
|
||||
assign LMB_UE = Sl_UE;
|
||||
assign LMB_Wait = Sl_Wait;
|
||||
assign LMB_WriteDBus[0:31] = M_DBus;
|
||||
assign LMB_WriteStrobe = M_WriteStrobe;
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* XILINX_LEGACY_PRIM = "FDS" *)
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
POR_FF_I
|
||||
(.C(LMB_Clk),
|
||||
.CE(1'b1),
|
||||
.D(1'b0),
|
||||
.Q(LMB_Rst),
|
||||
.S(SYS_Rst));
|
||||
endmodule
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "system_bd_dlmb_v10_0,lmb_v10,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "lmb_v10,Vivado 2019.1.3" *)
|
||||
(* NotValidForBitStream *)
|
||||
module system_bd_dlmb_v10_0
|
||||
(LMB_Clk,
|
||||
SYS_Rst,
|
||||
LMB_Rst,
|
||||
M_ABus,
|
||||
M_ReadStrobe,
|
||||
M_WriteStrobe,
|
||||
M_AddrStrobe,
|
||||
M_DBus,
|
||||
M_BE,
|
||||
Sl_DBus,
|
||||
Sl_Ready,
|
||||
Sl_Wait,
|
||||
Sl_UE,
|
||||
Sl_CE,
|
||||
LMB_ABus,
|
||||
LMB_ReadStrobe,
|
||||
LMB_WriteStrobe,
|
||||
LMB_AddrStrobe,
|
||||
LMB_ReadDBus,
|
||||
LMB_WriteDBus,
|
||||
LMB_Ready,
|
||||
LMB_Wait,
|
||||
LMB_UE,
|
||||
LMB_CE,
|
||||
LMB_BE);
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M, ASSOCIATED_RESET SYS_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input LMB_Clk;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RST.SYS_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) input SYS_Rst;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_M RST" *) (* x_interface_parameter = "XIL_INTERFACENAME LMB_Sl_0, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, XIL_INTERFACENAME LMB_M, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE" *) output LMB_Rst;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M ABUS" *) input [0:31]M_ABus;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE" *) input M_ReadStrobe;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE" *) input M_WriteStrobe;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE" *) input M_AddrStrobe;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS" *) input [0:31]M_DBus;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M BE" *) input [0:3]M_BE;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS" *) input [0:31]Sl_DBus;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY" *) input [0:0]Sl_Ready;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT" *) input [0:0]Sl_Wait;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE" *) input [0:0]Sl_UE;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE" *) input [0:0]Sl_CE;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS" *) output [0:31]LMB_ABus;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE" *) output LMB_ReadStrobe;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE" *) output LMB_WriteStrobe;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE" *) output LMB_AddrStrobe;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M READDBUS" *) output [0:31]LMB_ReadDBus;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS" *) output [0:31]LMB_WriteDBus;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M READY" *) output LMB_Ready;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M WAIT" *) output LMB_Wait;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M UE" *) output LMB_UE;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M CE" *) output LMB_CE;
|
||||
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE" *) output [0:3]LMB_BE;
|
||||
|
||||
wire [0:31]LMB_ABus;
|
||||
wire LMB_AddrStrobe;
|
||||
wire [0:3]LMB_BE;
|
||||
wire LMB_CE;
|
||||
wire LMB_Clk;
|
||||
wire [0:31]LMB_ReadDBus;
|
||||
wire LMB_ReadStrobe;
|
||||
wire LMB_Ready;
|
||||
wire LMB_Rst;
|
||||
wire LMB_UE;
|
||||
wire LMB_Wait;
|
||||
wire [0:31]LMB_WriteDBus;
|
||||
wire LMB_WriteStrobe;
|
||||
wire [0:31]M_ABus;
|
||||
wire M_AddrStrobe;
|
||||
wire [0:3]M_BE;
|
||||
wire [0:31]M_DBus;
|
||||
wire M_ReadStrobe;
|
||||
wire M_WriteStrobe;
|
||||
wire SYS_Rst;
|
||||
wire [0:0]Sl_CE;
|
||||
wire [0:31]Sl_DBus;
|
||||
wire [0:0]Sl_Ready;
|
||||
wire [0:0]Sl_UE;
|
||||
wire [0:0]Sl_Wait;
|
||||
|
||||
(* C_EXT_RESET_HIGH = "1" *)
|
||||
(* C_LMB_AWIDTH = "32" *)
|
||||
(* C_LMB_DWIDTH = "32" *)
|
||||
(* C_LMB_NUM_SLAVES = "1" *)
|
||||
system_bd_dlmb_v10_0_lmb_v10 U0
|
||||
(.LMB_ABus(LMB_ABus),
|
||||
.LMB_AddrStrobe(LMB_AddrStrobe),
|
||||
.LMB_BE(LMB_BE),
|
||||
.LMB_CE(LMB_CE),
|
||||
.LMB_Clk(LMB_Clk),
|
||||
.LMB_ReadDBus(LMB_ReadDBus),
|
||||
.LMB_ReadStrobe(LMB_ReadStrobe),
|
||||
.LMB_Ready(LMB_Ready),
|
||||
.LMB_Rst(LMB_Rst),
|
||||
.LMB_UE(LMB_UE),
|
||||
.LMB_Wait(LMB_Wait),
|
||||
.LMB_WriteDBus(LMB_WriteDBus),
|
||||
.LMB_WriteStrobe(LMB_WriteStrobe),
|
||||
.M_ABus(M_ABus),
|
||||
.M_AddrStrobe(M_AddrStrobe),
|
||||
.M_BE(M_BE),
|
||||
.M_DBus(M_DBus),
|
||||
.M_ReadStrobe(M_ReadStrobe),
|
||||
.M_WriteStrobe(M_WriteStrobe),
|
||||
.SYS_Rst(SYS_Rst),
|
||||
.Sl_CE(Sl_CE),
|
||||
.Sl_DBus(Sl_DBus),
|
||||
.Sl_Ready(Sl_Ready),
|
||||
.Sl_UE(Sl_UE),
|
||||
.Sl_Wait(Sl_Wait));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+216
@@ -0,0 +1,216 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:57:10 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top system_bd_dlmb_v10_0 -prefix
|
||||
-- system_bd_dlmb_v10_0_ system_bd_dlmb_v10_0_sim_netlist.vhdl
|
||||
-- Design : system_bd_dlmb_v10_0
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity system_bd_dlmb_v10_0_lmb_v10 is
|
||||
port (
|
||||
LMB_Clk : in STD_LOGIC;
|
||||
SYS_Rst : in STD_LOGIC;
|
||||
LMB_Rst : out STD_LOGIC;
|
||||
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
M_ReadStrobe : in STD_LOGIC;
|
||||
M_WriteStrobe : in STD_LOGIC;
|
||||
M_AddrStrobe : in STD_LOGIC;
|
||||
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
|
||||
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB_ReadStrobe : out STD_LOGIC;
|
||||
LMB_WriteStrobe : out STD_LOGIC;
|
||||
LMB_AddrStrobe : out STD_LOGIC;
|
||||
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB_Ready : out STD_LOGIC;
|
||||
LMB_Wait : out STD_LOGIC;
|
||||
LMB_UE : out STD_LOGIC;
|
||||
LMB_CE : out STD_LOGIC;
|
||||
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
|
||||
);
|
||||
attribute C_EXT_RESET_HIGH : integer;
|
||||
attribute C_EXT_RESET_HIGH of system_bd_dlmb_v10_0_lmb_v10 : entity is 1;
|
||||
attribute C_LMB_AWIDTH : integer;
|
||||
attribute C_LMB_AWIDTH of system_bd_dlmb_v10_0_lmb_v10 : entity is 32;
|
||||
attribute C_LMB_DWIDTH : integer;
|
||||
attribute C_LMB_DWIDTH of system_bd_dlmb_v10_0_lmb_v10 : entity is 32;
|
||||
attribute C_LMB_NUM_SLAVES : integer;
|
||||
attribute C_LMB_NUM_SLAVES of system_bd_dlmb_v10_0_lmb_v10 : entity is 1;
|
||||
end system_bd_dlmb_v10_0_lmb_v10;
|
||||
|
||||
architecture STRUCTURE of system_bd_dlmb_v10_0_lmb_v10 is
|
||||
signal \^m_abus\ : STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
signal \^m_addrstrobe\ : STD_LOGIC;
|
||||
signal \^m_be\ : STD_LOGIC_VECTOR ( 0 to 3 );
|
||||
signal \^m_dbus\ : STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
signal \^m_readstrobe\ : STD_LOGIC;
|
||||
signal \^m_writestrobe\ : STD_LOGIC;
|
||||
signal \^sl_ce\ : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal \^sl_dbus\ : STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
signal \^sl_ready\ : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal \^sl_ue\ : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal \^sl_wait\ : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
attribute BOX_TYPE : string;
|
||||
attribute BOX_TYPE of POR_FF_I : label is "PRIMITIVE";
|
||||
attribute XILINX_LEGACY_PRIM : string;
|
||||
attribute XILINX_LEGACY_PRIM of POR_FF_I : label is "FDS";
|
||||
begin
|
||||
LMB_ABus(0 to 31) <= \^m_abus\(0 to 31);
|
||||
LMB_AddrStrobe <= \^m_addrstrobe\;
|
||||
LMB_BE(0 to 3) <= \^m_be\(0 to 3);
|
||||
LMB_CE <= \^sl_ce\(0);
|
||||
LMB_ReadDBus(0 to 31) <= \^sl_dbus\(0 to 31);
|
||||
LMB_ReadStrobe <= \^m_readstrobe\;
|
||||
LMB_Ready <= \^sl_ready\(0);
|
||||
LMB_UE <= \^sl_ue\(0);
|
||||
LMB_Wait <= \^sl_wait\(0);
|
||||
LMB_WriteDBus(0 to 31) <= \^m_dbus\(0 to 31);
|
||||
LMB_WriteStrobe <= \^m_writestrobe\;
|
||||
\^m_abus\(0 to 31) <= M_ABus(0 to 31);
|
||||
\^m_addrstrobe\ <= M_AddrStrobe;
|
||||
\^m_be\(0 to 3) <= M_BE(0 to 3);
|
||||
\^m_dbus\(0 to 31) <= M_DBus(0 to 31);
|
||||
\^m_readstrobe\ <= M_ReadStrobe;
|
||||
\^m_writestrobe\ <= M_WriteStrobe;
|
||||
\^sl_ce\(0) <= Sl_CE(0);
|
||||
\^sl_dbus\(0 to 31) <= Sl_DBus(0 to 31);
|
||||
\^sl_ready\(0) <= Sl_Ready(0);
|
||||
\^sl_ue\(0) <= Sl_UE(0);
|
||||
\^sl_wait\(0) <= Sl_Wait(0);
|
||||
POR_FF_I: unisim.vcomponents.FDSE
|
||||
generic map(
|
||||
INIT => '1'
|
||||
)
|
||||
port map (
|
||||
C => LMB_Clk,
|
||||
CE => '1',
|
||||
D => '0',
|
||||
Q => LMB_Rst,
|
||||
S => SYS_Rst
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity system_bd_dlmb_v10_0 is
|
||||
port (
|
||||
LMB_Clk : in STD_LOGIC;
|
||||
SYS_Rst : in STD_LOGIC;
|
||||
LMB_Rst : out STD_LOGIC;
|
||||
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
M_ReadStrobe : in STD_LOGIC;
|
||||
M_WriteStrobe : in STD_LOGIC;
|
||||
M_AddrStrobe : in STD_LOGIC;
|
||||
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
|
||||
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB_ReadStrobe : out STD_LOGIC;
|
||||
LMB_WriteStrobe : out STD_LOGIC;
|
||||
LMB_AddrStrobe : out STD_LOGIC;
|
||||
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB_Ready : out STD_LOGIC;
|
||||
LMB_Wait : out STD_LOGIC;
|
||||
LMB_UE : out STD_LOGIC;
|
||||
LMB_CE : out STD_LOGIC;
|
||||
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of system_bd_dlmb_v10_0 : entity is true;
|
||||
attribute CHECK_LICENSE_TYPE : string;
|
||||
attribute CHECK_LICENSE_TYPE of system_bd_dlmb_v10_0 : entity is "system_bd_dlmb_v10_0,lmb_v10,{}";
|
||||
attribute downgradeipidentifiedwarnings : string;
|
||||
attribute downgradeipidentifiedwarnings of system_bd_dlmb_v10_0 : entity is "yes";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of system_bd_dlmb_v10_0 : entity is "lmb_v10,Vivado 2019.1.3";
|
||||
end system_bd_dlmb_v10_0;
|
||||
|
||||
architecture STRUCTURE of system_bd_dlmb_v10_0 is
|
||||
attribute C_EXT_RESET_HIGH : integer;
|
||||
attribute C_EXT_RESET_HIGH of U0 : label is 1;
|
||||
attribute C_LMB_AWIDTH : integer;
|
||||
attribute C_LMB_AWIDTH of U0 : label is 32;
|
||||
attribute C_LMB_DWIDTH : integer;
|
||||
attribute C_LMB_DWIDTH of U0 : label is 32;
|
||||
attribute C_LMB_NUM_SLAVES : integer;
|
||||
attribute C_LMB_NUM_SLAVES of U0 : label is 1;
|
||||
attribute x_interface_info : string;
|
||||
attribute x_interface_info of LMB_AddrStrobe : signal is "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE";
|
||||
attribute x_interface_info of LMB_CE : signal is "xilinx.com:interface:lmb:1.0 LMB_M CE";
|
||||
attribute x_interface_info of LMB_Clk : signal is "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
|
||||
attribute x_interface_parameter : string;
|
||||
attribute x_interface_parameter of LMB_Clk : signal is "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M, ASSOCIATED_RESET SYS_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0";
|
||||
attribute x_interface_info of LMB_ReadStrobe : signal is "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE";
|
||||
attribute x_interface_info of LMB_Ready : signal is "xilinx.com:interface:lmb:1.0 LMB_M READY";
|
||||
attribute x_interface_info of LMB_Rst : signal is "xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_M RST";
|
||||
attribute x_interface_parameter of LMB_Rst : signal is "XIL_INTERFACENAME LMB_Sl_0, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, XIL_INTERFACENAME LMB_M, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE";
|
||||
attribute x_interface_info of LMB_UE : signal is "xilinx.com:interface:lmb:1.0 LMB_M UE";
|
||||
attribute x_interface_info of LMB_Wait : signal is "xilinx.com:interface:lmb:1.0 LMB_M WAIT";
|
||||
attribute x_interface_info of LMB_WriteStrobe : signal is "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE";
|
||||
attribute x_interface_info of M_AddrStrobe : signal is "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE";
|
||||
attribute x_interface_info of M_ReadStrobe : signal is "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE";
|
||||
attribute x_interface_info of M_WriteStrobe : signal is "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE";
|
||||
attribute x_interface_info of SYS_Rst : signal is "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST";
|
||||
attribute x_interface_parameter of SYS_Rst : signal is "XIL_INTERFACENAME RST.SYS_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
attribute x_interface_info of LMB_ABus : signal is "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS";
|
||||
attribute x_interface_info of LMB_BE : signal is "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE";
|
||||
attribute x_interface_info of LMB_ReadDBus : signal is "xilinx.com:interface:lmb:1.0 LMB_M READDBUS";
|
||||
attribute x_interface_info of LMB_WriteDBus : signal is "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS";
|
||||
attribute x_interface_info of M_ABus : signal is "xilinx.com:interface:lmb:1.0 LMB_M ABUS";
|
||||
attribute x_interface_info of M_BE : signal is "xilinx.com:interface:lmb:1.0 LMB_M BE";
|
||||
attribute x_interface_info of M_DBus : signal is "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS";
|
||||
attribute x_interface_info of Sl_CE : signal is "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE";
|
||||
attribute x_interface_info of Sl_DBus : signal is "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS";
|
||||
attribute x_interface_info of Sl_Ready : signal is "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY";
|
||||
attribute x_interface_info of Sl_UE : signal is "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE";
|
||||
attribute x_interface_info of Sl_Wait : signal is "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT";
|
||||
begin
|
||||
U0: entity work.system_bd_dlmb_v10_0_lmb_v10
|
||||
port map (
|
||||
LMB_ABus(0 to 31) => LMB_ABus(0 to 31),
|
||||
LMB_AddrStrobe => LMB_AddrStrobe,
|
||||
LMB_BE(0 to 3) => LMB_BE(0 to 3),
|
||||
LMB_CE => LMB_CE,
|
||||
LMB_Clk => LMB_Clk,
|
||||
LMB_ReadDBus(0 to 31) => LMB_ReadDBus(0 to 31),
|
||||
LMB_ReadStrobe => LMB_ReadStrobe,
|
||||
LMB_Ready => LMB_Ready,
|
||||
LMB_Rst => LMB_Rst,
|
||||
LMB_UE => LMB_UE,
|
||||
LMB_Wait => LMB_Wait,
|
||||
LMB_WriteDBus(0 to 31) => LMB_WriteDBus(0 to 31),
|
||||
LMB_WriteStrobe => LMB_WriteStrobe,
|
||||
M_ABus(0 to 31) => M_ABus(0 to 31),
|
||||
M_AddrStrobe => M_AddrStrobe,
|
||||
M_BE(0 to 3) => M_BE(0 to 3),
|
||||
M_DBus(0 to 31) => M_DBus(0 to 31),
|
||||
M_ReadStrobe => M_ReadStrobe,
|
||||
M_WriteStrobe => M_WriteStrobe,
|
||||
SYS_Rst => SYS_Rst,
|
||||
Sl_CE(0) => Sl_CE(0),
|
||||
Sl_DBus(0 to 31) => Sl_DBus(0 to 31),
|
||||
Sl_Ready(0) => Sl_Ready(0),
|
||||
Sl_UE(0) => Sl_UE(0),
|
||||
Sl_Wait(0) => Sl_Wait(0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:57:10 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top system_bd_dlmb_v10_0 -prefix
|
||||
// system_bd_dlmb_v10_0_ system_bd_dlmb_v10_0_stub.v
|
||||
// Design : system_bd_dlmb_v10_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "lmb_v10,Vivado 2019.1.3" *)
|
||||
module system_bd_dlmb_v10_0(LMB_Clk, SYS_Rst, LMB_Rst, M_ABus, M_ReadStrobe,
|
||||
M_WriteStrobe, M_AddrStrobe, M_DBus, M_BE, Sl_DBus, Sl_Ready, Sl_Wait, Sl_UE, Sl_CE, LMB_ABus,
|
||||
LMB_ReadStrobe, LMB_WriteStrobe, LMB_AddrStrobe, LMB_ReadDBus, LMB_WriteDBus, LMB_Ready,
|
||||
LMB_Wait, LMB_UE, LMB_CE, LMB_BE)
|
||||
/* synthesis syn_black_box black_box_pad_pin="LMB_Clk,SYS_Rst,LMB_Rst,M_ABus[0:31],M_ReadStrobe,M_WriteStrobe,M_AddrStrobe,M_DBus[0:31],M_BE[0:3],Sl_DBus[0:31],Sl_Ready[0:0],Sl_Wait[0:0],Sl_UE[0:0],Sl_CE[0:0],LMB_ABus[0:31],LMB_ReadStrobe,LMB_WriteStrobe,LMB_AddrStrobe,LMB_ReadDBus[0:31],LMB_WriteDBus[0:31],LMB_Ready,LMB_Wait,LMB_UE,LMB_CE,LMB_BE[0:3]" */;
|
||||
input LMB_Clk;
|
||||
input SYS_Rst;
|
||||
output LMB_Rst;
|
||||
input [0:31]M_ABus;
|
||||
input M_ReadStrobe;
|
||||
input M_WriteStrobe;
|
||||
input M_AddrStrobe;
|
||||
input [0:31]M_DBus;
|
||||
input [0:3]M_BE;
|
||||
input [0:31]Sl_DBus;
|
||||
input [0:0]Sl_Ready;
|
||||
input [0:0]Sl_Wait;
|
||||
input [0:0]Sl_UE;
|
||||
input [0:0]Sl_CE;
|
||||
output [0:31]LMB_ABus;
|
||||
output LMB_ReadStrobe;
|
||||
output LMB_WriteStrobe;
|
||||
output LMB_AddrStrobe;
|
||||
output [0:31]LMB_ReadDBus;
|
||||
output [0:31]LMB_WriteDBus;
|
||||
output LMB_Ready;
|
||||
output LMB_Wait;
|
||||
output LMB_UE;
|
||||
output LMB_CE;
|
||||
output [0:3]LMB_BE;
|
||||
endmodule
|
||||
+54
@@ -0,0 +1,54 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:57:10 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_dlmb_v10_0 -prefix
|
||||
-- system_bd_dlmb_v10_0_ system_bd_dlmb_v10_0_stub.vhdl
|
||||
-- Design : system_bd_dlmb_v10_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_bd_dlmb_v10_0 is
|
||||
Port (
|
||||
LMB_Clk : in STD_LOGIC;
|
||||
SYS_Rst : in STD_LOGIC;
|
||||
LMB_Rst : out STD_LOGIC;
|
||||
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
M_ReadStrobe : in STD_LOGIC;
|
||||
M_WriteStrobe : in STD_LOGIC;
|
||||
M_AddrStrobe : in STD_LOGIC;
|
||||
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
|
||||
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB_ReadStrobe : out STD_LOGIC;
|
||||
LMB_WriteStrobe : out STD_LOGIC;
|
||||
LMB_AddrStrobe : out STD_LOGIC;
|
||||
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
|
||||
LMB_Ready : out STD_LOGIC;
|
||||
LMB_Wait : out STD_LOGIC;
|
||||
LMB_UE : out STD_LOGIC;
|
||||
LMB_CE : out STD_LOGIC;
|
||||
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
|
||||
);
|
||||
|
||||
end system_bd_dlmb_v10_0;
|
||||
|
||||
architecture stub of system_bd_dlmb_v10_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "LMB_Clk,SYS_Rst,LMB_Rst,M_ABus[0:31],M_ReadStrobe,M_WriteStrobe,M_AddrStrobe,M_DBus[0:31],M_BE[0:3],Sl_DBus[0:31],Sl_Ready[0:0],Sl_Wait[0:0],Sl_UE[0:0],Sl_CE[0:0],LMB_ABus[0:31],LMB_ReadStrobe,LMB_WriteStrobe,LMB_AddrStrobe,LMB_ReadDBus[0:31],LMB_WriteDBus[0:31],LMB_Ready,LMB_Wait,LMB_UE,LMB_CE,LMB_BE[0:3]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "lmb_v10,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+295
@@ -0,0 +1,295 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
|
||||
-- IP Revision: 16
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY lmb_bram_if_cntlr_v4_0_16;
|
||||
USE lmb_bram_if_cntlr_v4_0_16.lmb_bram_if_cntlr;
|
||||
|
||||
ENTITY system_bd_ilmb_bram_if_cntlr_0 IS
|
||||
PORT (
|
||||
LMB_Clk : IN STD_LOGIC;
|
||||
LMB_Rst : IN STD_LOGIC;
|
||||
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_AddrStrobe : IN STD_LOGIC;
|
||||
LMB_ReadStrobe : IN STD_LOGIC;
|
||||
LMB_WriteStrobe : IN STD_LOGIC;
|
||||
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl_Ready : OUT STD_LOGIC;
|
||||
Sl_Wait : OUT STD_LOGIC;
|
||||
Sl_UE : OUT STD_LOGIC;
|
||||
Sl_CE : OUT STD_LOGIC;
|
||||
BRAM_Rst_A : OUT STD_LOGIC;
|
||||
BRAM_Clk_A : OUT STD_LOGIC;
|
||||
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
BRAM_EN_A : OUT STD_LOGIC;
|
||||
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
|
||||
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
|
||||
);
|
||||
END system_bd_ilmb_bram_if_cntlr_0;
|
||||
|
||||
ARCHITECTURE system_bd_ilmb_bram_if_cntlr_0_arch OF system_bd_ilmb_bram_if_cntlr_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT lmb_bram_if_cntlr IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_HIGHADDR : STD_LOGIC_VECTOR;
|
||||
C_BASEADDR : STD_LOGIC_VECTOR;
|
||||
C_NUM_LMB : INTEGER;
|
||||
C_MASK : STD_LOGIC_VECTOR;
|
||||
C_MASK1 : STD_LOGIC_VECTOR;
|
||||
C_MASK2 : STD_LOGIC_VECTOR;
|
||||
C_MASK3 : STD_LOGIC_VECTOR;
|
||||
C_LMB_AWIDTH : INTEGER;
|
||||
C_LMB_DWIDTH : INTEGER;
|
||||
C_ECC : INTEGER;
|
||||
C_INTERCONNECT : INTEGER;
|
||||
C_FAULT_INJECT : INTEGER;
|
||||
C_CE_FAILING_REGISTERS : INTEGER;
|
||||
C_UE_FAILING_REGISTERS : INTEGER;
|
||||
C_ECC_STATUS_REGISTERS : INTEGER;
|
||||
C_ECC_ONOFF_REGISTER : INTEGER;
|
||||
C_ECC_ONOFF_RESET_VALUE : INTEGER;
|
||||
C_CE_COUNTER_WIDTH : INTEGER;
|
||||
C_WRITE_ACCESS : INTEGER;
|
||||
C_BRAM_AWIDTH : INTEGER;
|
||||
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
LMB_Clk : IN STD_LOGIC;
|
||||
LMB_Rst : IN STD_LOGIC;
|
||||
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_AddrStrobe : IN STD_LOGIC;
|
||||
LMB_ReadStrobe : IN STD_LOGIC;
|
||||
LMB_WriteStrobe : IN STD_LOGIC;
|
||||
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl_Ready : OUT STD_LOGIC;
|
||||
Sl_Wait : OUT STD_LOGIC;
|
||||
Sl_UE : OUT STD_LOGIC;
|
||||
Sl_CE : OUT STD_LOGIC;
|
||||
LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB1_AddrStrobe : IN STD_LOGIC;
|
||||
LMB1_ReadStrobe : IN STD_LOGIC;
|
||||
LMB1_WriteStrobe : IN STD_LOGIC;
|
||||
LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl1_Ready : OUT STD_LOGIC;
|
||||
Sl1_Wait : OUT STD_LOGIC;
|
||||
Sl1_UE : OUT STD_LOGIC;
|
||||
Sl1_CE : OUT STD_LOGIC;
|
||||
LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB2_AddrStrobe : IN STD_LOGIC;
|
||||
LMB2_ReadStrobe : IN STD_LOGIC;
|
||||
LMB2_WriteStrobe : IN STD_LOGIC;
|
||||
LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl2_Ready : OUT STD_LOGIC;
|
||||
Sl2_Wait : OUT STD_LOGIC;
|
||||
Sl2_UE : OUT STD_LOGIC;
|
||||
Sl2_CE : OUT STD_LOGIC;
|
||||
LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB3_AddrStrobe : IN STD_LOGIC;
|
||||
LMB3_ReadStrobe : IN STD_LOGIC;
|
||||
LMB3_WriteStrobe : IN STD_LOGIC;
|
||||
LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl3_Ready : OUT STD_LOGIC;
|
||||
Sl3_Wait : OUT STD_LOGIC;
|
||||
Sl3_UE : OUT STD_LOGIC;
|
||||
Sl3_CE : OUT STD_LOGIC;
|
||||
BRAM_Rst_A : OUT STD_LOGIC;
|
||||
BRAM_Clk_A : OUT STD_LOGIC;
|
||||
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
BRAM_EN_A : OUT STD_LOGIC;
|
||||
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
|
||||
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
S_AXI_CTRL_ACLK : IN STD_LOGIC;
|
||||
S_AXI_CTRL_ARESETN : IN STD_LOGIC;
|
||||
S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_CTRL_AWVALID : IN STD_LOGIC;
|
||||
S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXI_CTRL_WVALID : IN STD_LOGIC;
|
||||
S_AXI_CTRL_WREADY : OUT STD_LOGIC;
|
||||
S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_CTRL_BVALID : OUT STD_LOGIC;
|
||||
S_AXI_CTRL_BREADY : IN STD_LOGIC;
|
||||
S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_CTRL_ARVALID : IN STD_LOGIC;
|
||||
S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_CTRL_RVALID : OUT STD_LOGIC;
|
||||
S_AXI_CTRL_RREADY : IN STD_LOGIC;
|
||||
UE : OUT STD_LOGIC;
|
||||
CE : OUT STD_LOGIC;
|
||||
Interrupt : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT lmb_bram_if_cntlr;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF BRAM_Rst_A: SIGNAL IS "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 262144, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_ABus: SIGNAL IS "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Rst: SIGNAL IS "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Clk: SIGNAL IS "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
|
||||
BEGIN
|
||||
U0 : lmb_bram_if_cntlr
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "kintex7",
|
||||
C_HIGHADDR => X"000000000003FFFF",
|
||||
C_BASEADDR => X"0000000000000000",
|
||||
C_NUM_LMB => 1,
|
||||
C_MASK => X"0000000000000000",
|
||||
C_MASK1 => X"0000000000800000",
|
||||
C_MASK2 => X"0000000000800000",
|
||||
C_MASK3 => X"0000000000800000",
|
||||
C_LMB_AWIDTH => 32,
|
||||
C_LMB_DWIDTH => 32,
|
||||
C_ECC => 0,
|
||||
C_INTERCONNECT => 0,
|
||||
C_FAULT_INJECT => 0,
|
||||
C_CE_FAILING_REGISTERS => 0,
|
||||
C_UE_FAILING_REGISTERS => 0,
|
||||
C_ECC_STATUS_REGISTERS => 0,
|
||||
C_ECC_ONOFF_REGISTER => 0,
|
||||
C_ECC_ONOFF_RESET_VALUE => 1,
|
||||
C_CE_COUNTER_WIDTH => 0,
|
||||
C_WRITE_ACCESS => 2,
|
||||
C_BRAM_AWIDTH => 32,
|
||||
C_S_AXI_CTRL_ADDR_WIDTH => 32,
|
||||
C_S_AXI_CTRL_DATA_WIDTH => 32
|
||||
)
|
||||
PORT MAP (
|
||||
LMB_Clk => LMB_Clk,
|
||||
LMB_Rst => LMB_Rst,
|
||||
LMB_ABus => LMB_ABus,
|
||||
LMB_WriteDBus => LMB_WriteDBus,
|
||||
LMB_AddrStrobe => LMB_AddrStrobe,
|
||||
LMB_ReadStrobe => LMB_ReadStrobe,
|
||||
LMB_WriteStrobe => LMB_WriteStrobe,
|
||||
LMB_BE => LMB_BE,
|
||||
Sl_DBus => Sl_DBus,
|
||||
Sl_Ready => Sl_Ready,
|
||||
Sl_Wait => Sl_Wait,
|
||||
Sl_UE => Sl_UE,
|
||||
Sl_CE => Sl_CE,
|
||||
LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB1_AddrStrobe => '0',
|
||||
LMB1_ReadStrobe => '0',
|
||||
LMB1_WriteStrobe => '0',
|
||||
LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB2_AddrStrobe => '0',
|
||||
LMB2_ReadStrobe => '0',
|
||||
LMB2_WriteStrobe => '0',
|
||||
LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB3_AddrStrobe => '0',
|
||||
LMB3_ReadStrobe => '0',
|
||||
LMB3_WriteStrobe => '0',
|
||||
LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
BRAM_Rst_A => BRAM_Rst_A,
|
||||
BRAM_Clk_A => BRAM_Clk_A,
|
||||
BRAM_Addr_A => BRAM_Addr_A,
|
||||
BRAM_EN_A => BRAM_EN_A,
|
||||
BRAM_WEN_A => BRAM_WEN_A,
|
||||
BRAM_Dout_A => BRAM_Dout_A,
|
||||
BRAM_Din_A => BRAM_Din_A,
|
||||
S_AXI_CTRL_ACLK => '0',
|
||||
S_AXI_CTRL_ARESETN => '0',
|
||||
S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
S_AXI_CTRL_AWVALID => '0',
|
||||
S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
S_AXI_CTRL_WVALID => '0',
|
||||
S_AXI_CTRL_BREADY => '0',
|
||||
S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
S_AXI_CTRL_ARVALID => '0',
|
||||
S_AXI_CTRL_RREADY => '0'
|
||||
);
|
||||
END system_bd_ilmb_bram_if_cntlr_0_arch;
|
||||
+302
@@ -0,0 +1,302 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
|
||||
-- IP Revision: 16
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY lmb_bram_if_cntlr_v4_0_16;
|
||||
USE lmb_bram_if_cntlr_v4_0_16.lmb_bram_if_cntlr;
|
||||
|
||||
ENTITY system_bd_ilmb_bram_if_cntlr_0 IS
|
||||
PORT (
|
||||
LMB_Clk : IN STD_LOGIC;
|
||||
LMB_Rst : IN STD_LOGIC;
|
||||
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_AddrStrobe : IN STD_LOGIC;
|
||||
LMB_ReadStrobe : IN STD_LOGIC;
|
||||
LMB_WriteStrobe : IN STD_LOGIC;
|
||||
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl_Ready : OUT STD_LOGIC;
|
||||
Sl_Wait : OUT STD_LOGIC;
|
||||
Sl_UE : OUT STD_LOGIC;
|
||||
Sl_CE : OUT STD_LOGIC;
|
||||
BRAM_Rst_A : OUT STD_LOGIC;
|
||||
BRAM_Clk_A : OUT STD_LOGIC;
|
||||
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
BRAM_EN_A : OUT STD_LOGIC;
|
||||
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
|
||||
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
|
||||
);
|
||||
END system_bd_ilmb_bram_if_cntlr_0;
|
||||
|
||||
ARCHITECTURE system_bd_ilmb_bram_if_cntlr_0_arch OF system_bd_ilmb_bram_if_cntlr_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT lmb_bram_if_cntlr IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_HIGHADDR : STD_LOGIC_VECTOR;
|
||||
C_BASEADDR : STD_LOGIC_VECTOR;
|
||||
C_NUM_LMB : INTEGER;
|
||||
C_MASK : STD_LOGIC_VECTOR;
|
||||
C_MASK1 : STD_LOGIC_VECTOR;
|
||||
C_MASK2 : STD_LOGIC_VECTOR;
|
||||
C_MASK3 : STD_LOGIC_VECTOR;
|
||||
C_LMB_AWIDTH : INTEGER;
|
||||
C_LMB_DWIDTH : INTEGER;
|
||||
C_ECC : INTEGER;
|
||||
C_INTERCONNECT : INTEGER;
|
||||
C_FAULT_INJECT : INTEGER;
|
||||
C_CE_FAILING_REGISTERS : INTEGER;
|
||||
C_UE_FAILING_REGISTERS : INTEGER;
|
||||
C_ECC_STATUS_REGISTERS : INTEGER;
|
||||
C_ECC_ONOFF_REGISTER : INTEGER;
|
||||
C_ECC_ONOFF_RESET_VALUE : INTEGER;
|
||||
C_CE_COUNTER_WIDTH : INTEGER;
|
||||
C_WRITE_ACCESS : INTEGER;
|
||||
C_BRAM_AWIDTH : INTEGER;
|
||||
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
LMB_Clk : IN STD_LOGIC;
|
||||
LMB_Rst : IN STD_LOGIC;
|
||||
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB_AddrStrobe : IN STD_LOGIC;
|
||||
LMB_ReadStrobe : IN STD_LOGIC;
|
||||
LMB_WriteStrobe : IN STD_LOGIC;
|
||||
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl_Ready : OUT STD_LOGIC;
|
||||
Sl_Wait : OUT STD_LOGIC;
|
||||
Sl_UE : OUT STD_LOGIC;
|
||||
Sl_CE : OUT STD_LOGIC;
|
||||
LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB1_AddrStrobe : IN STD_LOGIC;
|
||||
LMB1_ReadStrobe : IN STD_LOGIC;
|
||||
LMB1_WriteStrobe : IN STD_LOGIC;
|
||||
LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl1_Ready : OUT STD_LOGIC;
|
||||
Sl1_Wait : OUT STD_LOGIC;
|
||||
Sl1_UE : OUT STD_LOGIC;
|
||||
Sl1_CE : OUT STD_LOGIC;
|
||||
LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB2_AddrStrobe : IN STD_LOGIC;
|
||||
LMB2_ReadStrobe : IN STD_LOGIC;
|
||||
LMB2_WriteStrobe : IN STD_LOGIC;
|
||||
LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl2_Ready : OUT STD_LOGIC;
|
||||
Sl2_Wait : OUT STD_LOGIC;
|
||||
Sl2_UE : OUT STD_LOGIC;
|
||||
Sl2_CE : OUT STD_LOGIC;
|
||||
LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
LMB3_AddrStrobe : IN STD_LOGIC;
|
||||
LMB3_ReadStrobe : IN STD_LOGIC;
|
||||
LMB3_WriteStrobe : IN STD_LOGIC;
|
||||
LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
|
||||
Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
Sl3_Ready : OUT STD_LOGIC;
|
||||
Sl3_Wait : OUT STD_LOGIC;
|
||||
Sl3_UE : OUT STD_LOGIC;
|
||||
Sl3_CE : OUT STD_LOGIC;
|
||||
BRAM_Rst_A : OUT STD_LOGIC;
|
||||
BRAM_Clk_A : OUT STD_LOGIC;
|
||||
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
BRAM_EN_A : OUT STD_LOGIC;
|
||||
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
|
||||
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
|
||||
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
|
||||
S_AXI_CTRL_ACLK : IN STD_LOGIC;
|
||||
S_AXI_CTRL_ARESETN : IN STD_LOGIC;
|
||||
S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_CTRL_AWVALID : IN STD_LOGIC;
|
||||
S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXI_CTRL_WVALID : IN STD_LOGIC;
|
||||
S_AXI_CTRL_WREADY : OUT STD_LOGIC;
|
||||
S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_CTRL_BVALID : OUT STD_LOGIC;
|
||||
S_AXI_CTRL_BREADY : IN STD_LOGIC;
|
||||
S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_CTRL_ARVALID : IN STD_LOGIC;
|
||||
S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_CTRL_RVALID : OUT STD_LOGIC;
|
||||
S_AXI_CTRL_RREADY : IN STD_LOGIC;
|
||||
UE : OUT STD_LOGIC;
|
||||
CE : OUT STD_LOGIC;
|
||||
Interrupt : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT lmb_bram_if_cntlr;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_bd_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "lmb_bram_if_cntlr,Vivado 2019.1.3";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_bd_ilmb_bram_if_cntlr_0_arch : ARCHITECTURE IS "system_bd_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_bd_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "system_bd_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{x_ipProduct=Vivado 2019.1.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_bram_if_cntlr,x_ipVersion=4.0,x_ipCoreRevision=16,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=kintex7,C_HIGHADDR=0x000000000003FFFF,C_BASEADDR=0x0000000000000000,C_NUM_LMB=1,C_MASK=0x0000000000000000,C_MASK1=0x0000000000800000,C_MASK2=0x0000000000800000,C_MASK3=0x0000000000800000,C_LMB_AWIDTH=32,C_LMB_DWIDTH=32,C_ECC=0,C_INTERCONNECT=0,C_FAULT_INJECT=0,C_CE_FAIL" &
|
||||
"ING_REGISTERS=0,C_UE_FAILING_REGISTERS=0,C_ECC_STATUS_REGISTERS=0,C_ECC_ONOFF_REGISTER=0,C_ECC_ONOFF_RESET_VALUE=1,C_CE_COUNTER_WIDTH=0,C_WRITE_ACCESS=2,C_BRAM_AWIDTH=32,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF BRAM_Rst_A: SIGNAL IS "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 262144, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_ABus: SIGNAL IS "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Rst: SIGNAL IS "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Clk: SIGNAL IS "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
|
||||
BEGIN
|
||||
U0 : lmb_bram_if_cntlr
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "kintex7",
|
||||
C_HIGHADDR => X"000000000003FFFF",
|
||||
C_BASEADDR => X"0000000000000000",
|
||||
C_NUM_LMB => 1,
|
||||
C_MASK => X"0000000000000000",
|
||||
C_MASK1 => X"0000000000800000",
|
||||
C_MASK2 => X"0000000000800000",
|
||||
C_MASK3 => X"0000000000800000",
|
||||
C_LMB_AWIDTH => 32,
|
||||
C_LMB_DWIDTH => 32,
|
||||
C_ECC => 0,
|
||||
C_INTERCONNECT => 0,
|
||||
C_FAULT_INJECT => 0,
|
||||
C_CE_FAILING_REGISTERS => 0,
|
||||
C_UE_FAILING_REGISTERS => 0,
|
||||
C_ECC_STATUS_REGISTERS => 0,
|
||||
C_ECC_ONOFF_REGISTER => 0,
|
||||
C_ECC_ONOFF_RESET_VALUE => 1,
|
||||
C_CE_COUNTER_WIDTH => 0,
|
||||
C_WRITE_ACCESS => 2,
|
||||
C_BRAM_AWIDTH => 32,
|
||||
C_S_AXI_CTRL_ADDR_WIDTH => 32,
|
||||
C_S_AXI_CTRL_DATA_WIDTH => 32
|
||||
)
|
||||
PORT MAP (
|
||||
LMB_Clk => LMB_Clk,
|
||||
LMB_Rst => LMB_Rst,
|
||||
LMB_ABus => LMB_ABus,
|
||||
LMB_WriteDBus => LMB_WriteDBus,
|
||||
LMB_AddrStrobe => LMB_AddrStrobe,
|
||||
LMB_ReadStrobe => LMB_ReadStrobe,
|
||||
LMB_WriteStrobe => LMB_WriteStrobe,
|
||||
LMB_BE => LMB_BE,
|
||||
Sl_DBus => Sl_DBus,
|
||||
Sl_Ready => Sl_Ready,
|
||||
Sl_Wait => Sl_Wait,
|
||||
Sl_UE => Sl_UE,
|
||||
Sl_CE => Sl_CE,
|
||||
LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB1_AddrStrobe => '0',
|
||||
LMB1_ReadStrobe => '0',
|
||||
LMB1_WriteStrobe => '0',
|
||||
LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB2_AddrStrobe => '0',
|
||||
LMB2_ReadStrobe => '0',
|
||||
LMB2_WriteStrobe => '0',
|
||||
LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
LMB3_AddrStrobe => '0',
|
||||
LMB3_ReadStrobe => '0',
|
||||
LMB3_WriteStrobe => '0',
|
||||
LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
BRAM_Rst_A => BRAM_Rst_A,
|
||||
BRAM_Clk_A => BRAM_Clk_A,
|
||||
BRAM_Addr_A => BRAM_Addr_A,
|
||||
BRAM_EN_A => BRAM_EN_A,
|
||||
BRAM_WEN_A => BRAM_WEN_A,
|
||||
BRAM_Dout_A => BRAM_Dout_A,
|
||||
BRAM_Din_A => BRAM_Din_A,
|
||||
S_AXI_CTRL_ACLK => '0',
|
||||
S_AXI_CTRL_ARESETN => '0',
|
||||
S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
S_AXI_CTRL_AWVALID => '0',
|
||||
S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
S_AXI_CTRL_WVALID => '0',
|
||||
S_AXI_CTRL_BREADY => '0',
|
||||
S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
S_AXI_CTRL_ARVALID => '0',
|
||||
S_AXI_CTRL_RREADY => '0'
|
||||
);
|
||||
END system_bd_ilmb_bram_if_cntlr_0_arch;
|
||||
BIN
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