diff --git a/.gitignore b/.gitignore index 05474c80..1e91269c 100644 --- a/.gitignore +++ b/.gitignore @@ -3,14 +3,21 @@ ################################################################################ # everything -/* +* # exclude the directory structure !/adi_library/ +!/adi_library/**/* !/common/ +!/common/**/* +!/custom_ips/ +!/custom_ips/**/* !/modules/ +!/modules/**/* !/projects/ +!/projects/**/* !/template/ +!/template/**/* !/.gitignore !/README.md @@ -37,9 +44,11 @@ vivado_pid* ############################### Modules Specific ############################### ################################################################################ -# exclude project dir expect project tcl -/modules/*/*/project/*/* -!/modules/*/*/project/*/*.tcl +# exclude everything in project directory expect project tcl +# 1. exclude everything in the project directory +# 2. include project tcl +/modules/*/*/project/** +!/modules/*/*/project/*.tcl ################################################################################ ############################### Project Specific ############################### @@ -49,18 +58,33 @@ vivado_pid* # ------------------------------ Vivado Specific ------------------------------- # ------------------------------------------------------------------------------ -# exclude project dir except project tcl -/projects/*/*/project/*/* -!/projects/*/*/project/*/*.tcl +# exclude everything in project directory expect project tcl +# 1. exclude everything in the project directory +# 2. include project tcl +/projects/*/*/project/** +!/projects/*/*/project/*.tcl + +# include project subdirectory structure only +# 1. include project subdirectory +# 2. exclude everything in subdirectory +!/projects/*/*/project/*/ +/projects/*/*/project/*/** # include hardware manager projects and sources +# 1. include `.hw` directory +# 2. include everything in `.hw` directory !/projects/*/*/project/*/*.hw/ +!/projects/*/*/project/*/*.hw/** # include design run results +# 1. include `*.runs` directory +# 2. exclude everything in `.runs` directory +# 3. include `.impl_*` directory +# 4. include `*.bit` file in `.impl_*` directory +# 5. include `*.ltx` file in `.impl_*` directory !/projects/*/*/project/*/*.runs/ -/projects/*/*/project/*/*.runs/* +/projects/*/*/project/*/*.runs/** !/projects/*/*/project/*/*.runs/impl_*/ -/projects/*/*/project/*/*.runs/impl_*/* !/projects/*/*/project/*/*.runs/impl_*/*.bit !/projects/*/*/project/*/*.runs/impl_*/*.ltx @@ -68,8 +92,9 @@ vivado_pid* # -------------------------------- SDK Specific -------------------------------- # ------------------------------------------------------------------------------ -# include sdk dir except project tcl +# include sdk directory and everything in it !/projects/*/*/project/*/*.sdk/ +!/projects/*/*/project/*/*.sdk/** # exclude some obscure hidden SDK folders /projects/*/*/project/*/*.sdk/.metadata/ diff --git a/modules/xc7k410tffg900-2/ad9361_mapping/project/ad9361_mapping/ad9361_mapping.tcl b/modules/xc7k410tffg900-2/ad9361_mapping/project/ad9361_mapping.tcl similarity index 95% rename from modules/xc7k410tffg900-2/ad9361_mapping/project/ad9361_mapping/ad9361_mapping.tcl rename to modules/xc7k410tffg900-2/ad9361_mapping/project/ad9361_mapping.tcl index 417d56ab..024303dd 100644 --- a/modules/xc7k410tffg900-2/ad9361_mapping/project/ad9361_mapping/ad9361_mapping.tcl +++ b/modules/xc7k410tffg900-2/ad9361_mapping/project/ad9361_mapping.tcl @@ -3,7 +3,7 @@ # # ad9361_mapping.tcl: Tcl script for re-creating project 'ad9361_mapping' # -# Generated by Vivado on Sun Mar 19 23:43:33 +0800 2023 +# Generated by Vivado on Tue Mar 21 13:01:16 +0800 2023 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -108,7 +108,7 @@ if { $::argc > 0 } { } # Set the directory path for the original project from where this script was exported -set orig_proj_dir "[file normalize "$origin_dir/"]" +set orig_proj_dir "[file normalize "$origin_dir/ad9361_mapping"]" # Create project create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7k410tffg900-2 @@ -161,18 +161,18 @@ if {[string equal [get_filesets -quiet sources_1] ""]} { # Set 'sources_1' fileset object set obj [get_filesets sources_1] set files [list \ - [file normalize "${origin_dir}/../../ip/ad9361_fifo/ad9361_fifo.xci"] \ - [file normalize "${origin_dir}/../../rtl/ad9361_rx_map_cmos_dual.v"] \ - [file normalize "${origin_dir}/../../rtl/ad9361_rx_map_cmos_single.v"] \ - [file normalize "${origin_dir}/../../rtl/ad9361_rx_map_lvds_dual.v"] \ - [file normalize "${origin_dir}/../../rtl/ad9361_tx_map_cmos_dual.v"] \ - [file normalize "${origin_dir}/../../rtl/ad9361_tx_map_cmos_single.v"] \ - [file normalize "${origin_dir}/../../rtl/ad9361_tx_map_lvds_dual.v"] \ + [file normalize "${origin_dir}/../ip/ad9361_fifo/ad9361_fifo.xci"] \ + [file normalize "${origin_dir}/../rtl/ad9361_rx_map_cmos_dual.v"] \ + [file normalize "${origin_dir}/../rtl/ad9361_rx_map_cmos_single.v"] \ + [file normalize "${origin_dir}/../rtl/ad9361_rx_map_lvds_dual.v"] \ + [file normalize "${origin_dir}/../rtl/ad9361_tx_map_cmos_dual.v"] \ + [file normalize "${origin_dir}/../rtl/ad9361_tx_map_cmos_single.v"] \ + [file normalize "${origin_dir}/../rtl/ad9361_tx_map_lvds_dual.v"] \ ] add_files -norecurse -fileset $obj $files # Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/../../ip/ad9361_fifo/ad9361_fifo.xci" +set file "$origin_dir/../ip/ad9361_fifo/ad9361_fifo.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -212,12 +212,12 @@ if {[string equal [get_filesets -quiet sim_1] ""]} { # Set 'sim_1' fileset object set obj [get_filesets sim_1] set files [list \ - [file normalize "${origin_dir}/../../testbenches/tb_ad9361_rx_map_cmos_dual.v"] \ - [file normalize "${origin_dir}/../../testbenches/tb_ad9361_tx_map_cmos_dual.v"] \ - [file normalize "${origin_dir}/../../testbenches/tb_ad9361_tx_map_lvds_dual.v"] \ - [file normalize "${origin_dir}/../../testbenches/tb_ad9361_rx_map_lvds_dual.v"] \ - [file normalize "${origin_dir}/../../testbenches/tb_ad9361_tx_map_cmos_single.v"] \ - [file normalize "${origin_dir}/../../testbenches/tb_ad9361_rx_map_cmos_single.v"] \ + [file normalize "${origin_dir}/../testbenches/tb_ad9361_rx_map_cmos_dual.v"] \ + [file normalize "${origin_dir}/../testbenches/tb_ad9361_tx_map_cmos_dual.v"] \ + [file normalize "${origin_dir}/../testbenches/tb_ad9361_tx_map_lvds_dual.v"] \ + [file normalize "${origin_dir}/../testbenches/tb_ad9361_rx_map_lvds_dual.v"] \ + [file normalize "${origin_dir}/../testbenches/tb_ad9361_tx_map_cmos_single.v"] \ + [file normalize "${origin_dir}/../testbenches/tb_ad9361_rx_map_cmos_single.v"] \ ] add_files -norecurse -fileset $obj $files diff --git a/modules/xc7k410tffg900-2/multi_ch_cal/project/multi_ch_cal/multi_ch_cal.tcl b/modules/xc7k410tffg900-2/multi_ch_cal/project/multi_ch_cal.tcl similarity index 96% rename from modules/xc7k410tffg900-2/multi_ch_cal/project/multi_ch_cal/multi_ch_cal.tcl rename to modules/xc7k410tffg900-2/multi_ch_cal/project/multi_ch_cal.tcl index 2fc5b57e..6edd0956 100644 --- a/modules/xc7k410tffg900-2/multi_ch_cal/project/multi_ch_cal/multi_ch_cal.tcl +++ b/modules/xc7k410tffg900-2/multi_ch_cal/project/multi_ch_cal.tcl @@ -3,7 +3,7 @@ # # multi_ch_cal.tcl: Tcl script for re-creating project 'multi_ch_cal' # -# Generated by Vivado on Sun Mar 19 23:45:00 +0800 2023 +# Generated by Vivado on Tue Mar 21 13:00:50 +0800 2023 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -27,11 +27,11 @@ # # 3. The following remote source files that were added to the original project:- # -# "D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/atan2_16b/atan2_16b.xci" -# "D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/rotate_16b/rotate_16b.xci" -# "D:/vivado-git/common/ApproxModuli_26bit.v" -# "D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/rtl/multi_ch_cal.v" -# "D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/testbenches/tb_multi_ch_cal.v" +# "d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/atan2_16b/atan2_16b.xci" +# "d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/rotate_16b/rotate_16b.xci" +# "d:/vivado-git/common/ApproxModuli_26bit.v" +# "d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/rtl/multi_ch_cal.v" +# "d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/testbenches/tb_multi_ch_cal.v" # #***************************************************************************************** @@ -100,7 +100,7 @@ if { $::argc > 0 } { } # Set the directory path for the original project from where this script was exported -set orig_proj_dir "[file normalize "$origin_dir/"]" +set orig_proj_dir "[file normalize "$origin_dir/multi_ch_cal"]" # Create project create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7k410tffg900-2 @@ -142,7 +142,6 @@ set_property -name "webtalk.modelsim_export_sim" -value "2" -objects $obj set_property -name "webtalk.questa_export_sim" -value "2" -objects $obj set_property -name "webtalk.riviera_export_sim" -value "2" -objects $obj set_property -name "webtalk.vcs_export_sim" -value "2" -objects $obj -set_property -name "webtalk.xcelium_export_sim" -value "2" -objects $obj set_property -name "webtalk.xsim_export_sim" -value "2" -objects $obj # Create 'sources_1' fileset (if not found) @@ -153,15 +152,15 @@ if {[string equal [get_filesets -quiet sources_1] ""]} { # Set 'sources_1' fileset object set obj [get_filesets sources_1] set files [list \ - [file normalize "${origin_dir}/../../ip/atan2_16b/atan2_16b.xci"] \ - [file normalize "${origin_dir}/../../ip/rotate_16b/rotate_16b.xci"] \ - [file normalize "${origin_dir}/../../../../../common/ApproxModuli_26bit.v"] \ - [file normalize "${origin_dir}/../../rtl/multi_ch_cal.v"] \ + [file normalize "${origin_dir}/../ip/atan2_16b/atan2_16b.xci"] \ + [file normalize "${origin_dir}/../ip/rotate_16b/rotate_16b.xci"] \ + [file normalize "${origin_dir}/../../../../common/ApproxModuli_26bit.v"] \ + [file normalize "${origin_dir}/../rtl/multi_ch_cal.v"] \ ] add_files -norecurse -fileset $obj $files # Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/../../ip/atan2_16b/atan2_16b.xci" +set file "$origin_dir/../ip/atan2_16b/atan2_16b.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -170,7 +169,7 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/../../ip/rotate_16b/rotate_16b.xci" +set file "$origin_dir/../ip/rotate_16b/rotate_16b.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -210,7 +209,7 @@ if {[string equal [get_filesets -quiet sim_1] ""]} { # Set 'sim_1' fileset object set obj [get_filesets sim_1] set files [list \ - [file normalize "${origin_dir}/../../testbenches/tb_multi_ch_cal.v"] \ + [file normalize "${origin_dir}/../testbenches/tb_multi_ch_cal.v"] \ ] add_files -norecurse -fileset $obj $files diff --git a/modules/xc7k410tffg900-2/tx_qpsk/project/tx_qpsk/tx_qpsk.tcl b/modules/xc7k410tffg900-2/tx_qpsk/project/tx_qpsk.tcl similarity index 95% rename from modules/xc7k410tffg900-2/tx_qpsk/project/tx_qpsk/tx_qpsk.tcl rename to modules/xc7k410tffg900-2/tx_qpsk/project/tx_qpsk.tcl index 32f62071..66005789 100644 --- a/modules/xc7k410tffg900-2/tx_qpsk/project/tx_qpsk/tx_qpsk.tcl +++ b/modules/xc7k410tffg900-2/tx_qpsk/project/tx_qpsk.tcl @@ -3,7 +3,7 @@ # # tx_qpsk.tcl: Tcl script for re-creating project 'tx_qpsk' # -# Generated by Vivado on Sun Mar 19 23:49:39 +0800 2023 +# Generated by Vivado on Tue Mar 21 13:00:21 +0800 2023 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -27,14 +27,14 @@ # # 3. The following remote source files that were added to the original project:- # -# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci" -# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci" -# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci" -# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci" -# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/rtl/tx_qpsk.v" +# "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci" +# "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci" +# "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci" +# "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci" +# "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/rtl/tx_qpsk.v" # "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe" # "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe" -# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/testbenches/tb_tx_qpsk.v" +# "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/testbenches/tb_tx_qpsk.v" # #***************************************************************************************** @@ -103,7 +103,7 @@ if { $::argc > 0 } { } # Set the directory path for the original project from where this script was exported -set orig_proj_dir "[file normalize "$origin_dir/"]" +set orig_proj_dir "[file normalize "$origin_dir/tx_qpsk"]" # Create project create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7k410tffg900-2 @@ -156,18 +156,18 @@ if {[string equal [get_filesets -quiet sources_1] ""]} { # Set 'sources_1' fileset object set obj [get_filesets sources_1] set files [list \ - [file normalize "${origin_dir}/../../ip/cmpy_18x8/cmpy_18x8.xci"] \ - [file normalize "${origin_dir}/../../ip/dds_32b_8b/dds_32b_8b.xci"] \ - [file normalize "${origin_dir}/../../ip/hop_rom/hop_rom.xci"] \ - [file normalize "${origin_dir}/../../ip/hrc_64_12_025/hrc_64_12_025.xci"] \ - [file normalize "${origin_dir}/../../rtl/tx_qpsk.v"] \ - [file normalize "${origin_dir}/../../ip/coe/sweep_freq.coe"] \ - [file normalize "${origin_dir}/../../ip/coe/hrc_64_12_025.coe"] \ + [file normalize "${origin_dir}/../ip/cmpy_18x8/cmpy_18x8.xci"] \ + [file normalize "${origin_dir}/../ip/dds_32b_8b/dds_32b_8b.xci"] \ + [file normalize "${origin_dir}/../ip/hop_rom/hop_rom.xci"] \ + [file normalize "${origin_dir}/../ip/hrc_64_12_025/hrc_64_12_025.xci"] \ + [file normalize "${origin_dir}/../rtl/tx_qpsk.v"] \ + [file normalize "${origin_dir}/../ip/coe/sweep_freq.coe"] \ + [file normalize "${origin_dir}/../ip/coe/hrc_64_12_025.coe"] \ ] add_files -norecurse -fileset $obj $files # Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/../../ip/cmpy_18x8/cmpy_18x8.xci" +set file "$origin_dir/../ip/cmpy_18x8/cmpy_18x8.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -176,7 +176,7 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/../../ip/dds_32b_8b/dds_32b_8b.xci" +set file "$origin_dir/../ip/dds_32b_8b/dds_32b_8b.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -185,7 +185,7 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/../../ip/hop_rom/hop_rom.xci" +set file "$origin_dir/../ip/hop_rom/hop_rom.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -194,7 +194,7 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/../../ip/hrc_64_12_025/hrc_64_12_025.xci" +set file "$origin_dir/../ip/hrc_64_12_025/hrc_64_12_025.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -234,7 +234,7 @@ if {[string equal [get_filesets -quiet sim_1] ""]} { # Set 'sim_1' fileset object set obj [get_filesets sim_1] set files [list \ - [file normalize "${origin_dir}/../../testbenches/tb_tx_qpsk.v"] \ + [file normalize "${origin_dir}/../testbenches/tb_tx_qpsk.v"] \ ] add_files -norecurse -fileset $obj $files diff --git a/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.tcl b/projects/datalink_814/dl814_dj/project/dl814_dj.tcl similarity index 93% rename from projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.tcl rename to projects/datalink_814/dl814_dj/project/dl814_dj.tcl index e46a9bd2..a1113565 100644 --- a/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.tcl +++ b/projects/datalink_814/dl814_dj/project/dl814_dj.tcl @@ -3,7 +3,7 @@ # # dl814_dj.tcl: Tcl script for re-creating project 'dl814_dj' # -# Generated by Vivado on Sun Mar 19 20:10:54 +0800 2023 +# Generated by Vivado on Tue Mar 21 11:20:46 +0800 2023 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -112,7 +112,7 @@ if { $::argc > 0 } { } # Set the directory path for the original project from where this script was exported -set orig_proj_dir "[file normalize "$origin_dir/"]" +set orig_proj_dir "[file normalize "$origin_dir/dl814_dj"]" # Create project create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z100ffg900-2 @@ -165,27 +165,27 @@ if {[string equal [get_filesets -quiet sources_1] ""]} { # Set 'sources_1' fileset object set obj [get_filesets sources_1] set files [list \ - [file normalize "${origin_dir}/../../ip/vio_rf_control/vio_rf_control.xci"] \ - [file normalize "${origin_dir}/../../ip/vio_manual_ctrl/vio_manual_ctrl.xci"] \ - [file normalize "${origin_dir}/../../ip/ila_ctrl_signal/ila_ctrl_signal.xci"] \ - [file normalize "${origin_dir}/../../ip/ila_tx_rx/ila_tx_rx.xci"] \ - [file normalize "${origin_dir}/../../ip/cmpy_18x8/cmpy_18x8.xci"] \ - [file normalize "${origin_dir}/../../ip/dds_32b_8b/dds_32b_8b.xci"] \ - [file normalize "${origin_dir}/../../ip/hop_rom/hop_rom.xci"] \ - [file normalize "${origin_dir}/../../ip/hrc_64_12_025/hrc_64_12_025.xci"] \ - [file normalize "${origin_dir}/../../ipi-bds/system_bd/system_bd.bd"] \ - [file normalize "${origin_dir}/../../ip/sig_clk_gen/sig_clk_gen.xci"] \ - [file normalize "${origin_dir}/../../rtl/rf_control.v"] \ - [file normalize "${origin_dir}/../../ipi-bds/system_bd/hdl/system_bd_wrapper.v"] \ - [file normalize "${origin_dir}/../../rtl/tx_qpsk.v"] \ - [file normalize "${origin_dir}/../../rtl/system_top.v"] \ - [file normalize "${origin_dir}/../../ip/coe/hrc_64_12_025.coe"] \ - [file normalize "${origin_dir}/../../ip/coe/sweep_freq.coe"] \ + [file normalize "${origin_dir}/../ip/vio_rf_control/vio_rf_control.xci"] \ + [file normalize "${origin_dir}/../ip/vio_manual_ctrl/vio_manual_ctrl.xci"] \ + [file normalize "${origin_dir}/../ip/ila_ctrl_signal/ila_ctrl_signal.xci"] \ + [file normalize "${origin_dir}/../ip/ila_tx_rx/ila_tx_rx.xci"] \ + [file normalize "${origin_dir}/../ip/cmpy_18x8/cmpy_18x8.xci"] \ + [file normalize "${origin_dir}/../ip/dds_32b_8b/dds_32b_8b.xci"] \ + [file normalize "${origin_dir}/../ip/hop_rom/hop_rom.xci"] \ + [file normalize "${origin_dir}/../ip/hrc_64_12_025/hrc_64_12_025.xci"] \ + [file normalize "${origin_dir}/../ipi-bds/system_bd/system_bd.bd"] \ + [file normalize "${origin_dir}/../ip/sig_clk_gen/sig_clk_gen.xci"] \ + [file normalize "${origin_dir}/../rtl/rf_control.v"] \ + [file normalize "${origin_dir}/../ipi-bds/system_bd/hdl/system_bd_wrapper.v"] \ + [file normalize "${origin_dir}/../rtl/tx_qpsk.v"] \ + [file normalize "${origin_dir}/../rtl/system_top.v"] \ + [file normalize "${origin_dir}/../ip/coe/hrc_64_12_025.coe"] \ + [file normalize "${origin_dir}/../ip/coe/sweep_freq.coe"] \ ] add_files -norecurse -fileset $obj $files # Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/../../ip/vio_rf_control/vio_rf_control.xci" +set file "$origin_dir/../ip/vio_rf_control/vio_rf_control.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -194,7 +194,7 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/../../ip/vio_manual_ctrl/vio_manual_ctrl.xci" +set file "$origin_dir/../ip/vio_manual_ctrl/vio_manual_ctrl.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -203,7 +203,7 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/../../ip/ila_ctrl_signal/ila_ctrl_signal.xci" +set file "$origin_dir/../ip/ila_ctrl_signal/ila_ctrl_signal.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -212,7 +212,7 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/../../ip/ila_tx_rx/ila_tx_rx.xci" +set file "$origin_dir/../ip/ila_tx_rx/ila_tx_rx.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -221,7 +221,7 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/../../ip/cmpy_18x8/cmpy_18x8.xci" +set file "$origin_dir/../ip/cmpy_18x8/cmpy_18x8.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -230,7 +230,7 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/../../ip/dds_32b_8b/dds_32b_8b.xci" +set file "$origin_dir/../ip/dds_32b_8b/dds_32b_8b.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -239,7 +239,7 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/../../ip/hop_rom/hop_rom.xci" +set file "$origin_dir/../ip/hop_rom/hop_rom.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -248,7 +248,7 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/../../ip/hrc_64_12_025/hrc_64_12_025.xci" +set file "$origin_dir/../ip/hrc_64_12_025/hrc_64_12_025.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -257,12 +257,12 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/../../ipi-bds/system_bd/system_bd.bd" +set file "$origin_dir/../ipi-bds/system_bd/system_bd.bd" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "registered_with_manager" -value "1" -objects $file_obj -set file "$origin_dir/../../ip/sig_clk_gen/sig_clk_gen.xci" +set file "$origin_dir/../ip/sig_clk_gen/sig_clk_gen.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -288,9 +288,9 @@ if {[string equal [get_filesets -quiet constrs_1] ""]} { set obj [get_filesets constrs_1] # Add/Import constrs file and set constrs file properties -set file "[file normalize "$origin_dir/../../constraints/z7100_ad9528_ad9371.xdc"]" +set file "[file normalize "$origin_dir/../constraints/z7100_ad9528_ad9371.xdc"]" set file_added [add_files -norecurse -fileset $obj [list $file]] -set file "$origin_dir/../../constraints/z7100_ad9528_ad9371.xdc" +set file "$origin_dir/../constraints/z7100_ad9528_ad9371.xdc" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] set_property -name "file_type" -value "XDC" -objects $file_obj diff --git a/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.sdk/SDK.log b/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.sdk/SDK.log new file mode 100644 index 00000000..edf73d06 --- /dev/null +++ b/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.sdk/SDK.log @@ -0,0 +1,6 @@ +19:17:26 INFO : Registering command handlers for SDK TCF services +19:17:26 INFO : Launching XSCT server: xsct.bat -interactive D:\vivado-git\projects\datalink_814\dl814_dj\project\dl814_dj\dl814_dj.sdk\temp_xsdb_launch_script.tcl +19:17:28 INFO : XSCT server has started successfully. +19:17:28 INFO : Successfully done setting XSCT server connection channel +19:17:28 INFO : Successfully done setting SDK workspace +19:17:28 INFO : Processing command line option -hwspec D:/vivado-git/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.sdk/system_top.hdf. diff --git a/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx.xcix b/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx.xcix deleted file mode 100644 index 72d5fef8..00000000 Binary files a/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx.xcix and /dev/null differ diff --git a/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx.xcix b/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx.xcix deleted file mode 100644 index 499d5b77..00000000 Binary files a/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx.xcix and /dev/null differ diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx.v deleted file mode 100644 index 880b5682..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx.v +++ /dev/null @@ -1,85 +0,0 @@ - -// file: selectio_lvds_rx.v -// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//---------------------------------------------------------------------------- -// User entered comments -//---------------------------------------------------------------------------- -// None -//---------------------------------------------------------------------------- - -`timescale 1ps/1ps - -(* CORE_GENERATION_INFO = "selectio_lvds_rx,selectio_wiz_v5_1_13,{component_name=selectio_lvds_rx,bus_dir=INPUTS,bus_sig_type=SINGLE,bus_io_std=LVCMOS33,use_serialization=false,use_phase_detector=false,serialization_factor=4,enable_bitslip=false,enable_train=false,system_data_width=2,bus_in_delay=NONE,bus_out_delay=NONE,clk_sig_type=SINGLE,clk_io_std=LVCMOS18,clk_buf=BUFIO2,active_edge=RISING,clk_delay=NONE,selio_bus_in_delay=NONE,selio_bus_out_delay=NONE,selio_clk_buf=MMCM,selio_active_edge=SDR,selio_ddr_alignment=SAME_EDGE_PIPELINED,selio_oddr_alignment=SAME_EDGE,ddr_alignment=C0,selio_interface_type=NETWORKING,interface_type=NETWORKING,selio_bus_in_tap=0,selio_bus_out_tap=0,selio_clk_io_std=LVCMOS33,selio_clk_sig_type=SINGLE}" *) - -module selectio_lvds_rx - // width of the data for the system - #(parameter SYS_W = 2, - // width of the data for the device - parameter DEV_W = 2) - ( - // From the system into the device - input [SYS_W-1:0] data_in_from_pins, - output [DEV_W-1:0] data_in_to_device, - input clk_in, // Fast clock input from PLL/MMCM - input io_reset); - - - selectio_lvds_rx_selectio_wiz - #( - .SYS_W(SYS_W), - .DEV_W(DEV_W) - ) - inst - ( - .data_in_from_pins(data_in_from_pins), - .data_in_to_device(data_in_to_device), - .clk_in(clk_in), - .io_reset(io_reset) -); - -endmodule - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx.veo b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx.veo deleted file mode 100644 index 6f4444f8..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx.veo +++ /dev/null @@ -1,67 +0,0 @@ - -// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. - - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -// User NOTES: -//None - - selectio_lvds_rx - instance_name - ( - .data_in_from_pins(data_in_from_pins), // input [1:0] data_in_from_pins - .data_in_to_device(data_in_to_device), // output [1:0] data_in_to_device - .clk_in(clk_in), // input clk_in - .io_reset(io_reset) // input io_reset -); - -// INST_TAG_END ------ End INSTANTIATION Template --------- - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v deleted file mode 100644 index 5f3e4aa0..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v +++ /dev/null @@ -1,115 +0,0 @@ - -// file: selectio_lvds_rx_selectio_wiz.v -// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//---------------------------------------------------------------------------- -// User entered comments -//---------------------------------------------------------------------------- -// None -//---------------------------------------------------------------------------- - -`timescale 1ps/1ps - -module selectio_lvds_rx_selectio_wiz - // width of the data for the system - #(parameter SYS_W = 2, - // width of the data for the device - parameter DEV_W = 2) - ( - // From the system into the device - input [SYS_W-1:0] data_in_from_pins, - output [DEV_W-1:0] data_in_to_device, - input clk_in, // Fast clock input from PLL/MMCM - input io_reset); - wire clock_enable = 1'b1; - // Signal declarations - ////------------------------------ - // After the buffer - wire [SYS_W-1:0] data_in_from_pins_int; - // Between the delay and serdes - wire [SYS_W-1:0] data_in_from_pins_delay; - // Create the clock logic - - - assign clk_in_int_buf = clk_in; // clock coming from MMCM - - // We have multiple bits- step over every bit, instantiating the required elements - genvar pin_count; - generate for (pin_count = 0; pin_count < SYS_W; pin_count = pin_count + 1) begin: pins - // Instantiate the buffers - ////------------------------------ - // Instantiate a buffer for every bit of the data bus - IBUF - #(.IOSTANDARD ("LVCMOS33")) - ibuf_inst - (.I (data_in_from_pins [pin_count]), - .O (data_in_from_pins_int[pin_count])); - - // Pass through the delay - ////------------------------------- - assign data_in_from_pins_delay[pin_count] = data_in_from_pins_int[pin_count]; - - // Connect the delayed data to the fabric - ////-------------------------------------- - - // Pack the registers into the IOB - - wire data_in_to_device_int; - (* IOB = "true" *) - FDRE fdre_in_inst - (.D (data_in_from_pins_delay[pin_count]), - .C (clk_in_int_buf), - .CE (clock_enable), - .R (io_reset), - .Q (data_in_to_device_int) - ); - assign data_in_to_device[pin_count] = data_in_to_device_int; - end - endgenerate - -//// NO ODELAY - -endmodule diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_sim_netlist.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_sim_netlist.v deleted file mode 100644 index 925586ae..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_sim_netlist.v +++ /dev/null @@ -1,168 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sun Mar 19 18:25:55 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -// D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.v -// Design : selectio_lvds_rx -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* DEV_W = "2" *) (* SYS_W = "2" *) -(* NotValidForBitStream *) -module selectio_lvds_rx - (data_in_from_pins, - data_in_to_device, - clk_in, - io_reset); - input [1:0]data_in_from_pins; - output [1:0]data_in_to_device; - input clk_in; - input io_reset; - - wire clk_in; - (* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire [1:0]data_in_from_pins; - wire [1:0]data_in_to_device; - wire io_reset; - - (* DEV_W = "2" *) - (* SYS_W = "2" *) - selectio_lvds_rx_selectio_lvds_rx_selectio_wiz inst - (.clk_in(clk_in), - .data_in_from_pins(data_in_from_pins), - .data_in_to_device(data_in_to_device), - .io_reset(io_reset)); -endmodule - -(* DEV_W = "2" *) (* ORIG_REF_NAME = "selectio_lvds_rx_selectio_wiz" *) (* SYS_W = "2" *) -module selectio_lvds_rx_selectio_lvds_rx_selectio_wiz - (data_in_from_pins, - data_in_to_device, - clk_in, - io_reset); - input [1:0]data_in_from_pins; - output [1:0]data_in_to_device; - input clk_in; - input io_reset; - - wire clk_in; - wire [1:0]data_in_from_pins; - wire [1:0]data_in_from_pins_int; - wire [1:0]data_in_to_device; - wire io_reset; - - (* BOX_TYPE = "PRIMITIVE" *) - (* IOB = "TRUE" *) - FDRE #( - .INIT(1'b0), - .IS_C_INVERTED(1'b0), - .IS_D_INVERTED(1'b0), - .IS_R_INVERTED(1'b0)) - \pins[0].fdre_in_inst - (.C(clk_in), - .CE(1'b1), - .D(data_in_from_pins_int[0]), - .Q(data_in_to_device[0]), - .R(io_reset)); - (* BOX_TYPE = "PRIMITIVE" *) - (* CAPACITANCE = "DONT_CARE" *) - (* IBUF_DELAY_VALUE = "0" *) - (* IFD_DELAY_VALUE = "AUTO" *) - IBUF \pins[0].ibuf_inst - (.I(data_in_from_pins[0]), - .O(data_in_from_pins_int[0])); - (* BOX_TYPE = "PRIMITIVE" *) - (* IOB = "TRUE" *) - FDRE #( - .INIT(1'b0), - .IS_C_INVERTED(1'b0), - .IS_D_INVERTED(1'b0), - .IS_R_INVERTED(1'b0)) - \pins[1].fdre_in_inst - (.C(clk_in), - .CE(1'b1), - .D(data_in_from_pins_int[1]), - .Q(data_in_to_device[1]), - .R(io_reset)); - (* BOX_TYPE = "PRIMITIVE" *) - (* CAPACITANCE = "DONT_CARE" *) - (* IBUF_DELAY_VALUE = "0" *) - (* IFD_DELAY_VALUE = "AUTO" *) - IBUF \pins[1].ibuf_inst - (.I(data_in_from_pins[1]), - .O(data_in_from_pins_int[1])); -endmodule -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_sim_netlist.vhdl b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_sim_netlist.vhdl deleted file mode 100644 index 8998975d..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_sim_netlist.vhdl +++ /dev/null @@ -1,121 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sun Mar 19 18:25:55 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim --- D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.vhdl --- Design : selectio_lvds_rx --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity selectio_lvds_rx_selectio_lvds_rx_selectio_wiz is - port ( - data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 ); - data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 ); - clk_in : in STD_LOGIC; - io_reset : in STD_LOGIC - ); - attribute DEV_W : integer; - attribute DEV_W of selectio_lvds_rx_selectio_lvds_rx_selectio_wiz : entity is 2; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of selectio_lvds_rx_selectio_lvds_rx_selectio_wiz : entity is "selectio_lvds_rx_selectio_wiz"; - attribute SYS_W : integer; - attribute SYS_W of selectio_lvds_rx_selectio_lvds_rx_selectio_wiz : entity is 2; -end selectio_lvds_rx_selectio_lvds_rx_selectio_wiz; - -architecture STRUCTURE of selectio_lvds_rx_selectio_lvds_rx_selectio_wiz is - signal data_in_from_pins_int : STD_LOGIC_VECTOR ( 1 downto 0 ); - attribute BOX_TYPE : string; - attribute BOX_TYPE of \pins[0].fdre_in_inst\ : label is "PRIMITIVE"; - attribute IOB : string; - attribute IOB of \pins[0].fdre_in_inst\ : label is "TRUE"; - attribute BOX_TYPE of \pins[0].ibuf_inst\ : label is "PRIMITIVE"; - attribute CAPACITANCE : string; - attribute CAPACITANCE of \pins[0].ibuf_inst\ : label is "DONT_CARE"; - attribute IBUF_DELAY_VALUE : string; - attribute IBUF_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "0"; - attribute IFD_DELAY_VALUE : string; - attribute IFD_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "AUTO"; - attribute BOX_TYPE of \pins[1].fdre_in_inst\ : label is "PRIMITIVE"; - attribute IOB of \pins[1].fdre_in_inst\ : label is "TRUE"; - attribute BOX_TYPE of \pins[1].ibuf_inst\ : label is "PRIMITIVE"; - attribute CAPACITANCE of \pins[1].ibuf_inst\ : label is "DONT_CARE"; - attribute IBUF_DELAY_VALUE of \pins[1].ibuf_inst\ : label is "0"; - attribute IFD_DELAY_VALUE of \pins[1].ibuf_inst\ : label is "AUTO"; -begin -\pins[0].fdre_in_inst\: unisim.vcomponents.FDRE - generic map( - INIT => '0', - IS_C_INVERTED => '0', - IS_D_INVERTED => '0', - IS_R_INVERTED => '0' - ) - port map ( - C => clk_in, - CE => '1', - D => data_in_from_pins_int(0), - Q => data_in_to_device(0), - R => io_reset - ); -\pins[0].ibuf_inst\: unisim.vcomponents.IBUF - port map ( - I => data_in_from_pins(0), - O => data_in_from_pins_int(0) - ); -\pins[1].fdre_in_inst\: unisim.vcomponents.FDRE - generic map( - INIT => '0', - IS_C_INVERTED => '0', - IS_D_INVERTED => '0', - IS_R_INVERTED => '0' - ) - port map ( - C => clk_in, - CE => '1', - D => data_in_from_pins_int(1), - Q => data_in_to_device(1), - R => io_reset - ); -\pins[1].ibuf_inst\: unisim.vcomponents.IBUF - port map ( - I => data_in_from_pins(1), - O => data_in_from_pins_int(1) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity selectio_lvds_rx is - port ( - data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 ); - data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 ); - clk_in : in STD_LOGIC; - io_reset : in STD_LOGIC - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of selectio_lvds_rx : entity is true; - attribute DEV_W : integer; - attribute DEV_W of selectio_lvds_rx : entity is 2; - attribute SYS_W : integer; - attribute SYS_W of selectio_lvds_rx : entity is 2; -end selectio_lvds_rx; - -architecture STRUCTURE of selectio_lvds_rx is - attribute DEV_W of inst : label is 2; - attribute SYS_W of inst : label is 2; -begin -inst: entity work.selectio_lvds_rx_selectio_lvds_rx_selectio_wiz - port map ( - clk_in => clk_in, - data_in_from_pins(1 downto 0) => data_in_from_pins(1 downto 0), - data_in_to_device(1 downto 0) => data_in_to_device(1 downto 0), - io_reset => io_reset - ); -end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_stub.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_stub.v deleted file mode 100644 index eadd56c4..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_stub.v +++ /dev/null @@ -1,23 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sun Mar 19 18:25:55 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -// D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.v -// Design : selectio_lvds_rx -// Purpose : Stub declaration of top-level module interface -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -module selectio_lvds_rx(data_in_from_pins, data_in_to_device, clk_in, - io_reset) -/* synthesis syn_black_box black_box_pad_pin="data_in_from_pins[1:0],data_in_to_device[1:0],clk_in,io_reset" */; - input [1:0]data_in_from_pins; - output [1:0]data_in_to_device; - input clk_in; - input io_reset; -endmodule diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_stub.vhdl b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_stub.vhdl deleted file mode 100644 index 681e6822..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_stub.vhdl +++ /dev/null @@ -1,31 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sun Mar 19 18:25:55 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub --- D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.vhdl --- Design : selectio_lvds_rx --- Purpose : Stub declaration of top-level module interface --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity selectio_lvds_rx is - Port ( - data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 ); - data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 ); - clk_in : in STD_LOGIC; - io_reset : in STD_LOGIC - ); - -end selectio_lvds_rx; - -architecture stub of selectio_lvds_rx is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "data_in_from_pins[1:0],data_in_to_device[1:0],clk_in,io_reset"; -begin -end; diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx.v deleted file mode 100644 index e58d2865..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx.v +++ /dev/null @@ -1,87 +0,0 @@ - -// file: selectio_lvds_tx.v -// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//---------------------------------------------------------------------------- -// User entered comments -//---------------------------------------------------------------------------- -// None -//---------------------------------------------------------------------------- - -`timescale 1ps/1ps - -(* CORE_GENERATION_INFO = "selectio_lvds_tx,selectio_wiz_v5_1_13,{component_name=selectio_lvds_tx,bus_dir=OUTPUTS,bus_sig_type=SINGLE,bus_io_std=LVCMOS33,use_serialization=false,use_phase_detector=false,serialization_factor=4,enable_bitslip=false,enable_train=false,system_data_width=4,bus_in_delay=NONE,bus_out_delay=NONE,clk_sig_type=SINGLE,clk_io_std=LVCMOS18,clk_buf=BUFIO2,active_edge=RISING,clk_delay=NONE,selio_bus_in_delay=NONE,selio_bus_out_delay=NONE,selio_clk_buf=BUFIO,selio_active_edge=SDR,selio_ddr_alignment=SAME_EDGE_PIPELINED,selio_oddr_alignment=SAME_EDGE,ddr_alignment=C0,selio_interface_type=NETWORKING,interface_type=NETWORKING,selio_bus_in_tap=0,selio_bus_out_tap=0,selio_clk_io_std=LVCMOS33,selio_clk_sig_type=SINGLE}" *) - -module selectio_lvds_tx - // width of the data for the system - #(parameter SYS_W = 4, - // width of the data for the device - parameter DEV_W = 4) - ( - // From the device out to the system - input [DEV_W-1:0] data_out_from_device, - output [SYS_W-1:0] data_out_to_pins, - input clk_in, // Single ended clock from IOB - output clk_out, - input io_reset); - - - selectio_lvds_tx_selectio_wiz - #( - .SYS_W(SYS_W), - .DEV_W(DEV_W) - ) - inst - ( - .data_out_from_device(data_out_from_device), - .data_out_to_pins(data_out_to_pins), - .clk_in(clk_in), - .clk_out(clk_out), - .io_reset(io_reset) -); - -endmodule - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx.veo b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx.veo deleted file mode 100644 index 4ede0b3d..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx.veo +++ /dev/null @@ -1,68 +0,0 @@ - -// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. - - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -// User NOTES: -//None - - selectio_lvds_tx - instance_name - ( - .data_out_from_device(data_out_from_device), // input [3:0] data_out_from_device - .data_out_to_pins(data_out_to_pins), // output [3:0] data_out_to_pins - .clk_in(clk_in), // input clk_in - .clk_out(clk_out), // output clk_out - .io_reset(io_reset) // input io_reset -); - -// INST_TAG_END ------ End INSTANTIATION Template --------- - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v deleted file mode 100644 index 2fe8e3e5..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v +++ /dev/null @@ -1,130 +0,0 @@ - -// file: selectio_lvds_tx_selectio_wiz.v -// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//---------------------------------------------------------------------------- -// User entered comments -//---------------------------------------------------------------------------- -// None -//---------------------------------------------------------------------------- - -`timescale 1ps/1ps - -module selectio_lvds_tx_selectio_wiz - // width of the data for the system - #(parameter SYS_W = 4, - // width of the data for the device - parameter DEV_W = 4) - ( - // From the device out to the system - input [DEV_W-1:0] data_out_from_device, - output [SYS_W-1:0] data_out_to_pins, - input clk_in, // Single ended clock from IOB - output clk_out, - input io_reset); - wire clock_enable = 1'b1; - // Signal declarations - ////------------------------------ - // Before the buffer - wire [SYS_W-1:0] data_out_to_pins_int; - // Between the delay and serdes - wire [SYS_W-1:0] data_out_to_pins_predelay; - // Create the clock logic - - - IBUF - #(.IOSTANDARD ("LVCMOS33")) - ibuf_clk_inst - (.I (clk_in), - .O (clk_in_int)); - - // BUFR generates the slow clock - BUFR - #(.SIM_DEVICE("7SERIES"), - .BUFR_DIVIDE("BYPASS")) - clkout_buf_inst - (.O (clk_div), - .CE(1'b1), - .CLR(1'b0), - .I (clk_in_int)); - - assign clk_out = clk_div; // This is regional clock; - // We have multiple bits- step over every bit, instantiating the required elements - genvar pin_count; - generate for (pin_count = 0; pin_count < SYS_W; pin_count = pin_count + 1) begin: pins - // Instantiate the buffers - ////------------------------------ - // Instantiate a buffer for every bit of the data bus - OBUF - #(.IOSTANDARD ("LVCMOS33")) - obuf_inst - (.O (data_out_to_pins [pin_count]), - .I (data_out_to_pins_int[pin_count])); - - // Pass through the delay - ////------------------------------- - assign data_out_to_pins_int[pin_count] = data_out_to_pins_predelay[pin_count]; - - // Connect the delayed data to the fabric - ////-------------------------------------- - - // Pack the registers into the IOB - wire data_out_from_device_q; - (* IOB = "true" *) - FDRE fdre_out_inst - (.D (data_out_from_device[pin_count]), - .C (clk_div), - .CE (clock_enable), - .R (io_reset), - .Q (data_out_from_device_q) - ); - assign data_out_to_pins_predelay[pin_count] = data_out_from_device_q; - end - endgenerate - -//// NO ODELAY - -endmodule diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_sim_netlist.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_sim_netlist.v deleted file mode 100644 index 9cf47661..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_sim_netlist.v +++ /dev/null @@ -1,227 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sun Mar 19 17:32:20 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -// D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v -// Design : selectio_lvds_tx -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* DEV_W = "4" *) (* SYS_W = "4" *) -(* NotValidForBitStream *) -module selectio_lvds_tx - (data_out_from_device, - data_out_to_pins, - clk_in, - clk_out, - io_reset); - input [3:0]data_out_from_device; - output [3:0]data_out_to_pins; - input clk_in; - output clk_out; - input io_reset; - - (* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire clk_in; - wire clk_out; - wire [3:0]data_out_from_device; - (* DRIVE = "12" *) (* IOSTANDARD = "LVCMOS33" *) (* SLEW = "SLOW" *) wire [3:0]data_out_to_pins; - wire io_reset; - - (* DEV_W = "4" *) - (* SYS_W = "4" *) - selectio_lvds_tx_selectio_lvds_tx_selectio_wiz inst - (.clk_in(clk_in), - .clk_out(clk_out), - .data_out_from_device(data_out_from_device), - .data_out_to_pins(data_out_to_pins), - .io_reset(io_reset)); -endmodule - -(* DEV_W = "4" *) (* ORIG_REF_NAME = "selectio_lvds_tx_selectio_wiz" *) (* SYS_W = "4" *) -module selectio_lvds_tx_selectio_lvds_tx_selectio_wiz - (data_out_from_device, - data_out_to_pins, - clk_in, - clk_out, - io_reset); - input [3:0]data_out_from_device; - output [3:0]data_out_to_pins; - input clk_in; - output clk_out; - input io_reset; - - wire clk_in; - wire clk_in_int; - wire clk_out; - wire [3:0]data_out_from_device; - wire [3:0]data_out_to_pins; - wire io_reset; - wire \pins[0].data_out_from_device_q ; - wire \pins[1].data_out_from_device_q ; - wire \pins[2].data_out_from_device_q ; - wire \pins[3].data_out_from_device_q ; - - (* BOX_TYPE = "PRIMITIVE" *) - BUFR #( - .BUFR_DIVIDE("BYPASS"), - .SIM_DEVICE("7SERIES")) - clkout_buf_inst - (.CE(1'b1), - .CLR(1'b0), - .I(clk_in_int), - .O(clk_out)); - (* BOX_TYPE = "PRIMITIVE" *) - (* CAPACITANCE = "DONT_CARE" *) - (* IBUF_DELAY_VALUE = "0" *) - (* IFD_DELAY_VALUE = "AUTO" *) - IBUF ibuf_clk_inst - (.I(clk_in), - .O(clk_in_int)); - (* BOX_TYPE = "PRIMITIVE" *) - (* IOB = "TRUE" *) - FDRE #( - .INIT(1'b0), - .IS_C_INVERTED(1'b0), - .IS_D_INVERTED(1'b0), - .IS_R_INVERTED(1'b0)) - \pins[0].fdre_out_inst - (.C(clk_out), - .CE(1'b1), - .D(data_out_from_device[0]), - .Q(\pins[0].data_out_from_device_q ), - .R(io_reset)); - (* BOX_TYPE = "PRIMITIVE" *) - (* CAPACITANCE = "DONT_CARE" *) - OBUF \pins[0].obuf_inst - (.I(\pins[0].data_out_from_device_q ), - .O(data_out_to_pins[0])); - (* BOX_TYPE = "PRIMITIVE" *) - (* IOB = "TRUE" *) - FDRE #( - .INIT(1'b0), - .IS_C_INVERTED(1'b0), - .IS_D_INVERTED(1'b0), - .IS_R_INVERTED(1'b0)) - \pins[1].fdre_out_inst - (.C(clk_out), - .CE(1'b1), - .D(data_out_from_device[1]), - .Q(\pins[1].data_out_from_device_q ), - .R(io_reset)); - (* BOX_TYPE = "PRIMITIVE" *) - (* CAPACITANCE = "DONT_CARE" *) - OBUF \pins[1].obuf_inst - (.I(\pins[1].data_out_from_device_q ), - .O(data_out_to_pins[1])); - (* BOX_TYPE = "PRIMITIVE" *) - (* IOB = "TRUE" *) - FDRE #( - .INIT(1'b0), - .IS_C_INVERTED(1'b0), - .IS_D_INVERTED(1'b0), - .IS_R_INVERTED(1'b0)) - \pins[2].fdre_out_inst - (.C(clk_out), - .CE(1'b1), - .D(data_out_from_device[2]), - .Q(\pins[2].data_out_from_device_q ), - .R(io_reset)); - (* BOX_TYPE = "PRIMITIVE" *) - (* CAPACITANCE = "DONT_CARE" *) - OBUF \pins[2].obuf_inst - (.I(\pins[2].data_out_from_device_q ), - .O(data_out_to_pins[2])); - (* BOX_TYPE = "PRIMITIVE" *) - (* IOB = "TRUE" *) - FDRE #( - .INIT(1'b0), - .IS_C_INVERTED(1'b0), - .IS_D_INVERTED(1'b0), - .IS_R_INVERTED(1'b0)) - \pins[3].fdre_out_inst - (.C(clk_out), - .CE(1'b1), - .D(data_out_from_device[3]), - .Q(\pins[3].data_out_from_device_q ), - .R(io_reset)); - (* BOX_TYPE = "PRIMITIVE" *) - (* CAPACITANCE = "DONT_CARE" *) - OBUF \pins[3].obuf_inst - (.I(\pins[3].data_out_from_device_q ), - .O(data_out_to_pins[3])); -endmodule -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_sim_netlist.vhdl b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_sim_netlist.vhdl deleted file mode 100644 index 196d3869..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_sim_netlist.vhdl +++ /dev/null @@ -1,193 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sun Mar 19 17:32:20 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim --- D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl --- Design : selectio_lvds_tx --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity selectio_lvds_tx_selectio_lvds_tx_selectio_wiz is - port ( - data_out_from_device : in STD_LOGIC_VECTOR ( 3 downto 0 ); - data_out_to_pins : out STD_LOGIC_VECTOR ( 3 downto 0 ); - clk_in : in STD_LOGIC; - clk_out : out STD_LOGIC; - io_reset : in STD_LOGIC - ); - attribute DEV_W : integer; - attribute DEV_W of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz : entity is 4; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz : entity is "selectio_lvds_tx_selectio_wiz"; - attribute SYS_W : integer; - attribute SYS_W of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz : entity is 4; -end selectio_lvds_tx_selectio_lvds_tx_selectio_wiz; - -architecture STRUCTURE of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz is - signal clk_in_int : STD_LOGIC; - signal \^clk_out\ : STD_LOGIC; - signal \pins[0].data_out_from_device_q\ : STD_LOGIC; - signal \pins[1].data_out_from_device_q\ : STD_LOGIC; - signal \pins[2].data_out_from_device_q\ : STD_LOGIC; - signal \pins[3].data_out_from_device_q\ : STD_LOGIC; - attribute BOX_TYPE : string; - attribute BOX_TYPE of clkout_buf_inst : label is "PRIMITIVE"; - attribute BOX_TYPE of ibuf_clk_inst : label is "PRIMITIVE"; - attribute CAPACITANCE : string; - attribute CAPACITANCE of ibuf_clk_inst : label is "DONT_CARE"; - attribute IBUF_DELAY_VALUE : string; - attribute IBUF_DELAY_VALUE of ibuf_clk_inst : label is "0"; - attribute IFD_DELAY_VALUE : string; - attribute IFD_DELAY_VALUE of ibuf_clk_inst : label is "AUTO"; - attribute BOX_TYPE of \pins[0].fdre_out_inst\ : label is "PRIMITIVE"; - attribute IOB : string; - attribute IOB of \pins[0].fdre_out_inst\ : label is "TRUE"; - attribute BOX_TYPE of \pins[0].obuf_inst\ : label is "PRIMITIVE"; - attribute CAPACITANCE of \pins[0].obuf_inst\ : label is "DONT_CARE"; - attribute BOX_TYPE of \pins[1].fdre_out_inst\ : label is "PRIMITIVE"; - attribute IOB of \pins[1].fdre_out_inst\ : label is "TRUE"; - attribute BOX_TYPE of \pins[1].obuf_inst\ : label is "PRIMITIVE"; - attribute CAPACITANCE of \pins[1].obuf_inst\ : label is "DONT_CARE"; - attribute BOX_TYPE of \pins[2].fdre_out_inst\ : label is "PRIMITIVE"; - attribute IOB of \pins[2].fdre_out_inst\ : label is "TRUE"; - attribute BOX_TYPE of \pins[2].obuf_inst\ : label is "PRIMITIVE"; - attribute CAPACITANCE of \pins[2].obuf_inst\ : label is "DONT_CARE"; - attribute BOX_TYPE of \pins[3].fdre_out_inst\ : label is "PRIMITIVE"; - attribute IOB of \pins[3].fdre_out_inst\ : label is "TRUE"; - attribute BOX_TYPE of \pins[3].obuf_inst\ : label is "PRIMITIVE"; - attribute CAPACITANCE of \pins[3].obuf_inst\ : label is "DONT_CARE"; -begin - clk_out <= \^clk_out\; -clkout_buf_inst: unisim.vcomponents.BUFR - generic map( - BUFR_DIVIDE => "BYPASS", - SIM_DEVICE => "7SERIES" - ) - port map ( - CE => '1', - CLR => '0', - I => clk_in_int, - O => \^clk_out\ - ); -ibuf_clk_inst: unisim.vcomponents.IBUF - port map ( - I => clk_in, - O => clk_in_int - ); -\pins[0].fdre_out_inst\: unisim.vcomponents.FDRE - generic map( - INIT => '0', - IS_C_INVERTED => '0', - IS_D_INVERTED => '0', - IS_R_INVERTED => '0' - ) - port map ( - C => \^clk_out\, - CE => '1', - D => data_out_from_device(0), - Q => \pins[0].data_out_from_device_q\, - R => io_reset - ); -\pins[0].obuf_inst\: unisim.vcomponents.OBUF - port map ( - I => \pins[0].data_out_from_device_q\, - O => data_out_to_pins(0) - ); -\pins[1].fdre_out_inst\: unisim.vcomponents.FDRE - generic map( - INIT => '0', - IS_C_INVERTED => '0', - IS_D_INVERTED => '0', - IS_R_INVERTED => '0' - ) - port map ( - C => \^clk_out\, - CE => '1', - D => data_out_from_device(1), - Q => \pins[1].data_out_from_device_q\, - R => io_reset - ); -\pins[1].obuf_inst\: unisim.vcomponents.OBUF - port map ( - I => \pins[1].data_out_from_device_q\, - O => data_out_to_pins(1) - ); -\pins[2].fdre_out_inst\: unisim.vcomponents.FDRE - generic map( - INIT => '0', - IS_C_INVERTED => '0', - IS_D_INVERTED => '0', - IS_R_INVERTED => '0' - ) - port map ( - C => \^clk_out\, - CE => '1', - D => data_out_from_device(2), - Q => \pins[2].data_out_from_device_q\, - R => io_reset - ); -\pins[2].obuf_inst\: unisim.vcomponents.OBUF - port map ( - I => \pins[2].data_out_from_device_q\, - O => data_out_to_pins(2) - ); -\pins[3].fdre_out_inst\: unisim.vcomponents.FDRE - generic map( - INIT => '0', - IS_C_INVERTED => '0', - IS_D_INVERTED => '0', - IS_R_INVERTED => '0' - ) - port map ( - C => \^clk_out\, - CE => '1', - D => data_out_from_device(3), - Q => \pins[3].data_out_from_device_q\, - R => io_reset - ); -\pins[3].obuf_inst\: unisim.vcomponents.OBUF - port map ( - I => \pins[3].data_out_from_device_q\, - O => data_out_to_pins(3) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity selectio_lvds_tx is - port ( - data_out_from_device : in STD_LOGIC_VECTOR ( 3 downto 0 ); - data_out_to_pins : out STD_LOGIC_VECTOR ( 3 downto 0 ); - clk_in : in STD_LOGIC; - clk_out : out STD_LOGIC; - io_reset : in STD_LOGIC - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of selectio_lvds_tx : entity is true; - attribute DEV_W : integer; - attribute DEV_W of selectio_lvds_tx : entity is 4; - attribute SYS_W : integer; - attribute SYS_W of selectio_lvds_tx : entity is 4; -end selectio_lvds_tx; - -architecture STRUCTURE of selectio_lvds_tx is - attribute DEV_W of inst : label is 4; - attribute SYS_W of inst : label is 4; -begin -inst: entity work.selectio_lvds_tx_selectio_lvds_tx_selectio_wiz - port map ( - clk_in => clk_in, - clk_out => clk_out, - data_out_from_device(3 downto 0) => data_out_from_device(3 downto 0), - data_out_to_pins(3 downto 0) => data_out_to_pins(3 downto 0), - io_reset => io_reset - ); -end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_stub.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_stub.v deleted file mode 100644 index b520abfc..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_stub.v +++ /dev/null @@ -1,24 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sun Mar 19 17:32:20 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -// D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v -// Design : selectio_lvds_tx -// Purpose : Stub declaration of top-level module interface -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -module selectio_lvds_tx(data_out_from_device, data_out_to_pins, - clk_in, clk_out, io_reset) -/* synthesis syn_black_box black_box_pad_pin="data_out_from_device[3:0],data_out_to_pins[3:0],clk_in,clk_out,io_reset" */; - input [3:0]data_out_from_device; - output [3:0]data_out_to_pins; - input clk_in; - output clk_out; - input io_reset; -endmodule diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_stub.vhdl b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_stub.vhdl deleted file mode 100644 index 9591245e..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_stub.vhdl +++ /dev/null @@ -1,32 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sun Mar 19 17:32:20 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub --- D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl --- Design : selectio_lvds_tx --- Purpose : Stub declaration of top-level module interface --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity selectio_lvds_tx is - Port ( - data_out_from_device : in STD_LOGIC_VECTOR ( 3 downto 0 ); - data_out_to_pins : out STD_LOGIC_VECTOR ( 3 downto 0 ); - clk_in : in STD_LOGIC; - clk_out : out STD_LOGIC; - io_reset : in STD_LOGIC - ); - -end selectio_lvds_tx; - -architecture stub of selectio_lvds_tx is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "data_out_from_device[3:0],data_out_to_pins[3:0],clk_in,clk_out,io_reset"; -begin -end; diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/README.txt deleted file mode 100644 index f3d66c82..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/README.txt +++ /dev/null @@ -1,83 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required -# to simulate the design for a simulator, the directory structure -# and the generated exported files. -# -################################################################################ - -1. Simulate Design - -To simulate design, cd to the simulator directory and execute the script. - -For example:- - -% cd questa -% ./top.sh - -The export simulation flow requires the Xilinx pre-compiled simulation library -components for the target simulator. These components are referred using the -'-lib_map_path' switch. If this switch is specified, then the export simulation -will automatically set this library path in the generated script and update, -copy the simulator setup file(s) in the exported directory. - -If '-lib_map_path' is not specified, then the pre-compiled simulation library -information will not be included in the exported scripts and that may cause -simulation errors when running this script. Alternatively, you can provide the -library information using this switch while executing the generated script. - -For example:- - -% ./top.sh -lib_map_path /design/questa/clibs - -Please refer to the generated script header 'Prerequisite' section for more details. - -2. Directory Structure - -By default, if the -directory switch is not specified, export_simulation will -create the following directory structure:- - -/export_sim/ - -For example, if the current working directory is /tmp/test, export_simulation -will create the following directory path:- - -/tmp/test/export_sim/questa - -If -directory switch is specified, export_simulation will create a simulator -sub-directory under the specified directory path. - -For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' -command will create the following directory:- - -/tmp/test/my_test_area/func_sim/questa - -By default, if -simulator is not specified, export_simulation will create a -simulator sub-directory for each simulator and export the files for each simulator -in this sub-directory respectively. - -IMPORTANT: Please note that the simulation library path must be specified manually -in the generated script for the respective simulator. Please refer to the generated -script header 'Prerequisite' section for more details. - -3. Exported script and files - -Export simulation will create the driver shell script, setup files and copy the -design sources in the output directory path. - -By default, when the -script_name switch is not specified, export_simulation will -create the following script name:- - -.sh (Unix) -When exporting the files for an IP using the -of_objects switch, export_simulation -will create the following script name:- - -.sh (Unix) -Export simulation will create the setup files for the target simulator specified -with the -simulator switch. - -For example, if the target simulator is "ies", export_simulation will create the -'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' -file. - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/README.txt deleted file mode 100644 index 8965a407..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun Mar 19 18:25:33 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./selectio_lvds_rx.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './selectio_lvds_rx.sh' script. - -./selectio_lvds_rx.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./selectio_lvds_rx.sh -noclean_files - -For more information on the script, please type './selectio_lvds_rx.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/compile.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/compile.do deleted file mode 100644 index 322d8d25..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/compile.do +++ /dev/null @@ -1,23 +0,0 @@ -vlib work -vlib activehdl - -vlib activehdl/xil_defaultlib -vlib activehdl/xpm - -vmap xil_defaultlib activehdl/xil_defaultlib -vmap xpm activehdl/xpm - -vlog -work xil_defaultlib -sv2k12 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -93 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work xil_defaultlib -v2k5 \ -"../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v" \ -"../../../ip/selectio_lvds_rx/selectio_lvds_rx.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/file_info.txt deleted file mode 100644 index 6d7cb2d8..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -selectio_lvds_rx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v, -selectio_lvds_rx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/selectio_lvds_rx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/selectio_lvds_rx.sh deleted file mode 100644 index 4aaefff4..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/selectio_lvds_rx.sh +++ /dev/null @@ -1,153 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : selectio_lvds_rx.sh -# Simulator : Aldec Active-HDL Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sun Mar 19 18:25:33 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: selectio_lvds_rx.sh [-help] -# usage: selectio_lvds_rx.sh [-lib_map_path] -# usage: selectio_lvds_rx.sh [-noclean_files] -# usage: selectio_lvds_rx.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'selectio_lvds_rx.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "selectio_lvds_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - runvsimsa -l simulate.log -do "do {simulate.do}" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_rx.sh -help\" for more information)\n" - exit 1 - fi - map_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - map_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Map library.cfg file -map_setup_file() -{ - file="library.cfg" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - else - lib_map_path="D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/activehdl" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - vmap -link $lib_map_path - fi - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_rx.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: selectio_lvds_rx.sh [-help]\n\ -Usage: selectio_lvds_rx.sh [-lib_map_path]\n\ -Usage: selectio_lvds_rx.sh [-reset_run]\n\ -Usage: selectio_lvds_rx.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/selectio_lvds_rx.udo b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/selectio_lvds_rx.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/simulate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/simulate.do deleted file mode 100644 index 1232b429..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/simulate.do +++ /dev/null @@ -1,17 +0,0 @@ -onbreak {quit -force} -onerror {quit -force} - -asim -t 1ps +access +r +m+selectio_lvds_rx -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.selectio_lvds_rx xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure - -do {selectio_lvds_rx.udo} - -run -all - -endsim - -quit -force diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/wave.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/README.txt deleted file mode 100644 index c7a8bbf2..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/README.txt +++ /dev/null @@ -1,48 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun Mar 19 18:25:33 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./selectio_lvds_rx.sh - -This command will launch the 'execute' function for the single-step flow. This -function is called from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './selectio_lvds_rx.sh' script. - -./selectio_lvds_rx.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./selectio_lvds_rx.sh -noclean_files - -For more information on the script, please type './selectio_lvds_rx.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/file_info.txt deleted file mode 100644 index 6d7cb2d8..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -selectio_lvds_rx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v, -selectio_lvds_rx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/run.f b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/run.f deleted file mode 100644 index 44edac75..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/run.f +++ /dev/null @@ -1,15 +0,0 @@ --makelib ies_lib/xil_defaultlib -sv \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ --endlib --makelib ies_lib/xpm \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ --endlib --makelib ies_lib/xil_defaultlib \ - "../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v" \ - "../../../ip/selectio_lvds_rx/selectio_lvds_rx.v" \ --endlib --makelib ies_lib/xil_defaultlib \ - glbl.v --endlib - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/selectio_lvds_rx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/selectio_lvds_rx.sh deleted file mode 100644 index 38cec837..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/selectio_lvds_rx.sh +++ /dev/null @@ -1,175 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : selectio_lvds_rx.sh -# Simulator : Cadence Incisive Enterprise Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sun Mar 19 18:25:33 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: selectio_lvds_rx.sh [-help] -# usage: selectio_lvds_rx.sh [-lib_map_path] -# usage: selectio_lvds_rx.sh [-noclean_files] -# usage: selectio_lvds_rx.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'selectio_lvds_rx.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Set the compiled library directory -ref_lib_dir="." - -# Command line options -irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" - -# Design libraries -design_libs=(xil_defaultlib xpm) - -# Simulation root library directory -sim_lib_dir="ies_lib" - -# Script info -echo -e "selectio_lvds_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - execute -} - -# RUN_STEP: -execute() -{ - irun $irun_opts \ - -reflib "$ref_lib_dir/unisim:unisim" \ - -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ - -reflib "$ref_lib_dir/secureip:secureip" \ - -reflib "$ref_lib_dir/unimacro:unimacro" \ - -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.selectio_lvds_rx \ - -f run.f \ - -top glbl \ - glbl.v -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_rx.sh -help\" for more information)\n" - exit 1 - else - ref_lib_dir=$2 - fi - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_rx.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: selectio_lvds_rx.sh [-help]\n\ -Usage: selectio_lvds_rx.sh [-lib_map_path]\n\ -Usage: selectio_lvds_rx.sh [-reset_run]\n\ -Usage: selectio_lvds_rx.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/README.txt deleted file mode 100644 index 8965a407..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun Mar 19 18:25:33 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./selectio_lvds_rx.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './selectio_lvds_rx.sh' script. - -./selectio_lvds_rx.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./selectio_lvds_rx.sh -noclean_files - -For more information on the script, please type './selectio_lvds_rx.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/compile.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/compile.do deleted file mode 100644 index 093e666c..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/compile.do +++ /dev/null @@ -1,15 +0,0 @@ -vlib modelsim_lib/work -vlib modelsim_lib/msim - -vlib modelsim_lib/msim/xil_defaultlib - -vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib - -vlog -work xil_defaultlib -64 -incr \ -"../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v" \ -"../../../ip/selectio_lvds_rx/selectio_lvds_rx.v" \ - - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/file_info.txt deleted file mode 100644 index 27843160..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/file_info.txt +++ /dev/null @@ -1,3 +0,0 @@ -selectio_lvds_rx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v, -selectio_lvds_rx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/modelsim.ini b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/modelsim.ini deleted file mode 100644 index 04a43f2c..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/modelsim.ini +++ /dev/null @@ -1,2590 +0,0 @@ -; vsim modelsim.ini file -[Version] -INIVersion = "2020.4" - -; Copyright 1991-2020 Mentor Graphics Corporation -; -; All Rights Reserved. -; -; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF -; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. -; - -[Library] -others = $MODEL_TECH/../modelsim.ini -; -; VITAL concerns: -; -; The library ieee contains (among other packages) the packages of the -; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use -; the physical library ieee (recommended), or use the physical library -; vital2000, but not both. The design can use logical library ieee and/or -; vital2000 as long as each of these maps to the same physical library, either -; ieee or vital2000. -; -; A design using the 1995 version of the VITAL packages, whether or not -; it also uses the 2000 version of the VITAL packages, must have logical library -; name ieee mapped to physical library vital1995. (A design cannot use library -; vital1995 directly because some packages in this library use logical name ieee -; when referring to the other packages in the library.) The design source -; should use logical name ieee when referring to any packages there except the -; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical -; name vital2000 (mapped to physical library vital2000) to refer to those -; packages. -; ieee = $MODEL_TECH/../vital1995 -; -; For compatiblity with previous releases, logical library name vital2000 maps -; to library vital2000 (a different library than library ieee, containing the -; same packages). -; A design should not reference VITAL from both the ieee library and the -; vital2000 library because the vital packages are effectively different. -; A design that references both the ieee and vital2000 libraries must have -; both logical names ieee and vital2000 mapped to the same library, either of -; these: -; $MODEL_TECH/../ieee -; $MODEL_TECH/../vital2000 -; - -; added mapping for ADMS - -;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release -;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release -;mvc_lib = $MODEL_TECH/../mvc_lib - -; Automatically perform logical->physical mapping for physical libraries that -; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). -; The tail of the filesystem path name is chosen as the logical library name. -; For example, in the command "vopt -L ./path/to/lib1 -o opttop top", -; vopt automatically performs the mapping "lib1 -> ./path/to/lib1". -; See the User Manual for more details. -; -; AutoLibMapping = 0 - -secureip = C:/Mentor/CompLib/2019.1.3/secureip -unisim = C:/Mentor/CompLib/2019.1.3/unisim -unimacro = C:/Mentor/CompLib/2019.1.3/unimacro -unifast = C:/Mentor/CompLib/2019.1.3/unifast -unisims_ver = C:/Mentor/CompLib/2019.1.3/unisims_ver -unimacro_ver = C:/Mentor/CompLib/2019.1.3/unimacro_ver -unifast_ver = C:/Mentor/CompLib/2019.1.3/unifast_ver -simprims_ver = C:/Mentor/CompLib/2019.1.3/simprims_ver -xpm = C:/Mentor/CompLib/2019.1.3/xpm -xilinx_vip = C:/Mentor/CompLib/2019.1.3/xilinx_vip -advanced_io_wizard_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/advanced_io_wizard_phy_v1_0_0 -advanced_io_wizard_v1_0_0 = C:/Mentor/CompLib/2019.1.3/advanced_io_wizard_v1_0_0 -ahblite_axi_bridge_v3_0_14 = C:/Mentor/CompLib/2019.1.3/ahblite_axi_bridge_v3_0_14 -ai_noc = C:/Mentor/CompLib/2019.1.3/ai_noc -ai_pl_trig = C:/Mentor/CompLib/2019.1.3/ai_pl_trig -ai_pl = C:/Mentor/CompLib/2019.1.3/ai_pl -audio_clock_recovery_v1_0 = C:/Mentor/CompLib/2019.1.3/audio_clock_recovery_v1_0 -audio_tpg_v1_0_0 = C:/Mentor/CompLib/2019.1.3/audio_tpg_v1_0_0 -av_pat_gen_v1_0_0 = C:/Mentor/CompLib/2019.1.3/av_pat_gen_v1_0_0 -axis_infrastructure_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axis_infrastructure_v1_1_0 -axis_protocol_checker_v2_0_3 = C:/Mentor/CompLib/2019.1.3/axis_protocol_checker_v2_0_3 -axi_ahblite_bridge_v3_0_16 = C:/Mentor/CompLib/2019.1.3/axi_ahblite_bridge_v3_0_16 -axi_amm_bridge_v1_0_9 = C:/Mentor/CompLib/2019.1.3/axi_amm_bridge_v1_0_9 -axi_bram_ctrl_v4_1_1 = C:/Mentor/CompLib/2019.1.3/axi_bram_ctrl_v4_1_1 -axi_chip2chip_v5_0_6 = C:/Mentor/CompLib/2019.1.3/axi_chip2chip_v5_0_6 -axi_dbg_hub = C:/Mentor/CompLib/2019.1.3/axi_dbg_hub -axi_infrastructure_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axi_infrastructure_v1_1_0 -axi_jtag_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_jtag_v1_0_0 -axi_lite_ipif_v3_0_4 = C:/Mentor/CompLib/2019.1.3/axi_lite_ipif_v3_0_4 -axi_pcie3_v3_0_9 = C:/Mentor/CompLib/2019.1.3/axi_pcie3_v3_0_9 -axi_perf_mon_v5_0_21 = C:/Mentor/CompLib/2019.1.3/axi_perf_mon_v5_0_21 -axi_pmon_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_pmon_v1_0_0 -blk_mem_gen_v8_3_6 = C:/Mentor/CompLib/2019.1.3/blk_mem_gen_v8_3_6 -blk_mem_gen_v8_4_3 = C:/Mentor/CompLib/2019.1.3/blk_mem_gen_v8_4_3 -bsip_v1_1_0 = C:/Mentor/CompLib/2019.1.3/bsip_v1_1_0 -bs_mux_v1_0_0 = C:/Mentor/CompLib/2019.1.3/bs_mux_v1_0_0 -clk_gen_sim_v1_0_0 = C:/Mentor/CompLib/2019.1.3/clk_gen_sim_v1_0_0 -clk_vip_v1_0_2 = C:/Mentor/CompLib/2019.1.3/clk_vip_v1_0_2 -cmac_usplus_v2_4_5 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_4_5 -cmac_usplus_v2_5_3 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_5_3 -cmac_usplus_v2_6_2 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_6_2 -cmac_v2_3_5 = C:/Mentor/CompLib/2019.1.3/cmac_v2_3_5 -cmac_v2_4_1 = C:/Mentor/CompLib/2019.1.3/cmac_v2_4_1 -cmac_v2_5_1 = C:/Mentor/CompLib/2019.1.3/cmac_v2_5_1 -compact_gt_v1_0_5 = C:/Mentor/CompLib/2019.1.3/compact_gt_v1_0_5 -ddr4_pl_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/ddr4_pl_phy_v1_0_0 -ddr4_pl_v1_0_2 = C:/Mentor/CompLib/2019.1.3/ddr4_pl_v1_0_2 -dist_mem_gen_v8_0_13 = C:/Mentor/CompLib/2019.1.3/dist_mem_gen_v8_0_13 -ecc_v2_0_13 = C:/Mentor/CompLib/2019.1.3/ecc_v2_0_13 -emb_fifo_gen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/emb_fifo_gen_v1_0_1 -emb_mem_gen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/emb_mem_gen_v1_0_1 -emc_common_v3_0_5 = C:/Mentor/CompLib/2019.1.3/emc_common_v3_0_5 -ethernet_1_10_25g_v2_0_5 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_0_5 -ethernet_1_10_25g_v2_1_4 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_1_4 -ethernet_1_10_25g_v2_2_3 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_2_3 -ethernet_1_10_25g_v2_3_3 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_3_3 -fifo_generator_v13_0_6 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_0_6 -fifo_generator_v13_1_4 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_1_4 -fifo_generator_v13_2_4 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_2_4 -fit_timer_v2_0_10 = C:/Mentor/CompLib/2019.1.3/fit_timer_v2_0_10 -generic_baseblocks_v2_1_0 = C:/Mentor/CompLib/2019.1.3/generic_baseblocks_v2_1_0 -gigantic_mux = C:/Mentor/CompLib/2019.1.3/gigantic_mux -gig_ethernet_pcs_pma_v16_1_6 = C:/Mentor/CompLib/2019.1.3/gig_ethernet_pcs_pma_v16_1_6 -gmii_to_rgmii_v4_0_7 = C:/Mentor/CompLib/2019.1.3/gmii_to_rgmii_v4_0_7 -gtwizard_ultrascale_v1_5_4 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_5_4 -gtwizard_ultrascale_v1_6_11 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_6_11 -gtwizard_ultrascale_v1_7_6 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_7_6 -hbm_v1_0_4 = C:/Mentor/CompLib/2019.1.3/hbm_v1_0_4 -hdcp22_cipher_dp_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdcp22_cipher_dp_v1_0_0 -hdcp22_cipher_v1_0_3 = C:/Mentor/CompLib/2019.1.3/hdcp22_cipher_v1_0_3 -hdcp22_rng_v1_0_1 = C:/Mentor/CompLib/2019.1.3/hdcp22_rng_v1_0_1 -hdcp_keymngmt_blk_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdcp_keymngmt_blk_v1_0_0 -hdcp_v1_0_3 = C:/Mentor/CompLib/2019.1.3/hdcp_v1_0_3 -hdmi_gt_controller_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdmi_gt_controller_v1_0_0 -high_speed_selectio_wiz_v3_2_3 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_2_3 -high_speed_selectio_wiz_v3_3_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_3_1 -high_speed_selectio_wiz_v3_4_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_4_1 -high_speed_selectio_wiz_v3_5_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_5_1 -i2s_receiver_v1_0_3 = C:/Mentor/CompLib/2019.1.3/i2s_receiver_v1_0_3 -i2s_transmitter_v1_0_3 = C:/Mentor/CompLib/2019.1.3/i2s_transmitter_v1_0_3 -ibert_lib_v1_0_6 = C:/Mentor/CompLib/2019.1.3/ibert_lib_v1_0_6 -ieee802d3_clause74_fec_v1_0_4 = C:/Mentor/CompLib/2019.1.3/ieee802d3_clause74_fec_v1_0_4 -interlaken_v2_4_3 = C:/Mentor/CompLib/2019.1.3/interlaken_v2_4_3 -in_system_ibert_v1_0_9 = C:/Mentor/CompLib/2019.1.3/in_system_ibert_v1_0_9 -iomodule_v3_1_4 = C:/Mentor/CompLib/2019.1.3/iomodule_v3_1_4 -jesd204c_v4_1_1 = C:/Mentor/CompLib/2019.1.3/jesd204c_v4_1_1 -jesd204_v7_2_6 = C:/Mentor/CompLib/2019.1.3/jesd204_v7_2_6 -jtag_axi = C:/Mentor/CompLib/2019.1.3/jtag_axi -lib_cdc_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_cdc_v1_0_2 -lib_pkg_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_pkg_v1_0_2 -lmb_bram_if_cntlr_v4_0_16 = C:/Mentor/CompLib/2019.1.3/lmb_bram_if_cntlr_v4_0_16 -lmb_v10_v3_0_9 = C:/Mentor/CompLib/2019.1.3/lmb_v10_v3_0_9 -ltlib_v1_0_0 = C:/Mentor/CompLib/2019.1.3/ltlib_v1_0_0 -lut_buffer_v1_0_0 = C:/Mentor/CompLib/2019.1.3/lut_buffer_v1_0_0 -lut_buffer_v2_0_0 = C:/Mentor/CompLib/2019.1.3/lut_buffer_v2_0_0 -l_ethernet_v2_3_5 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_3_5 -l_ethernet_v2_4_3 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_4_3 -l_ethernet_v2_5_2 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_5_2 -mammoth_transcode_v1_0_0 = C:/Mentor/CompLib/2019.1.3/mammoth_transcode_v1_0_0 -microblaze_v10_0_7 = C:/Mentor/CompLib/2019.1.3/microblaze_v10_0_7 -microblaze_v11_0_1 = C:/Mentor/CompLib/2019.1.3/microblaze_v11_0_1 -microblaze_v9_5_4 = C:/Mentor/CompLib/2019.1.3/microblaze_v9_5_4 -mii_to_rmii_v2_0_21 = C:/Mentor/CompLib/2019.1.3/mii_to_rmii_v2_0_21 -mipi_csi2_rx_ctrl_v1_0_8 = C:/Mentor/CompLib/2019.1.3/mipi_csi2_rx_ctrl_v1_0_8 -mipi_csi2_tx_ctrl_v1_0_4 = C:/Mentor/CompLib/2019.1.3/mipi_csi2_tx_ctrl_v1_0_4 -mipi_dphy_v4_1_4 = C:/Mentor/CompLib/2019.1.3/mipi_dphy_v4_1_4 -mipi_dsi_tx_ctrl_v1_0_7 = C:/Mentor/CompLib/2019.1.3/mipi_dsi_tx_ctrl_v1_0_7 -mrmac_v1_0_0 = C:/Mentor/CompLib/2019.1.3/mrmac_v1_0_0 -multi_channel_25g_rs_fec_v1_0_5 = C:/Mentor/CompLib/2019.1.3/multi_channel_25g_rs_fec_v1_0_5 -mutex_v2_1_10 = C:/Mentor/CompLib/2019.1.3/mutex_v2_1_10 -axi_tg_lib = C:/Mentor/CompLib/2019.1.3/axi_tg_lib -noc_na_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_na_v1_0_0 -noc_nidb_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nidb_v1_0_0 -noc_nmu_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nmu_v1_0_0 -noc_nps_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nps_v1_0_0 -nvmeha_v1_0_0 = C:/Mentor/CompLib/2019.1.3/nvmeha_v1_0_0 -oddr_v1_0_0 = C:/Mentor/CompLib/2019.1.3/oddr_v1_0_0 -pci32_v5_0_12 = C:/Mentor/CompLib/2019.1.3/pci32_v5_0_12 -pci64_v5_0_11 = C:/Mentor/CompLib/2019.1.3/pci64_v5_0_11 -pcie_jtag_v1_0_0 = C:/Mentor/CompLib/2019.1.3/pcie_jtag_v1_0_0 -pc_cfr_v6_0_8 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_0_8 -pc_cfr_v6_1_4 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_1_4 -pc_cfr_v6_2_2 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_2_2 -pc_cfr_v6_3_0 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_3_0 -picxo = C:/Mentor/CompLib/2019.1.3/picxo -qdma_v3_0_2 = C:/Mentor/CompLib/2019.1.3/qdma_v3_0_2 -rama_v1_1_2_lib = C:/Mentor/CompLib/2019.1.3/rama_v1_1_2_lib -rld3_pl_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/rld3_pl_phy_v1_0_0 -rld3_pl_v1_0_1 = C:/Mentor/CompLib/2019.1.3/rld3_pl_v1_0_1 -roe_framer_v2_0_1 = C:/Mentor/CompLib/2019.1.3/roe_framer_v2_0_1 -rst_vip_v1_0_3 = C:/Mentor/CompLib/2019.1.3/rst_vip_v1_0_3 -smartconnect_v1_0 = C:/Mentor/CompLib/2019.1.3/smartconnect_v1_0 -sd_fec_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sd_fec_v1_0_2 -sem_ultra_v3_1_11 = C:/Mentor/CompLib/2019.1.3/sem_ultra_v3_1_11 -sem_v4_1_12 = C:/Mentor/CompLib/2019.1.3/sem_v4_1_12 -shell_utils_msp432_bsl_crc_gen_v1_0_0 = C:/Mentor/CompLib/2019.1.3/shell_utils_msp432_bsl_crc_gen_v1_0_0 -sim_clk_gen_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sim_clk_gen_v1_0_2 -sim_rst_gen_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sim_rst_gen_v1_0_2 -sim_trig_top_v1_0 = C:/Mentor/CompLib/2019.1.3/sim_trig_top_v1_0 -stm_v1_0 = C:/Mentor/CompLib/2019.1.3/stm_v1_0 -stm_v1_0_0 = C:/Mentor/CompLib/2019.1.3/stm_v1_0_0 -system_cache_v4_0_6 = C:/Mentor/CompLib/2019.1.3/system_cache_v4_0_6 -ta_dma_v1_0_3 = C:/Mentor/CompLib/2019.1.3/ta_dma_v1_0_3 -tcc_decoder_3gpplte_v3_0_6 = C:/Mentor/CompLib/2019.1.3/tcc_decoder_3gpplte_v3_0_6 -ten_gig_eth_mac_v15_1_7 = C:/Mentor/CompLib/2019.1.3/ten_gig_eth_mac_v15_1_7 -ten_gig_eth_pcs_pma_v6_0_15 = C:/Mentor/CompLib/2019.1.3/ten_gig_eth_pcs_pma_v6_0_15 -timer_sync_1588_v1_2_4 = C:/Mentor/CompLib/2019.1.3/timer_sync_1588_v1_2_4 -tmr_inject_v1_0_3 = C:/Mentor/CompLib/2019.1.3/tmr_inject_v1_0_3 -tmr_manager_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tmr_manager_v1_0_4 -tmr_voter_v1_0_2 = C:/Mentor/CompLib/2019.1.3/tmr_voter_v1_0_2 -tsn_endpoint_ethernet_mac_block_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tsn_endpoint_ethernet_mac_block_v1_0_4 -uhdsdi_gt_v1_0_3 = C:/Mentor/CompLib/2019.1.3/uhdsdi_gt_v1_0_3 -uhdsdi_gt_v2_0_0 = C:/Mentor/CompLib/2019.1.3/uhdsdi_gt_v2_0_0 -usxgmii_v1_0_5 = C:/Mentor/CompLib/2019.1.3/usxgmii_v1_0_5 -usxgmii_v1_1_0 = C:/Mentor/CompLib/2019.1.3/usxgmii_v1_1_0 -util_idelay_ctrl_v1_0_1 = C:/Mentor/CompLib/2019.1.3/util_idelay_ctrl_v1_0_1 -util_reduced_logic_v2_0_4 = C:/Mentor/CompLib/2019.1.3/util_reduced_logic_v2_0_4 -util_vector_logic_v2_0_1 = C:/Mentor/CompLib/2019.1.3/util_vector_logic_v2_0_1 -ba317 = C:/Mentor/CompLib/2019.1.3/ba317 -vfb_v1_0_13 = C:/Mentor/CompLib/2019.1.3/vfb_v1_0_13 -video_frame_crc_v1_0_1 = C:/Mentor/CompLib/2019.1.3/video_frame_crc_v1_0_1 -vid_edid_v1_0_0 = C:/Mentor/CompLib/2019.1.3/vid_edid_v1_0_0 -vid_phy_controller_v2_1_5 = C:/Mentor/CompLib/2019.1.3/vid_phy_controller_v2_1_5 -vid_phy_controller_v2_2_3 = C:/Mentor/CompLib/2019.1.3/vid_phy_controller_v2_2_3 -v_axi4s_remap_v1_0_11 = C:/Mentor/CompLib/2019.1.3/v_axi4s_remap_v1_0_11 -v_csc_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_csc_v1_0_13 -v_deinterlacer_v4_0_12 = C:/Mentor/CompLib/2019.1.3/v_deinterlacer_v4_0_12 -v_deinterlacer_v5_0_13 = C:/Mentor/CompLib/2019.1.3/v_deinterlacer_v5_0_13 -v_demosaic_v1_0_5 = C:/Mentor/CompLib/2019.1.3/v_demosaic_v1_0_5 -v_frmbuf_rd_v2_1_2 = C:/Mentor/CompLib/2019.1.3/v_frmbuf_rd_v2_1_2 -v_frmbuf_wr_v2_1_2 = C:/Mentor/CompLib/2019.1.3/v_frmbuf_wr_v2_1_2 -v_gamma_lut_v1_0_5 = C:/Mentor/CompLib/2019.1.3/v_gamma_lut_v1_0_5 -v_hcresampler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_hcresampler_v1_0_13 -v_hdmi_rx_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_rx_v2_0_0 -v_hdmi_rx_v3_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_rx_v3_0_0 -v_hdmi_tx_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_tx_v2_0_0 -v_hdmi_tx_v3_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_tx_v3_0_0 -v_hscaler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_hscaler_v1_0_13 -v_letterbox_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_letterbox_v1_0_13 -v_mix_v3_0_3 = C:/Mentor/CompLib/2019.1.3/v_mix_v3_0_3 -v_mix_v4_0_0 = C:/Mentor/CompLib/2019.1.3/v_mix_v4_0_0 -v_multi_scaler_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_multi_scaler_v1_0_1 -v_scenechange_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_scenechange_v1_0_1 -v_sdi_rx_vid_bridge_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_sdi_rx_vid_bridge_v2_0_0 -v_smpte_sdi_v3_0_8 = C:/Mentor/CompLib/2019.1.3/v_smpte_sdi_v3_0_8 -v_smpte_uhdsdi_rx_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_rx_v1_0_0 -v_smpte_uhdsdi_tx_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_tx_v1_0_0 -v_smpte_uhdsdi_v1_0_7 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_v1_0_7 -v_tpg_v7_0_13 = C:/Mentor/CompLib/2019.1.3/v_tpg_v7_0_13 -v_tpg_v8_0_1 = C:/Mentor/CompLib/2019.1.3/v_tpg_v8_0_1 -v_uhdsdi_audio_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v1_0_0 -v_uhdsdi_audio_v1_1_0 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v1_1_0 -v_uhdsdi_audio_v2_0_1 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v2_0_1 -v_uhdsdi_vidgen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_vidgen_v1_0_1 -v_vcresampler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_vcresampler_v1_0_13 -v_vid_in_axi4s_v4_0_9 = C:/Mentor/CompLib/2019.1.3/v_vid_in_axi4s_v4_0_9 -v_vscaler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_vscaler_v1_0_13 -xaui_v12_3_6 = C:/Mentor/CompLib/2019.1.3/xaui_v12_3_6 -xbip_dsp48_wrapper_v3_0_4 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_wrapper_v3_0_4 -xbip_utils_v3_0_10 = C:/Mentor/CompLib/2019.1.3/xbip_utils_v3_0_10 -xdma_v4_1_3 = C:/Mentor/CompLib/2019.1.3/xdma_v4_1_3 -xhmc_v1_0_9 = C:/Mentor/CompLib/2019.1.3/xhmc_v1_0_9 -xlconcat_v2_1_3 = C:/Mentor/CompLib/2019.1.3/xlconcat_v2_1_3 -xlconstant_v1_1_6 = C:/Mentor/CompLib/2019.1.3/xlconstant_v1_1_6 -xlslice_v1_0_2 = C:/Mentor/CompLib/2019.1.3/xlslice_v1_0_2 -xsdbm_v2_0_0 = C:/Mentor/CompLib/2019.1.3/xsdbm_v2_0_0 -xsdbm_v3_0_0 = C:/Mentor/CompLib/2019.1.3/xsdbm_v3_0_0 -xxv_ethernet_v2_4_5 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v2_4_5 -xxv_ethernet_v2_5_3 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v2_5_3 -xxv_ethernet_v3_0_3 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v3_0_3 -zynq_ultra_ps_e_v3_2_3 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_v3_2_3 -zynq_ultra_ps_e_v3_3_0 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_v3_3_0 -lib_srl_fifo_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_srl_fifo_v1_0_2 -lib_fifo_v1_0_13 = C:/Mentor/CompLib/2019.1.3/lib_fifo_v1_0_13 -axi_datamover_v5_1_21 = C:/Mentor/CompLib/2019.1.3/axi_datamover_v5_1_21 -amm_axi_bridge_v1_0_5 = C:/Mentor/CompLib/2019.1.3/amm_axi_bridge_v1_0_5 -axis_interconnect_v1_1_17 = C:/Mentor/CompLib/2019.1.3/axis_interconnect_v1_1_17 -ats_switch_v1_0_2 = C:/Mentor/CompLib/2019.1.3/ats_switch_v1_0_2 -audio_formatter_v1_0_1 = C:/Mentor/CompLib/2019.1.3/audio_formatter_v1_0_1 -axi4stream_vip_v1_1_5 = C:/Mentor/CompLib/2019.1.3/axi4stream_vip_v1_1_5 -v_tc_v6_1_13 = C:/Mentor/CompLib/2019.1.3/v_tc_v6_1_13 -v_axi4s_vid_out_v4_0_10 = C:/Mentor/CompLib/2019.1.3/v_axi4s_vid_out_v4_0_10 -axi4svideo_bridge_v1_0_10 = C:/Mentor/CompLib/2019.1.3/axi4svideo_bridge_v1_0_10 -axis_accelerator_adapter_v2_1_15 = C:/Mentor/CompLib/2019.1.3/axis_accelerator_adapter_v2_1_15 -axis_broadcaster_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axis_broadcaster_v1_1_18 -axis_clock_converter_v1_1_20 = C:/Mentor/CompLib/2019.1.3/axis_clock_converter_v1_1_20 -axis_combiner_v1_1_17 = C:/Mentor/CompLib/2019.1.3/axis_combiner_v1_1_17 -axis_data_fifo_v1_1_20 = C:/Mentor/CompLib/2019.1.3/axis_data_fifo_v1_1_20 -axis_data_fifo_v2_0_1 = C:/Mentor/CompLib/2019.1.3/axis_data_fifo_v2_0_1 -axis_register_slice_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_register_slice_v1_1_19 -axis_dwidth_converter_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axis_dwidth_converter_v1_1_18 -axis_subset_converter_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_subset_converter_v1_1_19 -axis_switch_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_switch_v1_1_19 -axis_vio_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axis_vio_v1_0_0 -axi_apb_bridge_v3_0_15 = C:/Mentor/CompLib/2019.1.3/axi_apb_bridge_v3_0_15 -axi_bram_ctrl_v4_0_14 = C:/Mentor/CompLib/2019.1.3/axi_bram_ctrl_v4_0_14 -axi_sg_v4_1_12 = C:/Mentor/CompLib/2019.1.3/axi_sg_v4_1_12 -axi_cdma_v4_1_19 = C:/Mentor/CompLib/2019.1.3/axi_cdma_v4_1_19 -axi_clock_converter_v2_1_18 = C:/Mentor/CompLib/2019.1.3/axi_clock_converter_v2_1_18 -axi_data_fifo_v2_1_18 = C:/Mentor/CompLib/2019.1.3/axi_data_fifo_v2_1_18 -axi_register_slice_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_register_slice_v2_1_19 -axi_crossbar_v2_1_20 = C:/Mentor/CompLib/2019.1.3/axi_crossbar_v2_1_20 -axi_dma_v7_1_20 = C:/Mentor/CompLib/2019.1.3/axi_dma_v7_1_20 -axi_protocol_converter_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_protocol_converter_v2_1_19 -axi_dwidth_converter_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_dwidth_converter_v2_1_19 -axi_emc_v3_0_19 = C:/Mentor/CompLib/2019.1.3/axi_emc_v3_0_19 -axi_epc_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_epc_v2_0_22 -lib_bmg_v1_0_12 = C:/Mentor/CompLib/2019.1.3/lib_bmg_v1_0_12 -axi_ethernetlite_v3_0_17 = C:/Mentor/CompLib/2019.1.3/axi_ethernetlite_v3_0_17 -axi_ethernet_buffer_v2_0_20 = C:/Mentor/CompLib/2019.1.3/axi_ethernet_buffer_v2_0_20 -axi_fifo_mm_s_v4_1_16 = C:/Mentor/CompLib/2019.1.3/axi_fifo_mm_s_v4_1_16 -axi_fifo_mm_s_v4_2_1 = C:/Mentor/CompLib/2019.1.3/axi_fifo_mm_s_v4_2_1 -axi_firewall_v1_0_7 = C:/Mentor/CompLib/2019.1.3/axi_firewall_v1_0_7 -interrupt_control_v3_1_4 = C:/Mentor/CompLib/2019.1.3/interrupt_control_v3_1_4 -axi_gpio_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_gpio_v2_0_21 -axi_hwicap_v3_0_23 = C:/Mentor/CompLib/2019.1.3/axi_hwicap_v3_0_23 -axi_iic_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_iic_v2_0_22 -axi_intc_v4_1_13 = C:/Mentor/CompLib/2019.1.3/axi_intc_v4_1_13 -axi_interconnect_v1_7_16 = C:/Mentor/CompLib/2019.1.3/axi_interconnect_v1_7_16 -axi_master_burst_v2_0_7 = C:/Mentor/CompLib/2019.1.3/axi_master_burst_v2_0_7 -axi_msg_v1_0_5 = C:/Mentor/CompLib/2019.1.3/axi_msg_v1_0_5 -axi_mcdma_v1_0_5 = C:/Mentor/CompLib/2019.1.3/axi_mcdma_v1_0_5 -axi_mcdma_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axi_mcdma_v1_1_0 -axi_memory_init_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_memory_init_v1_0_0 -axi_mm2s_mapper_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axi_mm2s_mapper_v1_1_18 -axi_mmu_v2_1_17 = C:/Mentor/CompLib/2019.1.3/axi_mmu_v2_1_17 -axi_pcie_v2_9_1 = C:/Mentor/CompLib/2019.1.3/axi_pcie_v2_9_1 -axi_protocol_checker_v2_0_5 = C:/Mentor/CompLib/2019.1.3/axi_protocol_checker_v2_0_5 -axi_quad_spi_v3_2_18 = C:/Mentor/CompLib/2019.1.3/axi_quad_spi_v3_2_18 -axi_sideband_util_v1_0_3 = C:/Mentor/CompLib/2019.1.3/axi_sideband_util_v1_0_3 -axi_tft_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_tft_v2_0_22 -axi_timebase_wdt_v3_0_11 = C:/Mentor/CompLib/2019.1.3/axi_timebase_wdt_v3_0_11 -axi_timer_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_timer_v2_0_21 -axi_traffic_gen_v2_0_20 = C:/Mentor/CompLib/2019.1.3/axi_traffic_gen_v2_0_20 -axi_traffic_gen_v3_0_5 = C:/Mentor/CompLib/2019.1.3/axi_traffic_gen_v3_0_5 -axi_uart16550_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_uart16550_v2_0_21 -axi_uartlite_v2_0_23 = C:/Mentor/CompLib/2019.1.3/axi_uartlite_v2_0_23 -axi_usb2_device_v5_0_20 = C:/Mentor/CompLib/2019.1.3/axi_usb2_device_v5_0_20 -axi_utils_v2_0_6 = C:/Mentor/CompLib/2019.1.3/axi_utils_v2_0_6 -axi_vdma_v6_3_7 = C:/Mentor/CompLib/2019.1.3/axi_vdma_v6_3_7 -xbip_pipe_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_pipe_v3_0_6 -xbip_dsp48_addsub_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_addsub_v3_0_6 -xbip_addsub_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_addsub_v3_0_6 -c_reg_fd_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_reg_fd_v12_0_6 -c_addsub_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_addsub_v12_0_13 -axi_vfifo_ctrl_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_vfifo_ctrl_v2_0_21 -axi_vip_v1_1_5 = C:/Mentor/CompLib/2019.1.3/axi_vip_v1_1_5 -bs_switch_v1_0_0 = C:/Mentor/CompLib/2019.1.3/bs_switch_v1_0_0 -canfd_v2_0_1 = C:/Mentor/CompLib/2019.1.3/canfd_v2_0_1 -can_v5_0_22 = C:/Mentor/CompLib/2019.1.3/can_v5_0_22 -cic_compiler_v4_0_14 = C:/Mentor/CompLib/2019.1.3/cic_compiler_v4_0_14 -xbip_bram18k_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_bram18k_v3_0_6 -mult_gen_v12_0_15 = C:/Mentor/CompLib/2019.1.3/mult_gen_v12_0_15 -cmpy_v6_0_17 = C:/Mentor/CompLib/2019.1.3/cmpy_v6_0_17 -c_mux_bit_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_mux_bit_v12_0_6 -c_shift_ram_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_shift_ram_v12_0_13 -c_mux_bus_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_mux_bus_v12_0_6 -c_gate_bit_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_gate_bit_v12_0_6 -xbip_counter_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_counter_v3_0_6 -c_counter_binary_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_counter_binary_v12_0_13 -c_compare_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_compare_v12_0_6 -convolution_v9_0_14 = C:/Mentor/CompLib/2019.1.3/convolution_v9_0_14 -cordic_v6_0_15 = C:/Mentor/CompLib/2019.1.3/cordic_v6_0_15 -cpri_v8_10_3 = C:/Mentor/CompLib/2019.1.3/cpri_v8_10_3 -xbip_dsp48_acc_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_acc_v3_0_6 -xbip_accum_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_accum_v3_0_6 -c_accum_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_accum_v12_0_13 -xbip_dsp48_multadd_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_multadd_v3_0_6 -dds_compiler_v6_0_18 = C:/Mentor/CompLib/2019.1.3/dds_compiler_v6_0_18 -dft_v4_0_16 = C:/Mentor/CompLib/2019.1.3/dft_v4_0_16 -dft_v4_1_1 = C:/Mentor/CompLib/2019.1.3/dft_v4_1_1 -displayport_v7_0_11 = C:/Mentor/CompLib/2019.1.3/displayport_v7_0_11 -displayport_v8_1_1 = C:/Mentor/CompLib/2019.1.3/displayport_v8_1_1 -displayport_v9_0_1 = C:/Mentor/CompLib/2019.1.3/displayport_v9_0_1 -xbip_dsp48_mult_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_mult_v3_0_6 -floating_point_v7_0_16 = C:/Mentor/CompLib/2019.1.3/floating_point_v7_0_16 -div_gen_v5_1_15 = C:/Mentor/CompLib/2019.1.3/div_gen_v5_1_15 -dp_videoaxi4s_bridge_v1_0_0 = C:/Mentor/CompLib/2019.1.3/dp_videoaxi4s_bridge_v1_0_0 -dsp_macro_v1_0_0 = C:/Mentor/CompLib/2019.1.3/dsp_macro_v1_0_0 -fir_compiler_v5_2_6 = C:/Mentor/CompLib/2019.1.3/fir_compiler_v5_2_6 -duc_ddc_compiler_v3_0_15 = C:/Mentor/CompLib/2019.1.3/duc_ddc_compiler_v3_0_15 -ernic_v1_0_1 = C:/Mentor/CompLib/2019.1.3/ernic_v1_0_1 -etrnic_v1_0_3 = C:/Mentor/CompLib/2019.1.3/etrnic_v1_0_3 -etrnic_v1_1_2 = C:/Mentor/CompLib/2019.1.3/etrnic_v1_1_2 -fc32_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/fc32_rs_fec_v1_0_11 -fec_5g_common_v1_0_1 = C:/Mentor/CompLib/2019.1.3/fec_5g_common_v1_0_1 -fec_5g_common_v1_1_1 = C:/Mentor/CompLib/2019.1.3/fec_5g_common_v1_1_1 -fir_compiler_v7_2_12 = C:/Mentor/CompLib/2019.1.3/fir_compiler_v7_2_12 -flexo_100g_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/flexo_100g_rs_fec_v1_0_11 -floating_point_v7_1_8 = C:/Mentor/CompLib/2019.1.3/floating_point_v7_1_8 -g709_rs_encoder_v2_2_6 = C:/Mentor/CompLib/2019.1.3/g709_rs_encoder_v2_2_6 -rs_toolbox_v9_0_7 = C:/Mentor/CompLib/2019.1.3/rs_toolbox_v9_0_7 -g709_rs_decoder_v2_2_8 = C:/Mentor/CompLib/2019.1.3/g709_rs_decoder_v2_2_8 -g709_fec_v2_3_5 = C:/Mentor/CompLib/2019.1.3/g709_fec_v2_3_5 -g709_fec_v2_4_1 = C:/Mentor/CompLib/2019.1.3/g709_fec_v2_4_1 -g975_efec_i4_v1_0_17 = C:/Mentor/CompLib/2019.1.3/g975_efec_i4_v1_0_17 -g975_efec_i7_v2_0_18 = C:/Mentor/CompLib/2019.1.3/g975_efec_i7_v2_0_18 -ieee802d3_200g_rs_fec_v1_0_7 = C:/Mentor/CompLib/2019.1.3/ieee802d3_200g_rs_fec_v1_0_7 -ieee802d3_25g_rs_fec_v1_0_13 = C:/Mentor/CompLib/2019.1.3/ieee802d3_25g_rs_fec_v1_0_13 -ieee802d3_400g_rs_fec_v1_0_7 = C:/Mentor/CompLib/2019.1.3/ieee802d3_400g_rs_fec_v1_0_7 -ieee802d3_50g_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/ieee802d3_50g_rs_fec_v1_0_11 -ieee802d3_50g_rs_fec_v2_0_1 = C:/Mentor/CompLib/2019.1.3/ieee802d3_50g_rs_fec_v2_0_1 -ieee802d3_rs_fec_v1_0_15 = C:/Mentor/CompLib/2019.1.3/ieee802d3_rs_fec_v1_0_15 -ieee802d3_rs_fec_v2_0_5 = C:/Mentor/CompLib/2019.1.3/ieee802d3_rs_fec_v2_0_5 -ldpc_v2_0_3 = C:/Mentor/CompLib/2019.1.3/ldpc_v2_0_3 -lte_3gpp_channel_estimator_v2_0_16 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_channel_estimator_v2_0_16 -lte_3gpp_mimo_decoder_v3_0_15 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_mimo_decoder_v3_0_15 -lte_3gpp_mimo_encoder_v4_0_14 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_mimo_encoder_v4_0_14 -tcc_encoder_3gpplte_v4_0_15 = C:/Mentor/CompLib/2019.1.3/tcc_encoder_3gpplte_v4_0_15 -lte_dl_channel_encoder_v3_0_15 = C:/Mentor/CompLib/2019.1.3/lte_dl_channel_encoder_v3_0_15 -lte_dl_channel_encoder_v4_0_0 = C:/Mentor/CompLib/2019.1.3/lte_dl_channel_encoder_v4_0_0 -xfft_v7_2_9 = C:/Mentor/CompLib/2019.1.3/xfft_v7_2_9 -lte_fft_v2_0_18 = C:/Mentor/CompLib/2019.1.3/lte_fft_v2_0_18 -xfft_v9_1_2 = C:/Mentor/CompLib/2019.1.3/xfft_v9_1_2 -lte_fft_v2_1_0 = C:/Mentor/CompLib/2019.1.3/lte_fft_v2_1_0 -xbip_dsp48_multacc_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_multacc_v3_0_6 -lte_pucch_receiver_v2_0_16 = C:/Mentor/CompLib/2019.1.3/lte_pucch_receiver_v2_0_16 -xbip_multadd_v3_0_14 = C:/Mentor/CompLib/2019.1.3/xbip_multadd_v3_0_14 -lte_rach_detector_v3_1_5 = C:/Mentor/CompLib/2019.1.3/lte_rach_detector_v3_1_5 -lte_ul_channel_decoder_v4_0_16 = C:/Mentor/CompLib/2019.1.3/lte_ul_channel_decoder_v4_0_16 -mailbox_v2_1_11 = C:/Mentor/CompLib/2019.1.3/mailbox_v2_1_11 -mdm_v3_2_16 = C:/Mentor/CompLib/2019.1.3/mdm_v3_2_16 -iomodule_v3_0 = C:/Mentor/CompLib/2019.1.3/iomodule_v3_0 -lmb_bram_if_cntlr_v4_0 = C:/Mentor/CompLib/2019.1.3/lmb_bram_if_cntlr_v4_0 -lmb_v10_v3_0 = C:/Mentor/CompLib/2019.1.3/lmb_v10_v3_0 -axi_lite_ipif_v3_0 = C:/Mentor/CompLib/2019.1.3/axi_lite_ipif_v3_0 -mdm_v3_2 = C:/Mentor/CompLib/2019.1.3/mdm_v3_2 -microblaze_mcs_v2_3_6 = C:/Mentor/CompLib/2019.1.3/microblaze_mcs_v2_3_6 -noc_mc_ddr4_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_mc_ddr4_phy_v1_0_0 -perf_axi_tg_v1_0_8 = C:/Mentor/CompLib/2019.1.3/perf_axi_tg_v1_0_8 -polar_v1_0_3 = C:/Mentor/CompLib/2019.1.3/polar_v1_0_3 -prc_v1_3_2 = C:/Mentor/CompLib/2019.1.3/prc_v1_3_2 -processing_system7_vip_v1_0_7 = C:/Mentor/CompLib/2019.1.3/processing_system7_vip_v1_0_7 -proc_sys_reset_v5_0_13 = C:/Mentor/CompLib/2019.1.3/proc_sys_reset_v5_0_13 -pr_axi_shutdown_manager_v1_0_1 = C:/Mentor/CompLib/2019.1.3/pr_axi_shutdown_manager_v1_0_1 -pr_bitstream_monitor_v1_0_1 = C:/Mentor/CompLib/2019.1.3/pr_bitstream_monitor_v1_0_1 -pr_decoupler_v1_0_7 = C:/Mentor/CompLib/2019.1.3/pr_decoupler_v1_0_7 -quadsgmii_v3_4_6 = C:/Mentor/CompLib/2019.1.3/quadsgmii_v3_4_6 -rs_decoder_v9_0_16 = C:/Mentor/CompLib/2019.1.3/rs_decoder_v9_0_16 -rs_encoder_v9_0_15 = C:/Mentor/CompLib/2019.1.3/rs_encoder_v9_0_15 -rxaui_v4_4_6 = C:/Mentor/CompLib/2019.1.3/rxaui_v4_4_6 -sd_fec_v1_1_3 = C:/Mentor/CompLib/2019.1.3/sd_fec_v1_1_3 -sid_v8_0_14 = C:/Mentor/CompLib/2019.1.3/sid_v8_0_14 -soft_ecc_proxy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/soft_ecc_proxy_v1_0_0 -spdif_v2_0_21 = C:/Mentor/CompLib/2019.1.3/spdif_v2_0_21 -srio_gen2_v4_1_6 = C:/Mentor/CompLib/2019.1.3/srio_gen2_v4_1_6 -switch_core_top_v1_0_7 = C:/Mentor/CompLib/2019.1.3/switch_core_top_v1_0_7 -sync_ip = C:/Mentor/CompLib/2019.1.3/sync_ip -tcc_decoder_3gppmm_v2_0_18 = C:/Mentor/CompLib/2019.1.3/tcc_decoder_3gppmm_v2_0_18 -tcc_encoder_3gpp_v5_0_15 = C:/Mentor/CompLib/2019.1.3/tcc_encoder_3gpp_v5_0_15 -tmr_comparator_v1_0_2 = C:/Mentor/CompLib/2019.1.3/tmr_comparator_v1_0_2 -tmr_sem_v1_0_9 = C:/Mentor/CompLib/2019.1.3/tmr_sem_v1_0_9 -tri_mode_ethernet_mac_v9_0_14 = C:/Mentor/CompLib/2019.1.3/tri_mode_ethernet_mac_v9_0_14 -tsn_temac_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tsn_temac_v1_0_4 -videoaxi4s_bridge_v1_0_5 = C:/Mentor/CompLib/2019.1.3/videoaxi4s_bridge_v1_0_5 -viterbi_v9_1_11 = C:/Mentor/CompLib/2019.1.3/viterbi_v9_1_11 -v_ccm_v6_0_15 = C:/Mentor/CompLib/2019.1.3/v_ccm_v6_0_15 -v_cfa_v7_0_14 = C:/Mentor/CompLib/2019.1.3/v_cfa_v7_0_14 -v_cresample_v4_0_14 = C:/Mentor/CompLib/2019.1.3/v_cresample_v4_0_14 -v_dual_splitter_v1_0_9 = C:/Mentor/CompLib/2019.1.3/v_dual_splitter_v1_0_9 -v_enhance_v8_0_15 = C:/Mentor/CompLib/2019.1.3/v_enhance_v8_0_15 -v_gamma_v7_0_15 = C:/Mentor/CompLib/2019.1.3/v_gamma_v7_0_15 -v_osd_v6_0_16 = C:/Mentor/CompLib/2019.1.3/v_osd_v6_0_16 -v_rgb2ycrcb_v7_1_13 = C:/Mentor/CompLib/2019.1.3/v_rgb2ycrcb_v7_1_13 -v_vid_sdi_tx_bridge_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_vid_sdi_tx_bridge_v2_0_0 -v_ycrcb2rgb_v7_1_13 = C:/Mentor/CompLib/2019.1.3/v_ycrcb2rgb_v7_1_13 -xbip_dsp48_macro_v3_0_17 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_macro_v3_0_17 -xfft_v9_0_17 = C:/Mentor/CompLib/2019.1.3/xfft_v9_0_17 -xsdbs_v1_0_2 = C:/Mentor/CompLib/2019.1.3/xsdbs_v1_0_2 -zynq_ultra_ps_e_vip_v1_0_5 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_vip_v1_0_5 -[DefineOptionset] -; Define optionset entries for the various compilers, vmake, and vsim. -; These option sets can be used with the "-optionset " syntax. -; i.e. -; vlog -optionset COMPILEDEBUG top.sv -; vsim -optionset UVMDEBUG my_top -; -; Following are some useful examples. - -; define a vsim optionset for uvm debugging -UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop - -; define a vopt optionset for debugging -VOPTDEBUG = +acc -debugdb - -[encryption] -; For vencrypt and vhencrypt. - -; Controls whether to encrypt whole files by ignoring all protect directives -; (except "viewport" and "interface_viewport") that are present in the input. -; The default is 0, use embedded protect directives to control the encryption. -; Set this to 1 to encrypt whole files by ignoring embedded protect directives. -; wholefile = 0 - -; Sets the data_method to use for the symmetric session key. -; The session key is a symmetric key that is randomly generated for each -; protected region (envelope) and is the heart of all encryption. This is used -; to set the length of the session key to generate and use when encrypting the -; HDL text. Supported values are aes128, aes192, and aes256. -; data_method = aes128 - -; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption -; "recipe" comprising an optional common block, at least one tool block (which -; contains the key public key), and the text to be encrypted. The common block -; and any of the tool blocks may contain rights in the form of the "control" -; directive. The text to be encrypted is specified either by setting -; "wholefile" to 1 or by embedding protect "begin" and "end" directives in -; the input HDL files. - -; Common recipe specification file. This file is optional. Its presence will -; require at least one "toolblock" to be specified. -; Directives such as "author" "author_info" and "data_method", -; as well as the common block license specification, go in this file. -; common = - -; Tool block specification recipe(s). Public key file with optional tool block -; file name. May be multiply-defined; at least one tool block is required if -; a recipe is being specified. -; Key file is a file name with no extension (.deprecated or .active will be -; supplied by the encryption tool). -; Rights file name is optional. -; toolblock = [,]{:[,]} - -; Location of directory containing recipe files. -; The default location is in the product installation directory. -; keyring = $MODEL_TECH/../keyring - -; Enable encryption statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list] -; Add '-' to disable specific statistics. Default is [cmd,msg]. -Stats = cmd,msg - -[vcom] -; VHDL93 variable selects language version as the default. -; Default is VHDL-2002. -; Value of 0 or 1987 for VHDL-1987. -; Value of 1 or 1993 for VHDL-1993. -; Default or value of 2 or 2002 for VHDL-2002. -; Value of 3 or 2008 for VHDL-2008 -; Value of 4 or ams99 for VHDL-AMS-1999 -; Value of 5 or ams07 for VHDL-AMS-2007 -VHDL93 = 2002 - -; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. -; ignoreStandardRealVector = 1 - -; Show source line containing error. Default is off. -; Show_source = 1 - -; Turn off unbound-component warnings. Default is on. -; Show_Warning1 = 0 - -; Turn off process-without-a-wait-statement warnings. Default is on. -; Show_Warning2 = 0 - -; Turn off null-range warnings. Default is on. -; Show_Warning3 = 0 - -; Turn off no-space-in-time-literal warnings. Default is on. -; Show_Warning4 = 0 - -; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. -; Show_Warning5 = 0 - -; Turn off optimization for IEEE std_logic_1164 package. Default is on. -; Optimize_1164 = 0 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Turn on resolving of ambiguous function overloading in favor of the -; "explicit" function declaration (not the one automatically created by -; the compiler for each type declaration). Default is off. -; The .ini file has Explicit enabled so that std_logic_signed/unsigned -; will match the behavior of synthesis tools. -Explicit = 1 - -; Turn off acceleration of the VITAL packages. Default is to accelerate. -; NoVital = 1 - -; Turn off VITAL compliance checking. Default is checking on. -; NoVitalCheck = 1 - -; Ignore VITAL compliance checking errors. Default is to not ignore. -; IgnoreVitalErrors = 1 - -; Turn off VITAL compliance checking warnings. Default is to show warnings. -; Show_VitalChecksWarnings = 0 - -; Turn off PSL assertion warning messages. Default is to show warnings. -; Show_PslChecksWarnings = 0 - -; Enable parsing of embedded PSL assertions. Default is enabled. -; EmbeddedPsl = 0 - -; Keep silent about case statement static warnings. -; Default is to give a warning. -; NoCaseStaticError = 1 - -; Keep silent about warnings caused by aggregates that are not locally static. -; Default is to give a warning. -; NoOthersStaticError = 1 - -; Treat as errors: -; case statement static warnings -; warnings caused by aggregates that are not locally static -; Overrides NoCaseStaticError, NoOthersStaticError settings. -; PedanticErrors = 1 - -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn off "Loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on some limited synthesis rule compliance checking. Checks only: -; -- signals used (read) by a process must be in the sensitivity list -; CheckSynthesis = 1 - -; Activate optimizations on expressions that do not involve signals, -; waits, or function/procedure/task invocations. Default is off. -; ScalarOpts = 1 - -; Turns on lint-style checking. -; Show_Lint = 1 - -; Require the user to specify a configuration for all bindings, -; and do not generate a compile time default binding for the -; component. This will result in an elaboration error of -; 'component not bound' if the user fails to do so. Avoids the rare -; issue of a false dependency upon the unused default binding. -; RequireConfigForAllDefaultBinding = 1 - -; Perform default binding at compile time. -; Default is to do default binding at load time. -; BindAtCompile = 1; - -; Inhibit range checking on subscripts of arrays. Range checking on -; scalars defined with subtypes is inhibited by default. -; NoIndexCheck = 1 - -; Inhibit range checks on all (implicit and explicit) assignments to -; scalar objects defined with subtypes. -; NoRangeCheck = 1 - -; Set the prefix to be honored for synthesis/coverage pragma recognition. -; Default is "". -; AddPragmaPrefix = "" - -; Ignore synthesis and coverage pragmas with this prefix. -; Default is "". -; IgnorePragmaPrefix = "" - -; Turn on code coverage in VHDL design units. Default is off. -; Coverage = sbceft - -; Turn off code coverage in VHDL subprograms. Default is on. -; CoverSub = 0 - -; Automatically exclude VHDL case statement OTHERS choice branches. -; This includes OTHERS choices in selected signal assigment statements. -; Default is to not exclude. -; CoverExcludeDefault = 1 - -; Control compiler and VOPT optimizations that are allowed when -; code coverage is on. Refer to the comment for this in the [vlog] area. -; CoverOpt = 3 - -; Turn on or off clkOpt optimization for code coverage. Default is on. -; CoverClkOpt = 1 - -; Turn on or off clkOpt optimization builtins for code coverage. Default is on. -; CoverClkOptBuiltins = 0 - -; Inform code coverage optimizations to respect VHDL 'H' and 'L' -; values on signals in conditions and expressions, and to not automatically -; convert them to '1' and '0'. Default is to not convert. -; CoverRespectHandL = 0 - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable or disable Focused Expression Coverage analysis for conditions and -; expressions. Focused Expression Coverage data is provided by default when -; expression and/or condition coverage is active. -; CoverFEC = 0 - -; Enable or disable UDP Coverage analysis for conditions and expressions. -; UDP Coverage data is disabled by default when expression and/or condition -; coverage is active. -; CoverUDP = 1 - -; Enable or disable Rapid Expression Coverage mode for conditions and expressions. -; Disabling this would convert non-masking conditions in FEC tables to matching -; input patterns. -; CoverREC = 1 - -; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions -; for expression/condition coverage. -; NOTE: Enabling this may have a negative impact on simulation performance. -; CoverExpandReductionPrefix = 0 - -; Enable or disable short circuit evaluation of conditions and expressions when -; condition or expression coverage is active. Short circuit evaluation is enabled -; by default. -; CoverShortCircuit = 0 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Use this directory for compiler temporary files instead of "work/_temp" -; CompilerTempDir = /tmp - -; Set this to cause the compilers to force data to be committed to disk -; when the files are closed. -; SyncCompilerFiles = 1 - -; Add VHDL-AMS declarations to package STANDARD -; Default is not to add -; AmsStandard = 1 - -; Range and length checking will be performed on array indices and discrete -; ranges, and when violations are found within subprograms, errors will be -; reported. Default is to issue warnings for violations, because subprograms -; may not be invoked. -; NoDeferSubpgmCheck = 0 - -; Turn ON detection of FSMs having single bit current state variable. -; FsmSingle = 1 - -; Turn off reset state transitions in FSM. -; FsmResetTrans = 0 - -; Turn ON detection of FSM Implicit Transitions. -; FsmImplicitTrans = 1 - -; Controls whether or not to show immediate assertions with constant expressions -; in GUI/report/UCDB etc. By default, immediate assertions with constant -; expressions are shown in GUI/report/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Controls how VHDL basic identifiers are stored with the design unit. -; Does not make the language case-sensitive, affects only how declarations -; declared with basic identifiers have their names stored and printed -; (in the GUI, examine, etc.). -; Default is to preserve the case as originally depicted in the VHDL source. -; Value of 0 indicates to change all basic identifiers to lower case. -; PreserveCase = 0 - -; For Configuration Declarations, controls the effect that USE clauses have -; on visibility inside the configuration items being configured. If 1 -; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, -; extend the visibility of objects made visible through USE clauses into nested -; component configurations. -; OldVHDLConfigurationVisibility = 0 - -; Allows VHDL configuration declarations to be in a different library from -; the corresponding configured entity. Default is to not allow this for -; stricter LRM-compliance. -; SeparateConfigLibrary = 1; - -; Determine how mode OUT subprogram parameters of type array and record are treated. -; If 0 (the default), then only VHDL 2008 will do this initialization. -; If 1, always initialize the mode OUT parameter to its default value. -; If 2, do not initialize the mode OUT out parameter. -; Note that prior to release 10.1, all language versions did not initialize mode -; OUT array and record type parameters, unless overridden here via this mechanism. -; In release 10.1 and later, only files compiled with VHDL 2008 will cause this -; initialization, unless overridden here. -; InitOutCompositeParam = 0 - -; Generate symbols debugging database in only some special cases to save on -; the number of files in the library. For other design-units, this database is -; generated on-demand in vsim. -; Default is to to generate debugging database for all design-units. -; SmartDbgSym = 1 - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -; Describe compilation options according to matching file patterns. -; File pattern * matches all printing characters other than '/'. -; File pattern **/x matches all paths containing file/directory x. -; File pattern x/** matches all paths beginning at directory x. -; FileOptMap = (**/*.vhd => -2008); - -; Describe library targets of compilation according to matching file patterns. -; LibMap = (**/*.vhd => work); - -[vlog] -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn off "Loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on Verilog hazard checking (order-dependent accessing of global vars). -; Default is off. -; Hazard = 1 - -; Turn on converting regular Verilog identifiers to uppercase. Allows case -; insensitivity for module names. Default is no conversion. -; UpCase = 1 - -; Activate optimizations on expressions that do not involve signals, -; waits, or function/procedure/task invocations. Default is off. -; ScalarOpts = 1 - -; Turns on lint-style checking. -; Show_Lint = 1 - -; Show source line containing error. Default is off. -; Show_source = 1 - -; Turn on bad option warning. Default is off. -; Show_BadOptionWarning = 1 - -; Revert back to IEEE 1364-1995 syntax, default is 0 (off). -; vlog95compat = 1 - -; Turn off PSL warning messages. Default is to show warnings. -; Show_PslChecksWarnings = 0 - -; Enable parsing of embedded PSL assertions. Default is enabled. -; EmbeddedPsl = 0 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Set the threshold for automatically identifying sparse Verilog memories. -; A memory with total size in bytes equal to or more than the sparse memory -; threshold gets marked as sparse automatically, unless specified otherwise -; in source code or by the +nosparse commandline option of vlog or vopt. -; The default is 1M. (i.e. memories with total size equal -; to or greater than 1Mb are marked as sparse) -; SparseMemThreshold = 1048576 - -; Set the prefix to be honored for synthesis and coverage pragma recognition. -; Default is "". -; AddPragmaPrefix = "" - -; Ignore synthesis and coverage pragmas with this prefix. -; Default is "". -; IgnorePragmaPrefix = "" - -; Set the option to treat all files specified in a vlog invocation as a -; single compilation unit. The default value is set to 0 which will treat -; each file as a separate compilation unit as specified in the P1800 draft standard. -; MultiFileCompilationUnit = 1 - -; Turn on code coverage in Verilog design units. Default is off. -; Coverage = sbceft - -; Automatically exclude Verilog case statement default branches. -; Default is to not automatically exclude defaults. -; CoverExcludeDefault = 1 - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Enable Multi Bit Expression Coverage in a Design, If design has expression with -; multi bit operands, this option enables its Expression Coverage. -; The default value is 0. -; CoverFecMultiBit = 1 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable or disable Focused Expression Coverage analysis for conditions and -; expressions. Focused Expression Coverage data is provided by default when -; expression and/or condition coverage is active. -; CoverFEC = 0 - -; Enable or disable UDP Coverage analysis for conditions and expressions. -; UDP Coverage data is disabled by default when expression and/or condition -; coverage is active. -; CoverUDP = 1 - -; Enable or disable Rapid Expression Coverage mode for conditions and expressions. -; Disabling this would convert non-masking conditions in FEC tables to matching -; input patterns. -; CoverREC = 1 - -; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions -; for expression/condition coverage. -; NOTE: Enabling this may have a negative impact on simulation performance. -; CoverExpandReductionPrefix = 0 - -; Enable or disable short circuit evaluation of conditions and expressions when -; condition or expression coverage is active. Short circuit evaluation is enabled -; by default. -; CoverShortCircuit = 0 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Turn on code coverage in VLOG `celldefine modules, modules containing -; specify blocks, and modules included using vlog -v and -y. Default is off. -; CoverCells = 1 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Control compiler and VOPT optimizations that are allowed when -; code coverage is on. This is a number from 0 to 5, with the following -; meanings (the default is 3): -; 5 -- All allowable optimizations are on. -; 4 -- Turn off removing unreferenced code. -; 3 -- Turn off process, always block and if statement merging. -; 2 -- Turn off expression optimization, converting primitives -; to continuous assignments, VHDL subprogram inlining. -; and VHDL clkOpt (converting FF's to builtins). -; 1 -- Turn off continuous assignment optimizations and clock suppression. -; 0 -- Turn off Verilog module inlining and VHDL arch inlining. -; HOWEVER, if fsm coverage is turned on, optimizations will be forced to -; level 3, with also turning off converting primitives to continuous assigns. -; CoverOpt = 3 - -; Specify the override for the default value of "cross_num_print_missing" -; option for the Cross in Covergroups. If not specified then LRM default -; value of 0 (zero) is used. This is a compile time option. -; SVCrossNumPrintMissingDefault = 0 - -; Setting following to 1 would cause creation of variables which -; would represent the value of Coverpoint expressions. This is used -; in conjunction with "SVCoverpointExprVariablePrefix" option -; in the modelsim.ini -; EnableSVCoverpointExprVariable = 0 - -; Specify the override for the prefix used in forming the variable names -; which represent the Coverpoint expressions. This is used in conjunction with -; "EnableSVCoverpointExprVariable" option of the modelsim.ini -; The default prefix is "expr". -; The variable name is -; variable name => _ -; SVCoverpointExprVariablePrefix = expr - -; Override for the default value of the SystemVerilog covergroup, -; coverpoint, and cross option.goal (defined to be 100 in the LRM). -; NOTE: It does not override specific assignments in SystemVerilog -; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" -; in the [vsim] section can override this value. -; SVCovergroupGoalDefault = 100 - -; Override for the default value of the SystemVerilog covergroup, -; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) -; NOTE: It does not override specific assignments in SystemVerilog -; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" -; in the [vsim] section can override this value. -; SVCovergroupTypeGoalDefault = 100 - -; Specify the override for the default value of "strobe" option for the -; Covergroup Type. This is a compile time option which forces "strobe" to -; a user specified default value and supersedes SystemVerilog specified -; default value of '0'(zero). NOTE: This can be overriden by a runtime -; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. -; SVCovergroupStrobeDefault = 0 - -; Specify the override for the default value of "per_instance" option for the -; Covergroup variables. This is a compile time option which forces "per_instance" -; to a user specified default value and supersedes SystemVerilog specified -; default value of '0'(zero). -; SVCovergroupPerInstanceDefault = 0 - -; Specify the override for the default value of "get_inst_coverage" option for the -; Covergroup variables. This is a compile time option which forces -; "get_inst_coverage" to a user specified default value and supersedes -; SystemVerilog specified default value of '0'(zero). -; SVCovergroupGetInstCoverageDefault = 0 - -; -; A space separated list of resource libraries that contain precompiled -; packages. The behavior is identical to using the "-L" switch. -; -; LibrarySearchPath = [ ...] -LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact - -; The behavior is identical to the "-mixedansiports" switch. Default is off. -; MixedAnsiPorts = 1 - -; Enable SystemVerilog 3.1a $typeof() function. Default is off. -; EnableTypeOf = 1 - -; Only allow lower case pragmas. Default is disabled. -; AcceptLowerCasePragmaOnly = 1 - -; Set the maximum depth permitted for a recursive include file nesting. -; IncludeRecursionDepthMax = 5 - -; Turn ON detection of FSMs having single bit current state variable. -; FsmSingle = 1 - -; Turn off reset state transitions in FSM. -; FsmResetTrans = 0 - -; Turn off detections of FSMs having x-assignment. -; FsmXAssign = 0 - -; Turn ON detection of FSM Implicit Transitions. -; FsmImplicitTrans = 1 - -; List of file suffixes which will be read as SystemVerilog. White space -; in extensions can be specified with a back-slash: "\ ". Back-slashes -; can be specified with two consecutive back-slashes: "\\"; -; SvFileSuffixes = sv svp svh - -; This setting is the same as the vlog -sv command line switch. -; Enables SystemVerilog features and keywords when true (1). -; When false (0), the rules of IEEE Std 1364-2005 are followed and -; SystemVerilog keywords are ignored. -; Svlog = 0 - -; Prints attribute placed upon SV packages during package import -; when true (1). The attribute will be ignored when this -; entry is false (0). The attribute name is "mti_design_element_load_message". -; The value of this attribute is a string literal. -; Default is true (1). -; PrintSVPackageLoadingAttribute = 1 - -; Do not show immediate assertions with constant expressions in -; GUI/reports/UCDB etc. By default immediate assertions with constant -; expressions are shown in GUI/reports/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Controls if untyped parameters that are initialized with values greater -; than 2147483647 are mapped to generics of type INTEGER or ignored. -; If mapped to VHDL Integers, values greater than 2147483647 -; are mapped to negative values. -; Default is to map these parameter to generic of type INTEGER -; ForceUnsignedToVHDLInteger = 1 - -; Enable AMS wreal (wired real) extensions. Default is 0. -; WrealType = 1 - -; Controls SystemVerilog Language Extensions. These options enable -; some non-LRM compliant behavior. -; SvExtensions = [+|-][,[+|-]*] - -; Generate symbols debugging database in only some special cases to save on -; the number of files in the library. For other design-units, this database is -; generated on-demand in vsim. -; Default is to to generate debugging database for all design-units. -; SmartDbgSym = 1 - -; Controls how $unit library entries are named. Valid options are: -; "file" (generate name based on the first file on the command line) -; "du" (generate name based on first design unit following an item -; found in $unit scope) -; CUAutoName = file - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -[sccom] -; Enable use of SCV include files and library. Default is off. -; UseScv = 1 - -; Add C++ compiler options to the sccom command line by using this variable. -; CppOptions = -g - -; Use custom C++ compiler located at this path rather than the default path. -; The path should point directly at a compiler executable. -; CppPath = /usr/bin/g++ - -; Specify the compiler version from the list of support GNU compilers. -; examples 4.7.4, 5.3.0, 7.4.0 -; CppInstall = 7.4.0 - -; Enable verbose messages from sccom. Default is off. -; SccomVerbose = 1 - -; sccom logfile. Default is no logfile. -; SccomLogfile = sccom.log - -; Enable use of SC_MS include files and library. Default is off. -; UseScMs = 1 - -; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. -; Sc22Mode = 1 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -; Enable use of UVMC library. Default is off. -; UseUvmc = 1 - -[vopt] -; Turn on code coverage in vopt. Default is off. -; Coverage = sbceft - -; enable or disable param saving in UCDB. -; CoverageSaveParam = 0 - -; Control compiler optimizations that are allowed when -; code coverage is on. Refer to the comment for this in the [vlog] area. -; CoverOpt = 3 - -; Controls set of CoverConstructs that are being considered for Coverage -; Collection. -; Some of Valid options are: default,set1,set2 -; Covermode = default - -; Controls set of HDL cover constructs that would be considered(or not considered) -; for Coverage Collection. (Default corresponds to covermode default). -; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". -; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Enable Multi Bit Expression Coverage in a Design, If design has expression with -; multi bit operands, this option enables its Expression Coverage. -; The default value is 0. -; CoverFecMultiBit = 1 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Do not show immediate assertions with constant expressions in -; GUI/reports/UCDB etc. By default immediate assertions with constant -; expressions are shown in GUI/reports/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Set the maximum number of iterations permitted for a generate loop. -; Restricting this permits the implementation to recognize infinite -; generate loops. -; GenerateLoopIterationMax = 100000 - -; Set the maximum depth permitted for a recursive generate instantiation. -; Restricting this permits the implementation to recognize infinite -; recursions. -; GenerateRecursionDepthMax = 200 - -; Set the number of processes created during the code generation phase. -; By default a heuristic is used to set this value. This may be set to 0 -; to disable this feature completely. -; ParallelJobs = 0 - -; Controls SystemVerilog Language Extensions. These options enable -; some non-LRM compliant behavior. -; SvExtensions = [+|-][,[+|-]*] - -; Load the specified shared objects with the RTLD_GLOBAL flag. -; This gives global visibility to all symbols in the shared objects, -; meaning that subsequently loaded shared objects can bind to symbols -; in the global shared objects. The list of shared objects should -; be whitespace delimited. This option is not supported on the -; Windows or AIX platforms. -; GlobalSharedObjectList = example1.so example2.so example3.so - -; Disable SystemVerilog elaboration system task messages -; IgnoreSVAInfo = 1 -; IgnoreSVAWarning = 1 -; IgnoreSVAError = 1 -; IgnoreSVAFatal = 1 - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -[vsim] -; vopt flow -; Set to turn on automatic optimization of a design. -; Default is on -VoptFlow = 1 - -; Simulator resolution -; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. -Resolution = fs - -; Disable certain code coverage exclusions automatically. -; Assertions and FSM are exluded from the code coverage by default -; Set AutoExclusionsDisable = fsm to enable code coverage for fsm -; Set AutoExclusionsDisable = assertions to enable code coverage for assertions -; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions -; Or specify comma or space separated list -;AutoExclusionsDisable = fsm,assertions - -; User time unit for run commands -; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the -; unit specified for Resolution. For example, if Resolution is 100ps, -; then UserTimeUnit defaults to ps. -; Should generally be set to default. -UserTimeUnit = default - -; Default run length -RunLength = 100 - -; Maximum iterations that can be run without advancing simulation time -IterationLimit = 10000000 - -; Specify libraries to be searched for precompiled modules -; LibrarySearchPath = [ ...] - -; Set XPROP assertion fail limit. Default is 5. -; Any positive integer, -1 for infinity. -; XpropAssertionLimit = 5 - -; Control PSL and Verilog Assume directives during simulation -; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts -; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts -; SimulateAssumeDirectives = 1 - -; Control the simulation of PSL and SVA -; These switches can be overridden by the vsim command line switches: -; -psl, -nopsl, -sva, -nosva. -; Set SimulatePSL = 0 to disable PSL simulation -; Set SimulatePSL = 1 to enable PSL simulation (default) -; SimulatePSL = 1 -; Set SimulateSVA = 0 to disable SVA simulation -; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) -; SimulateSVA = 1 - -; Control SVA and VHDL immediate assertion directives during simulation -; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts -; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts -; SimulateImmedAsserts = 1 - -; License feature mappings for Verilog and VHDL -; qhsimvh Single language VHDL license -; qhsimvl Single language Verilog license -; msimhdlsim Language neutral license for either Verilog or VHDL -; msimhdlmix Second language only, language neutral license for either -; Verilog or VHDL -; -; Directives to license manager can be set either as single value or as -; space separated multi-values: -; vhdl Immediately checkout and hold a VHDL license (i.e., one of -; qhsimvh, msimhdlsim, or msimhdlmix) -; vlog Immediately checkout and hold a Verilog license (i.e., one of -; qhsimvl, msimhdlsim, or msimhdlmix) -; plus Immediately checkout and hold a VHDL license and a Verilog license -; noqueue Do not wait in the license queue when a license is not available -; viewsim Try for viewer license but accept simulator license(s) instead -; of queuing for viewer license (PE ONLY) -; noviewer Disable checkout of msimviewer license feature (PE ONLY) -; noslvhdl Disable checkout of qhsimvh license feature -; noslvlog Disable checkout of qhsimvl license feature -; nomix Disable checkout of msimhdlmix license feature -; nolnl Disable checkout of msimhdlsim license feature -; mixedonly Disable checkout of qhsimvh and qhsimvl license features -; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features -; -; Examples (remove ";" comment character to activate licensing directives): -; Single directive: -; License = plus -; Multi-directive (Note: space delimited directives): -; License = noqueue plus - -; Severity level of a VHDL assertion message or of a SystemVerilog severity system task -; which will cause a running simulation to stop. -; VHDL assertions and SystemVerilog severity system task that occur with the -; given severity or higher will cause a running simulation to stop. -; This value is ignored during elaboration. -; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal -BreakOnAssertion = 3 - -; Severity level of a tool message which will cause a running simulation to -; stop. This value is ignored during elaboration. Default is to not break. -; 0 = Note 1 = Warning 2 = Error 3 = Fatal -;BreakOnMessage = 2 - -; The class debug feature enables more visibility and tracking of class instances -; during simulation. By default this feature is disabled (0). To enable this -; feature set ClassDebug to 1. -; ClassDebug = 1 - -; Message Format conversion specifications: -; %S - Severity Level of message/assertion -; %R - Text of message -; %T - Time of message -; %D - Delta value (iteration number) of Time -; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected -; %i - Instance/Region/Signal pathname with Process name (if available) -; %I - shorthand for one of these: -; " %K: %i" -; " %K: %i File: %F" (when path is not Process or Signal) -; except that the %i in this case does not report the Process name -; %O - Process name -; %P - Instance/Region path without leaf process -; %F - File name -; %L - Line number; if assertion message, then line number of assertion or, if -; assertion is in a subprogram, line from which the call is made -; %u - Design unit name in form library.primary -; %U - Design unit name in form library.primary(secondary) -; %% - The '%' character itself -; -; If specific format for Severity Level is defined, use that format. -; Else, for a message that occurs during elaboration: -; -- Failure/Fatal message in VHDL region that is not a Process, and in -; certain non-VHDL regions, uses MessageFormatBreakLine; -; -- Failure/Fatal message otherwise uses MessageFormatBreak; -; -- Note/Warning/Error message uses MessageFormat. -; Else, for a message that occurs during runtime and triggers a breakpoint because -; of the BreakOnAssertion setting: -; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; -; -- otherwise uses MessageFormatBreak. -; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. -; -; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" -; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" -; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" -; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" - -; Error File - alternate file for storing error messages -; ErrorFile = error.log - -; Simulation Breakpoint messages -; This flag controls the display of function names when reporting the location -; where the simulator stops because of a breakpoint or fatal error. -; Example with function name: # Break in Process ctr at counter.vhd line 44 -; Example without function name: # Break at counter.vhd line 44 -; Default value is 1. -ShowFunctions = 1 - -; Default radix for all windows and commands. -; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned -; Flags may be one of: enumnumeric, showbase, wreal -DefaultRadix = hexadecimal -DefaultRadixFlags = showbase -; Set to 1 for make the signal_force VHDL and Verilog functions use the -; default radix when processing the force value. Prior to 10.2 signal_force -; used the default radix, now it always uses symbolic unless value explicitly indicates base -;SignalForceFunctionUseDefaultRadix = 0 - -; VSIM Startup command -; Startup = do startup.do - -; VSIM Shutdown file -; Filename to save u/i formats and configurations. -; ShutdownFile = restart.do -; To explicitly disable auto save: -; ShutdownFile = --disable-auto-save - -; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. -; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. -; BatchMode = 1 - -; File for saving command transcript when -batch option used -; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero -; default is unset so command transcript only goes to stdout for better performance -; BatchTranscriptFile = transcript - -; File for saving command transcript, this option is ignored when -batch option is used -TranscriptFile = transcript - -; Transcript file long line wrapping mode(s) -; mode == 0 :: no wrapping, line recorded as is -; mode == 1 :: wrap at first whitespace after WSColumn -; or at Column. -; mode == 2 :: wrap as above, but add continuation -; character ('\') at end of each wrapped line -; -; WrapMode = 0 -; WrapColumn = 30000 -; WrapWSColumn = 27000 - -; File for saving command history -; CommandHistory = cmdhist.log - -; Specify whether paths in simulator commands should be described -; in VHDL or Verilog format. -; For VHDL, PathSeparator = / -; For Verilog, PathSeparator = . -; Must not be the same character as DatasetSeparator. -PathSeparator = / - -; Specify the dataset separator for fully rooted contexts. -; The default is ':'. For example: sim:/top -; Must not be the same character as PathSeparator. -DatasetSeparator = : - -; Specify a unique path separator for the Signal Spy set of functions. -; The default will be to use the PathSeparator variable. -; Must not be the same character as DatasetSeparator. -; SignalSpyPathSeparator = / - -; Used to control parsing of HDL identifiers input to the tool. -; This includes CLI commands, vsim/vopt/vlog/vcom options, -; string arguments to FLI/VPI/DPI calls, etc. -; If set to 1, accept either Verilog escaped Id syntax or -; VHDL extended id syntax, regardless of source language. -; If set to 0, the syntax of the source language must be used. -; Each identifier in a hierarchical name may need different syntax, -; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or -; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" -; GenerousIdentifierParsing = 1 - -; Disable VHDL assertion messages -; IgnoreNote = 1 -; IgnoreWarning = 1 -; IgnoreError = 1 -; IgnoreFailure = 1 - -; Disable SystemVerilog assertion messages -; IgnoreSVAInfo = 1 -; IgnoreSVAWarning = 1 -; IgnoreSVAError = 1 -; IgnoreSVAFatal = 1 - -; Do not print any additional information from Severity System tasks. -; Only the message provided by the user is printed along with severity -; information. -; SVAPrintOnlyUserMessage = 1; - -; Default force kind. May be freeze, drive, deposit, or default -; or in other terms, fixed, wired, or charged. -; A value of "default" will use the signal kind to determine the -; force kind, drive for resolved signals, freeze for unresolved signals -; DefaultForceKind = freeze - -; Control the iteration of events when a VHDL signal is forced to a value -; This flag can be set to honour the signal update event in next iteration, -; the default is to update and propagate in the same iteration. -; ForceSigNextIter = 1 - -; Enable simulation statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; If zero, open files when elaborated; otherwise, open files on -; first read or write. Default is 0. -; DelayFileOpen = 1 - -; Control VHDL files opened for write. -; 0 = Buffered, 1 = Unbuffered -UnbufferedOutput = 0 - -; Control the number of VHDL files open concurrently. -; This number should always be less than the current ulimit -; setting for max file descriptors. -; 0 = unlimited -ConcurrentFileLimit = 40 - -; If nonzero, close files as soon as there is either an explicit call to -; file_close, or when the file variable's scope is closed. When zero, a -; file opened in append mode is not closed in case it is immediately -; reopened in append mode; otherwise, the file will be closed at the -; point it is reopened. -; AppendClose = 1 - -; Control the number of hierarchical regions displayed as -; part of a signal name shown in the Wave window. -; A value of zero tells VSIM to display the full name. -; The default is 0. -; WaveSignalNameWidth = 0 - -; Turn off warnings when changing VHDL constants and generics -; Default is 1 to generate warning messages -; WarnConstantChange = 0 - -; Turn off warnings from accelerated versions of the std_logic_arith, -; std_logic_unsigned, and std_logic_signed packages. -; StdArithNoWarnings = 1 - -; Turn off warnings from accelerated versions of the IEEE numeric_std -; and numeric_bit packages. -; NumericStdNoWarnings = 1 - -; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names -; in the design hierarchy. -; This style is controlled by the value of the GenerateFormat -; value described next. Default is to use new-style names, which -; comprise the generate statement label, '(', the value of the generate -; parameter, and a closing ')'. -; Set this to 1 to use old-style names. -; OldVhdlForGenNames = 1 - -; Control the format of the old-style VHDL FOR generate statement region -; name for each iteration. Do not quote the value. -; The format string here must contain the conversion codes %s and %d, -; in that order, and no other conversion codes. The %s represents -; the generate statement label; the %d represents the generate parameter value -; at a particular iteration (this is the position number if the generate parameter -; is of an enumeration type). Embedded whitespace is allowed (but discouraged); -; leading and trailing whitespace is ignored. -; Application of the format must result in a unique region name over all -; loop iterations for a particular immediately enclosing scope so that name -; lookup can function properly. The default is %s__%d. -; GenerateFormat = %s__%d - -; Enable more efficient logging of VHDL Variables. -; Logging VHDL variables without this enabled, while possible, is very -; inefficient. Enabling this will provide a more efficient logging methodology -; at the expense of more memory usage. By default this feature is disabled (0). -; To enabled this feature, set this variable to 1. -; VhdlVariableLogging = 1 - -; Enable logging of VHDL access type variables and their designated objects. -; This setting will allow both variables of an access type ("access variables") -; and their designated objects ("access objects") to be logged. Logging a -; variable of an access type will automatically also cause the designated -; object(s) of that variable to be logged as the simulation progresses. -; Further, enabling this allows access objects to be logged by name. By default -; this feature is disabled (0). To enable this feature, set this variable to 1. -; Enabling this will automatically enable the VhdlVariableLogging feature also. -; AccessObjDebug = 1 - -; Make each VHDL package in a PDU has its own separate copy of the package instead -; of sharing the package between PDUs. The default is to share packages. -; To ensure that each PDU has its own set of packages, set this variable to 1. -; VhdlSeparatePduPackage = 1 - -; Specify whether checkpoint files should be compressed. -; The default is 1 (compressed). -; CheckpointCompressMode = 0 - -; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. -; Use custom gcc compiler located at this path rather than the default path. -; The path should point directly at a compiler executable. -; DpiCppPath = /bin/gcc -; -; Specify the compiler version from the list of support GNU compilers. -; examples 4.7.4, 5.3.0, 7.4.0 -; DpiCppInstall = 7.4.0 - -; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. -; The term "out-of-the-blue" refers to SystemVerilog export function calls -; made from C functions that don't have the proper context setup -; (as is the case when running under "DPI-C" import functions). -; When this is enabled, one can call a DPI export function -; (but not task) from any C code. -; the setting of this variable can be one of the following values: -; 0 : dpioutoftheblue call is disabled (default) -; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. -; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. -; DpiOutOfTheBlue = 1 - -; Specify whether continuous assignments are run before other normal priority -; processes scheduled in the same iteration. This event ordering minimizes race -; differences between optimized and non-optimized designs, and is the default -; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set -; ImmediateContinuousAssign to 0. -; The default is 1 (enabled). -; ImmediateContinuousAssign = 0 - -; List of dynamically loaded objects for Verilog PLI applications -; Veriuser = veriuser.sl - -; Which default VPI object model should the tool conform to? -; The 1364 modes are Verilog-only, for backwards compatibility with older -; libraries, and SystemVerilog objects are not available in these modes. -; -; In the absence of a user-specified default, the tool default is the -; latest available LRM behavior. -; Options for PliCompatDefault are: -; VPI_COMPATIBILITY_VERSION_1364v1995 -; VPI_COMPATIBILITY_VERSION_1364v2001 -; VPI_COMPATIBILITY_VERSION_1364v2005 -; VPI_COMPATIBILITY_VERSION_1800v2005 -; VPI_COMPATIBILITY_VERSION_1800v2008 -; -; Synonyms for each string are also recognized: -; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) -; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) -; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) -; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) -; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) - - -; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 - -; Specify whether the Verilog system task $fopen or vpi_mcd_open() -; will create directories that do not exist when opening the file -; in "a" or "w" mode. -; The default is 0 (do not create non-existent directories) -; CreateDirForFileAccess = 1 - -; Specify default options for the restart command. Options can be one -; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions -; DefaultRestartOptions = -force - - -; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. -; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. -; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". -; The list of options must be delimited by commas, without spaces or tabs. -; -; Some examples -; To turn on all available UVM-aware debug features: -; UVMControl = all -; To turn on the struct window, mesage logging, and transaction logging: -; UVMControl = struct,msglog,trlog -; To turn on all options except certe: -; UVMControl = all,-certe -; To completely disable all UVM-aware debug functionality: -; UVMControl = disable - -; Specify the WildcardFilter setting. -; A space separated list of object types to be excluded when performing -; wildcard matches with log, wave, etc commands. The default value for this variable is: -; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" -; See "Using the WildcardFilter Preference Variable" in the documentation for -; details on how to use this variable and for descriptions of the filter types. -WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile - -; Specify the WildcardSizeThreshold setting. -; This integer setting specifies the size at which objects will be excluded when -; performing wildcard matches with log, wave, etc commands. Objects of size equal -; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard -; matches. The size is a simple calculation of number of bits or items in the object. -; The default value is 8k (8192). Setting this value to 0 will disable the checking -; of object size against this threshold and allow all objects of any size to be logged. -WildcardSizeThreshold = 8192 - -; Specify whether warning messages are output when objects are filtered out due to the -; WildcardSizeThreshold. The default is 0 (no messages generated). -WildcardSizeThresholdVerbose = 0 - -; Turn on (1) or off (0) WLF file compression. -; The default is 1 (compress WLF file). -; WLFCompress = 0 - -; Specify whether to save all design hierarchy (1) in the WLF file -; or only regions containing logged signals (0). -; The default is 0 (save only regions with logged signals). -; WLFSaveAllRegions = 1 - -; WLF file time limit. Limit WLF file by time, as closely as possible, -; to the specified amount of simulation time. When the limit is exceeded -; the earliest times get truncated from the file. -; If both time and size limits are specified the most restrictive is used. -; UserTimeUnits are used if time units are not specified. -; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} -; WLFTimeLimit = 0 - -; WLF file size limit. Limit WLF file size, as closely as possible, -; to the specified number of megabytes. If both time and size limits -; are specified then the most restrictive is used. -; The default is 0 (no limit). -; WLFSizeLimit = 1000 - -; Specify whether or not a WLF file should be deleted when the -; simulation ends. A value of 1 will cause the WLF file to be deleted. -; The default is 0 (do not delete WLF file when simulation ends). -; WLFDeleteOnQuit = 1 - -; Specify whether or not a WLF file should be optimized during -; simulation. If set to 0, the WLF file will not be optimized. -; The default is 1, optimize the WLF file. -; WLFOptimize = 0 - -; Specify the name of the WLF file. -; The default is vsim.wlf -; WLFFilename = vsim.wlf - -; Specify whether to lock the WLF file. -; Locking the file prevents other invocations of ModelSim/Questa tools from -; inadvertently overwriting the WLF file. -; The default is 1, lock the WLF file. -; WLFFileLock = 0 - -; Specify the update interval for the WLF file in live simulation. -; The interval is given in seconds. -; The value is the smallest interval between WLF file updates. The WLF file -; will be flushed (updated) after (at least) the interval has elapsed, ensuring -; that the data is correct when viewed from a separate viewer. -; A value of 0 means that no updating will occur. -; The default value is 10 seconds. -; WLFUpdateInterval = 10 - -; Specify the WLF cache size limit for WLF files. -; The value is given in megabytes. A value of 0 turns off the cache. -; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). -; On Windows, the default value is 1000 (megabytes) to help to avoid filling -; process memory. -; WLFSimCacheSize allows a different cache size to be set for a live simulation -; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize -; is not set, it defaults to the WLFCacheSize value. -; WLFCacheSize = 2000 -; WLFSimCacheSize = 500 - -; Specify the WLF file event collapse mode. -; 0 = Preserve all events and event order. (same as -wlfnocollapse) -; 1 = Only record values of logged objects at the end of a simulator iteration. -; (same as -wlfcollapsedelta) -; 2 = Only record values of logged objects at the end of a simulator time step. -; (same as -wlfcollapsetime) -; The default is 1. -; WLFCollapseMode = 0 - -; Specify whether WLF file logging can use threads on multi-processor machines. -; If 0, no threads will be used; if 1, threads will be used if the system has -; more than one processor. -; WLFUseThreads = 1 - -; Specify the size of objects that will trigger "large object" messages -; at log/wave/list time. The size calculation of the object is the same as that -; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. -; Setting LargeObjectSize to 0 will disable these messages. -; LargeObjectSize = 500000 - -; Specify the depth of stack frames returned by $stacktrace([level]). -; This depth will be picked up when the optional 'level' argument -; is not specified or its value is not a positive integer. -; StackTraceDepth = 100 - -; Turn on/off undebuggable SystemC type warnings. Default is on. -; ShowUndebuggableScTypeWarning = 0 - -; Turn on/off unassociated SystemC name warnings. Default is off. -; ShowUnassociatedScNameWarning = 1 - -; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. -; ScShowIeeeDeprecationWarnings = 1 - -; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. -; For SystemC-2.3.2 the valid values are 0,1 and 2 -; 0 = SC_SIGNAL_WRITE_CHECK_DISABLE_ -; 1 = SC_SIGNAL_WRITE_CHECK_DEFAULT_ -; 2 = SC_SIGNAL_WRITE_CHECK_CONFLICT_ -; For SystemC-2.2 the valid values are 0 and 1 -; 0 = DISABLE -; 1 = ENABLE -; ScEnableScSignalWriteCheck = 1 - -; Set SystemC default time unit. -; Set to fs, ps, ns, us, ms, or sec with optional -; prefix of 1, 10, or 100. The default is 1 ns. -; The ScTimeUnit value is honored if it is coarser than Resolution. -; If ScTimeUnit is finer than Resolution, it is set to the value -; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, -; then the default time unit will be 1 ns. However if Resolution -; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. -ScTimeUnit = ns - -; Set SystemC sc_main stack size. The stack size is set as an integer -; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or -; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends -; on the amount of data on the sc_main() stack and the memory required -; to succesfully execute the longest function call chain of sc_main(). -ScMainStackSize = 10 Mb - -; Set SystemC thread stack size. The stack size is set as an integer -; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or -; Gb(Giga-byte). The stack size for sc_thread depends -; on the amount of data on the sc_thread stack and the memory required -; to succesfully execute the thread. -; ScStackSize = 1 Mb - -; Turn on/off execution of remainder of sc_main upon quitting the current -; simulation session. If the cumulative length of sc_main() in terms of -; simulation time units is less than the length of the current simulation -; run upon quit or restart, sc_main() will be in the middle of execution. -; This switch gives the option to execute the remainder of sc_main upon -; quitting simulation. The drawback of not running sc_main till the end -; is memory leaks for objects created by sc_main. If on, the remainder of -; sc_main will be executed ignoring all delays. This may cause the simulator -; to crash if the code in sc_main is dependent on some simulation state. -; Default is on. -ScMainFinishOnQuit = 1 - -; Enable calling of the DPI export taks/functions from the -; SystemC start_of_simulation() callback. -; The default is off. -; EnableDpiSosCb = 1 - - -; Set the SCV relationship name that will be used to identify phase -; relations. If the name given to a transactor relation matches this -; name, the transactions involved will be treated as phase transactions -ScvPhaseRelationName = mti_phase - -; Customize the vsim kernel shutdown behavior at the end of the simulation. -; Some common causes of the end of simulation are $finish (implicit or explicit), -; sc_stop(), tf_dofinish(), and assertion failures. -; This should be set to "ask", "exit", or "stop". The default is "ask". -; "ask" -- In batch mode, the vsim kernel will abruptly exit. -; In GUI mode, a dialog box will pop up and ask for user confirmation -; whether or not to quit the simulation. -; "stop" -- Cause the simulation to stay loaded in memory. This can make some -; post-simulation tasks easier. -; "exit" -- The simulation will abruptly exit without asking for any confirmation. -; "final" -- Run SystemVerilog final blocks then behave as "stop". -; Note: This variable can be overridden with the vsim "-onfinish" command line switch. -OnFinish = ask - -; Print pending deferred assertion messages. -; Deferred assertion messages may be scheduled after the $finish in the same -; time step. Deferred assertions scheduled to print after the $finish are -; printed before exiting with severity level NOTE since it's not known whether -; the assertion is still valid due to being printed in the active region -; instead of the reactive region where they are normally printed. -; OnFinishPendingAssert = 1; - -; Print "simstats" result. Default is 0. -; 0 == do not print simstats -; 1 == print at end of simulation -; 2 == print at end of each run command and end of simulation -; PrintSimStats = 1 - -; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages -; AssertFile = assert.log - -; Enable assertion counts. Default is off. -; AssertionCounts = 1 - -; Run simulator in assertion debug mode. Default is off. -; AssertionDebug = 1 - -; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. -; AssertionEnable = 0 - -; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. -; Any positive integer, -1 for infinity. -; AssertionLimit = 1 - -; Turn on/off concurrent assertion pass log. Default is off. -; Assertion pass logging is only enabled when assertion is browseable -; and assertion debug is enabled. -; AssertionPassLog = 1 - -; Turn on/off PSL concurrent assertion fail log. Default is on. -; The flag does not affect SVA -; AssertionFailLog = 0 - -; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. -; AssertionFailLocalVarLog = 0 - -; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. -; 0 = Continue 1 = Break 2 = Exit -; AssertionFailAction = 1 - -; Enable the active thread monitor in the waveform display when assertion debug is enabled. -; AssertionActiveThreadMonitor = 1 - -; Control how many waveform rows will be used for displaying the active threads. Default is 5. -; AssertionActiveThreadMonitorLimit = 5 - -; Assertion thread limit after which assertion would be killed/switched off. -; The default is -1 (unlimited). If the number of threads for an assertion go -; beyond this limit, the assertion would be either switched off or killed. This -; limit applies to only assert directives. -;AssertionThreadLimit = -1 - -; Action to be taken once the assertion thread limit is reached. Default -; is kill. It can have a value of off or kill. In case of kill, all the existing -; threads are terminated and no new attempts are started. In case of off, the -; existing attempts keep on evaluating but no new attempts are started. This -; variable applies to only assert directives. -;AssertionThreadLimitAction = kill - -; Cover thread limit after which cover would be killed/switched off. -; The default is -1 (unlimited). If the number of threads for a cover go -; beyond this limit, the cover would be either switched off or killed. This -; limit applies to only cover directives. -;CoverThreadLimit = -1 - -; Action to be taken once the cover thread limit is reached. Default -; is kill. It can have a value of off or kill. In case of kill, all the existing -; threads are terminated and no new attempts are started. In case of off, the -; existing attempts keep on evaluating but no new attempts are started. This -; variable applies to only cover directives. -;CoverThreadLimitAction = kill - - -; By default immediate assertions do not participate in Assertion Coverage calculations -; unless they are executed. This switch causes all immediate assertions in the design -; to participate in Assertion Coverage calculations, whether attempted or not. -; UnattemptedImmediateAssertions = 0 - -; By default immediate covers participate in Coverage calculations -; whether they are attempted or not. This switch causes all unattempted -; immediate covers in the design to stop participating in Coverage -; calculations. -; UnattemptedImmediateCovers = 0 - -; By default pass action block is not executed for assertions on vacuous -; success. The following variable is provided to enable execution of -; pass action block on vacuous success. The following variable is only effective -; if the user does not disable pass action block execution by using either -; system tasks or CLI. Also there is a performance penalty for enabling -; the following variable. -;AssertionEnableVacuousPassActionBlock = 1 - -; As per strict 1850-2005 PSL LRM, an always property can either pass -; or fail. However, by default, Questa reports multiple passes and -; multiple fails on top always/never property (always/never operator -; is the top operator under Verification Directive). The reason -; being that Questa reports passes and fails on per attempt of the -; top always/never property. Use the following flag to instruct -; Questa to strictly follow LRM. With this flag, all assert/never -; directives will start an attempt once at start of simulation. -; The attempt can either fail, match or match vacuously. -; For e.g. if always is the top operator under assert, the always will -; keep on checking the property at every clock. If the property under -; always fails, the directive will be considered failed and no more -; checking will be done for that directive. A top always property, -; if it does not fail, will show a pass at end of simulation. -; The default value is '0' (i.e. zero is off). For example: -; PslOneAttempt = 1 - -; Specify the number of clock ticks to represent infinite clock ticks. -; This affects eventually!, until! and until_!. If at End of Simulation -; (EOS) an active strong-property has not clocked this number of -; clock ticks then neither pass or fail (vacuous match) is returned -; else respective fail/pass is returned. The default value is '0' (zero) -; which effectively does not check for clock tick condition. For example: -; PslInfinityThreshold = 5000 - -; Control how many thread start times will be preserved for ATV viewing for a given assertion -; instance. Default is -1 (ALL). -; ATVStartTimeKeepCount = -1 - -; Turn on/off code coverage -; CodeCoverage = 0 - -; This option applies to condition and expression coverage UDP tables. It -; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. -; If this option is used and a match occurs in more than one row in the UDP table, -; none of the counts for all matching rows is incremented. By default, counts are -; incremented for all matching rows. -; CoverCountAll = 1 - -; Turn off automatic inclusion of VHDL integers in toggle coverage. Default -; is to include them. -; ToggleNoIntegers = 1 - -; Set the maximum number of values that are collected for toggle coverage of -; VHDL integers. Default is 100; -; ToggleMaxIntValues = 100 - -; Set the maximum number of values that are collected for toggle coverage of -; Verilog real. Default is 100; -; ToggleMaxRealValues = 100 - -; Turn on automatic inclusion of Verilog integers in toggle coverage, except -; for enumeration types. Default is to include them. -; ToggleVlogIntegers = 0 - -; Turn on automatic inclusion of Verilog real type in toggle coverage, except -; for shortreal types. Default is to not include them. -; ToggleVlogReal = 1 - -; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays -; and VHDL arrays-of-arrays in toggle coverage. -; Default is to not include them. -; ToggleFixedSizeArray = 1 - -; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, -; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. -; This leads to a longer simulation time with bigger arrays covered with toggle coverage. -; Default is 1024. -; ToggleMaxFixedSizeArray = 1024 - -; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized -; one-dimensional packed vectors for toggle coverage. Default is 0. -; TogglePackedAsVec = 0 - -; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for -; toggle coverage. Default is 0. -; ToggleVlogEnumBits = 0 - -; Turn off automatic inclusion of VHDL records in toggle coverage. -; Default is to include them. -; ToggleVHDLRecords = 0 - -; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. -; For unlimited width, set to 0. -; ToggleWidthLimit = 128 - -; Limit the counts that are tracked for toggle coverage. When all edges for a bit have -; reached this count, further activity on the bit is ignored. Default is 1. -; For unlimited counts, set to 0. -; ToggleCountLimit = 1 - -; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. -; Following is the toggle coverage calculation criteria based on extended toggle mode: -; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). -; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. -; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. -; ExtendedToggleMode = 3 - -; Enable toggle statistics collection only for ports. Default is 0. -; TogglePortsOnly = 1 - -; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has -; reached this count, further tracking of the input patterns linked to it is ignored. -; Default is 1. For unlimited counts, set to 0. -; NOTE: Changing this value from its default value may affect simulation performance. -; FecCountLimit = 1 - -; Limit the counts that are tracked for UDP Coverage. When a bin has -; reached this count, further tracking of the input patterns linked to it is ignored. -; Default is 1. For unlimited counts, set to 0. -; NOTE: Changing this value from its default value may affect simulation performance. -; UdpCountLimit = 1 - -; Control toggle coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either -; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; ToggleDeglitchPeriod = 10.0ps - -; Turn on/off all PSL/SVA cover directive enables. Default is on. -; CoverEnable = 0 - -; Turn on/off PSL/SVA cover log. Default is off "0". -; CoverLog = 1 - -; Set "at_least" value for all PSL/SVA cover directives. Default is 1. -; CoverAtLeast = 2 - -; Set "limit" value for all PSL/SVA cover directives. Default is -1. -; Any positive integer, -1 for infinity. -; CoverLimit = 1 - -; Specify the coverage database filename. -; Default is "" (i.e. database is NOT automatically saved on close). -; UCDBFilename = vsim.ucdb - -; Specify the maximum limit for the number of Cross (bin) products reported -; in XML and UCDB report against a Cross. A warning is issued if the limit -; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this -; setting. -; MaxReportRhsSVCrossProducts = 1000 - -; Specify the override for the "auto_bin_max" option for the Covergroups. -; If not specified then value from Covergroup "option" is used. -; SVCoverpointAutoBinMax = 64 - -; Specify the override for the value of "cross_num_print_missing" -; option for the Cross in Covergroups. If not specified then value -; specified in the "option.cross_num_print_missing" is used. This -; is a runtime option. NOTE: This overrides any "cross_num_print_missing" -; value specified by user in source file and any SVCrossNumPrintMissingDefault -; specified in modelsim.ini. -; SVCrossNumPrintMissing = 0 - -; Specify whether to use the value of "cross_num_print_missing" -; option in report and GUI for the Cross in Covergroups. If not specified then -; cross_num_print_missing is ignored for creating reports and displaying -; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". -; UseSVCrossNumPrintMissing = 0 - -; Specify the threshold of Coverpoint wildcard bin value range size, above which -; a warning will be triggered. The default is 4K -- 12 wildcard bits. -; SVCoverpointWildCardBinValueSizeWarn = 4096 - -; Specify the override for the value of "strobe" option for the -; Covergroup Type. If not specified then value in "type_option.strobe" -; will be used. This is runtime option which forces "strobe" to -; user specified value and supersedes user specified values in the -; SystemVerilog Code. NOTE: This also overrides the compile time -; default value override specified using "SVCovergroupStrobeDefault" -; SVCovergroupStrobe = 0 - -; Override for explicit assignments in source code to "option.goal" of -; SystemVerilog covergroup, coverpoint, and cross. It also overrides the -; default value of "option.goal" (defined to be 100 in the SystemVerilog -; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". -; SVCovergroupGoal = 100 - -; Override for explicit assignments in source code to "type_option.goal" of -; SystemVerilog covergroup, coverpoint, and cross. It also overrides the -; default value of "type_option.goal" (defined to be 100 in the SystemVerilog -; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". -; SVCovergroupTypeGoal = 100 - -; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() -; builtin functions, and report. This setting changes the default values of -; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 -; behavior if explicit assignments are not made on option.get_inst_coverage and -; type_option.merge_instances by the user. There are two vsim command line -; options, -cvg63 and -nocvg63 to override this setting from vsim command line. -; The default value of this variable from release 6.6 onwards is 0. This default -; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. -; SVCovergroup63Compatibility = 0 - -; Enforce the default behavior of covergroup get_coverage() builtin function, GUI -; and report. This variable sets the default value of type_option.merge_instances. -; There are two vsim command line options, -cvgmergeinstances and -; -nocvgmergeinstances to override this setting from vsim command line. -; The default value of this variable, -1 (don't care), allows the tool to determine -; the effective value, based on factors related to capacity and optimization. -; The type_option.merge_instances appears in the GUI and coverage reports as either -; auto(1) or auto(0), depending on whether the effective value was determined to -; be a 1 or a 0. -; SVCovergroupMergeInstancesDefault = -1 - -; Enable or disable generation of more detailed information about the sampling -; of covergroup, cross, and coverpoints. It provides the details of the number -; of times the covergroup instance and type were sampled, as well as details -; about why covergroup, cross and coverpoint were not covered. A non-zero value -; is to enable this feature. 0 is to disable this feature. Default is 0 -; SVCovergroupSampleInfo = 0 - -; Specify the maximum number of Coverpoint bins in whole design for -; all Covergroups. -; MaxSVCoverpointBinsDesign = 2147483648 - -; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins -; MaxSVCoverpointBinsInst = 1048576 - -; Specify the maximum number of Cross bins in whole design for -; all Covergroups. -; MaxSVCrossBinsDesign = 2147483648 - -; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins -; MaxSVCrossBinsInst = 67108864 - -; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. -; By default, this variable is set 0, in which case option.no_collect setting will take effect. -; If this variable is set to 1, all zero-weight coverage items will not be saved. -; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting -; of this variable. -; CvgZWNoCollect = 1 - -; Specify a space delimited list of double quoted TCL style -; regular expressions which will be matched against the text of all messages. -; If any regular expression is found to be contained within any message, the -; status for that message will not be propagated to the UCDB TESTSTATUS. -; If no match is detected, then the status will be propagated to the -; UCDB TESTSTATUS. More than one such regular expression text is allowed, -; and each message text is compared for each regular expression in the list. -; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" - -; Set weight for all PSL/SVA cover directives. Default is 1. -; CoverWeight = 2 - -; Check vsim plusargs. Default is 0 (off). -; 0 = Don't check plusargs -; 1 = Warning on unrecognized plusarg -; 2 = Error and exit on unrecognized plusarg -; CheckPlusargs = 1 - -; Load the specified shared objects with the RTLD_GLOBAL flag. -; This gives global visibility to all symbols in the shared objects, -; meaning that subsequently loaded shared objects can bind to symbols -; in the global shared objects. The list of shared objects should -; be whitespace delimited. This option is not supported on the -; Windows or AIX platforms. -; GlobalSharedObjectList = example1.so example2.so example3.so - -; Generate the stub definitions for the undefined symbols in the shared libraries being -; loaded in the simulation. When this flow is turned on, the undefined symbols will not -; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. -; The valid arguments are: on, off, verbose. -; on : turn on the automatic generation of stub definitions. -; off: turn off the flow. The undefined symbols will trigger an immediate load failure. -; verbose: Turn on the flow and report the undefined symbols for each shared library. -; NOTE: This variable can be overriden with vsim switch "-undefsyms". -; The default is on. -; -; UndefSyms = off - -; Enable the support for checkpointing foreign C/C++ libraries. -; The valid arguments are: 0, 1, 2 -; 0: off (default) -; 1: on (manually save/restore user shared library data) -; 2: auto (automatically save/restore user shared library data) -; This option is not supported on the Windows platforms. -; -; AllowCheckpointCpp = 2 - -; Initial seed for the random number generator of the root thread (SystemVerilog). -; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. -; The default value is 0. -; Sv_Seed = 0 - -; Specify the solver "engine" that vsim will select for constrained random -; generation. -; Valid values are: -; "auto" - automatically select the best engine for the current -; constraint scenario -; "bdd" - evaluate all constraint scenarios using the BDD solver engine -; "act" - evaluate all constraint scenarios using the ACT solver engine -; While the BDD solver engine is generally efficient with constraint scenarios -; involving bitwise logical relationships, the ACT solver engine can exhibit -; superior performance with constraint scenarios involving large numbers of -; random variables related via arithmetic operators (+, *, etc). -; NOTE: This variable can be overridden with the vsim "-solveengine" command -; line switch. -; The default value is "auto". -; SolveEngine = auto - -; Specifies the maximum size that a dynamic array may be resized to by the -; solver. If the solver attempts to resize a dynamic array to a size greater -; than the specified limit, the solver will abort with an error. -; The default value is 10000. A value of 0 indicates no limit. -; SolveArrayResizeMax = 10000 - -; Specify error message severity when randomize() and randomize(null) failures -; are detected. -; -; Integer value up to two digits are allowed with each digit having the following legal values: -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; -; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents -; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit) -; represents the setting for randomize(null) calls. -; -; 2) When a single digit value is used, the setting is applied to both normal randomize() call -; and randomize(null) call. -; -; Example: Fatal error for randomize() failures and NO error for randomize(null) failures -; -solvefailseverity=40 -; -; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is -; enabled, a constraint contradiction report will be displayed for randomize() calls that -; have a message severity >= warning (i.e. constraint contradiction reports will not be -; generated for randomize() calls having a "no error" severity level) -; -; NOTE: This variable can be overridden with the vsim "-solvefailseverity" command -; line switch. -; -; The default is 1 (warning). -; SolveFailSeverity = 1 - -; Error message severity for suppressible errors that are detected in a -; solve/before constraint. -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" -; command line switch. -; The default is 3 (failure). -; SolveBeforeErrorSeverity = 3 - -; Error message severity for suppressible errors that are related to -; solve engine capacity limits -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" -; command line switch. -; The default is 3 (failure). -; SolveEngineErrorSeverity = 3 - -; Enable/disable constraint conflicts on randomize() failure -; Valid values: -; 0 - disable solvefaildebug -; 1 - basic debug (no performance penalty) -; 2 - enhanced debug (runtime performance penalty) -; -; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is -; enabled, a constraint contradiction report will be displayed for randomize() calls that -; have a message severity >= warning (i.e. constraint contradiction reports will not be -; generated for randomize() calls having a "no error" severity level) -; -; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command -; line switch. -; -; The default is 1 (basic debug). -; SolveFailDebug = 1 - -; Upon encountering a randomize() failure, generate a simplified testcase that -; will reproduce the failure. Optionally output the testcase to a file. -; Testcases for 'no-solution' failures will only be produced if SolveFailDebug -; is enabled (see above). -; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" -; command line switch. -; The default is OFF (do not generate a testcase). To enable testcase -; generation, uncomment this variable. To redirect testcase generation to a -; file, specify the name of the output file. -; SolveFailTestcase = - -; Specify solver timeout threshold (in seconds). randomize() will fail if the -; CPU time required to evaluate any randset exceeds the specified timeout. -; The default value is 500. A value of 0 will disable timeout failures. -; SolveTimeout = 500 - -; Specify the alternative behavior during solver replay. Must be used when combined with -solvereplay switch. -; SolveReplayOpt=[+|-][,[+|-]]*" -' Valid settings: -; validate : toggle the checking of value changes of non-random variables involved in randomize(). (default is off)" -; SolveReplayOpt=validate - -; Specify the maximum size of the solution graph generated by the BDD solver. -; This value can be used to force the BDD solver to abort the evaluation of a -; complex constraint scenario that cannot be evaluated with finite memory. -; This value is specified in 1000s of nodes. -; The default value is 10000. A value of 0 indicates no limit. -; SolveGraphMaxSize = 10000 - -; Specify the maximum number of evaluations that may be performed on the -; solution graph by the BDD solver. This value can be used to force the BDD -; solver to abort the evaluation of a complex constraint scenario that cannot -; be evaluated in finite time. This value is specified in 10000s of evaluations. -; The default value is 10000. A value of 0 indicates no limit. -; SolveGraphMaxEval = 10000 - -; Specify random sequence compatiblity with a prior release. This -; option is used to get the same random sequences during simulation as -; as a prior release. Only prior releases with the same major version -; as the current release are allowed. -; NOTE: Only those random sequence changes due to solver optimizations are -; reverted by this variable. Random sequence changes due to solver bugfixes -; cannot be un-done. -; NOTE: This variable can be overridden with the vsim "-solverev" command -; line switch. -; Default value set to "" (no compatibility). -; SolveRev = - -; Environment variable expansion of command line arguments has been depricated -; in favor shell level expansion. Universal environment variable expansion -; inside -f files is support and continued support for MGC Location Maps provide -; alternative methods for handling flexible pathnames. -; The following line may be uncommented and the value set to 1 to re-enable this -; deprecated behavior. The default value is 0. -; DeprecatedEnvironmentVariableExpansion = 0 - -; Specify the memory threshold for the System Verilog garbage collector. -; The value is the number of megabytes of class objects that must accumulate -; before the garbage collector is run. -; The GCThreshold setting is used when class debug mode is disabled to allow -; less frequent garbage collection and better simulation performance. -; The GCThresholdClassDebug setting is used when class debug mode is enabled -; to allow for more frequent garbage collection. -; GCThreshold = 100 -; GCThresholdClassDebug = 5 - -; Turn on/off collapsing of bus ports in VCD dumpports output -DumpportsCollapse = 1 - -; Location of Multi-Level Verification Component (MVC) installation. -; The default location is the product installation directory. -MvcHome = $QUESTA_MVC_HOME - -; Location of InFact installation. The default is $MODEL_TECH/../../infact -; -; InFactHome = $MODEL_TECH/../../infact - -; Initialize SystemVerilog enums using the base type's default value -; instead of the leftmost value. -; EnumBaseInit = 1 - -; Suppress file type registration. -; SuppressFileTypeReg = 1 - -; Enable/disable non-LRM compliant SystemVerilog language extensions. -; Valid extensions are: -; altdpiheader - Alternative style function signature generated in DPI header", -; cfce - generate an error if $cast fails as a function -; cfmt - C like formatting for specifiers with '#' prefix ('%#x', '%#h') -; dfsp - sets default format specifier as %p, if no format specifier is given for unpacked array in $display and related systasks -; expdfmt - enable format string extensions for $display/$sformatf -; extscan - support values greater than 32 bit for string builtin methods (atohex, atobin, atooct, atoi) -; fmtcap - prints capital hex digits with %X/%H in display calls -; iddp - ignore DPI disable protocol check -; lfmt - zero-pad data if '0' prefixes width in format specifier (e.g. "%04h") -; noexptc - ignore DPI export type name overloading check -; realrand - support randomize() with real variables and constraints (Default) -; SvExtensions = [+|-][,[+|-]*] - -; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions. -; Valid extensions are: -; arraymode - consider rand_mode of unpacked array field independently from its elements -; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles (Default) -; funcback - enable function backtracking (ACT only) -; genmodseedfix - enable LRM-compliant seeding of module/interface instances under for-generate blocks (Default) -; nodist - interpret 'dist' constraint as 'inside' (ACT only) -; noorder - ignore solve/before ordering constraints (ACT only) -; pathseed - enable unique seeding of module instances based on hierarchical path name -; prerandfirst - execute all pre_randomize() functions before evaluating any constraints -; promotedist - promote priority of 'dist' constraint if LHS has no solve/before -; purecheck - suppress pre_randomize() and post_randomize() calls for randomize(null) -; randindex - allow random index in constraint (Default) -; randstruct - consider all fields of unpacked structs as 'rand' -; skew - skew randomize results (ACT only) -; strictstab - strict random stability -; SvRandExtensions = [+|-][,[+|-]*] - -; Controls the formatting of '%p' and '%P' conversion specification, used in $display -; and similar system tasks. -; 1. SVPrettyPrintFlags=I use spaces(S) or tabs(T) per indentation level. -; The 'I' flag when present causes relevant data types to be expanded and indented into -; a more readable format. -; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). -; 2. SVPrettyPrintFlags=L limits the output to lines. -; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). -; 3. SVPrettyPrintFlags=C limits the output to characters. -; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). -; 4. SVPrettyPrintFlags=F limits the output to of relevant datatypes -; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). -; 5. SVPrettyPrintFlags=E limits the output to of relevant datatypes -; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). -; 6. SVPrettyPrintFlags=D suppresses the output of sub-elements below . -; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). -; 7. SVPrettyPrintFlags=R shows the output of specifier %p as per the specifed radix. -; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)). -; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format. -; 8. Items 1-7 above can be combined as a comma separated list. -; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb) -; SVPrettyPrintFlags=I4S - -[lmc] -; The simulator's interface to Logic Modeling's SmartModel SWIFT software -libsm = $MODEL_TECH/libsm.sl -; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) -; libsm = $MODEL_TECH/libsm.dll -; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) -; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl -; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) -; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o -; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) -; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so -; Logic Modeling's SmartModel SWIFT software (Windows NT) -; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll -; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) -; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so -; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) -; libswift = $LMC_HOME/lib/linux.lib/libswift.so - -; The simulator's interface to Logic Modeling's hardware modeler SFI software -libhm = $MODEL_TECH/libhm.sl -; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) -; libhm = $MODEL_TECH/libhm.dll -; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) -; libsfi = /lib/hp700/libsfi.sl -; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) -; libsfi = /lib/rs6000/libsfi.a -; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) -; libsfi = /lib/sun4.solaris/libsfi.so -; Logic Modeling's hardware modeler SFI software (Windows NT) -; libsfi = /lib/pcnt/lm_sfi.dll -; Logic Modeling's hardware modeler SFI software (Linux) -; libsfi = /lib/linux/libsfi.so - -[msg_system] -; Change a message severity or suppress a message. -; The format is: = [,...] -; suppress can be used to achieve +nowarn functionality -; The format is: suppress = ,,[,,...] -; Examples: -suppress = 8780 ;an explanation can be had by running: verror 8780 -; note = 3009 -; warning = 3033 -; error = 3010,3016 -; fatal = 3016,3033 -; suppress = 3009,3016,3601 -; suppress = 3009,CNNODP,3601,TFMPC -; suppress = 8683,8684 -; The command verror can be used to get the complete -; description of a message. - -; Control transcripting of Verilog display system task messages and -; PLI/FLI print function call messages. The system tasks include -; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They -; also include the analogous file I/O tasks that write to STDOUT -; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, -; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default -; is to have messages appear only in the transcript. The other -; settings are to send messages to the wlf file only (messages that -; are recorded in the wlf file can be viewed in the MsgViewer) or -; to both the transcript and the wlf file. The valid values are -; tran {transcript only (default)} -; wlf {wlf file only} -; both {transcript and wlf file} -; displaymsgmode = tran - -; Control transcripting of elaboration/runtime messages not -; addressed by the displaymsgmode setting. The default is to -; have messages appear only in the transcript. The other settings -; are to send messages to the wlf file only (messages that are -; recorded in the wlf file can be viewed in the MsgViewer) or to both -; the transcript and the wlf file. The valid values are -; tran {transcript only (default)} -; wlf {wlf file only} -; both {transcript and wlf file} -; msgmode = tran - -; Controls number of displays of a particluar message -; default value is 5 -; MsgLimitCount = 5 - -[utils] -; Default Library Type (while creating a library with "vlib") -; 0 - legacy library using subdirectories for design units -; 2 - flat library -; DefaultLibType = 2 - -; Flat Library Page Size (while creating a library with "vlib") -; Set the size in bytes for flat library file pages. Libraries containing -; very large files may benefit from a larger value. -; FlatLibPageSize = 8192 - -; Flat Library Page Cleanup Percentage (while creating a library with "vlib") -; Set the percentage of total pages deleted before library cleanup can occur. -; This setting is applied together with FlatLibPageDeleteThreshold. -; FlatLibPageDeletePercentage = 50 - -; Flat Library Page Cleanup Threshold (while creating a library with "vlib") -; Set the number of pages deleted before library cleanup can occur. -; This setting is applied together with FlatLibPageDeletePercentage. -; FlatLibPageDeleteThreshold = 1000 - - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/selectio_lvds_rx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/selectio_lvds_rx.sh deleted file mode 100644 index 55348d69..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/selectio_lvds_rx.sh +++ /dev/null @@ -1,167 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : selectio_lvds_rx.sh -# Simulator : Mentor Graphics ModelSim Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sun Mar 19 18:25:33 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: selectio_lvds_rx.sh [-help] -# usage: selectio_lvds_rx.sh [-lib_map_path] -# usage: selectio_lvds_rx.sh [-noclean_files] -# usage: selectio_lvds_rx.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'selectio_lvds_rx.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "selectio_lvds_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - vsim -64 -c -do "do {simulate.do}" -l simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_rx.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Copy modelsim.ini file -copy_setup_file() -{ - file="modelsim.ini" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - else - lib_map_path="C:/Mentor/CompLib/2019.1.3" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - cp $src_file . - fi -} - -# Create design library directory -create_lib_dir() -{ - lib_dir="modelsim_lib" - if [[ -e $lib_dir ]]; then - rm -rf $lib_dir - fi - - mkdir $lib_dir - -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_rx.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: selectio_lvds_rx.sh [-help]\n\ -Usage: selectio_lvds_rx.sh [-lib_map_path]\n\ -Usage: selectio_lvds_rx.sh [-reset_run]\n\ -Usage: selectio_lvds_rx.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/selectio_lvds_rx.udo b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/selectio_lvds_rx.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/simulate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/simulate.do deleted file mode 100644 index 54b4f399..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/simulate.do +++ /dev/null @@ -1,16 +0,0 @@ -onbreak {quit -f} -onerror {quit -f} - -vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.selectio_lvds_rx xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure -view signals - -do {selectio_lvds_rx.udo} - -run -all - -quit -force diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/wave.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/README.txt deleted file mode 100644 index 8965a407..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun Mar 19 18:25:33 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./selectio_lvds_rx.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './selectio_lvds_rx.sh' script. - -./selectio_lvds_rx.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./selectio_lvds_rx.sh -noclean_files - -For more information on the script, please type './selectio_lvds_rx.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/compile.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/compile.do deleted file mode 100644 index 13ea6452..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/compile.do +++ /dev/null @@ -1,23 +0,0 @@ -vlib questa_lib/work -vlib questa_lib/msim - -vlib questa_lib/msim/xil_defaultlib -vlib questa_lib/msim/xpm - -vmap xil_defaultlib questa_lib/msim/xil_defaultlib -vmap xpm questa_lib/msim/xpm - -vlog -work xil_defaultlib -64 -sv \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -64 -93 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work xil_defaultlib -64 \ -"../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v" \ -"../../../ip/selectio_lvds_rx/selectio_lvds_rx.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/elaborate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/elaborate.do deleted file mode 100644 index adb32e30..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/elaborate.do +++ /dev/null @@ -1 +0,0 @@ -vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.selectio_lvds_rx xil_defaultlib.glbl -o selectio_lvds_rx_opt diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/file_info.txt deleted file mode 100644 index 6d7cb2d8..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -selectio_lvds_rx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v, -selectio_lvds_rx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/selectio_lvds_rx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/selectio_lvds_rx.sh deleted file mode 100644 index 82f66dff..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/selectio_lvds_rx.sh +++ /dev/null @@ -1,174 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : selectio_lvds_rx.sh -# Simulator : Mentor Graphics Questa Advanced Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sun Mar 19 18:25:33 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: selectio_lvds_rx.sh [-help] -# usage: selectio_lvds_rx.sh [-lib_map_path] -# usage: selectio_lvds_rx.sh [-noclean_files] -# usage: selectio_lvds_rx.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'selectio_lvds_rx.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "selectio_lvds_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -elaborate() -{ - source elaborate.do 2>&1 | tee -a elaborate.log -} - -# RUN_STEP: -simulate() -{ - vsim -64 -c -do "do {simulate.do}" -l simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_rx.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Copy modelsim.ini file -copy_setup_file() -{ - file="modelsim.ini" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - else - lib_map_path="D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - cp $src_file . - fi -} - -# Create design library directory -create_lib_dir() -{ - lib_dir="questa_lib" - if [[ -e $lib_dir ]]; then - rm -rf $lib_dir - fi - - mkdir $lib_dir - -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_rx.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: selectio_lvds_rx.sh [-help]\n\ -Usage: selectio_lvds_rx.sh [-lib_map_path]\n\ -Usage: selectio_lvds_rx.sh [-reset_run]\n\ -Usage: selectio_lvds_rx.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/selectio_lvds_rx.udo b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/selectio_lvds_rx.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/simulate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/simulate.do deleted file mode 100644 index 9839c78f..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/simulate.do +++ /dev/null @@ -1,16 +0,0 @@ -onbreak {quit -f} -onerror {quit -f} - -vsim -t 1ps -lib xil_defaultlib selectio_lvds_rx_opt - -do {wave.do} - -view wave -view structure -view signals - -do {selectio_lvds_rx.udo} - -run -all - -quit -force diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/wave.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/README.txt deleted file mode 100644 index 8965a407..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun Mar 19 18:25:33 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./selectio_lvds_rx.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './selectio_lvds_rx.sh' script. - -./selectio_lvds_rx.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./selectio_lvds_rx.sh -noclean_files - -For more information on the script, please type './selectio_lvds_rx.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/compile.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/compile.do deleted file mode 100644 index 704d2832..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/compile.do +++ /dev/null @@ -1,23 +0,0 @@ -vlib work -vlib riviera - -vlib riviera/xil_defaultlib -vlib riviera/xpm - -vmap xil_defaultlib riviera/xil_defaultlib -vmap xpm riviera/xpm - -vlog -work xil_defaultlib -sv2k12 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -93 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work xil_defaultlib -v2k5 \ -"../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v" \ -"../../../ip/selectio_lvds_rx/selectio_lvds_rx.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/file_info.txt deleted file mode 100644 index 6d7cb2d8..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -selectio_lvds_rx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v, -selectio_lvds_rx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/selectio_lvds_rx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/selectio_lvds_rx.sh deleted file mode 100644 index eb0c64ea..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/selectio_lvds_rx.sh +++ /dev/null @@ -1,153 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : selectio_lvds_rx.sh -# Simulator : Aldec Riviera-PRO Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sun Mar 19 18:25:33 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: selectio_lvds_rx.sh [-help] -# usage: selectio_lvds_rx.sh [-lib_map_path] -# usage: selectio_lvds_rx.sh [-noclean_files] -# usage: selectio_lvds_rx.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'selectio_lvds_rx.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "selectio_lvds_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - runvsimsa -l simulate.log -do "do {simulate.do}" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_rx.sh -help\" for more information)\n" - exit 1 - fi - map_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - map_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Map library.cfg file -map_setup_file() -{ - file="library.cfg" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - else - lib_map_path="D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - vmap -link $lib_map_path - fi - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_rx.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: selectio_lvds_rx.sh [-help]\n\ -Usage: selectio_lvds_rx.sh [-lib_map_path]\n\ -Usage: selectio_lvds_rx.sh [-reset_run]\n\ -Usage: selectio_lvds_rx.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/selectio_lvds_rx.udo b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/selectio_lvds_rx.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/simulate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/simulate.do deleted file mode 100644 index 1232b429..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/simulate.do +++ /dev/null @@ -1,17 +0,0 @@ -onbreak {quit -force} -onerror {quit -force} - -asim -t 1ps +access +r +m+selectio_lvds_rx -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.selectio_lvds_rx xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure - -do {selectio_lvds_rx.udo} - -run -all - -endsim - -quit -force diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/wave.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/README.txt deleted file mode 100644 index 8965a407..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun Mar 19 18:25:33 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./selectio_lvds_rx.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './selectio_lvds_rx.sh' script. - -./selectio_lvds_rx.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./selectio_lvds_rx.sh -noclean_files - -For more information on the script, please type './selectio_lvds_rx.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/file_info.txt deleted file mode 100644 index 6d7cb2d8..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -selectio_lvds_rx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v, -selectio_lvds_rx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/selectio_lvds_rx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/selectio_lvds_rx.sh deleted file mode 100644 index b2505305..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/selectio_lvds_rx.sh +++ /dev/null @@ -1,230 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : selectio_lvds_rx.sh -# Simulator : Synopsys Verilog Compiler Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sun Mar 19 18:25:33 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: selectio_lvds_rx.sh [-help] -# usage: selectio_lvds_rx.sh [-lib_map_path] -# usage: selectio_lvds_rx.sh [-noclean_files] -# usage: selectio_lvds_rx.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'selectio_lvds_rx.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Command line options -vlogan_opts="-full64" -vhdlan_opts="-full64" -vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" -vcs_sim_opts="-ucli -licqueue -l simulate.log" - -# Design libraries -design_libs=(xil_defaultlib xpm) - -# Simulation root library directory -sim_lib_dir="vcs_lib" - -# Script info -echo -e "selectio_lvds_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - vlogan -work xil_defaultlib $vlogan_opts -sverilog \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - 2>&1 | tee -a vlogan.log - - vhdlan -work xpm $vhdlan_opts \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - 2>&1 | tee -a vhdlan.log - - vlogan -work xil_defaultlib $vlogan_opts +v2k \ - "$ref_dir/../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v" \ - "$ref_dir/../../../ip/selectio_lvds_rx/selectio_lvds_rx.v" \ - 2>&1 | tee -a vlogan.log - - - vlogan -work xil_defaultlib $vlogan_opts +v2k \ - glbl.v \ - 2>&1 | tee -a vlogan.log - -} - -# RUN_STEP: -elaborate() -{ - vcs $vcs_elab_opts xil_defaultlib.selectio_lvds_rx xil_defaultlib.glbl -o selectio_lvds_rx_simv -} - -# RUN_STEP: -simulate() -{ - ./selectio_lvds_rx_simv $vcs_sim_opts -do simulate.do -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_rx.sh -help\" for more information)\n" - exit 1 - fi - create_lib_mappings $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - create_lib_mappings $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Define design library mappings -create_lib_mappings() -{ - file="synopsys_sim.setup" - if [[ -e $file ]]; then - if [[ ($1 == "") ]]; then - return - else - rm -rf $file - fi - fi - - touch $file - - lib_map_path="" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - mapping="$lib:$sim_lib_dir/$lib" - echo $mapping >> $file - done - - if [[ ($lib_map_path != "") ]]; then - incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" - echo $incl_ref >> $file - fi -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(ucli.key selectio_lvds_rx_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc selectio_lvds_rx_simv.daidir) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_rx.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: selectio_lvds_rx.sh [-help]\n\ -Usage: selectio_lvds_rx.sh [-lib_map_path]\n\ -Usage: selectio_lvds_rx.sh [-reset_run]\n\ -Usage: selectio_lvds_rx.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/simulate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/simulate.do deleted file mode 100644 index 58afc787..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/simulate.do +++ /dev/null @@ -1,2 +0,0 @@ -run -quit diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/README.txt deleted file mode 100644 index c7a8bbf2..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/README.txt +++ /dev/null @@ -1,48 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun Mar 19 18:25:33 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./selectio_lvds_rx.sh - -This command will launch the 'execute' function for the single-step flow. This -function is called from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './selectio_lvds_rx.sh' script. - -./selectio_lvds_rx.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./selectio_lvds_rx.sh -noclean_files - -For more information on the script, please type './selectio_lvds_rx.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/file_info.txt deleted file mode 100644 index 6d7cb2d8..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -selectio_lvds_rx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v, -selectio_lvds_rx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/run.f b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/run.f deleted file mode 100644 index 274a0d4d..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/run.f +++ /dev/null @@ -1,15 +0,0 @@ --makelib xcelium_lib/xil_defaultlib -sv \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ --endlib --makelib xcelium_lib/xpm \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ --endlib --makelib xcelium_lib/xil_defaultlib \ - "../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v" \ - "../../../ip/selectio_lvds_rx/selectio_lvds_rx.v" \ --endlib --makelib xcelium_lib/xil_defaultlib \ - glbl.v --endlib - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/selectio_lvds_rx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/selectio_lvds_rx.sh deleted file mode 100644 index ab1dfdcd..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/selectio_lvds_rx.sh +++ /dev/null @@ -1,175 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : selectio_lvds_rx.sh -# Simulator : Cadence Xcelium Parallel Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sun Mar 19 18:25:33 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: selectio_lvds_rx.sh [-help] -# usage: selectio_lvds_rx.sh [-lib_map_path] -# usage: selectio_lvds_rx.sh [-noclean_files] -# usage: selectio_lvds_rx.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'selectio_lvds_rx.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Set the compiled library directory -ref_lib_dir="." - -# Command line options -xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" - -# Design libraries -design_libs=(xil_defaultlib xpm) - -# Simulation root library directory -sim_lib_dir="xcelium_lib" - -# Script info -echo -e "selectio_lvds_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - execute -} - -# RUN_STEP: -execute() -{ - xrun $xrun_opts \ - -reflib "$ref_lib_dir/unisim:unisim" \ - -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ - -reflib "$ref_lib_dir/secureip:secureip" \ - -reflib "$ref_lib_dir/unimacro:unimacro" \ - -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.selectio_lvds_rx \ - -f run.f \ - -top glbl \ - glbl.v -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_rx.sh -help\" for more information)\n" - exit 1 - else - ref_lib_dir=$2 - fi - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_rx.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: selectio_lvds_rx.sh [-help]\n\ -Usage: selectio_lvds_rx.sh [-lib_map_path]\n\ -Usage: selectio_lvds_rx.sh [-reset_run]\n\ -Usage: selectio_lvds_rx.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/README.txt deleted file mode 100644 index 8965a407..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun Mar 19 18:25:33 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./selectio_lvds_rx.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './selectio_lvds_rx.sh' script. - -./selectio_lvds_rx.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./selectio_lvds_rx.sh -noclean_files - -For more information on the script, please type './selectio_lvds_rx.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/cmd.tcl b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/cmd.tcl deleted file mode 100644 index eef7a0f0..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/cmd.tcl +++ /dev/null @@ -1,12 +0,0 @@ -set curr_wave [current_wave_config] -if { [string length $curr_wave] == 0 } { - if { [llength [get_objects]] > 0} { - add_wave / - set_property needs_save false [current_wave_config] - } else { - send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." - } -} - -run -all -quit diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/elab.opt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/elab.opt deleted file mode 100644 index cbdf0b26..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/elab.opt +++ /dev/null @@ -1 +0,0 @@ ---relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot selectio_lvds_rx xil_defaultlib.selectio_lvds_rx xil_defaultlib.glbl -log elaborate.log diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/file_info.txt deleted file mode 100644 index 27843160..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/file_info.txt +++ /dev/null @@ -1,3 +0,0 @@ -selectio_lvds_rx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v, -selectio_lvds_rx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/selectio_lvds_rx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/selectio_lvds_rx.sh deleted file mode 100644 index 0e8c2138..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/selectio_lvds_rx.sh +++ /dev/null @@ -1,212 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : selectio_lvds_rx.sh -# Simulator : Xilinx Vivado Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sun Mar 19 18:25:33 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: selectio_lvds_rx.sh [-help] -# usage: selectio_lvds_rx.sh [-lib_map_path] -# usage: selectio_lvds_rx.sh [-noclean_files] -# usage: selectio_lvds_rx.sh [-reset_run] -# -#********************************************************************************************************* - -# Command line options -xv_boost_lib_path=C:/Xilinx/Vivado/2019.1/tps/boost_1_64_0 -xvlog_opts="--relax" - - -# Script info -echo -e "selectio_lvds_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log - -} - -# RUN_STEP: -elaborate() -{ - xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot selectio_lvds_rx xil_defaultlib.selectio_lvds_rx xil_defaultlib.glbl -log elaborate.log -} - -# RUN_STEP: -simulate() -{ - xsim selectio_lvds_rx -key {Behavioral:sim_1:Functional:selectio_lvds_rx} -tclbatch cmd.tcl -log simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_rx.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Copy xsim.ini file -copy_setup_file() -{ - file="xsim.ini" - lib_map_path="C:/Xilinx/Vivado/2019.1/data/xsim" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - cp $src_file . - fi - - # Map local design libraries to xsim.ini - map_local_libs - - fi -} - -# Map local design libraries -map_local_libs() -{ - updated_mappings=() - local_mappings=() - - # Local design libraries - local_libs=() - - if [[ 0 == ${#local_libs[@]} ]]; then - return - fi - - file="xsim.ini" - file_backup="xsim.ini.bak" - - if [[ -e $file ]]; then - rm -f $file_backup - # Create a backup copy of the xsim.ini file - cp $file $file_backup - # Read libraries from backup file and search in local library collection - while read -r line - do - IN=$line - # Split mapping entry with '=' delimiter to fetch library name and mapping - read lib_name mapping <<<$(IFS="="; echo $IN) - # If local library found, then construct the local mapping and add to local mapping collection - if `echo ${local_libs[@]} | grep -wq $lib_name` ; then - line="$lib_name=xsim.dir/$lib_name" - local_mappings+=("$lib_name") - fi - # Add to updated library mapping collection - updated_mappings+=("$line") - done < "$file_backup" - # Append local libraries not found originally from xsim.ini - for (( i=0; i<${#local_libs[*]}; i++ )); do - lib_name="${local_libs[i]}" - if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then - line="$lib_name=xsim.dir/$lib_name" - updated_mappings+=("$line") - fi - done - # Write updated mappings in xsim.ini - rm -f $file - for (( i=0; i<${#updated_mappings[*]}; i++ )); do - lib_name="${updated_mappings[i]}" - echo $lib_name >> $file - done - else - for (( i=0; i<${#local_libs[*]}; i++ )); do - lib_name="${local_libs[i]}" - mapping="$lib_name=xsim.dir/$lib_name" - echo $mapping >> $file - done - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb selectio_lvds_rx.wdb xsim.dir) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_rx.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: selectio_lvds_rx.sh [-help]\n\ -Usage: selectio_lvds_rx.sh [-lib_map_path]\n\ -Usage: selectio_lvds_rx.sh [-reset_run]\n\ -Usage: selectio_lvds_rx.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/vlog.prj b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/vlog.prj deleted file mode 100644 index 8fd43844..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/vlog.prj +++ /dev/null @@ -1,7 +0,0 @@ -verilog xil_defaultlib \ -"../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v" \ -"../../../ip/selectio_lvds_rx/selectio_lvds_rx.v" \ - -verilog xil_defaultlib "glbl.v" - -nosort diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/xsim.ini b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/xsim.ini deleted file mode 100644 index 6cb07f57..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/xsim.ini +++ /dev/null @@ -1,430 +0,0 @@ -std=$RDI_DATADIR/xsim/vhdl/std -ieee=$RDI_DATADIR/xsim/vhdl/ieee -ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed -vl=$RDI_DATADIR/xsim/vhdl/vl -synopsys=$RDI_DATADIR/xsim/vhdl/synopsys -secureip=$RDI_DATADIR/xsim/verilog/secureip -unisim=$RDI_DATADIR/xsim/vhdl/unisim -unimacro=$RDI_DATADIR/xsim/vhdl/unimacro -unifast=$RDI_DATADIR/xsim/vhdl/unifast -unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver -unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver -unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver -simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver -system_cache_v4_0_6=$RDI_DATADIR/xsim/ip/system_cache_v4_0_6 -bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0 -g709_rs_decoder_v2_2_8=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_8 -xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0 -mipi_dphy_v4_1_4=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_1_4 -iomodule_v3_1_4=$RDI_DATADIR/xsim/ip/iomodule_v3_1_4 -ieee802d3_50g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_11 -common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0 -lte_fft_v2_1_0=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_0 -ieee802d3_50g_rs_fec_v2_0_1=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_1 -convolution_v9_0_14=$RDI_DATADIR/xsim/ip/convolution_v9_0_14 -gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4 -v_cfa_v7_0_14=$RDI_DATADIR/xsim/ip/v_cfa_v7_0_14 -axi4svideo_bridge_v1_0_10=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_10 -pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11 -v_vscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_13 -xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6 -gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux -ethernet_1_10_25g_v2_2_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_2_3 -zynq_ultra_ps_e_v3_3_0=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_0 -v_cresample_v4_0_14=$RDI_DATADIR/xsim/ip/v_cresample_v4_0_14 -v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9 -v_scenechange_v1_0_1=$RDI_DATADIR/xsim/ip/v_scenechange_v1_0_1 -hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0 -ahblite_axi_bridge_v3_0_14=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_14 -tri_mode_ethernet_mac_v9_0_14=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_14 -blk_mem_gen_v8_4_3=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_3 -noc_mc_ddr4_phy_v1_0_0=$RDI_DATADIR/xsim/ip/noc_mc_ddr4_phy_v1_0_0 -axi_data_fifo_v2_1_18=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_18 -axi_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_5 -ethernet_1_10_25g_v2_0_5=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_0_5 -compact_gt_v1_0_5=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_5 -axi_gpio_v2_0_21=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_21 -qdma_v3_0_2=$RDI_DATADIR/xsim/ip/qdma_v3_0_2 -viterbi_v9_1_11=$RDI_DATADIR/xsim/ip/viterbi_v9_1_11 -sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2 -ba317=$RDI_DATADIR/xsim/ip/ba317 -xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4 -fifo_generator_v13_2_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_4 -axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14 -vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0 -axi_emc_v3_0_19=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_19 -cmac_v2_5_1=$RDI_DATADIR/xsim/ip/cmac_v2_5_1 -floating_point_v7_1_8=$RDI_DATADIR/xsim/ip/floating_point_v7_1_8 -xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6 -vid_phy_controller_v2_2_3=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_3 -common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1 -axi_firewall_v1_0_7=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_7 -util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1 -axis_accelerator_adapter_v2_1_15=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_15 -tmr_comparator_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_2 -sd_fec_v1_0_2=$RDI_DATADIR/xsim/ip/sd_fec_v1_0_2 -tmr_manager_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_4 -tsn_temac_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_4 -usxgmii_v1_0_5=$RDI_DATADIR/xsim/ip/usxgmii_v1_0_5 -lte_dl_channel_encoder_v4_0_0=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v4_0_0 -ai_noc=$RDI_DATADIR/xsim/ip/ai_noc -lte_3gpp_mimo_decoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_15 -v_uhdsdi_audio_v1_0_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_0_0 -axi4stream_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_5 -cmac_usplus_v2_4_5=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_4_5 -etrnic_v1_1_2=$RDI_DATADIR/xsim/ip/etrnic_v1_1_2 -floating_point_v7_0_16=$RDI_DATADIR/xsim/ip/floating_point_v7_0_16 -axi_dma_v7_1_20=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_20 -jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi -axi_traffic_gen_v3_0_5=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_5 -emb_mem_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_1 -axi_amm_bridge_v1_0_9=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_9 -axi_datamover_v5_1_21=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_21 -v_axi4s_vid_out_v4_0_10=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_10 -jesd204_v7_2_6=$RDI_DATADIR/xsim/ip/jesd204_v7_2_6 -v_letterbox_v1_0_13=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_13 -interlaken_v2_4_3=$RDI_DATADIR/xsim/ip/interlaken_v2_4_3 -uhdsdi_gt_v2_0_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_0 -axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7 -rst_vip_v1_0_3=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_3 -audio_formatter_v1_0_1=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_1 -lte_3gpp_channel_estimator_v2_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_16 -v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13 -g709_fec_v2_3_5=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_5 -xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6 -axi_chip2chip_v5_0_6=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_6 -fc32_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_11 -v_mix_v3_0_3=$RDI_DATADIR/xsim/ip/v_mix_v3_0_3 -multi_channel_25g_rs_fec_v1_0_5=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_5 -in_system_ibert_v1_0_9=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_9 -ethernet_1_10_25g_v2_1_4=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_1_4 -axis_broadcaster_v1_1_18=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_18 -axis_combiner_v1_1_17=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_17 -axi_apb_bridge_v3_0_15=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_15 -displayport_v9_0_1=$RDI_DATADIR/xsim/ip/displayport_v9_0_1 -clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2 -hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1 -axi_register_slice_v2_1_19=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_19 -vid_phy_controller_v2_1_5=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_5 -picxo=$RDI_DATADIR/xsim/ip/picxo -usxgmii_v1_1_0=$RDI_DATADIR/xsim/ip/usxgmii_v1_1_0 -v_vcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_13 -bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0 -prc_v1_3_2=$RDI_DATADIR/xsim/ip/prc_v1_3_2 -axi_usb2_device_v5_0_20=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_20 -lte_3gpp_mimo_encoder_v4_0_14=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_14 -l_ethernet_v2_5_2=$RDI_DATADIR/xsim/ip/l_ethernet_v2_5_2 -xdma_v4_1_3=$RDI_DATADIR/xsim/ip/xdma_v4_1_3 -axis_vio_v1_0_0=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_0 -c_counter_binary_v12_0_13=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_13 -noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0 -xbip_dsp48_macro_v3_0_17=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_17 -c_accum_v12_0_13=$RDI_DATADIR/xsim/ip/c_accum_v12_0_13 -xbip_multadd_v3_0_14=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_14 -axi_uartlite_v2_0_23=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_23 -noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0 -axi_intc_v4_1_13=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_13 -i2s_transmitter_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_3 -pc_cfr_v6_0_8=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_8 -mutex_v2_1_10=$RDI_DATADIR/xsim/ip/mutex_v2_1_10 -c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6 -sid_v8_0_14=$RDI_DATADIR/xsim/ip/sid_v8_0_14 -fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6 -quadsgmii_v3_4_6=$RDI_DATADIR/xsim/ip/quadsgmii_v3_4_6 -microblaze_v11_0_1=$RDI_DATADIR/xsim/ip/microblaze_v11_0_1 -lib_bmg_v1_0_12=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_12 -dds_compiler_v6_0_18=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_18 -me_pl_v1_0=$RDI_DATADIR/xsim/ip/me_pl_v1_0 -gtwizard_ultrascale_v1_7_6=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_6 -axis_clock_converter_v1_1_20=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_20 -nvmeha_v1_0_0=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_0 -tmr_inject_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_3 -axi_mcdma_v1_1_0=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_0 -axi_hwicap_v3_0_23=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_23 -v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0 -v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0 -canfd_v2_0_1=$RDI_DATADIR/xsim/ip/canfd_v2_0_1 -gig_ethernet_pcs_pma_v16_1_6=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_6 -lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2 -ieee802d3_rs_fec_v2_0_5=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_5 -ibert_lib_v1_0_6=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_6 -high_speed_selectio_wiz_v3_4_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_1 -xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6 -fec_5g_common_v1_0_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_1 -tmr_voter_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_2 -hdmi_gt_controller_v1_0_0=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_0 -axi_traffic_gen_v2_0_20=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_20 -flexo_100g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_11 -v_smpte_uhdsdi_v1_0_7=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_7 -xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6 -fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10 -ieee802d3_rs_fec_v1_0_15=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_15 -axis_subset_converter_v1_1_19=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_19 -noc_nmu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_v1_0_0 -duc_ddc_compiler_v3_0_15=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_15 -dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13 -mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0 -ieee802d3_200g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_7 -sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1 -mrmac_v1_0_0=$RDI_DATADIR/xsim/ip/mrmac_v1_0_0 -sem_ultra_v3_1_11=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_11 -v_tpg_v8_0_1=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_1 -axi_tft_v2_0_22=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_22 -ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13 -switch_core_top_v1_0_7=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_7 -rama_v1_1_2_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_2_lib -v_hcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_13 -emb_fifo_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_1 -hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3 -axis_data_fifo_v2_0_1=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_1 -hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0 -rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1 -displayport_v8_1_1=$RDI_DATADIR/xsim/ip/displayport_v8_1_1 -axi_mmu_v2_1_17=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_17 -proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13 -pc_cfr_v6_3_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_3_0 -v_osd_v6_0_16=$RDI_DATADIR/xsim/ip/v_osd_v6_0_16 -pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12 -xfft_v9_0_17=$RDI_DATADIR/xsim/ip/xfft_v9_0_17 -axi_cdma_v4_1_19=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_19 -audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0 -lib_fifo_v1_0_13=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_13 -v_enhance_v8_0_15=$RDI_DATADIR/xsim/ip/v_enhance_v8_0_15 -axi_clock_converter_v2_1_18=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_18 -xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0 -emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5 -axi_mm2s_mapper_v1_1_18=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_18 -xfft_v7_2_9=$RDI_DATADIR/xsim/ip/xfft_v7_2_9 -pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0 -v_smpte_sdi_v3_0_8=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_8 -fir_compiler_v7_2_12=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_12 -div_gen_v5_1_15=$RDI_DATADIR/xsim/ip/div_gen_v5_1_15 -mdm_v3_2_16=$RDI_DATADIR/xsim/ip/mdm_v3_2_16 -v_axi4s_remap_v1_0_11=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_11 -xxv_ethernet_v2_5_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_5_3 -xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2 -ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig -remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4 -pr_axi_shutdown_manager_v1_0_1=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_1 -axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0 -smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0 -axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib -axi_dwidth_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_19 -xlconstant_v1_1_6=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_6 -tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6 -mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2 -v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1 -axi_fifo_mm_s_v4_2_1=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_1 -util_idelay_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_1 -rs_toolbox_v9_0_7=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_7 -v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0 -dsp_macro_v1_0_0=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_0 -pc_cfr_v6_2_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_2 -axi_timer_v2_0_21=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_21 -high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1 -axi_sideband_util_v1_0_3=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_3 -sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2 -gmii_to_rgmii_v4_0_7=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_0_7 -xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2 -high_speed_selectio_wiz_v3_5_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_5_1 -axi_msg_v1_0_5=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_5 -axi_ahblite_bridge_v3_0_16=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_16 -v_rgb2ycrcb_v7_1_13=$RDI_DATADIR/xsim/ip/v_rgb2ycrcb_v7_1_13 -v_mix_v4_0_0=$RDI_DATADIR/xsim/ip/v_mix_v4_0_0 -axi_ethernetlite_v3_0_17=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_17 -axi_uart16550_v2_0_21=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_21 -axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0 -vfb_v1_0_13=$RDI_DATADIR/xsim/ip/vfb_v1_0_13 -advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0 -ats_switch_v1_0_2=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_2 -interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4 -axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub -cpri_v8_10_3=$RDI_DATADIR/xsim/ip/cpri_v8_10_3 -c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6 -v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0 -stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0 -rld3_pl_v1_0_1=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_1 -ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0 -lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0 -axi_epc_v2_0_22=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_22 -g709_rs_encoder_v2_2_6=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_6 -blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6 -tmr_sem_v1_0_9=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_9 -fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6 -axi_vdma_v6_3_7=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_7 -axis_data_fifo_v1_1_20=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_20 -xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip -axi_ethernet_buffer_v2_0_20=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_20 -rs_encoder_v9_0_15=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_15 -axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0 -ta_dma_v1_0_3=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_3 -tcc_encoder_3gpp_v5_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_15 -axi_perf_mon_v5_0_21=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_21 -noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0 -sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1 -lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2 -v_csc_v1_0_13=$RDI_DATADIR/xsim/ip/v_csc_v1_0_13 -shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0 -lte_fft_v2_0_18=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_18 -gtwizard_ultrascale_v1_6_11=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_11 -amm_axi_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_5 -mii_to_rmii_v2_0_21=$RDI_DATADIR/xsim/ip/mii_to_rmii_v2_0_21 -videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5 -audio_clock_recovery_v1_0=$RDI_DATADIR/xsim/ip/audio_clock_recovery_v1_0 -cmac_v2_4_1=$RDI_DATADIR/xsim/ip/cmac_v2_4_1 -i2s_receiver_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_3 -v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0 -v_demosaic_v1_0_5=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_5 -remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4 -microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4 -hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3 -etrnic_v1_0_3=$RDI_DATADIR/xsim/ip/etrnic_v1_0_3 -xfft_v9_1_2=$RDI_DATADIR/xsim/ip/xfft_v9_1_2 -ddr4_pl_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_2 -xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6 -cmac_usplus_v2_5_3=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_5_3 -jesd204c_v4_1_1=$RDI_DATADIR/xsim/ip/jesd204c_v4_1_1 -debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1 -axis_protocol_checker_v2_0_3=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_3 -v_frmbuf_wr_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_2 -v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9 -mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4 -lte_dl_channel_encoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_15 -axi_protocol_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_19 -xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0 -clk_gen_sim_v1_0_0=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_0 -axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0 -microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7 -cmpy_v6_0_17=$RDI_DATADIR/xsim/ip/cmpy_v6_0_17 -cmac_v2_3_5=$RDI_DATADIR/xsim/ip/cmac_v2_3_5 -ieee802d3_400g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_7 -xxv_ethernet_v2_4_5=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_4_5 -axi_timebase_wdt_v3_0_11=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_11 -tcc_decoder_3gppmm_v2_0_18=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_18 -v_deinterlacer_v5_0_13=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_13 -dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16 -axi_fifo_mm_s_v4_1_16=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_16 -processing_system7_vip_v1_0_7=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_7 -g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18 -rs_decoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_16 -c_shift_ram_v12_0_13=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_13 -displayport_v7_0_11=$RDI_DATADIR/xsim/ip/displayport_v7_0_11 -v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0 -v_deinterlacer_v4_0_12=$RDI_DATADIR/xsim/ip/v_deinterlacer_v4_0_12 -sem_v4_1_12=$RDI_DATADIR/xsim/ip/sem_v4_1_12 -xaui_v12_3_6=$RDI_DATADIR/xsim/ip/xaui_v12_3_6 -ten_gig_eth_mac_v15_1_7=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_7 -oddr_v1_0_0=$RDI_DATADIR/xsim/ip/oddr_v1_0_0 -c_addsub_v12_0_13=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_13 -v_ccm_v6_0_15=$RDI_DATADIR/xsim/ip/v_ccm_v6_0_15 -zynq_ultra_ps_e_vip_v1_0_5=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_5 -cic_compiler_v4_0_14=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_14 -c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6 -axi_memory_init_v1_0_0=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_0 -pr_decoupler_v1_0_7=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_7 -timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4 -lte_pucch_receiver_v2_0_16=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_16 -zynq_ultra_ps_e_v3_2_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_3 -v_gamma_lut_v1_0_5=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_5 -bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0 -pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0 -tcc_encoder_3gpplte_v4_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_15 -polar_v1_0_3=$RDI_DATADIR/xsim/ip/polar_v1_0_3 -rxaui_v4_4_6=$RDI_DATADIR/xsim/ip/rxaui_v4_4_6 -xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6 -v_gamma_v7_0_15=$RDI_DATADIR/xsim/ip/v_gamma_v7_0_15 -ernic_v1_0_1=$RDI_DATADIR/xsim/ip/ernic_v1_0_1 -high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3 -mailbox_v2_1_11=$RDI_DATADIR/xsim/ip/mailbox_v2_1_11 -video_frame_crc_v1_0_1=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_1 -axi_sg_v4_1_12=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_12 -ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0 -lmb_bram_if_cntlr_v4_0_16=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_16 -l_ethernet_v2_4_3=$RDI_DATADIR/xsim/ip/l_ethernet_v2_4_3 -dft_v4_1_1=$RDI_DATADIR/xsim/ip/dft_v4_1_1 -rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0 -axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6 -v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0 -stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0 -lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0 -uhdsdi_gt_v1_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_3 -pc_cfr_v6_1_4=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_4 -lmb_v10_v3_0_9=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_9 -axis_interconnect_v1_1_17=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_17 -cordic_v6_0_15=$RDI_DATADIR/xsim/ip/cordic_v6_0_15 -axis_register_slice_v1_1_19=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_19 -axis_switch_v1_1_19=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_19 -axi_interconnect_v1_7_16=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_16 -mult_gen_v12_0_15=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_15 -spdif_v2_0_21=$RDI_DATADIR/xsim/ip/spdif_v2_0_21 -v_hscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_13 -ethernet_1_10_25g_v2_3_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_3_3 -xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6 -axi_quad_spi_v3_2_18=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_18 -axi_bram_ctrl_v4_1_1=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_1 -axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4 -axi_protocol_checker_v2_0_5=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_5 -axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0 -mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7 -ieee802d3_25g_rs_fec_v1_0_13=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_13 -aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0 -xtlm=$RDI_DATADIR/xsim/ip/xtlm -iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0 -ieee802d3_clause74_fec_v1_0_4=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_4 -xlconcat_v2_1_3=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_3 -perf_axi_tg_v1_0_8=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_8 -axi_crossbar_v2_1_20=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_20 -tsn_endpoint_ethernet_mac_block_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_4 -v_ycrcb2rgb_v7_1_13=$RDI_DATADIR/xsim/ip/v_ycrcb2rgb_v7_1_13 -xhmc_v1_0_9=$RDI_DATADIR/xsim/ip/xhmc_v1_0_9 -dp_videoaxi4s_bridge_v1_0_0=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_0 -lte_ul_channel_decoder_v4_0_16=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_16 -soft_ecc_proxy_v1_0_0=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_0 -pr_bitstream_monitor_v1_0_1=$RDI_DATADIR/xsim/ip/pr_bitstream_monitor_v1_0_1 -sync_ip=$RDI_DATADIR/xsim/ip/sync_ip -v_frmbuf_rd_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_1_2 -c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6 -cmac_usplus_v2_6_2=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_6_2 -axi_mcdma_v1_0_5=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_5 -c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6 -g709_fec_v2_4_1=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_1 -lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0 -ai_pl=$RDI_DATADIR/xsim/ip/ai_pl -fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4 -v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0 -l_ethernet_v2_3_5=$RDI_DATADIR/xsim/ip/l_ethernet_v2_3_5 -microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6 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-lte_rach_detector_v3_1_5=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_5 -xxv_ethernet_v3_0_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v3_0_3 -axi_iic_v2_0_22=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_22 -axi_pcie_v2_9_1=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_1 -util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4 -sim_trig_top_v1_0=$RDI_DATADIR/xsim/ip/sim_trig_top_v1_0 -v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0 -v_tpg_v7_0_13=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_13 -sd_fec_v1_1_3=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_3 -xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6 -lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2 -v_multi_scaler_v1_0_1=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_0_1 -axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0 -advanced_io_wizard_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_0 -mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8 -axi_pcie3_v3_0_9=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_9 -axi_vfifo_ctrl_v2_0_21=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_21 -xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/README.txt deleted file mode 100644 index f3d66c82..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/README.txt +++ /dev/null @@ -1,83 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required -# to simulate the design for a simulator, the directory structure -# and the generated exported files. -# -################################################################################ - -1. Simulate Design - -To simulate design, cd to the simulator directory and execute the script. - -For example:- - -% cd questa -% ./top.sh - -The export simulation flow requires the Xilinx pre-compiled simulation library -components for the target simulator. These components are referred using the -'-lib_map_path' switch. If this switch is specified, then the export simulation -will automatically set this library path in the generated script and update, -copy the simulator setup file(s) in the exported directory. - -If '-lib_map_path' is not specified, then the pre-compiled simulation library -information will not be included in the exported scripts and that may cause -simulation errors when running this script. Alternatively, you can provide the -library information using this switch while executing the generated script. - -For example:- - -% ./top.sh -lib_map_path /design/questa/clibs - -Please refer to the generated script header 'Prerequisite' section for more details. - -2. Directory Structure - -By default, if the -directory switch is not specified, export_simulation will -create the following directory structure:- - -/export_sim/ - -For example, if the current working directory is /tmp/test, export_simulation -will create the following directory path:- - -/tmp/test/export_sim/questa - -If -directory switch is specified, export_simulation will create a simulator -sub-directory under the specified directory path. - -For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' -command will create the following directory:- - -/tmp/test/my_test_area/func_sim/questa - -By default, if -simulator is not specified, export_simulation will create a -simulator sub-directory for each simulator and export the files for each simulator -in this sub-directory respectively. - -IMPORTANT: Please note that the simulation library path must be specified manually -in the generated script for the respective simulator. Please refer to the generated -script header 'Prerequisite' section for more details. - -3. Exported script and files - -Export simulation will create the driver shell script, setup files and copy the -design sources in the output directory path. - -By default, when the -script_name switch is not specified, export_simulation will -create the following script name:- - -.sh (Unix) -When exporting the files for an IP using the -of_objects switch, export_simulation -will create the following script name:- - -.sh (Unix) -Export simulation will create the setup files for the target simulator specified -with the -simulator switch. - -For example, if the target simulator is "ies", export_simulation will create the -'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' -file. - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/README.txt deleted file mode 100644 index 9e224e68..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun Mar 19 17:32:07 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./selectio_lvds_tx.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './selectio_lvds_tx.sh' script. - -./selectio_lvds_tx.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./selectio_lvds_tx.sh -noclean_files - -For more information on the script, please type './selectio_lvds_tx.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/compile.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/compile.do deleted file mode 100644 index 90297657..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/compile.do +++ /dev/null @@ -1,23 +0,0 @@ -vlib work -vlib activehdl - -vlib activehdl/xil_defaultlib -vlib activehdl/xpm - -vmap xil_defaultlib activehdl/xil_defaultlib -vmap xpm activehdl/xpm - -vlog -work xil_defaultlib -sv2k12 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -93 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work xil_defaultlib -v2k5 \ -"../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v" \ -"../../../ip/selectio_lvds_tx/selectio_lvds_tx.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/file_info.txt deleted file mode 100644 index eddbf85c..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -selectio_lvds_tx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v, -selectio_lvds_tx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/selectio_lvds_tx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/selectio_lvds_tx.sh deleted file mode 100644 index 85b5cc3a..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/selectio_lvds_tx.sh +++ /dev/null @@ -1,153 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : selectio_lvds_tx.sh -# Simulator : Aldec Active-HDL Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sun Mar 19 17:32:07 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: selectio_lvds_tx.sh [-help] -# usage: selectio_lvds_tx.sh [-lib_map_path] -# usage: selectio_lvds_tx.sh [-noclean_files] -# usage: selectio_lvds_tx.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'selectio_lvds_tx.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "selectio_lvds_tx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - runvsimsa -l simulate.log -do "do {simulate.do}" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_tx.sh -help\" for more information)\n" - exit 1 - fi - map_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - map_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Map library.cfg file -map_setup_file() -{ - file="library.cfg" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - else - lib_map_path="D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/activehdl" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - vmap -link $lib_map_path - fi - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_tx.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: selectio_lvds_tx.sh [-help]\n\ -Usage: selectio_lvds_tx.sh [-lib_map_path]\n\ -Usage: selectio_lvds_tx.sh [-reset_run]\n\ -Usage: selectio_lvds_tx.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/selectio_lvds_tx.udo b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/selectio_lvds_tx.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/simulate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/simulate.do deleted file mode 100644 index 934173ec..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/simulate.do +++ /dev/null @@ -1,17 +0,0 @@ -onbreak {quit -force} -onerror {quit -force} - -asim -t 1ps +access +r +m+selectio_lvds_tx -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.selectio_lvds_tx xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure - -do {selectio_lvds_tx.udo} - -run -all - -endsim - -quit -force diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/wave.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/README.txt deleted file mode 100644 index 03fedd1b..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/README.txt +++ /dev/null @@ -1,48 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun Mar 19 17:32:07 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./selectio_lvds_tx.sh - -This command will launch the 'execute' function for the single-step flow. This -function is called from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './selectio_lvds_tx.sh' script. - -./selectio_lvds_tx.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./selectio_lvds_tx.sh -noclean_files - -For more information on the script, please type './selectio_lvds_tx.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/file_info.txt deleted file mode 100644 index eddbf85c..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -selectio_lvds_tx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v, -selectio_lvds_tx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/run.f b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/run.f deleted file mode 100644 index de95176a..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/run.f +++ /dev/null @@ -1,15 +0,0 @@ --makelib ies_lib/xil_defaultlib -sv \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ --endlib --makelib ies_lib/xpm \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ --endlib --makelib ies_lib/xil_defaultlib \ - "../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v" \ - "../../../ip/selectio_lvds_tx/selectio_lvds_tx.v" \ --endlib --makelib ies_lib/xil_defaultlib \ - glbl.v --endlib - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/selectio_lvds_tx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/selectio_lvds_tx.sh deleted file mode 100644 index 4188c992..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/selectio_lvds_tx.sh +++ /dev/null @@ -1,175 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : selectio_lvds_tx.sh -# Simulator : Cadence Incisive Enterprise Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sun Mar 19 17:32:07 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: selectio_lvds_tx.sh [-help] -# usage: selectio_lvds_tx.sh [-lib_map_path] -# usage: selectio_lvds_tx.sh [-noclean_files] -# usage: selectio_lvds_tx.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'selectio_lvds_tx.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Set the compiled library directory -ref_lib_dir="." - -# Command line options -irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" - -# Design libraries -design_libs=(xil_defaultlib xpm) - -# Simulation root library directory -sim_lib_dir="ies_lib" - -# Script info -echo -e "selectio_lvds_tx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - execute -} - -# RUN_STEP: -execute() -{ - irun $irun_opts \ - -reflib "$ref_lib_dir/unisim:unisim" \ - -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ - -reflib "$ref_lib_dir/secureip:secureip" \ - -reflib "$ref_lib_dir/unimacro:unimacro" \ - -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.selectio_lvds_tx \ - -f run.f \ - -top glbl \ - glbl.v -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_tx.sh -help\" for more information)\n" - exit 1 - else - ref_lib_dir=$2 - fi - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_tx.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: selectio_lvds_tx.sh [-help]\n\ -Usage: selectio_lvds_tx.sh [-lib_map_path]\n\ -Usage: selectio_lvds_tx.sh [-reset_run]\n\ -Usage: selectio_lvds_tx.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/README.txt deleted file mode 100644 index 9e224e68..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun Mar 19 17:32:07 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./selectio_lvds_tx.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './selectio_lvds_tx.sh' script. - -./selectio_lvds_tx.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./selectio_lvds_tx.sh -noclean_files - -For more information on the script, please type './selectio_lvds_tx.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/compile.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/compile.do deleted file mode 100644 index 9905d936..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/compile.do +++ /dev/null @@ -1,15 +0,0 @@ -vlib modelsim_lib/work -vlib modelsim_lib/msim - -vlib modelsim_lib/msim/xil_defaultlib - -vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib - -vlog -work xil_defaultlib -64 -incr \ -"../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v" \ -"../../../ip/selectio_lvds_tx/selectio_lvds_tx.v" \ - - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/file_info.txt deleted file mode 100644 index 3f418daf..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/file_info.txt +++ /dev/null @@ -1,3 +0,0 @@ -selectio_lvds_tx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v, -selectio_lvds_tx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/modelsim.ini b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/modelsim.ini deleted file mode 100644 index 04a43f2c..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/modelsim.ini +++ /dev/null @@ -1,2590 +0,0 @@ -; vsim modelsim.ini file -[Version] -INIVersion = "2020.4" - -; Copyright 1991-2020 Mentor Graphics Corporation -; -; All Rights Reserved. -; -; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF -; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. -; - -[Library] -others = $MODEL_TECH/../modelsim.ini -; -; VITAL concerns: -; -; The library ieee contains (among other packages) the packages of the -; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use -; the physical library ieee (recommended), or use the physical library -; vital2000, but not both. The design can use logical library ieee and/or -; vital2000 as long as each of these maps to the same physical library, either -; ieee or vital2000. -; -; A design using the 1995 version of the VITAL packages, whether or not -; it also uses the 2000 version of the VITAL packages, must have logical library -; name ieee mapped to physical library vital1995. (A design cannot use library -; vital1995 directly because some packages in this library use logical name ieee -; when referring to the other packages in the library.) The design source -; should use logical name ieee when referring to any packages there except the -; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical -; name vital2000 (mapped to physical library vital2000) to refer to those -; packages. -; ieee = $MODEL_TECH/../vital1995 -; -; For compatiblity with previous releases, logical library name vital2000 maps -; to library vital2000 (a different library than library ieee, containing the -; same packages). -; A design should not reference VITAL from both the ieee library and the -; vital2000 library because the vital packages are effectively different. -; A design that references both the ieee and vital2000 libraries must have -; both logical names ieee and vital2000 mapped to the same library, either of -; these: -; $MODEL_TECH/../ieee -; $MODEL_TECH/../vital2000 -; - -; added mapping for ADMS - -;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release -;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release -;mvc_lib = $MODEL_TECH/../mvc_lib - -; Automatically perform logical->physical mapping for physical libraries that -; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). -; The tail of the filesystem path name is chosen as the logical library name. -; For example, in the command "vopt -L ./path/to/lib1 -o opttop top", -; vopt automatically performs the mapping "lib1 -> ./path/to/lib1". -; See the User Manual for more details. -; -; AutoLibMapping = 0 - -secureip = C:/Mentor/CompLib/2019.1.3/secureip -unisim = C:/Mentor/CompLib/2019.1.3/unisim -unimacro = C:/Mentor/CompLib/2019.1.3/unimacro -unifast = C:/Mentor/CompLib/2019.1.3/unifast -unisims_ver = C:/Mentor/CompLib/2019.1.3/unisims_ver -unimacro_ver = C:/Mentor/CompLib/2019.1.3/unimacro_ver -unifast_ver = C:/Mentor/CompLib/2019.1.3/unifast_ver -simprims_ver = C:/Mentor/CompLib/2019.1.3/simprims_ver -xpm = C:/Mentor/CompLib/2019.1.3/xpm -xilinx_vip = C:/Mentor/CompLib/2019.1.3/xilinx_vip -advanced_io_wizard_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/advanced_io_wizard_phy_v1_0_0 -advanced_io_wizard_v1_0_0 = C:/Mentor/CompLib/2019.1.3/advanced_io_wizard_v1_0_0 -ahblite_axi_bridge_v3_0_14 = C:/Mentor/CompLib/2019.1.3/ahblite_axi_bridge_v3_0_14 -ai_noc = C:/Mentor/CompLib/2019.1.3/ai_noc -ai_pl_trig = C:/Mentor/CompLib/2019.1.3/ai_pl_trig -ai_pl = C:/Mentor/CompLib/2019.1.3/ai_pl -audio_clock_recovery_v1_0 = C:/Mentor/CompLib/2019.1.3/audio_clock_recovery_v1_0 -audio_tpg_v1_0_0 = C:/Mentor/CompLib/2019.1.3/audio_tpg_v1_0_0 -av_pat_gen_v1_0_0 = C:/Mentor/CompLib/2019.1.3/av_pat_gen_v1_0_0 -axis_infrastructure_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axis_infrastructure_v1_1_0 -axis_protocol_checker_v2_0_3 = C:/Mentor/CompLib/2019.1.3/axis_protocol_checker_v2_0_3 -axi_ahblite_bridge_v3_0_16 = C:/Mentor/CompLib/2019.1.3/axi_ahblite_bridge_v3_0_16 -axi_amm_bridge_v1_0_9 = C:/Mentor/CompLib/2019.1.3/axi_amm_bridge_v1_0_9 -axi_bram_ctrl_v4_1_1 = C:/Mentor/CompLib/2019.1.3/axi_bram_ctrl_v4_1_1 -axi_chip2chip_v5_0_6 = C:/Mentor/CompLib/2019.1.3/axi_chip2chip_v5_0_6 -axi_dbg_hub = C:/Mentor/CompLib/2019.1.3/axi_dbg_hub -axi_infrastructure_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axi_infrastructure_v1_1_0 -axi_jtag_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_jtag_v1_0_0 -axi_lite_ipif_v3_0_4 = C:/Mentor/CompLib/2019.1.3/axi_lite_ipif_v3_0_4 -axi_pcie3_v3_0_9 = C:/Mentor/CompLib/2019.1.3/axi_pcie3_v3_0_9 -axi_perf_mon_v5_0_21 = C:/Mentor/CompLib/2019.1.3/axi_perf_mon_v5_0_21 -axi_pmon_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_pmon_v1_0_0 -blk_mem_gen_v8_3_6 = C:/Mentor/CompLib/2019.1.3/blk_mem_gen_v8_3_6 -blk_mem_gen_v8_4_3 = C:/Mentor/CompLib/2019.1.3/blk_mem_gen_v8_4_3 -bsip_v1_1_0 = C:/Mentor/CompLib/2019.1.3/bsip_v1_1_0 -bs_mux_v1_0_0 = C:/Mentor/CompLib/2019.1.3/bs_mux_v1_0_0 -clk_gen_sim_v1_0_0 = C:/Mentor/CompLib/2019.1.3/clk_gen_sim_v1_0_0 -clk_vip_v1_0_2 = C:/Mentor/CompLib/2019.1.3/clk_vip_v1_0_2 -cmac_usplus_v2_4_5 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_4_5 -cmac_usplus_v2_5_3 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_5_3 -cmac_usplus_v2_6_2 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_6_2 -cmac_v2_3_5 = C:/Mentor/CompLib/2019.1.3/cmac_v2_3_5 -cmac_v2_4_1 = C:/Mentor/CompLib/2019.1.3/cmac_v2_4_1 -cmac_v2_5_1 = C:/Mentor/CompLib/2019.1.3/cmac_v2_5_1 -compact_gt_v1_0_5 = C:/Mentor/CompLib/2019.1.3/compact_gt_v1_0_5 -ddr4_pl_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/ddr4_pl_phy_v1_0_0 -ddr4_pl_v1_0_2 = C:/Mentor/CompLib/2019.1.3/ddr4_pl_v1_0_2 -dist_mem_gen_v8_0_13 = C:/Mentor/CompLib/2019.1.3/dist_mem_gen_v8_0_13 -ecc_v2_0_13 = C:/Mentor/CompLib/2019.1.3/ecc_v2_0_13 -emb_fifo_gen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/emb_fifo_gen_v1_0_1 -emb_mem_gen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/emb_mem_gen_v1_0_1 -emc_common_v3_0_5 = C:/Mentor/CompLib/2019.1.3/emc_common_v3_0_5 -ethernet_1_10_25g_v2_0_5 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_0_5 -ethernet_1_10_25g_v2_1_4 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_1_4 -ethernet_1_10_25g_v2_2_3 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_2_3 -ethernet_1_10_25g_v2_3_3 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_3_3 -fifo_generator_v13_0_6 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_0_6 -fifo_generator_v13_1_4 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_1_4 -fifo_generator_v13_2_4 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_2_4 -fit_timer_v2_0_10 = C:/Mentor/CompLib/2019.1.3/fit_timer_v2_0_10 -generic_baseblocks_v2_1_0 = C:/Mentor/CompLib/2019.1.3/generic_baseblocks_v2_1_0 -gigantic_mux = C:/Mentor/CompLib/2019.1.3/gigantic_mux -gig_ethernet_pcs_pma_v16_1_6 = C:/Mentor/CompLib/2019.1.3/gig_ethernet_pcs_pma_v16_1_6 -gmii_to_rgmii_v4_0_7 = C:/Mentor/CompLib/2019.1.3/gmii_to_rgmii_v4_0_7 -gtwizard_ultrascale_v1_5_4 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_5_4 -gtwizard_ultrascale_v1_6_11 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_6_11 -gtwizard_ultrascale_v1_7_6 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_7_6 -hbm_v1_0_4 = C:/Mentor/CompLib/2019.1.3/hbm_v1_0_4 -hdcp22_cipher_dp_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdcp22_cipher_dp_v1_0_0 -hdcp22_cipher_v1_0_3 = C:/Mentor/CompLib/2019.1.3/hdcp22_cipher_v1_0_3 -hdcp22_rng_v1_0_1 = C:/Mentor/CompLib/2019.1.3/hdcp22_rng_v1_0_1 -hdcp_keymngmt_blk_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdcp_keymngmt_blk_v1_0_0 -hdcp_v1_0_3 = C:/Mentor/CompLib/2019.1.3/hdcp_v1_0_3 -hdmi_gt_controller_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdmi_gt_controller_v1_0_0 -high_speed_selectio_wiz_v3_2_3 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_2_3 -high_speed_selectio_wiz_v3_3_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_3_1 -high_speed_selectio_wiz_v3_4_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_4_1 -high_speed_selectio_wiz_v3_5_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_5_1 -i2s_receiver_v1_0_3 = C:/Mentor/CompLib/2019.1.3/i2s_receiver_v1_0_3 -i2s_transmitter_v1_0_3 = C:/Mentor/CompLib/2019.1.3/i2s_transmitter_v1_0_3 -ibert_lib_v1_0_6 = C:/Mentor/CompLib/2019.1.3/ibert_lib_v1_0_6 -ieee802d3_clause74_fec_v1_0_4 = C:/Mentor/CompLib/2019.1.3/ieee802d3_clause74_fec_v1_0_4 -interlaken_v2_4_3 = C:/Mentor/CompLib/2019.1.3/interlaken_v2_4_3 -in_system_ibert_v1_0_9 = C:/Mentor/CompLib/2019.1.3/in_system_ibert_v1_0_9 -iomodule_v3_1_4 = C:/Mentor/CompLib/2019.1.3/iomodule_v3_1_4 -jesd204c_v4_1_1 = C:/Mentor/CompLib/2019.1.3/jesd204c_v4_1_1 -jesd204_v7_2_6 = C:/Mentor/CompLib/2019.1.3/jesd204_v7_2_6 -jtag_axi = C:/Mentor/CompLib/2019.1.3/jtag_axi -lib_cdc_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_cdc_v1_0_2 -lib_pkg_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_pkg_v1_0_2 -lmb_bram_if_cntlr_v4_0_16 = C:/Mentor/CompLib/2019.1.3/lmb_bram_if_cntlr_v4_0_16 -lmb_v10_v3_0_9 = C:/Mentor/CompLib/2019.1.3/lmb_v10_v3_0_9 -ltlib_v1_0_0 = C:/Mentor/CompLib/2019.1.3/ltlib_v1_0_0 -lut_buffer_v1_0_0 = C:/Mentor/CompLib/2019.1.3/lut_buffer_v1_0_0 -lut_buffer_v2_0_0 = C:/Mentor/CompLib/2019.1.3/lut_buffer_v2_0_0 -l_ethernet_v2_3_5 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_3_5 -l_ethernet_v2_4_3 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_4_3 -l_ethernet_v2_5_2 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_5_2 -mammoth_transcode_v1_0_0 = C:/Mentor/CompLib/2019.1.3/mammoth_transcode_v1_0_0 -microblaze_v10_0_7 = C:/Mentor/CompLib/2019.1.3/microblaze_v10_0_7 -microblaze_v11_0_1 = C:/Mentor/CompLib/2019.1.3/microblaze_v11_0_1 -microblaze_v9_5_4 = C:/Mentor/CompLib/2019.1.3/microblaze_v9_5_4 -mii_to_rmii_v2_0_21 = C:/Mentor/CompLib/2019.1.3/mii_to_rmii_v2_0_21 -mipi_csi2_rx_ctrl_v1_0_8 = C:/Mentor/CompLib/2019.1.3/mipi_csi2_rx_ctrl_v1_0_8 -mipi_csi2_tx_ctrl_v1_0_4 = C:/Mentor/CompLib/2019.1.3/mipi_csi2_tx_ctrl_v1_0_4 -mipi_dphy_v4_1_4 = C:/Mentor/CompLib/2019.1.3/mipi_dphy_v4_1_4 -mipi_dsi_tx_ctrl_v1_0_7 = C:/Mentor/CompLib/2019.1.3/mipi_dsi_tx_ctrl_v1_0_7 -mrmac_v1_0_0 = C:/Mentor/CompLib/2019.1.3/mrmac_v1_0_0 -multi_channel_25g_rs_fec_v1_0_5 = C:/Mentor/CompLib/2019.1.3/multi_channel_25g_rs_fec_v1_0_5 -mutex_v2_1_10 = C:/Mentor/CompLib/2019.1.3/mutex_v2_1_10 -axi_tg_lib = C:/Mentor/CompLib/2019.1.3/axi_tg_lib -noc_na_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_na_v1_0_0 -noc_nidb_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nidb_v1_0_0 -noc_nmu_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nmu_v1_0_0 -noc_nps_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nps_v1_0_0 -nvmeha_v1_0_0 = C:/Mentor/CompLib/2019.1.3/nvmeha_v1_0_0 -oddr_v1_0_0 = C:/Mentor/CompLib/2019.1.3/oddr_v1_0_0 -pci32_v5_0_12 = C:/Mentor/CompLib/2019.1.3/pci32_v5_0_12 -pci64_v5_0_11 = C:/Mentor/CompLib/2019.1.3/pci64_v5_0_11 -pcie_jtag_v1_0_0 = C:/Mentor/CompLib/2019.1.3/pcie_jtag_v1_0_0 -pc_cfr_v6_0_8 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_0_8 -pc_cfr_v6_1_4 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_1_4 -pc_cfr_v6_2_2 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_2_2 -pc_cfr_v6_3_0 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_3_0 -picxo = C:/Mentor/CompLib/2019.1.3/picxo -qdma_v3_0_2 = C:/Mentor/CompLib/2019.1.3/qdma_v3_0_2 -rama_v1_1_2_lib = C:/Mentor/CompLib/2019.1.3/rama_v1_1_2_lib -rld3_pl_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/rld3_pl_phy_v1_0_0 -rld3_pl_v1_0_1 = C:/Mentor/CompLib/2019.1.3/rld3_pl_v1_0_1 -roe_framer_v2_0_1 = C:/Mentor/CompLib/2019.1.3/roe_framer_v2_0_1 -rst_vip_v1_0_3 = C:/Mentor/CompLib/2019.1.3/rst_vip_v1_0_3 -smartconnect_v1_0 = C:/Mentor/CompLib/2019.1.3/smartconnect_v1_0 -sd_fec_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sd_fec_v1_0_2 -sem_ultra_v3_1_11 = C:/Mentor/CompLib/2019.1.3/sem_ultra_v3_1_11 -sem_v4_1_12 = C:/Mentor/CompLib/2019.1.3/sem_v4_1_12 -shell_utils_msp432_bsl_crc_gen_v1_0_0 = C:/Mentor/CompLib/2019.1.3/shell_utils_msp432_bsl_crc_gen_v1_0_0 -sim_clk_gen_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sim_clk_gen_v1_0_2 -sim_rst_gen_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sim_rst_gen_v1_0_2 -sim_trig_top_v1_0 = C:/Mentor/CompLib/2019.1.3/sim_trig_top_v1_0 -stm_v1_0 = C:/Mentor/CompLib/2019.1.3/stm_v1_0 -stm_v1_0_0 = C:/Mentor/CompLib/2019.1.3/stm_v1_0_0 -system_cache_v4_0_6 = C:/Mentor/CompLib/2019.1.3/system_cache_v4_0_6 -ta_dma_v1_0_3 = C:/Mentor/CompLib/2019.1.3/ta_dma_v1_0_3 -tcc_decoder_3gpplte_v3_0_6 = C:/Mentor/CompLib/2019.1.3/tcc_decoder_3gpplte_v3_0_6 -ten_gig_eth_mac_v15_1_7 = C:/Mentor/CompLib/2019.1.3/ten_gig_eth_mac_v15_1_7 -ten_gig_eth_pcs_pma_v6_0_15 = C:/Mentor/CompLib/2019.1.3/ten_gig_eth_pcs_pma_v6_0_15 -timer_sync_1588_v1_2_4 = C:/Mentor/CompLib/2019.1.3/timer_sync_1588_v1_2_4 -tmr_inject_v1_0_3 = C:/Mentor/CompLib/2019.1.3/tmr_inject_v1_0_3 -tmr_manager_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tmr_manager_v1_0_4 -tmr_voter_v1_0_2 = C:/Mentor/CompLib/2019.1.3/tmr_voter_v1_0_2 -tsn_endpoint_ethernet_mac_block_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tsn_endpoint_ethernet_mac_block_v1_0_4 -uhdsdi_gt_v1_0_3 = C:/Mentor/CompLib/2019.1.3/uhdsdi_gt_v1_0_3 -uhdsdi_gt_v2_0_0 = C:/Mentor/CompLib/2019.1.3/uhdsdi_gt_v2_0_0 -usxgmii_v1_0_5 = C:/Mentor/CompLib/2019.1.3/usxgmii_v1_0_5 -usxgmii_v1_1_0 = C:/Mentor/CompLib/2019.1.3/usxgmii_v1_1_0 -util_idelay_ctrl_v1_0_1 = C:/Mentor/CompLib/2019.1.3/util_idelay_ctrl_v1_0_1 -util_reduced_logic_v2_0_4 = C:/Mentor/CompLib/2019.1.3/util_reduced_logic_v2_0_4 -util_vector_logic_v2_0_1 = C:/Mentor/CompLib/2019.1.3/util_vector_logic_v2_0_1 -ba317 = C:/Mentor/CompLib/2019.1.3/ba317 -vfb_v1_0_13 = C:/Mentor/CompLib/2019.1.3/vfb_v1_0_13 -video_frame_crc_v1_0_1 = C:/Mentor/CompLib/2019.1.3/video_frame_crc_v1_0_1 -vid_edid_v1_0_0 = C:/Mentor/CompLib/2019.1.3/vid_edid_v1_0_0 -vid_phy_controller_v2_1_5 = C:/Mentor/CompLib/2019.1.3/vid_phy_controller_v2_1_5 -vid_phy_controller_v2_2_3 = C:/Mentor/CompLib/2019.1.3/vid_phy_controller_v2_2_3 -v_axi4s_remap_v1_0_11 = C:/Mentor/CompLib/2019.1.3/v_axi4s_remap_v1_0_11 -v_csc_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_csc_v1_0_13 -v_deinterlacer_v4_0_12 = C:/Mentor/CompLib/2019.1.3/v_deinterlacer_v4_0_12 -v_deinterlacer_v5_0_13 = C:/Mentor/CompLib/2019.1.3/v_deinterlacer_v5_0_13 -v_demosaic_v1_0_5 = C:/Mentor/CompLib/2019.1.3/v_demosaic_v1_0_5 -v_frmbuf_rd_v2_1_2 = C:/Mentor/CompLib/2019.1.3/v_frmbuf_rd_v2_1_2 -v_frmbuf_wr_v2_1_2 = C:/Mentor/CompLib/2019.1.3/v_frmbuf_wr_v2_1_2 -v_gamma_lut_v1_0_5 = C:/Mentor/CompLib/2019.1.3/v_gamma_lut_v1_0_5 -v_hcresampler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_hcresampler_v1_0_13 -v_hdmi_rx_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_rx_v2_0_0 -v_hdmi_rx_v3_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_rx_v3_0_0 -v_hdmi_tx_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_tx_v2_0_0 -v_hdmi_tx_v3_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_tx_v3_0_0 -v_hscaler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_hscaler_v1_0_13 -v_letterbox_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_letterbox_v1_0_13 -v_mix_v3_0_3 = C:/Mentor/CompLib/2019.1.3/v_mix_v3_0_3 -v_mix_v4_0_0 = C:/Mentor/CompLib/2019.1.3/v_mix_v4_0_0 -v_multi_scaler_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_multi_scaler_v1_0_1 -v_scenechange_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_scenechange_v1_0_1 -v_sdi_rx_vid_bridge_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_sdi_rx_vid_bridge_v2_0_0 -v_smpte_sdi_v3_0_8 = C:/Mentor/CompLib/2019.1.3/v_smpte_sdi_v3_0_8 -v_smpte_uhdsdi_rx_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_rx_v1_0_0 -v_smpte_uhdsdi_tx_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_tx_v1_0_0 -v_smpte_uhdsdi_v1_0_7 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_v1_0_7 -v_tpg_v7_0_13 = C:/Mentor/CompLib/2019.1.3/v_tpg_v7_0_13 -v_tpg_v8_0_1 = C:/Mentor/CompLib/2019.1.3/v_tpg_v8_0_1 -v_uhdsdi_audio_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v1_0_0 -v_uhdsdi_audio_v1_1_0 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v1_1_0 -v_uhdsdi_audio_v2_0_1 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v2_0_1 -v_uhdsdi_vidgen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_vidgen_v1_0_1 -v_vcresampler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_vcresampler_v1_0_13 -v_vid_in_axi4s_v4_0_9 = C:/Mentor/CompLib/2019.1.3/v_vid_in_axi4s_v4_0_9 -v_vscaler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_vscaler_v1_0_13 -xaui_v12_3_6 = C:/Mentor/CompLib/2019.1.3/xaui_v12_3_6 -xbip_dsp48_wrapper_v3_0_4 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_wrapper_v3_0_4 -xbip_utils_v3_0_10 = C:/Mentor/CompLib/2019.1.3/xbip_utils_v3_0_10 -xdma_v4_1_3 = C:/Mentor/CompLib/2019.1.3/xdma_v4_1_3 -xhmc_v1_0_9 = C:/Mentor/CompLib/2019.1.3/xhmc_v1_0_9 -xlconcat_v2_1_3 = C:/Mentor/CompLib/2019.1.3/xlconcat_v2_1_3 -xlconstant_v1_1_6 = C:/Mentor/CompLib/2019.1.3/xlconstant_v1_1_6 -xlslice_v1_0_2 = C:/Mentor/CompLib/2019.1.3/xlslice_v1_0_2 -xsdbm_v2_0_0 = C:/Mentor/CompLib/2019.1.3/xsdbm_v2_0_0 -xsdbm_v3_0_0 = C:/Mentor/CompLib/2019.1.3/xsdbm_v3_0_0 -xxv_ethernet_v2_4_5 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v2_4_5 -xxv_ethernet_v2_5_3 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v2_5_3 -xxv_ethernet_v3_0_3 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v3_0_3 -zynq_ultra_ps_e_v3_2_3 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_v3_2_3 -zynq_ultra_ps_e_v3_3_0 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_v3_3_0 -lib_srl_fifo_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_srl_fifo_v1_0_2 -lib_fifo_v1_0_13 = C:/Mentor/CompLib/2019.1.3/lib_fifo_v1_0_13 -axi_datamover_v5_1_21 = C:/Mentor/CompLib/2019.1.3/axi_datamover_v5_1_21 -amm_axi_bridge_v1_0_5 = C:/Mentor/CompLib/2019.1.3/amm_axi_bridge_v1_0_5 -axis_interconnect_v1_1_17 = C:/Mentor/CompLib/2019.1.3/axis_interconnect_v1_1_17 -ats_switch_v1_0_2 = C:/Mentor/CompLib/2019.1.3/ats_switch_v1_0_2 -audio_formatter_v1_0_1 = C:/Mentor/CompLib/2019.1.3/audio_formatter_v1_0_1 -axi4stream_vip_v1_1_5 = C:/Mentor/CompLib/2019.1.3/axi4stream_vip_v1_1_5 -v_tc_v6_1_13 = C:/Mentor/CompLib/2019.1.3/v_tc_v6_1_13 -v_axi4s_vid_out_v4_0_10 = C:/Mentor/CompLib/2019.1.3/v_axi4s_vid_out_v4_0_10 -axi4svideo_bridge_v1_0_10 = C:/Mentor/CompLib/2019.1.3/axi4svideo_bridge_v1_0_10 -axis_accelerator_adapter_v2_1_15 = C:/Mentor/CompLib/2019.1.3/axis_accelerator_adapter_v2_1_15 -axis_broadcaster_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axis_broadcaster_v1_1_18 -axis_clock_converter_v1_1_20 = C:/Mentor/CompLib/2019.1.3/axis_clock_converter_v1_1_20 -axis_combiner_v1_1_17 = C:/Mentor/CompLib/2019.1.3/axis_combiner_v1_1_17 -axis_data_fifo_v1_1_20 = C:/Mentor/CompLib/2019.1.3/axis_data_fifo_v1_1_20 -axis_data_fifo_v2_0_1 = C:/Mentor/CompLib/2019.1.3/axis_data_fifo_v2_0_1 -axis_register_slice_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_register_slice_v1_1_19 -axis_dwidth_converter_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axis_dwidth_converter_v1_1_18 -axis_subset_converter_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_subset_converter_v1_1_19 -axis_switch_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_switch_v1_1_19 -axis_vio_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axis_vio_v1_0_0 -axi_apb_bridge_v3_0_15 = C:/Mentor/CompLib/2019.1.3/axi_apb_bridge_v3_0_15 -axi_bram_ctrl_v4_0_14 = C:/Mentor/CompLib/2019.1.3/axi_bram_ctrl_v4_0_14 -axi_sg_v4_1_12 = C:/Mentor/CompLib/2019.1.3/axi_sg_v4_1_12 -axi_cdma_v4_1_19 = C:/Mentor/CompLib/2019.1.3/axi_cdma_v4_1_19 -axi_clock_converter_v2_1_18 = C:/Mentor/CompLib/2019.1.3/axi_clock_converter_v2_1_18 -axi_data_fifo_v2_1_18 = C:/Mentor/CompLib/2019.1.3/axi_data_fifo_v2_1_18 -axi_register_slice_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_register_slice_v2_1_19 -axi_crossbar_v2_1_20 = C:/Mentor/CompLib/2019.1.3/axi_crossbar_v2_1_20 -axi_dma_v7_1_20 = C:/Mentor/CompLib/2019.1.3/axi_dma_v7_1_20 -axi_protocol_converter_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_protocol_converter_v2_1_19 -axi_dwidth_converter_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_dwidth_converter_v2_1_19 -axi_emc_v3_0_19 = C:/Mentor/CompLib/2019.1.3/axi_emc_v3_0_19 -axi_epc_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_epc_v2_0_22 -lib_bmg_v1_0_12 = C:/Mentor/CompLib/2019.1.3/lib_bmg_v1_0_12 -axi_ethernetlite_v3_0_17 = C:/Mentor/CompLib/2019.1.3/axi_ethernetlite_v3_0_17 -axi_ethernet_buffer_v2_0_20 = C:/Mentor/CompLib/2019.1.3/axi_ethernet_buffer_v2_0_20 -axi_fifo_mm_s_v4_1_16 = C:/Mentor/CompLib/2019.1.3/axi_fifo_mm_s_v4_1_16 -axi_fifo_mm_s_v4_2_1 = C:/Mentor/CompLib/2019.1.3/axi_fifo_mm_s_v4_2_1 -axi_firewall_v1_0_7 = C:/Mentor/CompLib/2019.1.3/axi_firewall_v1_0_7 -interrupt_control_v3_1_4 = C:/Mentor/CompLib/2019.1.3/interrupt_control_v3_1_4 -axi_gpio_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_gpio_v2_0_21 -axi_hwicap_v3_0_23 = C:/Mentor/CompLib/2019.1.3/axi_hwicap_v3_0_23 -axi_iic_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_iic_v2_0_22 -axi_intc_v4_1_13 = C:/Mentor/CompLib/2019.1.3/axi_intc_v4_1_13 -axi_interconnect_v1_7_16 = C:/Mentor/CompLib/2019.1.3/axi_interconnect_v1_7_16 -axi_master_burst_v2_0_7 = C:/Mentor/CompLib/2019.1.3/axi_master_burst_v2_0_7 -axi_msg_v1_0_5 = C:/Mentor/CompLib/2019.1.3/axi_msg_v1_0_5 -axi_mcdma_v1_0_5 = C:/Mentor/CompLib/2019.1.3/axi_mcdma_v1_0_5 -axi_mcdma_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axi_mcdma_v1_1_0 -axi_memory_init_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_memory_init_v1_0_0 -axi_mm2s_mapper_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axi_mm2s_mapper_v1_1_18 -axi_mmu_v2_1_17 = C:/Mentor/CompLib/2019.1.3/axi_mmu_v2_1_17 -axi_pcie_v2_9_1 = C:/Mentor/CompLib/2019.1.3/axi_pcie_v2_9_1 -axi_protocol_checker_v2_0_5 = C:/Mentor/CompLib/2019.1.3/axi_protocol_checker_v2_0_5 -axi_quad_spi_v3_2_18 = C:/Mentor/CompLib/2019.1.3/axi_quad_spi_v3_2_18 -axi_sideband_util_v1_0_3 = C:/Mentor/CompLib/2019.1.3/axi_sideband_util_v1_0_3 -axi_tft_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_tft_v2_0_22 -axi_timebase_wdt_v3_0_11 = C:/Mentor/CompLib/2019.1.3/axi_timebase_wdt_v3_0_11 -axi_timer_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_timer_v2_0_21 -axi_traffic_gen_v2_0_20 = C:/Mentor/CompLib/2019.1.3/axi_traffic_gen_v2_0_20 -axi_traffic_gen_v3_0_5 = C:/Mentor/CompLib/2019.1.3/axi_traffic_gen_v3_0_5 -axi_uart16550_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_uart16550_v2_0_21 -axi_uartlite_v2_0_23 = C:/Mentor/CompLib/2019.1.3/axi_uartlite_v2_0_23 -axi_usb2_device_v5_0_20 = C:/Mentor/CompLib/2019.1.3/axi_usb2_device_v5_0_20 -axi_utils_v2_0_6 = C:/Mentor/CompLib/2019.1.3/axi_utils_v2_0_6 -axi_vdma_v6_3_7 = C:/Mentor/CompLib/2019.1.3/axi_vdma_v6_3_7 -xbip_pipe_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_pipe_v3_0_6 -xbip_dsp48_addsub_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_addsub_v3_0_6 -xbip_addsub_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_addsub_v3_0_6 -c_reg_fd_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_reg_fd_v12_0_6 -c_addsub_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_addsub_v12_0_13 -axi_vfifo_ctrl_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_vfifo_ctrl_v2_0_21 -axi_vip_v1_1_5 = C:/Mentor/CompLib/2019.1.3/axi_vip_v1_1_5 -bs_switch_v1_0_0 = C:/Mentor/CompLib/2019.1.3/bs_switch_v1_0_0 -canfd_v2_0_1 = C:/Mentor/CompLib/2019.1.3/canfd_v2_0_1 -can_v5_0_22 = C:/Mentor/CompLib/2019.1.3/can_v5_0_22 -cic_compiler_v4_0_14 = C:/Mentor/CompLib/2019.1.3/cic_compiler_v4_0_14 -xbip_bram18k_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_bram18k_v3_0_6 -mult_gen_v12_0_15 = C:/Mentor/CompLib/2019.1.3/mult_gen_v12_0_15 -cmpy_v6_0_17 = C:/Mentor/CompLib/2019.1.3/cmpy_v6_0_17 -c_mux_bit_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_mux_bit_v12_0_6 -c_shift_ram_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_shift_ram_v12_0_13 -c_mux_bus_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_mux_bus_v12_0_6 -c_gate_bit_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_gate_bit_v12_0_6 -xbip_counter_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_counter_v3_0_6 -c_counter_binary_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_counter_binary_v12_0_13 -c_compare_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_compare_v12_0_6 -convolution_v9_0_14 = C:/Mentor/CompLib/2019.1.3/convolution_v9_0_14 -cordic_v6_0_15 = C:/Mentor/CompLib/2019.1.3/cordic_v6_0_15 -cpri_v8_10_3 = C:/Mentor/CompLib/2019.1.3/cpri_v8_10_3 -xbip_dsp48_acc_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_acc_v3_0_6 -xbip_accum_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_accum_v3_0_6 -c_accum_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_accum_v12_0_13 -xbip_dsp48_multadd_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_multadd_v3_0_6 -dds_compiler_v6_0_18 = C:/Mentor/CompLib/2019.1.3/dds_compiler_v6_0_18 -dft_v4_0_16 = C:/Mentor/CompLib/2019.1.3/dft_v4_0_16 -dft_v4_1_1 = C:/Mentor/CompLib/2019.1.3/dft_v4_1_1 -displayport_v7_0_11 = C:/Mentor/CompLib/2019.1.3/displayport_v7_0_11 -displayport_v8_1_1 = C:/Mentor/CompLib/2019.1.3/displayport_v8_1_1 -displayport_v9_0_1 = C:/Mentor/CompLib/2019.1.3/displayport_v9_0_1 -xbip_dsp48_mult_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_mult_v3_0_6 -floating_point_v7_0_16 = C:/Mentor/CompLib/2019.1.3/floating_point_v7_0_16 -div_gen_v5_1_15 = C:/Mentor/CompLib/2019.1.3/div_gen_v5_1_15 -dp_videoaxi4s_bridge_v1_0_0 = C:/Mentor/CompLib/2019.1.3/dp_videoaxi4s_bridge_v1_0_0 -dsp_macro_v1_0_0 = C:/Mentor/CompLib/2019.1.3/dsp_macro_v1_0_0 -fir_compiler_v5_2_6 = C:/Mentor/CompLib/2019.1.3/fir_compiler_v5_2_6 -duc_ddc_compiler_v3_0_15 = C:/Mentor/CompLib/2019.1.3/duc_ddc_compiler_v3_0_15 -ernic_v1_0_1 = C:/Mentor/CompLib/2019.1.3/ernic_v1_0_1 -etrnic_v1_0_3 = C:/Mentor/CompLib/2019.1.3/etrnic_v1_0_3 -etrnic_v1_1_2 = C:/Mentor/CompLib/2019.1.3/etrnic_v1_1_2 -fc32_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/fc32_rs_fec_v1_0_11 -fec_5g_common_v1_0_1 = C:/Mentor/CompLib/2019.1.3/fec_5g_common_v1_0_1 -fec_5g_common_v1_1_1 = C:/Mentor/CompLib/2019.1.3/fec_5g_common_v1_1_1 -fir_compiler_v7_2_12 = C:/Mentor/CompLib/2019.1.3/fir_compiler_v7_2_12 -flexo_100g_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/flexo_100g_rs_fec_v1_0_11 -floating_point_v7_1_8 = C:/Mentor/CompLib/2019.1.3/floating_point_v7_1_8 -g709_rs_encoder_v2_2_6 = C:/Mentor/CompLib/2019.1.3/g709_rs_encoder_v2_2_6 -rs_toolbox_v9_0_7 = C:/Mentor/CompLib/2019.1.3/rs_toolbox_v9_0_7 -g709_rs_decoder_v2_2_8 = C:/Mentor/CompLib/2019.1.3/g709_rs_decoder_v2_2_8 -g709_fec_v2_3_5 = C:/Mentor/CompLib/2019.1.3/g709_fec_v2_3_5 -g709_fec_v2_4_1 = C:/Mentor/CompLib/2019.1.3/g709_fec_v2_4_1 -g975_efec_i4_v1_0_17 = C:/Mentor/CompLib/2019.1.3/g975_efec_i4_v1_0_17 -g975_efec_i7_v2_0_18 = C:/Mentor/CompLib/2019.1.3/g975_efec_i7_v2_0_18 -ieee802d3_200g_rs_fec_v1_0_7 = C:/Mentor/CompLib/2019.1.3/ieee802d3_200g_rs_fec_v1_0_7 -ieee802d3_25g_rs_fec_v1_0_13 = C:/Mentor/CompLib/2019.1.3/ieee802d3_25g_rs_fec_v1_0_13 -ieee802d3_400g_rs_fec_v1_0_7 = C:/Mentor/CompLib/2019.1.3/ieee802d3_400g_rs_fec_v1_0_7 -ieee802d3_50g_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/ieee802d3_50g_rs_fec_v1_0_11 -ieee802d3_50g_rs_fec_v2_0_1 = C:/Mentor/CompLib/2019.1.3/ieee802d3_50g_rs_fec_v2_0_1 -ieee802d3_rs_fec_v1_0_15 = C:/Mentor/CompLib/2019.1.3/ieee802d3_rs_fec_v1_0_15 -ieee802d3_rs_fec_v2_0_5 = C:/Mentor/CompLib/2019.1.3/ieee802d3_rs_fec_v2_0_5 -ldpc_v2_0_3 = C:/Mentor/CompLib/2019.1.3/ldpc_v2_0_3 -lte_3gpp_channel_estimator_v2_0_16 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_channel_estimator_v2_0_16 -lte_3gpp_mimo_decoder_v3_0_15 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_mimo_decoder_v3_0_15 -lte_3gpp_mimo_encoder_v4_0_14 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_mimo_encoder_v4_0_14 -tcc_encoder_3gpplte_v4_0_15 = C:/Mentor/CompLib/2019.1.3/tcc_encoder_3gpplte_v4_0_15 -lte_dl_channel_encoder_v3_0_15 = C:/Mentor/CompLib/2019.1.3/lte_dl_channel_encoder_v3_0_15 -lte_dl_channel_encoder_v4_0_0 = C:/Mentor/CompLib/2019.1.3/lte_dl_channel_encoder_v4_0_0 -xfft_v7_2_9 = C:/Mentor/CompLib/2019.1.3/xfft_v7_2_9 -lte_fft_v2_0_18 = C:/Mentor/CompLib/2019.1.3/lte_fft_v2_0_18 -xfft_v9_1_2 = C:/Mentor/CompLib/2019.1.3/xfft_v9_1_2 -lte_fft_v2_1_0 = C:/Mentor/CompLib/2019.1.3/lte_fft_v2_1_0 -xbip_dsp48_multacc_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_multacc_v3_0_6 -lte_pucch_receiver_v2_0_16 = C:/Mentor/CompLib/2019.1.3/lte_pucch_receiver_v2_0_16 -xbip_multadd_v3_0_14 = C:/Mentor/CompLib/2019.1.3/xbip_multadd_v3_0_14 -lte_rach_detector_v3_1_5 = C:/Mentor/CompLib/2019.1.3/lte_rach_detector_v3_1_5 -lte_ul_channel_decoder_v4_0_16 = C:/Mentor/CompLib/2019.1.3/lte_ul_channel_decoder_v4_0_16 -mailbox_v2_1_11 = C:/Mentor/CompLib/2019.1.3/mailbox_v2_1_11 -mdm_v3_2_16 = C:/Mentor/CompLib/2019.1.3/mdm_v3_2_16 -iomodule_v3_0 = C:/Mentor/CompLib/2019.1.3/iomodule_v3_0 -lmb_bram_if_cntlr_v4_0 = C:/Mentor/CompLib/2019.1.3/lmb_bram_if_cntlr_v4_0 -lmb_v10_v3_0 = C:/Mentor/CompLib/2019.1.3/lmb_v10_v3_0 -axi_lite_ipif_v3_0 = C:/Mentor/CompLib/2019.1.3/axi_lite_ipif_v3_0 -mdm_v3_2 = C:/Mentor/CompLib/2019.1.3/mdm_v3_2 -microblaze_mcs_v2_3_6 = C:/Mentor/CompLib/2019.1.3/microblaze_mcs_v2_3_6 -noc_mc_ddr4_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_mc_ddr4_phy_v1_0_0 -perf_axi_tg_v1_0_8 = C:/Mentor/CompLib/2019.1.3/perf_axi_tg_v1_0_8 -polar_v1_0_3 = C:/Mentor/CompLib/2019.1.3/polar_v1_0_3 -prc_v1_3_2 = C:/Mentor/CompLib/2019.1.3/prc_v1_3_2 -processing_system7_vip_v1_0_7 = C:/Mentor/CompLib/2019.1.3/processing_system7_vip_v1_0_7 -proc_sys_reset_v5_0_13 = C:/Mentor/CompLib/2019.1.3/proc_sys_reset_v5_0_13 -pr_axi_shutdown_manager_v1_0_1 = C:/Mentor/CompLib/2019.1.3/pr_axi_shutdown_manager_v1_0_1 -pr_bitstream_monitor_v1_0_1 = C:/Mentor/CompLib/2019.1.3/pr_bitstream_monitor_v1_0_1 -pr_decoupler_v1_0_7 = C:/Mentor/CompLib/2019.1.3/pr_decoupler_v1_0_7 -quadsgmii_v3_4_6 = C:/Mentor/CompLib/2019.1.3/quadsgmii_v3_4_6 -rs_decoder_v9_0_16 = C:/Mentor/CompLib/2019.1.3/rs_decoder_v9_0_16 -rs_encoder_v9_0_15 = C:/Mentor/CompLib/2019.1.3/rs_encoder_v9_0_15 -rxaui_v4_4_6 = C:/Mentor/CompLib/2019.1.3/rxaui_v4_4_6 -sd_fec_v1_1_3 = C:/Mentor/CompLib/2019.1.3/sd_fec_v1_1_3 -sid_v8_0_14 = C:/Mentor/CompLib/2019.1.3/sid_v8_0_14 -soft_ecc_proxy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/soft_ecc_proxy_v1_0_0 -spdif_v2_0_21 = C:/Mentor/CompLib/2019.1.3/spdif_v2_0_21 -srio_gen2_v4_1_6 = C:/Mentor/CompLib/2019.1.3/srio_gen2_v4_1_6 -switch_core_top_v1_0_7 = C:/Mentor/CompLib/2019.1.3/switch_core_top_v1_0_7 -sync_ip = C:/Mentor/CompLib/2019.1.3/sync_ip -tcc_decoder_3gppmm_v2_0_18 = C:/Mentor/CompLib/2019.1.3/tcc_decoder_3gppmm_v2_0_18 -tcc_encoder_3gpp_v5_0_15 = C:/Mentor/CompLib/2019.1.3/tcc_encoder_3gpp_v5_0_15 -tmr_comparator_v1_0_2 = C:/Mentor/CompLib/2019.1.3/tmr_comparator_v1_0_2 -tmr_sem_v1_0_9 = C:/Mentor/CompLib/2019.1.3/tmr_sem_v1_0_9 -tri_mode_ethernet_mac_v9_0_14 = C:/Mentor/CompLib/2019.1.3/tri_mode_ethernet_mac_v9_0_14 -tsn_temac_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tsn_temac_v1_0_4 -videoaxi4s_bridge_v1_0_5 = C:/Mentor/CompLib/2019.1.3/videoaxi4s_bridge_v1_0_5 -viterbi_v9_1_11 = C:/Mentor/CompLib/2019.1.3/viterbi_v9_1_11 -v_ccm_v6_0_15 = C:/Mentor/CompLib/2019.1.3/v_ccm_v6_0_15 -v_cfa_v7_0_14 = C:/Mentor/CompLib/2019.1.3/v_cfa_v7_0_14 -v_cresample_v4_0_14 = C:/Mentor/CompLib/2019.1.3/v_cresample_v4_0_14 -v_dual_splitter_v1_0_9 = C:/Mentor/CompLib/2019.1.3/v_dual_splitter_v1_0_9 -v_enhance_v8_0_15 = C:/Mentor/CompLib/2019.1.3/v_enhance_v8_0_15 -v_gamma_v7_0_15 = C:/Mentor/CompLib/2019.1.3/v_gamma_v7_0_15 -v_osd_v6_0_16 = C:/Mentor/CompLib/2019.1.3/v_osd_v6_0_16 -v_rgb2ycrcb_v7_1_13 = C:/Mentor/CompLib/2019.1.3/v_rgb2ycrcb_v7_1_13 -v_vid_sdi_tx_bridge_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_vid_sdi_tx_bridge_v2_0_0 -v_ycrcb2rgb_v7_1_13 = C:/Mentor/CompLib/2019.1.3/v_ycrcb2rgb_v7_1_13 -xbip_dsp48_macro_v3_0_17 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_macro_v3_0_17 -xfft_v9_0_17 = C:/Mentor/CompLib/2019.1.3/xfft_v9_0_17 -xsdbs_v1_0_2 = C:/Mentor/CompLib/2019.1.3/xsdbs_v1_0_2 -zynq_ultra_ps_e_vip_v1_0_5 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_vip_v1_0_5 -[DefineOptionset] -; Define optionset entries for the various compilers, vmake, and vsim. -; These option sets can be used with the "-optionset " syntax. -; i.e. -; vlog -optionset COMPILEDEBUG top.sv -; vsim -optionset UVMDEBUG my_top -; -; Following are some useful examples. - -; define a vsim optionset for uvm debugging -UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop - -; define a vopt optionset for debugging -VOPTDEBUG = +acc -debugdb - -[encryption] -; For vencrypt and vhencrypt. - -; Controls whether to encrypt whole files by ignoring all protect directives -; (except "viewport" and "interface_viewport") that are present in the input. -; The default is 0, use embedded protect directives to control the encryption. -; Set this to 1 to encrypt whole files by ignoring embedded protect directives. -; wholefile = 0 - -; Sets the data_method to use for the symmetric session key. -; The session key is a symmetric key that is randomly generated for each -; protected region (envelope) and is the heart of all encryption. This is used -; to set the length of the session key to generate and use when encrypting the -; HDL text. Supported values are aes128, aes192, and aes256. -; data_method = aes128 - -; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption -; "recipe" comprising an optional common block, at least one tool block (which -; contains the key public key), and the text to be encrypted. The common block -; and any of the tool blocks may contain rights in the form of the "control" -; directive. The text to be encrypted is specified either by setting -; "wholefile" to 1 or by embedding protect "begin" and "end" directives in -; the input HDL files. - -; Common recipe specification file. This file is optional. Its presence will -; require at least one "toolblock" to be specified. -; Directives such as "author" "author_info" and "data_method", -; as well as the common block license specification, go in this file. -; common = - -; Tool block specification recipe(s). Public key file with optional tool block -; file name. May be multiply-defined; at least one tool block is required if -; a recipe is being specified. -; Key file is a file name with no extension (.deprecated or .active will be -; supplied by the encryption tool). -; Rights file name is optional. -; toolblock = [,]{:[,]} - -; Location of directory containing recipe files. -; The default location is in the product installation directory. -; keyring = $MODEL_TECH/../keyring - -; Enable encryption statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list] -; Add '-' to disable specific statistics. Default is [cmd,msg]. -Stats = cmd,msg - -[vcom] -; VHDL93 variable selects language version as the default. -; Default is VHDL-2002. -; Value of 0 or 1987 for VHDL-1987. -; Value of 1 or 1993 for VHDL-1993. -; Default or value of 2 or 2002 for VHDL-2002. -; Value of 3 or 2008 for VHDL-2008 -; Value of 4 or ams99 for VHDL-AMS-1999 -; Value of 5 or ams07 for VHDL-AMS-2007 -VHDL93 = 2002 - -; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. -; ignoreStandardRealVector = 1 - -; Show source line containing error. Default is off. -; Show_source = 1 - -; Turn off unbound-component warnings. Default is on. -; Show_Warning1 = 0 - -; Turn off process-without-a-wait-statement warnings. Default is on. -; Show_Warning2 = 0 - -; Turn off null-range warnings. Default is on. -; Show_Warning3 = 0 - -; Turn off no-space-in-time-literal warnings. Default is on. -; Show_Warning4 = 0 - -; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. -; Show_Warning5 = 0 - -; Turn off optimization for IEEE std_logic_1164 package. Default is on. -; Optimize_1164 = 0 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Turn on resolving of ambiguous function overloading in favor of the -; "explicit" function declaration (not the one automatically created by -; the compiler for each type declaration). Default is off. -; The .ini file has Explicit enabled so that std_logic_signed/unsigned -; will match the behavior of synthesis tools. -Explicit = 1 - -; Turn off acceleration of the VITAL packages. Default is to accelerate. -; NoVital = 1 - -; Turn off VITAL compliance checking. Default is checking on. -; NoVitalCheck = 1 - -; Ignore VITAL compliance checking errors. Default is to not ignore. -; IgnoreVitalErrors = 1 - -; Turn off VITAL compliance checking warnings. Default is to show warnings. -; Show_VitalChecksWarnings = 0 - -; Turn off PSL assertion warning messages. Default is to show warnings. -; Show_PslChecksWarnings = 0 - -; Enable parsing of embedded PSL assertions. Default is enabled. -; EmbeddedPsl = 0 - -; Keep silent about case statement static warnings. -; Default is to give a warning. -; NoCaseStaticError = 1 - -; Keep silent about warnings caused by aggregates that are not locally static. -; Default is to give a warning. -; NoOthersStaticError = 1 - -; Treat as errors: -; case statement static warnings -; warnings caused by aggregates that are not locally static -; Overrides NoCaseStaticError, NoOthersStaticError settings. -; PedanticErrors = 1 - -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn off "Loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on some limited synthesis rule compliance checking. Checks only: -; -- signals used (read) by a process must be in the sensitivity list -; CheckSynthesis = 1 - -; Activate optimizations on expressions that do not involve signals, -; waits, or function/procedure/task invocations. Default is off. -; ScalarOpts = 1 - -; Turns on lint-style checking. -; Show_Lint = 1 - -; Require the user to specify a configuration for all bindings, -; and do not generate a compile time default binding for the -; component. This will result in an elaboration error of -; 'component not bound' if the user fails to do so. Avoids the rare -; issue of a false dependency upon the unused default binding. -; RequireConfigForAllDefaultBinding = 1 - -; Perform default binding at compile time. -; Default is to do default binding at load time. -; BindAtCompile = 1; - -; Inhibit range checking on subscripts of arrays. Range checking on -; scalars defined with subtypes is inhibited by default. -; NoIndexCheck = 1 - -; Inhibit range checks on all (implicit and explicit) assignments to -; scalar objects defined with subtypes. -; NoRangeCheck = 1 - -; Set the prefix to be honored for synthesis/coverage pragma recognition. -; Default is "". -; AddPragmaPrefix = "" - -; Ignore synthesis and coverage pragmas with this prefix. -; Default is "". -; IgnorePragmaPrefix = "" - -; Turn on code coverage in VHDL design units. Default is off. -; Coverage = sbceft - -; Turn off code coverage in VHDL subprograms. Default is on. -; CoverSub = 0 - -; Automatically exclude VHDL case statement OTHERS choice branches. -; This includes OTHERS choices in selected signal assigment statements. -; Default is to not exclude. -; CoverExcludeDefault = 1 - -; Control compiler and VOPT optimizations that are allowed when -; code coverage is on. Refer to the comment for this in the [vlog] area. -; CoverOpt = 3 - -; Turn on or off clkOpt optimization for code coverage. Default is on. -; CoverClkOpt = 1 - -; Turn on or off clkOpt optimization builtins for code coverage. Default is on. -; CoverClkOptBuiltins = 0 - -; Inform code coverage optimizations to respect VHDL 'H' and 'L' -; values on signals in conditions and expressions, and to not automatically -; convert them to '1' and '0'. Default is to not convert. -; CoverRespectHandL = 0 - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable or disable Focused Expression Coverage analysis for conditions and -; expressions. Focused Expression Coverage data is provided by default when -; expression and/or condition coverage is active. -; CoverFEC = 0 - -; Enable or disable UDP Coverage analysis for conditions and expressions. -; UDP Coverage data is disabled by default when expression and/or condition -; coverage is active. -; CoverUDP = 1 - -; Enable or disable Rapid Expression Coverage mode for conditions and expressions. -; Disabling this would convert non-masking conditions in FEC tables to matching -; input patterns. -; CoverREC = 1 - -; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions -; for expression/condition coverage. -; NOTE: Enabling this may have a negative impact on simulation performance. -; CoverExpandReductionPrefix = 0 - -; Enable or disable short circuit evaluation of conditions and expressions when -; condition or expression coverage is active. Short circuit evaluation is enabled -; by default. -; CoverShortCircuit = 0 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Use this directory for compiler temporary files instead of "work/_temp" -; CompilerTempDir = /tmp - -; Set this to cause the compilers to force data to be committed to disk -; when the files are closed. -; SyncCompilerFiles = 1 - -; Add VHDL-AMS declarations to package STANDARD -; Default is not to add -; AmsStandard = 1 - -; Range and length checking will be performed on array indices and discrete -; ranges, and when violations are found within subprograms, errors will be -; reported. Default is to issue warnings for violations, because subprograms -; may not be invoked. -; NoDeferSubpgmCheck = 0 - -; Turn ON detection of FSMs having single bit current state variable. -; FsmSingle = 1 - -; Turn off reset state transitions in FSM. -; FsmResetTrans = 0 - -; Turn ON detection of FSM Implicit Transitions. -; FsmImplicitTrans = 1 - -; Controls whether or not to show immediate assertions with constant expressions -; in GUI/report/UCDB etc. By default, immediate assertions with constant -; expressions are shown in GUI/report/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Controls how VHDL basic identifiers are stored with the design unit. -; Does not make the language case-sensitive, affects only how declarations -; declared with basic identifiers have their names stored and printed -; (in the GUI, examine, etc.). -; Default is to preserve the case as originally depicted in the VHDL source. -; Value of 0 indicates to change all basic identifiers to lower case. -; PreserveCase = 0 - -; For Configuration Declarations, controls the effect that USE clauses have -; on visibility inside the configuration items being configured. If 1 -; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, -; extend the visibility of objects made visible through USE clauses into nested -; component configurations. -; OldVHDLConfigurationVisibility = 0 - -; Allows VHDL configuration declarations to be in a different library from -; the corresponding configured entity. Default is to not allow this for -; stricter LRM-compliance. -; SeparateConfigLibrary = 1; - -; Determine how mode OUT subprogram parameters of type array and record are treated. -; If 0 (the default), then only VHDL 2008 will do this initialization. -; If 1, always initialize the mode OUT parameter to its default value. -; If 2, do not initialize the mode OUT out parameter. -; Note that prior to release 10.1, all language versions did not initialize mode -; OUT array and record type parameters, unless overridden here via this mechanism. -; In release 10.1 and later, only files compiled with VHDL 2008 will cause this -; initialization, unless overridden here. -; InitOutCompositeParam = 0 - -; Generate symbols debugging database in only some special cases to save on -; the number of files in the library. For other design-units, this database is -; generated on-demand in vsim. -; Default is to to generate debugging database for all design-units. -; SmartDbgSym = 1 - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -; Describe compilation options according to matching file patterns. -; File pattern * matches all printing characters other than '/'. -; File pattern **/x matches all paths containing file/directory x. -; File pattern x/** matches all paths beginning at directory x. -; FileOptMap = (**/*.vhd => -2008); - -; Describe library targets of compilation according to matching file patterns. -; LibMap = (**/*.vhd => work); - -[vlog] -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn off "Loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on Verilog hazard checking (order-dependent accessing of global vars). -; Default is off. -; Hazard = 1 - -; Turn on converting regular Verilog identifiers to uppercase. Allows case -; insensitivity for module names. Default is no conversion. -; UpCase = 1 - -; Activate optimizations on expressions that do not involve signals, -; waits, or function/procedure/task invocations. Default is off. -; ScalarOpts = 1 - -; Turns on lint-style checking. -; Show_Lint = 1 - -; Show source line containing error. Default is off. -; Show_source = 1 - -; Turn on bad option warning. Default is off. -; Show_BadOptionWarning = 1 - -; Revert back to IEEE 1364-1995 syntax, default is 0 (off). -; vlog95compat = 1 - -; Turn off PSL warning messages. Default is to show warnings. -; Show_PslChecksWarnings = 0 - -; Enable parsing of embedded PSL assertions. Default is enabled. -; EmbeddedPsl = 0 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Set the threshold for automatically identifying sparse Verilog memories. -; A memory with total size in bytes equal to or more than the sparse memory -; threshold gets marked as sparse automatically, unless specified otherwise -; in source code or by the +nosparse commandline option of vlog or vopt. -; The default is 1M. (i.e. memories with total size equal -; to or greater than 1Mb are marked as sparse) -; SparseMemThreshold = 1048576 - -; Set the prefix to be honored for synthesis and coverage pragma recognition. -; Default is "". -; AddPragmaPrefix = "" - -; Ignore synthesis and coverage pragmas with this prefix. -; Default is "". -; IgnorePragmaPrefix = "" - -; Set the option to treat all files specified in a vlog invocation as a -; single compilation unit. The default value is set to 0 which will treat -; each file as a separate compilation unit as specified in the P1800 draft standard. -; MultiFileCompilationUnit = 1 - -; Turn on code coverage in Verilog design units. Default is off. -; Coverage = sbceft - -; Automatically exclude Verilog case statement default branches. -; Default is to not automatically exclude defaults. -; CoverExcludeDefault = 1 - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Enable Multi Bit Expression Coverage in a Design, If design has expression with -; multi bit operands, this option enables its Expression Coverage. -; The default value is 0. -; CoverFecMultiBit = 1 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable or disable Focused Expression Coverage analysis for conditions and -; expressions. Focused Expression Coverage data is provided by default when -; expression and/or condition coverage is active. -; CoverFEC = 0 - -; Enable or disable UDP Coverage analysis for conditions and expressions. -; UDP Coverage data is disabled by default when expression and/or condition -; coverage is active. -; CoverUDP = 1 - -; Enable or disable Rapid Expression Coverage mode for conditions and expressions. -; Disabling this would convert non-masking conditions in FEC tables to matching -; input patterns. -; CoverREC = 1 - -; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions -; for expression/condition coverage. -; NOTE: Enabling this may have a negative impact on simulation performance. -; CoverExpandReductionPrefix = 0 - -; Enable or disable short circuit evaluation of conditions and expressions when -; condition or expression coverage is active. Short circuit evaluation is enabled -; by default. -; CoverShortCircuit = 0 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Turn on code coverage in VLOG `celldefine modules, modules containing -; specify blocks, and modules included using vlog -v and -y. Default is off. -; CoverCells = 1 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Control compiler and VOPT optimizations that are allowed when -; code coverage is on. This is a number from 0 to 5, with the following -; meanings (the default is 3): -; 5 -- All allowable optimizations are on. -; 4 -- Turn off removing unreferenced code. -; 3 -- Turn off process, always block and if statement merging. -; 2 -- Turn off expression optimization, converting primitives -; to continuous assignments, VHDL subprogram inlining. -; and VHDL clkOpt (converting FF's to builtins). -; 1 -- Turn off continuous assignment optimizations and clock suppression. -; 0 -- Turn off Verilog module inlining and VHDL arch inlining. -; HOWEVER, if fsm coverage is turned on, optimizations will be forced to -; level 3, with also turning off converting primitives to continuous assigns. -; CoverOpt = 3 - -; Specify the override for the default value of "cross_num_print_missing" -; option for the Cross in Covergroups. If not specified then LRM default -; value of 0 (zero) is used. This is a compile time option. -; SVCrossNumPrintMissingDefault = 0 - -; Setting following to 1 would cause creation of variables which -; would represent the value of Coverpoint expressions. This is used -; in conjunction with "SVCoverpointExprVariablePrefix" option -; in the modelsim.ini -; EnableSVCoverpointExprVariable = 0 - -; Specify the override for the prefix used in forming the variable names -; which represent the Coverpoint expressions. This is used in conjunction with -; "EnableSVCoverpointExprVariable" option of the modelsim.ini -; The default prefix is "expr". -; The variable name is -; variable name => _ -; SVCoverpointExprVariablePrefix = expr - -; Override for the default value of the SystemVerilog covergroup, -; coverpoint, and cross option.goal (defined to be 100 in the LRM). -; NOTE: It does not override specific assignments in SystemVerilog -; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" -; in the [vsim] section can override this value. -; SVCovergroupGoalDefault = 100 - -; Override for the default value of the SystemVerilog covergroup, -; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) -; NOTE: It does not override specific assignments in SystemVerilog -; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" -; in the [vsim] section can override this value. -; SVCovergroupTypeGoalDefault = 100 - -; Specify the override for the default value of "strobe" option for the -; Covergroup Type. This is a compile time option which forces "strobe" to -; a user specified default value and supersedes SystemVerilog specified -; default value of '0'(zero). NOTE: This can be overriden by a runtime -; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. -; SVCovergroupStrobeDefault = 0 - -; Specify the override for the default value of "per_instance" option for the -; Covergroup variables. This is a compile time option which forces "per_instance" -; to a user specified default value and supersedes SystemVerilog specified -; default value of '0'(zero). -; SVCovergroupPerInstanceDefault = 0 - -; Specify the override for the default value of "get_inst_coverage" option for the -; Covergroup variables. This is a compile time option which forces -; "get_inst_coverage" to a user specified default value and supersedes -; SystemVerilog specified default value of '0'(zero). -; SVCovergroupGetInstCoverageDefault = 0 - -; -; A space separated list of resource libraries that contain precompiled -; packages. The behavior is identical to using the "-L" switch. -; -; LibrarySearchPath = [ ...] -LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact - -; The behavior is identical to the "-mixedansiports" switch. Default is off. -; MixedAnsiPorts = 1 - -; Enable SystemVerilog 3.1a $typeof() function. Default is off. -; EnableTypeOf = 1 - -; Only allow lower case pragmas. Default is disabled. -; AcceptLowerCasePragmaOnly = 1 - -; Set the maximum depth permitted for a recursive include file nesting. -; IncludeRecursionDepthMax = 5 - -; Turn ON detection of FSMs having single bit current state variable. -; FsmSingle = 1 - -; Turn off reset state transitions in FSM. -; FsmResetTrans = 0 - -; Turn off detections of FSMs having x-assignment. -; FsmXAssign = 0 - -; Turn ON detection of FSM Implicit Transitions. -; FsmImplicitTrans = 1 - -; List of file suffixes which will be read as SystemVerilog. White space -; in extensions can be specified with a back-slash: "\ ". Back-slashes -; can be specified with two consecutive back-slashes: "\\"; -; SvFileSuffixes = sv svp svh - -; This setting is the same as the vlog -sv command line switch. -; Enables SystemVerilog features and keywords when true (1). -; When false (0), the rules of IEEE Std 1364-2005 are followed and -; SystemVerilog keywords are ignored. -; Svlog = 0 - -; Prints attribute placed upon SV packages during package import -; when true (1). The attribute will be ignored when this -; entry is false (0). The attribute name is "mti_design_element_load_message". -; The value of this attribute is a string literal. -; Default is true (1). -; PrintSVPackageLoadingAttribute = 1 - -; Do not show immediate assertions with constant expressions in -; GUI/reports/UCDB etc. By default immediate assertions with constant -; expressions are shown in GUI/reports/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Controls if untyped parameters that are initialized with values greater -; than 2147483647 are mapped to generics of type INTEGER or ignored. -; If mapped to VHDL Integers, values greater than 2147483647 -; are mapped to negative values. -; Default is to map these parameter to generic of type INTEGER -; ForceUnsignedToVHDLInteger = 1 - -; Enable AMS wreal (wired real) extensions. Default is 0. -; WrealType = 1 - -; Controls SystemVerilog Language Extensions. These options enable -; some non-LRM compliant behavior. -; SvExtensions = [+|-][,[+|-]*] - -; Generate symbols debugging database in only some special cases to save on -; the number of files in the library. For other design-units, this database is -; generated on-demand in vsim. -; Default is to to generate debugging database for all design-units. -; SmartDbgSym = 1 - -; Controls how $unit library entries are named. Valid options are: -; "file" (generate name based on the first file on the command line) -; "du" (generate name based on first design unit following an item -; found in $unit scope) -; CUAutoName = file - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -[sccom] -; Enable use of SCV include files and library. Default is off. -; UseScv = 1 - -; Add C++ compiler options to the sccom command line by using this variable. -; CppOptions = -g - -; Use custom C++ compiler located at this path rather than the default path. -; The path should point directly at a compiler executable. -; CppPath = /usr/bin/g++ - -; Specify the compiler version from the list of support GNU compilers. -; examples 4.7.4, 5.3.0, 7.4.0 -; CppInstall = 7.4.0 - -; Enable verbose messages from sccom. Default is off. -; SccomVerbose = 1 - -; sccom logfile. Default is no logfile. -; SccomLogfile = sccom.log - -; Enable use of SC_MS include files and library. Default is off. -; UseScMs = 1 - -; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. -; Sc22Mode = 1 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -; Enable use of UVMC library. Default is off. -; UseUvmc = 1 - -[vopt] -; Turn on code coverage in vopt. Default is off. -; Coverage = sbceft - -; enable or disable param saving in UCDB. -; CoverageSaveParam = 0 - -; Control compiler optimizations that are allowed when -; code coverage is on. Refer to the comment for this in the [vlog] area. -; CoverOpt = 3 - -; Controls set of CoverConstructs that are being considered for Coverage -; Collection. -; Some of Valid options are: default,set1,set2 -; Covermode = default - -; Controls set of HDL cover constructs that would be considered(or not considered) -; for Coverage Collection. (Default corresponds to covermode default). -; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". -; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Enable Multi Bit Expression Coverage in a Design, If design has expression with -; multi bit operands, this option enables its Expression Coverage. -; The default value is 0. -; CoverFecMultiBit = 1 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Do not show immediate assertions with constant expressions in -; GUI/reports/UCDB etc. By default immediate assertions with constant -; expressions are shown in GUI/reports/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Set the maximum number of iterations permitted for a generate loop. -; Restricting this permits the implementation to recognize infinite -; generate loops. -; GenerateLoopIterationMax = 100000 - -; Set the maximum depth permitted for a recursive generate instantiation. -; Restricting this permits the implementation to recognize infinite -; recursions. -; GenerateRecursionDepthMax = 200 - -; Set the number of processes created during the code generation phase. -; By default a heuristic is used to set this value. This may be set to 0 -; to disable this feature completely. -; ParallelJobs = 0 - -; Controls SystemVerilog Language Extensions. These options enable -; some non-LRM compliant behavior. -; SvExtensions = [+|-][,[+|-]*] - -; Load the specified shared objects with the RTLD_GLOBAL flag. -; This gives global visibility to all symbols in the shared objects, -; meaning that subsequently loaded shared objects can bind to symbols -; in the global shared objects. The list of shared objects should -; be whitespace delimited. This option is not supported on the -; Windows or AIX platforms. -; GlobalSharedObjectList = example1.so example2.so example3.so - -; Disable SystemVerilog elaboration system task messages -; IgnoreSVAInfo = 1 -; IgnoreSVAWarning = 1 -; IgnoreSVAError = 1 -; IgnoreSVAFatal = 1 - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -[vsim] -; vopt flow -; Set to turn on automatic optimization of a design. -; Default is on -VoptFlow = 1 - -; Simulator resolution -; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. -Resolution = fs - -; Disable certain code coverage exclusions automatically. -; Assertions and FSM are exluded from the code coverage by default -; Set AutoExclusionsDisable = fsm to enable code coverage for fsm -; Set AutoExclusionsDisable = assertions to enable code coverage for assertions -; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions -; Or specify comma or space separated list -;AutoExclusionsDisable = fsm,assertions - -; User time unit for run commands -; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the -; unit specified for Resolution. For example, if Resolution is 100ps, -; then UserTimeUnit defaults to ps. -; Should generally be set to default. -UserTimeUnit = default - -; Default run length -RunLength = 100 - -; Maximum iterations that can be run without advancing simulation time -IterationLimit = 10000000 - -; Specify libraries to be searched for precompiled modules -; LibrarySearchPath = [ ...] - -; Set XPROP assertion fail limit. Default is 5. -; Any positive integer, -1 for infinity. -; XpropAssertionLimit = 5 - -; Control PSL and Verilog Assume directives during simulation -; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts -; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts -; SimulateAssumeDirectives = 1 - -; Control the simulation of PSL and SVA -; These switches can be overridden by the vsim command line switches: -; -psl, -nopsl, -sva, -nosva. -; Set SimulatePSL = 0 to disable PSL simulation -; Set SimulatePSL = 1 to enable PSL simulation (default) -; SimulatePSL = 1 -; Set SimulateSVA = 0 to disable SVA simulation -; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) -; SimulateSVA = 1 - -; Control SVA and VHDL immediate assertion directives during simulation -; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts -; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts -; SimulateImmedAsserts = 1 - -; License feature mappings for Verilog and VHDL -; qhsimvh Single language VHDL license -; qhsimvl Single language Verilog license -; msimhdlsim Language neutral license for either Verilog or VHDL -; msimhdlmix Second language only, language neutral license for either -; Verilog or VHDL -; -; Directives to license manager can be set either as single value or as -; space separated multi-values: -; vhdl Immediately checkout and hold a VHDL license (i.e., one of -; qhsimvh, msimhdlsim, or msimhdlmix) -; vlog Immediately checkout and hold a Verilog license (i.e., one of -; qhsimvl, msimhdlsim, or msimhdlmix) -; plus Immediately checkout and hold a VHDL license and a Verilog license -; noqueue Do not wait in the license queue when a license is not available -; viewsim Try for viewer license but accept simulator license(s) instead -; of queuing for viewer license (PE ONLY) -; noviewer Disable checkout of msimviewer license feature (PE ONLY) -; noslvhdl Disable checkout of qhsimvh license feature -; noslvlog Disable checkout of qhsimvl license feature -; nomix Disable checkout of msimhdlmix license feature -; nolnl Disable checkout of msimhdlsim license feature -; mixedonly Disable checkout of qhsimvh and qhsimvl license features -; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features -; -; Examples (remove ";" comment character to activate licensing directives): -; Single directive: -; License = plus -; Multi-directive (Note: space delimited directives): -; License = noqueue plus - -; Severity level of a VHDL assertion message or of a SystemVerilog severity system task -; which will cause a running simulation to stop. -; VHDL assertions and SystemVerilog severity system task that occur with the -; given severity or higher will cause a running simulation to stop. -; This value is ignored during elaboration. -; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal -BreakOnAssertion = 3 - -; Severity level of a tool message which will cause a running simulation to -; stop. This value is ignored during elaboration. Default is to not break. -; 0 = Note 1 = Warning 2 = Error 3 = Fatal -;BreakOnMessage = 2 - -; The class debug feature enables more visibility and tracking of class instances -; during simulation. By default this feature is disabled (0). To enable this -; feature set ClassDebug to 1. -; ClassDebug = 1 - -; Message Format conversion specifications: -; %S - Severity Level of message/assertion -; %R - Text of message -; %T - Time of message -; %D - Delta value (iteration number) of Time -; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected -; %i - Instance/Region/Signal pathname with Process name (if available) -; %I - shorthand for one of these: -; " %K: %i" -; " %K: %i File: %F" (when path is not Process or Signal) -; except that the %i in this case does not report the Process name -; %O - Process name -; %P - Instance/Region path without leaf process -; %F - File name -; %L - Line number; if assertion message, then line number of assertion or, if -; assertion is in a subprogram, line from which the call is made -; %u - Design unit name in form library.primary -; %U - Design unit name in form library.primary(secondary) -; %% - The '%' character itself -; -; If specific format for Severity Level is defined, use that format. -; Else, for a message that occurs during elaboration: -; -- Failure/Fatal message in VHDL region that is not a Process, and in -; certain non-VHDL regions, uses MessageFormatBreakLine; -; -- Failure/Fatal message otherwise uses MessageFormatBreak; -; -- Note/Warning/Error message uses MessageFormat. -; Else, for a message that occurs during runtime and triggers a breakpoint because -; of the BreakOnAssertion setting: -; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; -; -- otherwise uses MessageFormatBreak. -; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. -; -; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" -; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" -; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" -; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" - -; Error File - alternate file for storing error messages -; ErrorFile = error.log - -; Simulation Breakpoint messages -; This flag controls the display of function names when reporting the location -; where the simulator stops because of a breakpoint or fatal error. -; Example with function name: # Break in Process ctr at counter.vhd line 44 -; Example without function name: # Break at counter.vhd line 44 -; Default value is 1. -ShowFunctions = 1 - -; Default radix for all windows and commands. -; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned -; Flags may be one of: enumnumeric, showbase, wreal -DefaultRadix = hexadecimal -DefaultRadixFlags = showbase -; Set to 1 for make the signal_force VHDL and Verilog functions use the -; default radix when processing the force value. Prior to 10.2 signal_force -; used the default radix, now it always uses symbolic unless value explicitly indicates base -;SignalForceFunctionUseDefaultRadix = 0 - -; VSIM Startup command -; Startup = do startup.do - -; VSIM Shutdown file -; Filename to save u/i formats and configurations. -; ShutdownFile = restart.do -; To explicitly disable auto save: -; ShutdownFile = --disable-auto-save - -; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. -; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. -; BatchMode = 1 - -; File for saving command transcript when -batch option used -; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero -; default is unset so command transcript only goes to stdout for better performance -; BatchTranscriptFile = transcript - -; File for saving command transcript, this option is ignored when -batch option is used -TranscriptFile = transcript - -; Transcript file long line wrapping mode(s) -; mode == 0 :: no wrapping, line recorded as is -; mode == 1 :: wrap at first whitespace after WSColumn -; or at Column. -; mode == 2 :: wrap as above, but add continuation -; character ('\') at end of each wrapped line -; -; WrapMode = 0 -; WrapColumn = 30000 -; WrapWSColumn = 27000 - -; File for saving command history -; CommandHistory = cmdhist.log - -; Specify whether paths in simulator commands should be described -; in VHDL or Verilog format. -; For VHDL, PathSeparator = / -; For Verilog, PathSeparator = . -; Must not be the same character as DatasetSeparator. -PathSeparator = / - -; Specify the dataset separator for fully rooted contexts. -; The default is ':'. For example: sim:/top -; Must not be the same character as PathSeparator. -DatasetSeparator = : - -; Specify a unique path separator for the Signal Spy set of functions. -; The default will be to use the PathSeparator variable. -; Must not be the same character as DatasetSeparator. -; SignalSpyPathSeparator = / - -; Used to control parsing of HDL identifiers input to the tool. -; This includes CLI commands, vsim/vopt/vlog/vcom options, -; string arguments to FLI/VPI/DPI calls, etc. -; If set to 1, accept either Verilog escaped Id syntax or -; VHDL extended id syntax, regardless of source language. -; If set to 0, the syntax of the source language must be used. -; Each identifier in a hierarchical name may need different syntax, -; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or -; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" -; GenerousIdentifierParsing = 1 - -; Disable VHDL assertion messages -; IgnoreNote = 1 -; IgnoreWarning = 1 -; IgnoreError = 1 -; IgnoreFailure = 1 - -; Disable SystemVerilog assertion messages -; IgnoreSVAInfo = 1 -; IgnoreSVAWarning = 1 -; IgnoreSVAError = 1 -; IgnoreSVAFatal = 1 - -; Do not print any additional information from Severity System tasks. -; Only the message provided by the user is printed along with severity -; information. -; SVAPrintOnlyUserMessage = 1; - -; Default force kind. May be freeze, drive, deposit, or default -; or in other terms, fixed, wired, or charged. -; A value of "default" will use the signal kind to determine the -; force kind, drive for resolved signals, freeze for unresolved signals -; DefaultForceKind = freeze - -; Control the iteration of events when a VHDL signal is forced to a value -; This flag can be set to honour the signal update event in next iteration, -; the default is to update and propagate in the same iteration. -; ForceSigNextIter = 1 - -; Enable simulation statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; If zero, open files when elaborated; otherwise, open files on -; first read or write. Default is 0. -; DelayFileOpen = 1 - -; Control VHDL files opened for write. -; 0 = Buffered, 1 = Unbuffered -UnbufferedOutput = 0 - -; Control the number of VHDL files open concurrently. -; This number should always be less than the current ulimit -; setting for max file descriptors. -; 0 = unlimited -ConcurrentFileLimit = 40 - -; If nonzero, close files as soon as there is either an explicit call to -; file_close, or when the file variable's scope is closed. When zero, a -; file opened in append mode is not closed in case it is immediately -; reopened in append mode; otherwise, the file will be closed at the -; point it is reopened. -; AppendClose = 1 - -; Control the number of hierarchical regions displayed as -; part of a signal name shown in the Wave window. -; A value of zero tells VSIM to display the full name. -; The default is 0. -; WaveSignalNameWidth = 0 - -; Turn off warnings when changing VHDL constants and generics -; Default is 1 to generate warning messages -; WarnConstantChange = 0 - -; Turn off warnings from accelerated versions of the std_logic_arith, -; std_logic_unsigned, and std_logic_signed packages. -; StdArithNoWarnings = 1 - -; Turn off warnings from accelerated versions of the IEEE numeric_std -; and numeric_bit packages. -; NumericStdNoWarnings = 1 - -; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names -; in the design hierarchy. -; This style is controlled by the value of the GenerateFormat -; value described next. Default is to use new-style names, which -; comprise the generate statement label, '(', the value of the generate -; parameter, and a closing ')'. -; Set this to 1 to use old-style names. -; OldVhdlForGenNames = 1 - -; Control the format of the old-style VHDL FOR generate statement region -; name for each iteration. Do not quote the value. -; The format string here must contain the conversion codes %s and %d, -; in that order, and no other conversion codes. The %s represents -; the generate statement label; the %d represents the generate parameter value -; at a particular iteration (this is the position number if the generate parameter -; is of an enumeration type). Embedded whitespace is allowed (but discouraged); -; leading and trailing whitespace is ignored. -; Application of the format must result in a unique region name over all -; loop iterations for a particular immediately enclosing scope so that name -; lookup can function properly. The default is %s__%d. -; GenerateFormat = %s__%d - -; Enable more efficient logging of VHDL Variables. -; Logging VHDL variables without this enabled, while possible, is very -; inefficient. Enabling this will provide a more efficient logging methodology -; at the expense of more memory usage. By default this feature is disabled (0). -; To enabled this feature, set this variable to 1. -; VhdlVariableLogging = 1 - -; Enable logging of VHDL access type variables and their designated objects. -; This setting will allow both variables of an access type ("access variables") -; and their designated objects ("access objects") to be logged. Logging a -; variable of an access type will automatically also cause the designated -; object(s) of that variable to be logged as the simulation progresses. -; Further, enabling this allows access objects to be logged by name. By default -; this feature is disabled (0). To enable this feature, set this variable to 1. -; Enabling this will automatically enable the VhdlVariableLogging feature also. -; AccessObjDebug = 1 - -; Make each VHDL package in a PDU has its own separate copy of the package instead -; of sharing the package between PDUs. The default is to share packages. -; To ensure that each PDU has its own set of packages, set this variable to 1. -; VhdlSeparatePduPackage = 1 - -; Specify whether checkpoint files should be compressed. -; The default is 1 (compressed). -; CheckpointCompressMode = 0 - -; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. -; Use custom gcc compiler located at this path rather than the default path. -; The path should point directly at a compiler executable. -; DpiCppPath = /bin/gcc -; -; Specify the compiler version from the list of support GNU compilers. -; examples 4.7.4, 5.3.0, 7.4.0 -; DpiCppInstall = 7.4.0 - -; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. -; The term "out-of-the-blue" refers to SystemVerilog export function calls -; made from C functions that don't have the proper context setup -; (as is the case when running under "DPI-C" import functions). -; When this is enabled, one can call a DPI export function -; (but not task) from any C code. -; the setting of this variable can be one of the following values: -; 0 : dpioutoftheblue call is disabled (default) -; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. -; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. -; DpiOutOfTheBlue = 1 - -; Specify whether continuous assignments are run before other normal priority -; processes scheduled in the same iteration. This event ordering minimizes race -; differences between optimized and non-optimized designs, and is the default -; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set -; ImmediateContinuousAssign to 0. -; The default is 1 (enabled). -; ImmediateContinuousAssign = 0 - -; List of dynamically loaded objects for Verilog PLI applications -; Veriuser = veriuser.sl - -; Which default VPI object model should the tool conform to? -; The 1364 modes are Verilog-only, for backwards compatibility with older -; libraries, and SystemVerilog objects are not available in these modes. -; -; In the absence of a user-specified default, the tool default is the -; latest available LRM behavior. -; Options for PliCompatDefault are: -; VPI_COMPATIBILITY_VERSION_1364v1995 -; VPI_COMPATIBILITY_VERSION_1364v2001 -; VPI_COMPATIBILITY_VERSION_1364v2005 -; VPI_COMPATIBILITY_VERSION_1800v2005 -; VPI_COMPATIBILITY_VERSION_1800v2008 -; -; Synonyms for each string are also recognized: -; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) -; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) -; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) -; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) -; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) - - -; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 - -; Specify whether the Verilog system task $fopen or vpi_mcd_open() -; will create directories that do not exist when opening the file -; in "a" or "w" mode. -; The default is 0 (do not create non-existent directories) -; CreateDirForFileAccess = 1 - -; Specify default options for the restart command. Options can be one -; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions -; DefaultRestartOptions = -force - - -; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. -; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. -; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". -; The list of options must be delimited by commas, without spaces or tabs. -; -; Some examples -; To turn on all available UVM-aware debug features: -; UVMControl = all -; To turn on the struct window, mesage logging, and transaction logging: -; UVMControl = struct,msglog,trlog -; To turn on all options except certe: -; UVMControl = all,-certe -; To completely disable all UVM-aware debug functionality: -; UVMControl = disable - -; Specify the WildcardFilter setting. -; A space separated list of object types to be excluded when performing -; wildcard matches with log, wave, etc commands. The default value for this variable is: -; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" -; See "Using the WildcardFilter Preference Variable" in the documentation for -; details on how to use this variable and for descriptions of the filter types. -WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile - -; Specify the WildcardSizeThreshold setting. -; This integer setting specifies the size at which objects will be excluded when -; performing wildcard matches with log, wave, etc commands. Objects of size equal -; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard -; matches. The size is a simple calculation of number of bits or items in the object. -; The default value is 8k (8192). Setting this value to 0 will disable the checking -; of object size against this threshold and allow all objects of any size to be logged. -WildcardSizeThreshold = 8192 - -; Specify whether warning messages are output when objects are filtered out due to the -; WildcardSizeThreshold. The default is 0 (no messages generated). -WildcardSizeThresholdVerbose = 0 - -; Turn on (1) or off (0) WLF file compression. -; The default is 1 (compress WLF file). -; WLFCompress = 0 - -; Specify whether to save all design hierarchy (1) in the WLF file -; or only regions containing logged signals (0). -; The default is 0 (save only regions with logged signals). -; WLFSaveAllRegions = 1 - -; WLF file time limit. Limit WLF file by time, as closely as possible, -; to the specified amount of simulation time. When the limit is exceeded -; the earliest times get truncated from the file. -; If both time and size limits are specified the most restrictive is used. -; UserTimeUnits are used if time units are not specified. -; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} -; WLFTimeLimit = 0 - -; WLF file size limit. Limit WLF file size, as closely as possible, -; to the specified number of megabytes. If both time and size limits -; are specified then the most restrictive is used. -; The default is 0 (no limit). -; WLFSizeLimit = 1000 - -; Specify whether or not a WLF file should be deleted when the -; simulation ends. A value of 1 will cause the WLF file to be deleted. -; The default is 0 (do not delete WLF file when simulation ends). -; WLFDeleteOnQuit = 1 - -; Specify whether or not a WLF file should be optimized during -; simulation. If set to 0, the WLF file will not be optimized. -; The default is 1, optimize the WLF file. -; WLFOptimize = 0 - -; Specify the name of the WLF file. -; The default is vsim.wlf -; WLFFilename = vsim.wlf - -; Specify whether to lock the WLF file. -; Locking the file prevents other invocations of ModelSim/Questa tools from -; inadvertently overwriting the WLF file. -; The default is 1, lock the WLF file. -; WLFFileLock = 0 - -; Specify the update interval for the WLF file in live simulation. -; The interval is given in seconds. -; The value is the smallest interval between WLF file updates. The WLF file -; will be flushed (updated) after (at least) the interval has elapsed, ensuring -; that the data is correct when viewed from a separate viewer. -; A value of 0 means that no updating will occur. -; The default value is 10 seconds. -; WLFUpdateInterval = 10 - -; Specify the WLF cache size limit for WLF files. -; The value is given in megabytes. A value of 0 turns off the cache. -; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). -; On Windows, the default value is 1000 (megabytes) to help to avoid filling -; process memory. -; WLFSimCacheSize allows a different cache size to be set for a live simulation -; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize -; is not set, it defaults to the WLFCacheSize value. -; WLFCacheSize = 2000 -; WLFSimCacheSize = 500 - -; Specify the WLF file event collapse mode. -; 0 = Preserve all events and event order. (same as -wlfnocollapse) -; 1 = Only record values of logged objects at the end of a simulator iteration. -; (same as -wlfcollapsedelta) -; 2 = Only record values of logged objects at the end of a simulator time step. -; (same as -wlfcollapsetime) -; The default is 1. -; WLFCollapseMode = 0 - -; Specify whether WLF file logging can use threads on multi-processor machines. -; If 0, no threads will be used; if 1, threads will be used if the system has -; more than one processor. -; WLFUseThreads = 1 - -; Specify the size of objects that will trigger "large object" messages -; at log/wave/list time. The size calculation of the object is the same as that -; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. -; Setting LargeObjectSize to 0 will disable these messages. -; LargeObjectSize = 500000 - -; Specify the depth of stack frames returned by $stacktrace([level]). -; This depth will be picked up when the optional 'level' argument -; is not specified or its value is not a positive integer. -; StackTraceDepth = 100 - -; Turn on/off undebuggable SystemC type warnings. Default is on. -; ShowUndebuggableScTypeWarning = 0 - -; Turn on/off unassociated SystemC name warnings. Default is off. -; ShowUnassociatedScNameWarning = 1 - -; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. -; ScShowIeeeDeprecationWarnings = 1 - -; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. -; For SystemC-2.3.2 the valid values are 0,1 and 2 -; 0 = SC_SIGNAL_WRITE_CHECK_DISABLE_ -; 1 = SC_SIGNAL_WRITE_CHECK_DEFAULT_ -; 2 = SC_SIGNAL_WRITE_CHECK_CONFLICT_ -; For SystemC-2.2 the valid values are 0 and 1 -; 0 = DISABLE -; 1 = ENABLE -; ScEnableScSignalWriteCheck = 1 - -; Set SystemC default time unit. -; Set to fs, ps, ns, us, ms, or sec with optional -; prefix of 1, 10, or 100. The default is 1 ns. -; The ScTimeUnit value is honored if it is coarser than Resolution. -; If ScTimeUnit is finer than Resolution, it is set to the value -; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, -; then the default time unit will be 1 ns. However if Resolution -; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. -ScTimeUnit = ns - -; Set SystemC sc_main stack size. The stack size is set as an integer -; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or -; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends -; on the amount of data on the sc_main() stack and the memory required -; to succesfully execute the longest function call chain of sc_main(). -ScMainStackSize = 10 Mb - -; Set SystemC thread stack size. The stack size is set as an integer -; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or -; Gb(Giga-byte). The stack size for sc_thread depends -; on the amount of data on the sc_thread stack and the memory required -; to succesfully execute the thread. -; ScStackSize = 1 Mb - -; Turn on/off execution of remainder of sc_main upon quitting the current -; simulation session. If the cumulative length of sc_main() in terms of -; simulation time units is less than the length of the current simulation -; run upon quit or restart, sc_main() will be in the middle of execution. -; This switch gives the option to execute the remainder of sc_main upon -; quitting simulation. The drawback of not running sc_main till the end -; is memory leaks for objects created by sc_main. If on, the remainder of -; sc_main will be executed ignoring all delays. This may cause the simulator -; to crash if the code in sc_main is dependent on some simulation state. -; Default is on. -ScMainFinishOnQuit = 1 - -; Enable calling of the DPI export taks/functions from the -; SystemC start_of_simulation() callback. -; The default is off. -; EnableDpiSosCb = 1 - - -; Set the SCV relationship name that will be used to identify phase -; relations. If the name given to a transactor relation matches this -; name, the transactions involved will be treated as phase transactions -ScvPhaseRelationName = mti_phase - -; Customize the vsim kernel shutdown behavior at the end of the simulation. -; Some common causes of the end of simulation are $finish (implicit or explicit), -; sc_stop(), tf_dofinish(), and assertion failures. -; This should be set to "ask", "exit", or "stop". The default is "ask". -; "ask" -- In batch mode, the vsim kernel will abruptly exit. -; In GUI mode, a dialog box will pop up and ask for user confirmation -; whether or not to quit the simulation. -; "stop" -- Cause the simulation to stay loaded in memory. This can make some -; post-simulation tasks easier. -; "exit" -- The simulation will abruptly exit without asking for any confirmation. -; "final" -- Run SystemVerilog final blocks then behave as "stop". -; Note: This variable can be overridden with the vsim "-onfinish" command line switch. -OnFinish = ask - -; Print pending deferred assertion messages. -; Deferred assertion messages may be scheduled after the $finish in the same -; time step. Deferred assertions scheduled to print after the $finish are -; printed before exiting with severity level NOTE since it's not known whether -; the assertion is still valid due to being printed in the active region -; instead of the reactive region where they are normally printed. -; OnFinishPendingAssert = 1; - -; Print "simstats" result. Default is 0. -; 0 == do not print simstats -; 1 == print at end of simulation -; 2 == print at end of each run command and end of simulation -; PrintSimStats = 1 - -; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages -; AssertFile = assert.log - -; Enable assertion counts. Default is off. -; AssertionCounts = 1 - -; Run simulator in assertion debug mode. Default is off. -; AssertionDebug = 1 - -; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. -; AssertionEnable = 0 - -; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. -; Any positive integer, -1 for infinity. -; AssertionLimit = 1 - -; Turn on/off concurrent assertion pass log. Default is off. -; Assertion pass logging is only enabled when assertion is browseable -; and assertion debug is enabled. -; AssertionPassLog = 1 - -; Turn on/off PSL concurrent assertion fail log. Default is on. -; The flag does not affect SVA -; AssertionFailLog = 0 - -; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. -; AssertionFailLocalVarLog = 0 - -; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. -; 0 = Continue 1 = Break 2 = Exit -; AssertionFailAction = 1 - -; Enable the active thread monitor in the waveform display when assertion debug is enabled. -; AssertionActiveThreadMonitor = 1 - -; Control how many waveform rows will be used for displaying the active threads. Default is 5. -; AssertionActiveThreadMonitorLimit = 5 - -; Assertion thread limit after which assertion would be killed/switched off. -; The default is -1 (unlimited). If the number of threads for an assertion go -; beyond this limit, the assertion would be either switched off or killed. This -; limit applies to only assert directives. -;AssertionThreadLimit = -1 - -; Action to be taken once the assertion thread limit is reached. Default -; is kill. It can have a value of off or kill. In case of kill, all the existing -; threads are terminated and no new attempts are started. In case of off, the -; existing attempts keep on evaluating but no new attempts are started. This -; variable applies to only assert directives. -;AssertionThreadLimitAction = kill - -; Cover thread limit after which cover would be killed/switched off. -; The default is -1 (unlimited). If the number of threads for a cover go -; beyond this limit, the cover would be either switched off or killed. This -; limit applies to only cover directives. -;CoverThreadLimit = -1 - -; Action to be taken once the cover thread limit is reached. Default -; is kill. It can have a value of off or kill. In case of kill, all the existing -; threads are terminated and no new attempts are started. In case of off, the -; existing attempts keep on evaluating but no new attempts are started. This -; variable applies to only cover directives. -;CoverThreadLimitAction = kill - - -; By default immediate assertions do not participate in Assertion Coverage calculations -; unless they are executed. This switch causes all immediate assertions in the design -; to participate in Assertion Coverage calculations, whether attempted or not. -; UnattemptedImmediateAssertions = 0 - -; By default immediate covers participate in Coverage calculations -; whether they are attempted or not. This switch causes all unattempted -; immediate covers in the design to stop participating in Coverage -; calculations. -; UnattemptedImmediateCovers = 0 - -; By default pass action block is not executed for assertions on vacuous -; success. The following variable is provided to enable execution of -; pass action block on vacuous success. The following variable is only effective -; if the user does not disable pass action block execution by using either -; system tasks or CLI. Also there is a performance penalty for enabling -; the following variable. -;AssertionEnableVacuousPassActionBlock = 1 - -; As per strict 1850-2005 PSL LRM, an always property can either pass -; or fail. However, by default, Questa reports multiple passes and -; multiple fails on top always/never property (always/never operator -; is the top operator under Verification Directive). The reason -; being that Questa reports passes and fails on per attempt of the -; top always/never property. Use the following flag to instruct -; Questa to strictly follow LRM. With this flag, all assert/never -; directives will start an attempt once at start of simulation. -; The attempt can either fail, match or match vacuously. -; For e.g. if always is the top operator under assert, the always will -; keep on checking the property at every clock. If the property under -; always fails, the directive will be considered failed and no more -; checking will be done for that directive. A top always property, -; if it does not fail, will show a pass at end of simulation. -; The default value is '0' (i.e. zero is off). For example: -; PslOneAttempt = 1 - -; Specify the number of clock ticks to represent infinite clock ticks. -; This affects eventually!, until! and until_!. If at End of Simulation -; (EOS) an active strong-property has not clocked this number of -; clock ticks then neither pass or fail (vacuous match) is returned -; else respective fail/pass is returned. The default value is '0' (zero) -; which effectively does not check for clock tick condition. For example: -; PslInfinityThreshold = 5000 - -; Control how many thread start times will be preserved for ATV viewing for a given assertion -; instance. Default is -1 (ALL). -; ATVStartTimeKeepCount = -1 - -; Turn on/off code coverage -; CodeCoverage = 0 - -; This option applies to condition and expression coverage UDP tables. It -; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. -; If this option is used and a match occurs in more than one row in the UDP table, -; none of the counts for all matching rows is incremented. By default, counts are -; incremented for all matching rows. -; CoverCountAll = 1 - -; Turn off automatic inclusion of VHDL integers in toggle coverage. Default -; is to include them. -; ToggleNoIntegers = 1 - -; Set the maximum number of values that are collected for toggle coverage of -; VHDL integers. Default is 100; -; ToggleMaxIntValues = 100 - -; Set the maximum number of values that are collected for toggle coverage of -; Verilog real. Default is 100; -; ToggleMaxRealValues = 100 - -; Turn on automatic inclusion of Verilog integers in toggle coverage, except -; for enumeration types. Default is to include them. -; ToggleVlogIntegers = 0 - -; Turn on automatic inclusion of Verilog real type in toggle coverage, except -; for shortreal types. Default is to not include them. -; ToggleVlogReal = 1 - -; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays -; and VHDL arrays-of-arrays in toggle coverage. -; Default is to not include them. -; ToggleFixedSizeArray = 1 - -; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, -; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. -; This leads to a longer simulation time with bigger arrays covered with toggle coverage. -; Default is 1024. -; ToggleMaxFixedSizeArray = 1024 - -; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized -; one-dimensional packed vectors for toggle coverage. Default is 0. -; TogglePackedAsVec = 0 - -; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for -; toggle coverage. Default is 0. -; ToggleVlogEnumBits = 0 - -; Turn off automatic inclusion of VHDL records in toggle coverage. -; Default is to include them. -; ToggleVHDLRecords = 0 - -; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. -; For unlimited width, set to 0. -; ToggleWidthLimit = 128 - -; Limit the counts that are tracked for toggle coverage. When all edges for a bit have -; reached this count, further activity on the bit is ignored. Default is 1. -; For unlimited counts, set to 0. -; ToggleCountLimit = 1 - -; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. -; Following is the toggle coverage calculation criteria based on extended toggle mode: -; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). -; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. -; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. -; ExtendedToggleMode = 3 - -; Enable toggle statistics collection only for ports. Default is 0. -; TogglePortsOnly = 1 - -; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has -; reached this count, further tracking of the input patterns linked to it is ignored. -; Default is 1. For unlimited counts, set to 0. -; NOTE: Changing this value from its default value may affect simulation performance. -; FecCountLimit = 1 - -; Limit the counts that are tracked for UDP Coverage. When a bin has -; reached this count, further tracking of the input patterns linked to it is ignored. -; Default is 1. For unlimited counts, set to 0. -; NOTE: Changing this value from its default value may affect simulation performance. -; UdpCountLimit = 1 - -; Control toggle coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either -; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; ToggleDeglitchPeriod = 10.0ps - -; Turn on/off all PSL/SVA cover directive enables. Default is on. -; CoverEnable = 0 - -; Turn on/off PSL/SVA cover log. Default is off "0". -; CoverLog = 1 - -; Set "at_least" value for all PSL/SVA cover directives. Default is 1. -; CoverAtLeast = 2 - -; Set "limit" value for all PSL/SVA cover directives. Default is -1. -; Any positive integer, -1 for infinity. -; CoverLimit = 1 - -; Specify the coverage database filename. -; Default is "" (i.e. database is NOT automatically saved on close). -; UCDBFilename = vsim.ucdb - -; Specify the maximum limit for the number of Cross (bin) products reported -; in XML and UCDB report against a Cross. A warning is issued if the limit -; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this -; setting. -; MaxReportRhsSVCrossProducts = 1000 - -; Specify the override for the "auto_bin_max" option for the Covergroups. -; If not specified then value from Covergroup "option" is used. -; SVCoverpointAutoBinMax = 64 - -; Specify the override for the value of "cross_num_print_missing" -; option for the Cross in Covergroups. If not specified then value -; specified in the "option.cross_num_print_missing" is used. This -; is a runtime option. NOTE: This overrides any "cross_num_print_missing" -; value specified by user in source file and any SVCrossNumPrintMissingDefault -; specified in modelsim.ini. -; SVCrossNumPrintMissing = 0 - -; Specify whether to use the value of "cross_num_print_missing" -; option in report and GUI for the Cross in Covergroups. If not specified then -; cross_num_print_missing is ignored for creating reports and displaying -; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". -; UseSVCrossNumPrintMissing = 0 - -; Specify the threshold of Coverpoint wildcard bin value range size, above which -; a warning will be triggered. The default is 4K -- 12 wildcard bits. -; SVCoverpointWildCardBinValueSizeWarn = 4096 - -; Specify the override for the value of "strobe" option for the -; Covergroup Type. If not specified then value in "type_option.strobe" -; will be used. This is runtime option which forces "strobe" to -; user specified value and supersedes user specified values in the -; SystemVerilog Code. NOTE: This also overrides the compile time -; default value override specified using "SVCovergroupStrobeDefault" -; SVCovergroupStrobe = 0 - -; Override for explicit assignments in source code to "option.goal" of -; SystemVerilog covergroup, coverpoint, and cross. It also overrides the -; default value of "option.goal" (defined to be 100 in the SystemVerilog -; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". -; SVCovergroupGoal = 100 - -; Override for explicit assignments in source code to "type_option.goal" of -; SystemVerilog covergroup, coverpoint, and cross. It also overrides the -; default value of "type_option.goal" (defined to be 100 in the SystemVerilog -; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". -; SVCovergroupTypeGoal = 100 - -; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() -; builtin functions, and report. This setting changes the default values of -; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 -; behavior if explicit assignments are not made on option.get_inst_coverage and -; type_option.merge_instances by the user. There are two vsim command line -; options, -cvg63 and -nocvg63 to override this setting from vsim command line. -; The default value of this variable from release 6.6 onwards is 0. This default -; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. -; SVCovergroup63Compatibility = 0 - -; Enforce the default behavior of covergroup get_coverage() builtin function, GUI -; and report. This variable sets the default value of type_option.merge_instances. -; There are two vsim command line options, -cvgmergeinstances and -; -nocvgmergeinstances to override this setting from vsim command line. -; The default value of this variable, -1 (don't care), allows the tool to determine -; the effective value, based on factors related to capacity and optimization. -; The type_option.merge_instances appears in the GUI and coverage reports as either -; auto(1) or auto(0), depending on whether the effective value was determined to -; be a 1 or a 0. -; SVCovergroupMergeInstancesDefault = -1 - -; Enable or disable generation of more detailed information about the sampling -; of covergroup, cross, and coverpoints. It provides the details of the number -; of times the covergroup instance and type were sampled, as well as details -; about why covergroup, cross and coverpoint were not covered. A non-zero value -; is to enable this feature. 0 is to disable this feature. Default is 0 -; SVCovergroupSampleInfo = 0 - -; Specify the maximum number of Coverpoint bins in whole design for -; all Covergroups. -; MaxSVCoverpointBinsDesign = 2147483648 - -; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins -; MaxSVCoverpointBinsInst = 1048576 - -; Specify the maximum number of Cross bins in whole design for -; all Covergroups. -; MaxSVCrossBinsDesign = 2147483648 - -; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins -; MaxSVCrossBinsInst = 67108864 - -; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. -; By default, this variable is set 0, in which case option.no_collect setting will take effect. -; If this variable is set to 1, all zero-weight coverage items will not be saved. -; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting -; of this variable. -; CvgZWNoCollect = 1 - -; Specify a space delimited list of double quoted TCL style -; regular expressions which will be matched against the text of all messages. -; If any regular expression is found to be contained within any message, the -; status for that message will not be propagated to the UCDB TESTSTATUS. -; If no match is detected, then the status will be propagated to the -; UCDB TESTSTATUS. More than one such regular expression text is allowed, -; and each message text is compared for each regular expression in the list. -; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" - -; Set weight for all PSL/SVA cover directives. Default is 1. -; CoverWeight = 2 - -; Check vsim plusargs. Default is 0 (off). -; 0 = Don't check plusargs -; 1 = Warning on unrecognized plusarg -; 2 = Error and exit on unrecognized plusarg -; CheckPlusargs = 1 - -; Load the specified shared objects with the RTLD_GLOBAL flag. -; This gives global visibility to all symbols in the shared objects, -; meaning that subsequently loaded shared objects can bind to symbols -; in the global shared objects. The list of shared objects should -; be whitespace delimited. This option is not supported on the -; Windows or AIX platforms. -; GlobalSharedObjectList = example1.so example2.so example3.so - -; Generate the stub definitions for the undefined symbols in the shared libraries being -; loaded in the simulation. When this flow is turned on, the undefined symbols will not -; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. -; The valid arguments are: on, off, verbose. -; on : turn on the automatic generation of stub definitions. -; off: turn off the flow. The undefined symbols will trigger an immediate load failure. -; verbose: Turn on the flow and report the undefined symbols for each shared library. -; NOTE: This variable can be overriden with vsim switch "-undefsyms". -; The default is on. -; -; UndefSyms = off - -; Enable the support for checkpointing foreign C/C++ libraries. -; The valid arguments are: 0, 1, 2 -; 0: off (default) -; 1: on (manually save/restore user shared library data) -; 2: auto (automatically save/restore user shared library data) -; This option is not supported on the Windows platforms. -; -; AllowCheckpointCpp = 2 - -; Initial seed for the random number generator of the root thread (SystemVerilog). -; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. -; The default value is 0. -; Sv_Seed = 0 - -; Specify the solver "engine" that vsim will select for constrained random -; generation. -; Valid values are: -; "auto" - automatically select the best engine for the current -; constraint scenario -; "bdd" - evaluate all constraint scenarios using the BDD solver engine -; "act" - evaluate all constraint scenarios using the ACT solver engine -; While the BDD solver engine is generally efficient with constraint scenarios -; involving bitwise logical relationships, the ACT solver engine can exhibit -; superior performance with constraint scenarios involving large numbers of -; random variables related via arithmetic operators (+, *, etc). -; NOTE: This variable can be overridden with the vsim "-solveengine" command -; line switch. -; The default value is "auto". -; SolveEngine = auto - -; Specifies the maximum size that a dynamic array may be resized to by the -; solver. If the solver attempts to resize a dynamic array to a size greater -; than the specified limit, the solver will abort with an error. -; The default value is 10000. A value of 0 indicates no limit. -; SolveArrayResizeMax = 10000 - -; Specify error message severity when randomize() and randomize(null) failures -; are detected. -; -; Integer value up to two digits are allowed with each digit having the following legal values: -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; -; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents -; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit) -; represents the setting for randomize(null) calls. -; -; 2) When a single digit value is used, the setting is applied to both normal randomize() call -; and randomize(null) call. -; -; Example: Fatal error for randomize() failures and NO error for randomize(null) failures -; -solvefailseverity=40 -; -; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is -; enabled, a constraint contradiction report will be displayed for randomize() calls that -; have a message severity >= warning (i.e. constraint contradiction reports will not be -; generated for randomize() calls having a "no error" severity level) -; -; NOTE: This variable can be overridden with the vsim "-solvefailseverity" command -; line switch. -; -; The default is 1 (warning). -; SolveFailSeverity = 1 - -; Error message severity for suppressible errors that are detected in a -; solve/before constraint. -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" -; command line switch. -; The default is 3 (failure). -; SolveBeforeErrorSeverity = 3 - -; Error message severity for suppressible errors that are related to -; solve engine capacity limits -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" -; command line switch. -; The default is 3 (failure). -; SolveEngineErrorSeverity = 3 - -; Enable/disable constraint conflicts on randomize() failure -; Valid values: -; 0 - disable solvefaildebug -; 1 - basic debug (no performance penalty) -; 2 - enhanced debug (runtime performance penalty) -; -; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is -; enabled, a constraint contradiction report will be displayed for randomize() calls that -; have a message severity >= warning (i.e. constraint contradiction reports will not be -; generated for randomize() calls having a "no error" severity level) -; -; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command -; line switch. -; -; The default is 1 (basic debug). -; SolveFailDebug = 1 - -; Upon encountering a randomize() failure, generate a simplified testcase that -; will reproduce the failure. Optionally output the testcase to a file. -; Testcases for 'no-solution' failures will only be produced if SolveFailDebug -; is enabled (see above). -; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" -; command line switch. -; The default is OFF (do not generate a testcase). To enable testcase -; generation, uncomment this variable. To redirect testcase generation to a -; file, specify the name of the output file. -; SolveFailTestcase = - -; Specify solver timeout threshold (in seconds). randomize() will fail if the -; CPU time required to evaluate any randset exceeds the specified timeout. -; The default value is 500. A value of 0 will disable timeout failures. -; SolveTimeout = 500 - -; Specify the alternative behavior during solver replay. Must be used when combined with -solvereplay switch. -; SolveReplayOpt=[+|-][,[+|-]]*" -' Valid settings: -; validate : toggle the checking of value changes of non-random variables involved in randomize(). (default is off)" -; SolveReplayOpt=validate - -; Specify the maximum size of the solution graph generated by the BDD solver. -; This value can be used to force the BDD solver to abort the evaluation of a -; complex constraint scenario that cannot be evaluated with finite memory. -; This value is specified in 1000s of nodes. -; The default value is 10000. A value of 0 indicates no limit. -; SolveGraphMaxSize = 10000 - -; Specify the maximum number of evaluations that may be performed on the -; solution graph by the BDD solver. This value can be used to force the BDD -; solver to abort the evaluation of a complex constraint scenario that cannot -; be evaluated in finite time. This value is specified in 10000s of evaluations. -; The default value is 10000. A value of 0 indicates no limit. -; SolveGraphMaxEval = 10000 - -; Specify random sequence compatiblity with a prior release. This -; option is used to get the same random sequences during simulation as -; as a prior release. Only prior releases with the same major version -; as the current release are allowed. -; NOTE: Only those random sequence changes due to solver optimizations are -; reverted by this variable. Random sequence changes due to solver bugfixes -; cannot be un-done. -; NOTE: This variable can be overridden with the vsim "-solverev" command -; line switch. -; Default value set to "" (no compatibility). -; SolveRev = - -; Environment variable expansion of command line arguments has been depricated -; in favor shell level expansion. Universal environment variable expansion -; inside -f files is support and continued support for MGC Location Maps provide -; alternative methods for handling flexible pathnames. -; The following line may be uncommented and the value set to 1 to re-enable this -; deprecated behavior. The default value is 0. -; DeprecatedEnvironmentVariableExpansion = 0 - -; Specify the memory threshold for the System Verilog garbage collector. -; The value is the number of megabytes of class objects that must accumulate -; before the garbage collector is run. -; The GCThreshold setting is used when class debug mode is disabled to allow -; less frequent garbage collection and better simulation performance. -; The GCThresholdClassDebug setting is used when class debug mode is enabled -; to allow for more frequent garbage collection. -; GCThreshold = 100 -; GCThresholdClassDebug = 5 - -; Turn on/off collapsing of bus ports in VCD dumpports output -DumpportsCollapse = 1 - -; Location of Multi-Level Verification Component (MVC) installation. -; The default location is the product installation directory. -MvcHome = $QUESTA_MVC_HOME - -; Location of InFact installation. The default is $MODEL_TECH/../../infact -; -; InFactHome = $MODEL_TECH/../../infact - -; Initialize SystemVerilog enums using the base type's default value -; instead of the leftmost value. -; EnumBaseInit = 1 - -; Suppress file type registration. -; SuppressFileTypeReg = 1 - -; Enable/disable non-LRM compliant SystemVerilog language extensions. -; Valid extensions are: -; altdpiheader - Alternative style function signature generated in DPI header", -; cfce - generate an error if $cast fails as a function -; cfmt - C like formatting for specifiers with '#' prefix ('%#x', '%#h') -; dfsp - sets default format specifier as %p, if no format specifier is given for unpacked array in $display and related systasks -; expdfmt - enable format string extensions for $display/$sformatf -; extscan - support values greater than 32 bit for string builtin methods (atohex, atobin, atooct, atoi) -; fmtcap - prints capital hex digits with %X/%H in display calls -; iddp - ignore DPI disable protocol check -; lfmt - zero-pad data if '0' prefixes width in format specifier (e.g. "%04h") -; noexptc - ignore DPI export type name overloading check -; realrand - support randomize() with real variables and constraints (Default) -; SvExtensions = [+|-][,[+|-]*] - -; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions. -; Valid extensions are: -; arraymode - consider rand_mode of unpacked array field independently from its elements -; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles (Default) -; funcback - enable function backtracking (ACT only) -; genmodseedfix - enable LRM-compliant seeding of module/interface instances under for-generate blocks (Default) -; nodist - interpret 'dist' constraint as 'inside' (ACT only) -; noorder - ignore solve/before ordering constraints (ACT only) -; pathseed - enable unique seeding of module instances based on hierarchical path name -; prerandfirst - execute all pre_randomize() functions before evaluating any constraints -; promotedist - promote priority of 'dist' constraint if LHS has no solve/before -; purecheck - suppress pre_randomize() and post_randomize() calls for randomize(null) -; randindex - allow random index in constraint (Default) -; randstruct - consider all fields of unpacked structs as 'rand' -; skew - skew randomize results (ACT only) -; strictstab - strict random stability -; SvRandExtensions = [+|-][,[+|-]*] - -; Controls the formatting of '%p' and '%P' conversion specification, used in $display -; and similar system tasks. -; 1. SVPrettyPrintFlags=I use spaces(S) or tabs(T) per indentation level. -; The 'I' flag when present causes relevant data types to be expanded and indented into -; a more readable format. -; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). -; 2. SVPrettyPrintFlags=L limits the output to lines. -; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). -; 3. SVPrettyPrintFlags=C limits the output to characters. -; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). -; 4. SVPrettyPrintFlags=F limits the output to of relevant datatypes -; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). -; 5. SVPrettyPrintFlags=E limits the output to of relevant datatypes -; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). -; 6. SVPrettyPrintFlags=D suppresses the output of sub-elements below . -; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). -; 7. SVPrettyPrintFlags=R shows the output of specifier %p as per the specifed radix. -; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)). -; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format. -; 8. Items 1-7 above can be combined as a comma separated list. -; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb) -; SVPrettyPrintFlags=I4S - -[lmc] -; The simulator's interface to Logic Modeling's SmartModel SWIFT software -libsm = $MODEL_TECH/libsm.sl -; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) -; libsm = $MODEL_TECH/libsm.dll -; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) -; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl -; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) -; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o -; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) -; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so -; Logic Modeling's SmartModel SWIFT software (Windows NT) -; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll -; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) -; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so -; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) -; libswift = $LMC_HOME/lib/linux.lib/libswift.so - -; The simulator's interface to Logic Modeling's hardware modeler SFI software -libhm = $MODEL_TECH/libhm.sl -; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) -; libhm = $MODEL_TECH/libhm.dll -; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) -; libsfi = /lib/hp700/libsfi.sl -; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) -; libsfi = /lib/rs6000/libsfi.a -; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) -; libsfi = /lib/sun4.solaris/libsfi.so -; Logic Modeling's hardware modeler SFI software (Windows NT) -; libsfi = /lib/pcnt/lm_sfi.dll -; Logic Modeling's hardware modeler SFI software (Linux) -; libsfi = /lib/linux/libsfi.so - -[msg_system] -; Change a message severity or suppress a message. -; The format is: = [,...] -; suppress can be used to achieve +nowarn functionality -; The format is: suppress = ,,[,,...] -; Examples: -suppress = 8780 ;an explanation can be had by running: verror 8780 -; note = 3009 -; warning = 3033 -; error = 3010,3016 -; fatal = 3016,3033 -; suppress = 3009,3016,3601 -; suppress = 3009,CNNODP,3601,TFMPC -; suppress = 8683,8684 -; The command verror can be used to get the complete -; description of a message. - -; Control transcripting of Verilog display system task messages and -; PLI/FLI print function call messages. The system tasks include -; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They -; also include the analogous file I/O tasks that write to STDOUT -; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, -; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default -; is to have messages appear only in the transcript. The other -; settings are to send messages to the wlf file only (messages that -; are recorded in the wlf file can be viewed in the MsgViewer) or -; to both the transcript and the wlf file. The valid values are -; tran {transcript only (default)} -; wlf {wlf file only} -; both {transcript and wlf file} -; displaymsgmode = tran - -; Control transcripting of elaboration/runtime messages not -; addressed by the displaymsgmode setting. The default is to -; have messages appear only in the transcript. The other settings -; are to send messages to the wlf file only (messages that are -; recorded in the wlf file can be viewed in the MsgViewer) or to both -; the transcript and the wlf file. The valid values are -; tran {transcript only (default)} -; wlf {wlf file only} -; both {transcript and wlf file} -; msgmode = tran - -; Controls number of displays of a particluar message -; default value is 5 -; MsgLimitCount = 5 - -[utils] -; Default Library Type (while creating a library with "vlib") -; 0 - legacy library using subdirectories for design units -; 2 - flat library -; DefaultLibType = 2 - -; Flat Library Page Size (while creating a library with "vlib") -; Set the size in bytes for flat library file pages. Libraries containing -; very large files may benefit from a larger value. -; FlatLibPageSize = 8192 - -; Flat Library Page Cleanup Percentage (while creating a library with "vlib") -; Set the percentage of total pages deleted before library cleanup can occur. -; This setting is applied together with FlatLibPageDeleteThreshold. -; FlatLibPageDeletePercentage = 50 - -; Flat Library Page Cleanup Threshold (while creating a library with "vlib") -; Set the number of pages deleted before library cleanup can occur. -; This setting is applied together with FlatLibPageDeletePercentage. -; FlatLibPageDeleteThreshold = 1000 - - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/selectio_lvds_tx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/selectio_lvds_tx.sh deleted file mode 100644 index 92defc70..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/selectio_lvds_tx.sh +++ /dev/null @@ -1,167 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : selectio_lvds_tx.sh -# Simulator : Mentor Graphics ModelSim Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sun Mar 19 17:32:07 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: selectio_lvds_tx.sh [-help] -# usage: selectio_lvds_tx.sh [-lib_map_path] -# usage: selectio_lvds_tx.sh [-noclean_files] -# usage: selectio_lvds_tx.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'selectio_lvds_tx.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "selectio_lvds_tx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - vsim -64 -c -do "do {simulate.do}" -l simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_tx.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Copy modelsim.ini file -copy_setup_file() -{ - file="modelsim.ini" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - else - lib_map_path="C:/Mentor/CompLib/2019.1.3" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - cp $src_file . - fi -} - -# Create design library directory -create_lib_dir() -{ - lib_dir="modelsim_lib" - if [[ -e $lib_dir ]]; then - rm -rf $lib_dir - fi - - mkdir $lib_dir - -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_tx.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: selectio_lvds_tx.sh [-help]\n\ -Usage: selectio_lvds_tx.sh [-lib_map_path]\n\ -Usage: selectio_lvds_tx.sh [-reset_run]\n\ -Usage: selectio_lvds_tx.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/selectio_lvds_tx.udo b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/selectio_lvds_tx.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/simulate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/simulate.do deleted file mode 100644 index b02f3576..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/simulate.do +++ /dev/null @@ -1,16 +0,0 @@ -onbreak {quit -f} -onerror {quit -f} - -vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.selectio_lvds_tx xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure -view signals - -do {selectio_lvds_tx.udo} - -run -all - -quit -force diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/wave.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/README.txt deleted file mode 100644 index 9e224e68..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun Mar 19 17:32:07 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./selectio_lvds_tx.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './selectio_lvds_tx.sh' script. - -./selectio_lvds_tx.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./selectio_lvds_tx.sh -noclean_files - -For more information on the script, please type './selectio_lvds_tx.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/compile.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/compile.do deleted file mode 100644 index 03db5d0e..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/compile.do +++ /dev/null @@ -1,23 +0,0 @@ -vlib questa_lib/work -vlib questa_lib/msim - -vlib questa_lib/msim/xil_defaultlib -vlib questa_lib/msim/xpm - -vmap xil_defaultlib questa_lib/msim/xil_defaultlib -vmap xpm questa_lib/msim/xpm - -vlog -work xil_defaultlib -64 -sv \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -64 -93 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work xil_defaultlib -64 \ -"../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v" \ -"../../../ip/selectio_lvds_tx/selectio_lvds_tx.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/elaborate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/elaborate.do deleted file mode 100644 index b83fde90..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/elaborate.do +++ /dev/null @@ -1 +0,0 @@ -vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.selectio_lvds_tx xil_defaultlib.glbl -o selectio_lvds_tx_opt diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/file_info.txt deleted file mode 100644 index eddbf85c..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -selectio_lvds_tx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v, -selectio_lvds_tx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/selectio_lvds_tx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/selectio_lvds_tx.sh deleted file mode 100644 index ce28d77d..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/selectio_lvds_tx.sh +++ /dev/null @@ -1,174 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : selectio_lvds_tx.sh -# Simulator : Mentor Graphics Questa Advanced Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sun Mar 19 17:32:07 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: selectio_lvds_tx.sh [-help] -# usage: selectio_lvds_tx.sh [-lib_map_path] -# usage: selectio_lvds_tx.sh [-noclean_files] -# usage: selectio_lvds_tx.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'selectio_lvds_tx.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "selectio_lvds_tx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -elaborate() -{ - source elaborate.do 2>&1 | tee -a elaborate.log -} - -# RUN_STEP: -simulate() -{ - vsim -64 -c -do "do {simulate.do}" -l simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_tx.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Copy modelsim.ini file -copy_setup_file() -{ - file="modelsim.ini" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - else - lib_map_path="D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - cp $src_file . - fi -} - -# Create design library directory -create_lib_dir() -{ - lib_dir="questa_lib" - if [[ -e $lib_dir ]]; then - rm -rf $lib_dir - fi - - mkdir $lib_dir - -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_tx.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: selectio_lvds_tx.sh [-help]\n\ -Usage: selectio_lvds_tx.sh [-lib_map_path]\n\ -Usage: selectio_lvds_tx.sh [-reset_run]\n\ -Usage: selectio_lvds_tx.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/selectio_lvds_tx.udo b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/selectio_lvds_tx.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/simulate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/simulate.do deleted file mode 100644 index 86367bfa..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/simulate.do +++ /dev/null @@ -1,16 +0,0 @@ -onbreak {quit -f} -onerror {quit -f} - -vsim -t 1ps -lib xil_defaultlib selectio_lvds_tx_opt - -do {wave.do} - -view wave -view structure -view signals - -do {selectio_lvds_tx.udo} - -run -all - -quit -force diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/wave.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/README.txt deleted file mode 100644 index 9e224e68..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun Mar 19 17:32:07 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./selectio_lvds_tx.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './selectio_lvds_tx.sh' script. - -./selectio_lvds_tx.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./selectio_lvds_tx.sh -noclean_files - -For more information on the script, please type './selectio_lvds_tx.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/compile.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/compile.do deleted file mode 100644 index 3b4ef4cf..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/compile.do +++ /dev/null @@ -1,23 +0,0 @@ -vlib work -vlib riviera - -vlib riviera/xil_defaultlib -vlib riviera/xpm - -vmap xil_defaultlib riviera/xil_defaultlib -vmap xpm riviera/xpm - -vlog -work xil_defaultlib -sv2k12 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -93 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work xil_defaultlib -v2k5 \ -"../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v" \ -"../../../ip/selectio_lvds_tx/selectio_lvds_tx.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/file_info.txt deleted file mode 100644 index eddbf85c..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -selectio_lvds_tx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v, -selectio_lvds_tx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/selectio_lvds_tx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/selectio_lvds_tx.sh deleted file mode 100644 index 104c1667..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/selectio_lvds_tx.sh +++ /dev/null @@ -1,153 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : selectio_lvds_tx.sh -# Simulator : Aldec Riviera-PRO Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sun Mar 19 17:32:07 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: selectio_lvds_tx.sh [-help] -# usage: selectio_lvds_tx.sh [-lib_map_path] -# usage: selectio_lvds_tx.sh [-noclean_files] -# usage: selectio_lvds_tx.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'selectio_lvds_tx.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "selectio_lvds_tx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - runvsimsa -l simulate.log -do "do {simulate.do}" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_tx.sh -help\" for more information)\n" - exit 1 - fi - map_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - map_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Map library.cfg file -map_setup_file() -{ - file="library.cfg" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - else - lib_map_path="D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - vmap -link $lib_map_path - fi - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_tx.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: selectio_lvds_tx.sh [-help]\n\ -Usage: selectio_lvds_tx.sh [-lib_map_path]\n\ -Usage: selectio_lvds_tx.sh [-reset_run]\n\ -Usage: selectio_lvds_tx.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/selectio_lvds_tx.udo b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/selectio_lvds_tx.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/simulate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/simulate.do deleted file mode 100644 index 934173ec..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/simulate.do +++ /dev/null @@ -1,17 +0,0 @@ -onbreak {quit -force} -onerror {quit -force} - -asim -t 1ps +access +r +m+selectio_lvds_tx -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.selectio_lvds_tx xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure - -do {selectio_lvds_tx.udo} - -run -all - -endsim - -quit -force diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/wave.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/README.txt deleted file mode 100644 index 9e224e68..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun Mar 19 17:32:07 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./selectio_lvds_tx.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './selectio_lvds_tx.sh' script. - -./selectio_lvds_tx.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./selectio_lvds_tx.sh -noclean_files - -For more information on the script, please type './selectio_lvds_tx.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/file_info.txt deleted file mode 100644 index eddbf85c..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -selectio_lvds_tx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v, -selectio_lvds_tx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/selectio_lvds_tx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/selectio_lvds_tx.sh deleted file mode 100644 index 8bc40400..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/selectio_lvds_tx.sh +++ /dev/null @@ -1,230 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : selectio_lvds_tx.sh -# Simulator : Synopsys Verilog Compiler Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sun Mar 19 17:32:07 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: selectio_lvds_tx.sh [-help] -# usage: selectio_lvds_tx.sh [-lib_map_path] -# usage: selectio_lvds_tx.sh [-noclean_files] -# usage: selectio_lvds_tx.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'selectio_lvds_tx.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Command line options -vlogan_opts="-full64" -vhdlan_opts="-full64" -vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" -vcs_sim_opts="-ucli -licqueue -l simulate.log" - -# Design libraries -design_libs=(xil_defaultlib xpm) - -# Simulation root library directory -sim_lib_dir="vcs_lib" - -# Script info -echo -e "selectio_lvds_tx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - vlogan -work xil_defaultlib $vlogan_opts -sverilog \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - 2>&1 | tee -a vlogan.log - - vhdlan -work xpm $vhdlan_opts \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - 2>&1 | tee -a vhdlan.log - - vlogan -work xil_defaultlib $vlogan_opts +v2k \ - "$ref_dir/../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v" \ - "$ref_dir/../../../ip/selectio_lvds_tx/selectio_lvds_tx.v" \ - 2>&1 | tee -a vlogan.log - - - vlogan -work xil_defaultlib $vlogan_opts +v2k \ - glbl.v \ - 2>&1 | tee -a vlogan.log - -} - -# RUN_STEP: -elaborate() -{ - vcs $vcs_elab_opts xil_defaultlib.selectio_lvds_tx xil_defaultlib.glbl -o selectio_lvds_tx_simv -} - -# RUN_STEP: -simulate() -{ - ./selectio_lvds_tx_simv $vcs_sim_opts -do simulate.do -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_tx.sh -help\" for more information)\n" - exit 1 - fi - create_lib_mappings $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - create_lib_mappings $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Define design library mappings -create_lib_mappings() -{ - file="synopsys_sim.setup" - if [[ -e $file ]]; then - if [[ ($1 == "") ]]; then - return - else - rm -rf $file - fi - fi - - touch $file - - lib_map_path="" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - mapping="$lib:$sim_lib_dir/$lib" - echo $mapping >> $file - done - - if [[ ($lib_map_path != "") ]]; then - incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" - echo $incl_ref >> $file - fi -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(ucli.key selectio_lvds_tx_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc selectio_lvds_tx_simv.daidir) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_tx.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: selectio_lvds_tx.sh [-help]\n\ -Usage: selectio_lvds_tx.sh [-lib_map_path]\n\ -Usage: selectio_lvds_tx.sh [-reset_run]\n\ -Usage: selectio_lvds_tx.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/simulate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/simulate.do deleted file mode 100644 index 58afc787..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/simulate.do +++ /dev/null @@ -1,2 +0,0 @@ -run -quit diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/README.txt deleted file mode 100644 index 03fedd1b..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/README.txt +++ /dev/null @@ -1,48 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun Mar 19 17:32:07 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./selectio_lvds_tx.sh - -This command will launch the 'execute' function for the single-step flow. This -function is called from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './selectio_lvds_tx.sh' script. - -./selectio_lvds_tx.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./selectio_lvds_tx.sh -noclean_files - -For more information on the script, please type './selectio_lvds_tx.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/file_info.txt deleted file mode 100644 index eddbf85c..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -selectio_lvds_tx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v, -selectio_lvds_tx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/run.f b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/run.f deleted file mode 100644 index 36638505..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/run.f +++ /dev/null @@ -1,15 +0,0 @@ --makelib xcelium_lib/xil_defaultlib -sv \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ --endlib --makelib xcelium_lib/xpm \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ --endlib --makelib xcelium_lib/xil_defaultlib \ - "../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v" \ - "../../../ip/selectio_lvds_tx/selectio_lvds_tx.v" \ --endlib --makelib xcelium_lib/xil_defaultlib \ - glbl.v --endlib - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/selectio_lvds_tx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/selectio_lvds_tx.sh deleted file mode 100644 index 2879c179..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/selectio_lvds_tx.sh +++ /dev/null @@ -1,175 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : selectio_lvds_tx.sh -# Simulator : Cadence Xcelium Parallel Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sun Mar 19 17:32:07 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: selectio_lvds_tx.sh [-help] -# usage: selectio_lvds_tx.sh [-lib_map_path] -# usage: selectio_lvds_tx.sh [-noclean_files] -# usage: selectio_lvds_tx.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'selectio_lvds_tx.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Set the compiled library directory -ref_lib_dir="." - -# Command line options -xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" - -# Design libraries -design_libs=(xil_defaultlib xpm) - -# Simulation root library directory -sim_lib_dir="xcelium_lib" - -# Script info -echo -e "selectio_lvds_tx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - execute -} - -# RUN_STEP: -execute() -{ - xrun $xrun_opts \ - -reflib "$ref_lib_dir/unisim:unisim" \ - -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ - -reflib "$ref_lib_dir/secureip:secureip" \ - -reflib "$ref_lib_dir/unimacro:unimacro" \ - -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.selectio_lvds_tx \ - -f run.f \ - -top glbl \ - glbl.v -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_tx.sh -help\" for more information)\n" - exit 1 - else - ref_lib_dir=$2 - fi - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_tx.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: selectio_lvds_tx.sh [-help]\n\ -Usage: selectio_lvds_tx.sh [-lib_map_path]\n\ -Usage: selectio_lvds_tx.sh [-reset_run]\n\ -Usage: selectio_lvds_tx.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/README.txt deleted file mode 100644 index 9e224e68..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sun Mar 19 17:32:07 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./selectio_lvds_tx.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './selectio_lvds_tx.sh' script. - -./selectio_lvds_tx.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./selectio_lvds_tx.sh -noclean_files - -For more information on the script, please type './selectio_lvds_tx.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/cmd.tcl b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/cmd.tcl deleted file mode 100644 index eef7a0f0..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/cmd.tcl +++ /dev/null @@ -1,12 +0,0 @@ -set curr_wave [current_wave_config] -if { [string length $curr_wave] == 0 } { - if { [llength [get_objects]] > 0} { - add_wave / - set_property needs_save false [current_wave_config] - } else { - send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." - } -} - -run -all -quit diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/elab.opt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/elab.opt deleted file mode 100644 index 931a8002..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/elab.opt +++ /dev/null @@ -1 +0,0 @@ ---relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot selectio_lvds_tx xil_defaultlib.selectio_lvds_tx xil_defaultlib.glbl -log elaborate.log diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/file_info.txt deleted file mode 100644 index 3f418daf..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/file_info.txt +++ /dev/null @@ -1,3 +0,0 @@ -selectio_lvds_tx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v, -selectio_lvds_tx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/selectio_lvds_tx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/selectio_lvds_tx.sh deleted file mode 100644 index 828ad7b1..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/selectio_lvds_tx.sh +++ /dev/null @@ -1,212 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : selectio_lvds_tx.sh -# Simulator : Xilinx Vivado Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sun Mar 19 17:32:07 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: selectio_lvds_tx.sh [-help] -# usage: selectio_lvds_tx.sh [-lib_map_path] -# usage: selectio_lvds_tx.sh [-noclean_files] -# usage: selectio_lvds_tx.sh [-reset_run] -# -#********************************************************************************************************* - -# Command line options -xv_boost_lib_path=C:/Xilinx/Vivado/2019.1/tps/boost_1_64_0 -xvlog_opts="--relax" - - -# Script info -echo -e "selectio_lvds_tx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log - -} - -# RUN_STEP: -elaborate() -{ - xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot selectio_lvds_tx xil_defaultlib.selectio_lvds_tx xil_defaultlib.glbl -log elaborate.log -} - -# RUN_STEP: -simulate() -{ - xsim selectio_lvds_tx -key {Behavioral:sim_1:Functional:selectio_lvds_tx} -tclbatch cmd.tcl -log simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_tx.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Copy xsim.ini file -copy_setup_file() -{ - file="xsim.ini" - lib_map_path="C:/Xilinx/Vivado/2019.1/data/xsim" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - cp $src_file . - fi - - # Map local design libraries to xsim.ini - map_local_libs - - fi -} - -# Map local design libraries -map_local_libs() -{ - updated_mappings=() - local_mappings=() - - # Local design libraries - local_libs=() - - if [[ 0 == ${#local_libs[@]} ]]; then - return - fi - - file="xsim.ini" - file_backup="xsim.ini.bak" - - if [[ -e $file ]]; then - rm -f $file_backup - # Create a backup copy of the xsim.ini file - cp $file $file_backup - # Read libraries from backup file and search in local library collection - while read -r line - do - IN=$line - # Split mapping entry with '=' delimiter to fetch library name and mapping - read lib_name mapping <<<$(IFS="="; echo $IN) - # If local library found, then construct the local mapping and add to local mapping collection - if `echo ${local_libs[@]} | grep -wq $lib_name` ; then - line="$lib_name=xsim.dir/$lib_name" - local_mappings+=("$lib_name") - fi - # Add to updated library mapping collection - updated_mappings+=("$line") - done < "$file_backup" - # Append local libraries not found originally from xsim.ini - for (( i=0; i<${#local_libs[*]}; i++ )); do - lib_name="${local_libs[i]}" - if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then - line="$lib_name=xsim.dir/$lib_name" - updated_mappings+=("$line") - fi - done - # Write updated mappings in xsim.ini - rm -f $file - for (( i=0; i<${#updated_mappings[*]}; i++ )); do - lib_name="${updated_mappings[i]}" - echo $lib_name >> $file - done - else - for (( i=0; i<${#local_libs[*]}; i++ )); do - lib_name="${local_libs[i]}" - mapping="$lib_name=xsim.dir/$lib_name" - echo $mapping >> $file - done - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb selectio_lvds_tx.wdb xsim.dir) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_tx.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: selectio_lvds_tx.sh [-help]\n\ -Usage: selectio_lvds_tx.sh [-lib_map_path]\n\ -Usage: selectio_lvds_tx.sh [-reset_run]\n\ -Usage: selectio_lvds_tx.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/vlog.prj b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/vlog.prj deleted file mode 100644 index 4014d965..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/vlog.prj +++ /dev/null @@ -1,7 +0,0 @@ -verilog xil_defaultlib \ -"../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v" \ -"../../../ip/selectio_lvds_tx/selectio_lvds_tx.v" \ - -verilog xil_defaultlib "glbl.v" - -nosort diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/xsim.ini b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/xsim.ini deleted file mode 100644 index 6cb07f57..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/xsim.ini +++ /dev/null @@ -1,430 +0,0 @@ -std=$RDI_DATADIR/xsim/vhdl/std -ieee=$RDI_DATADIR/xsim/vhdl/ieee -ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed -vl=$RDI_DATADIR/xsim/vhdl/vl -synopsys=$RDI_DATADIR/xsim/vhdl/synopsys -secureip=$RDI_DATADIR/xsim/verilog/secureip -unisim=$RDI_DATADIR/xsim/vhdl/unisim -unimacro=$RDI_DATADIR/xsim/vhdl/unimacro -unifast=$RDI_DATADIR/xsim/vhdl/unifast -unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver -unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver -unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver -simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver -system_cache_v4_0_6=$RDI_DATADIR/xsim/ip/system_cache_v4_0_6 -bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0 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-axi_intc_v4_1_13=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_13 -i2s_transmitter_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_3 -pc_cfr_v6_0_8=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_8 -mutex_v2_1_10=$RDI_DATADIR/xsim/ip/mutex_v2_1_10 -c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6 -sid_v8_0_14=$RDI_DATADIR/xsim/ip/sid_v8_0_14 -fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6 -quadsgmii_v3_4_6=$RDI_DATADIR/xsim/ip/quadsgmii_v3_4_6 -microblaze_v11_0_1=$RDI_DATADIR/xsim/ip/microblaze_v11_0_1 -lib_bmg_v1_0_12=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_12 -dds_compiler_v6_0_18=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_18 -me_pl_v1_0=$RDI_DATADIR/xsim/ip/me_pl_v1_0 -gtwizard_ultrascale_v1_7_6=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_6 -axis_clock_converter_v1_1_20=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_20 -nvmeha_v1_0_0=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_0 -tmr_inject_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_3 -axi_mcdma_v1_1_0=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_0 -axi_hwicap_v3_0_23=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_23 -v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0 -v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0 -canfd_v2_0_1=$RDI_DATADIR/xsim/ip/canfd_v2_0_1 -gig_ethernet_pcs_pma_v16_1_6=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_6 -lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2 -ieee802d3_rs_fec_v2_0_5=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_5 -ibert_lib_v1_0_6=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_6 -high_speed_selectio_wiz_v3_4_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_1 -xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6 -fec_5g_common_v1_0_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_1 -tmr_voter_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_2 -hdmi_gt_controller_v1_0_0=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_0 -axi_traffic_gen_v2_0_20=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_20 -flexo_100g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_11 -v_smpte_uhdsdi_v1_0_7=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_7 -xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6 -fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10 -ieee802d3_rs_fec_v1_0_15=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_15 -axis_subset_converter_v1_1_19=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_19 -noc_nmu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_v1_0_0 -duc_ddc_compiler_v3_0_15=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_15 -dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13 -mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0 -ieee802d3_200g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_7 -sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1 -mrmac_v1_0_0=$RDI_DATADIR/xsim/ip/mrmac_v1_0_0 -sem_ultra_v3_1_11=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_11 -v_tpg_v8_0_1=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_1 -axi_tft_v2_0_22=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_22 -ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13 -switch_core_top_v1_0_7=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_7 -rama_v1_1_2_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_2_lib -v_hcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_13 -emb_fifo_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_1 -hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3 -axis_data_fifo_v2_0_1=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_1 -hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0 -rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1 -displayport_v8_1_1=$RDI_DATADIR/xsim/ip/displayport_v8_1_1 -axi_mmu_v2_1_17=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_17 -proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13 -pc_cfr_v6_3_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_3_0 -v_osd_v6_0_16=$RDI_DATADIR/xsim/ip/v_osd_v6_0_16 -pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12 -xfft_v9_0_17=$RDI_DATADIR/xsim/ip/xfft_v9_0_17 -axi_cdma_v4_1_19=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_19 -audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0 -lib_fifo_v1_0_13=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_13 -v_enhance_v8_0_15=$RDI_DATADIR/xsim/ip/v_enhance_v8_0_15 -axi_clock_converter_v2_1_18=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_18 -xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0 -emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5 -axi_mm2s_mapper_v1_1_18=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_18 -xfft_v7_2_9=$RDI_DATADIR/xsim/ip/xfft_v7_2_9 -pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0 -v_smpte_sdi_v3_0_8=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_8 -fir_compiler_v7_2_12=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_12 -div_gen_v5_1_15=$RDI_DATADIR/xsim/ip/div_gen_v5_1_15 -mdm_v3_2_16=$RDI_DATADIR/xsim/ip/mdm_v3_2_16 -v_axi4s_remap_v1_0_11=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_11 -xxv_ethernet_v2_5_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_5_3 -xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2 -ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig -remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4 -pr_axi_shutdown_manager_v1_0_1=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_1 -axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0 -smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0 -axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib -axi_dwidth_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_19 -xlconstant_v1_1_6=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_6 -tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6 -mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2 -v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1 -axi_fifo_mm_s_v4_2_1=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_1 -util_idelay_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_1 -rs_toolbox_v9_0_7=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_7 -v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0 -dsp_macro_v1_0_0=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_0 -pc_cfr_v6_2_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_2 -axi_timer_v2_0_21=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_21 -high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1 -axi_sideband_util_v1_0_3=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_3 -sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2 -gmii_to_rgmii_v4_0_7=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_0_7 -xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2 -high_speed_selectio_wiz_v3_5_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_5_1 -axi_msg_v1_0_5=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_5 -axi_ahblite_bridge_v3_0_16=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_16 -v_rgb2ycrcb_v7_1_13=$RDI_DATADIR/xsim/ip/v_rgb2ycrcb_v7_1_13 -v_mix_v4_0_0=$RDI_DATADIR/xsim/ip/v_mix_v4_0_0 -axi_ethernetlite_v3_0_17=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_17 -axi_uart16550_v2_0_21=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_21 -axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0 -vfb_v1_0_13=$RDI_DATADIR/xsim/ip/vfb_v1_0_13 -advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0 -ats_switch_v1_0_2=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_2 -interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4 -axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub -cpri_v8_10_3=$RDI_DATADIR/xsim/ip/cpri_v8_10_3 -c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6 -v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0 -stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0 -rld3_pl_v1_0_1=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_1 -ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0 -lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0 -axi_epc_v2_0_22=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_22 -g709_rs_encoder_v2_2_6=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_6 -blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6 -tmr_sem_v1_0_9=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_9 -fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6 -axi_vdma_v6_3_7=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_7 -axis_data_fifo_v1_1_20=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_20 -xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip -axi_ethernet_buffer_v2_0_20=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_20 -rs_encoder_v9_0_15=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_15 -axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0 -ta_dma_v1_0_3=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_3 -tcc_encoder_3gpp_v5_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_15 -axi_perf_mon_v5_0_21=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_21 -noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0 -sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1 -lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2 -v_csc_v1_0_13=$RDI_DATADIR/xsim/ip/v_csc_v1_0_13 -shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0 -lte_fft_v2_0_18=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_18 -gtwizard_ultrascale_v1_6_11=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_11 -amm_axi_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_5 -mii_to_rmii_v2_0_21=$RDI_DATADIR/xsim/ip/mii_to_rmii_v2_0_21 -videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5 -audio_clock_recovery_v1_0=$RDI_DATADIR/xsim/ip/audio_clock_recovery_v1_0 -cmac_v2_4_1=$RDI_DATADIR/xsim/ip/cmac_v2_4_1 -i2s_receiver_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_3 -v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0 -v_demosaic_v1_0_5=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_5 -remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4 -microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4 -hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3 -etrnic_v1_0_3=$RDI_DATADIR/xsim/ip/etrnic_v1_0_3 -xfft_v9_1_2=$RDI_DATADIR/xsim/ip/xfft_v9_1_2 -ddr4_pl_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_2 -xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6 -cmac_usplus_v2_5_3=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_5_3 -jesd204c_v4_1_1=$RDI_DATADIR/xsim/ip/jesd204c_v4_1_1 -debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1 -axis_protocol_checker_v2_0_3=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_3 -v_frmbuf_wr_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_2 -v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9 -mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4 -lte_dl_channel_encoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_15 -axi_protocol_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_19 -xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0 -clk_gen_sim_v1_0_0=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_0 -axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0 -microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7 -cmpy_v6_0_17=$RDI_DATADIR/xsim/ip/cmpy_v6_0_17 -cmac_v2_3_5=$RDI_DATADIR/xsim/ip/cmac_v2_3_5 -ieee802d3_400g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_7 -xxv_ethernet_v2_4_5=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_4_5 -axi_timebase_wdt_v3_0_11=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_11 -tcc_decoder_3gppmm_v2_0_18=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_18 -v_deinterlacer_v5_0_13=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_13 -dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16 -axi_fifo_mm_s_v4_1_16=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_16 -processing_system7_vip_v1_0_7=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_7 -g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18 -rs_decoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_16 -c_shift_ram_v12_0_13=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_13 -displayport_v7_0_11=$RDI_DATADIR/xsim/ip/displayport_v7_0_11 -v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0 -v_deinterlacer_v4_0_12=$RDI_DATADIR/xsim/ip/v_deinterlacer_v4_0_12 -sem_v4_1_12=$RDI_DATADIR/xsim/ip/sem_v4_1_12 -xaui_v12_3_6=$RDI_DATADIR/xsim/ip/xaui_v12_3_6 -ten_gig_eth_mac_v15_1_7=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_7 -oddr_v1_0_0=$RDI_DATADIR/xsim/ip/oddr_v1_0_0 -c_addsub_v12_0_13=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_13 -v_ccm_v6_0_15=$RDI_DATADIR/xsim/ip/v_ccm_v6_0_15 -zynq_ultra_ps_e_vip_v1_0_5=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_5 -cic_compiler_v4_0_14=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_14 -c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6 -axi_memory_init_v1_0_0=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_0 -pr_decoupler_v1_0_7=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_7 -timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4 -lte_pucch_receiver_v2_0_16=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_16 -zynq_ultra_ps_e_v3_2_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_3 -v_gamma_lut_v1_0_5=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_5 -bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0 -pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0 -tcc_encoder_3gpplte_v4_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_15 -polar_v1_0_3=$RDI_DATADIR/xsim/ip/polar_v1_0_3 -rxaui_v4_4_6=$RDI_DATADIR/xsim/ip/rxaui_v4_4_6 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-uhdsdi_gt_v1_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_3 -pc_cfr_v6_1_4=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_4 -lmb_v10_v3_0_9=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_9 -axis_interconnect_v1_1_17=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_17 -cordic_v6_0_15=$RDI_DATADIR/xsim/ip/cordic_v6_0_15 -axis_register_slice_v1_1_19=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_19 -axis_switch_v1_1_19=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_19 -axi_interconnect_v1_7_16=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_16 -mult_gen_v12_0_15=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_15 -spdif_v2_0_21=$RDI_DATADIR/xsim/ip/spdif_v2_0_21 -v_hscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_13 -ethernet_1_10_25g_v2_3_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_3_3 -xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6 -axi_quad_spi_v3_2_18=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_18 -axi_bram_ctrl_v4_1_1=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_1 -axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4 -axi_protocol_checker_v2_0_5=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_5 -axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0 -mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7 -ieee802d3_25g_rs_fec_v1_0_13=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_13 -aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0 -xtlm=$RDI_DATADIR/xsim/ip/xtlm -iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0 -ieee802d3_clause74_fec_v1_0_4=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_4 -xlconcat_v2_1_3=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_3 -perf_axi_tg_v1_0_8=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_8 -axi_crossbar_v2_1_20=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_20 -tsn_endpoint_ethernet_mac_block_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_4 -v_ycrcb2rgb_v7_1_13=$RDI_DATADIR/xsim/ip/v_ycrcb2rgb_v7_1_13 -xhmc_v1_0_9=$RDI_DATADIR/xsim/ip/xhmc_v1_0_9 -dp_videoaxi4s_bridge_v1_0_0=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_0 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-v_uhdsdi_audio_v2_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_1 -ldpc_v2_0_3=$RDI_DATADIR/xsim/ip/ldpc_v2_0_3 -xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6 -xpm=$RDI_DATADIR/xsim/ip/xpm -srio_gen2_v4_1_6=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_6 -g975_efec_i4_v1_0_17=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_17 -noc_na_v1_0_0=$RDI_DATADIR/xsim/ip/noc_na_v1_0_0 -roe_framer_v2_0_1=$RDI_DATADIR/xsim/ip/roe_framer_v2_0_1 -xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10 -generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0 -ten_gig_eth_pcs_pma_v6_0_15=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_15 -can_v5_0_22=$RDI_DATADIR/xsim/ip/can_v5_0_22 -av_pat_gen_v1_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_0 -fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1 -lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0 -axis_dwidth_converter_v1_1_18=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_18 -lte_rach_detector_v3_1_5=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_5 -xxv_ethernet_v3_0_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v3_0_3 -axi_iic_v2_0_22=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_22 -axi_pcie_v2_9_1=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_1 -util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4 -sim_trig_top_v1_0=$RDI_DATADIR/xsim/ip/sim_trig_top_v1_0 -v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0 -v_tpg_v7_0_13=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_13 -sd_fec_v1_1_3=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_3 -xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6 -lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2 -v_multi_scaler_v1_0_1=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_0_1 -axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0 -advanced_io_wizard_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_0 -mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8 -axi_pcie3_v3_0_9=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_9 -axi_vfifo_ctrl_v2_0_21=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_21 -xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0 diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf index 804c12cf..5d4ccedd 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf @@ -1,10 +1,10 @@ version:1 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:36:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:39:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3130:00:00 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-eof:3417462915 +eof:305610990 diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf index 71f49bca..28b3970c 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf @@ -1,11 +1,11 @@ version:1 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6164646578697374696e67697068616e646c6572:32:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:32:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:35:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657769706c6f636174696f6e68616e646c6572:31:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:34:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:35:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:32:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3132:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:33:00:00 -eof:1295650939 +eof:2810574154 diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc index 0161c5dc..2599f423 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc @@ -1,3 +1,3 @@ version:1 -6d6f64655f636f756e7465727c4755494d6f6465:6 +6d6f64655f636f756e7465727c4755494d6f6465:7 eof: diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml index 853a5270..639ecc15 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -18,22 +18,22 @@ This means code written to parse this file will need to be revisited each subseq - + - + - + - + @@ -57,17 +57,18 @@ This means code written to parse this file will need to be revisited each subseq + - + - + - +
diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/.Vivado_Synthesis.queue.rst b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/.Vivado_Synthesis.queue.rst deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/.vivado.begin.rst b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/.vivado.begin.rst deleted file mode 100644 index 2b4da80c..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/.vivado.end.rst b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/.vivado.end.rst deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/ISEWrap.js b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/ISEWrap.js deleted file mode 100644 index 97a2ecbc..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/ISEWrap.js +++ /dev/null @@ -1,270 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/ISEWrap.sh b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/ISEWrap.sh deleted file mode 100644 index f679f2e8..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/__synthesis_is_complete__ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/dont_touch.xdc b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/dont_touch.xdc deleted file mode 100644 index 7791a77c..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/dont_touch.xdc +++ /dev/null @@ -1,24 +0,0 @@ -# This file is automatically generated. -# It contains project source information necessary for synthesis and implementation. - -# IP: D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci -# IP: The module: 'selectio_lvds_rx' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_rx'. Do not add the DONT_TOUCH constraint. -set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet - -# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xdc -# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_rx'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet - -# IP: D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci -# IP: The module: 'selectio_lvds_rx' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_rx'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet - -# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xdc -# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_rx'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/gen_run.xml deleted file mode 100644 index 1bfd60c2..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/gen_run.xml +++ /dev/null @@ -1,62 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/htr.txt b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/htr.txt deleted file mode 100644 index 21b2764f..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log selectio_lvds_rx.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_rx.tcl diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/project.wdf b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/project.wdf deleted file mode 100644 index 556f4b3b..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/project.wdf +++ /dev/null @@ -1,61 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:36:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3633:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3633:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3661346264366134396337643466636438383330333461376438356536303661:506172656e742050412070726f6a656374204944:00 -eof:3953027363 diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/rundef.js b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/rundef.js deleted file mode 100644 index 834f3a85..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/rundef.js +++ /dev/null @@ -1,36 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log selectio_lvds_rx.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_rx.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/runme.bat b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/runme.bat deleted file mode 100644 index 1760626b..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/runme.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/runme.sh b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/runme.sh deleted file mode 100644 index a040db07..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/runme.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin -else - PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log selectio_lvds_rx.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_rx.tcl diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.dcp b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.dcp deleted file mode 100644 index d8aeb5d1..00000000 Binary files a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.dcp and /dev/null differ diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.tcl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.tcl deleted file mode 100644 index 7965001b..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.tcl +++ /dev/null @@ -1,156 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64 -set_param project.vivado.isBlockSynthRun true -set_msg_config -msgmgr_mode ooc_run -create_project -in_memory -part xc7k410tffg900-2 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] -set_property parent.project_path D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.xpr [current_project] -set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language Verilog [current_project] -set_property ip_output_repo d:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci -set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_ooc.xdc] -set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xdc] - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -read_xdc dont_touch.xdc -set_property used_in_implementation false [get_files dont_touch.xdc] -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1 -new_name selectio_lvds_rx -ip [get_ips selectio_lvds_rx]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top selectio_lvds_rx -part xc7k410tffg900-2 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix selectio_lvds_rx_ selectio_lvds_rx.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_stub.v - lappend ipCachedFiles selectio_lvds_rx_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_stub.vhdl - lappend ipCachedFiles selectio_lvds_rx_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_sim_netlist.v - lappend ipCachedFiles selectio_lvds_rx_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_sim_netlist.vhdl - lappend ipCachedFiles selectio_lvds_rx_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp selectio_lvds_rx.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips selectio_lvds_rx] -} - -rename_ref -prefix_all selectio_lvds_rx_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef selectio_lvds_rx.dcp -create_report "selectio_lvds_rx_synth_1_synth_report_utilization_0" "report_utilization -file selectio_lvds_rx_utilization_synth.rpt -pb selectio_lvds_rx_utilization_synth.pb" - -if { [catch { - write_verilog -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -}; # end if cached_ip - -add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.dcp -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci] - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.v D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.vhdl D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.v D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.vhdl D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.vds b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.vds deleted file mode 100644 index 09ad1655..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.vds +++ /dev/null @@ -1,289 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Sun Mar 19 18:25:34 2023 -# Process ID: 30212 -# Current directory: D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1 -# Command line: vivado.exe -log selectio_lvds_rx.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_rx.tcl -# Log file: D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.vds -# Journal file: D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1\vivado.jou -#----------------------------------------------------------- -Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl' -source selectio_lvds_rx.tcl -notrace -Command: synth_design -top selectio_lvds_rx -part xc7k410tffg900-2 -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' -INFO: [Device 21-403] Loading part xc7k410tffg900-2 -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 26720 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 884.641 ; gain = 176.336 ---------------------------------------------------------------------------------- -INFO: [Synth 8-6157] synthesizing module 'selectio_lvds_rx' [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.v:58] - Parameter SYS_W bound to: 2 - type: integer - Parameter DEV_W bound to: 2 - type: integer -INFO: [Synth 8-6157] synthesizing module 'selectio_lvds_rx_selectio_wiz' [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v:56] - Parameter SYS_W bound to: 2 - type: integer - Parameter DEV_W bound to: 2 - type: integer -INFO: [Synth 8-6157] synthesizing module 'IBUF' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:32856] - Parameter CAPACITANCE bound to: DONT_CARE - type: string - Parameter IBUF_DELAY_VALUE bound to: 0 - type: string - Parameter IBUF_LOW_PWR bound to: TRUE - type: string - Parameter IFD_DELAY_VALUE bound to: AUTO - type: string - Parameter IOSTANDARD bound to: LVCMOS33 - type: string -INFO: [Synth 8-6155] done synthesizing module 'IBUF' (1#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:32856] -INFO: [Synth 8-6157] synthesizing module 'FDRE' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] - Parameter INIT bound to: 1'b0 - Parameter IS_C_INVERTED bound to: 1'b0 - Parameter IS_D_INVERTED bound to: 1'b0 - Parameter IS_R_INVERTED bound to: 1'b0 -INFO: [Synth 8-6155] done synthesizing module 'FDRE' (2#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] -INFO: [Synth 8-6155] done synthesizing module 'selectio_lvds_rx_selectio_wiz' (3#1) [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v:56] -INFO: [Synth 8-6155] done synthesizing module 'selectio_lvds_rx' (4#1) [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.v:58] ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 952.234 ; gain = 243.930 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:00 ; elapsed = 00:00:03 . Memory (MB): peak = 952.234 ; gain = 243.930 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:00 ; elapsed = 00:00:03 . Memory (MB): peak = 952.234 ; gain = 243.930 ---------------------------------------------------------------------------------- -INFO: [Project 1-570] Preparing netlist for logic optimization - -Processing XDC Constraints -Initializing timing engine -Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_ooc.xdc] for cell 'inst' -Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_ooc.xdc] for cell 'inst' -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_ooc.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/selectio_lvds_rx_propImpl.xdc]. -Resolution: To avoid this warning, move constraints listed in [.Xil/selectio_lvds_rx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. -Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xdc] for cell 'inst' -Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xdc] for cell 'inst' -Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/dont_touch.xdc] -Finished Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/dont_touch.xdc] -Completed Processing XDC Constraints - -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 995.320 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1007.500 ; gain = 12.180 ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1007.500 ; gain = 299.195 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7k410tffg900-2 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1007.500 ; gain = 299.195 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying 'set_property' XDC Constraints ---------------------------------------------------------------------------------- -Applied set_property DONT_TOUCH = true for inst. (constraint file D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/dont_touch.xdc, line 9). ---------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1007.500 ; gain = 299.195 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1007.500 ; gain = 299.195 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- -Hierarchical RTL Component report ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 1540 (col length:140) -BRAMs: 1590 (col length: RAMB18 140 RAMB36 70) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1007.500 ; gain = 299.195 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Applying XDC Timing Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 1018.660 ; gain = 310.355 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 1018.660 ; gain = 310.355 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 1028.504 ; gain = 320.199 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+-----+------+ -| |Cell |Count | -+------+-----+------+ -|1 |FDRE | 2| -|2 |IBUF | 2| -+------+-----+------+ - -Report Instance Areas: -+------+---------+------------------------------+------+ -| |Instance |Module |Cells | -+------+---------+------------------------------+------+ -|1 |top | | 4| -|2 | inst |selectio_lvds_rx_selectio_wiz | 4| -+------+---------+------------------------------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:01 ; elapsed = 00:00:10 . Memory (MB): peak = 1043.328 ; gain = 279.758 -Synthesis Optimization Complete : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1070.727 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -18 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:17 . Memory (MB): peak = 1070.727 ; gain = 683.102 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1070.727 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.dcp' has been generated. -WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP selectio_lvds_rx, cache-ID = fffcbdb43410d449 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1070.727 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file selectio_lvds_rx_utilization_synth.rpt -pb selectio_lvds_rx_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sun Mar 19 18:25:55 2023... diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.v b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.v deleted file mode 100644 index 925586ae..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.v +++ /dev/null @@ -1,168 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sun Mar 19 18:25:55 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -// D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.v -// Design : selectio_lvds_rx -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* DEV_W = "2" *) (* SYS_W = "2" *) -(* NotValidForBitStream *) -module selectio_lvds_rx - (data_in_from_pins, - data_in_to_device, - clk_in, - io_reset); - input [1:0]data_in_from_pins; - output [1:0]data_in_to_device; - input clk_in; - input io_reset; - - wire clk_in; - (* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire [1:0]data_in_from_pins; - wire [1:0]data_in_to_device; - wire io_reset; - - (* DEV_W = "2" *) - (* SYS_W = "2" *) - selectio_lvds_rx_selectio_lvds_rx_selectio_wiz inst - (.clk_in(clk_in), - .data_in_from_pins(data_in_from_pins), - .data_in_to_device(data_in_to_device), - .io_reset(io_reset)); -endmodule - -(* DEV_W = "2" *) (* ORIG_REF_NAME = "selectio_lvds_rx_selectio_wiz" *) (* SYS_W = "2" *) -module selectio_lvds_rx_selectio_lvds_rx_selectio_wiz - (data_in_from_pins, - data_in_to_device, - clk_in, - io_reset); - input [1:0]data_in_from_pins; - output [1:0]data_in_to_device; - input clk_in; - input io_reset; - - wire clk_in; - wire [1:0]data_in_from_pins; - wire [1:0]data_in_from_pins_int; - wire [1:0]data_in_to_device; - wire io_reset; - - (* BOX_TYPE = "PRIMITIVE" *) - (* IOB = "TRUE" *) - FDRE #( - .INIT(1'b0), - .IS_C_INVERTED(1'b0), - .IS_D_INVERTED(1'b0), - .IS_R_INVERTED(1'b0)) - \pins[0].fdre_in_inst - (.C(clk_in), - .CE(1'b1), - .D(data_in_from_pins_int[0]), - .Q(data_in_to_device[0]), - .R(io_reset)); - (* BOX_TYPE = "PRIMITIVE" *) - (* CAPACITANCE = "DONT_CARE" *) - (* IBUF_DELAY_VALUE = "0" *) - (* IFD_DELAY_VALUE = "AUTO" *) - IBUF \pins[0].ibuf_inst - (.I(data_in_from_pins[0]), - .O(data_in_from_pins_int[0])); - (* BOX_TYPE = "PRIMITIVE" *) - (* IOB = "TRUE" *) - FDRE #( - .INIT(1'b0), - .IS_C_INVERTED(1'b0), - .IS_D_INVERTED(1'b0), - .IS_R_INVERTED(1'b0)) - \pins[1].fdre_in_inst - (.C(clk_in), - .CE(1'b1), - .D(data_in_from_pins_int[1]), - .Q(data_in_to_device[1]), - .R(io_reset)); - (* BOX_TYPE = "PRIMITIVE" *) - (* CAPACITANCE = "DONT_CARE" *) - (* IBUF_DELAY_VALUE = "0" *) - (* IFD_DELAY_VALUE = "AUTO" *) - IBUF \pins[1].ibuf_inst - (.I(data_in_from_pins[1]), - .O(data_in_from_pins_int[1])); -endmodule -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.vhdl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.vhdl deleted file mode 100644 index 8998975d..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.vhdl +++ /dev/null @@ -1,121 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sun Mar 19 18:25:55 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim --- D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.vhdl --- Design : selectio_lvds_rx --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity selectio_lvds_rx_selectio_lvds_rx_selectio_wiz is - port ( - data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 ); - data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 ); - clk_in : in STD_LOGIC; - io_reset : in STD_LOGIC - ); - attribute DEV_W : integer; - attribute DEV_W of selectio_lvds_rx_selectio_lvds_rx_selectio_wiz : entity is 2; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of selectio_lvds_rx_selectio_lvds_rx_selectio_wiz : entity is "selectio_lvds_rx_selectio_wiz"; - attribute SYS_W : integer; - attribute SYS_W of selectio_lvds_rx_selectio_lvds_rx_selectio_wiz : entity is 2; -end selectio_lvds_rx_selectio_lvds_rx_selectio_wiz; - -architecture STRUCTURE of selectio_lvds_rx_selectio_lvds_rx_selectio_wiz is - signal data_in_from_pins_int : STD_LOGIC_VECTOR ( 1 downto 0 ); - attribute BOX_TYPE : string; - attribute BOX_TYPE of \pins[0].fdre_in_inst\ : label is "PRIMITIVE"; - attribute IOB : string; - attribute IOB of \pins[0].fdre_in_inst\ : label is "TRUE"; - attribute BOX_TYPE of \pins[0].ibuf_inst\ : label is "PRIMITIVE"; - attribute CAPACITANCE : string; - attribute CAPACITANCE of \pins[0].ibuf_inst\ : label is "DONT_CARE"; - attribute IBUF_DELAY_VALUE : string; - attribute IBUF_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "0"; - attribute IFD_DELAY_VALUE : string; - attribute IFD_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "AUTO"; - attribute BOX_TYPE of \pins[1].fdre_in_inst\ : label is "PRIMITIVE"; - attribute IOB of \pins[1].fdre_in_inst\ : label is "TRUE"; - attribute BOX_TYPE of \pins[1].ibuf_inst\ : label is "PRIMITIVE"; - attribute CAPACITANCE of \pins[1].ibuf_inst\ : label is "DONT_CARE"; - attribute IBUF_DELAY_VALUE of \pins[1].ibuf_inst\ : label is "0"; - attribute IFD_DELAY_VALUE of \pins[1].ibuf_inst\ : label is "AUTO"; -begin -\pins[0].fdre_in_inst\: unisim.vcomponents.FDRE - generic map( - INIT => '0', - IS_C_INVERTED => '0', - IS_D_INVERTED => '0', - IS_R_INVERTED => '0' - ) - port map ( - C => clk_in, - CE => '1', - D => data_in_from_pins_int(0), - Q => data_in_to_device(0), - R => io_reset - ); -\pins[0].ibuf_inst\: unisim.vcomponents.IBUF - port map ( - I => data_in_from_pins(0), - O => data_in_from_pins_int(0) - ); -\pins[1].fdre_in_inst\: unisim.vcomponents.FDRE - generic map( - INIT => '0', - IS_C_INVERTED => '0', - IS_D_INVERTED => '0', - IS_R_INVERTED => '0' - ) - port map ( - C => clk_in, - CE => '1', - D => data_in_from_pins_int(1), - Q => data_in_to_device(1), - R => io_reset - ); -\pins[1].ibuf_inst\: unisim.vcomponents.IBUF - port map ( - I => data_in_from_pins(1), - O => data_in_from_pins_int(1) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity selectio_lvds_rx is - port ( - data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 ); - data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 ); - clk_in : in STD_LOGIC; - io_reset : in STD_LOGIC - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of selectio_lvds_rx : entity is true; - attribute DEV_W : integer; - attribute DEV_W of selectio_lvds_rx : entity is 2; - attribute SYS_W : integer; - attribute SYS_W of selectio_lvds_rx : entity is 2; -end selectio_lvds_rx; - -architecture STRUCTURE of selectio_lvds_rx is - attribute DEV_W of inst : label is 2; - attribute SYS_W of inst : label is 2; -begin -inst: entity work.selectio_lvds_rx_selectio_lvds_rx_selectio_wiz - port map ( - clk_in => clk_in, - data_in_from_pins(1 downto 0) => data_in_from_pins(1 downto 0), - data_in_to_device(1 downto 0) => data_in_to_device(1 downto 0), - io_reset => io_reset - ); -end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.v b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.v deleted file mode 100644 index eadd56c4..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.v +++ /dev/null @@ -1,23 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sun Mar 19 18:25:55 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -// D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.v -// Design : selectio_lvds_rx -// Purpose : Stub declaration of top-level module interface -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -module selectio_lvds_rx(data_in_from_pins, data_in_to_device, clk_in, - io_reset) -/* synthesis syn_black_box black_box_pad_pin="data_in_from_pins[1:0],data_in_to_device[1:0],clk_in,io_reset" */; - input [1:0]data_in_from_pins; - output [1:0]data_in_to_device; - input clk_in; - input io_reset; -endmodule diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.vhdl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.vhdl deleted file mode 100644 index 681e6822..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.vhdl +++ /dev/null @@ -1,31 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sun Mar 19 18:25:55 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub --- D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.vhdl --- Design : selectio_lvds_rx --- Purpose : Stub declaration of top-level module interface --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity selectio_lvds_rx is - Port ( - data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 ); - data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 ); - clk_in : in STD_LOGIC; - io_reset : in STD_LOGIC - ); - -end selectio_lvds_rx; - -architecture stub of selectio_lvds_rx is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "data_in_from_pins[1:0],data_in_to_device[1:0],clk_in,io_reset"; -begin -end; diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_utilization_synth.pb b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_utilization_synth.pb deleted file mode 100644 index ac67e098..00000000 Binary files a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_utilization_synth.pb and /dev/null differ diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_utilization_synth.rpt b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_utilization_synth.rpt deleted file mode 100644 index 879d224b..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_utilization_synth.rpt +++ /dev/null @@ -1,174 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -| Date : Sun Mar 19 18:25:55 2023 -| Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -| Command : report_utilization -file selectio_lvds_rx_utilization_synth.rpt -pb selectio_lvds_rx_utilization_synth.pb -| Design : selectio_lvds_rx -| Device : 7k410tffg900-2 -| Design State : Synthesized ---------------------------------------------------------------------------------------------------------------------------- - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 0 | 0 | 254200 | 0.00 | -| LUT as Logic | 0 | 0 | 254200 | 0.00 | -| LUT as Memory | 0 | 0 | 90600 | 0.00 | -| Slice Registers | 2 | 2 | 508400 | <0.01 | -| Register as Flip Flop | 2 | 2 | 508400 | <0.01 | -| Register as Latch | 0 | 0 | 508400 | 0.00 | -| F7 Muxes | 0 | 0 | 127100 | 0.00 | -| F8 Muxes | 0 | 0 | 63550 | 0.00 | -+-------------------------+------+-------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 2 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Memory ---------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 795 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 795 | 0.00 | -| RAMB18 | 0 | 0 | 1590 | 0.00 | -+----------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -3. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 1540 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -4. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 2 | 0 | 500 | 0.40 | -| Bonded IPADs | 0 | 0 | 50 | 0.00 | -| Bonded OPADs | 0 | 0 | 32 | 0.00 | -| PHY_CONTROL | 0 | 0 | 10 | 0.00 | -| PHASER_REF | 0 | 0 | 10 | 0.00 | -| OUT_FIFO | 0 | 0 | 40 | 0.00 | -| IN_FIFO | 0 | 0 | 40 | 0.00 | -| IDELAYCTRL | 0 | 0 | 10 | 0.00 | -| IBUFDS | 0 | 0 | 480 | 0.00 | -| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | -| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 | -| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | -| ILOGIC | 0 | 0 | 500 | 0.00 | -| OLOGIC | 0 | 0 | 500 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -5. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 0 | 0 | 32 | 0.00 | -| BUFIO | 0 | 0 | 40 | 0.00 | -| MMCME2_ADV | 0 | 0 | 10 | 0.00 | -| PLLE2_ADV | 0 | 0 | 10 | 0.00 | -| BUFMRCE | 0 | 0 | 20 | 0.00 | -| BUFHCE | 0 | 0 | 168 | 0.00 | -| BUFR | 0 | 0 | 40 | 0.00 | -+------------+------+-------+-----------+-------+ - - -6. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -7. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| IBUF | 2 | IO | -| FDRE | 2 | Flop & Latch | -+----------+------+---------------------+ - - -8. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -9. Instantiated Netlists ------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/vivado.pb b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/vivado.pb deleted file mode 100644 index 81f52aab..00000000 Binary files a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/vivado.pb and /dev/null differ diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/.Vivado_Synthesis.queue.rst b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/.Vivado_Synthesis.queue.rst deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/.vivado.begin.rst b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/.vivado.begin.rst deleted file mode 100644 index 9888d76d..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/.vivado.end.rst b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/.vivado.end.rst deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/ISEWrap.js b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/ISEWrap.js deleted file mode 100644 index 97a2ecbc..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/ISEWrap.js +++ /dev/null @@ -1,270 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/ISEWrap.sh b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/ISEWrap.sh deleted file mode 100644 index f679f2e8..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/__synthesis_is_complete__ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/dont_touch.xdc b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/dont_touch.xdc deleted file mode 100644 index 00cea94d..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/dont_touch.xdc +++ /dev/null @@ -1,24 +0,0 @@ -# This file is automatically generated. -# It contains project source information necessary for synthesis and implementation. - -# IP: D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci -# IP: The module: 'selectio_lvds_tx' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_tx'. Do not add the DONT_TOUCH constraint. -set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet - -# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xdc -# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_tx'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet - -# IP: D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci -# IP: The module: 'selectio_lvds_tx' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_tx'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet - -# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xdc -# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_tx'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/gen_run.xml deleted file mode 100644 index 5808da1a..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/gen_run.xml +++ /dev/null @@ -1,59 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/htr.txt b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/htr.txt deleted file mode 100644 index 6f803f89..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log selectio_lvds_tx.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_tx.tcl diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/project.wdf b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/project.wdf deleted file mode 100644 index bec260d7..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/project.wdf +++ /dev/null @@ -1,61 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:36:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3539:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3539:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3661346264366134396337643466636438383330333461376438356536303661:506172656e742050412070726f6a656374204944:00 -eof:1501154971 diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/rundef.js b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/rundef.js deleted file mode 100644 index 99169c8a..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/rundef.js +++ /dev/null @@ -1,36 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log selectio_lvds_tx.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_tx.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/runme.bat b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/runme.bat deleted file mode 100644 index 1760626b..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/runme.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/runme.sh b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/runme.sh deleted file mode 100644 index d2e2a879..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/runme.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin -else - PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log selectio_lvds_tx.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_tx.tcl diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.dcp b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.dcp deleted file mode 100644 index 0b9175b0..00000000 Binary files a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.dcp and /dev/null differ diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.tcl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.tcl deleted file mode 100644 index 2a7aa66d..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.tcl +++ /dev/null @@ -1,156 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64 -set_param project.vivado.isBlockSynthRun true -set_msg_config -msgmgr_mode ooc_run -create_project -in_memory -part xc7k410tffg900-2 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] -set_property parent.project_path D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.xpr [current_project] -set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language Verilog [current_project] -set_property ip_output_repo d:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci -set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx_ooc.xdc] -set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xdc] - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -read_xdc dont_touch.xdc -set_property used_in_implementation false [get_files dont_touch.xdc] -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1 -new_name selectio_lvds_tx -ip [get_ips selectio_lvds_tx]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top selectio_lvds_tx -part xc7k410tffg900-2 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix selectio_lvds_tx_ selectio_lvds_tx.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_stub.v - lappend ipCachedFiles selectio_lvds_tx_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_stub.vhdl - lappend ipCachedFiles selectio_lvds_tx_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_sim_netlist.v - lappend ipCachedFiles selectio_lvds_tx_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_sim_netlist.vhdl - lappend ipCachedFiles selectio_lvds_tx_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp selectio_lvds_tx.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips selectio_lvds_tx] -} - -rename_ref -prefix_all selectio_lvds_tx_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef selectio_lvds_tx.dcp -create_report "selectio_lvds_tx_synth_1_synth_report_utilization_0" "report_utilization -file selectio_lvds_tx_utilization_synth.rpt -pb selectio_lvds_tx_utilization_synth.pb" - -if { [catch { - write_verilog -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -}; # end if cached_ip - -add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.dcp -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci] - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.vds b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.vds deleted file mode 100644 index d97a62cc..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.vds +++ /dev/null @@ -1,305 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Sun Mar 19 17:31:58 2023 -# Process ID: 14484 -# Current directory: D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1 -# Command line: vivado.exe -log selectio_lvds_tx.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_tx.tcl -# Log file: D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.vds -# Journal file: D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1\vivado.jou -#----------------------------------------------------------- -Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl' -source selectio_lvds_tx.tcl -notrace -Command: synth_design -top selectio_lvds_tx -part xc7k410tffg900-2 -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' -INFO: [Device 21-403] Loading part xc7k410tffg900-2 -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 4804 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 883.914 ; gain = 177.477 ---------------------------------------------------------------------------------- -INFO: [Synth 8-6157] synthesizing module 'selectio_lvds_tx' [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.v:58] - Parameter SYS_W bound to: 4 - type: integer - Parameter DEV_W bound to: 4 - type: integer -INFO: [Synth 8-6157] synthesizing module 'selectio_lvds_tx_selectio_wiz' [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v:56] - Parameter SYS_W bound to: 4 - type: integer - Parameter DEV_W bound to: 4 - type: integer -INFO: [Synth 8-6157] synthesizing module 'OBUF' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:45998] - Parameter CAPACITANCE bound to: DONT_CARE - type: string - Parameter DRIVE bound to: 12 - type: integer - Parameter IOSTANDARD bound to: LVCMOS33 - type: string - Parameter SLEW bound to: SLOW - type: string -INFO: [Synth 8-6155] done synthesizing module 'OBUF' (1#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:45998] -INFO: [Synth 8-6157] synthesizing module 'FDRE' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] - Parameter INIT bound to: 1'b0 - Parameter IS_C_INVERTED bound to: 1'b0 - Parameter IS_D_INVERTED bound to: 1'b0 - Parameter IS_R_INVERTED bound to: 1'b0 -INFO: [Synth 8-6155] done synthesizing module 'FDRE' (2#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] -INFO: [Synth 8-6157] synthesizing module 'IBUF' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:32856] - Parameter CAPACITANCE bound to: DONT_CARE - type: string - Parameter IBUF_DELAY_VALUE bound to: 0 - type: string - Parameter IBUF_LOW_PWR bound to: TRUE - type: string - Parameter IFD_DELAY_VALUE bound to: AUTO - type: string - Parameter IOSTANDARD bound to: LVCMOS33 - type: string -INFO: [Synth 8-6155] done synthesizing module 'IBUF' (3#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:32856] -INFO: [Synth 8-6157] synthesizing module 'BUFR' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1402] - Parameter BUFR_DIVIDE bound to: BYPASS - type: string - Parameter SIM_DEVICE bound to: 7SERIES - type: string -INFO: [Synth 8-6155] done synthesizing module 'BUFR' (4#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1402] -INFO: [Synth 8-6155] done synthesizing module 'selectio_lvds_tx_selectio_wiz' (5#1) [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v:56] -INFO: [Synth 8-6155] done synthesizing module 'selectio_lvds_tx' (6#1) [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.v:58] ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 950.152 ; gain = 243.715 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:00 ; elapsed = 00:00:03 . Memory (MB): peak = 950.152 ; gain = 243.715 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:00 ; elapsed = 00:00:03 . Memory (MB): peak = 950.152 ; gain = 243.715 ---------------------------------------------------------------------------------- -INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization - -Processing XDC Constraints -Initializing timing engine -Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx_ooc.xdc] for cell 'inst' -Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx_ooc.xdc] for cell 'inst' -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx_ooc.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/selectio_lvds_tx_propImpl.xdc]. -Resolution: To avoid this warning, move constraints listed in [.Xil/selectio_lvds_tx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. -Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xdc] for cell 'inst' -Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xdc] for cell 'inst' -Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/dont_touch.xdc] -Finished Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/dont_touch.xdc] -Completed Processing XDC Constraints - -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1012.727 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1024.238 ; gain = 11.512 ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1024.238 ; gain = 317.801 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7k410tffg900-2 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1024.238 ; gain = 317.801 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying 'set_property' XDC Constraints ---------------------------------------------------------------------------------- -Applied set_property DONT_TOUCH = true for inst. (constraint file D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/dont_touch.xdc, line 9). ---------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1024.238 ; gain = 317.801 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1024.238 ; gain = 317.801 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- -Hierarchical RTL Component report ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 1540 (col length:140) -BRAMs: 1590 (col length: RAMB18 140 RAMB36 70) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1024.238 ; gain = 317.801 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Applying XDC Timing Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 1024.238 ; gain = 317.801 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 1024.238 ; gain = 317.801 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 1024.535 ; gain = 318.098 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1040.312 ; gain = 333.875 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1040.312 ; gain = 333.875 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1040.312 ; gain = 333.875 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1040.312 ; gain = 333.875 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1040.312 ; gain = 333.875 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1040.312 ; gain = 333.875 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+-----+------+ -| |Cell |Count | -+------+-----+------+ -|1 |BUFR | 1| -|2 |FDRE | 4| -|3 |IBUF | 1| -|4 |OBUF | 4| -+------+-----+------+ - -Report Instance Areas: -+------+---------+------------------------------+------+ -| |Instance |Module |Cells | -+------+---------+------------------------------+------+ -|1 |top | | 10| -|2 | inst |selectio_lvds_tx_selectio_wiz | 10| -+------+---------+------------------------------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1040.312 ; gain = 333.875 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 1040.312 ; gain = 259.789 -Synthesis Optimization Complete : Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.312 ; gain = 333.875 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1068.441 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:03 ; elapsed = 00:00:18 . Memory (MB): peak = 1068.441 ; gain = 681.945 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1068.441 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.dcp' has been generated. -WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP selectio_lvds_tx, cache-ID = 1ad2c59fcdfd22ab -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1068.441 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file selectio_lvds_tx_utilization_synth.rpt -pb selectio_lvds_tx_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sun Mar 19 17:32:20 2023... diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v deleted file mode 100644 index 9cf47661..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v +++ /dev/null @@ -1,227 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sun Mar 19 17:32:20 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -// D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v -// Design : selectio_lvds_tx -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* DEV_W = "4" *) (* SYS_W = "4" *) -(* NotValidForBitStream *) -module selectio_lvds_tx - (data_out_from_device, - data_out_to_pins, - clk_in, - clk_out, - io_reset); - input [3:0]data_out_from_device; - output [3:0]data_out_to_pins; - input clk_in; - output clk_out; - input io_reset; - - (* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire clk_in; - wire clk_out; - wire [3:0]data_out_from_device; - (* DRIVE = "12" *) (* IOSTANDARD = "LVCMOS33" *) (* SLEW = "SLOW" *) wire [3:0]data_out_to_pins; - wire io_reset; - - (* DEV_W = "4" *) - (* SYS_W = "4" *) - selectio_lvds_tx_selectio_lvds_tx_selectio_wiz inst - (.clk_in(clk_in), - .clk_out(clk_out), - .data_out_from_device(data_out_from_device), - .data_out_to_pins(data_out_to_pins), - .io_reset(io_reset)); -endmodule - -(* DEV_W = "4" *) (* ORIG_REF_NAME = "selectio_lvds_tx_selectio_wiz" *) (* SYS_W = "4" *) -module selectio_lvds_tx_selectio_lvds_tx_selectio_wiz - (data_out_from_device, - data_out_to_pins, - clk_in, - clk_out, - io_reset); - input [3:0]data_out_from_device; - output [3:0]data_out_to_pins; - input clk_in; - output clk_out; - input io_reset; - - wire clk_in; - wire clk_in_int; - wire clk_out; - wire [3:0]data_out_from_device; - wire [3:0]data_out_to_pins; - wire io_reset; - wire \pins[0].data_out_from_device_q ; - wire \pins[1].data_out_from_device_q ; - wire \pins[2].data_out_from_device_q ; - wire \pins[3].data_out_from_device_q ; - - (* BOX_TYPE = "PRIMITIVE" *) - BUFR #( - .BUFR_DIVIDE("BYPASS"), - .SIM_DEVICE("7SERIES")) - clkout_buf_inst - (.CE(1'b1), - .CLR(1'b0), - .I(clk_in_int), - .O(clk_out)); - (* BOX_TYPE = "PRIMITIVE" *) - (* CAPACITANCE = "DONT_CARE" *) - (* IBUF_DELAY_VALUE = "0" *) - (* IFD_DELAY_VALUE = "AUTO" *) - IBUF ibuf_clk_inst - (.I(clk_in), - .O(clk_in_int)); - (* BOX_TYPE = "PRIMITIVE" *) - (* IOB = "TRUE" *) - FDRE #( - .INIT(1'b0), - .IS_C_INVERTED(1'b0), - .IS_D_INVERTED(1'b0), - .IS_R_INVERTED(1'b0)) - \pins[0].fdre_out_inst - (.C(clk_out), - .CE(1'b1), - .D(data_out_from_device[0]), - .Q(\pins[0].data_out_from_device_q ), - .R(io_reset)); - (* BOX_TYPE = "PRIMITIVE" *) - (* CAPACITANCE = "DONT_CARE" *) - OBUF \pins[0].obuf_inst - (.I(\pins[0].data_out_from_device_q ), - .O(data_out_to_pins[0])); - (* BOX_TYPE = "PRIMITIVE" *) - (* IOB = "TRUE" *) - FDRE #( - .INIT(1'b0), - .IS_C_INVERTED(1'b0), - .IS_D_INVERTED(1'b0), - .IS_R_INVERTED(1'b0)) - \pins[1].fdre_out_inst - (.C(clk_out), - .CE(1'b1), - .D(data_out_from_device[1]), - .Q(\pins[1].data_out_from_device_q ), - .R(io_reset)); - (* BOX_TYPE = "PRIMITIVE" *) - (* CAPACITANCE = "DONT_CARE" *) - OBUF \pins[1].obuf_inst - (.I(\pins[1].data_out_from_device_q ), - .O(data_out_to_pins[1])); - (* BOX_TYPE = "PRIMITIVE" *) - (* IOB = "TRUE" *) - FDRE #( - .INIT(1'b0), - .IS_C_INVERTED(1'b0), - .IS_D_INVERTED(1'b0), - .IS_R_INVERTED(1'b0)) - \pins[2].fdre_out_inst - (.C(clk_out), - .CE(1'b1), - .D(data_out_from_device[2]), - .Q(\pins[2].data_out_from_device_q ), - .R(io_reset)); - (* BOX_TYPE = "PRIMITIVE" *) - (* CAPACITANCE = "DONT_CARE" *) - OBUF \pins[2].obuf_inst - (.I(\pins[2].data_out_from_device_q ), - .O(data_out_to_pins[2])); - (* BOX_TYPE = "PRIMITIVE" *) - (* IOB = "TRUE" *) - FDRE #( - .INIT(1'b0), - .IS_C_INVERTED(1'b0), - .IS_D_INVERTED(1'b0), - .IS_R_INVERTED(1'b0)) - \pins[3].fdre_out_inst - (.C(clk_out), - .CE(1'b1), - .D(data_out_from_device[3]), - .Q(\pins[3].data_out_from_device_q ), - .R(io_reset)); - (* BOX_TYPE = "PRIMITIVE" *) - (* CAPACITANCE = "DONT_CARE" *) - OBUF \pins[3].obuf_inst - (.I(\pins[3].data_out_from_device_q ), - .O(data_out_to_pins[3])); -endmodule -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl deleted file mode 100644 index 196d3869..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl +++ /dev/null @@ -1,193 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sun Mar 19 17:32:20 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim --- D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl --- Design : selectio_lvds_tx --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity selectio_lvds_tx_selectio_lvds_tx_selectio_wiz is - port ( - data_out_from_device : in STD_LOGIC_VECTOR ( 3 downto 0 ); - data_out_to_pins : out STD_LOGIC_VECTOR ( 3 downto 0 ); - clk_in : in STD_LOGIC; - clk_out : out STD_LOGIC; - io_reset : in STD_LOGIC - ); - attribute DEV_W : integer; - attribute DEV_W of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz : entity is 4; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz : entity is "selectio_lvds_tx_selectio_wiz"; - attribute SYS_W : integer; - attribute SYS_W of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz : entity is 4; -end selectio_lvds_tx_selectio_lvds_tx_selectio_wiz; - -architecture STRUCTURE of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz is - signal clk_in_int : STD_LOGIC; - signal \^clk_out\ : STD_LOGIC; - signal \pins[0].data_out_from_device_q\ : STD_LOGIC; - signal \pins[1].data_out_from_device_q\ : STD_LOGIC; - signal \pins[2].data_out_from_device_q\ : STD_LOGIC; - signal \pins[3].data_out_from_device_q\ : STD_LOGIC; - attribute BOX_TYPE : string; - attribute BOX_TYPE of clkout_buf_inst : label is "PRIMITIVE"; - attribute BOX_TYPE of ibuf_clk_inst : label is "PRIMITIVE"; - attribute CAPACITANCE : string; - attribute CAPACITANCE of ibuf_clk_inst : label is "DONT_CARE"; - attribute IBUF_DELAY_VALUE : string; - attribute IBUF_DELAY_VALUE of ibuf_clk_inst : label is "0"; - attribute IFD_DELAY_VALUE : string; - attribute IFD_DELAY_VALUE of ibuf_clk_inst : label is "AUTO"; - attribute BOX_TYPE of \pins[0].fdre_out_inst\ : label is "PRIMITIVE"; - attribute IOB : string; - attribute IOB of \pins[0].fdre_out_inst\ : label is "TRUE"; - attribute BOX_TYPE of \pins[0].obuf_inst\ : label is "PRIMITIVE"; - attribute CAPACITANCE of \pins[0].obuf_inst\ : label is "DONT_CARE"; - attribute BOX_TYPE of \pins[1].fdre_out_inst\ : label is "PRIMITIVE"; - attribute IOB of \pins[1].fdre_out_inst\ : label is "TRUE"; - attribute BOX_TYPE of \pins[1].obuf_inst\ : label is "PRIMITIVE"; - attribute CAPACITANCE of \pins[1].obuf_inst\ : label is "DONT_CARE"; - attribute BOX_TYPE of \pins[2].fdre_out_inst\ : label is "PRIMITIVE"; - attribute IOB of \pins[2].fdre_out_inst\ : label is "TRUE"; - attribute BOX_TYPE of \pins[2].obuf_inst\ : label is "PRIMITIVE"; - attribute CAPACITANCE of \pins[2].obuf_inst\ : label is "DONT_CARE"; - attribute BOX_TYPE of \pins[3].fdre_out_inst\ : label is "PRIMITIVE"; - attribute IOB of \pins[3].fdre_out_inst\ : label is "TRUE"; - attribute BOX_TYPE of \pins[3].obuf_inst\ : label is "PRIMITIVE"; - attribute CAPACITANCE of \pins[3].obuf_inst\ : label is "DONT_CARE"; -begin - clk_out <= \^clk_out\; -clkout_buf_inst: unisim.vcomponents.BUFR - generic map( - BUFR_DIVIDE => "BYPASS", - SIM_DEVICE => "7SERIES" - ) - port map ( - CE => '1', - CLR => '0', - I => clk_in_int, - O => \^clk_out\ - ); -ibuf_clk_inst: unisim.vcomponents.IBUF - port map ( - I => clk_in, - O => clk_in_int - ); -\pins[0].fdre_out_inst\: unisim.vcomponents.FDRE - generic map( - INIT => '0', - IS_C_INVERTED => '0', - IS_D_INVERTED => '0', - IS_R_INVERTED => '0' - ) - port map ( - C => \^clk_out\, - CE => '1', - D => data_out_from_device(0), - Q => \pins[0].data_out_from_device_q\, - R => io_reset - ); -\pins[0].obuf_inst\: unisim.vcomponents.OBUF - port map ( - I => \pins[0].data_out_from_device_q\, - O => data_out_to_pins(0) - ); -\pins[1].fdre_out_inst\: unisim.vcomponents.FDRE - generic map( - INIT => '0', - IS_C_INVERTED => '0', - IS_D_INVERTED => '0', - IS_R_INVERTED => '0' - ) - port map ( - C => \^clk_out\, - CE => '1', - D => data_out_from_device(1), - Q => \pins[1].data_out_from_device_q\, - R => io_reset - ); -\pins[1].obuf_inst\: unisim.vcomponents.OBUF - port map ( - I => \pins[1].data_out_from_device_q\, - O => data_out_to_pins(1) - ); -\pins[2].fdre_out_inst\: unisim.vcomponents.FDRE - generic map( - INIT => '0', - IS_C_INVERTED => '0', - IS_D_INVERTED => '0', - IS_R_INVERTED => '0' - ) - port map ( - C => \^clk_out\, - CE => '1', - D => data_out_from_device(2), - Q => \pins[2].data_out_from_device_q\, - R => io_reset - ); -\pins[2].obuf_inst\: unisim.vcomponents.OBUF - port map ( - I => \pins[2].data_out_from_device_q\, - O => data_out_to_pins(2) - ); -\pins[3].fdre_out_inst\: unisim.vcomponents.FDRE - generic map( - INIT => '0', - IS_C_INVERTED => '0', - IS_D_INVERTED => '0', - IS_R_INVERTED => '0' - ) - port map ( - C => \^clk_out\, - CE => '1', - D => data_out_from_device(3), - Q => \pins[3].data_out_from_device_q\, - R => io_reset - ); -\pins[3].obuf_inst\: unisim.vcomponents.OBUF - port map ( - I => \pins[3].data_out_from_device_q\, - O => data_out_to_pins(3) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity selectio_lvds_tx is - port ( - data_out_from_device : in STD_LOGIC_VECTOR ( 3 downto 0 ); - data_out_to_pins : out STD_LOGIC_VECTOR ( 3 downto 0 ); - clk_in : in STD_LOGIC; - clk_out : out STD_LOGIC; - io_reset : in STD_LOGIC - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of selectio_lvds_tx : entity is true; - attribute DEV_W : integer; - attribute DEV_W of selectio_lvds_tx : entity is 4; - attribute SYS_W : integer; - attribute SYS_W of selectio_lvds_tx : entity is 4; -end selectio_lvds_tx; - -architecture STRUCTURE of selectio_lvds_tx is - attribute DEV_W of inst : label is 4; - attribute SYS_W of inst : label is 4; -begin -inst: entity work.selectio_lvds_tx_selectio_lvds_tx_selectio_wiz - port map ( - clk_in => clk_in, - clk_out => clk_out, - data_out_from_device(3 downto 0) => data_out_from_device(3 downto 0), - data_out_to_pins(3 downto 0) => data_out_to_pins(3 downto 0), - io_reset => io_reset - ); -end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v deleted file mode 100644 index b520abfc..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v +++ /dev/null @@ -1,24 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sun Mar 19 17:32:20 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -// D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v -// Design : selectio_lvds_tx -// Purpose : Stub declaration of top-level module interface -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -module selectio_lvds_tx(data_out_from_device, data_out_to_pins, - clk_in, clk_out, io_reset) -/* synthesis syn_black_box black_box_pad_pin="data_out_from_device[3:0],data_out_to_pins[3:0],clk_in,clk_out,io_reset" */; - input [3:0]data_out_from_device; - output [3:0]data_out_to_pins; - input clk_in; - output clk_out; - input io_reset; -endmodule diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl deleted file mode 100644 index 9591245e..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl +++ /dev/null @@ -1,32 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sun Mar 19 17:32:20 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub --- D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl --- Design : selectio_lvds_tx --- Purpose : Stub declaration of top-level module interface --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity selectio_lvds_tx is - Port ( - data_out_from_device : in STD_LOGIC_VECTOR ( 3 downto 0 ); - data_out_to_pins : out STD_LOGIC_VECTOR ( 3 downto 0 ); - clk_in : in STD_LOGIC; - clk_out : out STD_LOGIC; - io_reset : in STD_LOGIC - ); - -end selectio_lvds_tx; - -architecture stub of selectio_lvds_tx is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "data_out_from_device[3:0],data_out_to_pins[3:0],clk_in,clk_out,io_reset"; -begin -end; diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_utilization_synth.pb b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_utilization_synth.pb deleted file mode 100644 index 661a3ce6..00000000 Binary files a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_utilization_synth.pb and /dev/null differ diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_utilization_synth.rpt b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_utilization_synth.rpt deleted file mode 100644 index 93bff00e..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_utilization_synth.rpt +++ /dev/null @@ -1,176 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -| Date : Sun Mar 19 17:32:20 2023 -| Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -| Command : report_utilization -file selectio_lvds_tx_utilization_synth.rpt -pb selectio_lvds_tx_utilization_synth.pb -| Design : selectio_lvds_tx -| Device : 7k410tffg900-2 -| Design State : Synthesized ---------------------------------------------------------------------------------------------------------------------------- - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 0 | 0 | 254200 | 0.00 | -| LUT as Logic | 0 | 0 | 254200 | 0.00 | -| LUT as Memory | 0 | 0 | 90600 | 0.00 | -| Slice Registers | 4 | 4 | 508400 | <0.01 | -| Register as Flip Flop | 4 | 4 | 508400 | <0.01 | -| Register as Latch | 0 | 0 | 508400 | 0.00 | -| F7 Muxes | 0 | 0 | 127100 | 0.00 | -| F8 Muxes | 0 | 0 | 63550 | 0.00 | -+-------------------------+------+-------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 4 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Memory ---------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 795 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 795 | 0.00 | -| RAMB18 | 0 | 0 | 1590 | 0.00 | -+----------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -3. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 1540 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -4. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 5 | 0 | 500 | 1.00 | -| Bonded IPADs | 0 | 0 | 50 | 0.00 | -| Bonded OPADs | 0 | 0 | 32 | 0.00 | -| PHY_CONTROL | 0 | 0 | 10 | 0.00 | -| PHASER_REF | 0 | 0 | 10 | 0.00 | -| OUT_FIFO | 0 | 0 | 40 | 0.00 | -| IN_FIFO | 0 | 0 | 40 | 0.00 | -| IDELAYCTRL | 0 | 0 | 10 | 0.00 | -| IBUFDS | 0 | 0 | 480 | 0.00 | -| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | -| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 | -| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | -| ILOGIC | 0 | 0 | 500 | 0.00 | -| OLOGIC | 0 | 0 | 500 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -5. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 0 | 0 | 32 | 0.00 | -| BUFIO | 0 | 0 | 40 | 0.00 | -| MMCME2_ADV | 0 | 0 | 10 | 0.00 | -| PLLE2_ADV | 0 | 0 | 10 | 0.00 | -| BUFMRCE | 0 | 0 | 20 | 0.00 | -| BUFHCE | 0 | 0 | 168 | 0.00 | -| BUFR | 1 | 0 | 40 | 2.50 | -+------------+------+-------+-----------+-------+ - - -6. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -7. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| OBUF | 4 | IO | -| FDRE | 4 | Flop & Latch | -| IBUF | 1 | IO | -| BUFR | 1 | Clock | -+----------+------+---------------------+ - - -8. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -9. Instantiated Netlists ------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/vivado.pb b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/vivado.pb deleted file mode 100644 index 6c6a53e3..00000000 Binary files a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/vivado.pb and /dev/null differ diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.xpr b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.xpr index 2987bd60..3b8e1f92 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.xpr +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.xpr @@ -665,46 +665,6 @@