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update dl814_k7_cal_coarse with new ad9361 rx data mapping

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This commit is contained in:
josh
2023-04-06 14:10:30 +08:00
parent 2f77b0a7e8
commit 6acef7b40f
62 changed files with 23245 additions and 229 deletions
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projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/README.txt
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# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Tue Apr 04 18:48:27 CST 2023
# Generated by export_simulation on Thu Apr 06 13:35:10 CST 2023
#
################################################################################
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/rom_hop_data.sh
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# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Tue Apr 04 18:48:27 CST 2023
# Generated by Vivado on Thu Apr 06 13:35:10 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/ies/README.txt
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# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Tue Apr 04 18:48:27 CST 2023
# Generated by export_simulation on Thu Apr 06 13:35:10 CST 2023
#
################################################################################
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/ies/rom_hop_data.sh
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# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Tue Apr 04 18:48:27 CST 2023
# Generated by Vivado on Thu Apr 06 13:35:10 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/README.txt
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# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Tue Apr 04 18:48:27 CST 2023
# Generated by export_simulation on Thu Apr 06 13:35:10 CST 2023
#
################################################################################
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/rom_hop_data.sh
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# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Tue Apr 04 18:48:27 CST 2023
# Generated by Vivado on Thu Apr 06 13:35:10 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/questa/README.txt
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# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Tue Apr 04 18:48:27 CST 2023
# Generated by export_simulation on Thu Apr 06 13:35:10 CST 2023
#
################################################################################
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/questa/rom_hop_data.sh
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# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Tue Apr 04 18:48:27 CST 2023
# Generated by Vivado on Thu Apr 06 13:35:10 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/README.txt
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# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Tue Apr 04 18:48:27 CST 2023
# Generated by export_simulation on Thu Apr 06 13:35:10 CST 2023
#
################################################################################
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/rom_hop_data.sh
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# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Tue Apr 04 18:48:27 CST 2023
# Generated by Vivado on Thu Apr 06 13:35:10 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/vcs/README.txt
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# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Tue Apr 04 18:48:27 CST 2023
# Generated by export_simulation on Thu Apr 06 13:35:10 CST 2023
#
################################################################################
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/vcs/rom_hop_data.sh
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# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Tue Apr 04 18:48:27 CST 2023
# Generated by Vivado on Thu Apr 06 13:35:10 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/xcelium/README.txt
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# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Tue Apr 04 18:48:27 CST 2023
# Generated by export_simulation on Thu Apr 06 13:35:10 CST 2023
#
################################################################################
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/xcelium/rom_hop_data.sh
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# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Tue Apr 04 18:48:27 CST 2023
# Generated by Vivado on Thu Apr 06 13:35:10 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/xsim/README.txt
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# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Tue Apr 04 18:48:27 CST 2023
# Generated by export_simulation on Thu Apr 06 13:35:10 CST 2023
#
################################################################################
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/xsim/rom_hop_data.sh
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# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Tue Apr 04 18:48:27 CST 2023
# Generated by Vivado on Thu Apr 06 13:35:10 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/398372dcfcfb2e33/stats.txt
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NumberHits:1
Timestamp: Tue Apr 04 10:48:26 UTC 2023
NumberHits:5
Timestamp: Thu Apr 06 05:35:09 UTC 2023
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d742c4d8ffbde2e6/d742c4d8ffbde2e6.xci
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>ipcache</spirit:library>
<spirit:name>d742c4d8ffbde2e6</spirit:name>
<spirit:version>0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>rom_hop_data</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.4"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">../coe/one_hop_data.coe</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">rom_hop_data</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Single_Port_ROM</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">d742c4d8ffbde2e6</spirit:configurableElementValue>
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projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d742c4d8ffbde2e6/rom_hop_data.dcp
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projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d742c4d8ffbde2e6/rom_hop_data_sim_netlist.v
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projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d742c4d8ffbde2e6/rom_hop_data_sim_netlist.vhdl
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projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d742c4d8ffbde2e6/rom_hop_data_stub.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Thu Apr 6 13:27:11 2023
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_hop_data_stub.v
// Design : rom_hop_data
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, addra, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,addra[13:0],douta[95:0]" */;
input clka;
input [13:0]addra;
output [95:0]douta;
endmodule
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/d742c4d8ffbde2e6/rom_hop_data_stub.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Thu Apr 6 13:27:11 2023
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_hop_data_stub.vhdl
-- Design : rom_hop_data
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
douta : out STD_LOGIC_VECTOR ( 95 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,addra[13:0],douta[95:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
begin
end;
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf
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@@ -1,25 +1,25 @@
version:1
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projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf
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projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf
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projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml
+33 -30
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@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Wed Apr 5 12:53:16 2023">
<application name="pa" timeStamp="Thu Apr 6 13:32:35 2023">
<section name="Project Information" visible="false">
<property name="ProjectID" value="dd2c041edc1245f6938f6800e430db6c" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
@@ -19,39 +19,40 @@ This means code written to parse this file will need to be revisited each subseq
<item name="Java Command Handlers">
<property name="AddExistingIPHandler" value="3" type="JavaHandler"/>
<property name="CloseProject" value="4" type="JavaHandler"/>
<property name="CustomizeCore" value="2" type="JavaHandler"/>
<property name="EditDelete" value="6" type="JavaHandler"/>
<property name="ManageCompositeTargets" value="7" type="JavaHandler"/>
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<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
<property name="OpenIPLocationHandler" value="9" type="JavaHandler"/>
<property name="OpenIPLocationHandler" value="10" type="JavaHandler"/>
<property name="OpenPreviousIPHandler" value="11" type="JavaHandler"/>
<property name="OpenProject" value="2" type="JavaHandler"/>
<property name="RecustomizeCore" value="28" type="JavaHandler"/>
<property name="OpenProject" value="3" type="JavaHandler"/>
<property name="RecustomizeCore" value="33" type="JavaHandler"/>
<property name="ReportIPStatus" value="1" type="JavaHandler"/>
<property name="ShowView" value="5" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="BaseDialog_CANCEL" value="15" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="30" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="18" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="38" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="3" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="1" type="GuiHandlerData"/>
<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="2" type="GuiHandlerData"/>
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="7" type="GuiHandlerData"/>
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="15" type="GuiHandlerData"/>
<property name="ExpRunMenu_RESET_AND_GENERATE_OUTPUT_PRODUCTS" value="2" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="23" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="174" type="GuiHandlerData"/>
<property name="GettingStartedView_MANAGE_IP" value="11" type="GuiHandlerData"/>
<property name="GettingStartedView_OPEN_PROJECT" value="2" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="41" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="201" type="GuiHandlerData"/>
<property name="GettingStartedView_MANAGE_IP" value="12" type="GuiHandlerData"/>
<property name="GettingStartedView_OPEN_PROJECT" value="3" type="GuiHandlerData"/>
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
<property name="HACGCCoeFileWidget_BROWSE" value="6" type="GuiHandlerData"/>
<property name="HACGCCoeFileWidget_BROWSE" value="8" type="GuiHandlerData"/>
<property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_EDIT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_EXPORT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="12" type="GuiHandlerData"/>
<property name="MainMenuMgr_IP" value="7" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_EDIT" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_EXPORT" value="5" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="16" type="GuiHandlerData"/>
<property name="MainMenuMgr_IP" value="10" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="6" type="GuiHandlerData"/>
<property name="MainMenuMgr_REPORTS" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_TEXT_EDITOR" value="3" type="GuiHandlerData"/>
<property name="MainMenuMgr_TEXT_EDITOR" value="7" type="GuiHandlerData"/>
<property name="MainMenuMgr_TOOLS" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_WINDOW" value="14" type="GuiHandlerData"/>
<property name="MainWinMenuMgr_LAYOUT" value="4" type="GuiHandlerData"/>
@@ -62,26 +63,28 @@ This means code written to parse this file will need to be revisited each subseq
<property name="NewIPProjectWizard_IP_LOCATION" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_EXISTING_IP" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_PROJECT" value="4" type="GuiHandlerData"/>
<property name="PACommandNames_COPY_IP" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_CUSTOMIZE_CORE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_FILESET_WINDOW" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="4" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_IP_LOCATION" value="9" type="GuiHandlerData"/>
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="5" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_IP_LOCATION" value="10" type="GuiHandlerData"/>
<property name="PACommandNames_PROPERTIES_WINDOW" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_REPORT_IP_STATUS" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_RESET_COMPOSITE_FILE" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_RESET_COMPOSITE_FILE" value="4" type="GuiHandlerData"/>
<property name="ProgressDialog_BACKGROUND" value="5" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
<property name="RemoveSourcesDialog_ALSO_DELETE" value="9" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_CLOSE_DIALOG_UNSAVED_CHANGES_WILL" value="5" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="18" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="5" type="GuiHandlerData"/>
<property name="RemoveSourcesDialog_ALSO_DELETE" value="12" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_CLOSE_DIALOG_UNSAVED_CHANGES_WILL" value="6" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="24" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="6" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="5" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="11" type="GuiHandlerData"/>
<property name="XPG_CoeFileWidgdet_BROWSE" value="2" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="63" type="GuiMode"/>
<property name="GuiMode" value="73" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="45" type="TclMode"/>
<property name="TclMode" value="53" type="TclMode"/>
</item>
</section>
</application>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_15.xml
+8
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="rom_hop_data_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_16.xml
+8
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="rom_hop_data_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_17.xml
+8
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="rom_hop_data1_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data1_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ad9361_clk_gen_synth_1/gen_run.xml
+1 -1
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ad9361_clk_gen_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153566">
<File Type="PA-TCL" Name="ad9361_clk_gen.tcl"/>
<File Type="RDS-DCP" Name="ad9361_clk_gen.dcp"/>
<File Type="PA-TCL" Name="ad9361_clk_gen.tcl"/>
<File Type="REPORTS-TCL" Name="ad9361_clk_gen_reports.tcl"/>
<File Type="RDS-RDS" Name="ad9361_clk_gen.vds"/>
<File Type="RDS-UTIL" Name="ad9361_clk_gen_utilization_synth.rpt"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/add_s24_s32_s32_synth_1/gen_run.xml
+1 -1
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="add_s24_s32_s32_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
<File Type="PA-TCL" Name="add_s24_s32_s32.tcl"/>
<File Type="RDS-DCP" Name="add_s24_s32_s32.dcp"/>
<File Type="PA-TCL" Name="add_s24_s32_s32.tcl"/>
<File Type="REPORTS-TCL" Name="add_s24_s32_s32_reports.tcl"/>
<File Type="RDS-RDS" Name="add_s24_s32_s32.vds"/>
<File Type="RDS-UTIL" Name="add_s24_s32_s32_utilization_synth.rpt"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg1_synth_1/gen_run.xml
+1 -1
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ant_clk_gen_stg1_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
<File Type="PA-TCL" Name="ant_clk_gen_stg1.tcl"/>
<File Type="RDS-DCP" Name="ant_clk_gen_stg1.dcp"/>
<File Type="PA-TCL" Name="ant_clk_gen_stg1.tcl"/>
<File Type="REPORTS-TCL" Name="ant_clk_gen_stg1_reports.tcl"/>
<File Type="RDS-RDS" Name="ant_clk_gen_stg1.vds"/>
<File Type="RDS-UTIL" Name="ant_clk_gen_stg1_utilization_synth.rpt"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg2_synth_1/gen_run.xml
+1 -1
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ant_clk_gen_stg2_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
<File Type="PA-TCL" Name="ant_clk_gen_stg2.tcl"/>
<File Type="RDS-DCP" Name="ant_clk_gen_stg2.dcp"/>
<File Type="PA-TCL" Name="ant_clk_gen_stg2.tcl"/>
<File Type="REPORTS-TCL" Name="ant_clk_gen_stg2_reports.tcl"/>
<File Type="RDS-RDS" Name="ant_clk_gen_stg2.vds"/>
<File Type="RDS-UTIL" Name="ant_clk_gen_stg2_utilization_synth.rpt"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/gen_run.xml
+1 -1
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="atan2_16b_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
<File Type="PA-TCL" Name="atan2_16b.tcl"/>
<File Type="RDS-DCP" Name="atan2_16b.dcp"/>
<File Type="PA-TCL" Name="atan2_16b.tcl"/>
<File Type="REPORTS-TCL" Name="atan2_16b_reports.tcl"/>
<File Type="RDS-RDS" Name="atan2_16b.vds"/>
<File Type="RDS-UTIL" Name="atan2_16b_utilization_synth.rpt"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x12_synth_1/gen_run.xml
+1 -1
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="cmpy_12x12_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
<File Type="PA-TCL" Name="cmpy_12x12.tcl"/>
<File Type="RDS-DCP" Name="cmpy_12x12.dcp"/>
<File Type="PA-TCL" Name="cmpy_12x12.tcl"/>
<File Type="REPORTS-TCL" Name="cmpy_12x12_reports.tcl"/>
<File Type="RDS-RDS" Name="cmpy_12x12.vds"/>
<File Type="RDS-UTIL" Name="cmpy_12x12_utilization_synth.rpt"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/cmpy_16x12_synth_1/gen_run.xml
+1 -1
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="cmpy_16x12_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
<File Type="PA-TCL" Name="cmpy_16x12.tcl"/>
<File Type="RDS-DCP" Name="cmpy_16x12.dcp"/>
<File Type="PA-TCL" Name="cmpy_16x12.tcl"/>
<File Type="REPORTS-TCL" Name="cmpy_16x12_reports.tcl"/>
<File Type="RDS-RDS" Name="cmpy_16x12.vds"/>
<File Type="RDS-UTIL" Name="cmpy_16x12_utilization_synth.rpt"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/fifo_accor_cdc_synth_1/gen_run.xml
+1 -1
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="fifo_accor_cdc_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
<File Type="PA-TCL" Name="fifo_accor_cdc.tcl"/>
<File Type="RDS-DCP" Name="fifo_accor_cdc.dcp"/>
<File Type="PA-TCL" Name="fifo_accor_cdc.tcl"/>
<File Type="REPORTS-TCL" Name="fifo_accor_cdc_reports.tcl"/>
<File Type="RDS-RDS" Name="fifo_accor_cdc.vds"/>
<File Type="RDS-UTIL" Name="fifo_accor_cdc_utilization_synth.rpt"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/gen_run.xml
+1 -1
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="fifo_weight_cdc_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153568">
<File Type="PA-TCL" Name="fifo_weight_cdc.tcl"/>
<File Type="RDS-DCP" Name="fifo_weight_cdc.dcp"/>
<File Type="PA-TCL" Name="fifo_weight_cdc.tcl"/>
<File Type="REPORTS-TCL" Name="fifo_weight_cdc_reports.tcl"/>
<File Type="RDS-RDS" Name="fifo_weight_cdc.vds"/>
<File Type="RDS-UTIL" Name="fifo_weight_cdc_utilization_synth.rpt"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_AntCtrl_synth_1/gen_run.xml
+1 -1
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ila_AntCtrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679400492">
<File Type="PA-TCL" Name="ila_AntCtrl.tcl"/>
<File Type="RDS-DCP" Name="ila_AntCtrl.dcp"/>
<File Type="PA-TCL" Name="ila_AntCtrl.tcl"/>
<File Type="REPORTS-TCL" Name="ila_AntCtrl_reports.tcl"/>
<File Type="RDS-RDS" Name="ila_AntCtrl.vds"/>
<File Type="RDS-UTIL" Name="ila_AntCtrl_utilization_synth.rpt"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_cal_synth_1/gen_run.xml
+1 -1
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ila_cal_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1680090743">
<File Type="PA-TCL" Name="ila_cal.tcl"/>
<File Type="RDS-DCP" Name="ila_cal.dcp"/>
<File Type="PA-TCL" Name="ila_cal.tcl"/>
<File Type="REPORTS-TCL" Name="ila_cal_reports.tcl"/>
<File Type="RDS-RDS" Name="ila_cal.vds"/>
<File Type="RDS-UTIL-PB" Name="ila_cal_utilization_synth.pb"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_rfcontrl_synth_1/gen_run.xml
+1 -1
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ila_rfcontrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679400492">
<File Type="PA-TCL" Name="ila_rfcontrl.tcl"/>
<File Type="RDS-DCP" Name="ila_rfcontrl.dcp"/>
<File Type="PA-TCL" Name="ila_rfcontrl.tcl"/>
<File Type="REPORTS-TCL" Name="ila_rfcontrl_reports.tcl"/>
<File Type="RDS-RDS" Name="ila_rfcontrl.vds"/>
<File Type="RDS-UTIL" Name="ila_rfcontrl_utilization_synth.rpt"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_rx_pre_synth_1/gen_run.xml
+1 -1
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ila_rx_pre_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1680090770">
<File Type="PA-TCL" Name="ila_rx_pre.tcl"/>
<File Type="RDS-DCP" Name="ila_rx_pre.dcp"/>
<File Type="PA-TCL" Name="ila_rx_pre.tcl"/>
<File Type="REPORTS-TCL" Name="ila_rx_pre_reports.tcl"/>
<File Type="RDS-RDS" Name="ila_rx_pre.vds"/>
<File Type="RDS-UTIL-PB" Name="ila_rx_pre_utilization_synth.pb"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_rx_synth_1/gen_run.xml
+1 -1
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ila_rx_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1680090829">
<File Type="PA-TCL" Name="ila_rx.tcl"/>
<File Type="RDS-DCP" Name="ila_rx.dcp"/>
<File Type="PA-TCL" Name="ila_rx.tcl"/>
<File Type="REPORTS-TCL" Name="ila_rx_reports.tcl"/>
<File Type="RDS-RDS" Name="ila_rx.vds"/>
<File Type="RDS-UTIL-PB" Name="ila_rx_utilization_synth.pb"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_tx_synth_1/gen_run.xml
+1 -1
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ila_tx_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679400355">
<File Type="PA-TCL" Name="ila_tx.tcl"/>
<File Type="RDS-DCP" Name="ila_tx.dcp"/>
<File Type="PA-TCL" Name="ila_tx.tcl"/>
<File Type="REPORTS-TCL" Name="ila_tx_reports.tcl"/>
<File Type="RDS-RDS" Name="ila_tx.vds"/>
<File Type="RDS-UTIL" Name="ila_tx_utilization_synth.rpt"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ram_hop_data_synth_1/gen_run.xml
+1 -1
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ram_hop_data_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153570">
<File Type="PA-TCL" Name="ram_hop_data.tcl"/>
<File Type="RDS-DCP" Name="ram_hop_data.dcp"/>
<File Type="PA-TCL" Name="ram_hop_data.tcl"/>
<File Type="REPORTS-TCL" Name="ram_hop_data_reports.tcl"/>
<File Type="RDS-RDS" Name="ram_hop_data.vds"/>
<File Type="RDS-UTIL" Name="ram_hop_data_utilization_synth.rpt"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/gen_run.xml
+1 -1
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="rotate_16b_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153571">
<File Type="PA-TCL" Name="rotate_16b.tcl"/>
<File Type="RDS-DCP" Name="rotate_16b.dcp"/>
<File Type="PA-TCL" Name="rotate_16b.tcl"/>
<File Type="REPORTS-TCL" Name="rotate_16b_reports.tcl"/>
<File Type="RDS-RDS" Name="rotate_16b.vds"/>
<File Type="RDS-UTIL" Name="rotate_16b_utilization_synth.rpt"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_ant_rd_synth_1/gen_run.xml
+1 -1
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="vio_ant_rd_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153571">
<File Type="PA-TCL" Name="vio_ant_rd.tcl"/>
<File Type="RDS-DCP" Name="vio_ant_rd.dcp"/>
<File Type="PA-TCL" Name="vio_ant_rd.tcl"/>
<File Type="REPORTS-TCL" Name="vio_ant_rd_reports.tcl"/>
<File Type="RDS-RDS" Name="vio_ant_rd.vds"/>
<File Type="RDS-UTIL" Name="vio_ant_rd_utilization_synth.rpt"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_ant_test_synth_1/gen_run.xml
+1 -1
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="vio_ant_test_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153571">
<File Type="PA-TCL" Name="vio_ant_test.tcl"/>
<File Type="RDS-DCP" Name="vio_ant_test.dcp"/>
<File Type="PA-TCL" Name="vio_ant_test.tcl"/>
<File Type="REPORTS-TCL" Name="vio_ant_test_reports.tcl"/>
<File Type="RDS-RDS" Name="vio_ant_test.vds"/>
<File Type="RDS-UTIL" Name="vio_ant_test_utilization_synth.rpt"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_cal_synth_1/gen_run.xml
+1 -1
View File
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="vio_cal_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153571">
<File Type="PA-TCL" Name="vio_cal.tcl"/>
<File Type="RDS-DCP" Name="vio_cal.dcp"/>
<File Type="PA-TCL" Name="vio_cal.tcl"/>
<File Type="REPORTS-TCL" Name="vio_cal_reports.tcl"/>
<File Type="RDS-RDS" Name="vio_cal.vds"/>
<File Type="RDS-UTIL" Name="vio_cal_utilization_synth.rpt"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_clk_ld_rd_synth_1/gen_run.xml
+1 -1
View File
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="vio_clk_ld_rd_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153571">
<File Type="PA-TCL" Name="vio_clk_ld_rd.tcl"/>
<File Type="RDS-DCP" Name="vio_clk_ld_rd.dcp"/>
<File Type="PA-TCL" Name="vio_clk_ld_rd.tcl"/>
<File Type="REPORTS-TCL" Name="vio_clk_ld_rd_reports.tcl"/>
<File Type="RDS-RDS" Name="vio_clk_ld_rd.vds"/>
<File Type="RDS-UTIL" Name="vio_clk_ld_rd_utilization_synth.rpt"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml
+2 -2
View File
@@ -1,9 +1,9 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="vio_manual_ctrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1680526047">
<File Type="PA-TCL" Name="vio_manual_ctrl.tcl"/>
<File Type="REPORTS-TCL" Name="vio_manual_ctrl_reports.tcl"/>
<File Type="RDS-RDS" Name="vio_manual_ctrl.vds"/>
<File Type="PA-TCL" Name="vio_manual_ctrl.tcl"/>
<File Type="RDS-DCP" Name="vio_manual_ctrl.dcp"/>
<File Type="RDS-RDS" Name="vio_manual_ctrl.vds"/>
<File Type="RDS-UTIL-PB" Name="vio_manual_ctrl_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="vio_manual_ctrl_utilization_synth.rpt"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_manual_ctrl">
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_rf_rd_synth_1/gen_run.xml
+1 -1
View File
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="vio_rf_rd_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153571">
<File Type="PA-TCL" Name="vio_rf_rd.tcl"/>
<File Type="RDS-DCP" Name="vio_rf_rd.dcp"/>
<File Type="PA-TCL" Name="vio_rf_rd.tcl"/>
<File Type="REPORTS-TCL" Name="vio_rf_rd_reports.tcl"/>
<File Type="RDS-RDS" Name="vio_rf_rd.vds"/>
<File Type="RDS-UTIL" Name="vio_rf_rd_utilization_synth.rpt"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml
+1 -1
View File
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="vio_rfcontrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153571">
<File Type="PA-TCL" Name="vio_rfcontrl.tcl"/>
<File Type="RDS-DCP" Name="vio_rfcontrl.dcp"/>
<File Type="PA-TCL" Name="vio_rfcontrl.tcl"/>
<File Type="REPORTS-TCL" Name="vio_rfcontrl_reports.tcl"/>
<File Type="RDS-RDS" Name="vio_rfcontrl.vds"/>
<File Type="RDS-UTIL" Name="vio_rfcontrl_utilization_synth.rpt"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr
+7 -7
View File
@@ -39,13 +39,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="77"/>
<Option Name="WTModelSimExportSim" Val="77"/>
<Option Name="WTQuestaExportSim" Val="77"/>
<Option Name="WTIesExportSim" Val="77"/>
<Option Name="WTVcsExportSim" Val="77"/>
<Option Name="WTRivieraExportSim" Val="77"/>
<Option Name="WTActivehdlExportSim" Val="77"/>
<Option Name="WTXSimExportSim" Val="84"/>
<Option Name="WTModelSimExportSim" Val="84"/>
<Option Name="WTQuestaExportSim" Val="84"/>
<Option Name="WTIesExportSim" Val="84"/>
<Option Name="WTVcsExportSim" Val="84"/>
<Option Name="WTRivieraExportSim" Val="84"/>
<Option Name="WTActivehdlExportSim" Val="84"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data.xcix
BIN
View File
Binary file not shown.
projects/datalink_814/dl814_k7_cal_coarse/project.tcl
+13 -13
View File
@@ -3,7 +3,7 @@
#
# project.tcl: Tcl script for re-creating project 'project'
#
# Generated by Vivado on Mon Apr 03 21:10:02 CST 2023
# Generated by Vivado on Thu Apr 06 14:08:02 CST 2023
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -92,13 +92,13 @@
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/rtl/tx_qpsk.v"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/weight_vec_formatting.v"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/system_top.v"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_ant_rd/vio_ant_rd.xci"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/atan2_16b/atan2_16b.xci"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rotate_16b/rotate_16b.xci"
# "/home/josh/Workspace/vivado-git/common/ApproxModuli_26bit.v"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/ad9361_phase_cal_fine.v"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_cal/vio_cal.xci"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/coe/one_hop_data.coe"
@@ -213,16 +213,16 @@ set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_use
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "target_simulator" -value "VCS" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "48" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "48" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "48" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "49" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "49" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "49" -objects $obj
set_property -name "webtalk.modelsim_launch_sim" -value "2" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "48" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "48" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "48" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "49" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "49" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "49" -objects $obj
set_property -name "webtalk.vcs_launch_sim" -value "29" -objects $obj
set_property -name "webtalk.xcelium_export_sim" -value "1" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "48" -objects $obj
set_property -name "webtalk.xcelium_export_sim" -value "2" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "49" -objects $obj
set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
# Create 'sources_1' fileset (if not found)
@@ -305,13 +305,13 @@ set files [list \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/rtl/tx_qpsk.v"] \
[file normalize "${origin_dir}/rtl/rx_pre_process/weight_vec_formatting.v"] \
[file normalize "${origin_dir}/rtl/system_top.v"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"] \
[file normalize "${origin_dir}/ip/vio_ant_rd/vio_ant_rd.xci"] \
[file normalize "${origin_dir}/ip/rx_pre_process/atan2_16b/atan2_16b.xci"] \
[file normalize "${origin_dir}/ip/rx_pre_process/rotate_16b/rotate_16b.xci"] \
[file normalize "${origin_dir}/../../../common/ApproxModuli_26bit.v"] \
[file normalize "${origin_dir}/rtl/rx_pre_process/ad9361_phase_cal_fine.v"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"] \
[file normalize "${origin_dir}/ip/vio_cal/vio_cal.xci"] \
[file normalize "${origin_dir}/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci"] \
[file normalize "${origin_dir}/ip/rx_pre_process/coe/one_hop_data.coe"] \
projects/datalink_814/dl814_k7_cal_coarse/project/project.runs/impl_1/system_top.bit
BIN
View File
Binary file not shown.
projects/datalink_814/dl814_k7_cal_coarse/project/project.sdk/dl814_k7_48m/.cproject
+99 -99
View File
@@ -1,8 +1,8 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="xilinx.gnu.mb.exe.debug.1177098019">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.mb.exe.debug.1177098019" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<cconfiguration id="xilinx.gnu.mb.exe.debug.749264029">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.mb.exe.debug.749264029" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings/>
<extensions>
<extension id="com.xilinx.sdk.managedbuilder.XELF.mb" point="org.eclipse.cdt.core.BinaryParser"/>
@@ -14,79 +14,79 @@
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="xilinx.gnu.mb.exe.debug.1177098019" name="Debug" parent="xilinx.gnu.mb.exe.debug">
<folderInfo id="xilinx.gnu.mb.exe.debug.1177098019." name="/" resourcePath="">
<toolChain id="xilinx.gnu.mb.exe.debug.toolchain.1508512482" name="Xilinx MicroBlaze GNU Toolchain" superClass="xilinx.gnu.mb.exe.debug.toolchain">
<targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.mb" id="xilinx.mb.target.gnu.base.debug.2146764007" isAbstract="false" name="Debug Platform" superClass="xilinx.mb.target.gnu.base.debug"/>
<builder buildPath="${workspace_loc:/dl814_k7_48m}/Debug" enableAutoBuild="true" id="xilinx.gnu.mb.toolchain.builder.debug.1008300846" managedBuildOn="true" name="GNU make.Debug" superClass="xilinx.gnu.mb.toolchain.builder.debug"/>
<tool id="xilinx.gnu.mb.c.toolchain.assembler.debug.544553594" name="MicroBlaze gcc assembler" superClass="xilinx.gnu.mb.c.toolchain.assembler.debug">
<option id="xilinx.gnu.mb.assembler.usele.540339797" superClass="xilinx.gnu.mb.assembler.usele" value="true" valueType="boolean"/>
<inputType id="xilinx.gnu.assembler.input.1360461947" superClass="xilinx.gnu.assembler.input"/>
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="xilinx.gnu.mb.exe.debug.749264029" name="Debug" parent="xilinx.gnu.mb.exe.debug">
<folderInfo id="xilinx.gnu.mb.exe.debug.749264029." name="/" resourcePath="">
<toolChain id="xilinx.gnu.mb.exe.debug.toolchain.1927414654" name="Xilinx MicroBlaze GNU Toolchain" superClass="xilinx.gnu.mb.exe.debug.toolchain">
<targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.mb" id="xilinx.mb.target.gnu.base.debug.2036180087" isAbstract="false" name="Debug Platform" superClass="xilinx.mb.target.gnu.base.debug"/>
<builder buildPath="${workspace_loc:/dl814_k7_48m}/Debug" enableAutoBuild="true" id="xilinx.gnu.mb.toolchain.builder.debug.587899424" managedBuildOn="true" name="GNU make.Debug" superClass="xilinx.gnu.mb.toolchain.builder.debug"/>
<tool id="xilinx.gnu.mb.c.toolchain.assembler.debug.723774151" name="MicroBlaze gcc assembler" superClass="xilinx.gnu.mb.c.toolchain.assembler.debug">
<option id="xilinx.gnu.mb.assembler.usele.769879884" superClass="xilinx.gnu.mb.assembler.usele" value="true" valueType="boolean"/>
<inputType id="xilinx.gnu.assembler.input.763158800" superClass="xilinx.gnu.assembler.input"/>
</tool>
<tool id="xilinx.gnu.mb.c.toolchain.compiler.debug.1714875505" name="MicroBlaze gcc compiler" superClass="xilinx.gnu.mb.c.toolchain.compiler.debug">
<option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.299766399" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.option.debugging.level.458674064" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
<option id="xilinx.gnu.mb.compiler.inferred.mbversion.2116144167" superClass="xilinx.gnu.mb.compiler.inferred.mbversion" value="11.0" valueType="string"/>
<option id="xilinx.gnu.mb.compiler.inferred.norelax.1182449189" superClass="xilinx.gnu.mb.compiler.inferred.norelax" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.garbage.1847149907" superClass="xilinx.gnu.mb.compiler.inferred.garbage" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.usele.258752273" superClass="xilinx.gnu.mb.compiler.inferred.usele" value="true" valueType="boolean"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.2094554542" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<tool id="xilinx.gnu.mb.c.toolchain.compiler.debug.441183682" name="MicroBlaze gcc compiler" superClass="xilinx.gnu.mb.c.toolchain.compiler.debug">
<option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.1150349940" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.option.debugging.level.1908855128" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
<option id="xilinx.gnu.mb.compiler.inferred.mbversion.532630896" superClass="xilinx.gnu.mb.compiler.inferred.mbversion" value="11.0" valueType="string"/>
<option id="xilinx.gnu.mb.compiler.inferred.norelax.946745523" superClass="xilinx.gnu.mb.compiler.inferred.norelax" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.garbage.523889752" superClass="xilinx.gnu.mb.compiler.inferred.garbage" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.usele.2126457831" superClass="xilinx.gnu.mb.compiler.inferred.usele" value="true" valueType="boolean"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.2066693939" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="../../dl814_k7_48m_bsp/microblaze_ps/include"/>
</option>
<inputType id="xilinx.gnu.compiler.input.60809803" name="C source files" superClass="xilinx.gnu.compiler.input"/>
<inputType id="xilinx.gnu.compiler.input.2122795276" name="C source files" superClass="xilinx.gnu.compiler.input"/>
</tool>
<tool id="xilinx.gnu.mb.cxx.toolchain.compiler.debug.1431967699" name="MicroBlaze g++ compiler" superClass="xilinx.gnu.mb.cxx.toolchain.compiler.debug">
<option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.1553664351" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.option.debugging.level.293737649" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
<option id="xilinx.gnu.mb.compiler.inferred.mbversion.1368543763" superClass="xilinx.gnu.mb.compiler.inferred.mbversion" value="11.0" valueType="string"/>
<option id="xilinx.gnu.mb.compiler.inferred.norelax.1519341464" superClass="xilinx.gnu.mb.compiler.inferred.norelax" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.garbage.1028248431" superClass="xilinx.gnu.mb.compiler.inferred.garbage" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.usele.1931461095" superClass="xilinx.gnu.mb.compiler.inferred.usele" value="true" valueType="boolean"/>
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<tool id="xilinx.gnu.mb.cxx.toolchain.compiler.debug.696530299" name="MicroBlaze g++ compiler" superClass="xilinx.gnu.mb.cxx.toolchain.compiler.debug">
<option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.1913881042" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.option.debugging.level.821099639" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
<option id="xilinx.gnu.mb.compiler.inferred.mbversion.1358919286" superClass="xilinx.gnu.mb.compiler.inferred.mbversion" value="11.0" valueType="string"/>
<option id="xilinx.gnu.mb.compiler.inferred.norelax.709372540" superClass="xilinx.gnu.mb.compiler.inferred.norelax" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.garbage.1025214269" superClass="xilinx.gnu.mb.compiler.inferred.garbage" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.usele.1244772267" superClass="xilinx.gnu.mb.compiler.inferred.usele" value="true" valueType="boolean"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.1140348216" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="../../dl814_k7_48m_bsp/microblaze_ps/include"/>
</option>
</tool>
<tool id="xilinx.gnu.mb.toolchain.archiver.842883263" name="MicroBlaze archiver" superClass="xilinx.gnu.mb.toolchain.archiver"/>
<tool id="xilinx.gnu.mb.c.toolchain.linker.debug.1770594353" name="MicroBlaze gcc linker" superClass="xilinx.gnu.mb.c.toolchain.linker.debug">
<option id="xilinx.gnu.mb.linker.inferred.mbversion.1192001189" superClass="xilinx.gnu.mb.linker.inferred.mbversion" value="11.0" valueType="string"/>
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projects/datalink_814/dl814_k7_cal_coarse/project/project.sdk/dl814_k7_48m_bsp/.cproject
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projects/datalink_814/dl814_k7_cal_coarse/project/project.sdk/system_top.hdf
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