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update dl814_k7_cal_coarse with new ad9361 rx data mapping

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josh
2023-04-06 14:10:30 +08:00
parent 2f77b0a7e8
commit 6acef7b40f
62 changed files with 23245 additions and 229 deletions
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projects/datalink_814/dl814_k7_cal_coarse/project.tcl
+13 -13
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@@ -3,7 +3,7 @@
#
# project.tcl: Tcl script for re-creating project 'project'
#
# Generated by Vivado on Mon Apr 03 21:10:02 CST 2023
# Generated by Vivado on Thu Apr 06 14:08:02 CST 2023
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -92,13 +92,13 @@
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/rtl/tx_qpsk.v"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/weight_vec_formatting.v"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/system_top.v"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_ant_rd/vio_ant_rd.xci"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/atan2_16b/atan2_16b.xci"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rotate_16b/rotate_16b.xci"
# "/home/josh/Workspace/vivado-git/common/ApproxModuli_26bit.v"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/ad9361_phase_cal_fine.v"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_cal/vio_cal.xci"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/coe/one_hop_data.coe"
@@ -213,16 +213,16 @@ set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_use
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "target_simulator" -value "VCS" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "48" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "48" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "48" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "49" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "49" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "49" -objects $obj
set_property -name "webtalk.modelsim_launch_sim" -value "2" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "48" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "48" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "48" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "49" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "49" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "49" -objects $obj
set_property -name "webtalk.vcs_launch_sim" -value "29" -objects $obj
set_property -name "webtalk.xcelium_export_sim" -value "1" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "48" -objects $obj
set_property -name "webtalk.xcelium_export_sim" -value "2" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "49" -objects $obj
set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
# Create 'sources_1' fileset (if not found)
@@ -305,13 +305,13 @@ set files [list \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/rtl/tx_qpsk.v"] \
[file normalize "${origin_dir}/rtl/rx_pre_process/weight_vec_formatting.v"] \
[file normalize "${origin_dir}/rtl/system_top.v"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"] \
[file normalize "${origin_dir}/ip/vio_ant_rd/vio_ant_rd.xci"] \
[file normalize "${origin_dir}/ip/rx_pre_process/atan2_16b/atan2_16b.xci"] \
[file normalize "${origin_dir}/ip/rx_pre_process/rotate_16b/rotate_16b.xci"] \
[file normalize "${origin_dir}/../../../common/ApproxModuli_26bit.v"] \
[file normalize "${origin_dir}/rtl/rx_pre_process/ad9361_phase_cal_fine.v"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"] \
[file normalize "${origin_dir}/ip/vio_cal/vio_cal.xci"] \
[file normalize "${origin_dir}/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci"] \
[file normalize "${origin_dir}/ip/rx_pre_process/coe/one_hop_data.coe"] \