diff --git a/projects/datalink_814/dl814_k7_cal_coarse/constraints/k7410t_ad9516_2ad9361_timing.xdc b/projects/datalink_814/dl814_k7_cal_coarse/constraints/k7410t_ad9516_2ad9361_timing.xdc index e5e036e6..cd739c97 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/constraints/k7410t_ad9516_2ad9361_timing.xdc +++ b/projects/datalink_814/dl814_k7_cal_coarse/constraints/k7410t_ad9516_2ad9361_timing.xdc @@ -1,4 +1,4 @@ -set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[8]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_recal_d1_reg/D] -set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[10]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_1_cal_start_d1_reg/D] +set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[8]/C}] -to [get_pins u_ad9361_phase_cal/ad9361_recal_d1_reg/D] +set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[10]/C}] -to [get_pins u_ad9361_phase_cal/ad9361_1_cal_start_d1_reg/D] set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[7]/C}] -to [get_pins u_tx_pre_process/ad9361_tx_switch_d1_reg/D] -set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[9]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_2_cal_start_d1_reg/D] \ No newline at end of file +set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[9]/C}] -to [get_pins u_ad9361_phase_cal/ad9361_2_cal_start_d1_reg/D] \ No newline at end of file diff --git a/projects/datalink_814/dl814_k7_cal_coarse/project/dl814_k7_cal_coarse.tcl b/projects/datalink_814/dl814_k7_cal_coarse/project/dl814_k7.tcl similarity index 90% rename from projects/datalink_814/dl814_k7_cal_coarse/project/dl814_k7_cal_coarse.tcl rename to projects/datalink_814/dl814_k7_cal_coarse/project/dl814_k7.tcl index e8e646e9..0a735651 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/project/dl814_k7_cal_coarse.tcl +++ b/projects/datalink_814/dl814_k7_cal_coarse/project/dl814_k7.tcl @@ -1,9 +1,9 @@ #***************************************************************************************** # Vivado (TM) v2019.1.3 (64-bit) # -# dl814_k7_cal_coarse.tcl: Tcl script for re-creating project 'dl814_k7_cal_coarse' +# dl814_k7.tcl: Tcl script for re-creating project 'dl814_k7' # -# Generated by Vivado on Tue Mar 21 20:47:28 +0800 2023 +# Generated by Vivado on Tue Mar 21 22:40:24 +0800 2023 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -18,7 +18,7 @@ # NOTE: In order to use this script for source control purposes, please make sure that the # following files are added to the source control system:- # -# 1. This project restoration tcl script (dl814_k7_cal_coarse.tcl) that was generated. +# 1. This project restoration tcl script (dl814_k7.tcl) that was generated. # # 2. The following source(s) files that were local or imported into the original project. # (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) @@ -27,91 +27,91 @@ # # 3. The following remote source files that were added to the original project:- # -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_manual_ctrl/vio_manual_ctrl.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_rx/ila_rx.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_tx/ila_tx.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_ant_rd/vio_ant_rd.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_rf_rd/vio_rf_rd.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_AntCtrl/ila_AntCtrl.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_rfcontrl/ila_rfcontrl.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_ant_test/vio_ant_test.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_rfcontrl/vio_rfcontrl.xci" -# "d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci" -# "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci" -# "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci" -# "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci" -# "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/GaussFir_12m/GaussFir_12m.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/data_1p5m/data_1p5m.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/GaussFir_1mp5/GaussFir_1mp5.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ant_rf_interface/fifo_AntCtrl/fifo_AntCtrl.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ipi-bds/system_bd/system_bd.bd" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ant_clk_gen_stg2/ant_clk_gen_stg2.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ant_clk_gen_stg1/ant_clk_gen_stg1.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ad9361_clk_gen/ad9361_clk_gen.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/ADF4351_2.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/transmitter/AddrtoWaveform.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/FRAC1.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/transmitter/GMSK_send.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/INT_ROMb.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_1.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_2.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_3.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_4.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/Sisyif.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/T_CAL.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/ad9361_phase_cal_coarse.v" -# "d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v" -# "d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_dual.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/adf4371_a.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/adf4371_b.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/ant_rf_ctrl.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/band_rom_a.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/band_rom_b.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/clk_dist.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/ds18b20_temp.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/frac2_rom.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/fre_caliatt.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/mgc_ctrl.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/mod2_rom.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/spi_master.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/spi_salve.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/spi_tx.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ipi-bds/system_bd/hdl/system_bd_wrapper.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/transmitter/tx_control.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/tx_pre_process.v" -# "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/rtl/tx_qpsk.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/system_top.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_cal/vio_cal.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_rx_pre/ila_rx_pre.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_cal/ila_cal.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/ram_hop_data/ram_hop_data.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/atan2_16b/atan2_16b.xci" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rotate_16b/rotate_16b.xci" -# "d:/vivado-git/common/ApproxModuli_26bit.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/accor_mat_formatting.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/accum_cmplx_mat.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/acorr_cmplx_col_vec.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/ad9361_phase_cal_fine.v" -# "d:/vivado-git/common/adder_tree_ppl.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_process.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/spatial_filter.v" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/weight_vec_formatting.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_manual_ctrl/vio_manual_ctrl.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_rx/ila_rx.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_tx/ila_tx.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_ant_rd/vio_ant_rd.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_rf_rd/vio_rf_rd.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_AntCtrl/ila_AntCtrl.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_rfcontrl/ila_rfcontrl.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_ant_test/vio_ant_test.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_rfcontrl/vio_rfcontrl.xci" +# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci" +# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci" +# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci" +# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci" +# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/GaussFir_12m/GaussFir_12m.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/data_1p5m/data_1p5m.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/GaussFir_1mp5/GaussFir_1mp5.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ant_rf_interface/fifo_AntCtrl/fifo_AntCtrl.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ipi-bds/system_bd/system_bd.bd" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ant_clk_gen_stg2/ant_clk_gen_stg2.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ant_clk_gen_stg1/ant_clk_gen_stg1.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ad9361_clk_gen/ad9361_clk_gen.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/ADF4351_2.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/transmitter/AddrtoWaveform.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/FRAC1.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/transmitter/GMSK_send.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/INT_ROMb.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_1.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_2.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_3.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_4.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/Sisyif.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/T_CAL.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/ad9361_phase_cal_coarse.v" +# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v" +# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_dual.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/adf4371_a.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/adf4371_b.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/ant_rf_ctrl.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/band_rom_a.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/band_rom_b.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/clk_dist.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/ds18b20_temp.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/frac2_rom.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/fre_caliatt.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/mgc_ctrl.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/mod2_rom.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/spi_master.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/spi_salve.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/spi_tx.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ipi-bds/system_bd/hdl/system_bd_wrapper.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/transmitter/tx_control.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/tx_pre_process.v" +# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/rtl/tx_qpsk.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/system_top.v" # "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe" # "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe" # "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/coe/cos_8192_18bit.coe" # "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/coe/GaussFir_12m.coe" # "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/coe/data_1m5.coe" # "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/coe/Gaussfir_1p5m.coe" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/constraints/k7401t_ad9516_2ad9361_physical.xdc" -# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/constraints/k7410t_ad9516_2ad9361_timing.xdc" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_cal/vio_cal.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_rx_pre/ila_rx_pre.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_cal/ila_cal.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/ram_hop_data/ram_hop_data.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/atan2_16b/atan2_16b.xci" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rotate_16b/rotate_16b.xci" +# "D:/vivado-git/common/ApproxModuli_26bit.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/accor_mat_formatting.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/accum_cmplx_mat.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/acorr_cmplx_col_vec.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/ad9361_phase_cal_fine.v" +# "D:/vivado-git/common/adder_tree_ppl.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_process.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/spatial_filter.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/weight_vec_formatting.v" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/constraints/k7401t_ad9516_2ad9361_physical.xdc" +# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/constraints/k7410t_ad9516_2ad9361_timing.xdc" # #***************************************************************************************** @@ -124,7 +124,7 @@ if { [info exists ::origin_dir_loc] } { } # Set the project name -set _xil_proj_name_ "dl814_k7_cal_coarse" +set _xil_proj_name_ "dl814_k7" # Use project name variable, if specified in the tcl shell if { [info exists ::user_project_name] } { @@ -132,7 +132,7 @@ if { [info exists ::user_project_name] } { } variable script_file -set script_file "dl814_k7_cal_coarse.tcl" +set script_file "dl814_k7.tcl" # Help information for this script proc print_help {} { @@ -180,7 +180,7 @@ if { $::argc > 0 } { } # Set the directory path for the original project from where this script was exported -set orig_proj_dir "[file normalize "$origin_dir/dl814_k7_cal_coarse"]" +set orig_proj_dir "[file normalize "$origin_dir/dl814_k7"]" # Create project create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7k410tffg900-2 @@ -296,6 +296,12 @@ set files [list \ [file normalize "${origin_dir}/../rtl/tx_pre_process.v"] \ [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/tx_qpsk/rtl/tx_qpsk.v"] \ [file normalize "${origin_dir}/../rtl/system_top.v"] \ + [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"] \ + [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"] \ + [file normalize "${origin_dir}/../ip/transmitter/coe/cos_8192_18bit.coe"] \ + [file normalize "${origin_dir}/../ip/transmitter/coe/GaussFir_12m.coe"] \ + [file normalize "${origin_dir}/../ip/transmitter/coe/data_1m5.coe"] \ + [file normalize "${origin_dir}/../ip/transmitter/coe/Gaussfir_1p5m.coe"] \ [file normalize "${origin_dir}/../ip/vio_cal/vio_cal.xci"] \ [file normalize "${origin_dir}/../ip/ila_rx_pre/ila_rx_pre.xci"] \ [file normalize "${origin_dir}/../ip/ila_cal/ila_cal.xci"] \ @@ -317,12 +323,6 @@ set files [list \ [file normalize "${origin_dir}/../rtl/rx_pre_process/rx_pre_process.v"] \ [file normalize "${origin_dir}/../rtl/rx_pre_process/spatial_filter.v"] \ [file normalize "${origin_dir}/../rtl/rx_pre_process/weight_vec_formatting.v"] \ - [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"] \ - [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"] \ - [file normalize "${origin_dir}/../ip/transmitter/coe/cos_8192_18bit.coe"] \ - [file normalize "${origin_dir}/../ip/transmitter/coe/GaussFir_12m.coe"] \ - [file normalize "${origin_dir}/../ip/transmitter/coe/data_1m5.coe"] \ - [file normalize "${origin_dir}/../ip/transmitter/coe/Gaussfir_1p5m.coe"] \ ] add_files -norecurse -fileset $obj $files diff --git a/projects/datalink_814/dl814_k7_cal_coarse/project/dl814_k7_cal_coarse/dl814_k7_cal_coarse.hw/dl814_k7_cal_coarse.lpr b/projects/datalink_814/dl814_k7_cal_coarse/project/dl814_k7/dl814_k7.hw/dl814_k7.lpr similarity index 100% rename from projects/datalink_814/dl814_k7_cal_coarse/project/dl814_k7_cal_coarse/dl814_k7_cal_coarse.hw/dl814_k7_cal_coarse.lpr rename to projects/datalink_814/dl814_k7_cal_coarse/project/dl814_k7/dl814_k7.hw/dl814_k7.lpr diff --git a/projects/datalink_814/dl814_k7_cal_coarse/project/dl814_k7/dl814_k7.runs/impl_1/debug_nets.ltx b/projects/datalink_814/dl814_k7_cal_coarse/project/dl814_k7/dl814_k7.runs/impl_1/debug_nets.ltx new file mode 100644 index 00000000..94c0890b --- /dev/null +++ b/projects/datalink_814/dl814_k7_cal_coarse/project/dl814_k7/dl814_k7.runs/impl_1/debug_nets.ltx @@ -0,0 +1,5455 @@ +{ + "ltx_root": { + "version": 4, + "minor": 0, + "ltx_data": [ + { + "name": "EDA_PROBESET", + "active": true, + "debug_cores": [ + { + "type": "XSDB_V3", + "name": "dbg_hub", + "spec": "labtools_xsdbm_v3", + "clk_input_freq_hz": "48000000" + }, + { + "type": "ILA_V3", + "name": "u_ila_AntCtrl", + "spec": "labtools_ila_v6", + "ipName": "ila", + "core_location": { + "user_chain": 1, + "slave_index": 0, + "bscan_switch_index": 0 + }, + "uuid": "4E206E6C660B571C9832C9CE4B8660D8", + "pins": [ + { + "name": "probe0", + "id": 0, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": false, + "leftIndex": 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