josh/vivado-202304
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modify project dir structure

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all three modules are modified, dl814_k7 projects are modified, .gitignore is modified, README needs to update
This commit is contained in:
josh
2023-03-26 01:19:11 +08:00
parent ade867ab22
commit 7a555fab92
5170 changed files with 9751239 additions and 2389576 deletions
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modules/xc7k410tffg900-2/ad9361_mapping/project/ad9361_mapping.tcl → modules/xc7k410tffg900-2/ad9361_mapping/project.tcl
+34 -34
View File
@@ -1,9 +1,9 @@
#*****************************************************************************************
# Vivado (TM) v2019.1.3 (64-bit)
#
# ad9361_mapping.tcl: Tcl script for re-creating project 'ad9361_mapping'
# project.tcl: Tcl script for re-creating project 'ad9361_mapping'
#
# Generated by Vivado on Tue Mar 21 13:01:16 +0800 2023
# Generated by Vivado on Sat Mar 25 23:40:00 CST 2023
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -18,7 +18,7 @@
# NOTE: In order to use this script for source control purposes, please make sure that the
# following files are added to the source control system:-
#
# 1. This project restoration tcl script (ad9361_mapping.tcl) that was generated.
# 1. This project restoration tcl script (project.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
@@ -27,19 +27,19 @@
#
# 3. The following remote source files that were added to the original project:-
#
# "d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"
# "d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v"
# "d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_single.v"
# "d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_lvds_dual.v"
# "d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_dual.v"
# "d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_single.v"
# "d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_lvds_dual.v"
# "d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/testbenches/tb_ad9361_rx_map_cmos_dual.v"
# "d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/testbenches/tb_ad9361_tx_map_cmos_dual.v"
# "d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/testbenches/tb_ad9361_tx_map_lvds_dual.v"
# "d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/testbenches/tb_ad9361_rx_map_lvds_dual.v"
# "d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/testbenches/tb_ad9361_tx_map_cmos_single.v"
# "d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/testbenches/tb_ad9361_rx_map_cmos_single.v"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_single.v"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_lvds_dual.v"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_dual.v"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_single.v"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_lvds_dual.v"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/testbenches/tb_ad9361_rx_map_cmos_dual.v"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/testbenches/tb_ad9361_tx_map_cmos_dual.v"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/testbenches/tb_ad9361_tx_map_lvds_dual.v"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/testbenches/tb_ad9361_rx_map_lvds_dual.v"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/testbenches/tb_ad9361_tx_map_cmos_single.v"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/testbenches/tb_ad9361_rx_map_cmos_single.v"
#
#*****************************************************************************************
@@ -52,7 +52,7 @@ if { [info exists ::origin_dir_loc] } {
}
# Set the project name
set _xil_proj_name_ "ad9361_mapping"
set _xil_proj_name_ "project"
# Use project name variable, if specified in the tcl shell
if { [info exists ::user_project_name] } {
@@ -60,7 +60,7 @@ if { [info exists ::user_project_name] } {
}
variable script_file
set script_file "ad9361_mapping.tcl"
set script_file "project.tcl"
# Help information for this script
proc print_help {} {
@@ -108,7 +108,7 @@ if { $::argc > 0 } {
}
# Set the directory path for the original project from where this script was exported
set orig_proj_dir "[file normalize "$origin_dir/ad9361_mapping"]"
set orig_proj_dir "[file normalize "$origin_dir/project/ad9361_mapping"]"
# Create project
create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7k410tffg900-2
@@ -118,7 +118,7 @@ set proj_dir [get_property directory [current_project]]
# Set project properties
set obj [current_project]
set_property -name "compxlib.modelsim_compiled_library_dir" -value "C:/Mentor/CompLib/2019.1.3" -objects $obj
set_property -name "compxlib.modelsim_compiled_library_dir" -value "/home/josh/Mentor/CompLib/2019.1.3" -objects $obj
set_property -name "corecontainer.enable" -value "1" -objects $obj
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj
@@ -161,18 +161,18 @@ if {[string equal [get_filesets -quiet sources_1] ""]} {
# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
[file normalize "${origin_dir}/../ip/ad9361_fifo/ad9361_fifo.xci"] \
[file normalize "${origin_dir}/../rtl/ad9361_rx_map_cmos_dual.v"] \
[file normalize "${origin_dir}/../rtl/ad9361_rx_map_cmos_single.v"] \
[file normalize "${origin_dir}/../rtl/ad9361_rx_map_lvds_dual.v"] \
[file normalize "${origin_dir}/../rtl/ad9361_tx_map_cmos_dual.v"] \
[file normalize "${origin_dir}/../rtl/ad9361_tx_map_cmos_single.v"] \
[file normalize "${origin_dir}/../rtl/ad9361_tx_map_lvds_dual.v"] \
[file normalize "${origin_dir}/ip/ad9361_fifo/ad9361_fifo.xci"] \
[file normalize "${origin_dir}/rtl/ad9361_rx_map_cmos_dual.v"] \
[file normalize "${origin_dir}/rtl/ad9361_rx_map_cmos_single.v"] \
[file normalize "${origin_dir}/rtl/ad9361_rx_map_lvds_dual.v"] \
[file normalize "${origin_dir}/rtl/ad9361_tx_map_cmos_dual.v"] \
[file normalize "${origin_dir}/rtl/ad9361_tx_map_cmos_single.v"] \
[file normalize "${origin_dir}/rtl/ad9361_tx_map_lvds_dual.v"] \
]
add_files -norecurse -fileset $obj $files
# Set 'sources_1' fileset file properties for remote files
set file "$origin_dir/../ip/ad9361_fifo/ad9361_fifo.xci"
set file "$origin_dir/ip/ad9361_fifo/ad9361_fifo.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
@@ -212,12 +212,12 @@ if {[string equal [get_filesets -quiet sim_1] ""]} {
# Set 'sim_1' fileset object
set obj [get_filesets sim_1]
set files [list \
[file normalize "${origin_dir}/../testbenches/tb_ad9361_rx_map_cmos_dual.v"] \
[file normalize "${origin_dir}/../testbenches/tb_ad9361_tx_map_cmos_dual.v"] \
[file normalize "${origin_dir}/../testbenches/tb_ad9361_tx_map_lvds_dual.v"] \
[file normalize "${origin_dir}/../testbenches/tb_ad9361_rx_map_lvds_dual.v"] \
[file normalize "${origin_dir}/../testbenches/tb_ad9361_tx_map_cmos_single.v"] \
[file normalize "${origin_dir}/../testbenches/tb_ad9361_rx_map_cmos_single.v"] \
[file normalize "${origin_dir}/testbenches/tb_ad9361_rx_map_cmos_dual.v"] \
[file normalize "${origin_dir}/testbenches/tb_ad9361_tx_map_cmos_dual.v"] \
[file normalize "${origin_dir}/testbenches/tb_ad9361_tx_map_lvds_dual.v"] \
[file normalize "${origin_dir}/testbenches/tb_ad9361_rx_map_lvds_dual.v"] \
[file normalize "${origin_dir}/testbenches/tb_ad9361_tx_map_cmos_single.v"] \
[file normalize "${origin_dir}/testbenches/tb_ad9361_rx_map_cmos_single.v"] \
]
add_files -norecurse -fileset $obj $files