modify project dir structure

all three modules are modified, dl814_k7 projects are modified, .gitignore is modified, README needs to update

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/cmpy_18x8/cmpy_18x8_stub.v

@@ -1,10 +1,10 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
-// Date        : Sat Mar 18 23:15:41 2023
-// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
-// Command     : write_verilog -force -mode synth_stub
-//               D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.v
+// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+// Date        : Sat Mar 25 22:38:34 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+// Command     : write_verilog -force -mode synth_stub -rename_top cmpy_18x8 -prefix
+//               cmpy_18x8_ cmpy_18x8_stub.v
 // Design      : cmpy_18x8
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7k410tffg900-2

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/cmpy_18x8/cmpy_18x8_stub.vhdl

@@ -1,10 +1,10 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
--- Date        : Sat Mar 18 23:15:41 2023
--- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
--- Command     : write_vhdl -force -mode synth_stub
---               D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.vhdl
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Sat Mar 25 22:38:34 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+-- Command     : write_vhdl -force -mode synth_stub -rename_top cmpy_18x8 -prefix
+--               cmpy_18x8_ cmpy_18x8_stub.vhdl
 -- Design      : cmpy_18x8
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7k410tffg900-2

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/cmpy_18x8/sim/cmpy_18x8.vhd

@@ -153,8 +153,8 @@ BEGIN
       C_A_WIDTH => 18,
       C_B_WIDTH => 8,
       C_OUT_WIDTH => 27,
-      C_LATENCY => 6,
-      C_MULT_TYPE => 1,
+      C_LATENCY => 4,
+      C_MULT_TYPE => 0,
       C_OPTIMIZE_GOAL => 0,
       HAS_NEGATE => 0,
       SINGLE_OUTPUT => 0,

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/dds_32b_8b/dds_32b_8b_stub.v

@@ -1,10 +1,10 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
-// Date        : Sat Mar 18 23:15:37 2023
-// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+// Date        : Sat Mar 25 22:38:34 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 // Command     : write_verilog -force -mode synth_stub
-//               D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.v
+//               /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk_new/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.v
 // Design      : dds_32b_8b
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7k410tffg900-2

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/dds_32b_8b/dds_32b_8b_stub.vhdl

@@ -1,10 +1,10 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
--- Date        : Sat Mar 18 23:15:37 2023
--- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Sat Mar 25 22:38:34 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 -- Command     : write_vhdl -force -mode synth_stub
---               D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.vhdl
+--               /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk_new/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.vhdl
 -- Design      : dds_32b_8b
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7k410tffg900-2

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/dds_32b_8b/demo_tb/tb_dds_32b_8b.vhd

@@ -165,23 +165,23 @@ begin
     -- The phase increment value here is derived from the output frequency value set in the CORE Generator GUI.
     s_axis_config_tvalid <= '1';
     s_axis_config_tdata <= (others => '0');  -- set unused TDATA bits to zero
-    s_axis_config_tdata(31 downto 0) <= "00000000000000000000000000000000";  -- phase increment
+    s_axis_config_tdata(31 downto 0) <= "00000000000000001101000110110111";  -- phase increment
     wait for CLOCK_PERIOD;
     s_axis_config_tvalid <= '0';
 
     -- Run for long enough to produce 5 periods of outputs
-    wait for CLOCK_PERIOD * 5;
+    wait for CLOCK_PERIOD * 400001;
 
     -- Configure the core with a different configuration:
     --   set phase increment to half of its current value
     s_axis_config_tvalid <= '1';
     s_axis_config_tdata <= (others => '0');  -- set unused TDATA bits to zero
-    s_axis_config_tdata(31 downto 0) <= "00000000000000000000000000000000";  -- current phase increment / 2
+    s_axis_config_tdata(31 downto 0) <= "00000000000000000110100011011011";  -- current phase increment / 2
     wait for CLOCK_PERIOD;
     s_axis_config_tvalid <= '0';
 
     -- Run for long enough to produce 5 periods of outputs
-    wait for CLOCK_PERIOD * 10;
+    wait for CLOCK_PERIOD * 800002;
 
     -- End of test
     end_of_simulation <= true;           

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/dds_32b_8b/sim/dds_32b_8b.vhd

@@ -183,7 +183,7 @@ BEGIN
       C_OUTPUT_WIDTH => 8,
       C_PHASE_ANGLE_WIDTH => 8,
       C_PHASE_INCREMENT => 1,
-      C_PHASE_INCREMENT_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
+      C_PHASE_INCREMENT_VALUE => "1101000110110111,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
       C_RESYNC => 0,
       C_PHASE_OFFSET => 0,
       C_PHASE_OFFSET_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hop_rom/hop_rom_sim_netlist.v

@@ -1,10 +1,10 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
-// Date        : Sat Mar 18 23:15:57 2023
-// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+// Date        : Sat Mar 25 22:39:00 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 // Command     : write_verilog -force -mode funcsim
-//               D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.v
+//               /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk_new/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.v
 // Design      : hop_rom
 // Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
 //               or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -75,9 +75,9 @@ module hop_rom
   (* C_HAS_ENA = "0" *) 
   (* C_HAS_ENB = "0" *) 
   (* C_HAS_INJECTERR = "0" *) 
-  (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) 
+  (* C_HAS_MEM_OUTPUT_REGS_A = "1" *) 
   (* C_HAS_MEM_OUTPUT_REGS_B = "0" *) 
-  (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) 
+  (* C_HAS_MUX_OUTPUT_REGS_A = "1" *) 
   (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) 
   (* C_HAS_REGCEA = "0" *) 
   (* C_HAS_REGCEB = "0" *) 
@@ -200,38 +200,295 @@ module hop_rom_blk_mem_gen_generic_cstr
   wire [7:0]addra;
   wire clka;
   wire [31:0]douta;
+  wire [31:0]ram_douta;
 
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[0] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[0]),
+        .Q(douta[0]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[10] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[10]),
+        .Q(douta[10]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[11] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[11]),
+        .Q(douta[11]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[12] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[12]),
+        .Q(douta[12]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[13] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[13]),
+        .Q(douta[13]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[14] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[14]),
+        .Q(douta[14]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[15] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[15]),
+        .Q(douta[15]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[16] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[16]),
+        .Q(douta[16]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[17] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[17]),
+        .Q(douta[17]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[18] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[18]),
+        .Q(douta[18]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[19] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[19]),
+        .Q(douta[19]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[1] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[1]),
+        .Q(douta[1]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[20] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[20]),
+        .Q(douta[20]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[21] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[21]),
+        .Q(douta[21]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[22] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[22]),
+        .Q(douta[22]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[23] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[23]),
+        .Q(douta[23]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[24] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[24]),
+        .Q(douta[24]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[25] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[25]),
+        .Q(douta[25]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[26] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[26]),
+        .Q(douta[26]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[27] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[27]),
+        .Q(douta[27]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[28] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[28]),
+        .Q(douta[28]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[29] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[29]),
+        .Q(douta[29]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[2] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[2]),
+        .Q(douta[2]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[30] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[30]),
+        .Q(douta[30]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[31] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[31]),
+        .Q(douta[31]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[3] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[3]),
+        .Q(douta[3]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[4] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[4]),
+        .Q(douta[4]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[5] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[5]),
+        .Q(douta[5]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[6] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[6]),
+        .Q(douta[6]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[7] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[7]),
+        .Q(douta[7]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[8] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[8]),
+        .Q(douta[8]),
+        .R(1'b0));
+  FDRE #(
+    .INIT(1'b0)) 
+    \mux_a_wire.mux_reg.ce_pri.douta_i_reg[9] 
+       (.C(clka),
+        .CE(1'b1),
+        .D(ram_douta[9]),
+        .Q(douta[9]),
+        .R(1'b0));
   hop_rom_blk_mem_gen_prim_width \ramloop[0].ram.r 
        (.addra(addra),
         .clka(clka),
-        .douta(douta));
+        .ram_douta(ram_douta));
 endmodule
 
 (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) 
 module hop_rom_blk_mem_gen_prim_width
-   (douta,
+   (ram_douta,
     clka,
     addra);
-  output [31:0]douta;
+  output [31:0]ram_douta;
   input clka;
   input [7:0]addra;
 
   wire [7:0]addra;
   wire clka;
-  wire [31:0]douta;
+  wire [31:0]ram_douta;
 
   hop_rom_blk_mem_gen_prim_wrapper_init \prim_init.ram 
        (.addra(addra),
         .clka(clka),
-        .douta(douta));
+        .ram_douta(ram_douta));
 endmodule
 
 (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) 
 module hop_rom_blk_mem_gen_prim_wrapper_init
-   (douta,
+   (ram_douta,
     clka,
     addra);
-  output [31:0]douta;
+  output [31:0]ram_douta;
   input clka;
   input [7:0]addra;
 
@@ -241,12 +498,12 @@ module hop_rom_blk_mem_gen_prim_wrapper_init
   wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 ;
   wire [7:0]addra;
   wire clka;
-  wire [31:0]douta;
+  wire [31:0]ram_douta;
 
   (* box_type = "PRIMITIVE" *) 
   RAMB18E1 #(
-    .DOA_REG(0),
-    .DOB_REG(0),
+    .DOA_REG(1),
+    .DOB_REG(1),
     .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
     .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
     .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
@@ -353,14 +610,14 @@ module hop_rom_blk_mem_gen_prim_wrapper_init
         .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
         .DIPADIP({1'b0,1'b0}),
         .DIPBDIP({1'b0,1'b0}),
-        .DOADO(douta[15:0]),
-        .DOBDO(douta[31:16]),
+        .DOADO(ram_douta[15:0]),
+        .DOBDO(ram_douta[31:16]),
         .DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 }),
         .DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 }),
         .ENARDEN(1'b1),
         .ENBWREN(1'b1),
-        .REGCEAREGCE(1'b0),
-        .REGCEB(1'b0),
+        .REGCEAREGCE(1'b1),
+        .REGCEB(1'b1),
         .RSTRAMARSTRAM(1'b0),
         .RSTRAMB(1'b0),
         .RSTREGARSTREG(1'b0),
@@ -397,8 +654,8 @@ endmodule
 (* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *) 
 (* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP     :     3.375199 mW" *) 
 (* C_FAMILY = "kintex7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *) 
-(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) 
-(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) 
+(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *) 
+(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "1" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) 
 (* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *) 
 (* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) 
 (* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "hop_rom.mem" *) 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hop_rom/hop_rom_sim_netlist.vhdl

@@ -1,10 +1,10 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
--- Date        : Sat Mar 18 23:15:57 2023
--- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Sat Mar 25 22:39:00 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 -- Command     : write_vhdl -force -mode funcsim
---               D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.vhdl
+--               /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk_new/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.vhdl
 -- Design      : hop_rom
 -- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
 --               synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -16,7 +16,7 @@ library UNISIM;
 use UNISIM.VCOMPONENTS.ALL;
 entity hop_rom_blk_mem_gen_prim_wrapper_init is
   port (
-    douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    ram_douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
     clka : in STD_LOGIC;
     addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
   );
@@ -34,8 +34,8 @@ architecture STRUCTURE of hop_rom_blk_mem_gen_prim_wrapper_init is
 begin
 \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
     generic map(
-      DOA_REG => 0,
-      DOB_REG => 0,
+      DOA_REG => 1,
+      DOB_REG => 1,
       INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
@@ -147,16 +147,16 @@ begin
       DIBDI(15 downto 0) => B"0000000000000000",
       DIPADIP(1 downto 0) => B"00",
       DIPBDIP(1 downto 0) => B"00",
-      DOADO(15 downto 0) => douta(15 downto 0),
-      DOBDO(15 downto 0) => douta(31 downto 16),
+      DOADO(15 downto 0) => ram_douta(15 downto 0),
+      DOBDO(15 downto 0) => ram_douta(31 downto 16),
       DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\,
       DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\,
       DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\,
       DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\,
       ENARDEN => '1',
       ENBWREN => '1',
-      REGCEAREGCE => '0',
-      REGCEB => '0',
+      REGCEAREGCE => '1',
+      REGCEB => '1',
       RSTRAMARSTRAM => '0',
       RSTRAMB => '0',
       RSTREGARSTREG => '0',
@@ -171,7 +171,7 @@ library UNISIM;
 use UNISIM.VCOMPONENTS.ALL;
 entity hop_rom_blk_mem_gen_prim_width is
   port (
-    douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    ram_douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
     clka : in STD_LOGIC;
     addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
   );
@@ -185,7 +185,7 @@ begin
      port map (
       addra(7 downto 0) => addra(7 downto 0),
       clka => clka,
-      douta(31 downto 0) => douta(31 downto 0)
+      ram_douta(31 downto 0) => ram_douta(31 downto 0)
     );
 end STRUCTURE;
 library IEEE;
@@ -203,12 +203,365 @@ entity hop_rom_blk_mem_gen_generic_cstr is
 end hop_rom_blk_mem_gen_generic_cstr;
 
 architecture STRUCTURE of hop_rom_blk_mem_gen_generic_cstr is
+  signal ram_douta : STD_LOGIC_VECTOR ( 31 downto 0 );
 begin
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[0]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(0),
+      Q => douta(0),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[10]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(10),
+      Q => douta(10),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[11]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(11),
+      Q => douta(11),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[12]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(12),
+      Q => douta(12),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[13]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(13),
+      Q => douta(13),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[14]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(14),
+      Q => douta(14),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[15]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(15),
+      Q => douta(15),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[16]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(16),
+      Q => douta(16),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[17]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(17),
+      Q => douta(17),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[18]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(18),
+      Q => douta(18),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[19]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(19),
+      Q => douta(19),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[1]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(1),
+      Q => douta(1),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[20]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(20),
+      Q => douta(20),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[21]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(21),
+      Q => douta(21),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[22]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(22),
+      Q => douta(22),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[23]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(23),
+      Q => douta(23),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[24]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(24),
+      Q => douta(24),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[25]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(25),
+      Q => douta(25),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[26]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(26),
+      Q => douta(26),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[27]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(27),
+      Q => douta(27),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[28]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(28),
+      Q => douta(28),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[29]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(29),
+      Q => douta(29),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[2]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(2),
+      Q => douta(2),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[30]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(30),
+      Q => douta(30),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[31]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(31),
+      Q => douta(31),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[3]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(3),
+      Q => douta(3),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[4]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(4),
+      Q => douta(4),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[5]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(5),
+      Q => douta(5),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[6]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(6),
+      Q => douta(6),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[7]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(7),
+      Q => douta(7),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[8]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(8),
+      Q => douta(8),
+      R => '0'
+    );
+\mux_a_wire.mux_reg.ce_pri.douta_i_reg[9]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => clka,
+      CE => '1',
+      D => ram_douta(9),
+      Q => douta(9),
+      R => '0'
+    );
 \ramloop[0].ram.r\: entity work.hop_rom_blk_mem_gen_prim_width
      port map (
       addra(7 downto 0) => addra(7 downto 0),
       clka => clka,
-      douta(31 downto 0) => douta(31 downto 0)
+      ram_douta(31 downto 0) => ram_douta(31 downto 0)
     );
 end STRUCTURE;
 library IEEE;
@@ -386,11 +739,11 @@ entity hop_rom_blk_mem_gen_v8_4_3 is
   attribute C_HAS_INJECTERR : integer;
   attribute C_HAS_INJECTERR of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
   attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
-  attribute C_HAS_MEM_OUTPUT_REGS_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_HAS_MEM_OUTPUT_REGS_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 1;
   attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
   attribute C_HAS_MEM_OUTPUT_REGS_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
   attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
-  attribute C_HAS_MUX_OUTPUT_REGS_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
+  attribute C_HAS_MUX_OUTPUT_REGS_A of hop_rom_blk_mem_gen_v8_4_3 : entity is 1;
   attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
   attribute C_HAS_MUX_OUTPUT_REGS_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 0;
   attribute C_HAS_REGCEA : integer;
@@ -701,11 +1054,11 @@ architecture STRUCTURE of hop_rom is
   attribute C_HAS_INJECTERR : integer;
   attribute C_HAS_INJECTERR of U0 : label is 0;
   attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
-  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
+  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
   attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
   attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
   attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
-  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
+  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 1;
   attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
   attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
   attribute C_HAS_REGCEA : integer;

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hop_rom/hop_rom_stub.v

@@ -1,10 +1,10 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
-// Date        : Sat Mar 18 23:15:57 2023
-// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+// Date        : Sat Mar 25 22:39:00 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 // Command     : write_verilog -force -mode synth_stub
-//               D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.v
+//               /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk_new/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.v
 // Design      : hop_rom
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7k410tffg900-2

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hop_rom/hop_rom_stub.vhdl

@@ -1,10 +1,10 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
--- Date        : Sat Mar 18 23:15:57 2023
--- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Sat Mar 25 22:39:00 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 -- Command     : write_vhdl -force -mode synth_stub
---               D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.vhdl
+--               /home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk_new/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.vhdl
 -- Design      : hop_rom
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7k410tffg900-2

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hop_rom/sim/hop_rom.v

@@ -116,9 +116,9 @@ output wire [31 : 0] douta;
     .C_WRITE_DEPTH_B(256),
     .C_READ_DEPTH_B(256),
     .C_ADDRB_WIDTH(8),
-    .C_HAS_MEM_OUTPUT_REGS_A(0),
+    .C_HAS_MEM_OUTPUT_REGS_A(1),
     .C_HAS_MEM_OUTPUT_REGS_B(0),
-    .C_HAS_MUX_OUTPUT_REGS_A(0),
+    .C_HAS_MUX_OUTPUT_REGS_A(1),
     .C_HAS_MUX_OUTPUT_REGS_B(0),
     .C_MUX_PIPELINE_STAGES(0),
     .C_HAS_SOFTECC_INPUT_REGS_A(0),

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hrc_64_12_025/demo_tb/tb_hrc_64_12_025.vhd

@@ -183,7 +183,7 @@ begin
 
     -- Procedure to drive an impulse and let the impulse response emerge on the data master channel
     -- samples is the number of input samples to drive; default is enough for impulse response output to emerge
-    procedure drive_impulse ( samples : natural := 837 ) is
+    procedure drive_impulse ( samples : natural := 901 ) is
       variable impulse : std_logic_vector(7 downto 0);
     begin
       impulse := (others => '0');  -- initialize unused bits to zero
@@ -210,7 +210,7 @@ begin
     drive_zeros(2);  -- 2 normal input samples
     s_axis_data_tvalid <= '1';
     wait for CLOCK_PERIOD * 320;  -- provide data as fast as the core can accept it for 5 input samples worth
-    drive_zeros(828);  -- back to normal operation
+    drive_zeros(892);  -- back to normal operation
 
     -- End of test
     report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hrc_64_12_025/hrc_64_12_025_stub.v

@@ -1,10 +1,10 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
-// Date        : Sat Mar 18 23:15:42 2023
-// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
-// Command     : write_verilog -force -mode synth_stub
-//               D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_stub.v
+// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+// Date        : Sat Mar 25 22:38:37 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+// Command     : write_verilog -force -mode synth_stub -rename_top hrc_64_12_025 -prefix
+//               hrc_64_12_025_ hrc_64_12_025_stub.v
 // Design      : hrc_64_12_025
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7k410tffg900-2

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hrc_64_12_025/hrc_64_12_025_stub.vhdl

@@ -1,10 +1,10 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
--- Date        : Sat Mar 18 23:15:42 2023
--- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
--- Command     : write_vhdl -force -mode synth_stub
---               D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_stub.vhdl
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Sat Mar 25 22:38:37 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+-- Command     : write_vhdl -force -mode synth_stub -rename_top hrc_64_12_025 -prefix
+--               hrc_64_12_025_ hrc_64_12_025_stub.vhdl
 -- Design      : hrc_64_12_025
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7k410tffg900-2

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/ip/hrc_64_12_025/sim/hrc_64_12_025.vhd

@@ -192,12 +192,12 @@ BEGIN
       C_ELABORATION_DIR => "./",
       C_COMPONENT_NAME => "hrc_64_12_025",
       C_COEF_FILE => "hrc_64_12_025.mif",
-      C_COEF_FILE_LINES => 832,
+      C_COEF_FILE_LINES => 448,
       C_FILTER_TYPE => 2,
       C_INTERP_RATE => 64,
       C_DECIM_RATE => 1,
       C_ZERO_PACKING_FACTOR => 1,
-      C_SYMMETRY => 0,
+      C_SYMMETRY => 1,
       C_NUM_FILTS => 1,
       C_NUM_TAPS => 769,
       C_NUM_CHANNELS => 1,
@@ -207,27 +207,27 @@ BEGIN
       C_NUM_RELOAD_SLOTS => 1,
       C_COL_MODE => 1,
       C_COL_PIPE_LEN => 4,
-      C_COL_CONFIG => "13",
+      C_COL_CONFIG => "7",
       C_OPTIMIZATION => 0,
       C_DATA_PATH_WIDTHS => "2",
       C_DATA_IP_PATH_WIDTHS => "2",
       C_DATA_PX_PATH_WIDTHS => "2",
       C_DATA_WIDTH => 2,
-      C_COEF_PATH_WIDTHS => "16",
+      C_COEF_PATH_WIDTHS => "17",
       C_COEF_WIDTH => 16,
       C_DATA_PATH_SRC => "0",
       C_COEF_PATH_SRC => "0",
       C_PX_PATH_SRC => "0",
       C_DATA_PATH_SIGN => "0",
       C_COEF_PATH_SIGN => "0",
-      C_ACCUM_PATH_WIDTHS => "18",
+      C_ACCUM_PATH_WIDTHS => "19",
       C_OUTPUT_WIDTH => 18,
       C_OUTPUT_PATH_WIDTHS => "18",
       C_ACCUM_OP_PATH_WIDTHS => "18",
       C_EXT_MULT_CNFG => "none",
       C_DATA_PATH_PSAMP_SRC => "0",
       C_OP_PATH_PSAMP_SRC => "0",
-      C_NUM_MADDS => 13,
+      C_NUM_MADDS => 7,
       C_OPT_MADDS => "none",
       C_OVERSAMPLING_RATE => 1,
       C_INPUT_RATE => 64,
@@ -235,13 +235,13 @@ BEGIN
       C_DATA_MEMTYPE => 0,
       C_COEF_MEMTYPE => 2,
       C_IPBUFF_MEMTYPE => 0,
-      C_OPBUFF_MEMTYPE => 0,
+      C_OPBUFF_MEMTYPE => 2,
       C_DATAPATH_MEMTYPE => 0,
-      C_MEM_ARRANGEMENT => 2,
+      C_MEM_ARRANGEMENT => 1,
       C_DATA_MEM_PACKING => 0,
       C_COEF_MEM_PACKING => 0,
       C_FILTS_PACKED => 0,
-      C_LATENCY => 19,
+      C_LATENCY => 17,
       C_HAS_ARESETn => 0,
       C_HAS_ACLKEN => 0,
       C_DATA_HAS_TLAST => 0,

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/activehdl/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Sat Mar 18 23:15:09 +0800 2023
+# Generated by export_simulation on Sat Mar 25 22:59:06 CST 2023
 #
 ################################################################################
 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/activehdl/cmpy_18x8.sh

@@ -9,8 +9,8 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Sat Mar 18 23:15:09 +0800 2023
-# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+# Generated by Vivado on Sat Mar 25 22:59:06 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
@@ -93,11 +93,9 @@ setup()
 map_setup_file()
 {
   file="library.cfg"
-  lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
-  if [[ ($1 != "" && -e $1) ]]; then
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
     lib_map_path="$1"
-  else
-    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
   fi
   if [[ ($lib_map_path != "") ]]; then
     src_file="$lib_map_path/$file"

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/activehdl/compile.do

@@ -20,10 +20,10 @@ vmap mult_gen_v12_0_15 activehdl/mult_gen_v12_0_15
 vmap cmpy_v6_0_17 activehdl/cmpy_v6_0_17
 
 vlog -work xil_defaultlib  -sv2k12 \
-"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 
 vcom -work xpm -93 \
-"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 
 vcom -work xbip_utils_v3_0_10 -93 \
 "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/activehdl/file_info.txt

@@ -1,5 +1,5 @@
-xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
 xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
 axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
 xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/ies/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Sat Mar 18 23:15:09 +0800 2023
+# Generated by export_simulation on Sat Mar 25 22:59:06 CST 2023
 #
 ################################################################################
 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/ies/cmpy_18x8.sh

@@ -9,8 +9,8 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Sat Mar 18 23:15:09 +0800 2023
-# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+# Generated by Vivado on Sat Mar 25 22:59:06 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/ies/file_info.txt

@@ -1,5 +1,5 @@
-xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
 xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
 axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
 xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/ies/run.f

@@ -1,8 +1,8 @@
 -makelib ies_lib/xil_defaultlib -sv \
-  "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 -endlib
 -makelib ies_lib/xpm \
-  "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 -endlib
 -makelib ies_lib/xbip_utils_v3_0_10 \
   "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/modelsim/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Sat Mar 18 23:15:09 +0800 2023
+# Generated by export_simulation on Sat Mar 25 22:59:06 CST 2023
 #
 ################################################################################
 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/modelsim/cmpy_18x8.sh

@@ -9,8 +9,8 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Sat Mar 18 23:15:09 +0800 2023
-# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+# Generated by Vivado on Sat Mar 25 22:59:06 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
@@ -98,7 +98,7 @@ copy_setup_file()
   if [[ ($1 != "") ]]; then
     lib_map_path="$1"
   else
-    lib_map_path="C:/Mentor/CompLib/2019.1.3"
+    lib_map_path="/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/modelsim"
   fi
   if [[ ($lib_map_path != "") ]]; then
     src_file="$lib_map_path/$file"

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/modelsim/compile.do

@@ -2,10 +2,51 @@ vlib modelsim_lib/work
 vlib modelsim_lib/msim
 
 vlib modelsim_lib/msim/xil_defaultlib
+vlib modelsim_lib/msim/xpm
+vlib modelsim_lib/msim/xbip_utils_v3_0_10
+vlib modelsim_lib/msim/axi_utils_v2_0_6
+vlib modelsim_lib/msim/xbip_pipe_v3_0_6
+vlib modelsim_lib/msim/xbip_bram18k_v3_0_6
+vlib modelsim_lib/msim/mult_gen_v12_0_15
+vlib modelsim_lib/msim/cmpy_v6_0_17
 
 vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+vmap xpm modelsim_lib/msim/xpm
+vmap xbip_utils_v3_0_10 modelsim_lib/msim/xbip_utils_v3_0_10
+vmap axi_utils_v2_0_6 modelsim_lib/msim/axi_utils_v2_0_6
+vmap xbip_pipe_v3_0_6 modelsim_lib/msim/xbip_pipe_v3_0_6
+vmap xbip_bram18k_v3_0_6 modelsim_lib/msim/xbip_bram18k_v3_0_6
+vmap mult_gen_v12_0_15 modelsim_lib/msim/mult_gen_v12_0_15
+vmap cmpy_v6_0_17 modelsim_lib/msim/cmpy_v6_0_17
+
+vlog -work xil_defaultlib -64 -incr -sv \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work xbip_utils_v3_0_10 -64 -93 \
+"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+
+vcom -work axi_utils_v2_0_6 -64 -93 \
+"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+
+vcom -work xbip_pipe_v3_0_6 -64 -93 \
+"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+
+vcom -work xbip_bram18k_v3_0_6 -64 -93 \
+"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+
+vcom -work mult_gen_v12_0_15 -64 -93 \
+"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+
+vcom -work cmpy_v6_0_17 -64 -93 \
+"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
 
 vcom -work xil_defaultlib -64 -93 \
 "../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd" \
 
 
+vlog -work xil_defaultlib \
+"glbl.v"
+

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/modelsim/file_info.txt

@@ -1 +1,10 @@
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
 cmpy_18x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd,
+glbl.v,Verilog,xil_defaultlib,glbl.v

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/modelsim/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/modelsim/simulate.do

@@ -1,7 +1,7 @@
 onbreak {quit -f}
 onerror {quit -f}
 
-vsim -voptargs="+acc" -t 1ps -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L xil_defaultlib -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.cmpy_18x8
+vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.cmpy_18x8 xil_defaultlib.glbl
 
 do {wave.do}
 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/modelsim/wave.do

@@ -1 +1,2 @@
 add wave *
+add wave /glbl/GSR

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/questa/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Sat Mar 18 23:15:09 +0800 2023
+# Generated by export_simulation on Sat Mar 25 22:59:06 CST 2023
 #
 ################################################################################
 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/questa/cmpy_18x8.sh

@@ -9,8 +9,8 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Sat Mar 18 23:15:09 +0800 2023
-# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+# Generated by Vivado on Sat Mar 25 22:59:06 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
@@ -102,11 +102,10 @@ setup()
 copy_setup_file()
 {
   file="modelsim.ini"
-  lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
-  if [[ ($1 != "" && -e $1) ]]; then
+  if [[ ($1 != "") ]]; then
     lib_map_path="$1"
   else
-    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+    lib_map_path="/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa"
   fi
   if [[ ($lib_map_path != "") ]]; then
     src_file="$lib_map_path/$file"

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/questa/compile.do

@@ -20,10 +20,10 @@ vmap mult_gen_v12_0_15 questa_lib/msim/mult_gen_v12_0_15
 vmap cmpy_v6_0_17 questa_lib/msim/cmpy_v6_0_17
 
 vlog -work xil_defaultlib -64 -sv \
-"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 
 vcom -work xpm -64 -93 \
-"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 
 vcom -work xbip_utils_v3_0_10 -64 -93 \
 "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/questa/file_info.txt

@@ -1,5 +1,5 @@
-xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
 xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
 axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
 xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/riviera/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Sat Mar 18 23:15:09 +0800 2023
+# Generated by export_simulation on Sat Mar 25 22:59:06 CST 2023
 #
 ################################################################################
 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/riviera/cmpy_18x8.sh

@@ -9,8 +9,8 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Sat Mar 18 23:15:09 +0800 2023
-# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+# Generated by Vivado on Sat Mar 25 22:59:06 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
@@ -93,11 +93,10 @@ setup()
 map_setup_file()
 {
   file="library.cfg"
-  lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
-  if [[ ($1 != "" && -e $1) ]]; then
+  if [[ ($1 != "") ]]; then
     lib_map_path="$1"
   else
-    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+    lib_map_path="/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera"
   fi
   if [[ ($lib_map_path != "") ]]; then
     src_file="$lib_map_path/$file"

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/riviera/compile.do

@@ -20,10 +20,10 @@ vmap mult_gen_v12_0_15 riviera/mult_gen_v12_0_15
 vmap cmpy_v6_0_17 riviera/cmpy_v6_0_17
 
 vlog -work xil_defaultlib  -sv2k12 \
-"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 
 vcom -work xpm -93 \
-"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 
 vcom -work xbip_utils_v3_0_10 -93 \
 "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/riviera/file_info.txt

@@ -1,5 +1,5 @@
-xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
 xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
 axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
 xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/vcs/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Sat Mar 18 23:15:09 +0800 2023
+# Generated by export_simulation on Sat Mar 25 22:59:06 CST 2023
 #
 ################################################################################
 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/vcs/cmpy_18x8.sh

@@ -9,8 +9,8 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Sat Mar 18 23:15:09 +0800 2023
-# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+# Generated by Vivado on Sat Mar 25 22:59:06 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
@@ -71,11 +71,11 @@ compile()
 {
   # Compile design files
   vlogan -work xil_defaultlib $vlogan_opts -sverilog \
-    "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+    "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
   2>&1 | tee -a vlogan.log
 
   vhdlan -work xpm $vhdlan_opts \
-    "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+    "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vhdlan -work xbip_utils_v3_0_10 $vhdlan_opts \
@@ -170,9 +170,10 @@ create_lib_mappings()
 
   touch $file
 
-  lib_map_path=""
   if [[ ($1 != "") ]]; then
     lib_map_path="$1"
+  else
+    lib_map_path="/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/vcs"
   fi
 
   for (( i=0; i<${#design_libs[*]}; i++ )); do

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/vcs/file_info.txt

@@ -1,5 +1,5 @@
-xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
 xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
 axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
 xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/xcelium/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Sat Mar 18 23:15:09 +0800 2023
+# Generated by export_simulation on Sat Mar 25 22:59:06 CST 2023
 #
 ################################################################################
 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/xcelium/cmpy_18x8.sh

@@ -9,8 +9,8 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Sat Mar 18 23:15:09 +0800 2023
-# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+# Generated by Vivado on Sat Mar 25 22:59:06 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/xcelium/file_info.txt

@@ -1,5 +1,5 @@
-xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
 xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
 axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
 xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/xcelium/run.f

@@ -1,8 +1,8 @@
 -makelib xcelium_lib/xil_defaultlib -sv \
-  "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 -endlib
 -makelib xcelium_lib/xpm \
-  "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 -endlib
 -makelib xcelium_lib/xbip_utils_v3_0_10 \
   "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/xsim/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Sat Mar 18 23:15:09 +0800 2023
+# Generated by export_simulation on Sat Mar 25 22:59:06 CST 2023
 #
 ################################################################################
 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/xsim/cmpy_18x8.sh

@@ -9,8 +9,8 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Sat Mar 18 23:15:09 +0800 2023
-# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+# Generated by Vivado on Sat Mar 25 22:59:06 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
@@ -22,7 +22,7 @@
 #*********************************************************************************************************
 
 # Command line options
-xv_boost_lib_path=C:/Xilinx/Vivado/2019.1/tps/boost_1_64_0
+xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0
 xvhdl_opts="--relax"
 
 
@@ -92,7 +92,7 @@ setup()
 copy_setup_file()
 {
   file="xsim.ini"
-  lib_map_path="C:/Xilinx/Vivado/2019.1/data/xsim"
+  lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim"
   if [[ ($1 != "") ]]; then
     lib_map_path="$1"
   fi

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/xsim/elab.opt

@@ -1 +0,0 @@
---relax --debug typical --mt auto -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L xil_defaultlib -L secureip -L xpm --snapshot cmpy_18x8 xil_defaultlib.cmpy_18x8 -log elaborate.log

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/cmpy_18x8/xsim/xsim.ini

@@ -1,430 +0,0 @@
-std=$RDI_DATADIR/xsim/vhdl/std
-ieee=$RDI_DATADIR/xsim/vhdl/ieee
-ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
-vl=$RDI_DATADIR/xsim/vhdl/vl
-synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
-secureip=$RDI_DATADIR/xsim/verilog/secureip
-unisim=$RDI_DATADIR/xsim/vhdl/unisim
-unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
-unifast=$RDI_DATADIR/xsim/vhdl/unifast
-unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
-unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
-unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
-simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
-system_cache_v4_0_6=$RDI_DATADIR/xsim/ip/system_cache_v4_0_6
-bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0
-g709_rs_decoder_v2_2_8=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_8
-xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
-mipi_dphy_v4_1_4=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_1_4
-iomodule_v3_1_4=$RDI_DATADIR/xsim/ip/iomodule_v3_1_4
-ieee802d3_50g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_11
-common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
-lte_fft_v2_1_0=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_0
-ieee802d3_50g_rs_fec_v2_0_1=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_1
-convolution_v9_0_14=$RDI_DATADIR/xsim/ip/convolution_v9_0_14
-gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
-v_cfa_v7_0_14=$RDI_DATADIR/xsim/ip/v_cfa_v7_0_14
-axi4svideo_bridge_v1_0_10=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_10
-pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11
-v_vscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_13
-xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6
-gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
-ethernet_1_10_25g_v2_2_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_2_3
-zynq_ultra_ps_e_v3_3_0=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_0
-v_cresample_v4_0_14=$RDI_DATADIR/xsim/ip/v_cresample_v4_0_14
-v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9
-v_scenechange_v1_0_1=$RDI_DATADIR/xsim/ip/v_scenechange_v1_0_1
-hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0
-ahblite_axi_bridge_v3_0_14=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_14
-tri_mode_ethernet_mac_v9_0_14=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_14
-blk_mem_gen_v8_4_3=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_3
-noc_mc_ddr4_phy_v1_0_0=$RDI_DATADIR/xsim/ip/noc_mc_ddr4_phy_v1_0_0
-axi_data_fifo_v2_1_18=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_18
-axi_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_5
-ethernet_1_10_25g_v2_0_5=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_0_5
-compact_gt_v1_0_5=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_5
-axi_gpio_v2_0_21=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_21
-qdma_v3_0_2=$RDI_DATADIR/xsim/ip/qdma_v3_0_2
-viterbi_v9_1_11=$RDI_DATADIR/xsim/ip/viterbi_v9_1_11
-sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2
-ba317=$RDI_DATADIR/xsim/ip/ba317
-xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4
-fifo_generator_v13_2_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_4
-axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14
-vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0
-axi_emc_v3_0_19=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_19
-cmac_v2_5_1=$RDI_DATADIR/xsim/ip/cmac_v2_5_1
-floating_point_v7_1_8=$RDI_DATADIR/xsim/ip/floating_point_v7_1_8
-xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6
-vid_phy_controller_v2_2_3=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_3
-common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
-axi_firewall_v1_0_7=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_7
-util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1
-axis_accelerator_adapter_v2_1_15=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_15
-tmr_comparator_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_2
-sd_fec_v1_0_2=$RDI_DATADIR/xsim/ip/sd_fec_v1_0_2
-tmr_manager_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_4
-tsn_temac_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_4
-usxgmii_v1_0_5=$RDI_DATADIR/xsim/ip/usxgmii_v1_0_5
-lte_dl_channel_encoder_v4_0_0=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v4_0_0
-ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
-lte_3gpp_mimo_decoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_15
-v_uhdsdi_audio_v1_0_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_0_0
-axi4stream_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_5
-cmac_usplus_v2_4_5=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_4_5
-etrnic_v1_1_2=$RDI_DATADIR/xsim/ip/etrnic_v1_1_2
-floating_point_v7_0_16=$RDI_DATADIR/xsim/ip/floating_point_v7_0_16
-axi_dma_v7_1_20=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_20
-jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
-axi_traffic_gen_v3_0_5=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_5
-emb_mem_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_1
-axi_amm_bridge_v1_0_9=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_9
-axi_datamover_v5_1_21=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_21
-v_axi4s_vid_out_v4_0_10=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_10
-jesd204_v7_2_6=$RDI_DATADIR/xsim/ip/jesd204_v7_2_6
-v_letterbox_v1_0_13=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_13
-interlaken_v2_4_3=$RDI_DATADIR/xsim/ip/interlaken_v2_4_3
-uhdsdi_gt_v2_0_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_0
-axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7
-rst_vip_v1_0_3=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_3
-audio_formatter_v1_0_1=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_1
-lte_3gpp_channel_estimator_v2_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_16
-v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13
-g709_fec_v2_3_5=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_5
-xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6
-axi_chip2chip_v5_0_6=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_6
-fc32_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_11
-v_mix_v3_0_3=$RDI_DATADIR/xsim/ip/v_mix_v3_0_3
-multi_channel_25g_rs_fec_v1_0_5=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_5
-in_system_ibert_v1_0_9=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_9
-ethernet_1_10_25g_v2_1_4=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_1_4
-axis_broadcaster_v1_1_18=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_18
-axis_combiner_v1_1_17=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_17
-axi_apb_bridge_v3_0_15=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_15
-displayport_v9_0_1=$RDI_DATADIR/xsim/ip/displayport_v9_0_1
-clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2
-hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1
-axi_register_slice_v2_1_19=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_19
-vid_phy_controller_v2_1_5=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_5
-picxo=$RDI_DATADIR/xsim/ip/picxo
-usxgmii_v1_1_0=$RDI_DATADIR/xsim/ip/usxgmii_v1_1_0
-v_vcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_13
-bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0
-prc_v1_3_2=$RDI_DATADIR/xsim/ip/prc_v1_3_2
-axi_usb2_device_v5_0_20=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_20
-lte_3gpp_mimo_encoder_v4_0_14=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_14
-l_ethernet_v2_5_2=$RDI_DATADIR/xsim/ip/l_ethernet_v2_5_2
-xdma_v4_1_3=$RDI_DATADIR/xsim/ip/xdma_v4_1_3
-axis_vio_v1_0_0=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_0
-c_counter_binary_v12_0_13=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_13
-noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0
-xbip_dsp48_macro_v3_0_17=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_17
-c_accum_v12_0_13=$RDI_DATADIR/xsim/ip/c_accum_v12_0_13
-xbip_multadd_v3_0_14=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_14
-axi_uartlite_v2_0_23=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_23
-noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
-axi_intc_v4_1_13=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_13
-i2s_transmitter_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_3
-pc_cfr_v6_0_8=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_8
-mutex_v2_1_10=$RDI_DATADIR/xsim/ip/mutex_v2_1_10
-c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6
-sid_v8_0_14=$RDI_DATADIR/xsim/ip/sid_v8_0_14
-fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6
-quadsgmii_v3_4_6=$RDI_DATADIR/xsim/ip/quadsgmii_v3_4_6
-microblaze_v11_0_1=$RDI_DATADIR/xsim/ip/microblaze_v11_0_1
-lib_bmg_v1_0_12=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_12
-dds_compiler_v6_0_18=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_18
-me_pl_v1_0=$RDI_DATADIR/xsim/ip/me_pl_v1_0
-gtwizard_ultrascale_v1_7_6=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_6
-axis_clock_converter_v1_1_20=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_20
-nvmeha_v1_0_0=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_0
-tmr_inject_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_3
-axi_mcdma_v1_1_0=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_0
-axi_hwicap_v3_0_23=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_23
-v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0
-v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0
-canfd_v2_0_1=$RDI_DATADIR/xsim/ip/canfd_v2_0_1
-gig_ethernet_pcs_pma_v16_1_6=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_6
-lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2
-ieee802d3_rs_fec_v2_0_5=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_5
-ibert_lib_v1_0_6=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_6
-high_speed_selectio_wiz_v3_4_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_1
-xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6
-fec_5g_common_v1_0_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_1
-tmr_voter_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_2
-hdmi_gt_controller_v1_0_0=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_0
-axi_traffic_gen_v2_0_20=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_20
-flexo_100g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_11
-v_smpte_uhdsdi_v1_0_7=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_7
-xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6
-fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10
-ieee802d3_rs_fec_v1_0_15=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_15
-axis_subset_converter_v1_1_19=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_19
-noc_nmu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_v1_0_0
-duc_ddc_compiler_v3_0_15=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_15
-dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13
-mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0
-ieee802d3_200g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_7
-sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
-mrmac_v1_0_0=$RDI_DATADIR/xsim/ip/mrmac_v1_0_0
-sem_ultra_v3_1_11=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_11
-v_tpg_v8_0_1=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_1
-axi_tft_v2_0_22=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_22
-ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13
-switch_core_top_v1_0_7=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_7
-rama_v1_1_2_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_2_lib
-v_hcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_13
-emb_fifo_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_1
-hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3
-axis_data_fifo_v2_0_1=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_1
-hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0
-rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
-displayport_v8_1_1=$RDI_DATADIR/xsim/ip/displayport_v8_1_1
-axi_mmu_v2_1_17=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_17
-proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13
-pc_cfr_v6_3_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_3_0
-v_osd_v6_0_16=$RDI_DATADIR/xsim/ip/v_osd_v6_0_16
-pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12
-xfft_v9_0_17=$RDI_DATADIR/xsim/ip/xfft_v9_0_17
-axi_cdma_v4_1_19=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_19
-audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0
-lib_fifo_v1_0_13=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_13
-v_enhance_v8_0_15=$RDI_DATADIR/xsim/ip/v_enhance_v8_0_15
-axi_clock_converter_v2_1_18=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_18
-xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0
-emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5
-axi_mm2s_mapper_v1_1_18=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_18
-xfft_v7_2_9=$RDI_DATADIR/xsim/ip/xfft_v7_2_9
-pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
-v_smpte_sdi_v3_0_8=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_8
-fir_compiler_v7_2_12=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_12
-div_gen_v5_1_15=$RDI_DATADIR/xsim/ip/div_gen_v5_1_15
-mdm_v3_2_16=$RDI_DATADIR/xsim/ip/mdm_v3_2_16
-v_axi4s_remap_v1_0_11=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_11
-xxv_ethernet_v2_5_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_5_3
-xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2
-ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
-remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
-pr_axi_shutdown_manager_v1_0_1=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_1
-axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0
-smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
-axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib
-axi_dwidth_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_19
-xlconstant_v1_1_6=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_6
-tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6
-mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
-v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1
-axi_fifo_mm_s_v4_2_1=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_1
-util_idelay_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_1
-rs_toolbox_v9_0_7=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_7
-v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0
-dsp_macro_v1_0_0=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_0
-pc_cfr_v6_2_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_2
-axi_timer_v2_0_21=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_21
-high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1
-axi_sideband_util_v1_0_3=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_3
-sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2
-gmii_to_rgmii_v4_0_7=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_0_7
-xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2
-high_speed_selectio_wiz_v3_5_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_5_1
-axi_msg_v1_0_5=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_5
-axi_ahblite_bridge_v3_0_16=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_16
-v_rgb2ycrcb_v7_1_13=$RDI_DATADIR/xsim/ip/v_rgb2ycrcb_v7_1_13
-v_mix_v4_0_0=$RDI_DATADIR/xsim/ip/v_mix_v4_0_0
-axi_ethernetlite_v3_0_17=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_17
-axi_uart16550_v2_0_21=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_21
-axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0
-vfb_v1_0_13=$RDI_DATADIR/xsim/ip/vfb_v1_0_13
-advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0
-ats_switch_v1_0_2=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_2
-interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4
-axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
-cpri_v8_10_3=$RDI_DATADIR/xsim/ip/cpri_v8_10_3
-c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6
-v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0
-stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
-rld3_pl_v1_0_1=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_1
-ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0
-lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0
-axi_epc_v2_0_22=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_22
-g709_rs_encoder_v2_2_6=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_6
-blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6
-tmr_sem_v1_0_9=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_9
-fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6
-axi_vdma_v6_3_7=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_7
-axis_data_fifo_v1_1_20=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_20
-xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
-axi_ethernet_buffer_v2_0_20=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_20
-rs_encoder_v9_0_15=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_15
-axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
-ta_dma_v1_0_3=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_3
-tcc_encoder_3gpp_v5_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_15
-axi_perf_mon_v5_0_21=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_21
-noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
-sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
-lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2
-v_csc_v1_0_13=$RDI_DATADIR/xsim/ip/v_csc_v1_0_13
-shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0
-lte_fft_v2_0_18=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_18
-gtwizard_ultrascale_v1_6_11=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_11
-amm_axi_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_5
-mii_to_rmii_v2_0_21=$RDI_DATADIR/xsim/ip/mii_to_rmii_v2_0_21
-videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5
-audio_clock_recovery_v1_0=$RDI_DATADIR/xsim/ip/audio_clock_recovery_v1_0
-cmac_v2_4_1=$RDI_DATADIR/xsim/ip/cmac_v2_4_1
-i2s_receiver_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_3
-v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0
-v_demosaic_v1_0_5=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_5
-remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
-microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4
-hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3
-etrnic_v1_0_3=$RDI_DATADIR/xsim/ip/etrnic_v1_0_3
-xfft_v9_1_2=$RDI_DATADIR/xsim/ip/xfft_v9_1_2
-ddr4_pl_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_2
-xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6
-cmac_usplus_v2_5_3=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_5_3
-jesd204c_v4_1_1=$RDI_DATADIR/xsim/ip/jesd204c_v4_1_1
-debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
-axis_protocol_checker_v2_0_3=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_3
-v_frmbuf_wr_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_2
-v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9
-mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4
-lte_dl_channel_encoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_15
-axi_protocol_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_19
-xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
-clk_gen_sim_v1_0_0=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_0
-axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
-microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7
-cmpy_v6_0_17=$RDI_DATADIR/xsim/ip/cmpy_v6_0_17
-cmac_v2_3_5=$RDI_DATADIR/xsim/ip/cmac_v2_3_5
-ieee802d3_400g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_7
-xxv_ethernet_v2_4_5=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_4_5
-axi_timebase_wdt_v3_0_11=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_11
-tcc_decoder_3gppmm_v2_0_18=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_18
-v_deinterlacer_v5_0_13=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_13
-dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16
-axi_fifo_mm_s_v4_1_16=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_16
-processing_system7_vip_v1_0_7=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_7
-g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18
-rs_decoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_16
-c_shift_ram_v12_0_13=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_13
-displayport_v7_0_11=$RDI_DATADIR/xsim/ip/displayport_v7_0_11
-v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0
-v_deinterlacer_v4_0_12=$RDI_DATADIR/xsim/ip/v_deinterlacer_v4_0_12
-sem_v4_1_12=$RDI_DATADIR/xsim/ip/sem_v4_1_12
-xaui_v12_3_6=$RDI_DATADIR/xsim/ip/xaui_v12_3_6
-ten_gig_eth_mac_v15_1_7=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_7
-oddr_v1_0_0=$RDI_DATADIR/xsim/ip/oddr_v1_0_0
-c_addsub_v12_0_13=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_13
-v_ccm_v6_0_15=$RDI_DATADIR/xsim/ip/v_ccm_v6_0_15
-zynq_ultra_ps_e_vip_v1_0_5=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_5
-cic_compiler_v4_0_14=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_14
-c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6
-axi_memory_init_v1_0_0=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_0
-pr_decoupler_v1_0_7=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_7
-timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4
-lte_pucch_receiver_v2_0_16=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_16
-zynq_ultra_ps_e_v3_2_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_3
-v_gamma_lut_v1_0_5=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_5
-bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0
-pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0
-tcc_encoder_3gpplte_v4_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_15
-polar_v1_0_3=$RDI_DATADIR/xsim/ip/polar_v1_0_3
-rxaui_v4_4_6=$RDI_DATADIR/xsim/ip/rxaui_v4_4_6
-xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6
-v_gamma_v7_0_15=$RDI_DATADIR/xsim/ip/v_gamma_v7_0_15
-ernic_v1_0_1=$RDI_DATADIR/xsim/ip/ernic_v1_0_1
-high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3
-mailbox_v2_1_11=$RDI_DATADIR/xsim/ip/mailbox_v2_1_11
-video_frame_crc_v1_0_1=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_1
-axi_sg_v4_1_12=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_12
-ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0
-lmb_bram_if_cntlr_v4_0_16=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_16
-l_ethernet_v2_4_3=$RDI_DATADIR/xsim/ip/l_ethernet_v2_4_3
-dft_v4_1_1=$RDI_DATADIR/xsim/ip/dft_v4_1_1
-rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0
-axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6
-v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0
-stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0
-lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
-uhdsdi_gt_v1_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_3
-pc_cfr_v6_1_4=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_4
-lmb_v10_v3_0_9=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_9
-axis_interconnect_v1_1_17=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_17
-cordic_v6_0_15=$RDI_DATADIR/xsim/ip/cordic_v6_0_15
-axis_register_slice_v1_1_19=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_19
-axis_switch_v1_1_19=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_19
-axi_interconnect_v1_7_16=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_16
-mult_gen_v12_0_15=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_15
-spdif_v2_0_21=$RDI_DATADIR/xsim/ip/spdif_v2_0_21
-v_hscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_13
-ethernet_1_10_25g_v2_3_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_3_3
-xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6
-axi_quad_spi_v3_2_18=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_18
-axi_bram_ctrl_v4_1_1=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_1
-axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
-axi_protocol_checker_v2_0_5=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_5
-axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
-mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7
-ieee802d3_25g_rs_fec_v1_0_13=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_13
-aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
-xtlm=$RDI_DATADIR/xsim/ip/xtlm
-iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
-ieee802d3_clause74_fec_v1_0_4=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_4
-xlconcat_v2_1_3=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_3
-perf_axi_tg_v1_0_8=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_8
-axi_crossbar_v2_1_20=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_20
-tsn_endpoint_ethernet_mac_block_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_4
-v_ycrcb2rgb_v7_1_13=$RDI_DATADIR/xsim/ip/v_ycrcb2rgb_v7_1_13
-xhmc_v1_0_9=$RDI_DATADIR/xsim/ip/xhmc_v1_0_9
-dp_videoaxi4s_bridge_v1_0_0=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_0
-lte_ul_channel_decoder_v4_0_16=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_16
-soft_ecc_proxy_v1_0_0=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_0
-pr_bitstream_monitor_v1_0_1=$RDI_DATADIR/xsim/ip/pr_bitstream_monitor_v1_0_1
-sync_ip=$RDI_DATADIR/xsim/ip/sync_ip
-v_frmbuf_rd_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_1_2
-c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6
-cmac_usplus_v2_6_2=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_6_2
-axi_mcdma_v1_0_5=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_5
-c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6
-g709_fec_v2_4_1=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_1
-lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0
-ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
-fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4
-v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0
-l_ethernet_v2_3_5=$RDI_DATADIR/xsim/ip/l_ethernet_v2_3_5
-microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6
-v_uhdsdi_audio_v2_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_1
-ldpc_v2_0_3=$RDI_DATADIR/xsim/ip/ldpc_v2_0_3
-xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6
-xpm=$RDI_DATADIR/xsim/ip/xpm
-srio_gen2_v4_1_6=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_6
-g975_efec_i4_v1_0_17=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_17
-noc_na_v1_0_0=$RDI_DATADIR/xsim/ip/noc_na_v1_0_0
-roe_framer_v2_0_1=$RDI_DATADIR/xsim/ip/roe_framer_v2_0_1
-xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10
-generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0
-ten_gig_eth_pcs_pma_v6_0_15=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_15
-can_v5_0_22=$RDI_DATADIR/xsim/ip/can_v5_0_22
-av_pat_gen_v1_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_0
-fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1
-lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
-axis_dwidth_converter_v1_1_18=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_18
-lte_rach_detector_v3_1_5=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_5
-xxv_ethernet_v3_0_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v3_0_3
-axi_iic_v2_0_22=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_22
-axi_pcie_v2_9_1=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_1
-util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4
-sim_trig_top_v1_0=$RDI_DATADIR/xsim/ip/sim_trig_top_v1_0
-v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0
-v_tpg_v7_0_13=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_13
-sd_fec_v1_1_3=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_3
-xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6
-lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2
-v_multi_scaler_v1_0_1=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_0_1
-axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0
-advanced_io_wizard_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_0
-mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8
-axi_pcie3_v3_0_9=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_9
-axi_vfifo_ctrl_v2_0_21=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_21
-xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/activehdl/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Sat Mar 18 23:15:11 +0800 2023
+# Generated by export_simulation on Sat Mar 25 22:38:14 CST 2023
 #
 ################################################################################
 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/activehdl/compile.do

@@ -26,10 +26,10 @@ vmap xbip_dsp48_multadd_v3_0_6 activehdl/xbip_dsp48_multadd_v3_0_6
 vmap dds_compiler_v6_0_18 activehdl/dds_compiler_v6_0_18
 
 vlog -work xil_defaultlib  -sv2k12 \
-"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 
 vcom -work xpm -93 \
-"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 
 vcom -work xbip_utils_v3_0_10 -93 \
 "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/activehdl/dds_32b_8b.sh

@@ -9,8 +9,8 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Sat Mar 18 23:15:11 +0800 2023
-# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+# Generated by Vivado on Sat Mar 25 22:38:14 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
@@ -93,11 +93,9 @@ setup()
 map_setup_file()
 {
   file="library.cfg"
-  lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
-  if [[ ($1 != "" && -e $1) ]]; then
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
     lib_map_path="$1"
-  else
-    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
   fi
   if [[ ($lib_map_path != "") ]]; then
     src_file="$lib_map_path/$file"

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/activehdl/file_info.txt

@@ -1,5 +1,5 @@
-xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
 xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
 axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
 xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/ies/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Sat Mar 18 23:15:11 +0800 2023
+# Generated by export_simulation on Sat Mar 25 22:38:14 CST 2023
 #
 ################################################################################
 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/ies/dds_32b_8b.sh

@@ -9,8 +9,8 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Sat Mar 18 23:15:11 +0800 2023
-# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+# Generated by Vivado on Sat Mar 25 22:38:14 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/ies/file_info.txt

@@ -1,5 +1,5 @@
-xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
 xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
 axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
 xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/ies/run.f

@@ -1,8 +1,8 @@
 -makelib ies_lib/xil_defaultlib -sv \
-  "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 -endlib
 -makelib ies_lib/xpm \
-  "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 -endlib
 -makelib ies_lib/xbip_utils_v3_0_10 \
   "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/modelsim/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Sat Mar 18 23:15:11 +0800 2023
+# Generated by export_simulation on Sat Mar 25 22:38:14 CST 2023
 #
 ################################################################################
 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/modelsim/compile.do

@@ -2,10 +2,66 @@ vlib modelsim_lib/work
 vlib modelsim_lib/msim
 
 vlib modelsim_lib/msim/xil_defaultlib
+vlib modelsim_lib/msim/xpm
+vlib modelsim_lib/msim/xbip_utils_v3_0_10
+vlib modelsim_lib/msim/axi_utils_v2_0_6
+vlib modelsim_lib/msim/xbip_pipe_v3_0_6
+vlib modelsim_lib/msim/xbip_bram18k_v3_0_6
+vlib modelsim_lib/msim/mult_gen_v12_0_15
+vlib modelsim_lib/msim/xbip_dsp48_wrapper_v3_0_4
+vlib modelsim_lib/msim/xbip_dsp48_addsub_v3_0_6
+vlib modelsim_lib/msim/xbip_dsp48_multadd_v3_0_6
+vlib modelsim_lib/msim/dds_compiler_v6_0_18
 
 vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+vmap xpm modelsim_lib/msim/xpm
+vmap xbip_utils_v3_0_10 modelsim_lib/msim/xbip_utils_v3_0_10
+vmap axi_utils_v2_0_6 modelsim_lib/msim/axi_utils_v2_0_6
+vmap xbip_pipe_v3_0_6 modelsim_lib/msim/xbip_pipe_v3_0_6
+vmap xbip_bram18k_v3_0_6 modelsim_lib/msim/xbip_bram18k_v3_0_6
+vmap mult_gen_v12_0_15 modelsim_lib/msim/mult_gen_v12_0_15
+vmap xbip_dsp48_wrapper_v3_0_4 modelsim_lib/msim/xbip_dsp48_wrapper_v3_0_4
+vmap xbip_dsp48_addsub_v3_0_6 modelsim_lib/msim/xbip_dsp48_addsub_v3_0_6
+vmap xbip_dsp48_multadd_v3_0_6 modelsim_lib/msim/xbip_dsp48_multadd_v3_0_6
+vmap dds_compiler_v6_0_18 modelsim_lib/msim/dds_compiler_v6_0_18
+
+vlog -work xil_defaultlib -64 -incr -sv \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work xbip_utils_v3_0_10 -64 -93 \
+"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+
+vcom -work axi_utils_v2_0_6 -64 -93 \
+"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+
+vcom -work xbip_pipe_v3_0_6 -64 -93 \
+"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+
+vcom -work xbip_bram18k_v3_0_6 -64 -93 \
+"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+
+vcom -work mult_gen_v12_0_15 -64 -93 \
+"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+
+vcom -work xbip_dsp48_wrapper_v3_0_4 -64 -93 \
+"../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd" \
+
+vcom -work xbip_dsp48_addsub_v3_0_6 -64 -93 \
+"../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd" \
+
+vcom -work xbip_dsp48_multadd_v3_0_6 -64 -93 \
+"../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd" \
+
+vcom -work dds_compiler_v6_0_18 -64 -93 \
+"../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd" \
 
 vcom -work xil_defaultlib -64 -93 \
 "../../../ip/dds_32b_8b/sim/dds_32b_8b.vhd" \
 
 
+vlog -work xil_defaultlib \
+"glbl.v"
+

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/modelsim/dds_32b_8b.sh

@@ -9,8 +9,8 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Sat Mar 18 23:15:11 +0800 2023
-# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+# Generated by Vivado on Sat Mar 25 22:38:14 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
@@ -95,10 +95,11 @@ setup()
 copy_setup_file()
 {
   file="modelsim.ini"
-  if [[ ($1 != "") ]]; then
+  lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+  if [[ ($1 != "" && -e $1) ]]; then
     lib_map_path="$1"
   else
-    lib_map_path="C:/Mentor/CompLib/2019.1.3"
+    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
   fi
   if [[ ($lib_map_path != "") ]]; then
     src_file="$lib_map_path/$file"

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/modelsim/file_info.txt

@@ -1 +1,13 @@
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
+xbip_dsp48_addsub_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_addsub_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd,
+xbip_dsp48_multadd_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_multadd_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd,
+dds_compiler_v6_0_vh_rfs.vhd,vhdl,dds_compiler_v6_0_18,../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd,
 dds_32b_8b.vhd,vhdl,xil_defaultlib,../../../ip/dds_32b_8b/sim/dds_32b_8b.vhd,
+glbl.v,Verilog,xil_defaultlib,glbl.v

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/modelsim/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/modelsim/simulate.do

@@ -1,7 +1,7 @@
 onbreak {quit -f}
 onerror {quit -f}
 
-vsim -voptargs="+acc" -t 1ps -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L dds_compiler_v6_0_18 -L xil_defaultlib -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.dds_32b_8b
+vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L dds_compiler_v6_0_18 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.dds_32b_8b xil_defaultlib.glbl
 
 do {wave.do}
 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/modelsim/wave.do

@@ -1 +1,2 @@
 add wave *
+add wave /glbl/GSR

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/questa/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Sat Mar 18 23:15:11 +0800 2023
+# Generated by export_simulation on Sat Mar 25 22:38:14 CST 2023
 #
 ################################################################################
 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/questa/compile.do

@@ -26,10 +26,10 @@ vmap xbip_dsp48_multadd_v3_0_6 questa_lib/msim/xbip_dsp48_multadd_v3_0_6
 vmap dds_compiler_v6_0_18 questa_lib/msim/dds_compiler_v6_0_18
 
 vlog -work xil_defaultlib -64 -sv \
-"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 
 vcom -work xpm -64 -93 \
-"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 
 vcom -work xbip_utils_v3_0_10 -64 -93 \
 "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/questa/dds_32b_8b.sh

@@ -9,8 +9,8 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Sat Mar 18 23:15:11 +0800 2023
-# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+# Generated by Vivado on Sat Mar 25 22:38:14 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/questa/file_info.txt

@@ -1,5 +1,5 @@
-xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
 xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
 axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
 xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/riviera/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Sat Mar 18 23:15:11 +0800 2023
+# Generated by export_simulation on Sat Mar 25 22:38:14 CST 2023
 #
 ################################################################################
 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/riviera/compile.do

@@ -26,10 +26,10 @@ vmap xbip_dsp48_multadd_v3_0_6 riviera/xbip_dsp48_multadd_v3_0_6
 vmap dds_compiler_v6_0_18 riviera/dds_compiler_v6_0_18
 
 vlog -work xil_defaultlib  -sv2k12 \
-"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 
 vcom -work xpm -93 \
-"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 
 vcom -work xbip_utils_v3_0_10 -93 \
 "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/riviera/dds_32b_8b.sh

@@ -9,8 +9,8 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Sat Mar 18 23:15:11 +0800 2023
-# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+# Generated by Vivado on Sat Mar 25 22:38:14 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/riviera/file_info.txt

@@ -1,5 +1,5 @@
-xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
 xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
 axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
 xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/vcs/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Sat Mar 18 23:15:11 +0800 2023
+# Generated by export_simulation on Sat Mar 25 22:38:14 CST 2023
 #
 ################################################################################
 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/vcs/dds_32b_8b.sh

@@ -9,8 +9,8 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Sat Mar 18 23:15:11 +0800 2023
-# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+# Generated by Vivado on Sat Mar 25 22:38:14 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
@@ -71,11 +71,11 @@ compile()
 {
   # Compile design files
   vlogan -work xil_defaultlib $vlogan_opts -sverilog \
-    "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+    "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
   2>&1 | tee -a vlogan.log
 
   vhdlan -work xpm $vhdlan_opts \
-    "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+    "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vhdlan -work xbip_utils_v3_0_10 $vhdlan_opts \
@@ -182,9 +182,11 @@ create_lib_mappings()
 
   touch $file
 
-  lib_map_path=""
-  if [[ ($1 != "") ]]; then
+  lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+  if [[ ($1 != "" && -e $1) ]]; then
     lib_map_path="$1"
+  else
+    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
   fi
 
   for (( i=0; i<${#design_libs[*]}; i++ )); do

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/vcs/file_info.txt

@@ -1,5 +1,5 @@
-xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
 xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
 axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
 xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/xcelium/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Sat Mar 18 23:15:11 +0800 2023
+# Generated by export_simulation on Sat Mar 25 22:38:14 CST 2023
 #
 ################################################################################
 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/xcelium/dds_32b_8b.sh

@@ -9,8 +9,8 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Sat Mar 18 23:15:11 +0800 2023
-# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+# Generated by Vivado on Sat Mar 25 22:38:14 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/xcelium/file_info.txt

@@ -1,5 +1,5 @@
-xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
 xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
 axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
 xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/xcelium/run.f

@@ -1,8 +1,8 @@
 -makelib xcelium_lib/xil_defaultlib -sv \
-  "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 -endlib
 -makelib xcelium_lib/xpm \
-  "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 -endlib
 -makelib xcelium_lib/xbip_utils_v3_0_10 \
   "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/xsim/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Sat Mar 18 23:15:11 +0800 2023
+# Generated by export_simulation on Sat Mar 25 22:38:14 CST 2023
 #
 ################################################################################
 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/xsim/dds_32b_8b.sh

@@ -9,8 +9,8 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Sat Mar 18 23:15:11 +0800 2023
-# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+# Generated by Vivado on Sat Mar 25 22:38:14 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
@@ -22,7 +22,7 @@
 #*********************************************************************************************************
 
 # Command line options
-xv_boost_lib_path=C:/Xilinx/Vivado/2019.1/tps/boost_1_64_0
+xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0
 xvhdl_opts="--relax"
 
 
@@ -92,7 +92,7 @@ setup()
 copy_setup_file()
 {
   file="xsim.ini"
-  lib_map_path="C:/Xilinx/Vivado/2019.1/data/xsim"
+  lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim"
   if [[ ($1 != "") ]]; then
     lib_map_path="$1"
   fi

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/xsim/elab.opt

@@ -1 +0,0 @@
---relax --debug typical --mt auto -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L dds_compiler_v6_0_18 -L xil_defaultlib -L secureip -L xpm --snapshot dds_32b_8b xil_defaultlib.dds_32b_8b -log elaborate.log

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/dds_32b_8b/xsim/xsim.ini

@@ -1,430 +0,0 @@
-std=$RDI_DATADIR/xsim/vhdl/std
-ieee=$RDI_DATADIR/xsim/vhdl/ieee
-ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
-vl=$RDI_DATADIR/xsim/vhdl/vl
-synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
-secureip=$RDI_DATADIR/xsim/verilog/secureip
-unisim=$RDI_DATADIR/xsim/vhdl/unisim
-unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
-unifast=$RDI_DATADIR/xsim/vhdl/unifast
-unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
-unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
-unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
-simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
-system_cache_v4_0_6=$RDI_DATADIR/xsim/ip/system_cache_v4_0_6
-bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0
-g709_rs_decoder_v2_2_8=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_8
-xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
-mipi_dphy_v4_1_4=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_1_4
-iomodule_v3_1_4=$RDI_DATADIR/xsim/ip/iomodule_v3_1_4
-ieee802d3_50g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_11
-common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
-lte_fft_v2_1_0=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_0
-ieee802d3_50g_rs_fec_v2_0_1=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_1
-convolution_v9_0_14=$RDI_DATADIR/xsim/ip/convolution_v9_0_14
-gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
-v_cfa_v7_0_14=$RDI_DATADIR/xsim/ip/v_cfa_v7_0_14
-axi4svideo_bridge_v1_0_10=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_10
-pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11
-v_vscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_13
-xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6
-gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
-ethernet_1_10_25g_v2_2_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_2_3
-zynq_ultra_ps_e_v3_3_0=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_0
-v_cresample_v4_0_14=$RDI_DATADIR/xsim/ip/v_cresample_v4_0_14
-v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9
-v_scenechange_v1_0_1=$RDI_DATADIR/xsim/ip/v_scenechange_v1_0_1
-hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0
-ahblite_axi_bridge_v3_0_14=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_14
-tri_mode_ethernet_mac_v9_0_14=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_14
-blk_mem_gen_v8_4_3=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_3
-noc_mc_ddr4_phy_v1_0_0=$RDI_DATADIR/xsim/ip/noc_mc_ddr4_phy_v1_0_0
-axi_data_fifo_v2_1_18=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_18
-axi_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_5
-ethernet_1_10_25g_v2_0_5=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_0_5
-compact_gt_v1_0_5=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_5
-axi_gpio_v2_0_21=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_21
-qdma_v3_0_2=$RDI_DATADIR/xsim/ip/qdma_v3_0_2
-viterbi_v9_1_11=$RDI_DATADIR/xsim/ip/viterbi_v9_1_11
-sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2
-ba317=$RDI_DATADIR/xsim/ip/ba317
-xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4
-fifo_generator_v13_2_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_4
-axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14
-vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0
-axi_emc_v3_0_19=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_19
-cmac_v2_5_1=$RDI_DATADIR/xsim/ip/cmac_v2_5_1
-floating_point_v7_1_8=$RDI_DATADIR/xsim/ip/floating_point_v7_1_8
-xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6
-vid_phy_controller_v2_2_3=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_3
-common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
-axi_firewall_v1_0_7=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_7
-util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1
-axis_accelerator_adapter_v2_1_15=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_15
-tmr_comparator_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_2
-sd_fec_v1_0_2=$RDI_DATADIR/xsim/ip/sd_fec_v1_0_2
-tmr_manager_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_4
-tsn_temac_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_4
-usxgmii_v1_0_5=$RDI_DATADIR/xsim/ip/usxgmii_v1_0_5
-lte_dl_channel_encoder_v4_0_0=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v4_0_0
-ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
-lte_3gpp_mimo_decoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_15
-v_uhdsdi_audio_v1_0_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_0_0
-axi4stream_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_5
-cmac_usplus_v2_4_5=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_4_5
-etrnic_v1_1_2=$RDI_DATADIR/xsim/ip/etrnic_v1_1_2
-floating_point_v7_0_16=$RDI_DATADIR/xsim/ip/floating_point_v7_0_16
-axi_dma_v7_1_20=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_20
-jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
-axi_traffic_gen_v3_0_5=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_5
-emb_mem_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_1
-axi_amm_bridge_v1_0_9=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_9
-axi_datamover_v5_1_21=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_21
-v_axi4s_vid_out_v4_0_10=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_10
-jesd204_v7_2_6=$RDI_DATADIR/xsim/ip/jesd204_v7_2_6
-v_letterbox_v1_0_13=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_13
-interlaken_v2_4_3=$RDI_DATADIR/xsim/ip/interlaken_v2_4_3
-uhdsdi_gt_v2_0_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_0
-axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7
-rst_vip_v1_0_3=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_3
-audio_formatter_v1_0_1=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_1
-lte_3gpp_channel_estimator_v2_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_16
-v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13
-g709_fec_v2_3_5=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_5
-xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6
-axi_chip2chip_v5_0_6=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_6
-fc32_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_11
-v_mix_v3_0_3=$RDI_DATADIR/xsim/ip/v_mix_v3_0_3
-multi_channel_25g_rs_fec_v1_0_5=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_5
-in_system_ibert_v1_0_9=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_9
-ethernet_1_10_25g_v2_1_4=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_1_4
-axis_broadcaster_v1_1_18=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_18
-axis_combiner_v1_1_17=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_17
-axi_apb_bridge_v3_0_15=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_15
-displayport_v9_0_1=$RDI_DATADIR/xsim/ip/displayport_v9_0_1
-clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2
-hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1
-axi_register_slice_v2_1_19=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_19
-vid_phy_controller_v2_1_5=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_5
-picxo=$RDI_DATADIR/xsim/ip/picxo
-usxgmii_v1_1_0=$RDI_DATADIR/xsim/ip/usxgmii_v1_1_0
-v_vcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_13
-bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0
-prc_v1_3_2=$RDI_DATADIR/xsim/ip/prc_v1_3_2
-axi_usb2_device_v5_0_20=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_20
-lte_3gpp_mimo_encoder_v4_0_14=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_14
-l_ethernet_v2_5_2=$RDI_DATADIR/xsim/ip/l_ethernet_v2_5_2
-xdma_v4_1_3=$RDI_DATADIR/xsim/ip/xdma_v4_1_3
-axis_vio_v1_0_0=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_0
-c_counter_binary_v12_0_13=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_13
-noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0
-xbip_dsp48_macro_v3_0_17=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_17
-c_accum_v12_0_13=$RDI_DATADIR/xsim/ip/c_accum_v12_0_13
-xbip_multadd_v3_0_14=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_14
-axi_uartlite_v2_0_23=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_23
-noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
-axi_intc_v4_1_13=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_13
-i2s_transmitter_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_3
-pc_cfr_v6_0_8=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_8
-mutex_v2_1_10=$RDI_DATADIR/xsim/ip/mutex_v2_1_10
-c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6
-sid_v8_0_14=$RDI_DATADIR/xsim/ip/sid_v8_0_14
-fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6
-quadsgmii_v3_4_6=$RDI_DATADIR/xsim/ip/quadsgmii_v3_4_6
-microblaze_v11_0_1=$RDI_DATADIR/xsim/ip/microblaze_v11_0_1
-lib_bmg_v1_0_12=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_12
-dds_compiler_v6_0_18=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_18
-me_pl_v1_0=$RDI_DATADIR/xsim/ip/me_pl_v1_0
-gtwizard_ultrascale_v1_7_6=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_6
-axis_clock_converter_v1_1_20=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_20
-nvmeha_v1_0_0=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_0
-tmr_inject_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_3
-axi_mcdma_v1_1_0=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_0
-axi_hwicap_v3_0_23=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_23
-v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0
-v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0
-canfd_v2_0_1=$RDI_DATADIR/xsim/ip/canfd_v2_0_1
-gig_ethernet_pcs_pma_v16_1_6=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_6
-lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2
-ieee802d3_rs_fec_v2_0_5=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_5
-ibert_lib_v1_0_6=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_6
-high_speed_selectio_wiz_v3_4_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_1
-xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6
-fec_5g_common_v1_0_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_1
-tmr_voter_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_2
-hdmi_gt_controller_v1_0_0=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_0
-axi_traffic_gen_v2_0_20=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_20
-flexo_100g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_11
-v_smpte_uhdsdi_v1_0_7=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_7
-xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6
-fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10
-ieee802d3_rs_fec_v1_0_15=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_15
-axis_subset_converter_v1_1_19=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_19
-noc_nmu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_v1_0_0
-duc_ddc_compiler_v3_0_15=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_15
-dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13
-mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0
-ieee802d3_200g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_7
-sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
-mrmac_v1_0_0=$RDI_DATADIR/xsim/ip/mrmac_v1_0_0
-sem_ultra_v3_1_11=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_11
-v_tpg_v8_0_1=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_1
-axi_tft_v2_0_22=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_22
-ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13
-switch_core_top_v1_0_7=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_7
-rama_v1_1_2_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_2_lib
-v_hcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_13
-emb_fifo_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_1
-hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3
-axis_data_fifo_v2_0_1=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_1
-hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0
-rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
-displayport_v8_1_1=$RDI_DATADIR/xsim/ip/displayport_v8_1_1
-axi_mmu_v2_1_17=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_17
-proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13
-pc_cfr_v6_3_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_3_0
-v_osd_v6_0_16=$RDI_DATADIR/xsim/ip/v_osd_v6_0_16
-pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12
-xfft_v9_0_17=$RDI_DATADIR/xsim/ip/xfft_v9_0_17
-axi_cdma_v4_1_19=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_19
-audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0
-lib_fifo_v1_0_13=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_13
-v_enhance_v8_0_15=$RDI_DATADIR/xsim/ip/v_enhance_v8_0_15
-axi_clock_converter_v2_1_18=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_18
-xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0
-emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5
-axi_mm2s_mapper_v1_1_18=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_18
-xfft_v7_2_9=$RDI_DATADIR/xsim/ip/xfft_v7_2_9
-pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
-v_smpte_sdi_v3_0_8=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_8
-fir_compiler_v7_2_12=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_12
-div_gen_v5_1_15=$RDI_DATADIR/xsim/ip/div_gen_v5_1_15
-mdm_v3_2_16=$RDI_DATADIR/xsim/ip/mdm_v3_2_16
-v_axi4s_remap_v1_0_11=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_11
-xxv_ethernet_v2_5_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_5_3
-xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2
-ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
-remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
-pr_axi_shutdown_manager_v1_0_1=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_1
-axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0
-smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
-axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib
-axi_dwidth_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_19
-xlconstant_v1_1_6=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_6
-tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6
-mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
-v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1
-axi_fifo_mm_s_v4_2_1=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_1
-util_idelay_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_1
-rs_toolbox_v9_0_7=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_7
-v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0
-dsp_macro_v1_0_0=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_0
-pc_cfr_v6_2_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_2
-axi_timer_v2_0_21=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_21
-high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1
-axi_sideband_util_v1_0_3=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_3
-sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2
-gmii_to_rgmii_v4_0_7=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_0_7
-xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2
-high_speed_selectio_wiz_v3_5_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_5_1
-axi_msg_v1_0_5=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_5
-axi_ahblite_bridge_v3_0_16=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_16
-v_rgb2ycrcb_v7_1_13=$RDI_DATADIR/xsim/ip/v_rgb2ycrcb_v7_1_13
-v_mix_v4_0_0=$RDI_DATADIR/xsim/ip/v_mix_v4_0_0
-axi_ethernetlite_v3_0_17=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_17
-axi_uart16550_v2_0_21=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_21
-axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0
-vfb_v1_0_13=$RDI_DATADIR/xsim/ip/vfb_v1_0_13
-advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0
-ats_switch_v1_0_2=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_2
-interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4
-axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
-cpri_v8_10_3=$RDI_DATADIR/xsim/ip/cpri_v8_10_3
-c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6
-v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0
-stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
-rld3_pl_v1_0_1=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_1
-ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0
-lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0
-axi_epc_v2_0_22=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_22
-g709_rs_encoder_v2_2_6=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_6
-blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6
-tmr_sem_v1_0_9=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_9
-fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6
-axi_vdma_v6_3_7=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_7
-axis_data_fifo_v1_1_20=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_20
-xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
-axi_ethernet_buffer_v2_0_20=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_20
-rs_encoder_v9_0_15=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_15
-axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
-ta_dma_v1_0_3=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_3
-tcc_encoder_3gpp_v5_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_15
-axi_perf_mon_v5_0_21=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_21
-noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
-sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
-lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2
-v_csc_v1_0_13=$RDI_DATADIR/xsim/ip/v_csc_v1_0_13
-shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0
-lte_fft_v2_0_18=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_18
-gtwizard_ultrascale_v1_6_11=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_11
-amm_axi_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_5
-mii_to_rmii_v2_0_21=$RDI_DATADIR/xsim/ip/mii_to_rmii_v2_0_21
-videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5
-audio_clock_recovery_v1_0=$RDI_DATADIR/xsim/ip/audio_clock_recovery_v1_0
-cmac_v2_4_1=$RDI_DATADIR/xsim/ip/cmac_v2_4_1
-i2s_receiver_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_3
-v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0
-v_demosaic_v1_0_5=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_5
-remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
-microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4
-hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3
-etrnic_v1_0_3=$RDI_DATADIR/xsim/ip/etrnic_v1_0_3
-xfft_v9_1_2=$RDI_DATADIR/xsim/ip/xfft_v9_1_2
-ddr4_pl_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_2
-xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6
-cmac_usplus_v2_5_3=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_5_3
-jesd204c_v4_1_1=$RDI_DATADIR/xsim/ip/jesd204c_v4_1_1
-debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
-axis_protocol_checker_v2_0_3=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_3
-v_frmbuf_wr_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_2
-v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9
-mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4
-lte_dl_channel_encoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_15
-axi_protocol_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_19
-xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
-clk_gen_sim_v1_0_0=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_0
-axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
-microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7
-cmpy_v6_0_17=$RDI_DATADIR/xsim/ip/cmpy_v6_0_17
-cmac_v2_3_5=$RDI_DATADIR/xsim/ip/cmac_v2_3_5
-ieee802d3_400g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_7
-xxv_ethernet_v2_4_5=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_4_5
-axi_timebase_wdt_v3_0_11=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_11
-tcc_decoder_3gppmm_v2_0_18=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_18
-v_deinterlacer_v5_0_13=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_13
-dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16
-axi_fifo_mm_s_v4_1_16=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_16
-processing_system7_vip_v1_0_7=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_7
-g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18
-rs_decoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_16
-c_shift_ram_v12_0_13=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_13
-displayport_v7_0_11=$RDI_DATADIR/xsim/ip/displayport_v7_0_11
-v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0
-v_deinterlacer_v4_0_12=$RDI_DATADIR/xsim/ip/v_deinterlacer_v4_0_12
-sem_v4_1_12=$RDI_DATADIR/xsim/ip/sem_v4_1_12
-xaui_v12_3_6=$RDI_DATADIR/xsim/ip/xaui_v12_3_6
-ten_gig_eth_mac_v15_1_7=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_7
-oddr_v1_0_0=$RDI_DATADIR/xsim/ip/oddr_v1_0_0
-c_addsub_v12_0_13=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_13
-v_ccm_v6_0_15=$RDI_DATADIR/xsim/ip/v_ccm_v6_0_15
-zynq_ultra_ps_e_vip_v1_0_5=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_5
-cic_compiler_v4_0_14=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_14
-c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6
-axi_memory_init_v1_0_0=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_0
-pr_decoupler_v1_0_7=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_7
-timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4
-lte_pucch_receiver_v2_0_16=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_16
-zynq_ultra_ps_e_v3_2_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_3
-v_gamma_lut_v1_0_5=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_5
-bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0
-pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0
-tcc_encoder_3gpplte_v4_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_15
-polar_v1_0_3=$RDI_DATADIR/xsim/ip/polar_v1_0_3
-rxaui_v4_4_6=$RDI_DATADIR/xsim/ip/rxaui_v4_4_6
-xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6
-v_gamma_v7_0_15=$RDI_DATADIR/xsim/ip/v_gamma_v7_0_15
-ernic_v1_0_1=$RDI_DATADIR/xsim/ip/ernic_v1_0_1
-high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3
-mailbox_v2_1_11=$RDI_DATADIR/xsim/ip/mailbox_v2_1_11
-video_frame_crc_v1_0_1=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_1
-axi_sg_v4_1_12=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_12
-ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0
-lmb_bram_if_cntlr_v4_0_16=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_16
-l_ethernet_v2_4_3=$RDI_DATADIR/xsim/ip/l_ethernet_v2_4_3
-dft_v4_1_1=$RDI_DATADIR/xsim/ip/dft_v4_1_1
-rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0
-axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6
-v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0
-stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0
-lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
-uhdsdi_gt_v1_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_3
-pc_cfr_v6_1_4=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_4
-lmb_v10_v3_0_9=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_9
-axis_interconnect_v1_1_17=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_17
-cordic_v6_0_15=$RDI_DATADIR/xsim/ip/cordic_v6_0_15
-axis_register_slice_v1_1_19=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_19
-axis_switch_v1_1_19=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_19
-axi_interconnect_v1_7_16=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_16
-mult_gen_v12_0_15=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_15
-spdif_v2_0_21=$RDI_DATADIR/xsim/ip/spdif_v2_0_21
-v_hscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_13
-ethernet_1_10_25g_v2_3_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_3_3
-xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6
-axi_quad_spi_v3_2_18=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_18
-axi_bram_ctrl_v4_1_1=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_1
-axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
-axi_protocol_checker_v2_0_5=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_5
-axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
-mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7
-ieee802d3_25g_rs_fec_v1_0_13=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_13
-aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
-xtlm=$RDI_DATADIR/xsim/ip/xtlm
-iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
-ieee802d3_clause74_fec_v1_0_4=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_4
-xlconcat_v2_1_3=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_3
-perf_axi_tg_v1_0_8=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_8
-axi_crossbar_v2_1_20=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_20
-tsn_endpoint_ethernet_mac_block_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_4
-v_ycrcb2rgb_v7_1_13=$RDI_DATADIR/xsim/ip/v_ycrcb2rgb_v7_1_13
-xhmc_v1_0_9=$RDI_DATADIR/xsim/ip/xhmc_v1_0_9
-dp_videoaxi4s_bridge_v1_0_0=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_0
-lte_ul_channel_decoder_v4_0_16=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_16
-soft_ecc_proxy_v1_0_0=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_0
-pr_bitstream_monitor_v1_0_1=$RDI_DATADIR/xsim/ip/pr_bitstream_monitor_v1_0_1
-sync_ip=$RDI_DATADIR/xsim/ip/sync_ip
-v_frmbuf_rd_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_1_2
-c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6
-cmac_usplus_v2_6_2=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_6_2
-axi_mcdma_v1_0_5=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_5
-c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6
-g709_fec_v2_4_1=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_1
-lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0
-ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
-fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4
-v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0
-l_ethernet_v2_3_5=$RDI_DATADIR/xsim/ip/l_ethernet_v2_3_5
-microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6
-v_uhdsdi_audio_v2_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_1
-ldpc_v2_0_3=$RDI_DATADIR/xsim/ip/ldpc_v2_0_3
-xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6
-xpm=$RDI_DATADIR/xsim/ip/xpm
-srio_gen2_v4_1_6=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_6
-g975_efec_i4_v1_0_17=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_17
-noc_na_v1_0_0=$RDI_DATADIR/xsim/ip/noc_na_v1_0_0
-roe_framer_v2_0_1=$RDI_DATADIR/xsim/ip/roe_framer_v2_0_1
-xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10
-generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0
-ten_gig_eth_pcs_pma_v6_0_15=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_15
-can_v5_0_22=$RDI_DATADIR/xsim/ip/can_v5_0_22
-av_pat_gen_v1_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_0
-fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1
-lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
-axis_dwidth_converter_v1_1_18=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_18
-lte_rach_detector_v3_1_5=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_5
-xxv_ethernet_v3_0_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v3_0_3
-axi_iic_v2_0_22=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_22
-axi_pcie_v2_9_1=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_1
-util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4
-sim_trig_top_v1_0=$RDI_DATADIR/xsim/ip/sim_trig_top_v1_0
-v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0
-v_tpg_v7_0_13=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_13
-sd_fec_v1_1_3=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_3
-xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6
-lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2
-v_multi_scaler_v1_0_1=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_0_1
-axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0
-advanced_io_wizard_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_0
-mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8
-axi_pcie3_v3_0_9=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_9
-axi_vfifo_ctrl_v2_0_21=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_21
-xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/hop_rom/activehdl/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Sat Mar 18 23:15:13 +0800 2023
+# Generated by export_simulation on Sat Mar 25 22:38:15 CST 2023
 #
 ################################################################################
 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/hop_rom/activehdl/compile.do

@@ -10,10 +10,10 @@ vmap xpm activehdl/xpm
 vmap blk_mem_gen_v8_4_3 activehdl/blk_mem_gen_v8_4_3
 
 vlog -work xil_defaultlib  -sv2k12 \
-"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 
 vcom -work xpm -93 \
-"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 
 vlog -work blk_mem_gen_v8_4_3  -v2k5 \
 "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/hop_rom/activehdl/file_info.txt

@@ -1,5 +1,5 @@
-xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
 blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
 hop_rom.v,verilog,xil_defaultlib,../../../ip/hop_rom/sim/hop_rom.v,
 glbl.v,Verilog,xil_defaultlib,glbl.v

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/hop_rom/activehdl/hop_rom.sh

@@ -9,8 +9,8 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Sat Mar 18 23:15:13 +0800 2023
-# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+# Generated by Vivado on Sat Mar 25 22:38:15 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
@@ -93,11 +93,9 @@ setup()
 map_setup_file()
 {
   file="library.cfg"
-  lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
-  if [[ ($1 != "" && -e $1) ]]; then
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
     lib_map_path="$1"
-  else
-    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
   fi
   if [[ ($lib_map_path != "") ]]; then
     src_file="$lib_map_path/$file"

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/hop_rom/ies/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Sat Mar 18 23:15:13 +0800 2023
+# Generated by export_simulation on Sat Mar 25 22:38:15 CST 2023
 #
 ################################################################################
 

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/hop_rom/ies/file_info.txt

@@ -1,5 +1,5 @@
-xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
 blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
 hop_rom.v,verilog,xil_defaultlib,../../../ip/hop_rom/sim/hop_rom.v,
 glbl.v,Verilog,xil_defaultlib,glbl.v

modules/xc7k410tffg900-2/tx_qpsk/ip/ip_user_files/sim_scripts/hop_rom/ies/hop_rom.sh

@@ -9,8 +9,8 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Sat Mar 18 23:15:13 +0800 2023
-# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+# Generated by Vivado on Sat Mar 25 22:38:15 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #