diff --git a/projects/datalink_814/dl814_k7_cal_coarse/project.tcl b/projects/datalink_814/dl814_k7_cal_coarse/project.tcl index 8c66182e..5e9898bd 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/project.tcl +++ b/projects/datalink_814/dl814_k7_cal_coarse/project.tcl @@ -1,9 +1,9 @@ #***************************************************************************************** # Vivado (TM) v2019.1.3 (64-bit) # -# project.tcl: Tcl script for re-creating project 'dl814_k7' +# project.tcl: Tcl script for re-creating project 'project' # -# Generated by Vivado on Sun Mar 26 00:06:08 CST 2023 +# Generated by Vivado on Sat Apr 01 17:22:07 CST 2023 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -28,14 +28,21 @@ # 3. The following remote source files that were added to the original project:- # # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_manual_ctrl/vio_manual_ctrl.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_rx_pre/ila_rx_pre.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_cal/ila_cal.xci" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_rx/ila_rx.xci" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_tx/ila_tx.xci" -# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_ant_rd/vio_ant_rd.xci" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_rf_rd/vio_rf_rd.xci" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_AntCtrl/ila_AntCtrl.xci" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_rfcontrl/ila_rfcontrl.xci" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_ant_test/vio_ant_test.xci" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_rfcontrl/vio_rfcontrl.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/ram_hop_data/ram_hop_data.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci" # "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci" # "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci" # "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci" @@ -55,9 +62,13 @@ # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_4.v" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/Sisyif.v" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/T_CAL.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/accor_mat_formatting.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/accum_cmplx_mat.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/acorr_cmplx_col_vec.v" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/ad9361_phase_cal_coarse.v" # "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v" # "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_dual.v" +# "/home/josh/Workspace/vivado-git/common/adder_tree_ppl.v" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/adf4371_a.v" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/adf4371_b.v" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/ant_rf_ctrl.v" @@ -69,37 +80,30 @@ # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/fre_caliatt.v" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/mgc_ctrl.v" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/mod2_rom.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_process.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/spatial_filter.v" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/spi_master.v" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/spi_salve.v" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/spi_tx.v" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ipi-bds/system_bd/hdl/system_bd_wrapper.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/tx_pre_process.v" # "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/rtl/tx_qpsk.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/weight_vec_formatting.v" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/system_top.v" -# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe" -# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe" -# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_cal/vio_cal.xci" -# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_rx_pre/ila_rx_pre.xci" -# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_cal/ila_cal.xci" -# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci" -# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci" -# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/ram_hop_data/ram_hop_data.xci" -# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci" -# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci" -# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci" -# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_ant_rd/vio_ant_rd.xci" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/atan2_16b/atan2_16b.xci" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rotate_16b/rotate_16b.xci" # "/home/josh/Workspace/vivado-git/common/ApproxModuli_26bit.v" -# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/accor_mat_formatting.v" -# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/accum_cmplx_mat.v" -# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/acorr_cmplx_col_vec.v" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/ad9361_phase_cal_fine.v" -# "/home/josh/Workspace/vivado-git/common/adder_tree_ppl.v" -# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_process.v" -# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/spatial_filter.v" -# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/weight_vec_formatting.v" +# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe" +# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_cal/vio_cal.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/constraints/k7401t_ad9516_2ad9361_physical.xdc" # "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/constraints/k7410t_ad9516_2ad9361_timing.xdc" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/testbenches/tb_rx_pre.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/testbenches/tb_xpm_cdc_pulse.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/testbenches/tb_tx_pre_process.v" # #***************************************************************************************** @@ -168,7 +172,7 @@ if { $::argc > 0 } { } # Set the directory path for the original project from where this script was exported -set orig_proj_dir "[file normalize "$origin_dir/project/dl814_k7"]" +set orig_proj_dir "[file normalize "$origin_dir/project"]" # Create project create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7k410tffg900-2 @@ -178,6 +182,8 @@ set proj_dir [get_property directory [current_project]] # Set project properties set obj [current_project] +set_property -name "compxlib.modelsim_compiled_library_dir" -value "/home/josh/Software/Xilinx/CompLib/Model/2019.1" -objects $obj +set_property -name "compxlib.vcs_compiled_library_dir" -value "/home/josh/Software/Xilinx/CompLib/VCS/2019.1" -objects $obj set_property -name "corecontainer.enable" -value "1" -objects $obj set_property -name "default_lib" -value "xil_defaultlib" -objects $obj set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj @@ -203,12 +209,15 @@ set_property -name "part" -value "xc7k410tffg900-2" -objects $obj set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "target_simulator" -value "VCS" -objects $obj set_property -name "webtalk.activehdl_export_sim" -value "47" -objects $obj set_property -name "webtalk.ies_export_sim" -value "47" -objects $obj set_property -name "webtalk.modelsim_export_sim" -value "47" -objects $obj +set_property -name "webtalk.modelsim_launch_sim" -value "2" -objects $obj set_property -name "webtalk.questa_export_sim" -value "47" -objects $obj set_property -name "webtalk.riviera_export_sim" -value "47" -objects $obj set_property -name "webtalk.vcs_export_sim" -value "47" -objects $obj +set_property -name "webtalk.vcs_launch_sim" -value "29" -objects $obj set_property -name "webtalk.xsim_export_sim" -value "47" -objects $obj set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj @@ -228,14 +237,21 @@ update_ip_catalog -rebuild set obj [get_filesets sources_1] set files [list \ [file normalize "${origin_dir}/ip/vio_manual_ctrl/vio_manual_ctrl.xci"] \ + [file normalize "${origin_dir}/ip/ila_rx_pre/ila_rx_pre.xci"] \ + [file normalize "${origin_dir}/ip/ila_cal/ila_cal.xci"] \ [file normalize "${origin_dir}/ip/ila_rx/ila_rx.xci"] \ [file normalize "${origin_dir}/ip/ila_tx/ila_tx.xci"] \ - [file normalize "${origin_dir}/ip/vio_ant_rd/vio_ant_rd.xci"] \ [file normalize "${origin_dir}/ip/vio_rf_rd/vio_rf_rd.xci"] \ [file normalize "${origin_dir}/ip/ila_AntCtrl/ila_AntCtrl.xci"] \ [file normalize "${origin_dir}/ip/ila_rfcontrl/ila_rfcontrl.xci"] \ [file normalize "${origin_dir}/ip/vio_ant_test/vio_ant_test.xci"] \ [file normalize "${origin_dir}/ip/vio_rfcontrl/vio_rfcontrl.xci"] \ + [file normalize "${origin_dir}/ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci"] \ + [file normalize "${origin_dir}/ip/rx_pre_process/ram_hop_data/ram_hop_data.xci"] \ + [file normalize "${origin_dir}/ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci"] \ + [file normalize "${origin_dir}/ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci"] \ + [file normalize "${origin_dir}/ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci"] \ + [file normalize "${origin_dir}/ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci"] \ [file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"] \ [file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci"] \ [file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci"] \ @@ -255,9 +271,13 @@ set files [list \ [file normalize "${origin_dir}/rtl/Sisyif_src/R_CAL_4.v"] \ [file normalize "${origin_dir}/rtl/Sisyif_src/Sisyif.v"] \ [file normalize "${origin_dir}/rtl/Sisyif_src/T_CAL.v"] \ + [file normalize "${origin_dir}/rtl/rx_pre_process/accor_mat_formatting.v"] \ + [file normalize "${origin_dir}/rtl/rx_pre_process/accum_cmplx_mat.v"] \ + [file normalize "${origin_dir}/rtl/rx_pre_process/acorr_cmplx_col_vec.v"] \ [file normalize "${origin_dir}/rtl/rx_pre_process/ad9361_phase_cal_coarse.v"] \ [file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v"] \ [file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_dual.v"] \ + [file normalize "${origin_dir}/../../../common/adder_tree_ppl.v"] \ [file normalize "${origin_dir}/rtl/Sisyif_src/adf4371_a.v"] \ [file normalize "${origin_dir}/rtl/Sisyif_src/adf4371_b.v"] \ [file normalize "${origin_dir}/rtl/ant_rf_ctrl.v"] \ @@ -269,35 +289,25 @@ set files [list \ [file normalize "${origin_dir}/rtl/Sisyif_src/fre_caliatt.v"] \ [file normalize "${origin_dir}/rtl/Sisyif_src/mgc_ctrl.v"] \ [file normalize "${origin_dir}/rtl/Sisyif_src/mod2_rom.v"] \ + [file normalize "${origin_dir}/rtl/rx_pre_process/rx_pre_process.v"] \ + [file normalize "${origin_dir}/rtl/rx_pre_process/spatial_filter.v"] \ [file normalize "${origin_dir}/rtl/Sisyif_src/spi_master.v"] \ [file normalize "${origin_dir}/rtl/Sisyif_src/spi_salve.v"] \ [file normalize "${origin_dir}/rtl/Sisyif_src/spi_tx.v"] \ [file normalize "${origin_dir}/ipi-bds/system_bd/hdl/system_bd_wrapper.v"] \ + [file normalize "${origin_dir}/rtl/tx_pre_process.v"] \ [file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/rtl/tx_qpsk.v"] \ + [file normalize "${origin_dir}/rtl/rx_pre_process/weight_vec_formatting.v"] \ [file normalize "${origin_dir}/rtl/system_top.v"] \ - [file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"] \ - [file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"] \ - [file normalize "${origin_dir}/ip/vio_cal/vio_cal.xci"] \ - [file normalize "${origin_dir}/ip/ila_rx_pre/ila_rx_pre.xci"] \ - [file normalize "${origin_dir}/ip/ila_cal/ila_cal.xci"] \ - [file normalize "${origin_dir}/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci"] \ - [file normalize "${origin_dir}/ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci"] \ - [file normalize "${origin_dir}/ip/rx_pre_process/ram_hop_data/ram_hop_data.xci"] \ - [file normalize "${origin_dir}/ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci"] \ - [file normalize "${origin_dir}/ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci"] \ - [file normalize "${origin_dir}/ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci"] \ - [file normalize "${origin_dir}/ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci"] \ + [file normalize "${origin_dir}/ip/vio_ant_rd/vio_ant_rd.xci"] \ [file normalize "${origin_dir}/ip/rx_pre_process/atan2_16b/atan2_16b.xci"] \ [file normalize "${origin_dir}/ip/rx_pre_process/rotate_16b/rotate_16b.xci"] \ [file normalize "${origin_dir}/../../../common/ApproxModuli_26bit.v"] \ - [file normalize "${origin_dir}/rtl/rx_pre_process/accor_mat_formatting.v"] \ - [file normalize "${origin_dir}/rtl/rx_pre_process/accum_cmplx_mat.v"] \ - [file normalize "${origin_dir}/rtl/rx_pre_process/acorr_cmplx_col_vec.v"] \ [file normalize "${origin_dir}/rtl/rx_pre_process/ad9361_phase_cal_fine.v"] \ - [file normalize "${origin_dir}/../../../common/adder_tree_ppl.v"] \ - [file normalize "${origin_dir}/rtl/rx_pre_process/rx_pre_process.v"] \ - [file normalize "${origin_dir}/rtl/rx_pre_process/spatial_filter.v"] \ - [file normalize "${origin_dir}/rtl/rx_pre_process/weight_vec_formatting.v"] \ + [file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"] \ + [file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"] \ + [file normalize "${origin_dir}/ip/vio_cal/vio_cal.xci"] \ + [file normalize "${origin_dir}/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci"] \ ] add_files -norecurse -fileset $obj $files @@ -311,6 +321,24 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } +set file "$origin_dir/ip/ila_rx_pre/ila_rx_pre.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/ip/ila_cal/ila_cal.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + set file "$origin_dir/ip/ila_rx/ila_rx.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] @@ -329,15 +357,6 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/ip/vio_ant_rd/vio_ant_rd.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - set file "$origin_dir/ip/vio_rf_rd/vio_rf_rd.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] @@ -383,6 +402,60 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } +set file "$origin_dir/ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/ip/rx_pre_process/ram_hop_data/ram_hop_data.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + set file "$origin_dir/../../../modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] @@ -469,88 +542,7 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/ip/vio_cal/vio_cal.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/ip/ila_rx_pre/ila_rx_pre.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/ip/ila_cal/ila_cal.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/ip/rx_pre_process/ram_hop_data/ram_hop_data.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci" +set file "$origin_dir/ip/vio_ant_rd/vio_ant_rd.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -577,6 +569,24 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } +set file "$origin_dir/ip/vio_cal/vio_cal.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + # Set 'sources_1' fileset file properties for local files # None @@ -621,13 +631,27 @@ if {[string equal [get_filesets -quiet sim_1] ""]} { # Set 'sim_1' fileset object set obj [get_filesets sim_1] -# Empty (no sources present) +set files [list \ + [file normalize "${origin_dir}/testbenches/tb_rx_pre.v"] \ + [file normalize "${origin_dir}/testbenches/tb_xpm_cdc_pulse.v"] \ + [file normalize "${origin_dir}/testbenches/tb_tx_pre_process.v"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sim_1' fileset file properties for remote files +# None + +# Set 'sim_1' fileset file properties for local files +# None # Set 'sim_1' fileset properties set obj [get_filesets sim_1] -set_property -name "top" -value "system_top" -objects $obj +set_property -name "top" -value "tb_rx_pre" -objects $obj set_property -name "top_auto_set" -value "0" -objects $obj set_property -name "top_lib" -value "xil_defaultlib" -objects $obj +set_property -name "vcs.compile.vlogan.more_options" -value "-v2005 -kdb" -objects $obj +set_property -name "vcs.elaborate.debug_pp" -value "0" -objects $obj +set_property -name "vcs.elaborate.vcs.more_options" -value "-debug_access+all" -objects $obj # Set 'utils_1' fileset object set obj [get_filesets utils_1] diff --git a/projects/datalink_814/dl814_k7_cal_coarse/project/project.runs/impl_1/debug_nets.ltx b/projects/datalink_814/dl814_k7_cal_coarse/project/project.runs/impl_1/debug_nets.ltx index ebf3e7ae..67db85ac 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/project/project.runs/impl_1/debug_nets.ltx +++ b/projects/datalink_814/dl814_k7_cal_coarse/project/project.runs/impl_1/debug_nets.ltx @@ -84,7 +84,7 @@ "portIndex": 3, "nets": [ { - "name": "ant_tr_OBUF", + "name": "ant_tr_orig", "isBus": false } ] @@ -100,7 +100,7 @@ "portIndex": 4, "nets": [ { - "name": "ant_dary_OBUF", + "name": "ant_dary_orig", "isBus": false } ] diff --git a/projects/datalink_814/dl814_k7_cal_coarse/project/project.runs/impl_1/system_top.bit b/projects/datalink_814/dl814_k7_cal_coarse/project/project.runs/impl_1/system_top.bit index aa00e23a..46195fb3 100644 Binary files a/projects/datalink_814/dl814_k7_cal_coarse/project/project.runs/impl_1/system_top.bit and b/projects/datalink_814/dl814_k7_cal_coarse/project/project.runs/impl_1/system_top.bit differ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/project/project.runs/impl_1/system_top.ltx b/projects/datalink_814/dl814_k7_cal_coarse/project/project.runs/impl_1/system_top.ltx index ebf3e7ae..67db85ac 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/project/project.runs/impl_1/system_top.ltx +++ b/projects/datalink_814/dl814_k7_cal_coarse/project/project.runs/impl_1/system_top.ltx @@ -84,7 +84,7 @@ "portIndex": 3, "nets": [ { - "name": "ant_tr_OBUF", + "name": "ant_tr_orig", "isBus": false } ] @@ -100,7 +100,7 @@ "portIndex": 4, "nets": [ { - "name": "ant_dary_OBUF", + "name": "ant_dary_orig", "isBus": false } ] diff --git a/projects/datalink_814/dl814_k7_cal_coarse/project/project.sdk/system_top.hdf b/projects/datalink_814/dl814_k7_cal_coarse/project/project.sdk/system_top.hdf index b23462b5..00cae765 100644 Binary files a/projects/datalink_814/dl814_k7_cal_coarse/project/project.sdk/system_top.hdf and b/projects/datalink_814/dl814_k7_cal_coarse/project/project.sdk/system_top.hdf differ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/rtl/system_top.v b/projects/datalink_814/dl814_k7_cal_coarse/rtl/system_top.v index fbea1ad8..d9583e2f 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/rtl/system_top.v +++ b/projects/datalink_814/dl814_k7_cal_coarse/rtl/system_top.v @@ -392,24 +392,48 @@ system_bd_wrapper u_system_bd_wrapper ///////////////// Phased-Array & RF Synthesizer Control & C2C ////////////////// //////////////////////////////////////////////////////////////////////////////// // antenna & rf interface -wire rf_clk ; -wire rf_en ; -wire rf_data; -wire rf_tr ; -wire rf_dary; -wire rf_dout; +wire rf_clk ; +wire rf_en ; +wire rf_data; +wire rf_tr ; +wire rf_dary; +wire rf_dout; -// output data -assign ant_cin = rf_clk; -// assign ant_din0 = accor_stream_data; // assigned afterwards -assign ant_din1 = rf_data; -assign ant_tr = rf_tr; -assign ant_dary = rf_dary; +// nulling algorithm +wire accor_stream_data; +wire weight_stream_data; + +// buffer output data +reg ant_cin_buf = 'b0; +reg ant_din1_buf = 'b0; +reg ant_tr_buf = 'b0; +reg ant_dary_buf = 'b0; + +assign ant_cin = ant_cin_buf ; +assign ant_din1 = ant_din1_buf; +assign ant_tr = ant_tr_buf ; +assign ant_dary = ant_dary_buf; + +always @(posedge clk_96m) begin + if (ant_rst) begin + ant_cin_buf <= 'b0; + ant_din1_buf <= 'b0; + ant_tr_buf <= 'b0; + ant_dary_buf <= 'b0; + end + else begin + ant_cin_buf <= rf_clk; + ant_din1_buf <= rf_data | accor_stream_data; + ant_tr_buf <= rf_tr; + ant_dary_buf <= rf_dary; + end +end // input data wire ant_dout0_cdc, ant_dout1_cdc; assign rf_dout = ant_dout1_cdc; +assign weight_stream_data = ant_dout1_cdc; xpm_cdc_single u_cdc_ant_dout0 ( @@ -576,14 +600,11 @@ wire [29:0] rx_data_i, rx_data_q; wire hop_start_flag ; wire accor_stream_valid ; -wire accor_stream_data ; -wire weight_stream_data ; +// wire accor_stream_data ; +// wire weight_stream_data ; wire [11:0] rx_data; -assign weight_stream_data = ant_dout1_cdc; -assign ant_din0 = accor_stream_data; - ad9361_rx_map_cmos_dual u_ad9361_1_rx_map ( .clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in