diff --git a/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v b/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v index 61f73017..ea930051 100644 --- a/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v +++ b/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v @@ -194,118 +194,3 @@ ad9361_fifo u_rx_fifo_ch2_q ); endmodule - - -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// _ _ ____ -// | | ___ ___| |__ / ___| __ _ ___ -// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ -// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | -// \___/ \___/|___/_| |_| \____|\__,_|\___/ -// -// Create Date: 2023/02/25 14:56:59 -// Design Name: -// Module Name: tb_ad9361_rx_map_cmos_dual -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -// module tb_ad9361_rx_map_cmos_dual; - -// reg rx_data_clk = 1'b1; -// reg clk_2x_in = 1'b1; -// reg clk_4x_in = 1'b1; -// reg rst = 1'b1; - -// wire clk_in_rst, rx_data_clk_rst; -// assign clk_in_rst = rst; -// assign rx_data_clk_rst = rst; - -// reg rx_frame; -// reg [11:0] rx_data; -// reg rx_fifo_rst = 1'b0; - -// wire [11:0] rx_ch1_i, rx_ch1_q, rx_ch2_i, rx_ch2_q; - -// ad9361_rx_map_cmos_dual u_ad9361_rx_map_cmos_dual -// ( -// .clk_2x_in (clk_2x_in ),// input clk_2x_in -// .clk_in_rst (clk_in_rst ),// input clk_in_rst - -// .rx_data_clk (rx_data_clk ),// input rx_data_clk -// .rx_data_clk_rst (rx_data_clk_rst ),// input rx_data_clk_rst - -// .rx_fifo_rst (rx_fifo_rst ),// input rx_fifo_rst - -// .rx_frame (rx_frame ),// input rx_frame -// .rx_data (rx_data ),// input [11:0] rx_data - -// .rx_ch1_i (rx_ch1_i ),// output [11:0] rx_ch1_i -// .rx_ch1_q (rx_ch1_q ),// output [11:0] rx_ch1_q -// .rx_ch2_i (rx_ch2_i ),// output [11:0] rx_ch2_i -// .rx_ch2_q (rx_ch2_q ) // output [11:0] rx_ch2_q -// ); - -// initial begin -// #102 rst = 1'b0; -// #10000 rx_fifo_rst = 1'b1; -// #100 rx_fifo_rst = 1'b0; -// end - -// always #5 clk_4x_in = ~clk_4x_in; - -// always begin -// #3; -// clk_2x_in = ~clk_2x_in; -// #7; -// end - -// always begin -// #6; -// rx_data_clk = ~rx_data_clk; -// #14; -// end - -// reg [1:0] rx_cnt; - -// always @(posedge clk_4x_in) begin -// if (rst) begin -// rx_cnt <= 'b0; -// end -// else begin -// rx_cnt <= rx_cnt + 1'b1; -// end -// end - -// always @(posedge clk_4x_in) begin -// if (rst) begin -// rx_frame <= 'b0; -// rx_data <= 'b0; -// end -// else begin -// rx_data <= rx_data + 12'd1; - -// case (rx_cnt[1]) -// 1'b0: begin -// rx_frame <= 1'b1; -// end -// 1'd1: begin -// rx_frame <= 1'b0; -// end -// endcase -// end -// end - -// endmodule diff --git a/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_single.v b/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_single.v index 36b56ab1..01272559 100644 --- a/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_single.v +++ b/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_single.v @@ -122,93 +122,3 @@ ad9361_fifo u_rx_fifo_q ); endmodule - - -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// _ _ ____ -// | | ___ ___| |__ / ___| __ _ ___ -// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ -// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | -// \___/ \___/|___/_| |_| \____|\__,_|\___/ -// -// Create Date: 2022/07/01 17:37:27 -// Design Name: -// Module Name: tb_ad9361_rx_map_cmos_single -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - -// module tb_ad9361_rx_map_cmos_single; - -// reg clk_in = 1'b1; -// reg clk_2x_in = 1'b1; -// reg rx_data_clk = 1'b1; -// reg rst = 1'b1; - -// wire clk_in_rst, rx_data_clk_rst; - -// assign clk_in_rst = rst; -// assign rx_data_clk_rst = rst; - -// reg rx_frame = 'b0; -// reg [11:0] rx_data = 'b0; - -// reg rx_fifo_rst = 'b0; - -// wire [11:0] rx_data_i, rx_data_q; - -// ad9361_rx_map_cmos_single u_ad9361_rx_map_cmos_single -// ( -// .clk_in (clk_in ), -// .clk_in_rst (clk_in_rst ), - -// .rx_data_clk (rx_data_clk ), -// .rx_data_clk_rst(rx_data_clk_rst), - -// .rx_fifo_rst (rx_fifo_rst ), - -// .rx_frame (rx_frame ), -// .rx_data (rx_data ), - -// .rx_data_i (rx_data_i ), -// .rx_data_q (rx_data_q ) -// ); - -// initial begin -// #102 rst = 1'b0; -// #1000 rx_fifo_rst = 1'b1; -// #100 rx_fifo_rst = 1'b0; -// end - -// always begin -// #5 clk_2x_in = ~clk_2x_in; -// end - -// always begin -// #3 rx_data_clk = ~rx_data_clk; -// #7 clk_in = ~clk_in; -// end - -// always @(posedge clk_2x_in) begin -// if (rst) begin -// rx_frame <= 'b0; -// rx_data <= 'b0; -// end -// else begin -// rx_frame <= ~rx_frame; -// rx_data <= rx_data + 1'b1; -// end -// end - -// endmodule diff --git a/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_lvds_dual.v b/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_lvds_dual.v index c2a62a11..3141e833 100644 --- a/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_lvds_dual.v +++ b/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_lvds_dual.v @@ -275,120 +275,3 @@ ad9361_fifo u_rx_fifo_ch2_q ); endmodule - - -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2023/02/25 14:56:59 -// Design Name: -// Module Name: tb_ad9361_rx_map_lvds_dual -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -// module tb_ad9361_rx_map_lvds_dual; - -// reg rx_data_clk = 1'b1; -// reg clk_4x_in = 1'b1; -// reg clk_8x_in = 1'b1; -// reg rst = 1'b1; - -// wire clk_in_rst, rx_data_clk_rst; -// assign clk_in_rst = rst; -// assign rx_data_clk_rst = rst; - -// reg rx_frame_p, rx_frame_n; -// reg [5:0] rx_data_p, rx_data_n; -// reg rx_fifo_rst = 1'b0; - -// wire [11:0] rx_ch1_i, rx_ch1_q, rx_ch2_i, rx_ch2_q; - -// ad9361_rx_map_lvds_dual u_ad9361_rx_map_lvds_dual -// ( -// .clk_4x_in (clk_4x_in ),// input clk_4x_in -// .clk_in_rst (clk_in_rst ),// input clk_in_rst - -// .rx_data_clk (rx_data_clk ),// input rx_data_clk -// .rx_data_clk_rst (rx_data_clk_rst ),// input rx_data_clk_rst - -// .rx_fifo_rst (rx_fifo_rst ),// input rx_fifo_rst - -// .rx_frame_p (rx_frame_p ),// input rx_frame_p -// .rx_frame_n (rx_frame_n ),// input rx_frame_n -// .rx_data_p (rx_data_p ),// input [ 5:0] rx_data_p -// .rx_data_n (rx_data_n ),// input [ 5:0] rx_data_n - -// .rx_ch1_i (rx_ch1_i ),// output [11:0] rx_ch1_i -// .rx_ch1_q (rx_ch1_q ),// output [11:0] rx_ch1_q -// .rx_ch2_i (rx_ch2_i ),// output [11:0] rx_ch2_i -// .rx_ch2_q (rx_ch2_q ) // output [11:0] rx_ch2_q -// ); - -// initial begin -// #102 rst = 1'b0; -// #10000 rx_fifo_rst = 1'b1; -// #100 rx_fifo_rst = 1'b0; -// end - -// always #5 clk_8x_in = ~clk_8x_in; - -// always begin -// #3; -// clk_4x_in = ~clk_4x_in; -// #7; -// end - -// always begin -// #23; -// rx_data_clk = ~rx_data_clk; -// #17; -// end - -// reg [2:0] rx_cnt; - -// always @(posedge clk_8x_in) begin -// if (rst) begin -// rx_cnt <= 'b0; -// end -// else begin -// rx_cnt <= rx_cnt + 1'b1; -// end -// end - -// always @(posedge clk_8x_in) begin -// if (rst) begin -// rx_frame_p <= 1'b0; -// rx_frame_n <= 1'b1; -// rx_data_p <= 6'b000000; -// rx_data_n <= 6'b111111; -// end -// else begin -// rx_data_p <= rx_data_p + 12'd1; -// rx_data_n <= ~(rx_data_p + 12'd1); - -// case (rx_cnt[2]) -// 1'b0: begin -// rx_frame_p <= 1'b1; -// rx_frame_n <= 1'b0; -// end -// 1'd1: begin -// rx_frame_p <= 1'b0; -// rx_frame_n <= 1'b1; -// end -// endcase -// end -// end - -// endmodule diff --git a/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_dual.v b/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_dual.v index 87bab2b1..7fb0b8a8 100644 --- a/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_dual.v +++ b/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_dual.v @@ -181,96 +181,3 @@ end endgenerate endmodule - - -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// _ _ ____ -// | | ___ ___| |__ / ___| __ _ ___ -// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ -// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | -// \___/ \___/|___/_| |_| \____|\__,_|\___/ -// -// Create Date: 2023/02/25 14:56:59 -// Design Name: -// Module Name: tb_ad9361_tx_map_cmos_dual -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -// module tb_ad9361_tx_map_cmos_dual; - -// reg tx_data_clk = 1'b1; -// reg clk_2x_in = 1'b1; -// reg rst = 1'b1; - -// wire clk_in_rst, tx_data_clk_rst; - -// assign clk_in_rst = rst; -// assign tx_data_clk_rst = rst; - -// reg [11:0] tx_ch1_i = 'b0; -// reg [11:0] tx_ch1_q = 'b0; -// reg [11:0] tx_ch2_i = 'b0; -// reg [11:0] tx_ch2_q = 'b0; - -// wire clk_out; -// wire tx_frame; -// wire tx_data; - -// ad9361_tx_map_cmos_dual u_ad9361_tx_map_cmos_dual -// ( -// .clk_2x_in (clk_2x_in ), -// .clk_in_rst (clk_in_rst ), - -// .tx_data_clk (tx_data_clk ), -// .tx_data_clk_rst(tx_data_clk_rst), - -// .tx_ch1_i (tx_ch1_i ), -// .tx_ch1_q (tx_ch1_q ), -// .tx_ch2_i (tx_ch2_i ), -// .tx_ch2_q (tx_ch2_q ), - -// .clk_out (clk_out ), -// .tx_frame (tx_frame ), -// .tx_data (tx_data ) -// ); - -// initial begin -// #102 rst = 1'b0; -// end - -// always #5 clk_2x_in = ~clk_2x_in; -// always begin -// #3; -// tx_data_clk = ~tx_data_clk; -// #7; -// end - -// always @(posedge tx_data_clk) begin -// if (tx_data_clk_rst) begin -// tx_ch1_i <= 'b0; -// tx_ch1_q <= 'b0; -// tx_ch2_i <= 'b0; -// tx_ch2_q <= 'b0; -// end -// else begin -// tx_ch1_i <= tx_ch1_i + 12'd1; -// tx_ch1_q <= tx_ch1_q + 12'd2; -// tx_ch2_i <= tx_ch2_i + 12'd3; -// tx_ch2_q <= tx_ch2_q + 12'd4; -// end -// end - -// endmodule diff --git a/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_single.v b/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_single.v index 998e7123..ad614384 100644 --- a/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_single.v +++ b/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_single.v @@ -117,81 +117,3 @@ end endgenerate endmodule - - -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2023/02/25 14:56:59 -// Design Name: -// Module Name: tb_ad9361_tx_map_cmos_single -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -// module tb_ad9361_tx_map_cmos_single; - -// reg clk_in = 1'b1; -// reg tx_data_clk = 1'b1; -// reg rst = 1'b1; - -// wire clk_in_rst, tx_data_clk_rst; - -// assign clk_in_rst = rst; -// assign tx_data_clk_rst = rst; - -// reg [11:0] tx_data_i = 'b0; -// reg [11:0] tx_data_q = 'b0; - -// wire clk_out; -// wire tx_frame; -// wire tx_data; - -// ad9361_tx_map_cmos_single u_ad9361_tx_map_cmos_single -// ( -// .clk_in (clk_in ), -// .clk_in_rst (clk_in_rst ), - -// .tx_data_clk (tx_data_clk ), -// .tx_data_clk_rst (tx_data_clk_rst ), - -// .tx_data_i (tx_data_i ), -// .tx_data_q (tx_data_q ), - -// .clk_out (clk_out ), -// .tx_frame (tx_frame ), -// .tx_data (tx_data ) -// ); - -// initial begin -// #102 rst = 1'b0; -// end - -// always begin -// #3 clk_in = ~clk_in; -// #7 tx_data_clk = ~tx_data_clk; -// end - -// always @(posedge clk_in) begin -// if (rst) begin -// tx_data_i <= 'b0; -// tx_data_q <= 'b0; -// end -// else begin -// tx_data_i <= tx_data_i + 12'd1; -// tx_data_q <= tx_data_q + 12'd2; -// end -// end - -// endmodule diff --git a/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_lvds_dual.v b/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_lvds_dual.v index fbe11903..0775eb88 100644 --- a/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_lvds_dual.v +++ b/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_lvds_dual.v @@ -244,94 +244,3 @@ end endgenerate endmodule - - -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2023/02/25 14:56:59 -// Design Name: -// Module Name: tb_ad9361_tx_map_lvds_dual -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -// module tb_ad9361_tx_map_lvds_dual; - -// reg tx_data_clk = 1'b1; -// reg clk_4x_in = 1'b1; -// reg rst = 1'b1; - -// wire clk_in_rst, tx_data_clk_rst; - -// assign clk_in_rst = rst; -// assign tx_data_clk_rst = rst; - -// reg [11:0] tx_ch1_i = 'b0; -// reg [11:0] tx_ch1_q = 'b0; -// reg [11:0] tx_ch2_i = 'b0; -// reg [11:0] tx_ch2_q = 'b0; - -// wire clk_out_p, clk_out_n; -// wire tx_frame_p, tx_frame_n; -// wire [5:0] tx_data_p, tx_data_n; - -// ad9361_tx_map_lvds_dual u_ad9361_tx_map_lvds_dual -// ( -// .clk_4x_in (clk_4x_in ), // input clk_4x_in -// .clk_in_rst (clk_in_rst ), // input clk_in_rst - -// .tx_data_clk (tx_data_clk ), // input tx_data_clk -// .tx_data_clk_rst (tx_data_clk_rst ), // input tx_data_clk_rst - -// .tx_ch1_i (tx_ch1_i ), // input [11:0] tx_ch1_i -// .tx_ch1_q (tx_ch1_q ), // input [11:0] tx_ch1_q -// .tx_ch2_i (tx_ch2_i ), // input [11:0] tx_ch2_i -// .tx_ch2_q (tx_ch2_q ), // input [11:0] tx_ch2_q - -// .clk_out_p (clk_out_p ), // output clk_out_p -// .clk_out_n (clk_out_n ), // output clk_out_n -// .tx_frame_p (tx_frame_p ), // output tx_frame_p -// .tx_frame_n (tx_frame_n ), // output tx_frame_n -// .tx_data_p (tx_data_p ), // output [ 5:0] tx_data_p -// .tx_data_n (tx_data_n ) // output [ 5:0] tx_data_n -// ); - -// initial begin -// #102 rst = 1'b0; -// end - -// always #5 clk_4x_in = ~clk_4x_in; -// always begin -// #13; -// tx_data_clk = ~tx_data_clk; -// #7; -// end - -// always @(posedge tx_data_clk) begin -// if (tx_data_clk_rst) begin -// tx_ch1_i <= 'b0; -// tx_ch1_q <= 'b0; -// tx_ch2_i <= 'b0; -// tx_ch2_q <= 'b0; -// end -// else begin -// tx_ch1_i <= tx_ch1_i + 12'd1; -// tx_ch1_q <= tx_ch1_q + 12'd2; -// tx_ch2_i <= tx_ch2_i + 12'd3; -// tx_ch2_q <= tx_ch2_q + 12'd4; -// end -// end - -// endmodule diff --git a/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.runs/impl_1/system_top.bit b/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.runs/impl_1/system_top.bit index 57316733..47115a64 100644 Binary files a/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.runs/impl_1/system_top.bit and b/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.runs/impl_1/system_top.bit differ diff --git a/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.sdk/dl814_dj/.cproject b/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.sdk/dl814_dj/.cproject index 3362c6c8..26abdd15 100644 --- a/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.sdk/dl814_dj/.cproject +++ b/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.sdk/dl814_dj/.cproject @@ -1,8 +1,8 @@ - - + + @@ -14,64 +14,64 @@ - - - - - - - + + + + + + + - - - - + + @@ -83,56 +83,56 @@ - - - - - - - + + + + + + + - - @@ -142,20 +142,20 @@ - + - + - + - + - + diff --git a/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.sdk/dl814_dj_bsp/.cproject b/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.sdk/dl814_dj_bsp/.cproject index d0c6f08d..38ab2187 100644 --- a/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.sdk/dl814_dj_bsp/.cproject +++ b/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.sdk/dl814_dj_bsp/.cproject @@ -1,8 +1,8 @@ - - + + diff --git a/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.sdk/system_top.hdf b/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.sdk/system_top.hdf index 7dc61278..3a7c5166 100644 Binary files a/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.sdk/system_top.hdf and b/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.sdk/system_top.hdf differ diff --git a/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.tcl b/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.tcl index 8a9189eb..d48e4130 100644 --- a/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.tcl +++ b/projects/datalink_814/dl814_dj/project/dl814_dj/dl814_dj.tcl @@ -3,7 +3,7 @@ # # dl814_dj.tcl: Tcl script for re-creating project 'dl814_dj' # -# Generated by Vivado on Sat Mar 18 09:24:09 +0800 2023 +# Generated by Vivado on Sun Mar 19 19:18:37 +0800 2023 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -27,23 +27,23 @@ # # 3. The following remote source files that were added to the original project:- # -# "D:/vivado-git/datalink_814/ip/vio_rf_control/vio_rf_control.xci" -# "D:/vivado-git/datalink_814/ip/vio_manual_ctrl/vio_manual_ctrl.xci" -# "D:/vivado-git/datalink_814/ip/ila_ctrl_signal/ila_ctrl_signal.xci" -# "D:/vivado-git/datalink_814/ip/ila_tx_rx/ila_tx_rx.xci" -# "D:/vivado-git/datalink_814/ip/cmpy_18x8/cmpy_18x8.xci" -# "D:/vivado-git/datalink_814/ip/dds_32b_8b/dds_32b_8b.xci" -# "D:/vivado-git/datalink_814/ip/hop_rom/hop_rom.xci" -# "D:/vivado-git/datalink_814/ip/hrc_64_12_025/hrc_64_12_025.xci" -# "D:/vivado-git/datalink_814/ipi-bds/system_bd/system_bd.bd" -# "D:/vivado-git/datalink_814/ip/sig_clk_gen/sig_clk_gen.xci" -# "D:/vivado-git/datalink_814/rtl/rf_control.v" -# "D:/vivado-git/datalink_814/ipi-bds/system_bd/hdl/system_bd_wrapper.v" -# "D:/vivado-git/datalink_814/rtl/tx_qpsk.v" -# "D:/vivado-git/datalink_814/rtl/system_top.v" -# "d:/vivado-git/datalink_814/ip/coe/hrc_64_12_025.coe" -# "d:/vivado-git/datalink_814/ip/coe/sweep_freq.coe" -# "D:/vivado-git/datalink_814/constraints/z7100_ad9528_ad9371.xdc" +# "D:/vivado-git/projects/datalink_814/dl814_dj/ip/vio_rf_control/vio_rf_control.xci" +# "D:/vivado-git/projects/datalink_814/dl814_dj/ip/vio_manual_ctrl/vio_manual_ctrl.xci" +# "D:/vivado-git/projects/datalink_814/dl814_dj/ip/ila_ctrl_signal/ila_ctrl_signal.xci" +# "D:/vivado-git/projects/datalink_814/dl814_dj/ip/ila_tx_rx/ila_tx_rx.xci" +# "D:/vivado-git/projects/datalink_814/dl814_dj/ip/cmpy_18x8/cmpy_18x8.xci" +# "D:/vivado-git/projects/datalink_814/dl814_dj/ip/dds_32b_8b/dds_32b_8b.xci" +# "D:/vivado-git/projects/datalink_814/dl814_dj/ip/hop_rom/hop_rom.xci" +# "D:/vivado-git/projects/datalink_814/dl814_dj/ip/hrc_64_12_025/hrc_64_12_025.xci" +# "D:/vivado-git/projects/datalink_814/dl814_dj/ipi-bds/system_bd/system_bd.bd" +# "D:/vivado-git/projects/datalink_814/dl814_dj/ip/sig_clk_gen/sig_clk_gen.xci" +# "D:/vivado-git/projects/datalink_814/dl814_dj/rtl/rf_control.v" +# "D:/vivado-git/projects/datalink_814/dl814_dj/ipi-bds/system_bd/hdl/system_bd_wrapper.v" +# "D:/vivado-git/projects/datalink_814/dl814_dj/rtl/tx_qpsk.v" +# "D:/vivado-git/projects/datalink_814/dl814_dj/rtl/system_top.v" +# "d:/vivado-git/projects/datalink_814/dl814_dj/ip/coe/hrc_64_12_025.coe" +# "d:/vivado-git/projects/datalink_814/dl814_dj/ip/coe/sweep_freq.coe" +# "D:/vivado-git/projects/datalink_814/dl814_dj/constraints/z7100_ad9528_ad9371.xdc" # #***************************************************************************************** @@ -112,7 +112,7 @@ if { $::argc > 0 } { } # Set the directory path for the original project from where this script was exported -set orig_proj_dir "[file normalize "$origin_dir/project"]" +set orig_proj_dir "[file normalize "$origin_dir/"]" # Create project create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z100ffg900-2 @@ -148,14 +148,14 @@ set_property -name "part" -value "xc7z100ffg900-2" -objects $obj set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj set_property -name "simulator_language" -value "Mixed" -objects $obj -set_property -name "webtalk.activehdl_export_sim" -value "9" -objects $obj -set_property -name "webtalk.ies_export_sim" -value "9" -objects $obj -set_property -name "webtalk.modelsim_export_sim" -value "9" -objects $obj -set_property -name "webtalk.questa_export_sim" -value "9" -objects $obj -set_property -name "webtalk.riviera_export_sim" -value "9" -objects $obj -set_property -name "webtalk.vcs_export_sim" -value "9" -objects $obj -set_property -name "webtalk.xcelium_export_sim" -value "9" -objects $obj -set_property -name "webtalk.xsim_export_sim" -value "9" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "19" -objects $obj +set_property -name "webtalk.ies_export_sim" -value "19" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "19" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "19" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "19" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "19" -objects $obj +set_property -name "webtalk.xcelium_export_sim" -value "10" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "19" -objects $obj set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj # Create 'sources_1' fileset (if not found) @@ -166,27 +166,27 @@ if {[string equal [get_filesets -quiet sources_1] ""]} { # Set 'sources_1' fileset object set obj [get_filesets sources_1] set files [list \ - [file normalize "${origin_dir}/ip/vio_rf_control/vio_rf_control.xci"] \ - [file normalize "${origin_dir}/ip/vio_manual_ctrl/vio_manual_ctrl.xci"] \ - [file normalize "${origin_dir}/ip/ila_ctrl_signal/ila_ctrl_signal.xci"] \ - [file normalize "${origin_dir}/ip/ila_tx_rx/ila_tx_rx.xci"] \ - [file normalize "${origin_dir}/ip/cmpy_18x8/cmpy_18x8.xci"] \ - [file normalize "${origin_dir}/ip/dds_32b_8b/dds_32b_8b.xci"] \ - [file normalize "${origin_dir}/ip/hop_rom/hop_rom.xci"] \ - [file normalize "${origin_dir}/ip/hrc_64_12_025/hrc_64_12_025.xci"] \ - [file normalize "${origin_dir}/ipi-bds/system_bd/system_bd.bd"] \ - [file normalize "${origin_dir}/ip/sig_clk_gen/sig_clk_gen.xci"] \ - [file normalize "${origin_dir}/rtl/rf_control.v"] \ - [file normalize "${origin_dir}/ipi-bds/system_bd/hdl/system_bd_wrapper.v"] \ - [file normalize "${origin_dir}/rtl/tx_qpsk.v"] \ - [file normalize "${origin_dir}/rtl/system_top.v"] \ - [file normalize "${origin_dir}/ip/coe/hrc_64_12_025.coe"] \ - [file normalize "${origin_dir}/ip/coe/sweep_freq.coe"] \ + [file normalize "${origin_dir}/../../ip/vio_rf_control/vio_rf_control.xci"] \ + [file normalize "${origin_dir}/../../ip/vio_manual_ctrl/vio_manual_ctrl.xci"] \ + [file normalize "${origin_dir}/../../ip/ila_ctrl_signal/ila_ctrl_signal.xci"] \ + [file normalize "${origin_dir}/../../ip/ila_tx_rx/ila_tx_rx.xci"] \ + [file normalize "${origin_dir}/../../ip/cmpy_18x8/cmpy_18x8.xci"] \ + [file normalize "${origin_dir}/../../ip/dds_32b_8b/dds_32b_8b.xci"] \ + [file normalize "${origin_dir}/../../ip/hop_rom/hop_rom.xci"] \ + [file normalize "${origin_dir}/../../ip/hrc_64_12_025/hrc_64_12_025.xci"] \ + [file normalize "${origin_dir}/../../ipi-bds/system_bd/system_bd.bd"] \ + [file normalize "${origin_dir}/../../ip/sig_clk_gen/sig_clk_gen.xci"] \ + [file normalize "${origin_dir}/../../rtl/rf_control.v"] \ + [file normalize "${origin_dir}/../../ipi-bds/system_bd/hdl/system_bd_wrapper.v"] \ + [file normalize "${origin_dir}/../../rtl/tx_qpsk.v"] \ + [file normalize "${origin_dir}/../../rtl/system_top.v"] \ + [file normalize "${origin_dir}/../../ip/coe/hrc_64_12_025.coe"] \ + [file normalize "${origin_dir}/../../ip/coe/sweep_freq.coe"] \ ] add_files -norecurse -fileset $obj $files # Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/ip/vio_rf_control/vio_rf_control.xci" +set file "$origin_dir/../../ip/vio_rf_control/vio_rf_control.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -195,7 +195,7 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/ip/vio_manual_ctrl/vio_manual_ctrl.xci" +set file "$origin_dir/../../ip/vio_manual_ctrl/vio_manual_ctrl.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -204,7 +204,7 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/ip/ila_ctrl_signal/ila_ctrl_signal.xci" +set file "$origin_dir/../../ip/ila_ctrl_signal/ila_ctrl_signal.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -213,7 +213,7 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/ip/ila_tx_rx/ila_tx_rx.xci" +set file "$origin_dir/../../ip/ila_tx_rx/ila_tx_rx.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -222,7 +222,7 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/ip/cmpy_18x8/cmpy_18x8.xci" +set file "$origin_dir/../../ip/cmpy_18x8/cmpy_18x8.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -231,7 +231,7 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/ip/dds_32b_8b/dds_32b_8b.xci" +set file "$origin_dir/../../ip/dds_32b_8b/dds_32b_8b.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -240,7 +240,7 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/ip/hop_rom/hop_rom.xci" +set file "$origin_dir/../../ip/hop_rom/hop_rom.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -249,7 +249,7 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/ip/hrc_64_12_025/hrc_64_12_025.xci" +set file "$origin_dir/../../ip/hrc_64_12_025/hrc_64_12_025.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -258,12 +258,12 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/ipi-bds/system_bd/system_bd.bd" +set file "$origin_dir/../../ipi-bds/system_bd/system_bd.bd" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "registered_with_manager" -value "1" -objects $file_obj -set file "$origin_dir/ip/sig_clk_gen/sig_clk_gen.xci" +set file "$origin_dir/../../ip/sig_clk_gen/sig_clk_gen.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -289,9 +289,9 @@ if {[string equal [get_filesets -quiet constrs_1] ""]} { set obj [get_filesets constrs_1] # Add/Import constrs file and set constrs file properties -set file "[file normalize "$origin_dir/constraints/z7100_ad9528_ad9371.xdc"]" +set file "[file normalize "$origin_dir/../../constraints/z7100_ad9528_ad9371.xdc"]" set file_added [add_files -norecurse -fileset $obj [list $file]] -set file "$origin_dir/constraints/z7100_ad9528_ad9371.xdc" +set file "$origin_dir/../../constraints/z7100_ad9528_ad9371.xdc" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] set_property -name "file_type" -value "XDC" -objects $file_obj diff --git a/projects/datalink_814/dl814_dj/rtl/system_top.v b/projects/datalink_814/dl814_dj/rtl/system_top.v index dad469a8..5c468289 100644 --- a/projects/datalink_814/dl814_dj/rtl/system_top.v +++ b/projects/datalink_814/dl814_dj/rtl/system_top.v @@ -351,7 +351,8 @@ wire [ 3:0] bb_rshift ; tx_qpsk #( .DATA_WIDTH (16 ), - .CLK_FREQ (122880000 ) + .CLK_FREQ (122880000 ), + .SQUARE_INTERP (32 ) ) u_tx_qpsk ( .clk (sys_clk ), // input clk diff --git a/projects/datalink_814/dl814_k7/constraints/k7401t_ad9516_2ad9361_physical.xdc b/projects/datalink_814/dl814_k7/constraints/k7401t_ad9516_2ad9361_physical.xdc index 368f74e4..99382e87 100644 --- a/projects/datalink_814/dl814_k7/constraints/k7401t_ad9516_2ad9361_physical.xdc +++ b/projects/datalink_814/dl814_k7/constraints/k7401t_ad9516_2ad9361_physical.xdc @@ -61,7 +61,7 @@ set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS18} [get_ports ad9361_ set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_reset_b ] ;# B9361_1_RESETB set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_en_agc ] ;# B9361_1_EN_AGC -set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_enbale ] ;# B9361_1_ENABLE +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_enable ] ;# B9361_1_ENABLE set_property -dict {PACKAGE_PIN A27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_txnrx ] ;# B9361_1_TXNRX set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[0] ] ;# B9361_1_CTRL_IN0 @@ -117,7 +117,7 @@ set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports ad9361_ set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_reset_b ] ;# B9361_2_RESETB set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS18} [get_ports ad9361_2_en_agc ] ;# B9361_2_EN_AGC -set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports ad9361_2_enbale ] ;# B9361_2_ENABLE +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports ad9361_2_enable ] ;# B9361_2_ENABLE set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_txnrx ] ;# B9361_2_TXNRX set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[0] ] ;# B9361_2_CTRL_IN0 diff --git a/projects/datalink_814/dl814_k7/ip/fifo_AntCtrl.xcix b/projects/datalink_814/dl814_k7/ip/ant_rf_interface/fifo_AntCtrl.xcix similarity index 98% rename from projects/datalink_814/dl814_k7/ip/fifo_AntCtrl.xcix rename to projects/datalink_814/dl814_k7/ip/ant_rf_interface/fifo_AntCtrl.xcix index 27a27296..22dc032b 100644 Binary files a/projects/datalink_814/dl814_k7/ip/fifo_AntCtrl.xcix and b/projects/datalink_814/dl814_k7/ip/ant_rf_interface/fifo_AntCtrl.xcix differ diff --git a/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx.xcix b/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx.xcix new file mode 100644 index 00000000..72d5fef8 Binary files /dev/null and b/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx.xcix differ diff --git a/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx.xcix b/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx.xcix new file mode 100644 index 00000000..499d5b77 Binary files /dev/null and b/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx.xcix differ diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/fifo_AntCtrl/fifo_AntCtrl_sim_netlist.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/fifo_AntCtrl/fifo_AntCtrl_sim_netlist.v index 545c5234..ab7411da 100644 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/fifo_AntCtrl/fifo_AntCtrl_sim_netlist.v +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/fifo_AntCtrl/fifo_AntCtrl_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:33:47 2023 +// Date : Sat Mar 18 23:33:46 2023 // Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.v +// Command : write_verilog -force -mode funcsim -rename_top fifo_AntCtrl -prefix +// fifo_AntCtrl_ fifo_AntCtrl_sim_netlist.v // Design : fifo_AntCtrl // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -604,8 +604,8 @@ module fifo_AntCtrl endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) -(* INV_DEF_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_cdc_async_rst" *) (* RST_ACTIVE_HIGH = "1" *) -(* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* xpm_cdc = "ASYNC_RST" *) +(* INV_DEF_VAL = "1'b1" *) (* RST_ACTIVE_HIGH = "1" *) (* VERSION = "0" *) +(* XPM_MODULE = "TRUE" *) (* xpm_cdc = "ASYNC_RST" *) module fifo_AntCtrl_xpm_cdc_async_rst (src_arst, dest_clk, @@ -683,10 +683,9 @@ module fifo_AntCtrl_xpm_cdc_async_rst__2 .Q(arststages_ff[1])); endmodule -(* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) -(* REG_OUTPUT = "1" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) -(* VERSION = "0" *) (* WIDTH = "10" *) (* XPM_MODULE = "TRUE" *) -(* xpm_cdc = "GRAY" *) +(* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) (* REG_OUTPUT = "1" *) +(* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) +(* WIDTH = "10" *) (* XPM_MODULE = "TRUE" *) (* xpm_cdc = "GRAY" *) module fifo_AntCtrl_xpm_cdc_gray (src_clk, src_in_bin, @@ -1599,9 +1598,9 @@ module fifo_AntCtrl_xpm_cdc_gray__2 .R(1'b0)); endmodule -(* DEST_SYNC_FF = "4" *) (* INIT_SYNC_FF = "0" *) (* ORIG_REF_NAME = "xpm_cdc_single" *) -(* SIM_ASSERT_CHK = "0" *) (* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) -(* XPM_MODULE = "TRUE" *) (* xpm_cdc = "SINGLE" *) +(* DEST_SYNC_FF = "4" *) (* INIT_SYNC_FF = "0" *) (* SIM_ASSERT_CHK = "0" *) +(* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) +(* xpm_cdc = "SINGLE" *) module fifo_AntCtrl_xpm_cdc_single (src_clk, src_in, @@ -1711,7 +1710,6 @@ module fifo_AntCtrl_xpm_cdc_single__2 .R(1'b0)); endmodule -(* ORIG_REF_NAME = "clk_x_pntrs" *) module fifo_AntCtrl_clk_x_pntrs (v1_reg, v1_reg_0, @@ -1853,7 +1851,6 @@ module fifo_AntCtrl_clk_x_pntrs .src_in_bin(\src_gray_ff_reg[9] )); endmodule -(* ORIG_REF_NAME = "compare" *) module fifo_AntCtrl_compare (comp1, v1_reg); @@ -2057,7 +2054,6 @@ module fifo_AntCtrl_compare_2 .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0[4]})); endmodule -(* ORIG_REF_NAME = "dmem" *) module fifo_AntCtrl_dmem (dout, wr_clk, @@ -3244,7 +3240,6 @@ module fifo_AntCtrl_dmem .S(Q[8])); endmodule -(* ORIG_REF_NAME = "fifo_generator_ramfifo" *) module fifo_AntCtrl_fifo_generator_ramfifo (wr_rst_busy, AR, @@ -3390,7 +3385,6 @@ module fifo_AntCtrl_fifo_generator_ramfifo .wr_rst_busy(wr_rst_busy)); endmodule -(* ORIG_REF_NAME = "fifo_generator_top" *) module fifo_AntCtrl_fifo_generator_top (wr_rst_busy, AR, @@ -3508,7 +3502,7 @@ endmodule (* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "10" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) -(* C_WR_RESPONSE_LATENCY = "1" *) (* ORIG_REF_NAME = "fifo_generator_v13_2_4" *) +(* C_WR_RESPONSE_LATENCY = "1" *) module fifo_AntCtrl_fifo_generator_v13_2_4 (backup, backup_marker, @@ -4528,7 +4522,6 @@ module fifo_AntCtrl_fifo_generator_v13_2_4 .wr_rst_busy(wr_rst_busy)); endmodule -(* ORIG_REF_NAME = "fifo_generator_v13_2_4_synth" *) module fifo_AntCtrl_fifo_generator_v13_2_4_synth (wr_rst_busy, AR, @@ -4579,7 +4572,6 @@ module fifo_AntCtrl_fifo_generator_v13_2_4_synth .wr_rst_busy(wr_rst_busy)); endmodule -(* ORIG_REF_NAME = "memory" *) module fifo_AntCtrl_memory (dout, wr_clk, @@ -4682,7 +4674,6 @@ module fifo_AntCtrl_memory .wr_clk(wr_clk)); endmodule -(* ORIG_REF_NAME = "rd_bin_cntr" *) module fifo_AntCtrl_rd_bin_cntr (v1_reg, Q, @@ -5045,7 +5036,6 @@ module fifo_AntCtrl_rd_bin_cntr .O(v1_reg_0[4])); endmodule -(* ORIG_REF_NAME = "rd_logic" *) module fifo_AntCtrl_rd_logic (empty, Q, @@ -5090,7 +5080,6 @@ module fifo_AntCtrl_rd_logic .v1_reg_0(\c1/v1_reg )); endmodule -(* ORIG_REF_NAME = "rd_status_flags_as" *) module fifo_AntCtrl_rd_status_flags_as (empty, E, @@ -5158,7 +5147,6 @@ module fifo_AntCtrl_rd_status_flags_as .Q(ram_empty_i)); endmodule -(* ORIG_REF_NAME = "reset_blk_ramfifo" *) module fifo_AntCtrl_reset_blk_ramfifo (AR, \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 , @@ -5382,7 +5370,6 @@ module fifo_AntCtrl_reset_blk_ramfifo .src_arst(rst)); endmodule -(* ORIG_REF_NAME = "wr_bin_cntr" *) module fifo_AntCtrl_wr_bin_cntr (ram_full_fb_i_reg, Q, @@ -5955,7 +5942,6 @@ module fifo_AntCtrl_wr_bin_cntr .Q(\gic0.gc0.count_reg[9]_0 [9])); endmodule -(* ORIG_REF_NAME = "wr_logic" *) module fifo_AntCtrl_wr_logic (full, ram_full_fb_i_reg, @@ -6079,7 +6065,6 @@ module fifo_AntCtrl_wr_logic .wr_en(wr_en)); endmodule -(* ORIG_REF_NAME = "wr_status_flags_as" *) module fifo_AntCtrl_wr_status_flags_as (full, out, diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/fifo_AntCtrl/fifo_AntCtrl_sim_netlist.vhdl b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/fifo_AntCtrl/fifo_AntCtrl_sim_netlist.vhdl index b7d8709f..f84c511d 100644 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/fifo_AntCtrl/fifo_AntCtrl_sim_netlist.vhdl +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/fifo_AntCtrl/fifo_AntCtrl_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:33:47 2023 +-- Date : Sat Mar 18 23:33:46 2023 -- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.vhdl +-- Command : write_vhdl -force -mode funcsim -rename_top fifo_AntCtrl -prefix +-- fifo_AntCtrl_ fifo_AntCtrl_sim_netlist.vhdl -- Design : fifo_AntCtrl -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -28,8 +28,6 @@ entity fifo_AntCtrl_xpm_cdc_async_rst is attribute INIT_SYNC_FF of fifo_AntCtrl_xpm_cdc_async_rst : entity is 0; attribute INV_DEF_VAL : string; attribute INV_DEF_VAL of fifo_AntCtrl_xpm_cdc_async_rst : entity is "1'b1"; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_xpm_cdc_async_rst : entity is "xpm_cdc_async_rst"; attribute RST_ACTIVE_HIGH : integer; attribute RST_ACTIVE_HIGH of fifo_AntCtrl_xpm_cdc_async_rst : entity is 1; attribute VERSION : integer; @@ -165,8 +163,6 @@ entity fifo_AntCtrl_xpm_cdc_gray is attribute DEST_SYNC_FF of fifo_AntCtrl_xpm_cdc_gray : entity is 2; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of fifo_AntCtrl_xpm_cdc_gray : entity is 0; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_xpm_cdc_gray : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of fifo_AntCtrl_xpm_cdc_gray : entity is 1; attribute SIM_ASSERT_CHK : integer; @@ -1401,8 +1397,6 @@ entity fifo_AntCtrl_xpm_cdc_single is attribute DEST_SYNC_FF of fifo_AntCtrl_xpm_cdc_single : entity is 4; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of fifo_AntCtrl_xpm_cdc_single : entity is 0; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_xpm_cdc_single : entity is "xpm_cdc_single"; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of fifo_AntCtrl_xpm_cdc_single : entity is 0; attribute SRC_INPUT_REG : integer; @@ -1565,8 +1559,6 @@ entity fifo_AntCtrl_compare is comp1 : out STD_LOGIC; v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_compare : entity is "compare"; end fifo_AntCtrl_compare; architecture STRUCTURE of fifo_AntCtrl_compare is @@ -1851,8 +1843,6 @@ entity fifo_AntCtrl_dmem is rd_clk : in STD_LOGIC; AR : in STD_LOGIC_VECTOR ( 0 to 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_dmem : entity is "dmem"; end fifo_AntCtrl_dmem; architecture STRUCTURE of fifo_AntCtrl_dmem is @@ -3137,8 +3127,6 @@ entity fifo_AntCtrl_rd_bin_cntr is rd_clk : in STD_LOGIC; AR : in STD_LOGIC_VECTOR ( 0 to 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_rd_bin_cntr : entity is "rd_bin_cntr"; end fifo_AntCtrl_rd_bin_cntr; architecture STRUCTURE of fifo_AntCtrl_rd_bin_cntr is @@ -3637,8 +3625,6 @@ entity fifo_AntCtrl_wr_bin_cntr is wr_clk : in STD_LOGIC; AR : in STD_LOGIC_VECTOR ( 0 to 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_wr_bin_cntr : entity is "wr_bin_cntr"; end fifo_AntCtrl_wr_bin_cntr; architecture STRUCTURE of fifo_AntCtrl_wr_bin_cntr is @@ -4333,8 +4319,6 @@ entity fifo_AntCtrl_clk_x_pntrs is rd_clk : in STD_LOGIC; \src_gray_ff_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_clk_x_pntrs : entity is "clk_x_pntrs"; end fifo_AntCtrl_clk_x_pntrs; architecture STRUCTURE of fifo_AntCtrl_clk_x_pntrs is @@ -4523,8 +4507,6 @@ entity fifo_AntCtrl_memory is rd_clk : in STD_LOGIC; AR : in STD_LOGIC_VECTOR ( 0 to 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_memory : entity is "memory"; end fifo_AntCtrl_memory; architecture STRUCTURE of fifo_AntCtrl_memory is @@ -4571,8 +4553,6 @@ entity fifo_AntCtrl_rd_status_flags_as is AR : in STD_LOGIC_VECTOR ( 0 to 0 ); rd_en : in STD_LOGIC ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_rd_status_flags_as : entity is "rd_status_flags_as"; end fifo_AntCtrl_rd_status_flags_as; architecture STRUCTURE of fifo_AntCtrl_rd_status_flags_as is @@ -4653,8 +4633,6 @@ entity fifo_AntCtrl_reset_blk_ramfifo is wr_clk : in STD_LOGIC; rd_clk : in STD_LOGIC ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_reset_blk_ramfifo : entity is "reset_blk_ramfifo"; end fifo_AntCtrl_reset_blk_ramfifo; architecture STRUCTURE of fifo_AntCtrl_reset_blk_ramfifo is @@ -4958,8 +4936,6 @@ entity fifo_AntCtrl_wr_status_flags_as is wr_en : in STD_LOGIC; ram_full_fb_i_reg_1 : in STD_LOGIC ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_wr_status_flags_as : entity is "wr_status_flags_as"; end fifo_AntCtrl_wr_status_flags_as; architecture STRUCTURE of fifo_AntCtrl_wr_status_flags_as is @@ -5041,8 +5017,6 @@ entity fifo_AntCtrl_rd_logic is rd_en : in STD_LOGIC; WR_PNTR_RD : in STD_LOGIC_VECTOR ( 9 downto 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_rd_logic : entity is "rd_logic"; end fifo_AntCtrl_rd_logic; architecture STRUCTURE of fifo_AntCtrl_rd_logic is @@ -5106,8 +5080,6 @@ entity fifo_AntCtrl_wr_logic is ram_full_fb_i_reg_5 : in STD_LOGIC; AR : in STD_LOGIC_VECTOR ( 0 to 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_wr_logic : entity is "wr_logic"; end fifo_AntCtrl_wr_logic; architecture STRUCTURE of fifo_AntCtrl_wr_logic is @@ -5172,8 +5144,6 @@ entity fifo_AntCtrl_fifo_generator_ramfifo is wr_en : in STD_LOGIC; rd_en : in STD_LOGIC ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo"; end fifo_AntCtrl_fifo_generator_ramfifo; architecture STRUCTURE of fifo_AntCtrl_fifo_generator_ramfifo is @@ -5316,8 +5286,6 @@ entity fifo_AntCtrl_fifo_generator_top is wr_en : in STD_LOGIC; rd_en : in STD_LOGIC ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_fifo_generator_top : entity is "fifo_generator_top"; end fifo_AntCtrl_fifo_generator_top; architecture STRUCTURE of fifo_AntCtrl_fifo_generator_top is @@ -5355,8 +5323,6 @@ entity fifo_AntCtrl_fifo_generator_v13_2_4_synth is wr_en : in STD_LOGIC; rd_en : in STD_LOGIC ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_fifo_generator_v13_2_4_synth : entity is "fifo_generator_v13_2_4_synth"; end fifo_AntCtrl_fifo_generator_v13_2_4_synth; architecture STRUCTURE of fifo_AntCtrl_fifo_generator_v13_2_4_synth is @@ -6018,8 +5984,6 @@ entity fifo_AntCtrl_fifo_generator_v13_2_4 is attribute C_WR_PNTR_WIDTH_WRCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 4; attribute C_WR_RESPONSE_LATENCY : integer; attribute C_WR_RESPONSE_LATENCY of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is "fifo_generator_v13_2_4"; end fifo_AntCtrl_fifo_generator_v13_2_4; architecture STRUCTURE of fifo_AntCtrl_fifo_generator_v13_2_4 is diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/fifo_AntCtrl/fifo_AntCtrl_stub.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/fifo_AntCtrl/fifo_AntCtrl_stub.v index 36a25cc7..c7489e78 100644 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/fifo_AntCtrl/fifo_AntCtrl_stub.v +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/fifo_AntCtrl/fifo_AntCtrl_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:33:47 2023 +// Date : Sat Mar 18 23:33:46 2023 // Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.v +// Command : write_verilog -force -mode synth_stub -rename_top fifo_AntCtrl -prefix +// fifo_AntCtrl_ fifo_AntCtrl_stub.v // Design : fifo_AntCtrl // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/fifo_AntCtrl/fifo_AntCtrl_stub.vhdl b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/fifo_AntCtrl/fifo_AntCtrl_stub.vhdl index 294c6912..efc3aa61 100644 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/fifo_AntCtrl/fifo_AntCtrl_stub.vhdl +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/fifo_AntCtrl/fifo_AntCtrl_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:33:47 2023 +-- Date : Sat Mar 18 23:33:46 2023 -- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.vhdl +-- Command : write_vhdl -force -mode synth_stub -rename_top fifo_AntCtrl -prefix +-- fifo_AntCtrl_ fifo_AntCtrl_stub.vhdl -- Design : fifo_AntCtrl -- Purpose : Stub declaration of top-level module interface -- Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx.v new file mode 100644 index 00000000..880b5682 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx.v @@ -0,0 +1,85 @@ + +// file: selectio_lvds_rx.v +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "selectio_lvds_rx,selectio_wiz_v5_1_13,{component_name=selectio_lvds_rx,bus_dir=INPUTS,bus_sig_type=SINGLE,bus_io_std=LVCMOS33,use_serialization=false,use_phase_detector=false,serialization_factor=4,enable_bitslip=false,enable_train=false,system_data_width=2,bus_in_delay=NONE,bus_out_delay=NONE,clk_sig_type=SINGLE,clk_io_std=LVCMOS18,clk_buf=BUFIO2,active_edge=RISING,clk_delay=NONE,selio_bus_in_delay=NONE,selio_bus_out_delay=NONE,selio_clk_buf=MMCM,selio_active_edge=SDR,selio_ddr_alignment=SAME_EDGE_PIPELINED,selio_oddr_alignment=SAME_EDGE,ddr_alignment=C0,selio_interface_type=NETWORKING,interface_type=NETWORKING,selio_bus_in_tap=0,selio_bus_out_tap=0,selio_clk_io_std=LVCMOS33,selio_clk_sig_type=SINGLE}" *) + +module selectio_lvds_rx + // width of the data for the system + #(parameter SYS_W = 2, + // width of the data for the device + parameter DEV_W = 2) + ( + // From the system into the device + input [SYS_W-1:0] data_in_from_pins, + output [DEV_W-1:0] data_in_to_device, + input clk_in, // Fast clock input from PLL/MMCM + input io_reset); + + + selectio_lvds_rx_selectio_wiz + #( + .SYS_W(SYS_W), + .DEV_W(DEV_W) + ) + inst + ( + .data_in_from_pins(data_in_from_pins), + .data_in_to_device(data_in_to_device), + .clk_in(clk_in), + .io_reset(io_reset) +); + +endmodule + diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx.veo b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx.veo new file mode 100644 index 00000000..6f4444f8 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx.veo @@ -0,0 +1,67 @@ + +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. + + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +// User NOTES: +//None + + selectio_lvds_rx + instance_name + ( + .data_in_from_pins(data_in_from_pins), // input [1:0] data_in_from_pins + .data_in_to_device(data_in_to_device), // output [1:0] data_in_to_device + .clk_in(clk_in), // input clk_in + .io_reset(io_reset) // input io_reset +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v new file mode 100644 index 00000000..5f3e4aa0 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v @@ -0,0 +1,115 @@ + +// file: selectio_lvds_rx_selectio_wiz.v +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +module selectio_lvds_rx_selectio_wiz + // width of the data for the system + #(parameter SYS_W = 2, + // width of the data for the device + parameter DEV_W = 2) + ( + // From the system into the device + input [SYS_W-1:0] data_in_from_pins, + output [DEV_W-1:0] data_in_to_device, + input clk_in, // Fast clock input from PLL/MMCM + input io_reset); + wire clock_enable = 1'b1; + // Signal declarations + ////------------------------------ + // After the buffer + wire [SYS_W-1:0] data_in_from_pins_int; + // Between the delay and serdes + wire [SYS_W-1:0] data_in_from_pins_delay; + // Create the clock logic + + + assign clk_in_int_buf = clk_in; // clock coming from MMCM + + // We have multiple bits- step over every bit, instantiating the required elements + genvar pin_count; + generate for (pin_count = 0; pin_count < SYS_W; pin_count = pin_count + 1) begin: pins + // Instantiate the buffers + ////------------------------------ + // Instantiate a buffer for every bit of the data bus + IBUF + #(.IOSTANDARD ("LVCMOS33")) + ibuf_inst + (.I (data_in_from_pins [pin_count]), + .O (data_in_from_pins_int[pin_count])); + + // Pass through the delay + ////------------------------------- + assign data_in_from_pins_delay[pin_count] = data_in_from_pins_int[pin_count]; + + // Connect the delayed data to the fabric + ////-------------------------------------- + + // Pack the registers into the IOB + + wire data_in_to_device_int; + (* IOB = "true" *) + FDRE fdre_in_inst + (.D (data_in_from_pins_delay[pin_count]), + .C (clk_in_int_buf), + .CE (clock_enable), + .R (io_reset), + .Q (data_in_to_device_int) + ); + assign data_in_to_device[pin_count] = data_in_to_device_int; + end + endgenerate + +//// NO ODELAY + +endmodule diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_sim_netlist.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_sim_netlist.v new file mode 100644 index 00000000..925586ae --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_sim_netlist.v @@ -0,0 +1,168 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +// Date : Sun Mar 19 18:25:55 2023 +// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.v +// Design : selectio_lvds_rx +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* DEV_W = "2" *) (* SYS_W = "2" *) +(* NotValidForBitStream *) +module selectio_lvds_rx + (data_in_from_pins, + data_in_to_device, + clk_in, + io_reset); + input [1:0]data_in_from_pins; + output [1:0]data_in_to_device; + input clk_in; + input io_reset; + + wire clk_in; + (* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire [1:0]data_in_from_pins; + wire [1:0]data_in_to_device; + wire io_reset; + + (* DEV_W = "2" *) + (* SYS_W = "2" *) + selectio_lvds_rx_selectio_lvds_rx_selectio_wiz inst + (.clk_in(clk_in), + .data_in_from_pins(data_in_from_pins), + .data_in_to_device(data_in_to_device), + .io_reset(io_reset)); +endmodule + +(* DEV_W = "2" *) (* ORIG_REF_NAME = "selectio_lvds_rx_selectio_wiz" *) (* SYS_W = "2" *) +module selectio_lvds_rx_selectio_lvds_rx_selectio_wiz + (data_in_from_pins, + data_in_to_device, + clk_in, + io_reset); + input [1:0]data_in_from_pins; + output [1:0]data_in_to_device; + input clk_in; + input io_reset; + + wire clk_in; + wire [1:0]data_in_from_pins; + wire [1:0]data_in_from_pins_int; + wire [1:0]data_in_to_device; + wire io_reset; + + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[0].fdre_in_inst + (.C(clk_in), + .CE(1'b1), + .D(data_in_from_pins_int[0]), + .Q(data_in_to_device[0]), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF \pins[0].ibuf_inst + (.I(data_in_from_pins[0]), + .O(data_in_from_pins_int[0])); + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[1].fdre_in_inst + (.C(clk_in), + .CE(1'b1), + .D(data_in_from_pins_int[1]), + .Q(data_in_to_device[1]), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF \pins[1].ibuf_inst + (.I(data_in_from_pins[1]), + .O(data_in_from_pins_int[1])); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_sim_netlist.vhdl b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_sim_netlist.vhdl new file mode 100644 index 00000000..8998975d --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_sim_netlist.vhdl @@ -0,0 +1,121 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Sun Mar 19 18:25:55 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim +-- D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.vhdl +-- Design : selectio_lvds_rx +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity selectio_lvds_rx_selectio_lvds_rx_selectio_wiz is + port ( + data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 ); + data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 ); + clk_in : in STD_LOGIC; + io_reset : in STD_LOGIC + ); + attribute DEV_W : integer; + attribute DEV_W of selectio_lvds_rx_selectio_lvds_rx_selectio_wiz : entity is 2; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of selectio_lvds_rx_selectio_lvds_rx_selectio_wiz : entity is "selectio_lvds_rx_selectio_wiz"; + attribute SYS_W : integer; + attribute SYS_W of selectio_lvds_rx_selectio_lvds_rx_selectio_wiz : entity is 2; +end selectio_lvds_rx_selectio_lvds_rx_selectio_wiz; + +architecture STRUCTURE of selectio_lvds_rx_selectio_lvds_rx_selectio_wiz is + signal data_in_from_pins_int : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of \pins[0].fdre_in_inst\ : label is "PRIMITIVE"; + attribute IOB : string; + attribute IOB of \pins[0].fdre_in_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[0].ibuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of \pins[0].ibuf_inst\ : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "AUTO"; + attribute BOX_TYPE of \pins[1].fdre_in_inst\ : label is "PRIMITIVE"; + attribute IOB of \pins[1].fdre_in_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[1].ibuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \pins[1].ibuf_inst\ : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE of \pins[1].ibuf_inst\ : label is "0"; + attribute IFD_DELAY_VALUE of \pins[1].ibuf_inst\ : label is "AUTO"; +begin +\pins[0].fdre_in_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => clk_in, + CE => '1', + D => data_in_from_pins_int(0), + Q => data_in_to_device(0), + R => io_reset + ); +\pins[0].ibuf_inst\: unisim.vcomponents.IBUF + port map ( + I => data_in_from_pins(0), + O => data_in_from_pins_int(0) + ); +\pins[1].fdre_in_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => clk_in, + CE => '1', + D => data_in_from_pins_int(1), + Q => data_in_to_device(1), + R => io_reset + ); +\pins[1].ibuf_inst\: unisim.vcomponents.IBUF + port map ( + I => data_in_from_pins(1), + O => data_in_from_pins_int(1) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity selectio_lvds_rx is + port ( + data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 ); + data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 ); + clk_in : in STD_LOGIC; + io_reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of selectio_lvds_rx : entity is true; + attribute DEV_W : integer; + attribute DEV_W of selectio_lvds_rx : entity is 2; + attribute SYS_W : integer; + attribute SYS_W of selectio_lvds_rx : entity is 2; +end selectio_lvds_rx; + +architecture STRUCTURE of selectio_lvds_rx is + attribute DEV_W of inst : label is 2; + attribute SYS_W of inst : label is 2; +begin +inst: entity work.selectio_lvds_rx_selectio_lvds_rx_selectio_wiz + port map ( + clk_in => clk_in, + data_in_from_pins(1 downto 0) => data_in_from_pins(1 downto 0), + data_in_to_device(1 downto 0) => data_in_to_device(1 downto 0), + io_reset => io_reset + ); +end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_stub.v similarity index 57% rename from projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.v rename to projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_stub.v index 36a25cc7..eadd56c4 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.v +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_stub.v @@ -1,11 +1,11 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:33:47 2023 +// Date : Sun Mar 19 18:25:55 2023 // Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) // Command : write_verilog -force -mode synth_stub -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.v -// Design : fifo_AntCtrl +// D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.v +// Design : selectio_lvds_rx // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 // -------------------------------------------------------------------------------- @@ -13,17 +13,11 @@ // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. -(* x_core_info = "fifo_generator_v13_2_4,Vivado 2019.1.3" *) -module fifo_AntCtrl(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, - empty) -/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[3:0],wr_en,rd_en,dout[3:0],full,empty" */; - input rst; - input wr_clk; - input rd_clk; - input [3:0]din; - input wr_en; - input rd_en; - output [3:0]dout; - output full; - output empty; +module selectio_lvds_rx(data_in_from_pins, data_in_to_device, clk_in, + io_reset) +/* synthesis syn_black_box black_box_pad_pin="data_in_from_pins[1:0],data_in_to_device[1:0],clk_in,io_reset" */; + input [1:0]data_in_from_pins; + output [1:0]data_in_to_device; + input clk_in; + input io_reset; endmodule diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_stub.vhdl b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_stub.vhdl new file mode 100644 index 00000000..681e6822 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx/selectio_lvds_rx_stub.vhdl @@ -0,0 +1,31 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Sun Mar 19 18:25:55 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub +-- D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.vhdl +-- Design : selectio_lvds_rx +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity selectio_lvds_rx is + Port ( + data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 ); + data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 ); + clk_in : in STD_LOGIC; + io_reset : in STD_LOGIC + ); + +end selectio_lvds_rx; + +architecture stub of selectio_lvds_rx is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "data_in_from_pins[1:0],data_in_to_device[1:0],clk_in,io_reset"; +begin +end; diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx.v new file mode 100644 index 00000000..e58d2865 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx.v @@ -0,0 +1,87 @@ + +// file: selectio_lvds_tx.v +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "selectio_lvds_tx,selectio_wiz_v5_1_13,{component_name=selectio_lvds_tx,bus_dir=OUTPUTS,bus_sig_type=SINGLE,bus_io_std=LVCMOS33,use_serialization=false,use_phase_detector=false,serialization_factor=4,enable_bitslip=false,enable_train=false,system_data_width=4,bus_in_delay=NONE,bus_out_delay=NONE,clk_sig_type=SINGLE,clk_io_std=LVCMOS18,clk_buf=BUFIO2,active_edge=RISING,clk_delay=NONE,selio_bus_in_delay=NONE,selio_bus_out_delay=NONE,selio_clk_buf=BUFIO,selio_active_edge=SDR,selio_ddr_alignment=SAME_EDGE_PIPELINED,selio_oddr_alignment=SAME_EDGE,ddr_alignment=C0,selio_interface_type=NETWORKING,interface_type=NETWORKING,selio_bus_in_tap=0,selio_bus_out_tap=0,selio_clk_io_std=LVCMOS33,selio_clk_sig_type=SINGLE}" *) + +module selectio_lvds_tx + // width of the data for the system + #(parameter SYS_W = 4, + // width of the data for the device + parameter DEV_W = 4) + ( + // From the device out to the system + input [DEV_W-1:0] data_out_from_device, + output [SYS_W-1:0] data_out_to_pins, + input clk_in, // Single ended clock from IOB + output clk_out, + input io_reset); + + + selectio_lvds_tx_selectio_wiz + #( + .SYS_W(SYS_W), + .DEV_W(DEV_W) + ) + inst + ( + .data_out_from_device(data_out_from_device), + .data_out_to_pins(data_out_to_pins), + .clk_in(clk_in), + .clk_out(clk_out), + .io_reset(io_reset) +); + +endmodule + diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx.veo b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx.veo new file mode 100644 index 00000000..4ede0b3d --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx.veo @@ -0,0 +1,68 @@ + +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. + + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +// User NOTES: +//None + + selectio_lvds_tx + instance_name + ( + .data_out_from_device(data_out_from_device), // input [3:0] data_out_from_device + .data_out_to_pins(data_out_to_pins), // output [3:0] data_out_to_pins + .clk_in(clk_in), // input clk_in + .clk_out(clk_out), // output clk_out + .io_reset(io_reset) // input io_reset +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v new file mode 100644 index 00000000..2fe8e3e5 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v @@ -0,0 +1,130 @@ + +// file: selectio_lvds_tx_selectio_wiz.v +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +module selectio_lvds_tx_selectio_wiz + // width of the data for the system + #(parameter SYS_W = 4, + // width of the data for the device + parameter DEV_W = 4) + ( + // From the device out to the system + input [DEV_W-1:0] data_out_from_device, + output [SYS_W-1:0] data_out_to_pins, + input clk_in, // Single ended clock from IOB + output clk_out, + input io_reset); + wire clock_enable = 1'b1; + // Signal declarations + ////------------------------------ + // Before the buffer + wire [SYS_W-1:0] data_out_to_pins_int; + // Between the delay and serdes + wire [SYS_W-1:0] data_out_to_pins_predelay; + // Create the clock logic + + + IBUF + #(.IOSTANDARD ("LVCMOS33")) + ibuf_clk_inst + (.I (clk_in), + .O (clk_in_int)); + + // BUFR generates the slow clock + BUFR + #(.SIM_DEVICE("7SERIES"), + .BUFR_DIVIDE("BYPASS")) + clkout_buf_inst + (.O (clk_div), + .CE(1'b1), + .CLR(1'b0), + .I (clk_in_int)); + + assign clk_out = clk_div; // This is regional clock; + // We have multiple bits- step over every bit, instantiating the required elements + genvar pin_count; + generate for (pin_count = 0; pin_count < SYS_W; pin_count = pin_count + 1) begin: pins + // Instantiate the buffers + ////------------------------------ + // Instantiate a buffer for every bit of the data bus + OBUF + #(.IOSTANDARD ("LVCMOS33")) + obuf_inst + (.O (data_out_to_pins [pin_count]), + .I (data_out_to_pins_int[pin_count])); + + // Pass through the delay + ////------------------------------- + assign data_out_to_pins_int[pin_count] = data_out_to_pins_predelay[pin_count]; + + // Connect the delayed data to the fabric + ////-------------------------------------- + + // Pack the registers into the IOB + wire data_out_from_device_q; + (* IOB = "true" *) + FDRE fdre_out_inst + (.D (data_out_from_device[pin_count]), + .C (clk_div), + .CE (clock_enable), + .R (io_reset), + .Q (data_out_from_device_q) + ); + assign data_out_to_pins_predelay[pin_count] = data_out_from_device_q; + end + endgenerate + +//// NO ODELAY + +endmodule diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_sim_netlist.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_sim_netlist.v new file mode 100644 index 00000000..9cf47661 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_sim_netlist.v @@ -0,0 +1,227 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +// Date : Sun Mar 19 17:32:20 2023 +// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v +// Design : selectio_lvds_tx +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* DEV_W = "4" *) (* SYS_W = "4" *) +(* NotValidForBitStream *) +module selectio_lvds_tx + (data_out_from_device, + data_out_to_pins, + clk_in, + clk_out, + io_reset); + input [3:0]data_out_from_device; + output [3:0]data_out_to_pins; + input clk_in; + output clk_out; + input io_reset; + + (* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire clk_in; + wire clk_out; + wire [3:0]data_out_from_device; + (* DRIVE = "12" *) (* IOSTANDARD = "LVCMOS33" *) (* SLEW = "SLOW" *) wire [3:0]data_out_to_pins; + wire io_reset; + + (* DEV_W = "4" *) + (* SYS_W = "4" *) + selectio_lvds_tx_selectio_lvds_tx_selectio_wiz inst + (.clk_in(clk_in), + .clk_out(clk_out), + .data_out_from_device(data_out_from_device), + .data_out_to_pins(data_out_to_pins), + .io_reset(io_reset)); +endmodule + +(* DEV_W = "4" *) (* ORIG_REF_NAME = "selectio_lvds_tx_selectio_wiz" *) (* SYS_W = "4" *) +module selectio_lvds_tx_selectio_lvds_tx_selectio_wiz + (data_out_from_device, + data_out_to_pins, + clk_in, + clk_out, + io_reset); + input [3:0]data_out_from_device; + output [3:0]data_out_to_pins; + input clk_in; + output clk_out; + input io_reset; + + wire clk_in; + wire clk_in_int; + wire clk_out; + wire [3:0]data_out_from_device; + wire [3:0]data_out_to_pins; + wire io_reset; + wire \pins[0].data_out_from_device_q ; + wire \pins[1].data_out_from_device_q ; + wire \pins[2].data_out_from_device_q ; + wire \pins[3].data_out_from_device_q ; + + (* BOX_TYPE = "PRIMITIVE" *) + BUFR #( + .BUFR_DIVIDE("BYPASS"), + .SIM_DEVICE("7SERIES")) + clkout_buf_inst + (.CE(1'b1), + .CLR(1'b0), + .I(clk_in_int), + .O(clk_out)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF ibuf_clk_inst + (.I(clk_in), + .O(clk_in_int)); + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[0].fdre_out_inst + (.C(clk_out), + .CE(1'b1), + .D(data_out_from_device[0]), + .Q(\pins[0].data_out_from_device_q ), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + OBUF \pins[0].obuf_inst + (.I(\pins[0].data_out_from_device_q ), + .O(data_out_to_pins[0])); + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[1].fdre_out_inst + (.C(clk_out), + .CE(1'b1), + .D(data_out_from_device[1]), + .Q(\pins[1].data_out_from_device_q ), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + OBUF \pins[1].obuf_inst + (.I(\pins[1].data_out_from_device_q ), + .O(data_out_to_pins[1])); + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[2].fdre_out_inst + (.C(clk_out), + .CE(1'b1), + .D(data_out_from_device[2]), + .Q(\pins[2].data_out_from_device_q ), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + OBUF \pins[2].obuf_inst + (.I(\pins[2].data_out_from_device_q ), + .O(data_out_to_pins[2])); + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[3].fdre_out_inst + (.C(clk_out), + .CE(1'b1), + .D(data_out_from_device[3]), + .Q(\pins[3].data_out_from_device_q ), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + OBUF \pins[3].obuf_inst + (.I(\pins[3].data_out_from_device_q ), + .O(data_out_to_pins[3])); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_sim_netlist.vhdl b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_sim_netlist.vhdl new file mode 100644 index 00000000..196d3869 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_sim_netlist.vhdl @@ -0,0 +1,193 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Sun Mar 19 17:32:20 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim +-- D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl +-- Design : selectio_lvds_tx +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity selectio_lvds_tx_selectio_lvds_tx_selectio_wiz is + port ( + data_out_from_device : in STD_LOGIC_VECTOR ( 3 downto 0 ); + data_out_to_pins : out STD_LOGIC_VECTOR ( 3 downto 0 ); + clk_in : in STD_LOGIC; + clk_out : out STD_LOGIC; + io_reset : in STD_LOGIC + ); + attribute DEV_W : integer; + attribute DEV_W of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz : entity is 4; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz : entity is "selectio_lvds_tx_selectio_wiz"; + attribute SYS_W : integer; + attribute SYS_W of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz : entity is 4; +end selectio_lvds_tx_selectio_lvds_tx_selectio_wiz; + +architecture STRUCTURE of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz is + signal clk_in_int : STD_LOGIC; + signal \^clk_out\ : STD_LOGIC; + signal \pins[0].data_out_from_device_q\ : STD_LOGIC; + signal \pins[1].data_out_from_device_q\ : STD_LOGIC; + signal \pins[2].data_out_from_device_q\ : STD_LOGIC; + signal \pins[3].data_out_from_device_q\ : STD_LOGIC; + attribute BOX_TYPE : string; + attribute BOX_TYPE of clkout_buf_inst : label is "PRIMITIVE"; + attribute BOX_TYPE of ibuf_clk_inst : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of ibuf_clk_inst : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of ibuf_clk_inst : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of ibuf_clk_inst : label is "AUTO"; + attribute BOX_TYPE of \pins[0].fdre_out_inst\ : label is "PRIMITIVE"; + attribute IOB : string; + attribute IOB of \pins[0].fdre_out_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[0].obuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \pins[0].obuf_inst\ : label is "DONT_CARE"; + attribute BOX_TYPE of \pins[1].fdre_out_inst\ : label is "PRIMITIVE"; + attribute IOB of \pins[1].fdre_out_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[1].obuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \pins[1].obuf_inst\ : label is "DONT_CARE"; + attribute BOX_TYPE of \pins[2].fdre_out_inst\ : label is "PRIMITIVE"; + attribute IOB of \pins[2].fdre_out_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[2].obuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \pins[2].obuf_inst\ : label is "DONT_CARE"; + attribute BOX_TYPE of \pins[3].fdre_out_inst\ : label is "PRIMITIVE"; + attribute IOB of \pins[3].fdre_out_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[3].obuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \pins[3].obuf_inst\ : label is "DONT_CARE"; +begin + clk_out <= \^clk_out\; +clkout_buf_inst: unisim.vcomponents.BUFR + generic map( + BUFR_DIVIDE => "BYPASS", + SIM_DEVICE => "7SERIES" + ) + port map ( + CE => '1', + CLR => '0', + I => clk_in_int, + O => \^clk_out\ + ); +ibuf_clk_inst: unisim.vcomponents.IBUF + port map ( + I => clk_in, + O => clk_in_int + ); +\pins[0].fdre_out_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => \^clk_out\, + CE => '1', + D => data_out_from_device(0), + Q => \pins[0].data_out_from_device_q\, + R => io_reset + ); +\pins[0].obuf_inst\: unisim.vcomponents.OBUF + port map ( + I => \pins[0].data_out_from_device_q\, + O => data_out_to_pins(0) + ); +\pins[1].fdre_out_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => \^clk_out\, + CE => '1', + D => data_out_from_device(1), + Q => \pins[1].data_out_from_device_q\, + R => io_reset + ); +\pins[1].obuf_inst\: unisim.vcomponents.OBUF + port map ( + I => \pins[1].data_out_from_device_q\, + O => data_out_to_pins(1) + ); +\pins[2].fdre_out_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => \^clk_out\, + CE => '1', + D => data_out_from_device(2), + Q => \pins[2].data_out_from_device_q\, + R => io_reset + ); +\pins[2].obuf_inst\: unisim.vcomponents.OBUF + port map ( + I => \pins[2].data_out_from_device_q\, + O => data_out_to_pins(2) + ); +\pins[3].fdre_out_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => \^clk_out\, + CE => '1', + D => data_out_from_device(3), + Q => \pins[3].data_out_from_device_q\, + R => io_reset + ); +\pins[3].obuf_inst\: unisim.vcomponents.OBUF + port map ( + I => \pins[3].data_out_from_device_q\, + O => data_out_to_pins(3) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity selectio_lvds_tx is + port ( + data_out_from_device : in STD_LOGIC_VECTOR ( 3 downto 0 ); + data_out_to_pins : out STD_LOGIC_VECTOR ( 3 downto 0 ); + clk_in : in STD_LOGIC; + clk_out : out STD_LOGIC; + io_reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of selectio_lvds_tx : entity is true; + attribute DEV_W : integer; + attribute DEV_W of selectio_lvds_tx : entity is 4; + attribute SYS_W : integer; + attribute SYS_W of selectio_lvds_tx : entity is 4; +end selectio_lvds_tx; + +architecture STRUCTURE of selectio_lvds_tx is + attribute DEV_W of inst : label is 4; + attribute SYS_W of inst : label is 4; +begin +inst: entity work.selectio_lvds_tx_selectio_lvds_tx_selectio_wiz + port map ( + clk_in => clk_in, + clk_out => clk_out, + data_out_from_device(3 downto 0) => data_out_from_device(3 downto 0), + data_out_to_pins(3 downto 0) => data_out_to_pins(3 downto 0), + io_reset => io_reset + ); +end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_stub.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_stub.v new file mode 100644 index 00000000..b520abfc --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_stub.v @@ -0,0 +1,24 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +// Date : Sun Mar 19 17:32:20 2023 +// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v +// Design : selectio_lvds_tx +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module selectio_lvds_tx(data_out_from_device, data_out_to_pins, + clk_in, clk_out, io_reset) +/* synthesis syn_black_box black_box_pad_pin="data_out_from_device[3:0],data_out_to_pins[3:0],clk_in,clk_out,io_reset" */; + input [3:0]data_out_from_device; + output [3:0]data_out_to_pins; + input clk_in; + output clk_out; + input io_reset; +endmodule diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_stub.vhdl b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_stub.vhdl new file mode 100644 index 00000000..9591245e --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx/selectio_lvds_tx_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Sun Mar 19 17:32:20 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub +-- D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl +-- Design : selectio_lvds_tx +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity selectio_lvds_tx is + Port ( + data_out_from_device : in STD_LOGIC_VECTOR ( 3 downto 0 ); + data_out_to_pins : out STD_LOGIC_VECTOR ( 3 downto 0 ); + clk_in : in STD_LOGIC; + clk_out : out STD_LOGIC; + io_reset : in STD_LOGIC + ); + +end selectio_lvds_tx; + +architecture stub of selectio_lvds_tx is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "data_out_from_device[3:0],data_out_to_pins[3:0],clk_in,clk_out,io_reset"; +begin +end; diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh b/projects/datalink_814/dl814_k7/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh deleted file mode 100644 index 652d7d11..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh +++ /dev/null @@ -1,671 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// -// Company: Xilinx -// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing -// Date: 7/30/2014 -// Design Name: MMCME2 DRP -// Module Name: mmcme2_drp_func.h -// Version: 1.04 -// Target Devices: 7 Series || MMCM -// Tool versions: 2014.3 -// Description: This header provides the functions necessary to -// calculate the DRP register values for the V6 MMCM. -// -// Revision Notes: 3/12 - Updating lookup_low/lookup_high (CR) -// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 -// -// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR -// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING -// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -// APPLICATION OR STANDARD, XILINX IS MAKING NO -// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE -// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY -// REQUIRE FOR YOUR IMPLEMENTATION. XILINX -// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH -// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, -// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES -// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// PURPOSE. -// -// (c) Copyright 2009-2010 Xilinx, Inc. -// All rights reserved. -// -/////////////////////////////////////////////////////////////////////////////// - -// These are user functions that should not be modified. Changes to the defines -// or code within the functions may alter the accuracy of the calculations. - -// Define debug to provide extra messages durring elaboration -//`define DEBUG 1 - -// FRAC_PRECISION describes the width of the fractional portion of the fixed -// point numbers. These should not be modified, they are for development -// only -`define FRAC_PRECISION 10 -// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). -// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs -// greater than 32 -`define FIXED_WIDTH 32 - -// This function takes a fixed point number and rounds it to the nearest -// fractional precision bit. -function [`FIXED_WIDTH:1] round_frac - ( - // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number - input [`FIXED_WIDTH:1] decimal, - - // This describes the precision of the fraction, for example a value - // of 1 would modify the fractional so that instead of being a .16 - // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) - input [`FIXED_WIDTH:1] precision - ); - - begin - - `ifdef DEBUG - $display("round_frac - decimal: %h, precision: %h", decimal, precision); - `endif - // If the fractional precision bit is high then round up - if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin - round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); - end else begin - round_frac = decimal; - end - `ifdef DEBUG - $display("round_frac: %h", round_frac); - `endif - end -endfunction - -// This function calculates high_time, low_time, w_edge, and no_count -// of a non-fractional counter based on the divide and duty cycle -// -// NOTE: high_time and low_time are returned as integers between 0 and 63 -// inclusive. 64 should equal 6'b000000 (in other words it is okay to -// ignore the overflow) -function [13:0] mmcm_pll_divider - ( - input [7:0] divide, // Max divide is 128 - input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 - ); - - reg [`FIXED_WIDTH:1] duty_cycle_fix; - - // High/Low time is initially calculated with a wider integer to prevent a - // calculation error when it overflows to 64. - reg [6:0] high_time; - reg [6:0] low_time; - reg w_edge; - reg no_count; - - reg [`FIXED_WIDTH:1] temp; - - begin - // Duty Cycle must be between 0 and 1,000 - if(duty_cycle <=0 || duty_cycle >= 100000) begin -`ifndef SYNTHESIS - $display("ERROR: duty_cycle: %d is invalid", duty_cycle); - `endif - $finish; - end - - // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point - duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; - - `ifdef DEBUG - $display("duty_cycle_fix: %h", duty_cycle_fix); - `endif - - // If the divide is 1 nothing needs to be set except the no_count bit. - // Other values are dummies - if(divide == 7'h01) begin - high_time = 7'h01; - w_edge = 1'b0; - low_time = 7'h01; - no_count = 1'b1; - end else begin - temp = round_frac(duty_cycle_fix*divide, 1); - - // comes from above round_frac - high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; - // If the duty cycle * divide rounded is .5 or greater then this bit - // is set. - w_edge = temp[`FRAC_PRECISION]; // comes from round_frac - - // If the high time comes out to 0, it needs to be set to at least 1 - // and w_edge set to 0 - if(high_time == 7'h00) begin - high_time = 7'h01; - w_edge = 1'b0; - end - - if(high_time == divide) begin - high_time = divide - 1; - w_edge = 1'b1; - end - - // Calculate low_time based on the divide setting and set no_count to - // 0 as it is only used when divide is 1. - low_time = divide - high_time; - no_count = 1'b0; - end - - // Set the return value. - mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; - end -endfunction - -// This function calculates mx, delay_time, and phase_mux -// of a non-fractional counter based on the divide and phase -// -// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux -// is used. -function [10:0] mmcm_pll_phase - ( - // divide must be an integer (use fractional if not) - // assumed that divide already checked to be valid - input [7:0] divide, // Max divide is 128 - - // Phase is given in degrees (-360,000 to 360,000) - input signed [31:0] phase - ); - - reg [`FIXED_WIDTH:1] phase_in_cycles; - reg [`FIXED_WIDTH:1] phase_fixed; - reg [1:0] mx; - reg [5:0] delay_time; - reg [2:0] phase_mux; - - reg [`FIXED_WIDTH:1] temp; - - begin -`ifdef DEBUG - $display("mmcm_pll_phase-divide:%d,phase:%d", - divide, phase); -`endif - - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - // If phase is less than 0, convert it to a positive phase shift - // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point - if(phase < 0) begin - phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; - end else begin - phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; - end - - // Put phase in terms of decimal number of vco clock cycles - phase_in_cycles = ( phase_fixed * divide ) / 360; - -`ifdef DEBUG - $display("phase_in_cycles: %h", phase_in_cycles); -`endif - - - temp = round_frac(phase_in_cycles, 3); - - // set mx to 2'b00 that the phase mux from the VCO is enabled - mx = 2'b00; - phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; - delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; - - `ifdef DEBUG - $display("temp: %h", temp); - `endif - - // Setup the return value - mmcm_pll_phase={mx, phase_mux, delay_time}; - end -endfunction - -// This function takes the divide value and outputs the necessary lock values -function [39:0] mmcm_pll_lock_lookup - ( - input [6:0] divide // Max divide is 64 - ); - - reg [2559:0] lookup; - - begin - lookup = { - // This table is composed of: - // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt - 40'b00110_00110_1111101000_1111101001_0000000001, - 40'b00110_00110_1111101000_1111101001_0000000001, - 40'b01000_01000_1111101000_1111101001_0000000001, - 40'b01011_01011_1111101000_1111101001_0000000001, - 40'b01110_01110_1111101000_1111101001_0000000001, - 40'b10001_10001_1111101000_1111101001_0000000001, - 40'b10011_10011_1111101000_1111101001_0000000001, - 40'b10110_10110_1111101000_1111101001_0000000001, - 40'b11001_11001_1111101000_1111101001_0000000001, - 40'b11100_11100_1111101000_1111101001_0000000001, - 40'b11111_11111_1110000100_1111101001_0000000001, - 40'b11111_11111_1100111001_1111101001_0000000001, - 40'b11111_11111_1011101110_1111101001_0000000001, - 40'b11111_11111_1010111100_1111101001_0000000001, - 40'b11111_11111_1010001010_1111101001_0000000001, - 40'b11111_11111_1001110001_1111101001_0000000001, - 40'b11111_11111_1000111111_1111101001_0000000001, - 40'b11111_11111_1000100110_1111101001_0000000001, - 40'b11111_11111_1000001101_1111101001_0000000001, - 40'b11111_11111_0111110100_1111101001_0000000001, - 40'b11111_11111_0111011011_1111101001_0000000001, - 40'b11111_11111_0111000010_1111101001_0000000001, - 40'b11111_11111_0110101001_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0101110111_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; - `ifdef DEBUG - $display("lock_lookup: %b", mmcm_pll_lock_lookup); - `endif - end -endfunction - -// This function takes the divide value and the bandwidth setting of the MMCM -// and outputs the digital filter settings necessary. -function [9:0] mmcm_pll_filter_lookup - ( - input [6:0] divide, // Max divide is 64 - input [8*9:0] BANDWIDTH - ); - - reg [639:0] lookup_low; - reg [639:0] lookup_high; - - reg [9:0] lookup_entry; - - begin - lookup_low = { - // CP_RES_LFHF - 10'b0010_1111_00, - 10'b0010_1111_00, - 10'b0010_1111_00, - 10'b0010_1111_00, - 10'b0010_0111_00, - 10'b0010_1011_00, - 10'b0010_1101_00, - 10'b0010_0011_00, - 10'b0010_0101_00, - 10'b0010_0101_00, - 10'b0010_1001_00, - 10'b0010_1110_00, - 10'b0010_1110_00, - 10'b0010_1110_00, - 10'b0010_1110_00, - 10'b0010_0001_00, - 10'b0010_0001_00, - 10'b0010_0001_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00 - }; - - lookup_high = { - // CP_RES_LFHF - 10'b0010_1111_00, - 10'b0100_1111_00, - 10'b0101_1011_00, - 10'b0111_0111_00, - 10'b1101_0111_00, - 10'b1110_1011_00, - 10'b1110_1101_00, - 10'b1111_0011_00, - 10'b1110_0101_00, - 10'b1111_0101_00, - 10'b1111_1001_00, - 10'b1101_0001_00, - 10'b1111_1001_00, - 10'b1111_1001_00, - 10'b1111_1001_00, - 10'b1111_1001_00, - 10'b1111_0101_00, - 10'b1111_0101_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b0101_1100_00, - 10'b0101_1100_00, - 10'b0101_1100_00, - 10'b0101_1100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0111_0001_00, - 10'b0111_0001_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0110_0001_00, - 10'b0110_0001_00, - 10'b0101_0110_00, - 10'b0101_0110_00, - 10'b0101_0110_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0100_1010_00, - 10'b0011_1100_00, - 10'b0011_1100_00 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - if(BANDWIDTH == "LOW") begin - // Low Bandwidth - mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; - end else begin - // High or optimized bandwidth - mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; - end - - `ifdef DEBUG - $display("filter_lookup: %b", mmcm_pll_filter_lookup); - `endif - end -endfunction - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -function [37:0] mmcm_pll_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle // Multiplied by 100,000 - ); - - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] - div_calc = mmcm_pll_divider(divide, duty_cycle); - // mx[10:9], pm[8:6], dt[5:0] - phase_calc = mmcm_pll_phase(divide, phase); - - // Return value is the upper and lower address of counter - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - `ifdef DEBUG - $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", - divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], - div_calc[13], div_calc[12], - phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); - `endif - - mmcm_pll_count_calc = - { - // Upper Address - 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], - // Lower Address - phase_calc[8:6], 1'b0, div_calc[11:0] - }; - end -endfunction - - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -// for fractional multiply/divide functions. -// -// -function [37:0] mmcm_frac_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle, // Multiplied by 1,000 - input [9:0] frac // Multiplied by 1000 - ); - - //Required for fractional divide calculations - reg [7:0] lt_frac; - reg [7:0] ht_frac; - - reg /*[7:0]*/ wf_fall_frac; - reg /*[7:0]*/ wf_rise_frac; - - reg [31:0] a; - reg [7:0] pm_rise_frac_filtered ; - reg [7:0] pm_fall_frac_filtered ; - reg [7:0] clkout0_divide_int; - reg [2:0] clkout0_divide_frac; - reg [7:0] even_part_high; - reg [7:0] even_part_low; - - reg [7:0] odd; - reg [7:0] odd_and_frac; - - reg [7:0] pm_fall; - reg [7:0] pm_rise; - reg [7:0] dt; - reg [7:0] dt_int; - reg [63:0] dt_calc; - - reg [7:0] pm_rise_frac; - reg [7:0] pm_fall_frac; - - reg [31:0] a_per_in_octets; - reg [31:0] a_phase_in_cycles; - - parameter precision = 0.125; - - reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 - reg [31: 0] phase_pos; - reg [31: 0] phase_vco; - reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - //convert phase to fixed - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - - // Return value is - // Transfer data - // RESERVED [37:36] - // FRAC_TIME [35:33] - // FRAC_WF_FALL [32] - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - - - clkout0_divide_frac = frac / 125; - clkout0_divide_int = divide; - - even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); - even_part_low = even_part_high; - - odd = clkout0_divide_int - even_part_high - even_part_low; - odd_and_frac = (8*odd) + clkout0_divide_frac; - - lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) - ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) - - pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 - pm_rise = 0; //0 - - wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 - wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) - - - - //Calculate phase in fractional cycles - a_per_in_octets = (8 * divide) + (frac / 125) ; - a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors - pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; - - dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) - dt = dt_calc[7:0]; - - pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; - - dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) - pm_fall_frac = pm_fall + pm_rise_frac; - pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; - - div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] - phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} - - mmcm_frac_count_calc[37:0] = - { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, - 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], - pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] - } ; - - `ifdef DEBUG - $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); - `endif - - end -endfunction - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh b/projects/datalink_814/dl814_k7/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh deleted file mode 100644 index 6a3e7c08..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh +++ /dev/null @@ -1,531 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// -// Company: Xilinx -// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing -// Date: 7/30/2014 -// Design Name: PLLE2 DRP -// Module Name: plle2_drp_func.h -// Version: 2.00 -// Target Devices: 7 Series || PLL -// Tool versions: 2014.3 -// Description: This header provides the functions necessary to -// calculate the DRP register values for the V6 PLL. -// Updated for CR663854. -// -// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR -// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING -// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -// APPLICATION OR STANDARD, XILINX IS MAKING NO -// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE -// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY -// REQUIRE FOR YOUR IMPLEMENTATION. XILINX -// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH -// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, -// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES -// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// PURPOSE. -// -// (c) Copyright 2009-2010 Xilinx, Inc. -// All rights reserved. -// -/////////////////////////////////////////////////////////////////////////////// - -// These are user functions that should not be modified. Changes to the defines -// or code within the functions may alter the accuracy of the calculations. - -// Define debug to provide extra messages durring elaboration -//`define DEBUG 1 - -// FRAC_PRECISION describes the width of the fractional portion of the fixed -// point numbers. These should not be modified, they are for development -// only -`define FRAC_PRECISION 10 -// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). -// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs -// greater than 32 -`define FIXED_WIDTH 32 - -// This function takes a fixed point number and rounds it to the nearest -// fractional precision bit. -function [`FIXED_WIDTH:1] round_frac - ( - // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number - input [`FIXED_WIDTH:1] decimal, - - // This describes the precision of the fraction, for example a value - // of 1 would modify the fractional so that instead of being a .16 - // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) - input [`FIXED_WIDTH:1] precision - ); - - begin - -`ifdef DEBUG - $display("round_frac - decimal: %h, precision: %h", decimal, precision); -`endif - // If the fractional precision bit is high then round up - if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin - round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); - end else begin - round_frac = decimal; - end -`ifdef DEBUG - $display("round_frac: %h", round_frac); -`endif - end -endfunction - -// This function calculates high_time, low_time, w_edge, and no_count -// of a non-fractional counter based on the divide and duty cycle -// -// NOTE: high_time and low_time are returned as integers between 0 and 63 -// inclusive. 64 should equal 6'b000000 (in other words it is okay to -// ignore the overflow) -function [13:0] mmcm_pll_divider - ( - input [7:0] divide, // Max divide is 128 - input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 - ); - - reg [`FIXED_WIDTH:1] duty_cycle_fix; - - // High/Low time is initially calculated with a wider integer to prevent a - // calculation error when it overflows to 64. - reg [6:0] high_time; - reg [6:0] low_time; - reg w_edge; - reg no_count; - - reg [`FIXED_WIDTH:1] temp; - - begin - // Duty Cycle must be between 0 and 1,000 - if(duty_cycle <=0 || duty_cycle >= 100000) begin -`ifndef SYNTHESIS - $display("ERROR: duty_cycle: %d is invalid", duty_cycle); - `endif - $finish; - end - - // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point - duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; - -`ifdef DEBUG - $display("duty_cycle_fix: %h", duty_cycle_fix); -`endif - - // If the divide is 1 nothing needs to be set except the no_count bit. - // Other values are dummies - if(divide == 7'h01) begin - high_time = 7'h01; - w_edge = 1'b0; - low_time = 7'h01; - no_count = 1'b1; - end else begin - temp = round_frac(duty_cycle_fix*divide, 1); - - // comes from above round_frac - high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; - // If the duty cycle * divide rounded is .5 or greater then this bit - // is set. - w_edge = temp[`FRAC_PRECISION]; // comes from round_frac - - // If the high time comes out to 0, it needs to be set to at least 1 - // and w_edge set to 0 - if(high_time == 7'h00) begin - high_time = 7'h01; - w_edge = 1'b0; - end - - if(high_time == divide) begin - high_time = divide - 1; - w_edge = 1'b1; - end - - // Calculate low_time based on the divide setting and set no_count to - // 0 as it is only used when divide is 1. - low_time = divide - high_time; - no_count = 1'b0; - end - - // Set the return value. - mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; - end -endfunction - -// This function calculates mx, delay_time, and phase_mux -// of a non-fractional counter based on the divide and phase -// -// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux -// is used. -function [10:0] mmcm_pll_phase - ( - // divide must be an integer (use fractional if not) - // assumed that divide already checked to be valid - input [7:0] divide, // Max divide is 128 - - // Phase is given in degrees (-360,000 to 360,000) - input signed [31:0] phase - ); - - reg [`FIXED_WIDTH:1] phase_in_cycles; - reg [`FIXED_WIDTH:1] phase_fixed; - reg [1:0] mx; - reg [5:0] delay_time; - reg [2:0] phase_mux; - - reg [`FIXED_WIDTH:1] temp; - - begin -`ifdef DEBUG - $display("mmcm_pll_phase-divide:%d,phase:%d", - divide, phase); -`endif - - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - // If phase is less than 0, convert it to a positive phase shift - // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point - if(phase < 0) begin - phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; - end else begin - phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; - end - - // Put phase in terms of decimal number of vco clock cycles - phase_in_cycles = ( phase_fixed * divide ) / 360; - -`ifdef DEBUG - $display("phase_in_cycles: %h", phase_in_cycles); -`endif - - - temp = round_frac(phase_in_cycles, 3); - - // set mx to 2'b00 that the phase mux from the VCO is enabled - mx = 2'b00; - phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; - delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; - -`ifdef DEBUG - $display("temp: %h", temp); -`endif - - // Setup the return value - mmcm_pll_phase={mx, phase_mux, delay_time}; - end -endfunction - -// This function takes the divide value and outputs the necessary lock values -function [39:0] mmcm_pll_lock_lookup - ( - input [6:0] divide // Max divide is 64 - ); - - reg [2559:0] lookup; - - begin - lookup = { - // This table is composed of: - // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt - 40'b00110_00110_1111101000_1111101001_0000000001, - 40'b00110_00110_1111101000_1111101001_0000000001, - 40'b01000_01000_1111101000_1111101001_0000000001, - 40'b01011_01011_1111101000_1111101001_0000000001, - 40'b01110_01110_1111101000_1111101001_0000000001, - 40'b10001_10001_1111101000_1111101001_0000000001, - 40'b10011_10011_1111101000_1111101001_0000000001, - 40'b10110_10110_1111101000_1111101001_0000000001, - 40'b11001_11001_1111101000_1111101001_0000000001, - 40'b11100_11100_1111101000_1111101001_0000000001, - 40'b11111_11111_1110000100_1111101001_0000000001, - 40'b11111_11111_1100111001_1111101001_0000000001, - 40'b11111_11111_1011101110_1111101001_0000000001, - 40'b11111_11111_1010111100_1111101001_0000000001, - 40'b11111_11111_1010001010_1111101001_0000000001, - 40'b11111_11111_1001110001_1111101001_0000000001, - 40'b11111_11111_1000111111_1111101001_0000000001, - 40'b11111_11111_1000100110_1111101001_0000000001, - 40'b11111_11111_1000001101_1111101001_0000000001, - 40'b11111_11111_0111110100_1111101001_0000000001, - 40'b11111_11111_0111011011_1111101001_0000000001, - 40'b11111_11111_0111000010_1111101001_0000000001, - 40'b11111_11111_0110101001_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0101110111_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; - `ifdef DEBUG - $display("lock_lookup: %b", mmcm_pll_lock_lookup); - `endif - end -endfunction - -// This function takes the divide value and the bandwidth setting of the PLL -// and outputs the digital filter settings necessary. -function [9:0] mmcm_pll_filter_lookup - ( - input [6:0] divide, // Max divide is 64 - input [8*9:0] BANDWIDTH - ); - - reg [639:0] lookup_low; - reg [639:0] lookup_high; - - reg [9:0] lookup_entry; - - begin - lookup_low = { - // CP_RES_LFHF - 10'b0010_1111_00, - 10'b0010_1111_00, - 10'b0010_0111_00, - 10'b0010_1101_00, - 10'b0010_0101_00, - 10'b0010_0101_00, - 10'b0010_1001_00, - 10'b0010_1110_00, - 10'b0010_1110_00, - 10'b0010_0001_00, - 10'b0010_0001_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0011_1100_00, - 10'b0011_1100_00, - 10'b0011_1100_00, - 10'b0011_1100_00, - 10'b0011_1100_00, - 10'b0011_1100_00, - 10'b0011_1100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00 - }; - - lookup_high = { - // CP_RES_LFHF - 10'b0011_0111_00, - 10'b0011_0111_00, - 10'b0101_1111_00, - 10'b0111_1111_00, - 10'b0111_1011_00, - 10'b1101_0111_00, - 10'b1110_1011_00, - 10'b1110_1101_00, - 10'b1111_1101_00, - 10'b1111_0111_00, - 10'b1111_1011_00, - 10'b1111_1101_00, - 10'b1111_0011_00, - 10'b1110_0101_00, - 10'b1111_0101_00, - 10'b1111_0101_00, - 10'b1111_0101_00, - 10'b1111_0101_00, - 10'b0111_0110_00, - 10'b0111_0110_00, - 10'b0111_0110_00, - 10'b0111_0110_00, - 10'b0101_1100_00, - 10'b0101_1100_00, - 10'b0101_1100_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b0100_0010_00, - 10'b0100_0010_00, - 10'b0100_0010_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0011_0100_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - if(BANDWIDTH == "LOW") begin - // Low Bandwidth - mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; - end else begin - // High or optimized bandwidth - mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; - end - - `ifdef DEBUG - $display("filter_lookup: %b", mmcm_pll_filter_lookup); - `endif - end -endfunction - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -function [37:0] mmcm_pll_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle // Multiplied by 100,000 - ); - - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); -`endif - - // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] - div_calc = mmcm_pll_divider(divide, duty_cycle); - // mx[10:9], pm[8:6], dt[5:0] - phase_calc = mmcm_pll_phase(divide, phase); - - // Return value is the upper and lower address of counter - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - -`ifdef DEBUG - $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", - divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], - div_calc[13], div_calc[12], - phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); -`endif - - mmcm_pll_count_calc = - { - // Upper Address - 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], - // Lower Address - phase_calc[8:6], 1'b0, div_calc[11:0] - }; - end -endfunction diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh b/projects/datalink_814/dl814_k7/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh deleted file mode 100644 index 2cffa9a7..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh +++ /dev/null @@ -1,671 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// -// Company: Xilinx -// Engineer: Jim Tatsukawa -// Date: 7/30/2014 -// Design Name: MMCME2 DRP -// Module Name: mmcme2_drp_func.h -// Version: 1.04 -// Target Devices: UltraScale Architecture || MMCM -// Tool versions: 2014.3 -// Description: This header provides the functions necessary to -// calculate the DRP register values for the V6 MMCM. -// -// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) -// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 -// -// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR -// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING -// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -// APPLICATION OR STANDARD, XILINX IS MAKING NO -// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE -// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY -// REQUIRE FOR YOUR IMPLEMENTATION. XILINX -// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH -// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, -// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES -// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// PURPOSE. -// -// (c) Copyright 2009-2010 Xilinx, Inc. -// All rights reserved. -// -/////////////////////////////////////////////////////////////////////////////// - -// These are user functions that should not be modified. Changes to the defines -// or code within the functions may alter the accuracy of the calculations. - -// Define debug to provide extra messages durring elaboration -//`define DEBUG 1 - -// FRAC_PRECISION describes the width of the fractional portion of the fixed -// point numbers. These should not be modified, they are for development -// only -`define FRAC_PRECISION 10 -// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). -// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs -// greater than 32 -`define FIXED_WIDTH 32 - -// This function takes a fixed point number and rounds it to the nearest -// fractional precision bit. -function [`FIXED_WIDTH:1] round_frac - ( - // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number - input [`FIXED_WIDTH:1] decimal, - - // This describes the precision of the fraction, for example a value - // of 1 would modify the fractional so that instead of being a .16 - // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) - input [`FIXED_WIDTH:1] precision - ); - - begin - - `ifdef DEBUG - $display("round_frac - decimal: %h, precision: %h", decimal, precision); - `endif - // If the fractional precision bit is high then round up - if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin - round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); - end else begin - round_frac = decimal; - end - `ifdef DEBUG - $display("round_frac: %h", round_frac); - `endif - end -endfunction - -// This function calculates high_time, low_time, w_edge, and no_count -// of a non-fractional counter based on the divide and duty cycle -// -// NOTE: high_time and low_time are returned as integers between 0 and 63 -// inclusive. 64 should equal 6'b000000 (in other words it is okay to -// ignore the overflow) -function [13:0] mmcm_pll_divider - ( - input [7:0] divide, // Max divide is 128 - input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 - ); - - reg [`FIXED_WIDTH:1] duty_cycle_fix; - - // High/Low time is initially calculated with a wider integer to prevent a - // calculation error when it overflows to 64. - reg [6:0] high_time; - reg [6:0] low_time; - reg w_edge; - reg no_count; - - reg [`FIXED_WIDTH:1] temp; - - begin - // Duty Cycle must be between 0 and 1,000 - if(duty_cycle <=0 || duty_cycle >= 100000) begin -`ifndef SYNTHESIS - $display("ERROR: duty_cycle: %d is invalid", duty_cycle); - `endif - $finish; - end - - // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point - duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; - - `ifdef DEBUG - $display("duty_cycle_fix: %h", duty_cycle_fix); - `endif - - // If the divide is 1 nothing needs to be set except the no_count bit. - // Other values are dummies - if(divide == 7'h01) begin - high_time = 7'h01; - w_edge = 1'b0; - low_time = 7'h01; - no_count = 1'b1; - end else begin - temp = round_frac(duty_cycle_fix*divide, 1); - - // comes from above round_frac - high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; - // If the duty cycle * divide rounded is .5 or greater then this bit - // is set. - w_edge = temp[`FRAC_PRECISION]; // comes from round_frac - - // If the high time comes out to 0, it needs to be set to at least 1 - // and w_edge set to 0 - if(high_time == 7'h00) begin - high_time = 7'h01; - w_edge = 1'b0; - end - - if(high_time == divide) begin - high_time = divide - 1; - w_edge = 1'b1; - end - - // Calculate low_time based on the divide setting and set no_count to - // 0 as it is only used when divide is 1. - low_time = divide - high_time; - no_count = 1'b0; - end - - // Set the return value. - mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; - end -endfunction - -// This function calculates mx, delay_time, and phase_mux -// of a non-fractional counter based on the divide and phase -// -// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux -// is used. -function [10:0] mmcm_pll_phase - ( - // divide must be an integer (use fractional if not) - // assumed that divide already checked to be valid - input [7:0] divide, // Max divide is 128 - - // Phase is given in degrees (-360,000 to 360,000) - input signed [31:0] phase - ); - - reg [`FIXED_WIDTH:1] phase_in_cycles; - reg [`FIXED_WIDTH:1] phase_fixed; - reg [1:0] mx; - reg [5:0] delay_time; - reg [2:0] phase_mux; - - reg [`FIXED_WIDTH:1] temp; - - begin -`ifdef DEBUG - $display("mmcm_pll_phase-divide:%d,phase:%d", - divide, phase); -`endif - - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - // If phase is less than 0, convert it to a positive phase shift - // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point - if(phase < 0) begin - phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; - end else begin - phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; - end - - // Put phase in terms of decimal number of vco clock cycles - phase_in_cycles = ( phase_fixed * divide ) / 360; - -`ifdef DEBUG - $display("phase_in_cycles: %h", phase_in_cycles); -`endif - - - temp = round_frac(phase_in_cycles, 3); - - // set mx to 2'b00 that the phase mux from the VCO is enabled - mx = 2'b00; - phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; - delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; - - `ifdef DEBUG - $display("temp: %h", temp); - `endif - - // Setup the return value - mmcm_pll_phase={mx, phase_mux, delay_time}; - end -endfunction - -// This function takes the divide value and outputs the necessary lock values -function [39:0] mmcm_pll_lock_lookup - ( - input [6:0] divide // Max divide is 64 - ); - - reg [2559:0] lookup; - - begin - lookup = { - // This table is composed of: - // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt - 40'b00110_00110_1111101000_1111101001_0000000001, - 40'b00110_00110_1111101000_1111101001_0000000001, - 40'b01000_01000_1111101000_1111101001_0000000001, - 40'b01011_01011_1111101000_1111101001_0000000001, - 40'b01110_01110_1111101000_1111101001_0000000001, - 40'b10001_10001_1111101000_1111101001_0000000001, - 40'b10011_10011_1111101000_1111101001_0000000001, - 40'b10110_10110_1111101000_1111101001_0000000001, - 40'b11001_11001_1111101000_1111101001_0000000001, - 40'b11100_11100_1111101000_1111101001_0000000001, - 40'b11111_11111_1110000100_1111101001_0000000001, - 40'b11111_11111_1100111001_1111101001_0000000001, - 40'b11111_11111_1011101110_1111101001_0000000001, - 40'b11111_11111_1010111100_1111101001_0000000001, - 40'b11111_11111_1010001010_1111101001_0000000001, - 40'b11111_11111_1001110001_1111101001_0000000001, - 40'b11111_11111_1000111111_1111101001_0000000001, - 40'b11111_11111_1000100110_1111101001_0000000001, - 40'b11111_11111_1000001101_1111101001_0000000001, - 40'b11111_11111_0111110100_1111101001_0000000001, - 40'b11111_11111_0111011011_1111101001_0000000001, - 40'b11111_11111_0111000010_1111101001_0000000001, - 40'b11111_11111_0110101001_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0101110111_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; - `ifdef DEBUG - $display("lock_lookup: %b", mmcm_pll_lock_lookup); - `endif - end -endfunction - -// This function takes the divide value and the bandwidth setting of the MMCM -// and outputs the digital filter settings necessary. -function [9:0] mmcm_pll_filter_lookup - ( - input [6:0] divide, // Max divide is 64 - input [8*9:0] BANDWIDTH - ); - - reg [639:0] lookup_low; - reg [639:0] lookup_high; - - reg [9:0] lookup_entry; - - begin - lookup_low = { - // CP_RES_LFHF - 10'b0010_1111_11, - 10'b0010_1111_11, - 10'b0010_1111_11, - 10'b0010_1111_11, - 10'b0010_1111_11, - 10'b0010_1111_11, - 10'b0010_0111_11, - 10'b0010_0111_11, - 10'b0010_0111_11, - 10'b0010_1101_11, - 10'b0010_1101_11, - 10'b0010_1101_11, - 10'b0010_0011_11, - 10'b0010_0101_11, - 10'b0010_0101_11, - 10'b0010_0101_11, - 10'b0010_1001_11, - 10'b0010_1001_11, - 10'b0010_1110_11, - 10'b0010_1110_11, - 10'b0010_1110_11, - 10'b0010_1110_11, - 10'b0010_1110_11, - 10'b0010_1110_11, - 10'b0010_0001_11, - 10'b0010_0001_11, - 10'b0010_0001_11, - 10'b0010_0001_11, - 10'b0010_0001_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11 - }; - - lookup_high = { - // CP_RES_LFHF - 10'b0010_1111_11, - 10'b0010_1111_11, - 10'b0010_1011_11, - 10'b0011_1111_11, - 10'b0100_1111_11, - 10'b0100_1111_11, - 10'b0101_1111_11, - 10'b0110_1111_11, - 10'b0111_1111_11, - 10'b0111_1111_11, - 10'b1100_1111_11, - 10'b1101_1111_11, - 10'b1110_1111_11, - 10'b1111_1111_11, - 10'b1111_1111_11, - 10'b1110_0111_11, - 10'b1110_1011_11, - 10'b1111_0111_11, - 10'b1111_1011_11, - 10'b1111_1011_11, - 10'b1110_1101_11, - 10'b1111_1101_11, - 10'b1111_1101_11, - 10'b1111_0011_11, - 10'b1111_0011_11, - 10'b1111_0011_11, - 10'b1110_0101_11, - 10'b1110_0101_11, - 10'b1110_0101_11, - 10'b1111_0101_11, - 10'b1111_0101_11, - 10'b1111_0101_11, - 10'b1111_1001_11, - 10'b1111_1001_11, - 10'b1111_1001_11, - 10'b1111_1001_11, - 10'b1111_1001_11, - 10'b1110_1110_11, - 10'b1110_1110_11, - 10'b1110_1110_11, - 10'b1110_1110_11, - 10'b1111_1110_11, - 10'b1111_1110_11, - 10'b1111_1110_11, - 10'b1111_1110_11, - 10'b1111_1110_11, - 10'b1111_1110_11, - 10'b1111_1110_11, - 10'b1110_0001_11, - 10'b1110_0001_11, - 10'b1110_0001_11, - 10'b1110_0001_11, - 10'b1110_0001_11, - 10'b1100_0110_11, - 10'b1100_0110_11, - 10'b1100_0110_11, - 10'b1100_0110_11, - 10'b1100_0110_11, - 10'b1100_0110_11, - 10'b1100_0110_11, - 10'b1100_1010_11, - 10'b1100_1010_11, - 10'b1100_1010_11, - 10'b1100_1010_11 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - if(BANDWIDTH == "LOW") begin - // Low Bandwidth - mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; - end else begin - // High or optimized bandwidth - mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; - end - - `ifdef DEBUG - $display("filter_lookup: %b", mmcm_pll_filter_lookup); - `endif - end -endfunction - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -function [37:0] mmcm_pll_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle // Multiplied by 100,000 - ); - - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] - div_calc = mmcm_pll_divider(divide, duty_cycle); - // mx[10:9], pm[8:6], dt[5:0] - phase_calc = mmcm_pll_phase(divide, phase); - - // Return value is the upper and lower address of counter - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - `ifdef DEBUG - $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", - divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], - div_calc[13], div_calc[12], - phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); - `endif - - mmcm_pll_count_calc = - { - // Upper Address - 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], - // Lower Address - phase_calc[8:6], 1'b0, div_calc[11:0] - }; - end -endfunction - - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -// for fractional multiply/divide functions. -// -// -function [37:0] mmcm_frac_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle, // Multiplied by 1,000 - input [9:0] frac // Multiplied by 1000 - ); - - //Required for fractional divide calculations - reg [7:0] lt_frac; - reg [7:0] ht_frac; - - reg /*[7:0]*/ wf_fall_frac; - reg /*[7:0]*/ wf_rise_frac; - - reg [31:0] a; - reg [7:0] pm_rise_frac_filtered ; - reg [7:0] pm_fall_frac_filtered ; - reg [7:0] clkout0_divide_int; - reg [2:0] clkout0_divide_frac; - reg [7:0] even_part_high; - reg [7:0] even_part_low; - - reg [7:0] odd; - reg [7:0] odd_and_frac; - - reg [7:0] pm_fall; - reg [7:0] pm_rise; - reg [7:0] dt; - reg [7:0] dt_int; - reg [63:0] dt_calc; - - reg [7:0] pm_rise_frac; - reg [7:0] pm_fall_frac; - - reg [31:0] a_per_in_octets; - reg [31:0] a_phase_in_cycles; - - parameter precision = 0.125; - - reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 - reg [31: 0] phase_pos; - reg [31: 0] phase_vco; - reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - //convert phase to fixed - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - - // Return value is - // Transfer data - // RESERVED [37:36] - // FRAC_TIME [35:33] - // FRAC_WF_FALL [32] - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - - - clkout0_divide_frac = frac / 125; - clkout0_divide_int = divide; - - even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); - even_part_low = even_part_high; - - odd = clkout0_divide_int - even_part_high - even_part_low; - odd_and_frac = (8*odd) + clkout0_divide_frac; - - lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) - ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) - - pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 - pm_rise = 0; //0 - - wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 - wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) - - - - //Calculate phase in fractional cycles - a_per_in_octets = (8 * divide) + (frac / 125) ; - a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors - pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; - - dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) - dt = dt_calc[7:0]; - - pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; - - dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) - pm_fall_frac = pm_fall + pm_rise_frac; - pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; - - div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] - phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} - - mmcm_frac_count_calc[37:0] = - { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, - 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], - pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] - } ; - - `ifdef DEBUG - $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); - `endif - - end -endfunction - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh b/projects/datalink_814/dl814_k7/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh deleted file mode 100644 index 9439f235..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh +++ /dev/null @@ -1,530 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// -// Company: Xilinx -// Engineer: Jim Tatsukawa -// Date: 6/15/2015 -// Design Name: PLLE3 DRP -// Module Name: plle3_drp_func.h -// Version: 1.10 -// Target Devices: UltraScale Architecture -// Tool versions: 2015.1 -// Description: This header provides the functions necessary to -// calculate the DRP register values for the V6 PLL. -// -// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 -// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 -// PM_Rise bits have been removed for PLLE3 -// -// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR -// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING -// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -// APPLICATION OR STANDARD, XILINX IS MAKING NO -// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE -// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY -// REQUIRE FOR YOUR IMPLEMENTATION. XILINX -// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH -// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, -// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES -// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// PURPOSE. -// -// (c) Copyright 2009-2010 Xilinx, Inc. -// All rights reserved. -// -/////////////////////////////////////////////////////////////////////////////// - -// These are user functions that should not be modified. Changes to the defines -// or code within the functions may alter the accuracy of the calculations. - -// Define debug to provide extra messages durring elaboration -//`define DEBUG 1 - -// FRAC_PRECISION describes the width of the fractional portion of the fixed -// point numbers. These should not be modified, they are for development -// only -`define FRAC_PRECISION 10 -// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). -// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs -// greater than 32 -`define FIXED_WIDTH 32 - -// This function takes a fixed point number and rounds it to the nearest -// fractional precision bit. -function [`FIXED_WIDTH:1] round_frac - ( - // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number - input [`FIXED_WIDTH:1] decimal, - - // This describes the precision of the fraction, for example a value - // of 1 would modify the fractional so that instead of being a .16 - // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) - input [`FIXED_WIDTH:1] precision - ); - - begin - - `ifdef DEBUG - $display("round_frac - decimal: %h, precision: %h", decimal, precision); - `endif - // If the fractional precision bit is high then round up - if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin - round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); - end else begin - round_frac = decimal; - end - `ifdef DEBUG - $display("round_frac: %h", round_frac); - `endif - end -endfunction - -// This function calculates high_time, low_time, w_edge, and no_count -// of a non-fractional counter based on the divide and duty cycle -// -// NOTE: high_time and low_time are returned as integers between 0 and 63 -// inclusive. 64 should equal 6'b000000 (in other words it is okay to -// ignore the overflow) -function [13:0] mmcm_pll_divider - ( - input [7:0] divide, // Max divide is 128 - input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 - ); - - reg [`FIXED_WIDTH:1] duty_cycle_fix; - - // High/Low time is initially calculated with a wider integer to prevent a - // calculation error when it overflows to 64. - reg [6:0] high_time; - reg [6:0] low_time; - reg w_edge; - reg no_count; - - reg [`FIXED_WIDTH:1] temp; - - begin - // Duty Cycle must be between 0 and 1,000 - if(duty_cycle <=0 || duty_cycle >= 100000) begin -`ifndef SYNTHESIS - $display("ERROR: duty_cycle: %d is invalid", duty_cycle); - `endif - $finish; - end - - // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point - duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; - - `ifdef DEBUG - $display("duty_cycle_fix: %h", duty_cycle_fix); - `endif - - // If the divide is 1 nothing needs to be set except the no_count bit. - // Other values are dummies - if(divide == 7'h01) begin - high_time = 7'h01; - w_edge = 1'b0; - low_time = 7'h01; - no_count = 1'b1; - end else begin - temp = round_frac(duty_cycle_fix*divide, 1); - - // comes from above round_frac - high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; - // If the duty cycle * divide rounded is .5 or greater then this bit - // is set. - w_edge = temp[`FRAC_PRECISION]; // comes from round_frac - - // If the high time comes out to 0, it needs to be set to at least 1 - // and w_edge set to 0 - if(high_time == 7'h00) begin - high_time = 7'h01; - w_edge = 1'b0; - end - - if(high_time == divide) begin - high_time = divide - 1; - w_edge = 1'b1; - end - - // Calculate low_time based on the divide setting and set no_count to - // 0 as it is only used when divide is 1. - low_time = divide - high_time; - no_count = 1'b0; - end - - // Set the return value. - mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; - end -endfunction - -// This function calculates mx, delay_time, and phase_mux -// of a non-fractional counter based on the divide and phase -// -// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux -// is used. -function [10:0] mmcm_pll_phase - ( - // divide must be an integer (use fractional if not) - // assumed that divide already checked to be valid - input [7:0] divide, // Max divide is 128 - - // Phase is given in degrees (-360,000 to 360,000) - input signed [31:0] phase - ); - - reg [`FIXED_WIDTH:1] phase_in_cycles; - reg [`FIXED_WIDTH:1] phase_fixed; - reg [1:0] mx; - reg [5:0] delay_time; - reg [2:0] phase_mux; - - reg [`FIXED_WIDTH:1] temp; - - begin -`ifdef DEBUG - $display("mmcm_pll_phase-divide:%d,phase:%d", - divide, phase); -`endif - - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - // If phase is less than 0, convert it to a positive phase shift - // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point - if(phase < 0) begin - phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; - end else begin - phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; - end - - // Put phase in terms of decimal number of vco clock cycles - phase_in_cycles = ( phase_fixed * divide ) / 360; - -`ifdef DEBUG - $display("phase_in_cycles: %h", phase_in_cycles); -`endif - - - temp = round_frac(phase_in_cycles, 3); - - // set mx to 2'b00 that the phase mux from the VCO is enabled - mx = 2'b00; - phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; - delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; - - `ifdef DEBUG - $display("temp: %h", temp); - `endif - - // Setup the return value - mmcm_pll_phase={mx, phase_mux, delay_time}; - end -endfunction - -// This function takes the divide value and outputs the necessary lock values -function [39:0] mmcm_pll_lock_lookup - ( - input [6:0] divide // Max divide is 64 - ); - - reg [759:0] lookup; - - begin - lookup = { - // This table is composed of: - // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt - 40'b00110_00110_1111101000_1111101001_0000000001, //1 - 40'b00110_00110_1111101000_1111101001_0000000001, //2 - 40'b01000_01000_1111101000_1111101001_0000000001, //3 - 40'b01011_01011_1111101000_1111101001_0000000001, //4 - 40'b01110_01110_1111101000_1111101001_0000000001, //5 - 40'b10001_10001_1111101000_1111101001_0000000001, //6 - 40'b10011_10011_1111101000_1111101001_0000000001, //7 - 40'b10110_10110_1111101000_1111101001_0000000001, //8 - 40'b11001_11001_1111101000_1111101001_0000000001, //9 - 40'b11100_11100_1111101000_1111101001_0000000001, //10 - 40'b11111_11111_1110000100_1111101001_0000000001, //11 - 40'b11111_11111_1100111001_1111101001_0000000001, //12 - 40'b11111_11111_1011101110_1111101001_0000000001, //13 - 40'b11111_11111_1010111100_1111101001_0000000001, //14 - 40'b11111_11111_1010001010_1111101001_0000000001, //15 - 40'b11111_11111_1001110001_1111101001_0000000001, //16 - 40'b11111_11111_1000111111_1111101001_0000000001, //17 - 40'b11111_11111_1000100110_1111101001_0000000001, //18 - 40'b11111_11111_1000001101_1111101001_0000000001 //19 - - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40]; - `ifdef DEBUG - $display("lock_lookup: %b", mmcm_pll_lock_lookup); - `endif - end -endfunction - -// This function takes the divide value and the bandwidth setting of the PLL -// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. -function [9:0] mmcm_pll_filter_lookup - ( - input [6:0] divide // Max divide is 19 - ); - - reg [639:0] lookup; - reg [9:0] lookup_entry; - - begin - - lookup = { - // CP_RES_LFHF - 10'b0010_1111_01, //1 - 10'b0010_0011_11, //2 - 10'b0011_0011_11, //3 - 10'b0010_0001_11, //4 - 10'b0010_0110_11, //5 - 10'b0010_1010_11, //6 - 10'b0010_1010_11, //7 - 10'b0011_0110_11, //8 - 10'b0010_1100_11, //9 - 10'b0010_1100_11, //10 - 10'b0010_1100_11, //11 - 10'b0010_0010_11, //12 - 10'b0011_1100_11, //13 - 10'b0011_1100_11, //14 - 10'b0011_1100_11, //15 - 10'b0011_1100_11, //16 - 10'b0011_0010_11, //17 - 10'b0011_0010_11, //18 - 10'b0011_0010_11 //19 - }; - - mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10]; - - `ifdef DEBUG - $display("filter_lookup: %b", mmcm_pll_filter_lookup); - `endif - end -endfunction - -// This function set the CLKOUTPHY divide settings to match -// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then -// the CLKOUTPHY will be set to 2'b00 since the VCO is internally -// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10 -function [9:0] mmcm_pll_clkoutphy_calc - ( - input [8*9:0] CLKOUTPHY_MODE - ); - - if(CLKOUTPHY_MODE == "VCO_X2") begin - mmcm_pll_clkoutphy_calc= 2'b00; - end else if(CLKOUTPHY_MODE == "VCO") begin - mmcm_pll_clkoutphy_calc= 2'b01; - end else if(CLKOUTPHY_MODE == "CLKIN") begin - mmcm_pll_clkoutphy_calc= 2'b11; - end else begin // Assume "VCO_HALF" - mmcm_pll_clkoutphy_calc= 2'b10; - end - -endfunction - - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -function [37:0] mmcm_pll_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle // Multiplied by 100,000 - ); - - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] - div_calc = mmcm_pll_divider(divide, duty_cycle); - // mx[10:9], pm[8:6], dt[5:0] - phase_calc = mmcm_pll_phase(divide, phase); - - // Return value is the upper and lower address of counter - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - `ifdef DEBUG - $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", - divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], - div_calc[13], div_calc[12], - phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits - `endif - - mmcm_pll_count_calc = - { - // Upper Address - 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], - // Lower Address - phase_calc[8:6], 1'b0, div_calc[11:0] - }; - end -endfunction - - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -// for fractional multiply/divide functions. -// -// -function [37:0] mmcm_pll_frac_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle, // Multiplied by 1,000 - input [9:0] frac // Multiplied by 1000 - ); - - //Required for fractional divide calculations - reg [7:0] lt_frac; - reg [7:0] ht_frac; - - reg /*[7:0]*/ wf_fall_frac; - reg /*[7:0]*/ wf_rise_frac; - - reg [31:0] a; - reg [7:0] pm_rise_frac_filtered ; - reg [7:0] pm_fall_frac_filtered ; - reg [7:0] clkout0_divide_int; - reg [2:0] clkout0_divide_frac; - reg [7:0] even_part_high; - reg [7:0] even_part_low; - - reg [7:0] odd; - reg [7:0] odd_and_frac; - - reg [7:0] pm_fall; - reg [7:0] pm_rise; - reg [7:0] dt; - reg [7:0] dt_int; - reg [63:0] dt_calc; - - reg [7:0] pm_rise_frac; - reg [7:0] pm_fall_frac; - - reg [31:0] a_per_in_octets; - reg [31:0] a_phase_in_cycles; - - parameter precision = 0.125; - - reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 - reg [31: 0] phase_pos; - reg [31: 0] phase_vco; - reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - //convert phase to fixed - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - - // Return value is - // Transfer data - // RESERVED [37:36] - // FRAC_TIME [35:33] - // FRAC_WF_FALL [32] - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - - - clkout0_divide_frac = frac / 125; - clkout0_divide_int = divide; - - even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); - even_part_low = even_part_high; - - odd = clkout0_divide_int - even_part_high - even_part_low; - odd_and_frac = (8*odd) + clkout0_divide_frac; - - lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) - ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) - - pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 - pm_rise = 0; //0 - - wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) - wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) - - - - //Calculate phase in fractional cycles - a_per_in_octets = (8 * divide) + (frac / 125) ; - a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors - pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; - - dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) - dt = dt_calc[7:0]; - - pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; - - dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) - pm_fall_frac = pm_fall + pm_rise_frac; - pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; - - div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] - phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} - - mmcm_pll_frac_count_calc[37:0] = - { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, - 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], - 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits -// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] - } ; - - `ifdef DEBUG - $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); - `endif - - end -endfunction - - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh b/projects/datalink_814/dl814_k7/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh deleted file mode 100644 index 61edf85c..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh +++ /dev/null @@ -1,861 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// -// Company: Xilinx -// Engineer: Jim Tatsukawa. Updated by Ralf Krueger -// Date: 7/30/2014 -// Design Name: MMCME4 DRP -// Module Name: mmcme4_drp_func.h -// Version: 1.31 -// Target Devices: UltraScale Plus Architecture -// Tool versions: 2017.1 -// Description: This header provides the functions necessary to -// calculate the DRP register values for UltraScal+ MMCM. -// -// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) -// 4/13 - Fractional divide function in mmcm_frac_count_calc function -// 2/28/17 - Updated for Ultrascale Plus -// -// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR -// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING -// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -// APPLICATION OR STANDARD, XILINX IS MAKING NO -// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE -// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY -// REQUIRE FOR YOUR IMPLEMENTATION. XILINX -// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH -// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, -// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES -// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// PURPOSE. -// -// (c) Copyright 2009-2017 Xilinx, Inc. -// All rights reserved. -// -/////////////////////////////////////////////////////////////////////////////// - -// These are user functions that should not be modified. Changes to the defines -// or code within the functions may alter the accuracy of the calculations. - -// Define debug to provide extra messages during elaboration -//`define DEBUG 1 - -// FRAC_PRECISION describes the width of the fractional portion of the fixed -// point numbers. These should not be modified, they are for development only -`define FRAC_PRECISION 10 -// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). -// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs -// greater than 32 -`define FIXED_WIDTH 32 - -// This function takes a fixed point number and rounds it to the nearest -// fractional precision bit. -function [`FIXED_WIDTH:1] round_frac - ( - // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number - input [`FIXED_WIDTH:1] decimal, - - // This describes the precision of the fraction, for example a value - // of 1 would modify the fractional so that instead of being a .16 - // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) - input [`FIXED_WIDTH:1] precision - ); - - begin - - `ifdef DEBUG - $display("round_frac - decimal: %h, precision: %h", decimal, precision); - `endif - // If the fractional precision bit is high then round up - if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin - round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); - end else begin - round_frac = decimal; - end - `ifdef DEBUG - $display("round_frac: %h", round_frac); - `endif - end -endfunction - -// This function calculates high_time, low_time, w_edge, and no_count -// of a non-fractional counter based on the divide and duty cycle -// -// NOTE: high_time and low_time are returned as integers between 0 and 63 -// inclusive. 64 should equal 6'b000000 (in other words it is okay to -// ignore the overflow) -function [13:0] mmcm_pll_divider - ( - input [7:0] divide, // Max divide is 128 - input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 - ); - - reg [`FIXED_WIDTH:1] duty_cycle_fix; - - // High/Low time is initially calculated with a wider integer to prevent a - // calculation error when it overflows to 64. - reg [6:0] high_time; - reg [6:0] low_time; - reg w_edge; - reg no_count; - - reg [`FIXED_WIDTH:1] temp; - - begin - // Duty Cycle must be between 0 and 1,000 - if(duty_cycle <=0 || duty_cycle >= 100000) begin -`ifndef SYNTHESIS - $display("ERROR: duty_cycle: %d is invalid", duty_cycle); - `endif - $finish; - end - - // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point - duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; - - `ifdef DEBUG - $display("duty_cycle_fix: %h", duty_cycle_fix); - `endif - - // If the divide is 1 nothing needs to be set except the no_count bit. - // Other values are dummies - if(divide == 7'h01) begin - high_time = 7'h01; - w_edge = 1'b0; - low_time = 7'h01; - no_count = 1'b1; - end else begin - temp = round_frac(duty_cycle_fix*divide, 1); - - // comes from above round_frac - high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; - // If the duty cycle * divide rounded is .5 or greater then this bit - // is set. - w_edge = temp[`FRAC_PRECISION]; // comes from round_frac - - // If the high time comes out to 0, it needs to be set to at least 1 - // and w_edge set to 0 - if(high_time == 7'h00) begin - high_time = 7'h01; - w_edge = 1'b0; - end - - if(high_time == divide) begin - high_time = divide - 1; - w_edge = 1'b1; - end - - // Calculate low_time based on the divide setting and set no_count to - // 0 as it is only used when divide is 1. - low_time = divide - high_time; - no_count = 1'b0; - end - - // Set the return value. - mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; - end -endfunction - -// This function calculates mx, delay_time, and phase_mux -// of a non-fractional counter based on the divide and phase -// -// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux -// is used. -function [10:0] mmcm_pll_phase - ( - // divide must be an integer (use fractional if not) - // assumed that divide already checked to be valid - input [7:0] divide, // Max divide is 128 - - // Phase is given in degrees (-360,000 to 360,000) - input signed [31:0] phase - ); - - reg [`FIXED_WIDTH:1] phase_in_cycles; - reg [`FIXED_WIDTH:1] phase_fixed; - reg [1:0] mx; - reg [5:0] delay_time; - reg [2:0] phase_mux; - - reg [`FIXED_WIDTH:1] temp; - - begin -`ifdef DEBUG - $display("mmcm_phase-divide:%d,phase:%d", divide, phase); -`endif - - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - // If phase is less than 0, convert it to a positive phase shift - // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point - if(phase < 0) begin - phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; - end else begin - phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; - end - - // Put phase in terms of decimal number of vco clock cycles - phase_in_cycles = ( phase_fixed * divide ) / 360; - -`ifdef DEBUG - $display("phase_in_cycles: %h", phase_in_cycles); -`endif - - temp = round_frac(phase_in_cycles, 3); - - // set mx to 2'b00 that the phase mux from the VCO is enabled - mx = 2'b00; - phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; - delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; - - `ifdef DEBUG - $display("temp: %h", temp); - `endif - - // Setup the return value - mmcm_pll_phase={mx, phase_mux, delay_time}; - end -endfunction - -// This function takes the divide value and outputs the necessary lock values -function [39:0] mmcm_pll_lock_lookup - ( - input [7:0] divide // Max M divide is 128 in UltrascalePlus - ); - - reg [5119:0] lookup; - - begin - lookup = { - // This table is composed of: - // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt - 40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed) - 40'b00110_00110_1111101000_1111101001_0000000001, // M=2 - 40'b01000_01000_1111101000_1111101001_0000000001, // M=3 - 40'b01011_01011_1111101000_1111101001_0000000001, // M=4 - 40'b01110_01110_1111101000_1111101001_0000000001, // M=5 - 40'b10001_10001_1111101000_1111101001_0000000001, // M=6 - 40'b10011_10011_1111101000_1111101001_0000000001, // M=7 - 40'b10110_10110_1111101000_1111101001_0000000001, - 40'b11001_11001_1111101000_1111101001_0000000001, - 40'b11100_11100_1111101000_1111101001_0000000001, - 40'b11111_11111_1110000100_1111101001_0000000001, - 40'b11111_11111_1100111001_1111101001_0000000001, - 40'b11111_11111_1011101110_1111101001_0000000001, - 40'b11111_11111_1010111100_1111101001_0000000001, - 40'b11111_11111_1010001010_1111101001_0000000001, - 40'b11111_11111_1001110001_1111101001_0000000001, - 40'b11111_11111_1000111111_1111101001_0000000001, - 40'b11111_11111_1000100110_1111101001_0000000001, - 40'b11111_11111_1000001101_1111101001_0000000001, - 40'b11111_11111_0111110100_1111101001_0000000001, - 40'b11111_11111_0111011011_1111101001_0000000001, - 40'b11111_11111_0111000010_1111101001_0000000001, - 40'b11111_11111_0110101001_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0101110111_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, // M=127 - 40'b11111_11111_0011111010_1111101001_0000000001 // M=128 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40]; - `ifdef DEBUG - $display("lock_lookup: %b", mmcm_pll_lock_lookup); - `endif - end -endfunction - -// This function takes the divide value and the bandwidth setting of the MMCM -// and outputs the digital filter settings necessary. -function [9:0] mmcm_pll_filter_lookup - ( - input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus - input [8*9:0] BANDWIDTH - ); - - reg [1279:0] lookup_low; - reg [1279:0] lookup_high; - - reg [9:0] lookup_entry; - - begin - lookup_low = { - // CP_RES_LFHF - 10'b0011_1111_11, // M=1 - not legal - 10'b0011_1111_11, // M=2 - 10'b0011_1101_11, // M=3 - 10'b0011_0101_11, // M=4 - 10'b0011_1001_11, // M=5 - 10'b0011_1110_11, // M=6 - 10'b0011_1110_11, // M=7 - 10'b0011_0001_11, - 10'b0011_0110_11, - 10'b0011_0110_11, - 10'b0011_0110_11, - 10'b0011_1010_11, - 10'b0011_1010_11, - 10'b0011_1010_11, - 10'b0100_0110_11, - 10'b0011_1100_11, - 10'b1110_0110_11, - 10'b1111_0110_11, - 10'b1110_1010_11, - 10'b1110_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1101_1100_11, - 10'b1101_1100_11, - 10'b1101_1100_11, - 10'b1110_1100_11, - 10'b1110_1100_11, - 10'b1110_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1110_0010_11, - 10'b1110_0010_11, - 10'b1110_0010_11, - 10'b1110_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, // M=127 - 10'b1101_1000_11 // M=128 -}; - - lookup_high = { - // CP_RES_LFHF - 10'b0111_1111_11, // M=1 - not legal - 10'b0111_1111_11, // M=2 - 10'b1110_1111_11, // M=3 - 10'b1111_1111_11, // M=4 - 10'b1111_1011_11, // M=5 - 10'b1111_1101_11, // M=6 - 10'b1111_0011_11, // M=7 - 10'b1110_0101_11, - 10'b1111_1001_11, - 10'b1111_1001_11, - 10'b1110_1110_11, - 10'b1111_1110_11, - 10'b1111_0001_11, - 10'b1111_0001_11, - 10'b1111_0001_11, - 10'b1110_0110_11, - 10'b1110_0110_11, - 10'b1111_0110_11, - 10'b1110_1010_11, - 10'b1110_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1101_1100_11, - 10'b1101_1100_11, - 10'b1101_1100_11, - 10'b1110_1100_11, - 10'b1110_1100_11, - 10'b1110_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1110_0010_11, - 10'b1110_0010_11, - 10'b1110_0010_11, - 10'b1110_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11 // M=128 -}; - - // Set lookup_entry with the explicit bits from lookup with a part select - if(BANDWIDTH == "LOW") begin - // Low Bandwidth - mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10]; - end else begin - // High or optimized bandwidth - mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10]; - end - - `ifdef DEBUG - $display("filter_lookup: %b", mmcm_pll_filter_lookup); - `endif - end -endfunction - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -function [37:0] mmcm_pll_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle // Multiplied by 100,000 - ); - - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] - div_calc = mmcm_pll_divider(divide, duty_cycle); - // mx[10:9], pm[8:6], dt[5:0] - phase_calc = mmcm_pll_phase(divide, phase); - - // Return value is the upper and lower address of counter - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - `ifdef DEBUG - $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", - divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], - div_calc[13], div_calc[12], - phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); - `endif - - mmcm_pll_count_calc = - { - // Upper Address - 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], - // Lower Address - phase_calc[8:6], 1'b0, div_calc[11:0] - }; - end -endfunction - - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -// for fractional multiply/divide functions. -// -// -function [37:0] mmcm_frac_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional - input [9:0] frac // Multiplied by 1000 - ); - - //Required for fractional divide calculations - reg [7:0] lt_frac; - reg [7:0] ht_frac; - - reg /*[7:0]*/ wf_fall_frac; - reg /*[7:0]*/ wf_rise_frac; - - reg [31:0] a; - reg [7:0] pm_rise_frac_filtered ; - reg [7:0] pm_fall_frac_filtered ; - reg [7:0] clkout0_divide_int; - reg [2:0] clkout0_divide_frac; - reg [7:0] even_part_high; - reg [7:0] even_part_low; - - reg [7:0] odd; - reg [7:0] odd_and_frac; - - reg [7:0] pm_fall; - reg [7:0] pm_rise; - reg [7:0] dt; - reg [7:0] dt_int; - reg [63:0] dt_calc; - - reg [7:0] pm_rise_frac; - reg [7:0] pm_fall_frac; - - reg [31:0] a_per_in_octets; - reg [31:0] a_phase_in_cycles; - - parameter precision = 0.125; - - reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 - reg [31: 0] phase_pos; - reg [31: 0] phase_vco; - reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - //convert phase to fixed - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - - // Return value is - // Transfer data - // RESERVED [37:36] - // FRAC_TIME [35:33] - // FRAC_WF_FALL [32] - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - - - clkout0_divide_frac = frac / 125; - clkout0_divide_int = divide; - - even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); - even_part_low = even_part_high; - - odd = clkout0_divide_int - even_part_high - even_part_low; - odd_and_frac = (8*odd) + clkout0_divide_frac; - - lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) - ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) - - pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 - pm_rise = 0; //0 - - wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) - wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) - - - - //Calculate phase in fractional cycles - a_per_in_octets = (8 * divide) + (frac / 125) ; - a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors - pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; - - dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) - dt = dt_calc[7:0]; - - pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; - - dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) - pm_fall_frac = pm_fall + pm_rise_frac; - pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; - - div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] - phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} - - mmcm_frac_count_calc[37:0] = - { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, - 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0], - pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] - } ; - - `ifdef DEBUG - $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); - `endif - - end -endfunction - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh b/projects/datalink_814/dl814_k7/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh deleted file mode 100644 index 1d2dc690..00000000 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh +++ /dev/null @@ -1,536 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// -// Company: Xilinx -// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+ -// Date: 6/15/2015 -// Design Name: PLLE4 DRP -// Module Name: plle4_drp_func.h -// Version: 2.0 -// Target Devices: UltraScale+ Architecture -// Tool versions: 2017.1 -// Description: This header provides the functions necessary to -// calculate the DRP register values for the V6 PLL. -// -// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 -// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 -// M_Rise bits have been removed for PLLE3 -// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for -// Ultrascale+ and for max M of 21 -// -// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR -// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING -// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -// APPLICATION OR STANDARD, XILINX IS MAKING NO -// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE -// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY -// REQUIRE FOR YOUR IMPLEMENTATION. XILINX -// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH -// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, -// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES -// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// PURPOSE. -// -// (c) Copyright 2009-2017 Xilinx, Inc. -// All rights reserved. -// -/////////////////////////////////////////////////////////////////////////////// - -// These are user functions that should not be modified. Changes to the defines -// or code within the functions may alter the accuracy of the calculations. - -// Define debug to provide extra messages durring elaboration -//`define DEBUG 1 - -// FRAC_PRECISION describes the width of the fractional portion of the fixed -// point numbers. These should not be modified, they are for development -// only -`define FRAC_PRECISION 10 -// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). -// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs -// greater than 32 -`define FIXED_WIDTH 32 - -// This function takes a fixed point number and rounds it to the nearest -// fractional precision bit. -function [`FIXED_WIDTH:1] round_frac - ( - // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number - input [`FIXED_WIDTH:1] decimal, - - // This describes the precision of the fraction, for example a value - // of 1 would modify the fractional so that instead of being a .16 - // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) - input [`FIXED_WIDTH:1] precision - ); - - begin - - `ifdef DEBUG - $display("round_frac - decimal: %h, precision: %h", decimal, precision); - `endif - // If the fractional precision bit is high then round up - if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin - round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); - end else begin - round_frac = decimal; - end - `ifdef DEBUG - $display("round_frac: %h", round_frac); - `endif - end -endfunction - -// This function calculates high_time, low_time, w_edge, and no_count -// of a non-fractional counter based on the divide and duty cycle -// -// NOTE: high_time and low_time are returned as integers between 0 and 63 -// inclusive. 64 should equal 6'b000000 (in other words it is okay to -// ignore the overflow) -function [13:0] mmcm_pll_divider - ( - input [7:0] divide, // Max divide is 128 - input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 - ); - - reg [`FIXED_WIDTH:1] duty_cycle_fix; - - // High/Low time is initially calculated with a wider integer to prevent a - // calculation error when it overflows to 64. - reg [6:0] high_time; - reg [6:0] low_time; - reg w_edge; - reg no_count; - - reg [`FIXED_WIDTH:1] temp; - - begin - // Duty Cycle must be between 0 and 1,000 - if(duty_cycle <=0 || duty_cycle >= 100000) begin -`ifndef SYNTHESIS - $display("ERROR: duty_cycle: %d is invalid", duty_cycle); - `endif - $finish; - end - - // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point - duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; - - `ifdef DEBUG - $display("duty_cycle_fix: %h", duty_cycle_fix); - `endif - - // If the divide is 1 nothing needs to be set except the no_count bit. - // Other values are dummies - if(divide == 7'h01) begin - high_time = 7'h01; - w_edge = 1'b0; - low_time = 7'h01; - no_count = 1'b1; - end else begin - temp = round_frac(duty_cycle_fix*divide, 1); - - // comes from above round_frac - high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; - // If the duty cycle * divide rounded is .5 or greater then this bit - // is set. - w_edge = temp[`FRAC_PRECISION]; // comes from round_frac - - // If the high time comes out to 0, it needs to be set to at least 1 - // and w_edge set to 0 - if(high_time == 7'h00) begin - high_time = 7'h01; - w_edge = 1'b0; - end - - if(high_time == divide) begin - high_time = divide - 1; - w_edge = 1'b1; - end - - // Calculate low_time based on the divide setting and set no_count to - // 0 as it is only used when divide is 1. - low_time = divide - high_time; - no_count = 1'b0; - end - - // Set the return value. - mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; - end -endfunction - -// This function calculates mx, delay_time, and phase_mux -// of a non-fractional counter based on the divide and phase -// -// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux -// is used. -function [10:0] mmcm_pll_phase - ( - // divide must be an integer (use fractional if not) - // assumed that divide already checked to be valid - input [7:0] divide, // Max divide is 128 - - // Phase is given in degrees (-360,000 to 360,000) - input signed [31:0] phase - ); - - reg [`FIXED_WIDTH:1] phase_in_cycles; - reg [`FIXED_WIDTH:1] phase_fixed; - reg [1:0] mx; - reg [5:0] delay_time; - reg [2:0] phase_mux; - - reg [`FIXED_WIDTH:1] temp; - - begin -`ifdef DEBUG - $display("pll_phase-divide:%d,phase:%d", - divide, phase); -`endif - - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); -`endif - $finish; - end - - // If phase is less than 0, convert it to a positive phase shift - // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point - if(phase < 0) begin - phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; - end else begin - phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; - end - - // Put phase in terms of decimal number of vco clock cycles - phase_in_cycles = ( phase_fixed * divide ) / 360; - -`ifdef DEBUG - $display("phase_in_cycles: %h", phase_in_cycles); -`endif - - - temp = round_frac(phase_in_cycles, 3); - - // set mx to 2'b00 that the phase mux from the VCO is enabled - mx = 2'b00; - phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; - delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; - - `ifdef DEBUG - $display("temp: %h", temp); - `endif - - // Setup the return value - mmcm_pll_phase={mx, phase_mux, delay_time}; - end -endfunction - -// This function takes the divide value and outputs the necessary lock values -function [39:0] mmcm_pll_lock_lookup - ( - input [6:0] divide // Max divide is 21 - ); - - reg [839:0] lookup; - - begin - lookup = { - // This table is composed of: - // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt - 40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+ - 40'b00110_00110_1111101000_1111101001_0000000001, //2 - 40'b01000_01000_1111101000_1111101001_0000000001, //3 - 40'b01011_01011_1111101000_1111101001_0000000001, //4 - 40'b01110_01110_1111101000_1111101001_0000000001, //5 - 40'b10001_10001_1111101000_1111101001_0000000001, //6 - 40'b10011_10011_1111101000_1111101001_0000000001, //7 - 40'b10110_10110_1111101000_1111101001_0000000001, //8 - 40'b11001_11001_1111101000_1111101001_0000000001, //9 - 40'b11100_11100_1111101000_1111101001_0000000001, //10 - 40'b11111_11111_1110000100_1111101001_0000000001, //11 - 40'b11111_11111_1100111001_1111101001_0000000001, //12 - 40'b11111_11111_1011101110_1111101001_0000000001, //13 - 40'b11111_11111_1010111100_1111101001_0000000001, //14 - 40'b11111_11111_1010001010_1111101001_0000000001, //15 - 40'b11111_11111_1001110001_1111101001_0000000001, //16 - 40'b11111_11111_1000111111_1111101001_0000000001, //17 - 40'b11111_11111_1000100110_1111101001_0000000001, //18 - 40'b11111_11111_1000001101_1111101001_0000000001, //19 - 40'b11111_11111_0111110100_1111101001_0000000001, //20 - 40'b11111_11111_0111011011_1111101001_0000000001 //21 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40]; - `ifdef DEBUG - $display("lock_lookup: %b", pll_lock_lookup); - `endif - end -endfunction - -// This function takes the divide value and the bandwidth setting of the PLL -// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. -function [9:0] mmcm_pll_filter_lookup - ( - input [6:0] divide // Max divide is 21 - ); - - reg [209:0] lookup; - reg [9:0] lookup_entry; - - begin - - lookup = { - // CP_RES_LFHF - 10'b0011_0111_11, //1 not legal in Ultrascale+ - 10'b0011_0111_11, //2 - 10'b0011_0011_11, //3 - 10'b0011_1001_11, //4 - 10'b0011_0001_11, //5 - 10'b0100_1110_11, //6 - 10'b0011_0110_11, //7 - 10'b0011_1010_11, //8 - 10'b0111_1001_11, //9 - 10'b0111_1001_11, //10 - 10'b0101_0110_11, //11 - 10'b1100_0101_11, //12 - 10'b0101_1010_11, //13 - 10'b0110_0110_11, //14 - 10'b0110_1010_11, //15 - 10'b0111_0110_11, //16 - 10'b1111_0101_11, //17 - 10'b1100_0110_11, //18 - 10'b1110_0001_11, //19 - 10'b1101_0110_11, //20 - 10'b1111_0001_11 //21 - }; - - mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10]; - - `ifdef DEBUG - $display("filter_lookup: %b", pll_filter_lookup); - `endif - end -endfunction - -// This function set the CLKOUTPHY divide settings to match -// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then -// the CLKOUTPHY will be set to 2'b00 since the VCO is internally -// doubled and 2'b00 will represent divide by 1. Similarly "VCO" -// will need to divide the doubled clock VCO clock frequency by -// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will -// need to divide the doubled VCO by 4, therefore 2'b10 -function [9:0] mmcm_pll_clkoutphy_calc - ( - input [8*9:0] CLKOUTPHY_MODE - ); - - if(CLKOUTPHY_MODE == "VCO_X2") begin - mmcm_pll_clkoutphy_calc= 2'b00; - end else if(CLKOUTPHY_MODE == "VCO") begin - mmcm_pll_clkoutphy_calc= 2'b01; - end else if(CLKOUTPHY_MODE == "CLKIN") begin - mmcm_pll_clkoutphy_calc= 2'b11; - end else begin // Assume "VCO_HALF" - mmcm_pll_clkoutphy_calc= 2'b10; - end - -endfunction - - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -function [37:0] mmcm_pll_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle // Multiplied by 100,000 - ); - - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] - div_calc = mmcm_pll_divider(divide, duty_cycle); - // mx[10:9], pm[8:6], dt[5:0] - phase_calc = mmcm_pll_phase(divide, phase); - - // Return value is the upper and lower address of counter - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - `ifdef DEBUG - $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", - divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], - div_calc[13], div_calc[12], - phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits - `endif - - mmcm_pll_count_calc = - { - // Upper Address - 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], - // Lower Address - phase_calc[8:6], 1'b0, div_calc[11:0] - }; - end -endfunction - - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -// for fractional multiply/divide functions. -// -// -function [37:0] mmcm_pll_frac_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle, // Multiplied by 1,000 - input [9:0] frac // Multiplied by 1000 - ); - - //Required for fractional divide calculations - reg [7:0] lt_frac; - reg [7:0] ht_frac; - - reg /*[7:0]*/ wf_fall_frac; - reg /*[7:0]*/ wf_rise_frac; - - reg [31:0] a; - reg [7:0] pm_rise_frac_filtered ; - reg [7:0] pm_fall_frac_filtered ; - reg [7:0] clkout0_divide_int; - reg [2:0] clkout0_divide_frac; - reg [7:0] even_part_high; - reg [7:0] even_part_low; - - reg [7:0] odd; - reg [7:0] odd_and_frac; - - reg [7:0] pm_fall; - reg [7:0] pm_rise; - reg [7:0] dt; - reg [7:0] dt_int; - reg [63:0] dt_calc; - - reg [7:0] pm_rise_frac; - reg [7:0] pm_fall_frac; - - reg [31:0] a_per_in_octets; - reg [31:0] a_phase_in_cycles; - - parameter precision = 0.125; - - reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 - reg [31: 0] phase_pos; - reg [31: 0] phase_vco; - reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - //convert phase to fixed - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - - // Return value is - // Transfer data - // RESERVED [37:36] - // FRAC_TIME [35:33] - // FRAC_WF_FALL [32] - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - - - clkout0_divide_frac = frac / 125; - clkout0_divide_int = divide; - - even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); - even_part_low = even_part_high; - - odd = clkout0_divide_int - even_part_high - even_part_low; - odd_and_frac = (8*odd) + clkout0_divide_frac; - - lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) - ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) - - pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 - pm_rise = 0; //0 - - wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) - wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) - - - - //Calculate phase in fractional cycles - a_per_in_octets = (8 * divide) + (frac / 125) ; - a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors - pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; - - dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) - dt = dt_calc[7:0]; - - pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; - - dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) - pm_fall_frac = pm_fall + pm_rise_frac; - pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; - - div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] - phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} - - mmcm_pll_frac_count_calc[37:0] = - { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, - 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], - 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits - } ; - - `ifdef DEBUG - $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); - `endif - - end -endfunction - diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/activehdl/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/activehdl/README.txt index 1e86f205..41a7053e 100644 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/activehdl/README.txt +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Mar 18 23:35:54 +0800 2023 +# Generated by export_simulation on Sun Mar 19 17:32:18 +0800 2023 # ################################################################################ diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/activehdl/fifo_AntCtrl.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/activehdl/fifo_AntCtrl.sh index 537a555a..b2bf6e8a 100644 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/activehdl/fifo_AntCtrl.sh +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/activehdl/fifo_AntCtrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Mar 18 23:35:54 +0800 2023 +# Generated by Vivado on Sun Mar 19 17:32:18 +0800 2023 # SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -93,11 +93,10 @@ setup() map_setup_file() { file="library.cfg" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then + if [[ ($1 != "") ]]; then lib_map_path="$1" else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + lib_map_path="D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/activehdl" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/ies/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/ies/README.txt index 47d88196..6eb1b70d 100644 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/ies/README.txt +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Mar 18 23:35:54 +0800 2023 +# Generated by export_simulation on Sun Mar 19 17:32:18 +0800 2023 # ################################################################################ diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/ies/fifo_AntCtrl.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/ies/fifo_AntCtrl.sh index cb4421dd..8e909e99 100644 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/ies/fifo_AntCtrl.sh +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/ies/fifo_AntCtrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Mar 18 23:35:54 +0800 2023 +# Generated by Vivado on Sun Mar 19 17:32:18 +0800 2023 # SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/modelsim/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/modelsim/README.txt index 1e86f205..41a7053e 100644 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/modelsim/README.txt +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Mar 18 23:35:54 +0800 2023 +# Generated by export_simulation on Sun Mar 19 17:32:18 +0800 2023 # ################################################################################ diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/modelsim/fifo_AntCtrl.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/modelsim/fifo_AntCtrl.sh index 04c7e097..02374a30 100644 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/modelsim/fifo_AntCtrl.sh +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/modelsim/fifo_AntCtrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Mar 18 23:35:54 +0800 2023 +# Generated by Vivado on Sun Mar 19 17:32:18 +0800 2023 # SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/questa/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/questa/README.txt index 1e86f205..41a7053e 100644 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/questa/README.txt +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Mar 18 23:35:54 +0800 2023 +# Generated by export_simulation on Sun Mar 19 17:32:18 +0800 2023 # ################################################################################ diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/questa/fifo_AntCtrl.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/questa/fifo_AntCtrl.sh index 4d215122..c120a04e 100644 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/questa/fifo_AntCtrl.sh +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/questa/fifo_AntCtrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Mar 18 23:35:54 +0800 2023 +# Generated by Vivado on Sun Mar 19 17:32:18 +0800 2023 # SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -102,11 +102,10 @@ setup() copy_setup_file() { file="modelsim.ini" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then + if [[ ($1 != "") ]]; then lib_map_path="$1" else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + lib_map_path="D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/riviera/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/riviera/README.txt index 1e86f205..41a7053e 100644 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/riviera/README.txt +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Mar 18 23:35:54 +0800 2023 +# Generated by export_simulation on Sun Mar 19 17:32:18 +0800 2023 # ################################################################################ diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/riviera/fifo_AntCtrl.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/riviera/fifo_AntCtrl.sh index 441bb4a7..142e0731 100644 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/riviera/fifo_AntCtrl.sh +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/riviera/fifo_AntCtrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Mar 18 23:35:54 +0800 2023 +# Generated by Vivado on Sun Mar 19 17:32:18 +0800 2023 # SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -93,11 +93,10 @@ setup() map_setup_file() { file="library.cfg" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then + if [[ ($1 != "") ]]; then lib_map_path="$1" else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + lib_map_path="D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/vcs/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/vcs/README.txt index 1e86f205..41a7053e 100644 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/vcs/README.txt +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Mar 18 23:35:54 +0800 2023 +# Generated by export_simulation on Sun Mar 19 17:32:18 +0800 2023 # ################################################################################ diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/vcs/fifo_AntCtrl.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/vcs/fifo_AntCtrl.sh index ff002536..a42edf34 100644 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/vcs/fifo_AntCtrl.sh +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/vcs/fifo_AntCtrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Mar 18 23:35:54 +0800 2023 +# Generated by Vivado on Sun Mar 19 17:32:18 +0800 2023 # SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/xcelium/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/xcelium/README.txt index 47d88196..6eb1b70d 100644 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/xcelium/README.txt +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Mar 18 23:35:54 +0800 2023 +# Generated by export_simulation on Sun Mar 19 17:32:18 +0800 2023 # ################################################################################ diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/xcelium/fifo_AntCtrl.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/xcelium/fifo_AntCtrl.sh index c5b22164..ac3d2a19 100644 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/xcelium/fifo_AntCtrl.sh +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/xcelium/fifo_AntCtrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Mar 18 23:35:54 +0800 2023 +# Generated by Vivado on Sun Mar 19 17:32:18 +0800 2023 # SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/xsim/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/xsim/README.txt index 1e86f205..41a7053e 100644 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/xsim/README.txt +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Mar 18 23:35:54 +0800 2023 +# Generated by export_simulation on Sun Mar 19 17:32:18 +0800 2023 # ################################################################################ diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/xsim/fifo_AntCtrl.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/xsim/fifo_AntCtrl.sh index d8873f5a..4fbd08be 100644 --- a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/xsim/fifo_AntCtrl.sh +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/fifo_AntCtrl/xsim/fifo_AntCtrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Mar 18 23:35:54 +0800 2023 +# Generated by Vivado on Sun Mar 19 17:32:18 +0800 2023 # SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/README.txt new file mode 100644 index 00000000..8965a407 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Mar 19 18:25:33 +0800 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./selectio_lvds_rx.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './selectio_lvds_rx.sh' script. + +./selectio_lvds_rx.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./selectio_lvds_rx.sh -noclean_files + +For more information on the script, please type './selectio_lvds_rx.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/compile.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/compile.do new file mode 100644 index 00000000..322d8d25 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/compile.do @@ -0,0 +1,23 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v" \ +"../../../ip/selectio_lvds_rx/selectio_lvds_rx.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/file_info.txt new file mode 100644 index 00000000..6d7cb2d8 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +selectio_lvds_rx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v, +selectio_lvds_rx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/selectio_lvds_rx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/selectio_lvds_rx.sh new file mode 100644 index 00000000..4aaefff4 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/selectio_lvds_rx.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : selectio_lvds_rx.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Mar 19 18:25:33 +0800 2023 +# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: selectio_lvds_rx.sh [-help] +# usage: selectio_lvds_rx.sh [-lib_map_path] +# usage: selectio_lvds_rx.sh [-noclean_files] +# usage: selectio_lvds_rx.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'selectio_lvds_rx.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "selectio_lvds_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_rx.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/activehdl" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_rx.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: selectio_lvds_rx.sh [-help]\n\ +Usage: selectio_lvds_rx.sh [-lib_map_path]\n\ +Usage: selectio_lvds_rx.sh [-reset_run]\n\ +Usage: selectio_lvds_rx.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/.Vivado_Synthesis.queue.rst b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/selectio_lvds_rx.udo similarity index 100% rename from projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/.Vivado_Synthesis.queue.rst rename to projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/selectio_lvds_rx.udo diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/simulate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/simulate.do new file mode 100644 index 00000000..1232b429 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+selectio_lvds_rx -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.selectio_lvds_rx xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {selectio_lvds_rx.udo} + +run -all + +endsim + +quit -force diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/wave.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/README.txt new file mode 100644 index 00000000..c7a8bbf2 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Mar 19 18:25:33 +0800 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./selectio_lvds_rx.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './selectio_lvds_rx.sh' script. + +./selectio_lvds_rx.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./selectio_lvds_rx.sh -noclean_files + +For more information on the script, please type './selectio_lvds_rx.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/file_info.txt new file mode 100644 index 00000000..6d7cb2d8 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +selectio_lvds_rx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v, +selectio_lvds_rx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/run.f b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/run.f new file mode 100644 index 00000000..44edac75 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/run.f @@ -0,0 +1,15 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v" \ + "../../../ip/selectio_lvds_rx/selectio_lvds_rx.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/selectio_lvds_rx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/selectio_lvds_rx.sh new file mode 100644 index 00000000..38cec837 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/ies/selectio_lvds_rx.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : selectio_lvds_rx.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Mar 19 18:25:33 +0800 2023 +# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: selectio_lvds_rx.sh [-help] +# usage: selectio_lvds_rx.sh [-lib_map_path] +# usage: selectio_lvds_rx.sh [-noclean_files] +# usage: selectio_lvds_rx.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'selectio_lvds_rx.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "selectio_lvds_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.selectio_lvds_rx \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_rx.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_rx.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: selectio_lvds_rx.sh [-help]\n\ +Usage: selectio_lvds_rx.sh [-lib_map_path]\n\ +Usage: selectio_lvds_rx.sh [-reset_run]\n\ +Usage: selectio_lvds_rx.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/README.txt new file mode 100644 index 00000000..8965a407 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Mar 19 18:25:33 +0800 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./selectio_lvds_rx.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './selectio_lvds_rx.sh' script. + +./selectio_lvds_rx.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./selectio_lvds_rx.sh -noclean_files + +For more information on the script, please type './selectio_lvds_rx.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/compile.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/compile.do new file mode 100644 index 00000000..093e666c --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/compile.do @@ -0,0 +1,15 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xil_defaultlib -64 -incr \ +"../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v" \ +"../../../ip/selectio_lvds_rx/selectio_lvds_rx.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/file_info.txt new file mode 100644 index 00000000..27843160 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/file_info.txt @@ -0,0 +1,3 @@ +selectio_lvds_rx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v, +selectio_lvds_rx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/modelsim.ini b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/modelsim.ini new file mode 100644 index 00000000..04a43f2c --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/modelsim.ini @@ -0,0 +1,2590 @@ +; vsim modelsim.ini file +[Version] +INIVersion = "2020.4" + +; Copyright 1991-2020 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini +; +; VITAL concerns: +; +; The library ieee contains (among other packages) the packages of the +; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use +; the physical library ieee (recommended), or use the physical library +; vital2000, but not both. The design can use logical library ieee and/or +; vital2000 as long as each of these maps to the same physical library, either +; ieee or vital2000. +; +; A design using the 1995 version of the VITAL packages, whether or not +; it also uses the 2000 version of the VITAL packages, must have logical library +; name ieee mapped to physical library vital1995. (A design cannot use library +; vital1995 directly because some packages in this library use logical name ieee +; when referring to the other packages in the library.) The design source +; should use logical name ieee when referring to any packages there except the +; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical +; name vital2000 (mapped to physical library vital2000) to refer to those +; packages. +; ieee = $MODEL_TECH/../vital1995 +; +; For compatiblity with previous releases, logical library name vital2000 maps +; to library vital2000 (a different library than library ieee, containing the +; same packages). +; A design should not reference VITAL from both the ieee library and the +; vital2000 library because the vital packages are effectively different. +; A design that references both the ieee and vital2000 libraries must have +; both logical names ieee and vital2000 mapped to the same library, either of +; these: +; $MODEL_TECH/../ieee +; $MODEL_TECH/../vital2000 +; + +; added mapping for ADMS + +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib + +; Automatically perform logical->physical mapping for physical libraries that +; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). +; The tail of the filesystem path name is chosen as the logical library name. +; For example, in the command "vopt -L ./path/to/lib1 -o opttop top", +; vopt automatically performs the mapping "lib1 -> ./path/to/lib1". +; See the User Manual for more details. +; +; AutoLibMapping = 0 + +secureip = C:/Mentor/CompLib/2019.1.3/secureip +unisim = C:/Mentor/CompLib/2019.1.3/unisim +unimacro = C:/Mentor/CompLib/2019.1.3/unimacro +unifast = C:/Mentor/CompLib/2019.1.3/unifast +unisims_ver = C:/Mentor/CompLib/2019.1.3/unisims_ver +unimacro_ver = C:/Mentor/CompLib/2019.1.3/unimacro_ver +unifast_ver = C:/Mentor/CompLib/2019.1.3/unifast_ver +simprims_ver = C:/Mentor/CompLib/2019.1.3/simprims_ver +xpm = C:/Mentor/CompLib/2019.1.3/xpm +xilinx_vip = C:/Mentor/CompLib/2019.1.3/xilinx_vip +advanced_io_wizard_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/advanced_io_wizard_phy_v1_0_0 +advanced_io_wizard_v1_0_0 = C:/Mentor/CompLib/2019.1.3/advanced_io_wizard_v1_0_0 +ahblite_axi_bridge_v3_0_14 = C:/Mentor/CompLib/2019.1.3/ahblite_axi_bridge_v3_0_14 +ai_noc = C:/Mentor/CompLib/2019.1.3/ai_noc +ai_pl_trig = C:/Mentor/CompLib/2019.1.3/ai_pl_trig +ai_pl = C:/Mentor/CompLib/2019.1.3/ai_pl +audio_clock_recovery_v1_0 = C:/Mentor/CompLib/2019.1.3/audio_clock_recovery_v1_0 +audio_tpg_v1_0_0 = C:/Mentor/CompLib/2019.1.3/audio_tpg_v1_0_0 +av_pat_gen_v1_0_0 = C:/Mentor/CompLib/2019.1.3/av_pat_gen_v1_0_0 +axis_infrastructure_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axis_infrastructure_v1_1_0 +axis_protocol_checker_v2_0_3 = C:/Mentor/CompLib/2019.1.3/axis_protocol_checker_v2_0_3 +axi_ahblite_bridge_v3_0_16 = C:/Mentor/CompLib/2019.1.3/axi_ahblite_bridge_v3_0_16 +axi_amm_bridge_v1_0_9 = C:/Mentor/CompLib/2019.1.3/axi_amm_bridge_v1_0_9 +axi_bram_ctrl_v4_1_1 = C:/Mentor/CompLib/2019.1.3/axi_bram_ctrl_v4_1_1 +axi_chip2chip_v5_0_6 = C:/Mentor/CompLib/2019.1.3/axi_chip2chip_v5_0_6 +axi_dbg_hub = C:/Mentor/CompLib/2019.1.3/axi_dbg_hub +axi_infrastructure_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axi_infrastructure_v1_1_0 +axi_jtag_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_jtag_v1_0_0 +axi_lite_ipif_v3_0_4 = C:/Mentor/CompLib/2019.1.3/axi_lite_ipif_v3_0_4 +axi_pcie3_v3_0_9 = C:/Mentor/CompLib/2019.1.3/axi_pcie3_v3_0_9 +axi_perf_mon_v5_0_21 = C:/Mentor/CompLib/2019.1.3/axi_perf_mon_v5_0_21 +axi_pmon_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_pmon_v1_0_0 +blk_mem_gen_v8_3_6 = C:/Mentor/CompLib/2019.1.3/blk_mem_gen_v8_3_6 +blk_mem_gen_v8_4_3 = C:/Mentor/CompLib/2019.1.3/blk_mem_gen_v8_4_3 +bsip_v1_1_0 = C:/Mentor/CompLib/2019.1.3/bsip_v1_1_0 +bs_mux_v1_0_0 = C:/Mentor/CompLib/2019.1.3/bs_mux_v1_0_0 +clk_gen_sim_v1_0_0 = C:/Mentor/CompLib/2019.1.3/clk_gen_sim_v1_0_0 +clk_vip_v1_0_2 = C:/Mentor/CompLib/2019.1.3/clk_vip_v1_0_2 +cmac_usplus_v2_4_5 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_4_5 +cmac_usplus_v2_5_3 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_5_3 +cmac_usplus_v2_6_2 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_6_2 +cmac_v2_3_5 = C:/Mentor/CompLib/2019.1.3/cmac_v2_3_5 +cmac_v2_4_1 = C:/Mentor/CompLib/2019.1.3/cmac_v2_4_1 +cmac_v2_5_1 = C:/Mentor/CompLib/2019.1.3/cmac_v2_5_1 +compact_gt_v1_0_5 = C:/Mentor/CompLib/2019.1.3/compact_gt_v1_0_5 +ddr4_pl_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/ddr4_pl_phy_v1_0_0 +ddr4_pl_v1_0_2 = C:/Mentor/CompLib/2019.1.3/ddr4_pl_v1_0_2 +dist_mem_gen_v8_0_13 = C:/Mentor/CompLib/2019.1.3/dist_mem_gen_v8_0_13 +ecc_v2_0_13 = C:/Mentor/CompLib/2019.1.3/ecc_v2_0_13 +emb_fifo_gen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/emb_fifo_gen_v1_0_1 +emb_mem_gen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/emb_mem_gen_v1_0_1 +emc_common_v3_0_5 = C:/Mentor/CompLib/2019.1.3/emc_common_v3_0_5 +ethernet_1_10_25g_v2_0_5 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_0_5 +ethernet_1_10_25g_v2_1_4 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_1_4 +ethernet_1_10_25g_v2_2_3 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_2_3 +ethernet_1_10_25g_v2_3_3 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_3_3 +fifo_generator_v13_0_6 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_0_6 +fifo_generator_v13_1_4 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_1_4 +fifo_generator_v13_2_4 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_2_4 +fit_timer_v2_0_10 = C:/Mentor/CompLib/2019.1.3/fit_timer_v2_0_10 +generic_baseblocks_v2_1_0 = C:/Mentor/CompLib/2019.1.3/generic_baseblocks_v2_1_0 +gigantic_mux = C:/Mentor/CompLib/2019.1.3/gigantic_mux +gig_ethernet_pcs_pma_v16_1_6 = C:/Mentor/CompLib/2019.1.3/gig_ethernet_pcs_pma_v16_1_6 +gmii_to_rgmii_v4_0_7 = C:/Mentor/CompLib/2019.1.3/gmii_to_rgmii_v4_0_7 +gtwizard_ultrascale_v1_5_4 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_5_4 +gtwizard_ultrascale_v1_6_11 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_6_11 +gtwizard_ultrascale_v1_7_6 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_7_6 +hbm_v1_0_4 = C:/Mentor/CompLib/2019.1.3/hbm_v1_0_4 +hdcp22_cipher_dp_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdcp22_cipher_dp_v1_0_0 +hdcp22_cipher_v1_0_3 = C:/Mentor/CompLib/2019.1.3/hdcp22_cipher_v1_0_3 +hdcp22_rng_v1_0_1 = C:/Mentor/CompLib/2019.1.3/hdcp22_rng_v1_0_1 +hdcp_keymngmt_blk_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdcp_keymngmt_blk_v1_0_0 +hdcp_v1_0_3 = C:/Mentor/CompLib/2019.1.3/hdcp_v1_0_3 +hdmi_gt_controller_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdmi_gt_controller_v1_0_0 +high_speed_selectio_wiz_v3_2_3 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_2_3 +high_speed_selectio_wiz_v3_3_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_3_1 +high_speed_selectio_wiz_v3_4_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_4_1 +high_speed_selectio_wiz_v3_5_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_5_1 +i2s_receiver_v1_0_3 = C:/Mentor/CompLib/2019.1.3/i2s_receiver_v1_0_3 +i2s_transmitter_v1_0_3 = C:/Mentor/CompLib/2019.1.3/i2s_transmitter_v1_0_3 +ibert_lib_v1_0_6 = C:/Mentor/CompLib/2019.1.3/ibert_lib_v1_0_6 +ieee802d3_clause74_fec_v1_0_4 = C:/Mentor/CompLib/2019.1.3/ieee802d3_clause74_fec_v1_0_4 +interlaken_v2_4_3 = C:/Mentor/CompLib/2019.1.3/interlaken_v2_4_3 +in_system_ibert_v1_0_9 = C:/Mentor/CompLib/2019.1.3/in_system_ibert_v1_0_9 +iomodule_v3_1_4 = C:/Mentor/CompLib/2019.1.3/iomodule_v3_1_4 +jesd204c_v4_1_1 = C:/Mentor/CompLib/2019.1.3/jesd204c_v4_1_1 +jesd204_v7_2_6 = C:/Mentor/CompLib/2019.1.3/jesd204_v7_2_6 +jtag_axi = C:/Mentor/CompLib/2019.1.3/jtag_axi +lib_cdc_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_cdc_v1_0_2 +lib_pkg_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_pkg_v1_0_2 +lmb_bram_if_cntlr_v4_0_16 = C:/Mentor/CompLib/2019.1.3/lmb_bram_if_cntlr_v4_0_16 +lmb_v10_v3_0_9 = C:/Mentor/CompLib/2019.1.3/lmb_v10_v3_0_9 +ltlib_v1_0_0 = C:/Mentor/CompLib/2019.1.3/ltlib_v1_0_0 +lut_buffer_v1_0_0 = C:/Mentor/CompLib/2019.1.3/lut_buffer_v1_0_0 +lut_buffer_v2_0_0 = C:/Mentor/CompLib/2019.1.3/lut_buffer_v2_0_0 +l_ethernet_v2_3_5 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_3_5 +l_ethernet_v2_4_3 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_4_3 +l_ethernet_v2_5_2 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_5_2 +mammoth_transcode_v1_0_0 = C:/Mentor/CompLib/2019.1.3/mammoth_transcode_v1_0_0 +microblaze_v10_0_7 = C:/Mentor/CompLib/2019.1.3/microblaze_v10_0_7 +microblaze_v11_0_1 = C:/Mentor/CompLib/2019.1.3/microblaze_v11_0_1 +microblaze_v9_5_4 = C:/Mentor/CompLib/2019.1.3/microblaze_v9_5_4 +mii_to_rmii_v2_0_21 = C:/Mentor/CompLib/2019.1.3/mii_to_rmii_v2_0_21 +mipi_csi2_rx_ctrl_v1_0_8 = C:/Mentor/CompLib/2019.1.3/mipi_csi2_rx_ctrl_v1_0_8 +mipi_csi2_tx_ctrl_v1_0_4 = C:/Mentor/CompLib/2019.1.3/mipi_csi2_tx_ctrl_v1_0_4 +mipi_dphy_v4_1_4 = C:/Mentor/CompLib/2019.1.3/mipi_dphy_v4_1_4 +mipi_dsi_tx_ctrl_v1_0_7 = C:/Mentor/CompLib/2019.1.3/mipi_dsi_tx_ctrl_v1_0_7 +mrmac_v1_0_0 = C:/Mentor/CompLib/2019.1.3/mrmac_v1_0_0 +multi_channel_25g_rs_fec_v1_0_5 = C:/Mentor/CompLib/2019.1.3/multi_channel_25g_rs_fec_v1_0_5 +mutex_v2_1_10 = C:/Mentor/CompLib/2019.1.3/mutex_v2_1_10 +axi_tg_lib = C:/Mentor/CompLib/2019.1.3/axi_tg_lib +noc_na_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_na_v1_0_0 +noc_nidb_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nidb_v1_0_0 +noc_nmu_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nmu_v1_0_0 +noc_nps_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nps_v1_0_0 +nvmeha_v1_0_0 = C:/Mentor/CompLib/2019.1.3/nvmeha_v1_0_0 +oddr_v1_0_0 = C:/Mentor/CompLib/2019.1.3/oddr_v1_0_0 +pci32_v5_0_12 = C:/Mentor/CompLib/2019.1.3/pci32_v5_0_12 +pci64_v5_0_11 = C:/Mentor/CompLib/2019.1.3/pci64_v5_0_11 +pcie_jtag_v1_0_0 = C:/Mentor/CompLib/2019.1.3/pcie_jtag_v1_0_0 +pc_cfr_v6_0_8 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_0_8 +pc_cfr_v6_1_4 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_1_4 +pc_cfr_v6_2_2 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_2_2 +pc_cfr_v6_3_0 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_3_0 +picxo = C:/Mentor/CompLib/2019.1.3/picxo +qdma_v3_0_2 = C:/Mentor/CompLib/2019.1.3/qdma_v3_0_2 +rama_v1_1_2_lib = C:/Mentor/CompLib/2019.1.3/rama_v1_1_2_lib +rld3_pl_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/rld3_pl_phy_v1_0_0 +rld3_pl_v1_0_1 = C:/Mentor/CompLib/2019.1.3/rld3_pl_v1_0_1 +roe_framer_v2_0_1 = C:/Mentor/CompLib/2019.1.3/roe_framer_v2_0_1 +rst_vip_v1_0_3 = C:/Mentor/CompLib/2019.1.3/rst_vip_v1_0_3 +smartconnect_v1_0 = C:/Mentor/CompLib/2019.1.3/smartconnect_v1_0 +sd_fec_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sd_fec_v1_0_2 +sem_ultra_v3_1_11 = C:/Mentor/CompLib/2019.1.3/sem_ultra_v3_1_11 +sem_v4_1_12 = C:/Mentor/CompLib/2019.1.3/sem_v4_1_12 +shell_utils_msp432_bsl_crc_gen_v1_0_0 = C:/Mentor/CompLib/2019.1.3/shell_utils_msp432_bsl_crc_gen_v1_0_0 +sim_clk_gen_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sim_clk_gen_v1_0_2 +sim_rst_gen_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sim_rst_gen_v1_0_2 +sim_trig_top_v1_0 = C:/Mentor/CompLib/2019.1.3/sim_trig_top_v1_0 +stm_v1_0 = C:/Mentor/CompLib/2019.1.3/stm_v1_0 +stm_v1_0_0 = C:/Mentor/CompLib/2019.1.3/stm_v1_0_0 +system_cache_v4_0_6 = C:/Mentor/CompLib/2019.1.3/system_cache_v4_0_6 +ta_dma_v1_0_3 = C:/Mentor/CompLib/2019.1.3/ta_dma_v1_0_3 +tcc_decoder_3gpplte_v3_0_6 = C:/Mentor/CompLib/2019.1.3/tcc_decoder_3gpplte_v3_0_6 +ten_gig_eth_mac_v15_1_7 = C:/Mentor/CompLib/2019.1.3/ten_gig_eth_mac_v15_1_7 +ten_gig_eth_pcs_pma_v6_0_15 = C:/Mentor/CompLib/2019.1.3/ten_gig_eth_pcs_pma_v6_0_15 +timer_sync_1588_v1_2_4 = C:/Mentor/CompLib/2019.1.3/timer_sync_1588_v1_2_4 +tmr_inject_v1_0_3 = C:/Mentor/CompLib/2019.1.3/tmr_inject_v1_0_3 +tmr_manager_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tmr_manager_v1_0_4 +tmr_voter_v1_0_2 = C:/Mentor/CompLib/2019.1.3/tmr_voter_v1_0_2 +tsn_endpoint_ethernet_mac_block_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tsn_endpoint_ethernet_mac_block_v1_0_4 +uhdsdi_gt_v1_0_3 = C:/Mentor/CompLib/2019.1.3/uhdsdi_gt_v1_0_3 +uhdsdi_gt_v2_0_0 = C:/Mentor/CompLib/2019.1.3/uhdsdi_gt_v2_0_0 +usxgmii_v1_0_5 = C:/Mentor/CompLib/2019.1.3/usxgmii_v1_0_5 +usxgmii_v1_1_0 = C:/Mentor/CompLib/2019.1.3/usxgmii_v1_1_0 +util_idelay_ctrl_v1_0_1 = C:/Mentor/CompLib/2019.1.3/util_idelay_ctrl_v1_0_1 +util_reduced_logic_v2_0_4 = C:/Mentor/CompLib/2019.1.3/util_reduced_logic_v2_0_4 +util_vector_logic_v2_0_1 = C:/Mentor/CompLib/2019.1.3/util_vector_logic_v2_0_1 +ba317 = C:/Mentor/CompLib/2019.1.3/ba317 +vfb_v1_0_13 = C:/Mentor/CompLib/2019.1.3/vfb_v1_0_13 +video_frame_crc_v1_0_1 = C:/Mentor/CompLib/2019.1.3/video_frame_crc_v1_0_1 +vid_edid_v1_0_0 = C:/Mentor/CompLib/2019.1.3/vid_edid_v1_0_0 +vid_phy_controller_v2_1_5 = C:/Mentor/CompLib/2019.1.3/vid_phy_controller_v2_1_5 +vid_phy_controller_v2_2_3 = C:/Mentor/CompLib/2019.1.3/vid_phy_controller_v2_2_3 +v_axi4s_remap_v1_0_11 = C:/Mentor/CompLib/2019.1.3/v_axi4s_remap_v1_0_11 +v_csc_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_csc_v1_0_13 +v_deinterlacer_v4_0_12 = C:/Mentor/CompLib/2019.1.3/v_deinterlacer_v4_0_12 +v_deinterlacer_v5_0_13 = C:/Mentor/CompLib/2019.1.3/v_deinterlacer_v5_0_13 +v_demosaic_v1_0_5 = C:/Mentor/CompLib/2019.1.3/v_demosaic_v1_0_5 +v_frmbuf_rd_v2_1_2 = C:/Mentor/CompLib/2019.1.3/v_frmbuf_rd_v2_1_2 +v_frmbuf_wr_v2_1_2 = C:/Mentor/CompLib/2019.1.3/v_frmbuf_wr_v2_1_2 +v_gamma_lut_v1_0_5 = C:/Mentor/CompLib/2019.1.3/v_gamma_lut_v1_0_5 +v_hcresampler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_hcresampler_v1_0_13 +v_hdmi_rx_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_rx_v2_0_0 +v_hdmi_rx_v3_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_rx_v3_0_0 +v_hdmi_tx_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_tx_v2_0_0 +v_hdmi_tx_v3_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_tx_v3_0_0 +v_hscaler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_hscaler_v1_0_13 +v_letterbox_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_letterbox_v1_0_13 +v_mix_v3_0_3 = C:/Mentor/CompLib/2019.1.3/v_mix_v3_0_3 +v_mix_v4_0_0 = C:/Mentor/CompLib/2019.1.3/v_mix_v4_0_0 +v_multi_scaler_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_multi_scaler_v1_0_1 +v_scenechange_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_scenechange_v1_0_1 +v_sdi_rx_vid_bridge_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_sdi_rx_vid_bridge_v2_0_0 +v_smpte_sdi_v3_0_8 = C:/Mentor/CompLib/2019.1.3/v_smpte_sdi_v3_0_8 +v_smpte_uhdsdi_rx_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_rx_v1_0_0 +v_smpte_uhdsdi_tx_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_tx_v1_0_0 +v_smpte_uhdsdi_v1_0_7 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_v1_0_7 +v_tpg_v7_0_13 = C:/Mentor/CompLib/2019.1.3/v_tpg_v7_0_13 +v_tpg_v8_0_1 = C:/Mentor/CompLib/2019.1.3/v_tpg_v8_0_1 +v_uhdsdi_audio_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v1_0_0 +v_uhdsdi_audio_v1_1_0 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v1_1_0 +v_uhdsdi_audio_v2_0_1 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v2_0_1 +v_uhdsdi_vidgen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_vidgen_v1_0_1 +v_vcresampler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_vcresampler_v1_0_13 +v_vid_in_axi4s_v4_0_9 = C:/Mentor/CompLib/2019.1.3/v_vid_in_axi4s_v4_0_9 +v_vscaler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_vscaler_v1_0_13 +xaui_v12_3_6 = C:/Mentor/CompLib/2019.1.3/xaui_v12_3_6 +xbip_dsp48_wrapper_v3_0_4 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_wrapper_v3_0_4 +xbip_utils_v3_0_10 = C:/Mentor/CompLib/2019.1.3/xbip_utils_v3_0_10 +xdma_v4_1_3 = C:/Mentor/CompLib/2019.1.3/xdma_v4_1_3 +xhmc_v1_0_9 = C:/Mentor/CompLib/2019.1.3/xhmc_v1_0_9 +xlconcat_v2_1_3 = C:/Mentor/CompLib/2019.1.3/xlconcat_v2_1_3 +xlconstant_v1_1_6 = C:/Mentor/CompLib/2019.1.3/xlconstant_v1_1_6 +xlslice_v1_0_2 = C:/Mentor/CompLib/2019.1.3/xlslice_v1_0_2 +xsdbm_v2_0_0 = C:/Mentor/CompLib/2019.1.3/xsdbm_v2_0_0 +xsdbm_v3_0_0 = C:/Mentor/CompLib/2019.1.3/xsdbm_v3_0_0 +xxv_ethernet_v2_4_5 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v2_4_5 +xxv_ethernet_v2_5_3 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v2_5_3 +xxv_ethernet_v3_0_3 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v3_0_3 +zynq_ultra_ps_e_v3_2_3 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_v3_2_3 +zynq_ultra_ps_e_v3_3_0 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_v3_3_0 +lib_srl_fifo_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_srl_fifo_v1_0_2 +lib_fifo_v1_0_13 = C:/Mentor/CompLib/2019.1.3/lib_fifo_v1_0_13 +axi_datamover_v5_1_21 = C:/Mentor/CompLib/2019.1.3/axi_datamover_v5_1_21 +amm_axi_bridge_v1_0_5 = C:/Mentor/CompLib/2019.1.3/amm_axi_bridge_v1_0_5 +axis_interconnect_v1_1_17 = C:/Mentor/CompLib/2019.1.3/axis_interconnect_v1_1_17 +ats_switch_v1_0_2 = C:/Mentor/CompLib/2019.1.3/ats_switch_v1_0_2 +audio_formatter_v1_0_1 = C:/Mentor/CompLib/2019.1.3/audio_formatter_v1_0_1 +axi4stream_vip_v1_1_5 = C:/Mentor/CompLib/2019.1.3/axi4stream_vip_v1_1_5 +v_tc_v6_1_13 = C:/Mentor/CompLib/2019.1.3/v_tc_v6_1_13 +v_axi4s_vid_out_v4_0_10 = C:/Mentor/CompLib/2019.1.3/v_axi4s_vid_out_v4_0_10 +axi4svideo_bridge_v1_0_10 = C:/Mentor/CompLib/2019.1.3/axi4svideo_bridge_v1_0_10 +axis_accelerator_adapter_v2_1_15 = C:/Mentor/CompLib/2019.1.3/axis_accelerator_adapter_v2_1_15 +axis_broadcaster_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axis_broadcaster_v1_1_18 +axis_clock_converter_v1_1_20 = C:/Mentor/CompLib/2019.1.3/axis_clock_converter_v1_1_20 +axis_combiner_v1_1_17 = C:/Mentor/CompLib/2019.1.3/axis_combiner_v1_1_17 +axis_data_fifo_v1_1_20 = C:/Mentor/CompLib/2019.1.3/axis_data_fifo_v1_1_20 +axis_data_fifo_v2_0_1 = C:/Mentor/CompLib/2019.1.3/axis_data_fifo_v2_0_1 +axis_register_slice_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_register_slice_v1_1_19 +axis_dwidth_converter_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axis_dwidth_converter_v1_1_18 +axis_subset_converter_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_subset_converter_v1_1_19 +axis_switch_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_switch_v1_1_19 +axis_vio_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axis_vio_v1_0_0 +axi_apb_bridge_v3_0_15 = C:/Mentor/CompLib/2019.1.3/axi_apb_bridge_v3_0_15 +axi_bram_ctrl_v4_0_14 = C:/Mentor/CompLib/2019.1.3/axi_bram_ctrl_v4_0_14 +axi_sg_v4_1_12 = C:/Mentor/CompLib/2019.1.3/axi_sg_v4_1_12 +axi_cdma_v4_1_19 = C:/Mentor/CompLib/2019.1.3/axi_cdma_v4_1_19 +axi_clock_converter_v2_1_18 = C:/Mentor/CompLib/2019.1.3/axi_clock_converter_v2_1_18 +axi_data_fifo_v2_1_18 = C:/Mentor/CompLib/2019.1.3/axi_data_fifo_v2_1_18 +axi_register_slice_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_register_slice_v2_1_19 +axi_crossbar_v2_1_20 = C:/Mentor/CompLib/2019.1.3/axi_crossbar_v2_1_20 +axi_dma_v7_1_20 = C:/Mentor/CompLib/2019.1.3/axi_dma_v7_1_20 +axi_protocol_converter_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_protocol_converter_v2_1_19 +axi_dwidth_converter_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_dwidth_converter_v2_1_19 +axi_emc_v3_0_19 = C:/Mentor/CompLib/2019.1.3/axi_emc_v3_0_19 +axi_epc_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_epc_v2_0_22 +lib_bmg_v1_0_12 = C:/Mentor/CompLib/2019.1.3/lib_bmg_v1_0_12 +axi_ethernetlite_v3_0_17 = C:/Mentor/CompLib/2019.1.3/axi_ethernetlite_v3_0_17 +axi_ethernet_buffer_v2_0_20 = C:/Mentor/CompLib/2019.1.3/axi_ethernet_buffer_v2_0_20 +axi_fifo_mm_s_v4_1_16 = C:/Mentor/CompLib/2019.1.3/axi_fifo_mm_s_v4_1_16 +axi_fifo_mm_s_v4_2_1 = C:/Mentor/CompLib/2019.1.3/axi_fifo_mm_s_v4_2_1 +axi_firewall_v1_0_7 = C:/Mentor/CompLib/2019.1.3/axi_firewall_v1_0_7 +interrupt_control_v3_1_4 = C:/Mentor/CompLib/2019.1.3/interrupt_control_v3_1_4 +axi_gpio_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_gpio_v2_0_21 +axi_hwicap_v3_0_23 = C:/Mentor/CompLib/2019.1.3/axi_hwicap_v3_0_23 +axi_iic_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_iic_v2_0_22 +axi_intc_v4_1_13 = C:/Mentor/CompLib/2019.1.3/axi_intc_v4_1_13 +axi_interconnect_v1_7_16 = C:/Mentor/CompLib/2019.1.3/axi_interconnect_v1_7_16 +axi_master_burst_v2_0_7 = C:/Mentor/CompLib/2019.1.3/axi_master_burst_v2_0_7 +axi_msg_v1_0_5 = C:/Mentor/CompLib/2019.1.3/axi_msg_v1_0_5 +axi_mcdma_v1_0_5 = C:/Mentor/CompLib/2019.1.3/axi_mcdma_v1_0_5 +axi_mcdma_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axi_mcdma_v1_1_0 +axi_memory_init_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_memory_init_v1_0_0 +axi_mm2s_mapper_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axi_mm2s_mapper_v1_1_18 +axi_mmu_v2_1_17 = C:/Mentor/CompLib/2019.1.3/axi_mmu_v2_1_17 +axi_pcie_v2_9_1 = C:/Mentor/CompLib/2019.1.3/axi_pcie_v2_9_1 +axi_protocol_checker_v2_0_5 = C:/Mentor/CompLib/2019.1.3/axi_protocol_checker_v2_0_5 +axi_quad_spi_v3_2_18 = C:/Mentor/CompLib/2019.1.3/axi_quad_spi_v3_2_18 +axi_sideband_util_v1_0_3 = C:/Mentor/CompLib/2019.1.3/axi_sideband_util_v1_0_3 +axi_tft_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_tft_v2_0_22 +axi_timebase_wdt_v3_0_11 = C:/Mentor/CompLib/2019.1.3/axi_timebase_wdt_v3_0_11 +axi_timer_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_timer_v2_0_21 +axi_traffic_gen_v2_0_20 = C:/Mentor/CompLib/2019.1.3/axi_traffic_gen_v2_0_20 +axi_traffic_gen_v3_0_5 = C:/Mentor/CompLib/2019.1.3/axi_traffic_gen_v3_0_5 +axi_uart16550_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_uart16550_v2_0_21 +axi_uartlite_v2_0_23 = C:/Mentor/CompLib/2019.1.3/axi_uartlite_v2_0_23 +axi_usb2_device_v5_0_20 = C:/Mentor/CompLib/2019.1.3/axi_usb2_device_v5_0_20 +axi_utils_v2_0_6 = C:/Mentor/CompLib/2019.1.3/axi_utils_v2_0_6 +axi_vdma_v6_3_7 = C:/Mentor/CompLib/2019.1.3/axi_vdma_v6_3_7 +xbip_pipe_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_pipe_v3_0_6 +xbip_dsp48_addsub_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_addsub_v3_0_6 +xbip_addsub_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_addsub_v3_0_6 +c_reg_fd_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_reg_fd_v12_0_6 +c_addsub_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_addsub_v12_0_13 +axi_vfifo_ctrl_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_vfifo_ctrl_v2_0_21 +axi_vip_v1_1_5 = C:/Mentor/CompLib/2019.1.3/axi_vip_v1_1_5 +bs_switch_v1_0_0 = C:/Mentor/CompLib/2019.1.3/bs_switch_v1_0_0 +canfd_v2_0_1 = C:/Mentor/CompLib/2019.1.3/canfd_v2_0_1 +can_v5_0_22 = C:/Mentor/CompLib/2019.1.3/can_v5_0_22 +cic_compiler_v4_0_14 = C:/Mentor/CompLib/2019.1.3/cic_compiler_v4_0_14 +xbip_bram18k_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_bram18k_v3_0_6 +mult_gen_v12_0_15 = C:/Mentor/CompLib/2019.1.3/mult_gen_v12_0_15 +cmpy_v6_0_17 = C:/Mentor/CompLib/2019.1.3/cmpy_v6_0_17 +c_mux_bit_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_mux_bit_v12_0_6 +c_shift_ram_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_shift_ram_v12_0_13 +c_mux_bus_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_mux_bus_v12_0_6 +c_gate_bit_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_gate_bit_v12_0_6 +xbip_counter_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_counter_v3_0_6 +c_counter_binary_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_counter_binary_v12_0_13 +c_compare_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_compare_v12_0_6 +convolution_v9_0_14 = C:/Mentor/CompLib/2019.1.3/convolution_v9_0_14 +cordic_v6_0_15 = C:/Mentor/CompLib/2019.1.3/cordic_v6_0_15 +cpri_v8_10_3 = C:/Mentor/CompLib/2019.1.3/cpri_v8_10_3 +xbip_dsp48_acc_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_acc_v3_0_6 +xbip_accum_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_accum_v3_0_6 +c_accum_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_accum_v12_0_13 +xbip_dsp48_multadd_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_multadd_v3_0_6 +dds_compiler_v6_0_18 = C:/Mentor/CompLib/2019.1.3/dds_compiler_v6_0_18 +dft_v4_0_16 = C:/Mentor/CompLib/2019.1.3/dft_v4_0_16 +dft_v4_1_1 = C:/Mentor/CompLib/2019.1.3/dft_v4_1_1 +displayport_v7_0_11 = C:/Mentor/CompLib/2019.1.3/displayport_v7_0_11 +displayport_v8_1_1 = C:/Mentor/CompLib/2019.1.3/displayport_v8_1_1 +displayport_v9_0_1 = C:/Mentor/CompLib/2019.1.3/displayport_v9_0_1 +xbip_dsp48_mult_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_mult_v3_0_6 +floating_point_v7_0_16 = C:/Mentor/CompLib/2019.1.3/floating_point_v7_0_16 +div_gen_v5_1_15 = C:/Mentor/CompLib/2019.1.3/div_gen_v5_1_15 +dp_videoaxi4s_bridge_v1_0_0 = C:/Mentor/CompLib/2019.1.3/dp_videoaxi4s_bridge_v1_0_0 +dsp_macro_v1_0_0 = C:/Mentor/CompLib/2019.1.3/dsp_macro_v1_0_0 +fir_compiler_v5_2_6 = C:/Mentor/CompLib/2019.1.3/fir_compiler_v5_2_6 +duc_ddc_compiler_v3_0_15 = C:/Mentor/CompLib/2019.1.3/duc_ddc_compiler_v3_0_15 +ernic_v1_0_1 = C:/Mentor/CompLib/2019.1.3/ernic_v1_0_1 +etrnic_v1_0_3 = C:/Mentor/CompLib/2019.1.3/etrnic_v1_0_3 +etrnic_v1_1_2 = C:/Mentor/CompLib/2019.1.3/etrnic_v1_1_2 +fc32_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/fc32_rs_fec_v1_0_11 +fec_5g_common_v1_0_1 = C:/Mentor/CompLib/2019.1.3/fec_5g_common_v1_0_1 +fec_5g_common_v1_1_1 = C:/Mentor/CompLib/2019.1.3/fec_5g_common_v1_1_1 +fir_compiler_v7_2_12 = C:/Mentor/CompLib/2019.1.3/fir_compiler_v7_2_12 +flexo_100g_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/flexo_100g_rs_fec_v1_0_11 +floating_point_v7_1_8 = C:/Mentor/CompLib/2019.1.3/floating_point_v7_1_8 +g709_rs_encoder_v2_2_6 = C:/Mentor/CompLib/2019.1.3/g709_rs_encoder_v2_2_6 +rs_toolbox_v9_0_7 = C:/Mentor/CompLib/2019.1.3/rs_toolbox_v9_0_7 +g709_rs_decoder_v2_2_8 = C:/Mentor/CompLib/2019.1.3/g709_rs_decoder_v2_2_8 +g709_fec_v2_3_5 = C:/Mentor/CompLib/2019.1.3/g709_fec_v2_3_5 +g709_fec_v2_4_1 = C:/Mentor/CompLib/2019.1.3/g709_fec_v2_4_1 +g975_efec_i4_v1_0_17 = C:/Mentor/CompLib/2019.1.3/g975_efec_i4_v1_0_17 +g975_efec_i7_v2_0_18 = C:/Mentor/CompLib/2019.1.3/g975_efec_i7_v2_0_18 +ieee802d3_200g_rs_fec_v1_0_7 = C:/Mentor/CompLib/2019.1.3/ieee802d3_200g_rs_fec_v1_0_7 +ieee802d3_25g_rs_fec_v1_0_13 = C:/Mentor/CompLib/2019.1.3/ieee802d3_25g_rs_fec_v1_0_13 +ieee802d3_400g_rs_fec_v1_0_7 = C:/Mentor/CompLib/2019.1.3/ieee802d3_400g_rs_fec_v1_0_7 +ieee802d3_50g_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/ieee802d3_50g_rs_fec_v1_0_11 +ieee802d3_50g_rs_fec_v2_0_1 = C:/Mentor/CompLib/2019.1.3/ieee802d3_50g_rs_fec_v2_0_1 +ieee802d3_rs_fec_v1_0_15 = C:/Mentor/CompLib/2019.1.3/ieee802d3_rs_fec_v1_0_15 +ieee802d3_rs_fec_v2_0_5 = C:/Mentor/CompLib/2019.1.3/ieee802d3_rs_fec_v2_0_5 +ldpc_v2_0_3 = C:/Mentor/CompLib/2019.1.3/ldpc_v2_0_3 +lte_3gpp_channel_estimator_v2_0_16 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_channel_estimator_v2_0_16 +lte_3gpp_mimo_decoder_v3_0_15 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_mimo_decoder_v3_0_15 +lte_3gpp_mimo_encoder_v4_0_14 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_mimo_encoder_v4_0_14 +tcc_encoder_3gpplte_v4_0_15 = C:/Mentor/CompLib/2019.1.3/tcc_encoder_3gpplte_v4_0_15 +lte_dl_channel_encoder_v3_0_15 = C:/Mentor/CompLib/2019.1.3/lte_dl_channel_encoder_v3_0_15 +lte_dl_channel_encoder_v4_0_0 = C:/Mentor/CompLib/2019.1.3/lte_dl_channel_encoder_v4_0_0 +xfft_v7_2_9 = C:/Mentor/CompLib/2019.1.3/xfft_v7_2_9 +lte_fft_v2_0_18 = C:/Mentor/CompLib/2019.1.3/lte_fft_v2_0_18 +xfft_v9_1_2 = C:/Mentor/CompLib/2019.1.3/xfft_v9_1_2 +lte_fft_v2_1_0 = C:/Mentor/CompLib/2019.1.3/lte_fft_v2_1_0 +xbip_dsp48_multacc_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_multacc_v3_0_6 +lte_pucch_receiver_v2_0_16 = C:/Mentor/CompLib/2019.1.3/lte_pucch_receiver_v2_0_16 +xbip_multadd_v3_0_14 = C:/Mentor/CompLib/2019.1.3/xbip_multadd_v3_0_14 +lte_rach_detector_v3_1_5 = C:/Mentor/CompLib/2019.1.3/lte_rach_detector_v3_1_5 +lte_ul_channel_decoder_v4_0_16 = C:/Mentor/CompLib/2019.1.3/lte_ul_channel_decoder_v4_0_16 +mailbox_v2_1_11 = C:/Mentor/CompLib/2019.1.3/mailbox_v2_1_11 +mdm_v3_2_16 = C:/Mentor/CompLib/2019.1.3/mdm_v3_2_16 +iomodule_v3_0 = C:/Mentor/CompLib/2019.1.3/iomodule_v3_0 +lmb_bram_if_cntlr_v4_0 = C:/Mentor/CompLib/2019.1.3/lmb_bram_if_cntlr_v4_0 +lmb_v10_v3_0 = C:/Mentor/CompLib/2019.1.3/lmb_v10_v3_0 +axi_lite_ipif_v3_0 = C:/Mentor/CompLib/2019.1.3/axi_lite_ipif_v3_0 +mdm_v3_2 = C:/Mentor/CompLib/2019.1.3/mdm_v3_2 +microblaze_mcs_v2_3_6 = C:/Mentor/CompLib/2019.1.3/microblaze_mcs_v2_3_6 +noc_mc_ddr4_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_mc_ddr4_phy_v1_0_0 +perf_axi_tg_v1_0_8 = C:/Mentor/CompLib/2019.1.3/perf_axi_tg_v1_0_8 +polar_v1_0_3 = C:/Mentor/CompLib/2019.1.3/polar_v1_0_3 +prc_v1_3_2 = C:/Mentor/CompLib/2019.1.3/prc_v1_3_2 +processing_system7_vip_v1_0_7 = C:/Mentor/CompLib/2019.1.3/processing_system7_vip_v1_0_7 +proc_sys_reset_v5_0_13 = C:/Mentor/CompLib/2019.1.3/proc_sys_reset_v5_0_13 +pr_axi_shutdown_manager_v1_0_1 = C:/Mentor/CompLib/2019.1.3/pr_axi_shutdown_manager_v1_0_1 +pr_bitstream_monitor_v1_0_1 = C:/Mentor/CompLib/2019.1.3/pr_bitstream_monitor_v1_0_1 +pr_decoupler_v1_0_7 = C:/Mentor/CompLib/2019.1.3/pr_decoupler_v1_0_7 +quadsgmii_v3_4_6 = C:/Mentor/CompLib/2019.1.3/quadsgmii_v3_4_6 +rs_decoder_v9_0_16 = C:/Mentor/CompLib/2019.1.3/rs_decoder_v9_0_16 +rs_encoder_v9_0_15 = C:/Mentor/CompLib/2019.1.3/rs_encoder_v9_0_15 +rxaui_v4_4_6 = C:/Mentor/CompLib/2019.1.3/rxaui_v4_4_6 +sd_fec_v1_1_3 = C:/Mentor/CompLib/2019.1.3/sd_fec_v1_1_3 +sid_v8_0_14 = C:/Mentor/CompLib/2019.1.3/sid_v8_0_14 +soft_ecc_proxy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/soft_ecc_proxy_v1_0_0 +spdif_v2_0_21 = C:/Mentor/CompLib/2019.1.3/spdif_v2_0_21 +srio_gen2_v4_1_6 = C:/Mentor/CompLib/2019.1.3/srio_gen2_v4_1_6 +switch_core_top_v1_0_7 = C:/Mentor/CompLib/2019.1.3/switch_core_top_v1_0_7 +sync_ip = C:/Mentor/CompLib/2019.1.3/sync_ip +tcc_decoder_3gppmm_v2_0_18 = C:/Mentor/CompLib/2019.1.3/tcc_decoder_3gppmm_v2_0_18 +tcc_encoder_3gpp_v5_0_15 = C:/Mentor/CompLib/2019.1.3/tcc_encoder_3gpp_v5_0_15 +tmr_comparator_v1_0_2 = C:/Mentor/CompLib/2019.1.3/tmr_comparator_v1_0_2 +tmr_sem_v1_0_9 = C:/Mentor/CompLib/2019.1.3/tmr_sem_v1_0_9 +tri_mode_ethernet_mac_v9_0_14 = C:/Mentor/CompLib/2019.1.3/tri_mode_ethernet_mac_v9_0_14 +tsn_temac_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tsn_temac_v1_0_4 +videoaxi4s_bridge_v1_0_5 = C:/Mentor/CompLib/2019.1.3/videoaxi4s_bridge_v1_0_5 +viterbi_v9_1_11 = C:/Mentor/CompLib/2019.1.3/viterbi_v9_1_11 +v_ccm_v6_0_15 = C:/Mentor/CompLib/2019.1.3/v_ccm_v6_0_15 +v_cfa_v7_0_14 = C:/Mentor/CompLib/2019.1.3/v_cfa_v7_0_14 +v_cresample_v4_0_14 = C:/Mentor/CompLib/2019.1.3/v_cresample_v4_0_14 +v_dual_splitter_v1_0_9 = C:/Mentor/CompLib/2019.1.3/v_dual_splitter_v1_0_9 +v_enhance_v8_0_15 = C:/Mentor/CompLib/2019.1.3/v_enhance_v8_0_15 +v_gamma_v7_0_15 = C:/Mentor/CompLib/2019.1.3/v_gamma_v7_0_15 +v_osd_v6_0_16 = C:/Mentor/CompLib/2019.1.3/v_osd_v6_0_16 +v_rgb2ycrcb_v7_1_13 = C:/Mentor/CompLib/2019.1.3/v_rgb2ycrcb_v7_1_13 +v_vid_sdi_tx_bridge_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_vid_sdi_tx_bridge_v2_0_0 +v_ycrcb2rgb_v7_1_13 = C:/Mentor/CompLib/2019.1.3/v_ycrcb2rgb_v7_1_13 +xbip_dsp48_macro_v3_0_17 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_macro_v3_0_17 +xfft_v9_0_17 = C:/Mentor/CompLib/2019.1.3/xfft_v9_0_17 +xsdbs_v1_0_2 = C:/Mentor/CompLib/2019.1.3/xsdbs_v1_0_2 +zynq_ultra_ps_e_vip_v1_0_5 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_vip_v1_0_5 +[DefineOptionset] +; Define optionset entries for the various compilers, vmake, and vsim. +; These option sets can be used with the "-optionset " syntax. +; i.e. +; vlog -optionset COMPILEDEBUG top.sv +; vsim -optionset UVMDEBUG my_top +; +; Following are some useful examples. + +; define a vsim optionset for uvm debugging +UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop + +; define a vopt optionset for debugging +VOPTDEBUG = +acc -debugdb + +[encryption] +; For vencrypt and vhencrypt. + +; Controls whether to encrypt whole files by ignoring all protect directives +; (except "viewport" and "interface_viewport") that are present in the input. +; The default is 0, use embedded protect directives to control the encryption. +; Set this to 1 to encrypt whole files by ignoring embedded protect directives. +; wholefile = 0 + +; Sets the data_method to use for the symmetric session key. +; The session key is a symmetric key that is randomly generated for each +; protected region (envelope) and is the heart of all encryption. This is used +; to set the length of the session key to generate and use when encrypting the +; HDL text. Supported values are aes128, aes192, and aes256. +; data_method = aes128 + +; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption +; "recipe" comprising an optional common block, at least one tool block (which +; contains the key public key), and the text to be encrypted. The common block +; and any of the tool blocks may contain rights in the form of the "control" +; directive. The text to be encrypted is specified either by setting +; "wholefile" to 1 or by embedding protect "begin" and "end" directives in +; the input HDL files. + +; Common recipe specification file. This file is optional. Its presence will +; require at least one "toolblock" to be specified. +; Directives such as "author" "author_info" and "data_method", +; as well as the common block license specification, go in this file. +; common = + +; Tool block specification recipe(s). Public key file with optional tool block +; file name. May be multiply-defined; at least one tool block is required if +; a recipe is being specified. +; Key file is a file name with no extension (.deprecated or .active will be +; supplied by the encryption tool). +; Rights file name is optional. +; toolblock = [,]{:[,]} + +; Location of directory containing recipe files. +; The default location is in the product installation directory. +; keyring = $MODEL_TECH/../keyring + +; Enable encryption statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [cmd,msg]. +Stats = cmd,msg + +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +; Value of 4 or ams99 for VHDL-AMS-1999 +; Value of 5 or ams07 for VHDL-AMS-2007 +VHDL93 = 2002 + +; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. +; ignoreStandardRealVector = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Set the prefix to be honored for synthesis/coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverSub = 0 + +; Automatically exclude VHDL case statement OTHERS choice branches. +; This includes OTHERS choices in selected signal assigment statements. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Turn on or off clkOpt optimization for code coverage. Default is on. +; CoverClkOpt = 1 + +; Turn on or off clkOpt optimization builtins for code coverage. Default is on. +; CoverClkOptBuiltins = 0 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Set this to cause the compilers to force data to be committed to disk +; when the files are closed. +; SyncCompilerFiles = 1 + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; Controls whether or not to show immediate assertions with constant expressions +; in GUI/report/UCDB etc. By default, immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls how VHDL basic identifiers are stored with the design unit. +; Does not make the language case-sensitive, affects only how declarations +; declared with basic identifiers have their names stored and printed +; (in the GUI, examine, etc.). +; Default is to preserve the case as originally depicted in the VHDL source. +; Value of 0 indicates to change all basic identifiers to lower case. +; PreserveCase = 0 + +; For Configuration Declarations, controls the effect that USE clauses have +; on visibility inside the configuration items being configured. If 1 +; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, +; extend the visibility of objects made visible through USE clauses into nested +; component configurations. +; OldVHDLConfigurationVisibility = 0 + +; Allows VHDL configuration declarations to be in a different library from +; the corresponding configured entity. Default is to not allow this for +; stricter LRM-compliance. +; SeparateConfigLibrary = 1; + +; Determine how mode OUT subprogram parameters of type array and record are treated. +; If 0 (the default), then only VHDL 2008 will do this initialization. +; If 1, always initialize the mode OUT parameter to its default value. +; If 2, do not initialize the mode OUT out parameter. +; Note that prior to release 10.1, all language versions did not initialize mode +; OUT array and record type parameters, unless overridden here via this mechanism. +; In release 10.1 and later, only files compiled with VHDL 2008 will cause this +; initialization, unless overridden here. +; InitOutCompositeParam = 0 + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Describe compilation options according to matching file patterns. +; File pattern * matches all printing characters other than '/'. +; File pattern **/x matches all paths containing file/directory x. +; File pattern x/** matches all paths beginning at directory x. +; FileOptMap = (**/*.vhd => -2008); + +; Describe library targets of compilation according to matching file patterns. +; LibMap = (**/*.vhd => work); + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with total size in bytes equal to or more than the sparse memory +; threshold gets marked as sparse automatically, unless specified otherwise +; in source code or by the +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with total size equal +; to or greater than 1Mb are marked as sparse) +; SparseMemThreshold = 1048576 + +; Set the prefix to be honored for synthesis and coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Turn on code coverage in VLOG `celldefine modules, modules containing +; specify blocks, and modules included using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 0 to 5, with the following +; meanings (the default is 3): +; 5 -- All allowable optimizations are on. +; 4 -- Turn off removing unreferenced code. +; 3 -- Turn off process, always block and if statement merging. +; 2 -- Turn off expression optimization, converting primitives +; to continuous assignments, VHDL subprogram inlining. +; and VHDL clkOpt (converting FF's to builtins). +; 1 -- Turn off continuous assignment optimizations and clock suppression. +; 0 -- Turn off Verilog module inlining and VHDL arch inlining. +; HOWEVER, if fsm coverage is turned on, optimizations will be forced to +; level 3, with also turning off converting primitives to continuous assigns. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => _ +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = [ ...] +LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SvFileSuffixes = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2005 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "mti_design_element_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls if untyped parameters that are initialized with values greater +; than 2147483647 are mapped to generics of type INTEGER or ignored. +; If mapped to VHDL Integers, values greater than 2147483647 +; are mapped to negative values. +; Default is to map these parameter to generic of type INTEGER +; ForceUnsignedToVHDLInteger = 1 + +; Enable AMS wreal (wired real) extensions. Default is 0. +; WrealType = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-][,[+|-]*] + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Controls how $unit library entries are named. Valid options are: +; "file" (generate name based on the first file on the command line) +; "du" (generate name based on first design unit following an item +; found in $unit scope) +; CUAutoName = file + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; CppInstall = 7.4.0 + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. +; Sc22Mode = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Enable use of UVMC library. Default is off. +; UseUvmc = 1 + +[vopt] +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; enable or disable param saving in UCDB. +; CoverageSaveParam = 0 + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Controls set of CoverConstructs that are being considered for Coverage +; Collection. +; Some of Valid options are: default,set1,set2 +; Covermode = default + +; Controls set of HDL cover constructs that would be considered(or not considered) +; for Coverage Collection. (Default corresponds to covermode default). +; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". +; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Set the number of processes created during the code generation phase. +; By default a heuristic is used to set this value. This may be set to 0 +; to disable this feature completely. +; ParallelJobs = 0 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-][,[+|-]*] + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Disable SystemVerilog elaboration system task messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = fs + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 10000000 + +; Specify libraries to be searched for precompiled modules +; LibrarySearchPath = [ ...] + +; Set XPROP assertion fail limit. Default is 5. +; Any positive integer, -1 for infinity. +; XpropAssertionLimit = 5 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Control SVA and VHDL immediate assertion directives during simulation +; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts +; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts +; SimulateImmedAsserts = 1 + +; License feature mappings for Verilog and VHDL +; qhsimvh Single language VHDL license +; qhsimvl Single language Verilog license +; msimhdlsim Language neutral license for either Verilog or VHDL +; msimhdlmix Second language only, language neutral license for either +; Verilog or VHDL +; +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately checkout and hold a VHDL license (i.e., one of +; qhsimvh, msimhdlsim, or msimhdlmix) +; vlog Immediately checkout and hold a Verilog license (i.e., one of +; qhsimvl, msimhdlsim, or msimhdlmix) +; plus Immediately checkout and hold a VHDL license and a Verilog license +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer license feature (PE ONLY) +; noslvhdl Disable checkout of qhsimvh license feature +; noslvlog Disable checkout of qhsimvl license feature +; nomix Disable checkout of msimhdlmix license feature +; nolnl Disable checkout of msimhdlsim license feature +; mixedonly Disable checkout of qhsimvh and qhsimvl license features +; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features +; +; Examples (remove ";" comment character to activate licensing directives): +; Single directive: +; License = plus +; Multi-directive (Note: space delimited directives): +; License = noqueue plus + +; Severity level of a VHDL assertion message or of a SystemVerilog severity system task +; which will cause a running simulation to stop. +; VHDL assertions and SystemVerilog severity system task that occur with the +; given severity or higher will cause a running simulation to stop. +; This value is ignored during elaboration. +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Severity level of a tool message which will cause a running simulation to +; stop. This value is ignored during elaboration. Default is to not break. +; 0 = Note 1 = Warning 2 = Error 3 = Fatal +;BreakOnMessage = 2 + +; The class debug feature enables more visibility and tracking of class instances +; during simulation. By default this feature is disabled (0). To enable this +; feature set ClassDebug to 1. +; ClassDebug = 1 + +; Message Format conversion specifications: +; %S - Severity Level of message/assertion +; %R - Text of message +; %T - Time of message +; %D - Delta value (iteration number) of Time +; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected +; %i - Instance/Region/Signal pathname with Process name (if available) +; %I - shorthand for one of these: +; " %K: %i" +; " %K: %i File: %F" (when path is not Process or Signal) +; except that the %i in this case does not report the Process name +; %O - Process name +; %P - Instance/Region path without leaf process +; %F - File name +; %L - Line number; if assertion message, then line number of assertion or, if +; assertion is in a subprogram, line from which the call is made +; %u - Design unit name in form library.primary +; %U - Design unit name in form library.primary(secondary) +; %% - The '%' character itself +; +; If specific format for Severity Level is defined, use that format. +; Else, for a message that occurs during elaboration: +; -- Failure/Fatal message in VHDL region that is not a Process, and in +; certain non-VHDL regions, uses MessageFormatBreakLine; +; -- Failure/Fatal message otherwise uses MessageFormatBreak; +; -- Note/Warning/Error message uses MessageFormat. +; Else, for a message that occurs during runtime and triggers a breakpoint because +; of the BreakOnAssertion setting: +; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; +; -- otherwise uses MessageFormatBreak. +; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. +; +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops because of a breakpoint or fatal error. +; Example with function name: # Break in Process ctr at counter.vhd line 44 +; Example without function name: # Break at counter.vhd line 44 +; Default value is 1. +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned +; Flags may be one of: enumnumeric, showbase, wreal +DefaultRadix = hexadecimal +DefaultRadixFlags = showbase +; Set to 1 for make the signal_force VHDL and Verilog functions use the +; default radix when processing the force value. Prior to 10.2 signal_force +; used the default radix, now it always uses symbolic unless value explicitly indicates base +;SignalForceFunctionUseDefaultRadix = 0 + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. +; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. +; BatchMode = 1 + +; File for saving command transcript when -batch option used +; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero +; default is unset so command transcript only goes to stdout for better performance +; BatchTranscriptFile = transcript + +; File for saving command transcript, this option is ignored when -batch option is used +TranscriptFile = transcript + +; Transcript file long line wrapping mode(s) +; mode == 0 :: no wrapping, line recorded as is +; mode == 1 :: wrap at first whitespace after WSColumn +; or at Column. +; mode == 2 :: wrap as above, but add continuation +; character ('\') at end of each wrapped line +; +; WrapMode = 0 +; WrapColumn = 30000 +; WrapWSColumn = 27000 + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable SystemVerilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; Control the iteration of events when a VHDL signal is forced to a value +; This flag can be set to honour the signal update event in next iteration, +; the default is to update and propagate in the same iteration. +; ForceSigNextIter = 1 + +; Enable simulation statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; If nonzero, close files as soon as there is either an explicit call to +; file_close, or when the file variable's scope is closed. When zero, a +; file opened in append mode is not closed in case it is immediately +; reopened in append mode; otherwise, the file will be closed at the +; point it is reopened. +; AppendClose = 1 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from accelerated versions of the std_logic_arith, +; std_logic_unsigned, and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from accelerated versions of the IEEE numeric_std +; and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names +; in the design hierarchy. +; This style is controlled by the value of the GenerateFormat +; value described next. Default is to use new-style names, which +; comprise the generate statement label, '(', the value of the generate +; parameter, and a closing ')'. +; Set this to 1 to use old-style names. +; OldVhdlForGenNames = 1 + +; Control the format of the old-style VHDL FOR generate statement region +; name for each iteration. Do not quote the value. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate statement label; the %d represents the generate parameter value +; at a particular iteration (this is the position number if the generate parameter +; is of an enumeration type). Embedded whitespace is allowed (but discouraged); +; leading and trailing whitespace is ignored. +; Application of the format must result in a unique region name over all +; loop iterations for a particular immediately enclosing scope so that name +; lookup can function properly. The default is %s__%d. +; GenerateFormat = %s__%d + +; Enable more efficient logging of VHDL Variables. +; Logging VHDL variables without this enabled, while possible, is very +; inefficient. Enabling this will provide a more efficient logging methodology +; at the expense of more memory usage. By default this feature is disabled (0). +; To enabled this feature, set this variable to 1. +; VhdlVariableLogging = 1 + +; Enable logging of VHDL access type variables and their designated objects. +; This setting will allow both variables of an access type ("access variables") +; and their designated objects ("access objects") to be logged. Logging a +; variable of an access type will automatically also cause the designated +; object(s) of that variable to be logged as the simulation progresses. +; Further, enabling this allows access objects to be logged by name. By default +; this feature is disabled (0). To enable this feature, set this variable to 1. +; Enabling this will automatically enable the VhdlVariableLogging feature also. +; AccessObjDebug = 1 + +; Make each VHDL package in a PDU has its own separate copy of the package instead +; of sharing the package between PDUs. The default is to share packages. +; To ensure that each PDU has its own set of packages, set this variable to 1. +; VhdlSeparatePduPackage = 1 + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. +; Use custom gcc compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; DpiCppPath = /bin/gcc +; +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; DpiCppInstall = 7.4.0 + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify whether the Verilog system task $fopen or vpi_mcd_open() +; will create directories that do not exist when opening the file +; in "a" or "w" mode. +; The default is 0 (do not create non-existent directories) +; CreateDirForFileAccess = 1 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + + +; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. +; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. +; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". +; The list of options must be delimited by commas, without spaces or tabs. +; +; Some examples +; To turn on all available UVM-aware debug features: +; UVMControl = all +; To turn on the struct window, mesage logging, and transaction logging: +; UVMControl = struct,msglog,trlog +; To turn on all options except certe: +; UVMControl = all,-certe +; To completely disable all UVM-aware debug functionality: +; UVMControl = disable + +; Specify the WildcardFilter setting. +; A space separated list of object types to be excluded when performing +; wildcard matches with log, wave, etc commands. The default value for this variable is: +; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" +; See "Using the WildcardFilter Preference Variable" in the documentation for +; details on how to use this variable and for descriptions of the filter types. +WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile + +; Specify the WildcardSizeThreshold setting. +; This integer setting specifies the size at which objects will be excluded when +; performing wildcard matches with log, wave, etc commands. Objects of size equal +; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard +; matches. The size is a simple calculation of number of bits or items in the object. +; The default value is 8k (8192). Setting this value to 0 will disable the checking +; of object size against this threshold and allow all objects of any size to be logged. +WildcardSizeThreshold = 8192 + +; Specify whether warning messages are output when objects are filtered out due to the +; WildcardSizeThreshold. The default is 0 (no messages generated). +WildcardSizeThresholdVerbose = 0 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify whether to lock the WLF file. +; Locking the file prevents other invocations of ModelSim/Questa tools from +; inadvertently overwriting the WLF file. +; The default is 1, lock the WLF file. +; WLFFileLock = 0 + +; Specify the update interval for the WLF file in live simulation. +; The interval is given in seconds. +; The value is the smallest interval between WLF file updates. The WLF file +; will be flushed (updated) after (at least) the interval has elapsed, ensuring +; that the data is correct when viewed from a separate viewer. +; A value of 0 means that no updating will occur. +; The default value is 10 seconds. +; WLFUpdateInterval = 10 + +; Specify the WLF cache size limit for WLF files. +; The value is given in megabytes. A value of 0 turns off the cache. +; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). +; On Windows, the default value is 1000 (megabytes) to help to avoid filling +; process memory. +; WLFSimCacheSize allows a different cache size to be set for a live simulation +; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize +; is not set, it defaults to the WLFCacheSize value. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines. +; If 0, no threads will be used; if 1, threads will be used if the system has +; more than one processor. +; WLFUseThreads = 1 + +; Specify the size of objects that will trigger "large object" messages +; at log/wave/list time. The size calculation of the object is the same as that +; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. +; Setting LargeObjectSize to 0 will disable these messages. +; LargeObjectSize = 500000 + +; Specify the depth of stack frames returned by $stacktrace([level]). +; This depth will be picked up when the optional 'level' argument +; is not specified or its value is not a positive integer. +; StackTraceDepth = 100 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; For SystemC-2.3.2 the valid values are 0,1 and 2 +; 0 = SC_SIGNAL_WRITE_CHECK_DISABLE_ +; 1 = SC_SIGNAL_WRITE_CHECK_DEFAULT_ +; 2 = SC_SIGNAL_WRITE_CHECK_CONFLICT_ +; For SystemC-2.2 the valid values are 0 and 1 +; 0 = DISABLE +; 1 = ENABLE +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Set SystemC thread stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). The stack size for sc_thread depends +; on the amount of data on the sc_thread stack and the memory required +; to succesfully execute the thread. +; ScStackSize = 1 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Enable calling of the DPI export taks/functions from the +; SystemC start_of_simulation() callback. +; The default is off. +; EnableDpiSosCb = 1 + + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: This variable can be overridden with the vsim "-onfinish" command line switch. +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result. Default is 0. +; 0 == do not print simstats +; 1 == print at end of simulation +; 2 == print at end of each run command and end of simulation +; PrintSimStats = 1 + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Enable assertion counts. Default is off. +; AssertionCounts = 1 + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. +; AssertionEnable = 0 + +; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionLimit = 1 + +; Turn on/off concurrent assertion pass log. Default is off. +; Assertion pass logging is only enabled when assertion is browseable +; and assertion debug is enabled. +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + +; Assertion thread limit after which assertion would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for an assertion go +; beyond this limit, the assertion would be either switched off or killed. This +; limit applies to only assert directives. +;AssertionThreadLimit = -1 + +; Action to be taken once the assertion thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only assert directives. +;AssertionThreadLimitAction = kill + +; Cover thread limit after which cover would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for a cover go +; beyond this limit, the cover would be either switched off or killed. This +; limit applies to only cover directives. +;CoverThreadLimit = -1 + +; Action to be taken once the cover thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only cover directives. +;CoverThreadLimitAction = kill + + +; By default immediate assertions do not participate in Assertion Coverage calculations +; unless they are executed. This switch causes all immediate assertions in the design +; to participate in Assertion Coverage calculations, whether attempted or not. +; UnattemptedImmediateAssertions = 0 + +; By default immediate covers participate in Coverage calculations +; whether they are attempted or not. This switch causes all unattempted +; immediate covers in the design to stop participating in Coverage +; calculations. +; UnattemptedImmediateCovers = 0 + +; By default pass action block is not executed for assertions on vacuous +; success. The following variable is provided to enable execution of +; pass action block on vacuous success. The following variable is only effective +; if the user does not disable pass action block execution by using either +; system tasks or CLI. Also there is a performance penalty for enabling +; the following variable. +;AssertionEnableVacuousPassActionBlock = 1 + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; This option applies to condition and expression coverage UDP tables. It +; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. +; If this option is used and a match occurs in more than one row in the UDP table, +; none of the counts for all matching rows is incremented. By default, counts are +; incremented for all matching rows. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays +; and VHDL arrays-of-arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, +; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. +; This leads to a longer simulation time with bigger arrays covered with toggle coverage. +; Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized +; one-dimensional packed vectors for toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for +; toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Turn off automatic inclusion of VHDL records in toggle coverage. +; Default is to include them. +; ToggleVHDLRecords = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. +; Following is the toggle coverage calculation criteria based on extended toggle mode: +; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). +; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. +; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. +; ExtendedToggleMode = 3 + +; Enable toggle statistics collection only for ports. Default is 0. +; TogglePortsOnly = 1 + +; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; FecCountLimit = 1 + +; Limit the counts that are tracked for UDP Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; UdpCountLimit = 1 + +; Control toggle coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either +; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; ToggleDeglitchPeriod = 10.0ps + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this +; setting. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the threshold of Coverpoint wildcard bin value range size, above which +; a warning will be triggered. The default is 4K -- 12 wildcard bits. +; SVCoverpointWildCardBinValueSizeWarn = 4096 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SVCovergroup63Compatibility = 0 + +; Enforce the default behavior of covergroup get_coverage() builtin function, GUI +; and report. This variable sets the default value of type_option.merge_instances. +; There are two vsim command line options, -cvgmergeinstances and +; -nocvgmergeinstances to override this setting from vsim command line. +; The default value of this variable, -1 (don't care), allows the tool to determine +; the effective value, based on factors related to capacity and optimization. +; The type_option.merge_instances appears in the GUI and coverage reports as either +; auto(1) or auto(0), depending on whether the effective value was determined to +; be a 1 or a 0. +; SVCovergroupMergeInstancesDefault = -1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins +; MaxSVCoverpointBinsInst = 1048576 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins +; MaxSVCrossBinsInst = 67108864 + +; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. +; By default, this variable is set 0, in which case option.no_collect setting will take effect. +; If this variable is set to 1, all zero-weight coverage items will not be saved. +; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting +; of this variable. +; CvgZWNoCollect = 1 + +; Specify a space delimited list of double quoted TCL style +; regular expressions which will be matched against the text of all messages. +; If any regular expression is found to be contained within any message, the +; status for that message will not be propagated to the UCDB TESTSTATUS. +; If no match is detected, then the status will be propagated to the +; UCDB TESTSTATUS. More than one such regular expression text is allowed, +; and each message text is compared for each regular expression in the list. +; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Generate the stub definitions for the undefined symbols in the shared libraries being +; loaded in the simulation. When this flow is turned on, the undefined symbols will not +; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. +; The valid arguments are: on, off, verbose. +; on : turn on the automatic generation of stub definitions. +; off: turn off the flow. The undefined symbols will trigger an immediate load failure. +; verbose: Turn on the flow and report the undefined symbols for each shared library. +; NOTE: This variable can be overriden with vsim switch "-undefsyms". +; The default is on. +; +; UndefSyms = off + +; Enable the support for checkpointing foreign C/C++ libraries. +; The valid arguments are: 0, 1, 2 +; 0: off (default) +; 1: on (manually save/restore user shared library data) +; 2: auto (automatically save/restore user shared library data) +; This option is not supported on the Windows platforms. +; +; AllowCheckpointCpp = 2 + +; Initial seed for the random number generator of the root thread (SystemVerilog). +; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. +; The default value is 0. +; Sv_Seed = 0 + +; Specify the solver "engine" that vsim will select for constrained random +; generation. +; Valid values are: +; "auto" - automatically select the best engine for the current +; constraint scenario +; "bdd" - evaluate all constraint scenarios using the BDD solver engine +; "act" - evaluate all constraint scenarios using the ACT solver engine +; While the BDD solver engine is generally efficient with constraint scenarios +; involving bitwise logical relationships, the ACT solver engine can exhibit +; superior performance with constraint scenarios involving large numbers of +; random variables related via arithmetic operators (+, *, etc). +; NOTE: This variable can be overridden with the vsim "-solveengine" command +; line switch. +; The default value is "auto". +; SolveEngine = auto + +; Specifies the maximum size that a dynamic array may be resized to by the +; solver. If the solver attempts to resize a dynamic array to a size greater +; than the specified limit, the solver will abort with an error. +; The default value is 10000. A value of 0 indicates no limit. +; SolveArrayResizeMax = 10000 + +; Specify error message severity when randomize() and randomize(null) failures +; are detected. +; +; Integer value up to two digits are allowed with each digit having the following legal values: +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; +; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents +; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit) +; represents the setting for randomize(null) calls. +; +; 2) When a single digit value is used, the setting is applied to both normal randomize() call +; and randomize(null) call. +; +; Example: Fatal error for randomize() failures and NO error for randomize(null) failures +; -solvefailseverity=40 +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefailseverity" command +; line switch. +; +; The default is 1 (warning). +; SolveFailSeverity = 1 + +; Error message severity for suppressible errors that are detected in a +; solve/before constraint. +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" +; command line switch. +; The default is 3 (failure). +; SolveBeforeErrorSeverity = 3 + +; Error message severity for suppressible errors that are related to +; solve engine capacity limits +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" +; command line switch. +; The default is 3 (failure). +; SolveEngineErrorSeverity = 3 + +; Enable/disable constraint conflicts on randomize() failure +; Valid values: +; 0 - disable solvefaildebug +; 1 - basic debug (no performance penalty) +; 2 - enhanced debug (runtime performance penalty) +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command +; line switch. +; +; The default is 1 (basic debug). +; SolveFailDebug = 1 + +; Upon encountering a randomize() failure, generate a simplified testcase that +; will reproduce the failure. Optionally output the testcase to a file. +; Testcases for 'no-solution' failures will only be produced if SolveFailDebug +; is enabled (see above). +; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" +; command line switch. +; The default is OFF (do not generate a testcase). To enable testcase +; generation, uncomment this variable. To redirect testcase generation to a +; file, specify the name of the output file. +; SolveFailTestcase = + +; Specify solver timeout threshold (in seconds). randomize() will fail if the +; CPU time required to evaluate any randset exceeds the specified timeout. +; The default value is 500. A value of 0 will disable timeout failures. +; SolveTimeout = 500 + +; Specify the alternative behavior during solver replay. Must be used when combined with -solvereplay switch. +; SolveReplayOpt=[+|-][,[+|-]]*" +' Valid settings: +; validate : toggle the checking of value changes of non-random variables involved in randomize(). (default is off)" +; SolveReplayOpt=validate + +; Specify the maximum size of the solution graph generated by the BDD solver. +; This value can be used to force the BDD solver to abort the evaluation of a +; complex constraint scenario that cannot be evaluated with finite memory. +; This value is specified in 1000s of nodes. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Specify the maximum number of evaluations that may be performed on the +; solution graph by the BDD solver. This value can be used to force the BDD +; solver to abort the evaluation of a complex constraint scenario that cannot +; be evaluated in finite time. This value is specified in 10000s of evaluations. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxEval = 10000 + +; Specify random sequence compatiblity with a prior release. This +; option is used to get the same random sequences during simulation as +; as a prior release. Only prior releases with the same major version +; as the current release are allowed. +; NOTE: Only those random sequence changes due to solver optimizations are +; reverted by this variable. Random sequence changes due to solver bugfixes +; cannot be un-done. +; NOTE: This variable can be overridden with the vsim "-solverev" command +; line switch. +; Default value set to "" (no compatibility). +; SolveRev = + +; Environment variable expansion of command line arguments has been depricated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Specify the memory threshold for the System Verilog garbage collector. +; The value is the number of megabytes of class objects that must accumulate +; before the garbage collector is run. +; The GCThreshold setting is used when class debug mode is disabled to allow +; less frequent garbage collection and better simulation performance. +; The GCThresholdClassDebug setting is used when class debug mode is enabled +; to allow for more frequent garbage collection. +; GCThreshold = 100 +; GCThresholdClassDebug = 5 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +; Location of Multi-Level Verification Component (MVC) installation. +; The default location is the product installation directory. +MvcHome = $QUESTA_MVC_HOME + +; Location of InFact installation. The default is $MODEL_TECH/../../infact +; +; InFactHome = $MODEL_TECH/../../infact + +; Initialize SystemVerilog enums using the base type's default value +; instead of the leftmost value. +; EnumBaseInit = 1 + +; Suppress file type registration. +; SuppressFileTypeReg = 1 + +; Enable/disable non-LRM compliant SystemVerilog language extensions. +; Valid extensions are: +; altdpiheader - Alternative style function signature generated in DPI header", +; cfce - generate an error if $cast fails as a function +; cfmt - C like formatting for specifiers with '#' prefix ('%#x', '%#h') +; dfsp - sets default format specifier as %p, if no format specifier is given for unpacked array in $display and related systasks +; expdfmt - enable format string extensions for $display/$sformatf +; extscan - support values greater than 32 bit for string builtin methods (atohex, atobin, atooct, atoi) +; fmtcap - prints capital hex digits with %X/%H in display calls +; iddp - ignore DPI disable protocol check +; lfmt - zero-pad data if '0' prefixes width in format specifier (e.g. "%04h") +; noexptc - ignore DPI export type name overloading check +; realrand - support randomize() with real variables and constraints (Default) +; SvExtensions = [+|-][,[+|-]*] + +; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions. +; Valid extensions are: +; arraymode - consider rand_mode of unpacked array field independently from its elements +; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles (Default) +; funcback - enable function backtracking (ACT only) +; genmodseedfix - enable LRM-compliant seeding of module/interface instances under for-generate blocks (Default) +; nodist - interpret 'dist' constraint as 'inside' (ACT only) +; noorder - ignore solve/before ordering constraints (ACT only) +; pathseed - enable unique seeding of module instances based on hierarchical path name +; prerandfirst - execute all pre_randomize() functions before evaluating any constraints +; promotedist - promote priority of 'dist' constraint if LHS has no solve/before +; purecheck - suppress pre_randomize() and post_randomize() calls for randomize(null) +; randindex - allow random index in constraint (Default) +; randstruct - consider all fields of unpacked structs as 'rand' +; skew - skew randomize results (ACT only) +; strictstab - strict random stability +; SvRandExtensions = [+|-][,[+|-]*] + +; Controls the formatting of '%p' and '%P' conversion specification, used in $display +; and similar system tasks. +; 1. SVPrettyPrintFlags=I use spaces(S) or tabs(T) per indentation level. +; The 'I' flag when present causes relevant data types to be expanded and indented into +; a more readable format. +; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). +; 2. SVPrettyPrintFlags=L limits the output to lines. +; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). +; 3. SVPrettyPrintFlags=C limits the output to characters. +; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). +; 4. SVPrettyPrintFlags=F limits the output to of relevant datatypes +; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). +; 5. SVPrettyPrintFlags=E limits the output to of relevant datatypes +; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). +; 6. SVPrettyPrintFlags=D suppresses the output of sub-elements below . +; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). +; 7. SVPrettyPrintFlags=R shows the output of specifier %p as per the specifed radix. +; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)). +; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format. +; 8. Items 1-7 above can be combined as a comma separated list. +; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb) +; SVPrettyPrintFlags=I4S + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = /lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = /lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = /lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = /lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = /lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; suppress can be used to achieve +nowarn functionality +; The format is: suppress = ,,[,,...] +; Examples: +suppress = 8780 ;an explanation can be had by running: verror 8780 +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3601 +; suppress = 3009,CNNODP,3601,TFMPC +; suppress = 8683,8684 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of Verilog display system task messages and +; PLI/FLI print function call messages. The system tasks include +; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They +; also include the analogous file I/O tasks that write to STDOUT +; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, +; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default +; is to have messages appear only in the transcript. The other +; settings are to send messages to the wlf file only (messages that +; are recorded in the wlf file can be viewed in the MsgViewer) or +; to both the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; displaymsgmode = tran + +; Control transcripting of elaboration/runtime messages not +; addressed by the displaymsgmode setting. The default is to +; have messages appear only in the transcript. The other settings +; are to send messages to the wlf file only (messages that are +; recorded in the wlf file can be viewed in the MsgViewer) or to both +; the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; msgmode = tran + +; Controls number of displays of a particluar message +; default value is 5 +; MsgLimitCount = 5 + +[utils] +; Default Library Type (while creating a library with "vlib") +; 0 - legacy library using subdirectories for design units +; 2 - flat library +; DefaultLibType = 2 + +; Flat Library Page Size (while creating a library with "vlib") +; Set the size in bytes for flat library file pages. Libraries containing +; very large files may benefit from a larger value. +; FlatLibPageSize = 8192 + +; Flat Library Page Cleanup Percentage (while creating a library with "vlib") +; Set the percentage of total pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeleteThreshold. +; FlatLibPageDeletePercentage = 50 + +; Flat Library Page Cleanup Threshold (while creating a library with "vlib") +; Set the number of pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeletePercentage. +; FlatLibPageDeleteThreshold = 1000 + + diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/selectio_lvds_rx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/selectio_lvds_rx.sh new file mode 100644 index 00000000..55348d69 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/selectio_lvds_rx.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : selectio_lvds_rx.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Mar 19 18:25:33 +0800 2023 +# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: selectio_lvds_rx.sh [-help] +# usage: selectio_lvds_rx.sh [-lib_map_path] +# usage: selectio_lvds_rx.sh [-noclean_files] +# usage: selectio_lvds_rx.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'selectio_lvds_rx.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "selectio_lvds_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_rx.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="C:/Mentor/CompLib/2019.1.3" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_rx.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: selectio_lvds_rx.sh [-help]\n\ +Usage: selectio_lvds_rx.sh [-lib_map_path]\n\ +Usage: selectio_lvds_rx.sh [-reset_run]\n\ +Usage: selectio_lvds_rx.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/.vivado.end.rst b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/selectio_lvds_rx.udo similarity index 100% rename from projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/.vivado.end.rst rename to projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/selectio_lvds_rx.udo diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/simulate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/simulate.do new file mode 100644 index 00000000..54b4f399 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.selectio_lvds_rx xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {selectio_lvds_rx.udo} + +run -all + +quit -force diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/wave.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/README.txt new file mode 100644 index 00000000..8965a407 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Mar 19 18:25:33 +0800 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./selectio_lvds_rx.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './selectio_lvds_rx.sh' script. + +./selectio_lvds_rx.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./selectio_lvds_rx.sh -noclean_files + +For more information on the script, please type './selectio_lvds_rx.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/compile.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/compile.do new file mode 100644 index 00000000..13ea6452 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/compile.do @@ -0,0 +1,23 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 \ +"../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v" \ +"../../../ip/selectio_lvds_rx/selectio_lvds_rx.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/elaborate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/elaborate.do new file mode 100644 index 00000000..adb32e30 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.selectio_lvds_rx xil_defaultlib.glbl -o selectio_lvds_rx_opt diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/file_info.txt new file mode 100644 index 00000000..6d7cb2d8 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +selectio_lvds_rx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v, +selectio_lvds_rx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/selectio_lvds_rx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/selectio_lvds_rx.sh new file mode 100644 index 00000000..82f66dff --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/selectio_lvds_rx.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : selectio_lvds_rx.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Mar 19 18:25:33 +0800 2023 +# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: selectio_lvds_rx.sh [-help] +# usage: selectio_lvds_rx.sh [-lib_map_path] +# usage: selectio_lvds_rx.sh [-noclean_files] +# usage: selectio_lvds_rx.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'selectio_lvds_rx.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "selectio_lvds_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_rx.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_rx.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: selectio_lvds_rx.sh [-help]\n\ +Usage: selectio_lvds_rx.sh [-lib_map_path]\n\ +Usage: selectio_lvds_rx.sh [-reset_run]\n\ +Usage: selectio_lvds_rx.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/__synthesis_is_complete__ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/selectio_lvds_rx.udo similarity index 100% rename from projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/__synthesis_is_complete__ rename to projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/selectio_lvds_rx.udo diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/simulate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/simulate.do new file mode 100644 index 00000000..9839c78f --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib selectio_lvds_rx_opt + +do {wave.do} + +view wave +view structure +view signals + +do {selectio_lvds_rx.udo} + +run -all + +quit -force diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/wave.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/README.txt new file mode 100644 index 00000000..8965a407 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Mar 19 18:25:33 +0800 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./selectio_lvds_rx.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './selectio_lvds_rx.sh' script. + +./selectio_lvds_rx.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./selectio_lvds_rx.sh -noclean_files + +For more information on the script, please type './selectio_lvds_rx.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/compile.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/compile.do new file mode 100644 index 00000000..704d2832 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/compile.do @@ -0,0 +1,23 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v" \ +"../../../ip/selectio_lvds_rx/selectio_lvds_rx.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/file_info.txt new file mode 100644 index 00000000..6d7cb2d8 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +selectio_lvds_rx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v, +selectio_lvds_rx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/selectio_lvds_rx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/selectio_lvds_rx.sh new file mode 100644 index 00000000..eb0c64ea --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/selectio_lvds_rx.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : selectio_lvds_rx.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Mar 19 18:25:33 +0800 2023 +# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: selectio_lvds_rx.sh [-help] +# usage: selectio_lvds_rx.sh [-lib_map_path] +# usage: selectio_lvds_rx.sh [-noclean_files] +# usage: selectio_lvds_rx.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'selectio_lvds_rx.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "selectio_lvds_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_rx.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_rx.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: selectio_lvds_rx.sh [-help]\n\ +Usage: selectio_lvds_rx.sh [-lib_map_path]\n\ +Usage: selectio_lvds_rx.sh [-reset_run]\n\ +Usage: selectio_lvds_rx.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/selectio_lvds_rx.udo b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/selectio_lvds_rx.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/simulate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/simulate.do new file mode 100644 index 00000000..1232b429 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+selectio_lvds_rx -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.selectio_lvds_rx xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {selectio_lvds_rx.udo} + +run -all + +endsim + +quit -force diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/wave.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/README.txt new file mode 100644 index 00000000..8965a407 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Mar 19 18:25:33 +0800 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./selectio_lvds_rx.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './selectio_lvds_rx.sh' script. + +./selectio_lvds_rx.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./selectio_lvds_rx.sh -noclean_files + +For more information on the script, please type './selectio_lvds_rx.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/file_info.txt new file mode 100644 index 00000000..6d7cb2d8 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +selectio_lvds_rx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v, +selectio_lvds_rx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/selectio_lvds_rx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/selectio_lvds_rx.sh new file mode 100644 index 00000000..b2505305 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/selectio_lvds_rx.sh @@ -0,0 +1,230 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : selectio_lvds_rx.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Mar 19 18:25:33 +0800 2023 +# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: selectio_lvds_rx.sh [-help] +# usage: selectio_lvds_rx.sh [-lib_map_path] +# usage: selectio_lvds_rx.sh [-noclean_files] +# usage: selectio_lvds_rx.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'selectio_lvds_rx.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "selectio_lvds_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts -sverilog \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + "$ref_dir/../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v" \ + "$ref_dir/../../../ip/selectio_lvds_rx/selectio_lvds_rx.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.selectio_lvds_rx xil_defaultlib.glbl -o selectio_lvds_rx_simv +} + +# RUN_STEP: +simulate() +{ + ./selectio_lvds_rx_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_rx.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key selectio_lvds_rx_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc selectio_lvds_rx_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_rx.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: selectio_lvds_rx.sh [-help]\n\ +Usage: selectio_lvds_rx.sh [-lib_map_path]\n\ +Usage: selectio_lvds_rx.sh [-reset_run]\n\ +Usage: selectio_lvds_rx.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/simulate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/README.txt new file mode 100644 index 00000000..c7a8bbf2 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Mar 19 18:25:33 +0800 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./selectio_lvds_rx.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './selectio_lvds_rx.sh' script. + +./selectio_lvds_rx.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./selectio_lvds_rx.sh -noclean_files + +For more information on the script, please type './selectio_lvds_rx.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/file_info.txt new file mode 100644 index 00000000..6d7cb2d8 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +selectio_lvds_rx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v, +selectio_lvds_rx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/run.f b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/run.f new file mode 100644 index 00000000..274a0d4d --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/run.f @@ -0,0 +1,15 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v" \ + "../../../ip/selectio_lvds_rx/selectio_lvds_rx.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/selectio_lvds_rx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/selectio_lvds_rx.sh new file mode 100644 index 00000000..ab1dfdcd --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xcelium/selectio_lvds_rx.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : selectio_lvds_rx.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Mar 19 18:25:33 +0800 2023 +# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: selectio_lvds_rx.sh [-help] +# usage: selectio_lvds_rx.sh [-lib_map_path] +# usage: selectio_lvds_rx.sh [-noclean_files] +# usage: selectio_lvds_rx.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'selectio_lvds_rx.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "selectio_lvds_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.selectio_lvds_rx \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_rx.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_rx.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: selectio_lvds_rx.sh [-help]\n\ +Usage: selectio_lvds_rx.sh [-lib_map_path]\n\ +Usage: selectio_lvds_rx.sh [-reset_run]\n\ +Usage: selectio_lvds_rx.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/README.txt new file mode 100644 index 00000000..8965a407 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Mar 19 18:25:33 +0800 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./selectio_lvds_rx.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './selectio_lvds_rx.sh' script. + +./selectio_lvds_rx.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./selectio_lvds_rx.sh -noclean_files + +For more information on the script, please type './selectio_lvds_rx.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/cmd.tcl b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/elab.opt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/elab.opt new file mode 100644 index 00000000..cbdf0b26 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/elab.opt @@ -0,0 +1 @@ +--relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot selectio_lvds_rx xil_defaultlib.selectio_lvds_rx xil_defaultlib.glbl -log elaborate.log diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/file_info.txt new file mode 100644 index 00000000..27843160 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/file_info.txt @@ -0,0 +1,3 @@ +selectio_lvds_rx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v, +selectio_lvds_rx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_rx/selectio_lvds_rx.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/selectio_lvds_rx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/selectio_lvds_rx.sh new file mode 100644 index 00000000..0e8c2138 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/selectio_lvds_rx.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : selectio_lvds_rx.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Mar 19 18:25:33 +0800 2023 +# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: selectio_lvds_rx.sh [-help] +# usage: selectio_lvds_rx.sh [-lib_map_path] +# usage: selectio_lvds_rx.sh [-noclean_files] +# usage: selectio_lvds_rx.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=C:/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "selectio_lvds_rx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot selectio_lvds_rx xil_defaultlib.selectio_lvds_rx xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim selectio_lvds_rx -key {Behavioral:sim_1:Functional:selectio_lvds_rx} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_rx.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="C:/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb selectio_lvds_rx.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_rx.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: selectio_lvds_rx.sh [-help]\n\ +Usage: selectio_lvds_rx.sh [-lib_map_path]\n\ +Usage: selectio_lvds_rx.sh [-reset_run]\n\ +Usage: selectio_lvds_rx.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/vlog.prj b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/vlog.prj new file mode 100644 index 00000000..8fd43844 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/vlog.prj @@ -0,0 +1,7 @@ +verilog xil_defaultlib \ +"../../../ip/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v" \ +"../../../ip/selectio_lvds_rx/selectio_lvds_rx.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/xsim.ini b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/xsim.ini new file mode 100644 index 00000000..6cb07f57 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_rx/xsim/xsim.ini @@ -0,0 +1,430 @@ +std=$RDI_DATADIR/xsim/vhdl/std +ieee=$RDI_DATADIR/xsim/vhdl/ieee +ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed +vl=$RDI_DATADIR/xsim/vhdl/vl +synopsys=$RDI_DATADIR/xsim/vhdl/synopsys +secureip=$RDI_DATADIR/xsim/verilog/secureip +unisim=$RDI_DATADIR/xsim/vhdl/unisim +unimacro=$RDI_DATADIR/xsim/vhdl/unimacro +unifast=$RDI_DATADIR/xsim/vhdl/unifast +unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver +unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver +unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver +simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver +system_cache_v4_0_6=$RDI_DATADIR/xsim/ip/system_cache_v4_0_6 +bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0 +g709_rs_decoder_v2_2_8=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_8 +xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0 +mipi_dphy_v4_1_4=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_1_4 +iomodule_v3_1_4=$RDI_DATADIR/xsim/ip/iomodule_v3_1_4 +ieee802d3_50g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_11 +common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0 +lte_fft_v2_1_0=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_0 +ieee802d3_50g_rs_fec_v2_0_1=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_1 +convolution_v9_0_14=$RDI_DATADIR/xsim/ip/convolution_v9_0_14 +gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4 +v_cfa_v7_0_14=$RDI_DATADIR/xsim/ip/v_cfa_v7_0_14 +axi4svideo_bridge_v1_0_10=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_10 +pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11 +v_vscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_13 +xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6 +gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux +ethernet_1_10_25g_v2_2_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_2_3 +zynq_ultra_ps_e_v3_3_0=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_0 +v_cresample_v4_0_14=$RDI_DATADIR/xsim/ip/v_cresample_v4_0_14 +v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9 +v_scenechange_v1_0_1=$RDI_DATADIR/xsim/ip/v_scenechange_v1_0_1 +hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0 +ahblite_axi_bridge_v3_0_14=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_14 +tri_mode_ethernet_mac_v9_0_14=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_14 +blk_mem_gen_v8_4_3=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_3 +noc_mc_ddr4_phy_v1_0_0=$RDI_DATADIR/xsim/ip/noc_mc_ddr4_phy_v1_0_0 +axi_data_fifo_v2_1_18=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_18 +axi_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_5 +ethernet_1_10_25g_v2_0_5=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_0_5 +compact_gt_v1_0_5=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_5 +axi_gpio_v2_0_21=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_21 +qdma_v3_0_2=$RDI_DATADIR/xsim/ip/qdma_v3_0_2 +viterbi_v9_1_11=$RDI_DATADIR/xsim/ip/viterbi_v9_1_11 +sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2 +ba317=$RDI_DATADIR/xsim/ip/ba317 +xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4 +fifo_generator_v13_2_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_4 +axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14 +vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0 +axi_emc_v3_0_19=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_19 +cmac_v2_5_1=$RDI_DATADIR/xsim/ip/cmac_v2_5_1 +floating_point_v7_1_8=$RDI_DATADIR/xsim/ip/floating_point_v7_1_8 +xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6 +vid_phy_controller_v2_2_3=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_3 +common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1 +axi_firewall_v1_0_7=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_7 +util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1 +axis_accelerator_adapter_v2_1_15=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_15 +tmr_comparator_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_2 +sd_fec_v1_0_2=$RDI_DATADIR/xsim/ip/sd_fec_v1_0_2 +tmr_manager_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_4 +tsn_temac_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_4 +usxgmii_v1_0_5=$RDI_DATADIR/xsim/ip/usxgmii_v1_0_5 +lte_dl_channel_encoder_v4_0_0=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v4_0_0 +ai_noc=$RDI_DATADIR/xsim/ip/ai_noc +lte_3gpp_mimo_decoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_15 +v_uhdsdi_audio_v1_0_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_0_0 +axi4stream_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_5 +cmac_usplus_v2_4_5=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_4_5 +etrnic_v1_1_2=$RDI_DATADIR/xsim/ip/etrnic_v1_1_2 +floating_point_v7_0_16=$RDI_DATADIR/xsim/ip/floating_point_v7_0_16 +axi_dma_v7_1_20=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_20 +jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi +axi_traffic_gen_v3_0_5=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_5 +emb_mem_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_1 +axi_amm_bridge_v1_0_9=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_9 +axi_datamover_v5_1_21=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_21 +v_axi4s_vid_out_v4_0_10=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_10 +jesd204_v7_2_6=$RDI_DATADIR/xsim/ip/jesd204_v7_2_6 +v_letterbox_v1_0_13=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_13 +interlaken_v2_4_3=$RDI_DATADIR/xsim/ip/interlaken_v2_4_3 +uhdsdi_gt_v2_0_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_0 +axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7 +rst_vip_v1_0_3=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_3 +audio_formatter_v1_0_1=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_1 +lte_3gpp_channel_estimator_v2_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_16 +v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13 +g709_fec_v2_3_5=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_5 +xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6 +axi_chip2chip_v5_0_6=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_6 +fc32_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_11 +v_mix_v3_0_3=$RDI_DATADIR/xsim/ip/v_mix_v3_0_3 +multi_channel_25g_rs_fec_v1_0_5=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_5 +in_system_ibert_v1_0_9=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_9 +ethernet_1_10_25g_v2_1_4=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_1_4 +axis_broadcaster_v1_1_18=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_18 +axis_combiner_v1_1_17=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_17 +axi_apb_bridge_v3_0_15=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_15 +displayport_v9_0_1=$RDI_DATADIR/xsim/ip/displayport_v9_0_1 +clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2 +hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1 +axi_register_slice_v2_1_19=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_19 +vid_phy_controller_v2_1_5=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_5 +picxo=$RDI_DATADIR/xsim/ip/picxo +usxgmii_v1_1_0=$RDI_DATADIR/xsim/ip/usxgmii_v1_1_0 +v_vcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_13 +bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0 +prc_v1_3_2=$RDI_DATADIR/xsim/ip/prc_v1_3_2 +axi_usb2_device_v5_0_20=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_20 +lte_3gpp_mimo_encoder_v4_0_14=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_14 +l_ethernet_v2_5_2=$RDI_DATADIR/xsim/ip/l_ethernet_v2_5_2 +xdma_v4_1_3=$RDI_DATADIR/xsim/ip/xdma_v4_1_3 +axis_vio_v1_0_0=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_0 +c_counter_binary_v12_0_13=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_13 +noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0 +xbip_dsp48_macro_v3_0_17=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_17 +c_accum_v12_0_13=$RDI_DATADIR/xsim/ip/c_accum_v12_0_13 +xbip_multadd_v3_0_14=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_14 +axi_uartlite_v2_0_23=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_23 +noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0 +axi_intc_v4_1_13=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_13 +i2s_transmitter_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_3 +pc_cfr_v6_0_8=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_8 +mutex_v2_1_10=$RDI_DATADIR/xsim/ip/mutex_v2_1_10 +c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6 +sid_v8_0_14=$RDI_DATADIR/xsim/ip/sid_v8_0_14 +fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6 +quadsgmii_v3_4_6=$RDI_DATADIR/xsim/ip/quadsgmii_v3_4_6 +microblaze_v11_0_1=$RDI_DATADIR/xsim/ip/microblaze_v11_0_1 +lib_bmg_v1_0_12=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_12 +dds_compiler_v6_0_18=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_18 +me_pl_v1_0=$RDI_DATADIR/xsim/ip/me_pl_v1_0 +gtwizard_ultrascale_v1_7_6=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_6 +axis_clock_converter_v1_1_20=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_20 +nvmeha_v1_0_0=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_0 +tmr_inject_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_3 +axi_mcdma_v1_1_0=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_0 +axi_hwicap_v3_0_23=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_23 +v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0 +v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0 +canfd_v2_0_1=$RDI_DATADIR/xsim/ip/canfd_v2_0_1 +gig_ethernet_pcs_pma_v16_1_6=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_6 +lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2 +ieee802d3_rs_fec_v2_0_5=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_5 +ibert_lib_v1_0_6=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_6 +high_speed_selectio_wiz_v3_4_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_1 +xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6 +fec_5g_common_v1_0_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_1 +tmr_voter_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_2 +hdmi_gt_controller_v1_0_0=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_0 +axi_traffic_gen_v2_0_20=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_20 +flexo_100g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_11 +v_smpte_uhdsdi_v1_0_7=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_7 +xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6 +fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10 +ieee802d3_rs_fec_v1_0_15=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_15 +axis_subset_converter_v1_1_19=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_19 +noc_nmu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_v1_0_0 +duc_ddc_compiler_v3_0_15=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_15 +dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13 +mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0 +ieee802d3_200g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_7 +sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1 +mrmac_v1_0_0=$RDI_DATADIR/xsim/ip/mrmac_v1_0_0 +sem_ultra_v3_1_11=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_11 +v_tpg_v8_0_1=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_1 +axi_tft_v2_0_22=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_22 +ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13 +switch_core_top_v1_0_7=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_7 +rama_v1_1_2_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_2_lib +v_hcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_13 +emb_fifo_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_1 +hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3 +axis_data_fifo_v2_0_1=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_1 +hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0 +rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1 +displayport_v8_1_1=$RDI_DATADIR/xsim/ip/displayport_v8_1_1 +axi_mmu_v2_1_17=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_17 +proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13 +pc_cfr_v6_3_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_3_0 +v_osd_v6_0_16=$RDI_DATADIR/xsim/ip/v_osd_v6_0_16 +pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12 +xfft_v9_0_17=$RDI_DATADIR/xsim/ip/xfft_v9_0_17 +axi_cdma_v4_1_19=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_19 +audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0 +lib_fifo_v1_0_13=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_13 +v_enhance_v8_0_15=$RDI_DATADIR/xsim/ip/v_enhance_v8_0_15 +axi_clock_converter_v2_1_18=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_18 +xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0 +emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5 +axi_mm2s_mapper_v1_1_18=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_18 +xfft_v7_2_9=$RDI_DATADIR/xsim/ip/xfft_v7_2_9 +pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0 +v_smpte_sdi_v3_0_8=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_8 +fir_compiler_v7_2_12=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_12 +div_gen_v5_1_15=$RDI_DATADIR/xsim/ip/div_gen_v5_1_15 +mdm_v3_2_16=$RDI_DATADIR/xsim/ip/mdm_v3_2_16 +v_axi4s_remap_v1_0_11=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_11 +xxv_ethernet_v2_5_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_5_3 +xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2 +ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig +remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4 +pr_axi_shutdown_manager_v1_0_1=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_1 +axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0 +smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0 +axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib +axi_dwidth_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_19 +xlconstant_v1_1_6=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_6 +tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6 +mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2 +v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1 +axi_fifo_mm_s_v4_2_1=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_1 +util_idelay_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_1 +rs_toolbox_v9_0_7=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_7 +v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0 +dsp_macro_v1_0_0=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_0 +pc_cfr_v6_2_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_2 +axi_timer_v2_0_21=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_21 +high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1 +axi_sideband_util_v1_0_3=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_3 +sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2 +gmii_to_rgmii_v4_0_7=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_0_7 +xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2 +high_speed_selectio_wiz_v3_5_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_5_1 +axi_msg_v1_0_5=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_5 +axi_ahblite_bridge_v3_0_16=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_16 +v_rgb2ycrcb_v7_1_13=$RDI_DATADIR/xsim/ip/v_rgb2ycrcb_v7_1_13 +v_mix_v4_0_0=$RDI_DATADIR/xsim/ip/v_mix_v4_0_0 +axi_ethernetlite_v3_0_17=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_17 +axi_uart16550_v2_0_21=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_21 +axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0 +vfb_v1_0_13=$RDI_DATADIR/xsim/ip/vfb_v1_0_13 +advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0 +ats_switch_v1_0_2=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_2 +interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4 +axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub +cpri_v8_10_3=$RDI_DATADIR/xsim/ip/cpri_v8_10_3 +c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6 +v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0 +stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0 +rld3_pl_v1_0_1=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_1 +ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0 +lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0 +axi_epc_v2_0_22=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_22 +g709_rs_encoder_v2_2_6=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_6 +blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6 +tmr_sem_v1_0_9=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_9 +fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6 +axi_vdma_v6_3_7=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_7 +axis_data_fifo_v1_1_20=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_20 +xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip +axi_ethernet_buffer_v2_0_20=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_20 +rs_encoder_v9_0_15=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_15 +axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0 +ta_dma_v1_0_3=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_3 +tcc_encoder_3gpp_v5_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_15 +axi_perf_mon_v5_0_21=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_21 +noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0 +sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1 +lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2 +v_csc_v1_0_13=$RDI_DATADIR/xsim/ip/v_csc_v1_0_13 +shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0 +lte_fft_v2_0_18=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_18 +gtwizard_ultrascale_v1_6_11=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_11 +amm_axi_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_5 +mii_to_rmii_v2_0_21=$RDI_DATADIR/xsim/ip/mii_to_rmii_v2_0_21 +videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5 +audio_clock_recovery_v1_0=$RDI_DATADIR/xsim/ip/audio_clock_recovery_v1_0 +cmac_v2_4_1=$RDI_DATADIR/xsim/ip/cmac_v2_4_1 +i2s_receiver_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_3 +v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0 +v_demosaic_v1_0_5=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_5 +remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4 +microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4 +hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3 +etrnic_v1_0_3=$RDI_DATADIR/xsim/ip/etrnic_v1_0_3 +xfft_v9_1_2=$RDI_DATADIR/xsim/ip/xfft_v9_1_2 +ddr4_pl_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_2 +xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6 +cmac_usplus_v2_5_3=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_5_3 +jesd204c_v4_1_1=$RDI_DATADIR/xsim/ip/jesd204c_v4_1_1 +debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1 +axis_protocol_checker_v2_0_3=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_3 +v_frmbuf_wr_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_2 +v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9 +mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4 +lte_dl_channel_encoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_15 +axi_protocol_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_19 +xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0 +clk_gen_sim_v1_0_0=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_0 +axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0 +microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7 +cmpy_v6_0_17=$RDI_DATADIR/xsim/ip/cmpy_v6_0_17 +cmac_v2_3_5=$RDI_DATADIR/xsim/ip/cmac_v2_3_5 +ieee802d3_400g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_7 +xxv_ethernet_v2_4_5=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_4_5 +axi_timebase_wdt_v3_0_11=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_11 +tcc_decoder_3gppmm_v2_0_18=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_18 +v_deinterlacer_v5_0_13=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_13 +dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16 +axi_fifo_mm_s_v4_1_16=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_16 +processing_system7_vip_v1_0_7=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_7 +g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18 +rs_decoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_16 +c_shift_ram_v12_0_13=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_13 +displayport_v7_0_11=$RDI_DATADIR/xsim/ip/displayport_v7_0_11 +v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0 +v_deinterlacer_v4_0_12=$RDI_DATADIR/xsim/ip/v_deinterlacer_v4_0_12 +sem_v4_1_12=$RDI_DATADIR/xsim/ip/sem_v4_1_12 +xaui_v12_3_6=$RDI_DATADIR/xsim/ip/xaui_v12_3_6 +ten_gig_eth_mac_v15_1_7=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_7 +oddr_v1_0_0=$RDI_DATADIR/xsim/ip/oddr_v1_0_0 +c_addsub_v12_0_13=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_13 +v_ccm_v6_0_15=$RDI_DATADIR/xsim/ip/v_ccm_v6_0_15 +zynq_ultra_ps_e_vip_v1_0_5=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_5 +cic_compiler_v4_0_14=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_14 +c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6 +axi_memory_init_v1_0_0=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_0 +pr_decoupler_v1_0_7=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_7 +timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4 +lte_pucch_receiver_v2_0_16=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_16 +zynq_ultra_ps_e_v3_2_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_3 +v_gamma_lut_v1_0_5=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_5 +bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0 +pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0 +tcc_encoder_3gpplte_v4_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_15 +polar_v1_0_3=$RDI_DATADIR/xsim/ip/polar_v1_0_3 +rxaui_v4_4_6=$RDI_DATADIR/xsim/ip/rxaui_v4_4_6 +xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6 +v_gamma_v7_0_15=$RDI_DATADIR/xsim/ip/v_gamma_v7_0_15 +ernic_v1_0_1=$RDI_DATADIR/xsim/ip/ernic_v1_0_1 +high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3 +mailbox_v2_1_11=$RDI_DATADIR/xsim/ip/mailbox_v2_1_11 +video_frame_crc_v1_0_1=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_1 +axi_sg_v4_1_12=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_12 +ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0 +lmb_bram_if_cntlr_v4_0_16=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_16 +l_ethernet_v2_4_3=$RDI_DATADIR/xsim/ip/l_ethernet_v2_4_3 +dft_v4_1_1=$RDI_DATADIR/xsim/ip/dft_v4_1_1 +rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0 +axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6 +v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0 +stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0 +lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0 +uhdsdi_gt_v1_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_3 +pc_cfr_v6_1_4=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_4 +lmb_v10_v3_0_9=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_9 +axis_interconnect_v1_1_17=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_17 +cordic_v6_0_15=$RDI_DATADIR/xsim/ip/cordic_v6_0_15 +axis_register_slice_v1_1_19=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_19 +axis_switch_v1_1_19=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_19 +axi_interconnect_v1_7_16=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_16 +mult_gen_v12_0_15=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_15 +spdif_v2_0_21=$RDI_DATADIR/xsim/ip/spdif_v2_0_21 +v_hscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_13 +ethernet_1_10_25g_v2_3_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_3_3 +xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6 +axi_quad_spi_v3_2_18=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_18 +axi_bram_ctrl_v4_1_1=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_1 +axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4 +axi_protocol_checker_v2_0_5=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_5 +axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0 +mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7 +ieee802d3_25g_rs_fec_v1_0_13=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_13 +aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0 +xtlm=$RDI_DATADIR/xsim/ip/xtlm +iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0 +ieee802d3_clause74_fec_v1_0_4=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_4 +xlconcat_v2_1_3=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_3 +perf_axi_tg_v1_0_8=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_8 +axi_crossbar_v2_1_20=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_20 +tsn_endpoint_ethernet_mac_block_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_4 +v_ycrcb2rgb_v7_1_13=$RDI_DATADIR/xsim/ip/v_ycrcb2rgb_v7_1_13 +xhmc_v1_0_9=$RDI_DATADIR/xsim/ip/xhmc_v1_0_9 +dp_videoaxi4s_bridge_v1_0_0=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_0 +lte_ul_channel_decoder_v4_0_16=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_16 +soft_ecc_proxy_v1_0_0=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_0 +pr_bitstream_monitor_v1_0_1=$RDI_DATADIR/xsim/ip/pr_bitstream_monitor_v1_0_1 +sync_ip=$RDI_DATADIR/xsim/ip/sync_ip +v_frmbuf_rd_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_1_2 +c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6 +cmac_usplus_v2_6_2=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_6_2 +axi_mcdma_v1_0_5=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_5 +c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6 +g709_fec_v2_4_1=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_1 +lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0 +ai_pl=$RDI_DATADIR/xsim/ip/ai_pl +fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4 +v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0 +l_ethernet_v2_3_5=$RDI_DATADIR/xsim/ip/l_ethernet_v2_3_5 +microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6 +v_uhdsdi_audio_v2_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_1 +ldpc_v2_0_3=$RDI_DATADIR/xsim/ip/ldpc_v2_0_3 +xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6 +xpm=$RDI_DATADIR/xsim/ip/xpm +srio_gen2_v4_1_6=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_6 +g975_efec_i4_v1_0_17=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_17 +noc_na_v1_0_0=$RDI_DATADIR/xsim/ip/noc_na_v1_0_0 +roe_framer_v2_0_1=$RDI_DATADIR/xsim/ip/roe_framer_v2_0_1 +xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10 +generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0 +ten_gig_eth_pcs_pma_v6_0_15=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_15 +can_v5_0_22=$RDI_DATADIR/xsim/ip/can_v5_0_22 +av_pat_gen_v1_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_0 +fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1 +lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0 +axis_dwidth_converter_v1_1_18=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_18 +lte_rach_detector_v3_1_5=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_5 +xxv_ethernet_v3_0_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v3_0_3 +axi_iic_v2_0_22=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_22 +axi_pcie_v2_9_1=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_1 +util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4 +sim_trig_top_v1_0=$RDI_DATADIR/xsim/ip/sim_trig_top_v1_0 +v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0 +v_tpg_v7_0_13=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_13 +sd_fec_v1_1_3=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_3 +xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6 +lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2 +v_multi_scaler_v1_0_1=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_0_1 +axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0 +advanced_io_wizard_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_0 +mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8 +axi_pcie3_v3_0_9=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_9 +axi_vfifo_ctrl_v2_0_21=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_21 +xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/README.txt new file mode 100644 index 00000000..9e224e68 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Mar 19 17:32:07 +0800 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./selectio_lvds_tx.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './selectio_lvds_tx.sh' script. + +./selectio_lvds_tx.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./selectio_lvds_tx.sh -noclean_files + +For more information on the script, please type './selectio_lvds_tx.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/compile.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/compile.do new file mode 100644 index 00000000..90297657 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/compile.do @@ -0,0 +1,23 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v" \ +"../../../ip/selectio_lvds_tx/selectio_lvds_tx.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/file_info.txt new file mode 100644 index 00000000..eddbf85c --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +selectio_lvds_tx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v, +selectio_lvds_tx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/selectio_lvds_tx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/selectio_lvds_tx.sh new file mode 100644 index 00000000..85b5cc3a --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/selectio_lvds_tx.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : selectio_lvds_tx.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Mar 19 17:32:07 +0800 2023 +# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: selectio_lvds_tx.sh [-help] +# usage: selectio_lvds_tx.sh [-lib_map_path] +# usage: selectio_lvds_tx.sh [-noclean_files] +# usage: selectio_lvds_tx.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'selectio_lvds_tx.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "selectio_lvds_tx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_tx.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/activehdl" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_tx.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: selectio_lvds_tx.sh [-help]\n\ +Usage: selectio_lvds_tx.sh [-lib_map_path]\n\ +Usage: selectio_lvds_tx.sh [-reset_run]\n\ +Usage: selectio_lvds_tx.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/selectio_lvds_tx.udo b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/selectio_lvds_tx.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/simulate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/simulate.do new file mode 100644 index 00000000..934173ec --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+selectio_lvds_tx -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.selectio_lvds_tx xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {selectio_lvds_tx.udo} + +run -all + +endsim + +quit -force diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/wave.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/README.txt new file mode 100644 index 00000000..03fedd1b --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Mar 19 17:32:07 +0800 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./selectio_lvds_tx.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './selectio_lvds_tx.sh' script. + +./selectio_lvds_tx.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./selectio_lvds_tx.sh -noclean_files + +For more information on the script, please type './selectio_lvds_tx.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/file_info.txt new file mode 100644 index 00000000..eddbf85c --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +selectio_lvds_tx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v, +selectio_lvds_tx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/run.f b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/run.f new file mode 100644 index 00000000..de95176a --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/run.f @@ -0,0 +1,15 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v" \ + "../../../ip/selectio_lvds_tx/selectio_lvds_tx.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/selectio_lvds_tx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/selectio_lvds_tx.sh new file mode 100644 index 00000000..4188c992 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/ies/selectio_lvds_tx.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : selectio_lvds_tx.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Mar 19 17:32:07 +0800 2023 +# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: selectio_lvds_tx.sh [-help] +# usage: selectio_lvds_tx.sh [-lib_map_path] +# usage: selectio_lvds_tx.sh [-noclean_files] +# usage: selectio_lvds_tx.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'selectio_lvds_tx.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "selectio_lvds_tx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.selectio_lvds_tx \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_tx.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_tx.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: selectio_lvds_tx.sh [-help]\n\ +Usage: selectio_lvds_tx.sh [-lib_map_path]\n\ +Usage: selectio_lvds_tx.sh [-reset_run]\n\ +Usage: selectio_lvds_tx.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/README.txt new file mode 100644 index 00000000..9e224e68 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Mar 19 17:32:07 +0800 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./selectio_lvds_tx.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './selectio_lvds_tx.sh' script. + +./selectio_lvds_tx.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./selectio_lvds_tx.sh -noclean_files + +For more information on the script, please type './selectio_lvds_tx.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/compile.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/compile.do new file mode 100644 index 00000000..9905d936 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/compile.do @@ -0,0 +1,15 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xil_defaultlib -64 -incr \ +"../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v" \ +"../../../ip/selectio_lvds_tx/selectio_lvds_tx.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/file_info.txt new file mode 100644 index 00000000..3f418daf --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/file_info.txt @@ -0,0 +1,3 @@ +selectio_lvds_tx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v, +selectio_lvds_tx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/modelsim.ini b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/modelsim.ini new file mode 100644 index 00000000..04a43f2c --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/modelsim.ini @@ -0,0 +1,2590 @@ +; vsim modelsim.ini file +[Version] +INIVersion = "2020.4" + +; Copyright 1991-2020 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini +; +; VITAL concerns: +; +; The library ieee contains (among other packages) the packages of the +; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use +; the physical library ieee (recommended), or use the physical library +; vital2000, but not both. The design can use logical library ieee and/or +; vital2000 as long as each of these maps to the same physical library, either +; ieee or vital2000. +; +; A design using the 1995 version of the VITAL packages, whether or not +; it also uses the 2000 version of the VITAL packages, must have logical library +; name ieee mapped to physical library vital1995. (A design cannot use library +; vital1995 directly because some packages in this library use logical name ieee +; when referring to the other packages in the library.) The design source +; should use logical name ieee when referring to any packages there except the +; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical +; name vital2000 (mapped to physical library vital2000) to refer to those +; packages. +; ieee = $MODEL_TECH/../vital1995 +; +; For compatiblity with previous releases, logical library name vital2000 maps +; to library vital2000 (a different library than library ieee, containing the +; same packages). +; A design should not reference VITAL from both the ieee library and the +; vital2000 library because the vital packages are effectively different. +; A design that references both the ieee and vital2000 libraries must have +; both logical names ieee and vital2000 mapped to the same library, either of +; these: +; $MODEL_TECH/../ieee +; $MODEL_TECH/../vital2000 +; + +; added mapping for ADMS + +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib + +; Automatically perform logical->physical mapping for physical libraries that +; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). +; The tail of the filesystem path name is chosen as the logical library name. +; For example, in the command "vopt -L ./path/to/lib1 -o opttop top", +; vopt automatically performs the mapping "lib1 -> ./path/to/lib1". +; See the User Manual for more details. +; +; AutoLibMapping = 0 + +secureip = C:/Mentor/CompLib/2019.1.3/secureip +unisim = C:/Mentor/CompLib/2019.1.3/unisim +unimacro = C:/Mentor/CompLib/2019.1.3/unimacro +unifast = C:/Mentor/CompLib/2019.1.3/unifast +unisims_ver = C:/Mentor/CompLib/2019.1.3/unisims_ver +unimacro_ver = C:/Mentor/CompLib/2019.1.3/unimacro_ver +unifast_ver = C:/Mentor/CompLib/2019.1.3/unifast_ver +simprims_ver = C:/Mentor/CompLib/2019.1.3/simprims_ver +xpm = C:/Mentor/CompLib/2019.1.3/xpm +xilinx_vip = C:/Mentor/CompLib/2019.1.3/xilinx_vip +advanced_io_wizard_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/advanced_io_wizard_phy_v1_0_0 +advanced_io_wizard_v1_0_0 = C:/Mentor/CompLib/2019.1.3/advanced_io_wizard_v1_0_0 +ahblite_axi_bridge_v3_0_14 = C:/Mentor/CompLib/2019.1.3/ahblite_axi_bridge_v3_0_14 +ai_noc = C:/Mentor/CompLib/2019.1.3/ai_noc +ai_pl_trig = C:/Mentor/CompLib/2019.1.3/ai_pl_trig +ai_pl = C:/Mentor/CompLib/2019.1.3/ai_pl +audio_clock_recovery_v1_0 = C:/Mentor/CompLib/2019.1.3/audio_clock_recovery_v1_0 +audio_tpg_v1_0_0 = C:/Mentor/CompLib/2019.1.3/audio_tpg_v1_0_0 +av_pat_gen_v1_0_0 = C:/Mentor/CompLib/2019.1.3/av_pat_gen_v1_0_0 +axis_infrastructure_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axis_infrastructure_v1_1_0 +axis_protocol_checker_v2_0_3 = C:/Mentor/CompLib/2019.1.3/axis_protocol_checker_v2_0_3 +axi_ahblite_bridge_v3_0_16 = C:/Mentor/CompLib/2019.1.3/axi_ahblite_bridge_v3_0_16 +axi_amm_bridge_v1_0_9 = C:/Mentor/CompLib/2019.1.3/axi_amm_bridge_v1_0_9 +axi_bram_ctrl_v4_1_1 = C:/Mentor/CompLib/2019.1.3/axi_bram_ctrl_v4_1_1 +axi_chip2chip_v5_0_6 = C:/Mentor/CompLib/2019.1.3/axi_chip2chip_v5_0_6 +axi_dbg_hub = C:/Mentor/CompLib/2019.1.3/axi_dbg_hub +axi_infrastructure_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axi_infrastructure_v1_1_0 +axi_jtag_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_jtag_v1_0_0 +axi_lite_ipif_v3_0_4 = C:/Mentor/CompLib/2019.1.3/axi_lite_ipif_v3_0_4 +axi_pcie3_v3_0_9 = C:/Mentor/CompLib/2019.1.3/axi_pcie3_v3_0_9 +axi_perf_mon_v5_0_21 = C:/Mentor/CompLib/2019.1.3/axi_perf_mon_v5_0_21 +axi_pmon_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_pmon_v1_0_0 +blk_mem_gen_v8_3_6 = C:/Mentor/CompLib/2019.1.3/blk_mem_gen_v8_3_6 +blk_mem_gen_v8_4_3 = C:/Mentor/CompLib/2019.1.3/blk_mem_gen_v8_4_3 +bsip_v1_1_0 = C:/Mentor/CompLib/2019.1.3/bsip_v1_1_0 +bs_mux_v1_0_0 = C:/Mentor/CompLib/2019.1.3/bs_mux_v1_0_0 +clk_gen_sim_v1_0_0 = C:/Mentor/CompLib/2019.1.3/clk_gen_sim_v1_0_0 +clk_vip_v1_0_2 = C:/Mentor/CompLib/2019.1.3/clk_vip_v1_0_2 +cmac_usplus_v2_4_5 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_4_5 +cmac_usplus_v2_5_3 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_5_3 +cmac_usplus_v2_6_2 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_6_2 +cmac_v2_3_5 = C:/Mentor/CompLib/2019.1.3/cmac_v2_3_5 +cmac_v2_4_1 = C:/Mentor/CompLib/2019.1.3/cmac_v2_4_1 +cmac_v2_5_1 = C:/Mentor/CompLib/2019.1.3/cmac_v2_5_1 +compact_gt_v1_0_5 = C:/Mentor/CompLib/2019.1.3/compact_gt_v1_0_5 +ddr4_pl_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/ddr4_pl_phy_v1_0_0 +ddr4_pl_v1_0_2 = C:/Mentor/CompLib/2019.1.3/ddr4_pl_v1_0_2 +dist_mem_gen_v8_0_13 = C:/Mentor/CompLib/2019.1.3/dist_mem_gen_v8_0_13 +ecc_v2_0_13 = C:/Mentor/CompLib/2019.1.3/ecc_v2_0_13 +emb_fifo_gen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/emb_fifo_gen_v1_0_1 +emb_mem_gen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/emb_mem_gen_v1_0_1 +emc_common_v3_0_5 = C:/Mentor/CompLib/2019.1.3/emc_common_v3_0_5 +ethernet_1_10_25g_v2_0_5 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_0_5 +ethernet_1_10_25g_v2_1_4 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_1_4 +ethernet_1_10_25g_v2_2_3 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_2_3 +ethernet_1_10_25g_v2_3_3 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_3_3 +fifo_generator_v13_0_6 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_0_6 +fifo_generator_v13_1_4 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_1_4 +fifo_generator_v13_2_4 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_2_4 +fit_timer_v2_0_10 = C:/Mentor/CompLib/2019.1.3/fit_timer_v2_0_10 +generic_baseblocks_v2_1_0 = C:/Mentor/CompLib/2019.1.3/generic_baseblocks_v2_1_0 +gigantic_mux = C:/Mentor/CompLib/2019.1.3/gigantic_mux +gig_ethernet_pcs_pma_v16_1_6 = C:/Mentor/CompLib/2019.1.3/gig_ethernet_pcs_pma_v16_1_6 +gmii_to_rgmii_v4_0_7 = C:/Mentor/CompLib/2019.1.3/gmii_to_rgmii_v4_0_7 +gtwizard_ultrascale_v1_5_4 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_5_4 +gtwizard_ultrascale_v1_6_11 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_6_11 +gtwizard_ultrascale_v1_7_6 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_7_6 +hbm_v1_0_4 = C:/Mentor/CompLib/2019.1.3/hbm_v1_0_4 +hdcp22_cipher_dp_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdcp22_cipher_dp_v1_0_0 +hdcp22_cipher_v1_0_3 = C:/Mentor/CompLib/2019.1.3/hdcp22_cipher_v1_0_3 +hdcp22_rng_v1_0_1 = C:/Mentor/CompLib/2019.1.3/hdcp22_rng_v1_0_1 +hdcp_keymngmt_blk_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdcp_keymngmt_blk_v1_0_0 +hdcp_v1_0_3 = C:/Mentor/CompLib/2019.1.3/hdcp_v1_0_3 +hdmi_gt_controller_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdmi_gt_controller_v1_0_0 +high_speed_selectio_wiz_v3_2_3 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_2_3 +high_speed_selectio_wiz_v3_3_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_3_1 +high_speed_selectio_wiz_v3_4_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_4_1 +high_speed_selectio_wiz_v3_5_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_5_1 +i2s_receiver_v1_0_3 = C:/Mentor/CompLib/2019.1.3/i2s_receiver_v1_0_3 +i2s_transmitter_v1_0_3 = C:/Mentor/CompLib/2019.1.3/i2s_transmitter_v1_0_3 +ibert_lib_v1_0_6 = C:/Mentor/CompLib/2019.1.3/ibert_lib_v1_0_6 +ieee802d3_clause74_fec_v1_0_4 = C:/Mentor/CompLib/2019.1.3/ieee802d3_clause74_fec_v1_0_4 +interlaken_v2_4_3 = C:/Mentor/CompLib/2019.1.3/interlaken_v2_4_3 +in_system_ibert_v1_0_9 = C:/Mentor/CompLib/2019.1.3/in_system_ibert_v1_0_9 +iomodule_v3_1_4 = C:/Mentor/CompLib/2019.1.3/iomodule_v3_1_4 +jesd204c_v4_1_1 = C:/Mentor/CompLib/2019.1.3/jesd204c_v4_1_1 +jesd204_v7_2_6 = C:/Mentor/CompLib/2019.1.3/jesd204_v7_2_6 +jtag_axi = C:/Mentor/CompLib/2019.1.3/jtag_axi +lib_cdc_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_cdc_v1_0_2 +lib_pkg_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_pkg_v1_0_2 +lmb_bram_if_cntlr_v4_0_16 = C:/Mentor/CompLib/2019.1.3/lmb_bram_if_cntlr_v4_0_16 +lmb_v10_v3_0_9 = C:/Mentor/CompLib/2019.1.3/lmb_v10_v3_0_9 +ltlib_v1_0_0 = C:/Mentor/CompLib/2019.1.3/ltlib_v1_0_0 +lut_buffer_v1_0_0 = C:/Mentor/CompLib/2019.1.3/lut_buffer_v1_0_0 +lut_buffer_v2_0_0 = C:/Mentor/CompLib/2019.1.3/lut_buffer_v2_0_0 +l_ethernet_v2_3_5 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_3_5 +l_ethernet_v2_4_3 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_4_3 +l_ethernet_v2_5_2 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_5_2 +mammoth_transcode_v1_0_0 = C:/Mentor/CompLib/2019.1.3/mammoth_transcode_v1_0_0 +microblaze_v10_0_7 = C:/Mentor/CompLib/2019.1.3/microblaze_v10_0_7 +microblaze_v11_0_1 = C:/Mentor/CompLib/2019.1.3/microblaze_v11_0_1 +microblaze_v9_5_4 = C:/Mentor/CompLib/2019.1.3/microblaze_v9_5_4 +mii_to_rmii_v2_0_21 = C:/Mentor/CompLib/2019.1.3/mii_to_rmii_v2_0_21 +mipi_csi2_rx_ctrl_v1_0_8 = C:/Mentor/CompLib/2019.1.3/mipi_csi2_rx_ctrl_v1_0_8 +mipi_csi2_tx_ctrl_v1_0_4 = C:/Mentor/CompLib/2019.1.3/mipi_csi2_tx_ctrl_v1_0_4 +mipi_dphy_v4_1_4 = C:/Mentor/CompLib/2019.1.3/mipi_dphy_v4_1_4 +mipi_dsi_tx_ctrl_v1_0_7 = C:/Mentor/CompLib/2019.1.3/mipi_dsi_tx_ctrl_v1_0_7 +mrmac_v1_0_0 = C:/Mentor/CompLib/2019.1.3/mrmac_v1_0_0 +multi_channel_25g_rs_fec_v1_0_5 = C:/Mentor/CompLib/2019.1.3/multi_channel_25g_rs_fec_v1_0_5 +mutex_v2_1_10 = C:/Mentor/CompLib/2019.1.3/mutex_v2_1_10 +axi_tg_lib = C:/Mentor/CompLib/2019.1.3/axi_tg_lib +noc_na_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_na_v1_0_0 +noc_nidb_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nidb_v1_0_0 +noc_nmu_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nmu_v1_0_0 +noc_nps_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nps_v1_0_0 +nvmeha_v1_0_0 = C:/Mentor/CompLib/2019.1.3/nvmeha_v1_0_0 +oddr_v1_0_0 = C:/Mentor/CompLib/2019.1.3/oddr_v1_0_0 +pci32_v5_0_12 = C:/Mentor/CompLib/2019.1.3/pci32_v5_0_12 +pci64_v5_0_11 = C:/Mentor/CompLib/2019.1.3/pci64_v5_0_11 +pcie_jtag_v1_0_0 = C:/Mentor/CompLib/2019.1.3/pcie_jtag_v1_0_0 +pc_cfr_v6_0_8 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_0_8 +pc_cfr_v6_1_4 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_1_4 +pc_cfr_v6_2_2 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_2_2 +pc_cfr_v6_3_0 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_3_0 +picxo = C:/Mentor/CompLib/2019.1.3/picxo +qdma_v3_0_2 = C:/Mentor/CompLib/2019.1.3/qdma_v3_0_2 +rama_v1_1_2_lib = C:/Mentor/CompLib/2019.1.3/rama_v1_1_2_lib +rld3_pl_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/rld3_pl_phy_v1_0_0 +rld3_pl_v1_0_1 = C:/Mentor/CompLib/2019.1.3/rld3_pl_v1_0_1 +roe_framer_v2_0_1 = C:/Mentor/CompLib/2019.1.3/roe_framer_v2_0_1 +rst_vip_v1_0_3 = C:/Mentor/CompLib/2019.1.3/rst_vip_v1_0_3 +smartconnect_v1_0 = C:/Mentor/CompLib/2019.1.3/smartconnect_v1_0 +sd_fec_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sd_fec_v1_0_2 +sem_ultra_v3_1_11 = C:/Mentor/CompLib/2019.1.3/sem_ultra_v3_1_11 +sem_v4_1_12 = C:/Mentor/CompLib/2019.1.3/sem_v4_1_12 +shell_utils_msp432_bsl_crc_gen_v1_0_0 = C:/Mentor/CompLib/2019.1.3/shell_utils_msp432_bsl_crc_gen_v1_0_0 +sim_clk_gen_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sim_clk_gen_v1_0_2 +sim_rst_gen_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sim_rst_gen_v1_0_2 +sim_trig_top_v1_0 = C:/Mentor/CompLib/2019.1.3/sim_trig_top_v1_0 +stm_v1_0 = C:/Mentor/CompLib/2019.1.3/stm_v1_0 +stm_v1_0_0 = C:/Mentor/CompLib/2019.1.3/stm_v1_0_0 +system_cache_v4_0_6 = C:/Mentor/CompLib/2019.1.3/system_cache_v4_0_6 +ta_dma_v1_0_3 = C:/Mentor/CompLib/2019.1.3/ta_dma_v1_0_3 +tcc_decoder_3gpplte_v3_0_6 = C:/Mentor/CompLib/2019.1.3/tcc_decoder_3gpplte_v3_0_6 +ten_gig_eth_mac_v15_1_7 = C:/Mentor/CompLib/2019.1.3/ten_gig_eth_mac_v15_1_7 +ten_gig_eth_pcs_pma_v6_0_15 = C:/Mentor/CompLib/2019.1.3/ten_gig_eth_pcs_pma_v6_0_15 +timer_sync_1588_v1_2_4 = C:/Mentor/CompLib/2019.1.3/timer_sync_1588_v1_2_4 +tmr_inject_v1_0_3 = C:/Mentor/CompLib/2019.1.3/tmr_inject_v1_0_3 +tmr_manager_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tmr_manager_v1_0_4 +tmr_voter_v1_0_2 = C:/Mentor/CompLib/2019.1.3/tmr_voter_v1_0_2 +tsn_endpoint_ethernet_mac_block_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tsn_endpoint_ethernet_mac_block_v1_0_4 +uhdsdi_gt_v1_0_3 = C:/Mentor/CompLib/2019.1.3/uhdsdi_gt_v1_0_3 +uhdsdi_gt_v2_0_0 = C:/Mentor/CompLib/2019.1.3/uhdsdi_gt_v2_0_0 +usxgmii_v1_0_5 = C:/Mentor/CompLib/2019.1.3/usxgmii_v1_0_5 +usxgmii_v1_1_0 = C:/Mentor/CompLib/2019.1.3/usxgmii_v1_1_0 +util_idelay_ctrl_v1_0_1 = C:/Mentor/CompLib/2019.1.3/util_idelay_ctrl_v1_0_1 +util_reduced_logic_v2_0_4 = C:/Mentor/CompLib/2019.1.3/util_reduced_logic_v2_0_4 +util_vector_logic_v2_0_1 = C:/Mentor/CompLib/2019.1.3/util_vector_logic_v2_0_1 +ba317 = C:/Mentor/CompLib/2019.1.3/ba317 +vfb_v1_0_13 = C:/Mentor/CompLib/2019.1.3/vfb_v1_0_13 +video_frame_crc_v1_0_1 = C:/Mentor/CompLib/2019.1.3/video_frame_crc_v1_0_1 +vid_edid_v1_0_0 = C:/Mentor/CompLib/2019.1.3/vid_edid_v1_0_0 +vid_phy_controller_v2_1_5 = C:/Mentor/CompLib/2019.1.3/vid_phy_controller_v2_1_5 +vid_phy_controller_v2_2_3 = C:/Mentor/CompLib/2019.1.3/vid_phy_controller_v2_2_3 +v_axi4s_remap_v1_0_11 = C:/Mentor/CompLib/2019.1.3/v_axi4s_remap_v1_0_11 +v_csc_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_csc_v1_0_13 +v_deinterlacer_v4_0_12 = C:/Mentor/CompLib/2019.1.3/v_deinterlacer_v4_0_12 +v_deinterlacer_v5_0_13 = C:/Mentor/CompLib/2019.1.3/v_deinterlacer_v5_0_13 +v_demosaic_v1_0_5 = C:/Mentor/CompLib/2019.1.3/v_demosaic_v1_0_5 +v_frmbuf_rd_v2_1_2 = C:/Mentor/CompLib/2019.1.3/v_frmbuf_rd_v2_1_2 +v_frmbuf_wr_v2_1_2 = C:/Mentor/CompLib/2019.1.3/v_frmbuf_wr_v2_1_2 +v_gamma_lut_v1_0_5 = C:/Mentor/CompLib/2019.1.3/v_gamma_lut_v1_0_5 +v_hcresampler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_hcresampler_v1_0_13 +v_hdmi_rx_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_rx_v2_0_0 +v_hdmi_rx_v3_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_rx_v3_0_0 +v_hdmi_tx_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_tx_v2_0_0 +v_hdmi_tx_v3_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_tx_v3_0_0 +v_hscaler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_hscaler_v1_0_13 +v_letterbox_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_letterbox_v1_0_13 +v_mix_v3_0_3 = C:/Mentor/CompLib/2019.1.3/v_mix_v3_0_3 +v_mix_v4_0_0 = C:/Mentor/CompLib/2019.1.3/v_mix_v4_0_0 +v_multi_scaler_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_multi_scaler_v1_0_1 +v_scenechange_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_scenechange_v1_0_1 +v_sdi_rx_vid_bridge_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_sdi_rx_vid_bridge_v2_0_0 +v_smpte_sdi_v3_0_8 = C:/Mentor/CompLib/2019.1.3/v_smpte_sdi_v3_0_8 +v_smpte_uhdsdi_rx_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_rx_v1_0_0 +v_smpte_uhdsdi_tx_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_tx_v1_0_0 +v_smpte_uhdsdi_v1_0_7 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_v1_0_7 +v_tpg_v7_0_13 = C:/Mentor/CompLib/2019.1.3/v_tpg_v7_0_13 +v_tpg_v8_0_1 = C:/Mentor/CompLib/2019.1.3/v_tpg_v8_0_1 +v_uhdsdi_audio_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v1_0_0 +v_uhdsdi_audio_v1_1_0 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v1_1_0 +v_uhdsdi_audio_v2_0_1 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v2_0_1 +v_uhdsdi_vidgen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_vidgen_v1_0_1 +v_vcresampler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_vcresampler_v1_0_13 +v_vid_in_axi4s_v4_0_9 = C:/Mentor/CompLib/2019.1.3/v_vid_in_axi4s_v4_0_9 +v_vscaler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_vscaler_v1_0_13 +xaui_v12_3_6 = C:/Mentor/CompLib/2019.1.3/xaui_v12_3_6 +xbip_dsp48_wrapper_v3_0_4 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_wrapper_v3_0_4 +xbip_utils_v3_0_10 = C:/Mentor/CompLib/2019.1.3/xbip_utils_v3_0_10 +xdma_v4_1_3 = C:/Mentor/CompLib/2019.1.3/xdma_v4_1_3 +xhmc_v1_0_9 = C:/Mentor/CompLib/2019.1.3/xhmc_v1_0_9 +xlconcat_v2_1_3 = C:/Mentor/CompLib/2019.1.3/xlconcat_v2_1_3 +xlconstant_v1_1_6 = C:/Mentor/CompLib/2019.1.3/xlconstant_v1_1_6 +xlslice_v1_0_2 = C:/Mentor/CompLib/2019.1.3/xlslice_v1_0_2 +xsdbm_v2_0_0 = C:/Mentor/CompLib/2019.1.3/xsdbm_v2_0_0 +xsdbm_v3_0_0 = C:/Mentor/CompLib/2019.1.3/xsdbm_v3_0_0 +xxv_ethernet_v2_4_5 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v2_4_5 +xxv_ethernet_v2_5_3 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v2_5_3 +xxv_ethernet_v3_0_3 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v3_0_3 +zynq_ultra_ps_e_v3_2_3 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_v3_2_3 +zynq_ultra_ps_e_v3_3_0 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_v3_3_0 +lib_srl_fifo_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_srl_fifo_v1_0_2 +lib_fifo_v1_0_13 = C:/Mentor/CompLib/2019.1.3/lib_fifo_v1_0_13 +axi_datamover_v5_1_21 = C:/Mentor/CompLib/2019.1.3/axi_datamover_v5_1_21 +amm_axi_bridge_v1_0_5 = C:/Mentor/CompLib/2019.1.3/amm_axi_bridge_v1_0_5 +axis_interconnect_v1_1_17 = C:/Mentor/CompLib/2019.1.3/axis_interconnect_v1_1_17 +ats_switch_v1_0_2 = C:/Mentor/CompLib/2019.1.3/ats_switch_v1_0_2 +audio_formatter_v1_0_1 = C:/Mentor/CompLib/2019.1.3/audio_formatter_v1_0_1 +axi4stream_vip_v1_1_5 = C:/Mentor/CompLib/2019.1.3/axi4stream_vip_v1_1_5 +v_tc_v6_1_13 = C:/Mentor/CompLib/2019.1.3/v_tc_v6_1_13 +v_axi4s_vid_out_v4_0_10 = C:/Mentor/CompLib/2019.1.3/v_axi4s_vid_out_v4_0_10 +axi4svideo_bridge_v1_0_10 = C:/Mentor/CompLib/2019.1.3/axi4svideo_bridge_v1_0_10 +axis_accelerator_adapter_v2_1_15 = C:/Mentor/CompLib/2019.1.3/axis_accelerator_adapter_v2_1_15 +axis_broadcaster_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axis_broadcaster_v1_1_18 +axis_clock_converter_v1_1_20 = C:/Mentor/CompLib/2019.1.3/axis_clock_converter_v1_1_20 +axis_combiner_v1_1_17 = C:/Mentor/CompLib/2019.1.3/axis_combiner_v1_1_17 +axis_data_fifo_v1_1_20 = C:/Mentor/CompLib/2019.1.3/axis_data_fifo_v1_1_20 +axis_data_fifo_v2_0_1 = C:/Mentor/CompLib/2019.1.3/axis_data_fifo_v2_0_1 +axis_register_slice_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_register_slice_v1_1_19 +axis_dwidth_converter_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axis_dwidth_converter_v1_1_18 +axis_subset_converter_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_subset_converter_v1_1_19 +axis_switch_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_switch_v1_1_19 +axis_vio_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axis_vio_v1_0_0 +axi_apb_bridge_v3_0_15 = C:/Mentor/CompLib/2019.1.3/axi_apb_bridge_v3_0_15 +axi_bram_ctrl_v4_0_14 = C:/Mentor/CompLib/2019.1.3/axi_bram_ctrl_v4_0_14 +axi_sg_v4_1_12 = C:/Mentor/CompLib/2019.1.3/axi_sg_v4_1_12 +axi_cdma_v4_1_19 = C:/Mentor/CompLib/2019.1.3/axi_cdma_v4_1_19 +axi_clock_converter_v2_1_18 = C:/Mentor/CompLib/2019.1.3/axi_clock_converter_v2_1_18 +axi_data_fifo_v2_1_18 = C:/Mentor/CompLib/2019.1.3/axi_data_fifo_v2_1_18 +axi_register_slice_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_register_slice_v2_1_19 +axi_crossbar_v2_1_20 = C:/Mentor/CompLib/2019.1.3/axi_crossbar_v2_1_20 +axi_dma_v7_1_20 = C:/Mentor/CompLib/2019.1.3/axi_dma_v7_1_20 +axi_protocol_converter_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_protocol_converter_v2_1_19 +axi_dwidth_converter_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_dwidth_converter_v2_1_19 +axi_emc_v3_0_19 = C:/Mentor/CompLib/2019.1.3/axi_emc_v3_0_19 +axi_epc_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_epc_v2_0_22 +lib_bmg_v1_0_12 = C:/Mentor/CompLib/2019.1.3/lib_bmg_v1_0_12 +axi_ethernetlite_v3_0_17 = C:/Mentor/CompLib/2019.1.3/axi_ethernetlite_v3_0_17 +axi_ethernet_buffer_v2_0_20 = C:/Mentor/CompLib/2019.1.3/axi_ethernet_buffer_v2_0_20 +axi_fifo_mm_s_v4_1_16 = C:/Mentor/CompLib/2019.1.3/axi_fifo_mm_s_v4_1_16 +axi_fifo_mm_s_v4_2_1 = C:/Mentor/CompLib/2019.1.3/axi_fifo_mm_s_v4_2_1 +axi_firewall_v1_0_7 = C:/Mentor/CompLib/2019.1.3/axi_firewall_v1_0_7 +interrupt_control_v3_1_4 = C:/Mentor/CompLib/2019.1.3/interrupt_control_v3_1_4 +axi_gpio_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_gpio_v2_0_21 +axi_hwicap_v3_0_23 = C:/Mentor/CompLib/2019.1.3/axi_hwicap_v3_0_23 +axi_iic_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_iic_v2_0_22 +axi_intc_v4_1_13 = C:/Mentor/CompLib/2019.1.3/axi_intc_v4_1_13 +axi_interconnect_v1_7_16 = C:/Mentor/CompLib/2019.1.3/axi_interconnect_v1_7_16 +axi_master_burst_v2_0_7 = C:/Mentor/CompLib/2019.1.3/axi_master_burst_v2_0_7 +axi_msg_v1_0_5 = C:/Mentor/CompLib/2019.1.3/axi_msg_v1_0_5 +axi_mcdma_v1_0_5 = C:/Mentor/CompLib/2019.1.3/axi_mcdma_v1_0_5 +axi_mcdma_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axi_mcdma_v1_1_0 +axi_memory_init_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_memory_init_v1_0_0 +axi_mm2s_mapper_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axi_mm2s_mapper_v1_1_18 +axi_mmu_v2_1_17 = C:/Mentor/CompLib/2019.1.3/axi_mmu_v2_1_17 +axi_pcie_v2_9_1 = C:/Mentor/CompLib/2019.1.3/axi_pcie_v2_9_1 +axi_protocol_checker_v2_0_5 = C:/Mentor/CompLib/2019.1.3/axi_protocol_checker_v2_0_5 +axi_quad_spi_v3_2_18 = C:/Mentor/CompLib/2019.1.3/axi_quad_spi_v3_2_18 +axi_sideband_util_v1_0_3 = C:/Mentor/CompLib/2019.1.3/axi_sideband_util_v1_0_3 +axi_tft_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_tft_v2_0_22 +axi_timebase_wdt_v3_0_11 = C:/Mentor/CompLib/2019.1.3/axi_timebase_wdt_v3_0_11 +axi_timer_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_timer_v2_0_21 +axi_traffic_gen_v2_0_20 = C:/Mentor/CompLib/2019.1.3/axi_traffic_gen_v2_0_20 +axi_traffic_gen_v3_0_5 = C:/Mentor/CompLib/2019.1.3/axi_traffic_gen_v3_0_5 +axi_uart16550_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_uart16550_v2_0_21 +axi_uartlite_v2_0_23 = C:/Mentor/CompLib/2019.1.3/axi_uartlite_v2_0_23 +axi_usb2_device_v5_0_20 = C:/Mentor/CompLib/2019.1.3/axi_usb2_device_v5_0_20 +axi_utils_v2_0_6 = C:/Mentor/CompLib/2019.1.3/axi_utils_v2_0_6 +axi_vdma_v6_3_7 = C:/Mentor/CompLib/2019.1.3/axi_vdma_v6_3_7 +xbip_pipe_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_pipe_v3_0_6 +xbip_dsp48_addsub_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_addsub_v3_0_6 +xbip_addsub_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_addsub_v3_0_6 +c_reg_fd_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_reg_fd_v12_0_6 +c_addsub_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_addsub_v12_0_13 +axi_vfifo_ctrl_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_vfifo_ctrl_v2_0_21 +axi_vip_v1_1_5 = C:/Mentor/CompLib/2019.1.3/axi_vip_v1_1_5 +bs_switch_v1_0_0 = C:/Mentor/CompLib/2019.1.3/bs_switch_v1_0_0 +canfd_v2_0_1 = C:/Mentor/CompLib/2019.1.3/canfd_v2_0_1 +can_v5_0_22 = C:/Mentor/CompLib/2019.1.3/can_v5_0_22 +cic_compiler_v4_0_14 = C:/Mentor/CompLib/2019.1.3/cic_compiler_v4_0_14 +xbip_bram18k_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_bram18k_v3_0_6 +mult_gen_v12_0_15 = C:/Mentor/CompLib/2019.1.3/mult_gen_v12_0_15 +cmpy_v6_0_17 = C:/Mentor/CompLib/2019.1.3/cmpy_v6_0_17 +c_mux_bit_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_mux_bit_v12_0_6 +c_shift_ram_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_shift_ram_v12_0_13 +c_mux_bus_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_mux_bus_v12_0_6 +c_gate_bit_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_gate_bit_v12_0_6 +xbip_counter_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_counter_v3_0_6 +c_counter_binary_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_counter_binary_v12_0_13 +c_compare_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_compare_v12_0_6 +convolution_v9_0_14 = C:/Mentor/CompLib/2019.1.3/convolution_v9_0_14 +cordic_v6_0_15 = C:/Mentor/CompLib/2019.1.3/cordic_v6_0_15 +cpri_v8_10_3 = C:/Mentor/CompLib/2019.1.3/cpri_v8_10_3 +xbip_dsp48_acc_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_acc_v3_0_6 +xbip_accum_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_accum_v3_0_6 +c_accum_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_accum_v12_0_13 +xbip_dsp48_multadd_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_multadd_v3_0_6 +dds_compiler_v6_0_18 = C:/Mentor/CompLib/2019.1.3/dds_compiler_v6_0_18 +dft_v4_0_16 = C:/Mentor/CompLib/2019.1.3/dft_v4_0_16 +dft_v4_1_1 = C:/Mentor/CompLib/2019.1.3/dft_v4_1_1 +displayport_v7_0_11 = C:/Mentor/CompLib/2019.1.3/displayport_v7_0_11 +displayport_v8_1_1 = C:/Mentor/CompLib/2019.1.3/displayport_v8_1_1 +displayport_v9_0_1 = C:/Mentor/CompLib/2019.1.3/displayport_v9_0_1 +xbip_dsp48_mult_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_mult_v3_0_6 +floating_point_v7_0_16 = C:/Mentor/CompLib/2019.1.3/floating_point_v7_0_16 +div_gen_v5_1_15 = C:/Mentor/CompLib/2019.1.3/div_gen_v5_1_15 +dp_videoaxi4s_bridge_v1_0_0 = C:/Mentor/CompLib/2019.1.3/dp_videoaxi4s_bridge_v1_0_0 +dsp_macro_v1_0_0 = C:/Mentor/CompLib/2019.1.3/dsp_macro_v1_0_0 +fir_compiler_v5_2_6 = C:/Mentor/CompLib/2019.1.3/fir_compiler_v5_2_6 +duc_ddc_compiler_v3_0_15 = C:/Mentor/CompLib/2019.1.3/duc_ddc_compiler_v3_0_15 +ernic_v1_0_1 = C:/Mentor/CompLib/2019.1.3/ernic_v1_0_1 +etrnic_v1_0_3 = C:/Mentor/CompLib/2019.1.3/etrnic_v1_0_3 +etrnic_v1_1_2 = C:/Mentor/CompLib/2019.1.3/etrnic_v1_1_2 +fc32_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/fc32_rs_fec_v1_0_11 +fec_5g_common_v1_0_1 = C:/Mentor/CompLib/2019.1.3/fec_5g_common_v1_0_1 +fec_5g_common_v1_1_1 = C:/Mentor/CompLib/2019.1.3/fec_5g_common_v1_1_1 +fir_compiler_v7_2_12 = C:/Mentor/CompLib/2019.1.3/fir_compiler_v7_2_12 +flexo_100g_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/flexo_100g_rs_fec_v1_0_11 +floating_point_v7_1_8 = C:/Mentor/CompLib/2019.1.3/floating_point_v7_1_8 +g709_rs_encoder_v2_2_6 = C:/Mentor/CompLib/2019.1.3/g709_rs_encoder_v2_2_6 +rs_toolbox_v9_0_7 = C:/Mentor/CompLib/2019.1.3/rs_toolbox_v9_0_7 +g709_rs_decoder_v2_2_8 = C:/Mentor/CompLib/2019.1.3/g709_rs_decoder_v2_2_8 +g709_fec_v2_3_5 = C:/Mentor/CompLib/2019.1.3/g709_fec_v2_3_5 +g709_fec_v2_4_1 = C:/Mentor/CompLib/2019.1.3/g709_fec_v2_4_1 +g975_efec_i4_v1_0_17 = C:/Mentor/CompLib/2019.1.3/g975_efec_i4_v1_0_17 +g975_efec_i7_v2_0_18 = C:/Mentor/CompLib/2019.1.3/g975_efec_i7_v2_0_18 +ieee802d3_200g_rs_fec_v1_0_7 = C:/Mentor/CompLib/2019.1.3/ieee802d3_200g_rs_fec_v1_0_7 +ieee802d3_25g_rs_fec_v1_0_13 = C:/Mentor/CompLib/2019.1.3/ieee802d3_25g_rs_fec_v1_0_13 +ieee802d3_400g_rs_fec_v1_0_7 = C:/Mentor/CompLib/2019.1.3/ieee802d3_400g_rs_fec_v1_0_7 +ieee802d3_50g_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/ieee802d3_50g_rs_fec_v1_0_11 +ieee802d3_50g_rs_fec_v2_0_1 = C:/Mentor/CompLib/2019.1.3/ieee802d3_50g_rs_fec_v2_0_1 +ieee802d3_rs_fec_v1_0_15 = C:/Mentor/CompLib/2019.1.3/ieee802d3_rs_fec_v1_0_15 +ieee802d3_rs_fec_v2_0_5 = C:/Mentor/CompLib/2019.1.3/ieee802d3_rs_fec_v2_0_5 +ldpc_v2_0_3 = C:/Mentor/CompLib/2019.1.3/ldpc_v2_0_3 +lte_3gpp_channel_estimator_v2_0_16 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_channel_estimator_v2_0_16 +lte_3gpp_mimo_decoder_v3_0_15 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_mimo_decoder_v3_0_15 +lte_3gpp_mimo_encoder_v4_0_14 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_mimo_encoder_v4_0_14 +tcc_encoder_3gpplte_v4_0_15 = C:/Mentor/CompLib/2019.1.3/tcc_encoder_3gpplte_v4_0_15 +lte_dl_channel_encoder_v3_0_15 = C:/Mentor/CompLib/2019.1.3/lte_dl_channel_encoder_v3_0_15 +lte_dl_channel_encoder_v4_0_0 = C:/Mentor/CompLib/2019.1.3/lte_dl_channel_encoder_v4_0_0 +xfft_v7_2_9 = C:/Mentor/CompLib/2019.1.3/xfft_v7_2_9 +lte_fft_v2_0_18 = C:/Mentor/CompLib/2019.1.3/lte_fft_v2_0_18 +xfft_v9_1_2 = C:/Mentor/CompLib/2019.1.3/xfft_v9_1_2 +lte_fft_v2_1_0 = C:/Mentor/CompLib/2019.1.3/lte_fft_v2_1_0 +xbip_dsp48_multacc_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_multacc_v3_0_6 +lte_pucch_receiver_v2_0_16 = C:/Mentor/CompLib/2019.1.3/lte_pucch_receiver_v2_0_16 +xbip_multadd_v3_0_14 = C:/Mentor/CompLib/2019.1.3/xbip_multadd_v3_0_14 +lte_rach_detector_v3_1_5 = C:/Mentor/CompLib/2019.1.3/lte_rach_detector_v3_1_5 +lte_ul_channel_decoder_v4_0_16 = C:/Mentor/CompLib/2019.1.3/lte_ul_channel_decoder_v4_0_16 +mailbox_v2_1_11 = C:/Mentor/CompLib/2019.1.3/mailbox_v2_1_11 +mdm_v3_2_16 = C:/Mentor/CompLib/2019.1.3/mdm_v3_2_16 +iomodule_v3_0 = C:/Mentor/CompLib/2019.1.3/iomodule_v3_0 +lmb_bram_if_cntlr_v4_0 = C:/Mentor/CompLib/2019.1.3/lmb_bram_if_cntlr_v4_0 +lmb_v10_v3_0 = C:/Mentor/CompLib/2019.1.3/lmb_v10_v3_0 +axi_lite_ipif_v3_0 = C:/Mentor/CompLib/2019.1.3/axi_lite_ipif_v3_0 +mdm_v3_2 = C:/Mentor/CompLib/2019.1.3/mdm_v3_2 +microblaze_mcs_v2_3_6 = C:/Mentor/CompLib/2019.1.3/microblaze_mcs_v2_3_6 +noc_mc_ddr4_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_mc_ddr4_phy_v1_0_0 +perf_axi_tg_v1_0_8 = C:/Mentor/CompLib/2019.1.3/perf_axi_tg_v1_0_8 +polar_v1_0_3 = C:/Mentor/CompLib/2019.1.3/polar_v1_0_3 +prc_v1_3_2 = C:/Mentor/CompLib/2019.1.3/prc_v1_3_2 +processing_system7_vip_v1_0_7 = C:/Mentor/CompLib/2019.1.3/processing_system7_vip_v1_0_7 +proc_sys_reset_v5_0_13 = C:/Mentor/CompLib/2019.1.3/proc_sys_reset_v5_0_13 +pr_axi_shutdown_manager_v1_0_1 = C:/Mentor/CompLib/2019.1.3/pr_axi_shutdown_manager_v1_0_1 +pr_bitstream_monitor_v1_0_1 = C:/Mentor/CompLib/2019.1.3/pr_bitstream_monitor_v1_0_1 +pr_decoupler_v1_0_7 = C:/Mentor/CompLib/2019.1.3/pr_decoupler_v1_0_7 +quadsgmii_v3_4_6 = C:/Mentor/CompLib/2019.1.3/quadsgmii_v3_4_6 +rs_decoder_v9_0_16 = C:/Mentor/CompLib/2019.1.3/rs_decoder_v9_0_16 +rs_encoder_v9_0_15 = C:/Mentor/CompLib/2019.1.3/rs_encoder_v9_0_15 +rxaui_v4_4_6 = C:/Mentor/CompLib/2019.1.3/rxaui_v4_4_6 +sd_fec_v1_1_3 = C:/Mentor/CompLib/2019.1.3/sd_fec_v1_1_3 +sid_v8_0_14 = C:/Mentor/CompLib/2019.1.3/sid_v8_0_14 +soft_ecc_proxy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/soft_ecc_proxy_v1_0_0 +spdif_v2_0_21 = C:/Mentor/CompLib/2019.1.3/spdif_v2_0_21 +srio_gen2_v4_1_6 = C:/Mentor/CompLib/2019.1.3/srio_gen2_v4_1_6 +switch_core_top_v1_0_7 = C:/Mentor/CompLib/2019.1.3/switch_core_top_v1_0_7 +sync_ip = C:/Mentor/CompLib/2019.1.3/sync_ip +tcc_decoder_3gppmm_v2_0_18 = C:/Mentor/CompLib/2019.1.3/tcc_decoder_3gppmm_v2_0_18 +tcc_encoder_3gpp_v5_0_15 = C:/Mentor/CompLib/2019.1.3/tcc_encoder_3gpp_v5_0_15 +tmr_comparator_v1_0_2 = C:/Mentor/CompLib/2019.1.3/tmr_comparator_v1_0_2 +tmr_sem_v1_0_9 = C:/Mentor/CompLib/2019.1.3/tmr_sem_v1_0_9 +tri_mode_ethernet_mac_v9_0_14 = C:/Mentor/CompLib/2019.1.3/tri_mode_ethernet_mac_v9_0_14 +tsn_temac_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tsn_temac_v1_0_4 +videoaxi4s_bridge_v1_0_5 = C:/Mentor/CompLib/2019.1.3/videoaxi4s_bridge_v1_0_5 +viterbi_v9_1_11 = C:/Mentor/CompLib/2019.1.3/viterbi_v9_1_11 +v_ccm_v6_0_15 = C:/Mentor/CompLib/2019.1.3/v_ccm_v6_0_15 +v_cfa_v7_0_14 = C:/Mentor/CompLib/2019.1.3/v_cfa_v7_0_14 +v_cresample_v4_0_14 = C:/Mentor/CompLib/2019.1.3/v_cresample_v4_0_14 +v_dual_splitter_v1_0_9 = C:/Mentor/CompLib/2019.1.3/v_dual_splitter_v1_0_9 +v_enhance_v8_0_15 = C:/Mentor/CompLib/2019.1.3/v_enhance_v8_0_15 +v_gamma_v7_0_15 = C:/Mentor/CompLib/2019.1.3/v_gamma_v7_0_15 +v_osd_v6_0_16 = C:/Mentor/CompLib/2019.1.3/v_osd_v6_0_16 +v_rgb2ycrcb_v7_1_13 = C:/Mentor/CompLib/2019.1.3/v_rgb2ycrcb_v7_1_13 +v_vid_sdi_tx_bridge_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_vid_sdi_tx_bridge_v2_0_0 +v_ycrcb2rgb_v7_1_13 = C:/Mentor/CompLib/2019.1.3/v_ycrcb2rgb_v7_1_13 +xbip_dsp48_macro_v3_0_17 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_macro_v3_0_17 +xfft_v9_0_17 = C:/Mentor/CompLib/2019.1.3/xfft_v9_0_17 +xsdbs_v1_0_2 = C:/Mentor/CompLib/2019.1.3/xsdbs_v1_0_2 +zynq_ultra_ps_e_vip_v1_0_5 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_vip_v1_0_5 +[DefineOptionset] +; Define optionset entries for the various compilers, vmake, and vsim. +; These option sets can be used with the "-optionset " syntax. +; i.e. +; vlog -optionset COMPILEDEBUG top.sv +; vsim -optionset UVMDEBUG my_top +; +; Following are some useful examples. + +; define a vsim optionset for uvm debugging +UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop + +; define a vopt optionset for debugging +VOPTDEBUG = +acc -debugdb + +[encryption] +; For vencrypt and vhencrypt. + +; Controls whether to encrypt whole files by ignoring all protect directives +; (except "viewport" and "interface_viewport") that are present in the input. +; The default is 0, use embedded protect directives to control the encryption. +; Set this to 1 to encrypt whole files by ignoring embedded protect directives. +; wholefile = 0 + +; Sets the data_method to use for the symmetric session key. +; The session key is a symmetric key that is randomly generated for each +; protected region (envelope) and is the heart of all encryption. This is used +; to set the length of the session key to generate and use when encrypting the +; HDL text. Supported values are aes128, aes192, and aes256. +; data_method = aes128 + +; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption +; "recipe" comprising an optional common block, at least one tool block (which +; contains the key public key), and the text to be encrypted. The common block +; and any of the tool blocks may contain rights in the form of the "control" +; directive. The text to be encrypted is specified either by setting +; "wholefile" to 1 or by embedding protect "begin" and "end" directives in +; the input HDL files. + +; Common recipe specification file. This file is optional. Its presence will +; require at least one "toolblock" to be specified. +; Directives such as "author" "author_info" and "data_method", +; as well as the common block license specification, go in this file. +; common = + +; Tool block specification recipe(s). Public key file with optional tool block +; file name. May be multiply-defined; at least one tool block is required if +; a recipe is being specified. +; Key file is a file name with no extension (.deprecated or .active will be +; supplied by the encryption tool). +; Rights file name is optional. +; toolblock = [,]{:[,]} + +; Location of directory containing recipe files. +; The default location is in the product installation directory. +; keyring = $MODEL_TECH/../keyring + +; Enable encryption statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [cmd,msg]. +Stats = cmd,msg + +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +; Value of 4 or ams99 for VHDL-AMS-1999 +; Value of 5 or ams07 for VHDL-AMS-2007 +VHDL93 = 2002 + +; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. +; ignoreStandardRealVector = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Set the prefix to be honored for synthesis/coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverSub = 0 + +; Automatically exclude VHDL case statement OTHERS choice branches. +; This includes OTHERS choices in selected signal assigment statements. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Turn on or off clkOpt optimization for code coverage. Default is on. +; CoverClkOpt = 1 + +; Turn on or off clkOpt optimization builtins for code coverage. Default is on. +; CoverClkOptBuiltins = 0 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Set this to cause the compilers to force data to be committed to disk +; when the files are closed. +; SyncCompilerFiles = 1 + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; Controls whether or not to show immediate assertions with constant expressions +; in GUI/report/UCDB etc. By default, immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls how VHDL basic identifiers are stored with the design unit. +; Does not make the language case-sensitive, affects only how declarations +; declared with basic identifiers have their names stored and printed +; (in the GUI, examine, etc.). +; Default is to preserve the case as originally depicted in the VHDL source. +; Value of 0 indicates to change all basic identifiers to lower case. +; PreserveCase = 0 + +; For Configuration Declarations, controls the effect that USE clauses have +; on visibility inside the configuration items being configured. If 1 +; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, +; extend the visibility of objects made visible through USE clauses into nested +; component configurations. +; OldVHDLConfigurationVisibility = 0 + +; Allows VHDL configuration declarations to be in a different library from +; the corresponding configured entity. Default is to not allow this for +; stricter LRM-compliance. +; SeparateConfigLibrary = 1; + +; Determine how mode OUT subprogram parameters of type array and record are treated. +; If 0 (the default), then only VHDL 2008 will do this initialization. +; If 1, always initialize the mode OUT parameter to its default value. +; If 2, do not initialize the mode OUT out parameter. +; Note that prior to release 10.1, all language versions did not initialize mode +; OUT array and record type parameters, unless overridden here via this mechanism. +; In release 10.1 and later, only files compiled with VHDL 2008 will cause this +; initialization, unless overridden here. +; InitOutCompositeParam = 0 + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Describe compilation options according to matching file patterns. +; File pattern * matches all printing characters other than '/'. +; File pattern **/x matches all paths containing file/directory x. +; File pattern x/** matches all paths beginning at directory x. +; FileOptMap = (**/*.vhd => -2008); + +; Describe library targets of compilation according to matching file patterns. +; LibMap = (**/*.vhd => work); + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with total size in bytes equal to or more than the sparse memory +; threshold gets marked as sparse automatically, unless specified otherwise +; in source code or by the +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with total size equal +; to or greater than 1Mb are marked as sparse) +; SparseMemThreshold = 1048576 + +; Set the prefix to be honored for synthesis and coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Turn on code coverage in VLOG `celldefine modules, modules containing +; specify blocks, and modules included using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 0 to 5, with the following +; meanings (the default is 3): +; 5 -- All allowable optimizations are on. +; 4 -- Turn off removing unreferenced code. +; 3 -- Turn off process, always block and if statement merging. +; 2 -- Turn off expression optimization, converting primitives +; to continuous assignments, VHDL subprogram inlining. +; and VHDL clkOpt (converting FF's to builtins). +; 1 -- Turn off continuous assignment optimizations and clock suppression. +; 0 -- Turn off Verilog module inlining and VHDL arch inlining. +; HOWEVER, if fsm coverage is turned on, optimizations will be forced to +; level 3, with also turning off converting primitives to continuous assigns. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => _ +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = [ ...] +LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SvFileSuffixes = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2005 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "mti_design_element_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls if untyped parameters that are initialized with values greater +; than 2147483647 are mapped to generics of type INTEGER or ignored. +; If mapped to VHDL Integers, values greater than 2147483647 +; are mapped to negative values. +; Default is to map these parameter to generic of type INTEGER +; ForceUnsignedToVHDLInteger = 1 + +; Enable AMS wreal (wired real) extensions. Default is 0. +; WrealType = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-][,[+|-]*] + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Controls how $unit library entries are named. Valid options are: +; "file" (generate name based on the first file on the command line) +; "du" (generate name based on first design unit following an item +; found in $unit scope) +; CUAutoName = file + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; CppInstall = 7.4.0 + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. +; Sc22Mode = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Enable use of UVMC library. Default is off. +; UseUvmc = 1 + +[vopt] +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; enable or disable param saving in UCDB. +; CoverageSaveParam = 0 + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Controls set of CoverConstructs that are being considered for Coverage +; Collection. +; Some of Valid options are: default,set1,set2 +; Covermode = default + +; Controls set of HDL cover constructs that would be considered(or not considered) +; for Coverage Collection. (Default corresponds to covermode default). +; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". +; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Set the number of processes created during the code generation phase. +; By default a heuristic is used to set this value. This may be set to 0 +; to disable this feature completely. +; ParallelJobs = 0 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-][,[+|-]*] + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Disable SystemVerilog elaboration system task messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = fs + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 10000000 + +; Specify libraries to be searched for precompiled modules +; LibrarySearchPath = [ ...] + +; Set XPROP assertion fail limit. Default is 5. +; Any positive integer, -1 for infinity. +; XpropAssertionLimit = 5 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Control SVA and VHDL immediate assertion directives during simulation +; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts +; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts +; SimulateImmedAsserts = 1 + +; License feature mappings for Verilog and VHDL +; qhsimvh Single language VHDL license +; qhsimvl Single language Verilog license +; msimhdlsim Language neutral license for either Verilog or VHDL +; msimhdlmix Second language only, language neutral license for either +; Verilog or VHDL +; +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately checkout and hold a VHDL license (i.e., one of +; qhsimvh, msimhdlsim, or msimhdlmix) +; vlog Immediately checkout and hold a Verilog license (i.e., one of +; qhsimvl, msimhdlsim, or msimhdlmix) +; plus Immediately checkout and hold a VHDL license and a Verilog license +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer license feature (PE ONLY) +; noslvhdl Disable checkout of qhsimvh license feature +; noslvlog Disable checkout of qhsimvl license feature +; nomix Disable checkout of msimhdlmix license feature +; nolnl Disable checkout of msimhdlsim license feature +; mixedonly Disable checkout of qhsimvh and qhsimvl license features +; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features +; +; Examples (remove ";" comment character to activate licensing directives): +; Single directive: +; License = plus +; Multi-directive (Note: space delimited directives): +; License = noqueue plus + +; Severity level of a VHDL assertion message or of a SystemVerilog severity system task +; which will cause a running simulation to stop. +; VHDL assertions and SystemVerilog severity system task that occur with the +; given severity or higher will cause a running simulation to stop. +; This value is ignored during elaboration. +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Severity level of a tool message which will cause a running simulation to +; stop. This value is ignored during elaboration. Default is to not break. +; 0 = Note 1 = Warning 2 = Error 3 = Fatal +;BreakOnMessage = 2 + +; The class debug feature enables more visibility and tracking of class instances +; during simulation. By default this feature is disabled (0). To enable this +; feature set ClassDebug to 1. +; ClassDebug = 1 + +; Message Format conversion specifications: +; %S - Severity Level of message/assertion +; %R - Text of message +; %T - Time of message +; %D - Delta value (iteration number) of Time +; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected +; %i - Instance/Region/Signal pathname with Process name (if available) +; %I - shorthand for one of these: +; " %K: %i" +; " %K: %i File: %F" (when path is not Process or Signal) +; except that the %i in this case does not report the Process name +; %O - Process name +; %P - Instance/Region path without leaf process +; %F - File name +; %L - Line number; if assertion message, then line number of assertion or, if +; assertion is in a subprogram, line from which the call is made +; %u - Design unit name in form library.primary +; %U - Design unit name in form library.primary(secondary) +; %% - The '%' character itself +; +; If specific format for Severity Level is defined, use that format. +; Else, for a message that occurs during elaboration: +; -- Failure/Fatal message in VHDL region that is not a Process, and in +; certain non-VHDL regions, uses MessageFormatBreakLine; +; -- Failure/Fatal message otherwise uses MessageFormatBreak; +; -- Note/Warning/Error message uses MessageFormat. +; Else, for a message that occurs during runtime and triggers a breakpoint because +; of the BreakOnAssertion setting: +; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; +; -- otherwise uses MessageFormatBreak. +; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. +; +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops because of a breakpoint or fatal error. +; Example with function name: # Break in Process ctr at counter.vhd line 44 +; Example without function name: # Break at counter.vhd line 44 +; Default value is 1. +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned +; Flags may be one of: enumnumeric, showbase, wreal +DefaultRadix = hexadecimal +DefaultRadixFlags = showbase +; Set to 1 for make the signal_force VHDL and Verilog functions use the +; default radix when processing the force value. Prior to 10.2 signal_force +; used the default radix, now it always uses symbolic unless value explicitly indicates base +;SignalForceFunctionUseDefaultRadix = 0 + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. +; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. +; BatchMode = 1 + +; File for saving command transcript when -batch option used +; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero +; default is unset so command transcript only goes to stdout for better performance +; BatchTranscriptFile = transcript + +; File for saving command transcript, this option is ignored when -batch option is used +TranscriptFile = transcript + +; Transcript file long line wrapping mode(s) +; mode == 0 :: no wrapping, line recorded as is +; mode == 1 :: wrap at first whitespace after WSColumn +; or at Column. +; mode == 2 :: wrap as above, but add continuation +; character ('\') at end of each wrapped line +; +; WrapMode = 0 +; WrapColumn = 30000 +; WrapWSColumn = 27000 + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable SystemVerilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; Control the iteration of events when a VHDL signal is forced to a value +; This flag can be set to honour the signal update event in next iteration, +; the default is to update and propagate in the same iteration. +; ForceSigNextIter = 1 + +; Enable simulation statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; If nonzero, close files as soon as there is either an explicit call to +; file_close, or when the file variable's scope is closed. When zero, a +; file opened in append mode is not closed in case it is immediately +; reopened in append mode; otherwise, the file will be closed at the +; point it is reopened. +; AppendClose = 1 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from accelerated versions of the std_logic_arith, +; std_logic_unsigned, and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from accelerated versions of the IEEE numeric_std +; and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names +; in the design hierarchy. +; This style is controlled by the value of the GenerateFormat +; value described next. Default is to use new-style names, which +; comprise the generate statement label, '(', the value of the generate +; parameter, and a closing ')'. +; Set this to 1 to use old-style names. +; OldVhdlForGenNames = 1 + +; Control the format of the old-style VHDL FOR generate statement region +; name for each iteration. Do not quote the value. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate statement label; the %d represents the generate parameter value +; at a particular iteration (this is the position number if the generate parameter +; is of an enumeration type). Embedded whitespace is allowed (but discouraged); +; leading and trailing whitespace is ignored. +; Application of the format must result in a unique region name over all +; loop iterations for a particular immediately enclosing scope so that name +; lookup can function properly. The default is %s__%d. +; GenerateFormat = %s__%d + +; Enable more efficient logging of VHDL Variables. +; Logging VHDL variables without this enabled, while possible, is very +; inefficient. Enabling this will provide a more efficient logging methodology +; at the expense of more memory usage. By default this feature is disabled (0). +; To enabled this feature, set this variable to 1. +; VhdlVariableLogging = 1 + +; Enable logging of VHDL access type variables and their designated objects. +; This setting will allow both variables of an access type ("access variables") +; and their designated objects ("access objects") to be logged. Logging a +; variable of an access type will automatically also cause the designated +; object(s) of that variable to be logged as the simulation progresses. +; Further, enabling this allows access objects to be logged by name. By default +; this feature is disabled (0). To enable this feature, set this variable to 1. +; Enabling this will automatically enable the VhdlVariableLogging feature also. +; AccessObjDebug = 1 + +; Make each VHDL package in a PDU has its own separate copy of the package instead +; of sharing the package between PDUs. The default is to share packages. +; To ensure that each PDU has its own set of packages, set this variable to 1. +; VhdlSeparatePduPackage = 1 + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. +; Use custom gcc compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; DpiCppPath = /bin/gcc +; +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; DpiCppInstall = 7.4.0 + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify whether the Verilog system task $fopen or vpi_mcd_open() +; will create directories that do not exist when opening the file +; in "a" or "w" mode. +; The default is 0 (do not create non-existent directories) +; CreateDirForFileAccess = 1 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + + +; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. +; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. +; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". +; The list of options must be delimited by commas, without spaces or tabs. +; +; Some examples +; To turn on all available UVM-aware debug features: +; UVMControl = all +; To turn on the struct window, mesage logging, and transaction logging: +; UVMControl = struct,msglog,trlog +; To turn on all options except certe: +; UVMControl = all,-certe +; To completely disable all UVM-aware debug functionality: +; UVMControl = disable + +; Specify the WildcardFilter setting. +; A space separated list of object types to be excluded when performing +; wildcard matches with log, wave, etc commands. The default value for this variable is: +; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" +; See "Using the WildcardFilter Preference Variable" in the documentation for +; details on how to use this variable and for descriptions of the filter types. +WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile + +; Specify the WildcardSizeThreshold setting. +; This integer setting specifies the size at which objects will be excluded when +; performing wildcard matches with log, wave, etc commands. Objects of size equal +; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard +; matches. The size is a simple calculation of number of bits or items in the object. +; The default value is 8k (8192). Setting this value to 0 will disable the checking +; of object size against this threshold and allow all objects of any size to be logged. +WildcardSizeThreshold = 8192 + +; Specify whether warning messages are output when objects are filtered out due to the +; WildcardSizeThreshold. The default is 0 (no messages generated). +WildcardSizeThresholdVerbose = 0 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify whether to lock the WLF file. +; Locking the file prevents other invocations of ModelSim/Questa tools from +; inadvertently overwriting the WLF file. +; The default is 1, lock the WLF file. +; WLFFileLock = 0 + +; Specify the update interval for the WLF file in live simulation. +; The interval is given in seconds. +; The value is the smallest interval between WLF file updates. The WLF file +; will be flushed (updated) after (at least) the interval has elapsed, ensuring +; that the data is correct when viewed from a separate viewer. +; A value of 0 means that no updating will occur. +; The default value is 10 seconds. +; WLFUpdateInterval = 10 + +; Specify the WLF cache size limit for WLF files. +; The value is given in megabytes. A value of 0 turns off the cache. +; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). +; On Windows, the default value is 1000 (megabytes) to help to avoid filling +; process memory. +; WLFSimCacheSize allows a different cache size to be set for a live simulation +; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize +; is not set, it defaults to the WLFCacheSize value. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines. +; If 0, no threads will be used; if 1, threads will be used if the system has +; more than one processor. +; WLFUseThreads = 1 + +; Specify the size of objects that will trigger "large object" messages +; at log/wave/list time. The size calculation of the object is the same as that +; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. +; Setting LargeObjectSize to 0 will disable these messages. +; LargeObjectSize = 500000 + +; Specify the depth of stack frames returned by $stacktrace([level]). +; This depth will be picked up when the optional 'level' argument +; is not specified or its value is not a positive integer. +; StackTraceDepth = 100 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; For SystemC-2.3.2 the valid values are 0,1 and 2 +; 0 = SC_SIGNAL_WRITE_CHECK_DISABLE_ +; 1 = SC_SIGNAL_WRITE_CHECK_DEFAULT_ +; 2 = SC_SIGNAL_WRITE_CHECK_CONFLICT_ +; For SystemC-2.2 the valid values are 0 and 1 +; 0 = DISABLE +; 1 = ENABLE +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Set SystemC thread stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). The stack size for sc_thread depends +; on the amount of data on the sc_thread stack and the memory required +; to succesfully execute the thread. +; ScStackSize = 1 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Enable calling of the DPI export taks/functions from the +; SystemC start_of_simulation() callback. +; The default is off. +; EnableDpiSosCb = 1 + + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: This variable can be overridden with the vsim "-onfinish" command line switch. +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result. Default is 0. +; 0 == do not print simstats +; 1 == print at end of simulation +; 2 == print at end of each run command and end of simulation +; PrintSimStats = 1 + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Enable assertion counts. Default is off. +; AssertionCounts = 1 + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. +; AssertionEnable = 0 + +; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionLimit = 1 + +; Turn on/off concurrent assertion pass log. Default is off. +; Assertion pass logging is only enabled when assertion is browseable +; and assertion debug is enabled. +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + +; Assertion thread limit after which assertion would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for an assertion go +; beyond this limit, the assertion would be either switched off or killed. This +; limit applies to only assert directives. +;AssertionThreadLimit = -1 + +; Action to be taken once the assertion thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only assert directives. +;AssertionThreadLimitAction = kill + +; Cover thread limit after which cover would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for a cover go +; beyond this limit, the cover would be either switched off or killed. This +; limit applies to only cover directives. +;CoverThreadLimit = -1 + +; Action to be taken once the cover thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only cover directives. +;CoverThreadLimitAction = kill + + +; By default immediate assertions do not participate in Assertion Coverage calculations +; unless they are executed. This switch causes all immediate assertions in the design +; to participate in Assertion Coverage calculations, whether attempted or not. +; UnattemptedImmediateAssertions = 0 + +; By default immediate covers participate in Coverage calculations +; whether they are attempted or not. This switch causes all unattempted +; immediate covers in the design to stop participating in Coverage +; calculations. +; UnattemptedImmediateCovers = 0 + +; By default pass action block is not executed for assertions on vacuous +; success. The following variable is provided to enable execution of +; pass action block on vacuous success. The following variable is only effective +; if the user does not disable pass action block execution by using either +; system tasks or CLI. Also there is a performance penalty for enabling +; the following variable. +;AssertionEnableVacuousPassActionBlock = 1 + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; This option applies to condition and expression coverage UDP tables. It +; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. +; If this option is used and a match occurs in more than one row in the UDP table, +; none of the counts for all matching rows is incremented. By default, counts are +; incremented for all matching rows. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays +; and VHDL arrays-of-arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, +; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. +; This leads to a longer simulation time with bigger arrays covered with toggle coverage. +; Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized +; one-dimensional packed vectors for toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for +; toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Turn off automatic inclusion of VHDL records in toggle coverage. +; Default is to include them. +; ToggleVHDLRecords = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. +; Following is the toggle coverage calculation criteria based on extended toggle mode: +; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). +; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. +; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. +; ExtendedToggleMode = 3 + +; Enable toggle statistics collection only for ports. Default is 0. +; TogglePortsOnly = 1 + +; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; FecCountLimit = 1 + +; Limit the counts that are tracked for UDP Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; UdpCountLimit = 1 + +; Control toggle coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either +; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; ToggleDeglitchPeriod = 10.0ps + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this +; setting. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the threshold of Coverpoint wildcard bin value range size, above which +; a warning will be triggered. The default is 4K -- 12 wildcard bits. +; SVCoverpointWildCardBinValueSizeWarn = 4096 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SVCovergroup63Compatibility = 0 + +; Enforce the default behavior of covergroup get_coverage() builtin function, GUI +; and report. This variable sets the default value of type_option.merge_instances. +; There are two vsim command line options, -cvgmergeinstances and +; -nocvgmergeinstances to override this setting from vsim command line. +; The default value of this variable, -1 (don't care), allows the tool to determine +; the effective value, based on factors related to capacity and optimization. +; The type_option.merge_instances appears in the GUI and coverage reports as either +; auto(1) or auto(0), depending on whether the effective value was determined to +; be a 1 or a 0. +; SVCovergroupMergeInstancesDefault = -1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins +; MaxSVCoverpointBinsInst = 1048576 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins +; MaxSVCrossBinsInst = 67108864 + +; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. +; By default, this variable is set 0, in which case option.no_collect setting will take effect. +; If this variable is set to 1, all zero-weight coverage items will not be saved. +; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting +; of this variable. +; CvgZWNoCollect = 1 + +; Specify a space delimited list of double quoted TCL style +; regular expressions which will be matched against the text of all messages. +; If any regular expression is found to be contained within any message, the +; status for that message will not be propagated to the UCDB TESTSTATUS. +; If no match is detected, then the status will be propagated to the +; UCDB TESTSTATUS. More than one such regular expression text is allowed, +; and each message text is compared for each regular expression in the list. +; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Generate the stub definitions for the undefined symbols in the shared libraries being +; loaded in the simulation. When this flow is turned on, the undefined symbols will not +; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. +; The valid arguments are: on, off, verbose. +; on : turn on the automatic generation of stub definitions. +; off: turn off the flow. The undefined symbols will trigger an immediate load failure. +; verbose: Turn on the flow and report the undefined symbols for each shared library. +; NOTE: This variable can be overriden with vsim switch "-undefsyms". +; The default is on. +; +; UndefSyms = off + +; Enable the support for checkpointing foreign C/C++ libraries. +; The valid arguments are: 0, 1, 2 +; 0: off (default) +; 1: on (manually save/restore user shared library data) +; 2: auto (automatically save/restore user shared library data) +; This option is not supported on the Windows platforms. +; +; AllowCheckpointCpp = 2 + +; Initial seed for the random number generator of the root thread (SystemVerilog). +; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. +; The default value is 0. +; Sv_Seed = 0 + +; Specify the solver "engine" that vsim will select for constrained random +; generation. +; Valid values are: +; "auto" - automatically select the best engine for the current +; constraint scenario +; "bdd" - evaluate all constraint scenarios using the BDD solver engine +; "act" - evaluate all constraint scenarios using the ACT solver engine +; While the BDD solver engine is generally efficient with constraint scenarios +; involving bitwise logical relationships, the ACT solver engine can exhibit +; superior performance with constraint scenarios involving large numbers of +; random variables related via arithmetic operators (+, *, etc). +; NOTE: This variable can be overridden with the vsim "-solveengine" command +; line switch. +; The default value is "auto". +; SolveEngine = auto + +; Specifies the maximum size that a dynamic array may be resized to by the +; solver. If the solver attempts to resize a dynamic array to a size greater +; than the specified limit, the solver will abort with an error. +; The default value is 10000. A value of 0 indicates no limit. +; SolveArrayResizeMax = 10000 + +; Specify error message severity when randomize() and randomize(null) failures +; are detected. +; +; Integer value up to two digits are allowed with each digit having the following legal values: +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; +; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents +; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit) +; represents the setting for randomize(null) calls. +; +; 2) When a single digit value is used, the setting is applied to both normal randomize() call +; and randomize(null) call. +; +; Example: Fatal error for randomize() failures and NO error for randomize(null) failures +; -solvefailseverity=40 +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefailseverity" command +; line switch. +; +; The default is 1 (warning). +; SolveFailSeverity = 1 + +; Error message severity for suppressible errors that are detected in a +; solve/before constraint. +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" +; command line switch. +; The default is 3 (failure). +; SolveBeforeErrorSeverity = 3 + +; Error message severity for suppressible errors that are related to +; solve engine capacity limits +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" +; command line switch. +; The default is 3 (failure). +; SolveEngineErrorSeverity = 3 + +; Enable/disable constraint conflicts on randomize() failure +; Valid values: +; 0 - disable solvefaildebug +; 1 - basic debug (no performance penalty) +; 2 - enhanced debug (runtime performance penalty) +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command +; line switch. +; +; The default is 1 (basic debug). +; SolveFailDebug = 1 + +; Upon encountering a randomize() failure, generate a simplified testcase that +; will reproduce the failure. Optionally output the testcase to a file. +; Testcases for 'no-solution' failures will only be produced if SolveFailDebug +; is enabled (see above). +; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" +; command line switch. +; The default is OFF (do not generate a testcase). To enable testcase +; generation, uncomment this variable. To redirect testcase generation to a +; file, specify the name of the output file. +; SolveFailTestcase = + +; Specify solver timeout threshold (in seconds). randomize() will fail if the +; CPU time required to evaluate any randset exceeds the specified timeout. +; The default value is 500. A value of 0 will disable timeout failures. +; SolveTimeout = 500 + +; Specify the alternative behavior during solver replay. Must be used when combined with -solvereplay switch. +; SolveReplayOpt=[+|-][,[+|-]]*" +' Valid settings: +; validate : toggle the checking of value changes of non-random variables involved in randomize(). (default is off)" +; SolveReplayOpt=validate + +; Specify the maximum size of the solution graph generated by the BDD solver. +; This value can be used to force the BDD solver to abort the evaluation of a +; complex constraint scenario that cannot be evaluated with finite memory. +; This value is specified in 1000s of nodes. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Specify the maximum number of evaluations that may be performed on the +; solution graph by the BDD solver. This value can be used to force the BDD +; solver to abort the evaluation of a complex constraint scenario that cannot +; be evaluated in finite time. This value is specified in 10000s of evaluations. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxEval = 10000 + +; Specify random sequence compatiblity with a prior release. This +; option is used to get the same random sequences during simulation as +; as a prior release. Only prior releases with the same major version +; as the current release are allowed. +; NOTE: Only those random sequence changes due to solver optimizations are +; reverted by this variable. Random sequence changes due to solver bugfixes +; cannot be un-done. +; NOTE: This variable can be overridden with the vsim "-solverev" command +; line switch. +; Default value set to "" (no compatibility). +; SolveRev = + +; Environment variable expansion of command line arguments has been depricated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Specify the memory threshold for the System Verilog garbage collector. +; The value is the number of megabytes of class objects that must accumulate +; before the garbage collector is run. +; The GCThreshold setting is used when class debug mode is disabled to allow +; less frequent garbage collection and better simulation performance. +; The GCThresholdClassDebug setting is used when class debug mode is enabled +; to allow for more frequent garbage collection. +; GCThreshold = 100 +; GCThresholdClassDebug = 5 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +; Location of Multi-Level Verification Component (MVC) installation. +; The default location is the product installation directory. +MvcHome = $QUESTA_MVC_HOME + +; Location of InFact installation. The default is $MODEL_TECH/../../infact +; +; InFactHome = $MODEL_TECH/../../infact + +; Initialize SystemVerilog enums using the base type's default value +; instead of the leftmost value. +; EnumBaseInit = 1 + +; Suppress file type registration. +; SuppressFileTypeReg = 1 + +; Enable/disable non-LRM compliant SystemVerilog language extensions. +; Valid extensions are: +; altdpiheader - Alternative style function signature generated in DPI header", +; cfce - generate an error if $cast fails as a function +; cfmt - C like formatting for specifiers with '#' prefix ('%#x', '%#h') +; dfsp - sets default format specifier as %p, if no format specifier is given for unpacked array in $display and related systasks +; expdfmt - enable format string extensions for $display/$sformatf +; extscan - support values greater than 32 bit for string builtin methods (atohex, atobin, atooct, atoi) +; fmtcap - prints capital hex digits with %X/%H in display calls +; iddp - ignore DPI disable protocol check +; lfmt - zero-pad data if '0' prefixes width in format specifier (e.g. "%04h") +; noexptc - ignore DPI export type name overloading check +; realrand - support randomize() with real variables and constraints (Default) +; SvExtensions = [+|-][,[+|-]*] + +; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions. +; Valid extensions are: +; arraymode - consider rand_mode of unpacked array field independently from its elements +; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles (Default) +; funcback - enable function backtracking (ACT only) +; genmodseedfix - enable LRM-compliant seeding of module/interface instances under for-generate blocks (Default) +; nodist - interpret 'dist' constraint as 'inside' (ACT only) +; noorder - ignore solve/before ordering constraints (ACT only) +; pathseed - enable unique seeding of module instances based on hierarchical path name +; prerandfirst - execute all pre_randomize() functions before evaluating any constraints +; promotedist - promote priority of 'dist' constraint if LHS has no solve/before +; purecheck - suppress pre_randomize() and post_randomize() calls for randomize(null) +; randindex - allow random index in constraint (Default) +; randstruct - consider all fields of unpacked structs as 'rand' +; skew - skew randomize results (ACT only) +; strictstab - strict random stability +; SvRandExtensions = [+|-][,[+|-]*] + +; Controls the formatting of '%p' and '%P' conversion specification, used in $display +; and similar system tasks. +; 1. SVPrettyPrintFlags=I use spaces(S) or tabs(T) per indentation level. +; The 'I' flag when present causes relevant data types to be expanded and indented into +; a more readable format. +; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). +; 2. SVPrettyPrintFlags=L limits the output to lines. +; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). +; 3. SVPrettyPrintFlags=C limits the output to characters. +; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). +; 4. SVPrettyPrintFlags=F limits the output to of relevant datatypes +; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). +; 5. SVPrettyPrintFlags=E limits the output to of relevant datatypes +; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). +; 6. SVPrettyPrintFlags=D suppresses the output of sub-elements below . +; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). +; 7. SVPrettyPrintFlags=R shows the output of specifier %p as per the specifed radix. +; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)). +; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format. +; 8. Items 1-7 above can be combined as a comma separated list. +; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb) +; SVPrettyPrintFlags=I4S + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = /lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = /lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = /lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = /lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = /lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; suppress can be used to achieve +nowarn functionality +; The format is: suppress = ,,[,,...] +; Examples: +suppress = 8780 ;an explanation can be had by running: verror 8780 +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3601 +; suppress = 3009,CNNODP,3601,TFMPC +; suppress = 8683,8684 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of Verilog display system task messages and +; PLI/FLI print function call messages. The system tasks include +; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They +; also include the analogous file I/O tasks that write to STDOUT +; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, +; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default +; is to have messages appear only in the transcript. The other +; settings are to send messages to the wlf file only (messages that +; are recorded in the wlf file can be viewed in the MsgViewer) or +; to both the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; displaymsgmode = tran + +; Control transcripting of elaboration/runtime messages not +; addressed by the displaymsgmode setting. The default is to +; have messages appear only in the transcript. The other settings +; are to send messages to the wlf file only (messages that are +; recorded in the wlf file can be viewed in the MsgViewer) or to both +; the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; msgmode = tran + +; Controls number of displays of a particluar message +; default value is 5 +; MsgLimitCount = 5 + +[utils] +; Default Library Type (while creating a library with "vlib") +; 0 - legacy library using subdirectories for design units +; 2 - flat library +; DefaultLibType = 2 + +; Flat Library Page Size (while creating a library with "vlib") +; Set the size in bytes for flat library file pages. Libraries containing +; very large files may benefit from a larger value. +; FlatLibPageSize = 8192 + +; Flat Library Page Cleanup Percentage (while creating a library with "vlib") +; Set the percentage of total pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeleteThreshold. +; FlatLibPageDeletePercentage = 50 + +; Flat Library Page Cleanup Threshold (while creating a library with "vlib") +; Set the number of pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeletePercentage. +; FlatLibPageDeleteThreshold = 1000 + + diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/selectio_lvds_tx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/selectio_lvds_tx.sh new file mode 100644 index 00000000..92defc70 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/selectio_lvds_tx.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : selectio_lvds_tx.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Mar 19 17:32:07 +0800 2023 +# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: selectio_lvds_tx.sh [-help] +# usage: selectio_lvds_tx.sh [-lib_map_path] +# usage: selectio_lvds_tx.sh [-noclean_files] +# usage: selectio_lvds_tx.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'selectio_lvds_tx.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "selectio_lvds_tx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_tx.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="C:/Mentor/CompLib/2019.1.3" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_tx.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: selectio_lvds_tx.sh [-help]\n\ +Usage: selectio_lvds_tx.sh [-lib_map_path]\n\ +Usage: selectio_lvds_tx.sh [-reset_run]\n\ +Usage: selectio_lvds_tx.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/selectio_lvds_tx.udo b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/selectio_lvds_tx.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/simulate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/simulate.do new file mode 100644 index 00000000..b02f3576 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.selectio_lvds_tx xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {selectio_lvds_tx.udo} + +run -all + +quit -force diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/wave.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/README.txt new file mode 100644 index 00000000..9e224e68 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Mar 19 17:32:07 +0800 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./selectio_lvds_tx.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './selectio_lvds_tx.sh' script. + +./selectio_lvds_tx.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./selectio_lvds_tx.sh -noclean_files + +For more information on the script, please type './selectio_lvds_tx.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/compile.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/compile.do new file mode 100644 index 00000000..03db5d0e --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/compile.do @@ -0,0 +1,23 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 \ +"../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v" \ +"../../../ip/selectio_lvds_tx/selectio_lvds_tx.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/elaborate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/elaborate.do new file mode 100644 index 00000000..b83fde90 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.selectio_lvds_tx xil_defaultlib.glbl -o selectio_lvds_tx_opt diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/file_info.txt new file mode 100644 index 00000000..eddbf85c --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +selectio_lvds_tx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v, +selectio_lvds_tx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/selectio_lvds_tx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/selectio_lvds_tx.sh new file mode 100644 index 00000000..ce28d77d --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/selectio_lvds_tx.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : selectio_lvds_tx.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Mar 19 17:32:07 +0800 2023 +# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: selectio_lvds_tx.sh [-help] +# usage: selectio_lvds_tx.sh [-lib_map_path] +# usage: selectio_lvds_tx.sh [-noclean_files] +# usage: selectio_lvds_tx.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'selectio_lvds_tx.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "selectio_lvds_tx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_tx.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_tx.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: selectio_lvds_tx.sh [-help]\n\ +Usage: selectio_lvds_tx.sh [-lib_map_path]\n\ +Usage: selectio_lvds_tx.sh [-reset_run]\n\ +Usage: selectio_lvds_tx.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/selectio_lvds_tx.udo b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/selectio_lvds_tx.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/simulate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/simulate.do new file mode 100644 index 00000000..86367bfa --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib selectio_lvds_tx_opt + +do {wave.do} + +view wave +view structure +view signals + +do {selectio_lvds_tx.udo} + +run -all + +quit -force diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/wave.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/README.txt new file mode 100644 index 00000000..9e224e68 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Mar 19 17:32:07 +0800 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./selectio_lvds_tx.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './selectio_lvds_tx.sh' script. + +./selectio_lvds_tx.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./selectio_lvds_tx.sh -noclean_files + +For more information on the script, please type './selectio_lvds_tx.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/compile.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/compile.do new file mode 100644 index 00000000..3b4ef4cf --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/compile.do @@ -0,0 +1,23 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v" \ +"../../../ip/selectio_lvds_tx/selectio_lvds_tx.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/file_info.txt new file mode 100644 index 00000000..eddbf85c --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +selectio_lvds_tx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v, +selectio_lvds_tx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/selectio_lvds_tx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/selectio_lvds_tx.sh new file mode 100644 index 00000000..104c1667 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/selectio_lvds_tx.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : selectio_lvds_tx.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Mar 19 17:32:07 +0800 2023 +# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: selectio_lvds_tx.sh [-help] +# usage: selectio_lvds_tx.sh [-lib_map_path] +# usage: selectio_lvds_tx.sh [-noclean_files] +# usage: selectio_lvds_tx.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'selectio_lvds_tx.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "selectio_lvds_tx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_tx.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_tx.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: selectio_lvds_tx.sh [-help]\n\ +Usage: selectio_lvds_tx.sh [-lib_map_path]\n\ +Usage: selectio_lvds_tx.sh [-reset_run]\n\ +Usage: selectio_lvds_tx.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/selectio_lvds_tx.udo b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/selectio_lvds_tx.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/simulate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/simulate.do new file mode 100644 index 00000000..934173ec --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+selectio_lvds_tx -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.selectio_lvds_tx xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {selectio_lvds_tx.udo} + +run -all + +endsim + +quit -force diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/wave.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/README.txt new file mode 100644 index 00000000..9e224e68 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Mar 19 17:32:07 +0800 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./selectio_lvds_tx.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './selectio_lvds_tx.sh' script. + +./selectio_lvds_tx.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./selectio_lvds_tx.sh -noclean_files + +For more information on the script, please type './selectio_lvds_tx.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/file_info.txt new file mode 100644 index 00000000..eddbf85c --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +selectio_lvds_tx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v, +selectio_lvds_tx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/selectio_lvds_tx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/selectio_lvds_tx.sh new file mode 100644 index 00000000..8bc40400 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/selectio_lvds_tx.sh @@ -0,0 +1,230 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : selectio_lvds_tx.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Mar 19 17:32:07 +0800 2023 +# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: selectio_lvds_tx.sh [-help] +# usage: selectio_lvds_tx.sh [-lib_map_path] +# usage: selectio_lvds_tx.sh [-noclean_files] +# usage: selectio_lvds_tx.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'selectio_lvds_tx.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "selectio_lvds_tx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts -sverilog \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + "$ref_dir/../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v" \ + "$ref_dir/../../../ip/selectio_lvds_tx/selectio_lvds_tx.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.selectio_lvds_tx xil_defaultlib.glbl -o selectio_lvds_tx_simv +} + +# RUN_STEP: +simulate() +{ + ./selectio_lvds_tx_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_tx.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key selectio_lvds_tx_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc selectio_lvds_tx_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_tx.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: selectio_lvds_tx.sh [-help]\n\ +Usage: selectio_lvds_tx.sh [-lib_map_path]\n\ +Usage: selectio_lvds_tx.sh [-reset_run]\n\ +Usage: selectio_lvds_tx.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/simulate.do b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/README.txt new file mode 100644 index 00000000..03fedd1b --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Mar 19 17:32:07 +0800 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./selectio_lvds_tx.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './selectio_lvds_tx.sh' script. + +./selectio_lvds_tx.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./selectio_lvds_tx.sh -noclean_files + +For more information on the script, please type './selectio_lvds_tx.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/file_info.txt new file mode 100644 index 00000000..eddbf85c --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +selectio_lvds_tx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v, +selectio_lvds_tx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/run.f b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/run.f new file mode 100644 index 00000000..36638505 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/run.f @@ -0,0 +1,15 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v" \ + "../../../ip/selectio_lvds_tx/selectio_lvds_tx.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/selectio_lvds_tx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/selectio_lvds_tx.sh new file mode 100644 index 00000000..2879c179 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xcelium/selectio_lvds_tx.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : selectio_lvds_tx.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Mar 19 17:32:07 +0800 2023 +# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: selectio_lvds_tx.sh [-help] +# usage: selectio_lvds_tx.sh [-lib_map_path] +# usage: selectio_lvds_tx.sh [-noclean_files] +# usage: selectio_lvds_tx.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'selectio_lvds_tx.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "selectio_lvds_tx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.selectio_lvds_tx \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_tx.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_tx.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: selectio_lvds_tx.sh [-help]\n\ +Usage: selectio_lvds_tx.sh [-lib_map_path]\n\ +Usage: selectio_lvds_tx.sh [-reset_run]\n\ +Usage: selectio_lvds_tx.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/README.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/README.txt new file mode 100644 index 00000000..9e224e68 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Mar 19 17:32:07 +0800 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./selectio_lvds_tx.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './selectio_lvds_tx.sh' script. + +./selectio_lvds_tx.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./selectio_lvds_tx.sh -noclean_files + +For more information on the script, please type './selectio_lvds_tx.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/cmd.tcl b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/elab.opt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/elab.opt new file mode 100644 index 00000000..931a8002 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/elab.opt @@ -0,0 +1 @@ +--relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot selectio_lvds_tx xil_defaultlib.selectio_lvds_tx xil_defaultlib.glbl -log elaborate.log diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/file_info.txt b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/file_info.txt new file mode 100644 index 00000000..3f418daf --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/file_info.txt @@ -0,0 +1,3 @@ +selectio_lvds_tx_selectio_wiz.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v, +selectio_lvds_tx.v,verilog,xil_defaultlib,../../../ip/selectio_lvds_tx/selectio_lvds_tx.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/glbl.v b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/selectio_lvds_tx.sh b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/selectio_lvds_tx.sh new file mode 100644 index 00000000..828ad7b1 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/selectio_lvds_tx.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : selectio_lvds_tx.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Mar 19 17:32:07 +0800 2023 +# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: selectio_lvds_tx.sh [-help] +# usage: selectio_lvds_tx.sh [-lib_map_path] +# usage: selectio_lvds_tx.sh [-noclean_files] +# usage: selectio_lvds_tx.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=C:/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "selectio_lvds_tx.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot selectio_lvds_tx xil_defaultlib.selectio_lvds_tx xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim selectio_lvds_tx -key {Behavioral:sim_1:Functional:selectio_lvds_tx} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./selectio_lvds_tx.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="C:/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb selectio_lvds_tx.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./selectio_lvds_tx.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: selectio_lvds_tx.sh [-help]\n\ +Usage: selectio_lvds_tx.sh [-lib_map_path]\n\ +Usage: selectio_lvds_tx.sh [-reset_run]\n\ +Usage: selectio_lvds_tx.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/vlog.prj b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/vlog.prj new file mode 100644 index 00000000..4014d965 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/vlog.prj @@ -0,0 +1,7 @@ +verilog xil_defaultlib \ +"../../../ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v" \ +"../../../ip/selectio_lvds_tx/selectio_lvds_tx.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/xsim.ini b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/xsim.ini new file mode 100644 index 00000000..6cb07f57 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/ip_user_files/sim_scripts/selectio_lvds_tx/xsim/xsim.ini @@ -0,0 +1,430 @@ +std=$RDI_DATADIR/xsim/vhdl/std +ieee=$RDI_DATADIR/xsim/vhdl/ieee +ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed +vl=$RDI_DATADIR/xsim/vhdl/vl +synopsys=$RDI_DATADIR/xsim/vhdl/synopsys +secureip=$RDI_DATADIR/xsim/verilog/secureip +unisim=$RDI_DATADIR/xsim/vhdl/unisim +unimacro=$RDI_DATADIR/xsim/vhdl/unimacro +unifast=$RDI_DATADIR/xsim/vhdl/unifast +unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver +unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver +unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver +simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver +system_cache_v4_0_6=$RDI_DATADIR/xsim/ip/system_cache_v4_0_6 +bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0 +g709_rs_decoder_v2_2_8=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_8 +xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0 +mipi_dphy_v4_1_4=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_1_4 +iomodule_v3_1_4=$RDI_DATADIR/xsim/ip/iomodule_v3_1_4 +ieee802d3_50g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_11 +common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0 +lte_fft_v2_1_0=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_0 +ieee802d3_50g_rs_fec_v2_0_1=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_1 +convolution_v9_0_14=$RDI_DATADIR/xsim/ip/convolution_v9_0_14 +gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4 +v_cfa_v7_0_14=$RDI_DATADIR/xsim/ip/v_cfa_v7_0_14 +axi4svideo_bridge_v1_0_10=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_10 +pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11 +v_vscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_13 +xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6 +gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux +ethernet_1_10_25g_v2_2_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_2_3 +zynq_ultra_ps_e_v3_3_0=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_0 +v_cresample_v4_0_14=$RDI_DATADIR/xsim/ip/v_cresample_v4_0_14 +v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9 +v_scenechange_v1_0_1=$RDI_DATADIR/xsim/ip/v_scenechange_v1_0_1 +hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0 +ahblite_axi_bridge_v3_0_14=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_14 +tri_mode_ethernet_mac_v9_0_14=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_14 +blk_mem_gen_v8_4_3=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_3 +noc_mc_ddr4_phy_v1_0_0=$RDI_DATADIR/xsim/ip/noc_mc_ddr4_phy_v1_0_0 +axi_data_fifo_v2_1_18=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_18 +axi_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_5 +ethernet_1_10_25g_v2_0_5=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_0_5 +compact_gt_v1_0_5=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_5 +axi_gpio_v2_0_21=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_21 +qdma_v3_0_2=$RDI_DATADIR/xsim/ip/qdma_v3_0_2 +viterbi_v9_1_11=$RDI_DATADIR/xsim/ip/viterbi_v9_1_11 +sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2 +ba317=$RDI_DATADIR/xsim/ip/ba317 +xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4 +fifo_generator_v13_2_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_4 +axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14 +vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0 +axi_emc_v3_0_19=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_19 +cmac_v2_5_1=$RDI_DATADIR/xsim/ip/cmac_v2_5_1 +floating_point_v7_1_8=$RDI_DATADIR/xsim/ip/floating_point_v7_1_8 +xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6 +vid_phy_controller_v2_2_3=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_3 +common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1 +axi_firewall_v1_0_7=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_7 +util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1 +axis_accelerator_adapter_v2_1_15=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_15 +tmr_comparator_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_2 +sd_fec_v1_0_2=$RDI_DATADIR/xsim/ip/sd_fec_v1_0_2 +tmr_manager_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_4 +tsn_temac_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_4 +usxgmii_v1_0_5=$RDI_DATADIR/xsim/ip/usxgmii_v1_0_5 +lte_dl_channel_encoder_v4_0_0=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v4_0_0 +ai_noc=$RDI_DATADIR/xsim/ip/ai_noc +lte_3gpp_mimo_decoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_15 +v_uhdsdi_audio_v1_0_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_0_0 +axi4stream_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_5 +cmac_usplus_v2_4_5=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_4_5 +etrnic_v1_1_2=$RDI_DATADIR/xsim/ip/etrnic_v1_1_2 +floating_point_v7_0_16=$RDI_DATADIR/xsim/ip/floating_point_v7_0_16 +axi_dma_v7_1_20=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_20 +jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi +axi_traffic_gen_v3_0_5=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_5 +emb_mem_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_1 +axi_amm_bridge_v1_0_9=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_9 +axi_datamover_v5_1_21=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_21 +v_axi4s_vid_out_v4_0_10=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_10 +jesd204_v7_2_6=$RDI_DATADIR/xsim/ip/jesd204_v7_2_6 +v_letterbox_v1_0_13=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_13 +interlaken_v2_4_3=$RDI_DATADIR/xsim/ip/interlaken_v2_4_3 +uhdsdi_gt_v2_0_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_0 +axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7 +rst_vip_v1_0_3=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_3 +audio_formatter_v1_0_1=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_1 +lte_3gpp_channel_estimator_v2_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_16 +v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13 +g709_fec_v2_3_5=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_5 +xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6 +axi_chip2chip_v5_0_6=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_6 +fc32_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_11 +v_mix_v3_0_3=$RDI_DATADIR/xsim/ip/v_mix_v3_0_3 +multi_channel_25g_rs_fec_v1_0_5=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_5 +in_system_ibert_v1_0_9=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_9 +ethernet_1_10_25g_v2_1_4=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_1_4 +axis_broadcaster_v1_1_18=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_18 +axis_combiner_v1_1_17=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_17 +axi_apb_bridge_v3_0_15=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_15 +displayport_v9_0_1=$RDI_DATADIR/xsim/ip/displayport_v9_0_1 +clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2 +hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1 +axi_register_slice_v2_1_19=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_19 +vid_phy_controller_v2_1_5=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_5 +picxo=$RDI_DATADIR/xsim/ip/picxo +usxgmii_v1_1_0=$RDI_DATADIR/xsim/ip/usxgmii_v1_1_0 +v_vcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_13 +bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0 +prc_v1_3_2=$RDI_DATADIR/xsim/ip/prc_v1_3_2 +axi_usb2_device_v5_0_20=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_20 +lte_3gpp_mimo_encoder_v4_0_14=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_14 +l_ethernet_v2_5_2=$RDI_DATADIR/xsim/ip/l_ethernet_v2_5_2 +xdma_v4_1_3=$RDI_DATADIR/xsim/ip/xdma_v4_1_3 +axis_vio_v1_0_0=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_0 +c_counter_binary_v12_0_13=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_13 +noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0 +xbip_dsp48_macro_v3_0_17=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_17 +c_accum_v12_0_13=$RDI_DATADIR/xsim/ip/c_accum_v12_0_13 +xbip_multadd_v3_0_14=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_14 +axi_uartlite_v2_0_23=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_23 +noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0 +axi_intc_v4_1_13=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_13 +i2s_transmitter_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_3 +pc_cfr_v6_0_8=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_8 +mutex_v2_1_10=$RDI_DATADIR/xsim/ip/mutex_v2_1_10 +c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6 +sid_v8_0_14=$RDI_DATADIR/xsim/ip/sid_v8_0_14 +fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6 +quadsgmii_v3_4_6=$RDI_DATADIR/xsim/ip/quadsgmii_v3_4_6 +microblaze_v11_0_1=$RDI_DATADIR/xsim/ip/microblaze_v11_0_1 +lib_bmg_v1_0_12=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_12 +dds_compiler_v6_0_18=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_18 +me_pl_v1_0=$RDI_DATADIR/xsim/ip/me_pl_v1_0 +gtwizard_ultrascale_v1_7_6=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_6 +axis_clock_converter_v1_1_20=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_20 +nvmeha_v1_0_0=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_0 +tmr_inject_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_3 +axi_mcdma_v1_1_0=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_0 +axi_hwicap_v3_0_23=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_23 +v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0 +v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0 +canfd_v2_0_1=$RDI_DATADIR/xsim/ip/canfd_v2_0_1 +gig_ethernet_pcs_pma_v16_1_6=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_6 +lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2 +ieee802d3_rs_fec_v2_0_5=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_5 +ibert_lib_v1_0_6=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_6 +high_speed_selectio_wiz_v3_4_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_1 +xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6 +fec_5g_common_v1_0_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_1 +tmr_voter_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_2 +hdmi_gt_controller_v1_0_0=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_0 +axi_traffic_gen_v2_0_20=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_20 +flexo_100g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_11 +v_smpte_uhdsdi_v1_0_7=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_7 +xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6 +fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10 +ieee802d3_rs_fec_v1_0_15=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_15 +axis_subset_converter_v1_1_19=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_19 +noc_nmu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_v1_0_0 +duc_ddc_compiler_v3_0_15=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_15 +dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13 +mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0 +ieee802d3_200g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_7 +sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1 +mrmac_v1_0_0=$RDI_DATADIR/xsim/ip/mrmac_v1_0_0 +sem_ultra_v3_1_11=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_11 +v_tpg_v8_0_1=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_1 +axi_tft_v2_0_22=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_22 +ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13 +switch_core_top_v1_0_7=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_7 +rama_v1_1_2_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_2_lib +v_hcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_13 +emb_fifo_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_1 +hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3 +axis_data_fifo_v2_0_1=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_1 +hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0 +rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1 +displayport_v8_1_1=$RDI_DATADIR/xsim/ip/displayport_v8_1_1 +axi_mmu_v2_1_17=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_17 +proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13 +pc_cfr_v6_3_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_3_0 +v_osd_v6_0_16=$RDI_DATADIR/xsim/ip/v_osd_v6_0_16 +pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12 +xfft_v9_0_17=$RDI_DATADIR/xsim/ip/xfft_v9_0_17 +axi_cdma_v4_1_19=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_19 +audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0 +lib_fifo_v1_0_13=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_13 +v_enhance_v8_0_15=$RDI_DATADIR/xsim/ip/v_enhance_v8_0_15 +axi_clock_converter_v2_1_18=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_18 +xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0 +emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5 +axi_mm2s_mapper_v1_1_18=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_18 +xfft_v7_2_9=$RDI_DATADIR/xsim/ip/xfft_v7_2_9 +pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0 +v_smpte_sdi_v3_0_8=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_8 +fir_compiler_v7_2_12=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_12 +div_gen_v5_1_15=$RDI_DATADIR/xsim/ip/div_gen_v5_1_15 +mdm_v3_2_16=$RDI_DATADIR/xsim/ip/mdm_v3_2_16 +v_axi4s_remap_v1_0_11=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_11 +xxv_ethernet_v2_5_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_5_3 +xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2 +ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig +remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4 +pr_axi_shutdown_manager_v1_0_1=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_1 +axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0 +smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0 +axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib +axi_dwidth_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_19 +xlconstant_v1_1_6=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_6 +tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6 +mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2 +v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1 +axi_fifo_mm_s_v4_2_1=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_1 +util_idelay_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_1 +rs_toolbox_v9_0_7=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_7 +v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0 +dsp_macro_v1_0_0=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_0 +pc_cfr_v6_2_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_2 +axi_timer_v2_0_21=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_21 +high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1 +axi_sideband_util_v1_0_3=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_3 +sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2 +gmii_to_rgmii_v4_0_7=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_0_7 +xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2 +high_speed_selectio_wiz_v3_5_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_5_1 +axi_msg_v1_0_5=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_5 +axi_ahblite_bridge_v3_0_16=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_16 +v_rgb2ycrcb_v7_1_13=$RDI_DATADIR/xsim/ip/v_rgb2ycrcb_v7_1_13 +v_mix_v4_0_0=$RDI_DATADIR/xsim/ip/v_mix_v4_0_0 +axi_ethernetlite_v3_0_17=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_17 +axi_uart16550_v2_0_21=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_21 +axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0 +vfb_v1_0_13=$RDI_DATADIR/xsim/ip/vfb_v1_0_13 +advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0 +ats_switch_v1_0_2=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_2 +interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4 +axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub +cpri_v8_10_3=$RDI_DATADIR/xsim/ip/cpri_v8_10_3 +c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6 +v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0 +stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0 +rld3_pl_v1_0_1=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_1 +ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0 +lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0 +axi_epc_v2_0_22=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_22 +g709_rs_encoder_v2_2_6=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_6 +blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6 +tmr_sem_v1_0_9=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_9 +fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6 +axi_vdma_v6_3_7=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_7 +axis_data_fifo_v1_1_20=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_20 +xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip +axi_ethernet_buffer_v2_0_20=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_20 +rs_encoder_v9_0_15=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_15 +axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0 +ta_dma_v1_0_3=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_3 +tcc_encoder_3gpp_v5_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_15 +axi_perf_mon_v5_0_21=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_21 +noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0 +sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1 +lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2 +v_csc_v1_0_13=$RDI_DATADIR/xsim/ip/v_csc_v1_0_13 +shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0 +lte_fft_v2_0_18=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_18 +gtwizard_ultrascale_v1_6_11=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_11 +amm_axi_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_5 +mii_to_rmii_v2_0_21=$RDI_DATADIR/xsim/ip/mii_to_rmii_v2_0_21 +videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5 +audio_clock_recovery_v1_0=$RDI_DATADIR/xsim/ip/audio_clock_recovery_v1_0 +cmac_v2_4_1=$RDI_DATADIR/xsim/ip/cmac_v2_4_1 +i2s_receiver_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_3 +v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0 +v_demosaic_v1_0_5=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_5 +remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4 +microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4 +hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3 +etrnic_v1_0_3=$RDI_DATADIR/xsim/ip/etrnic_v1_0_3 +xfft_v9_1_2=$RDI_DATADIR/xsim/ip/xfft_v9_1_2 +ddr4_pl_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_2 +xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6 +cmac_usplus_v2_5_3=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_5_3 +jesd204c_v4_1_1=$RDI_DATADIR/xsim/ip/jesd204c_v4_1_1 +debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1 +axis_protocol_checker_v2_0_3=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_3 +v_frmbuf_wr_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_2 +v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9 +mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4 +lte_dl_channel_encoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_15 +axi_protocol_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_19 +xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0 +clk_gen_sim_v1_0_0=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_0 +axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0 +microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7 +cmpy_v6_0_17=$RDI_DATADIR/xsim/ip/cmpy_v6_0_17 +cmac_v2_3_5=$RDI_DATADIR/xsim/ip/cmac_v2_3_5 +ieee802d3_400g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_7 +xxv_ethernet_v2_4_5=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_4_5 +axi_timebase_wdt_v3_0_11=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_11 +tcc_decoder_3gppmm_v2_0_18=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_18 +v_deinterlacer_v5_0_13=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_13 +dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16 +axi_fifo_mm_s_v4_1_16=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_16 +processing_system7_vip_v1_0_7=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_7 +g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18 +rs_decoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_16 +c_shift_ram_v12_0_13=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_13 +displayport_v7_0_11=$RDI_DATADIR/xsim/ip/displayport_v7_0_11 +v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0 +v_deinterlacer_v4_0_12=$RDI_DATADIR/xsim/ip/v_deinterlacer_v4_0_12 +sem_v4_1_12=$RDI_DATADIR/xsim/ip/sem_v4_1_12 +xaui_v12_3_6=$RDI_DATADIR/xsim/ip/xaui_v12_3_6 +ten_gig_eth_mac_v15_1_7=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_7 +oddr_v1_0_0=$RDI_DATADIR/xsim/ip/oddr_v1_0_0 +c_addsub_v12_0_13=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_13 +v_ccm_v6_0_15=$RDI_DATADIR/xsim/ip/v_ccm_v6_0_15 +zynq_ultra_ps_e_vip_v1_0_5=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_5 +cic_compiler_v4_0_14=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_14 +c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6 +axi_memory_init_v1_0_0=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_0 +pr_decoupler_v1_0_7=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_7 +timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4 +lte_pucch_receiver_v2_0_16=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_16 +zynq_ultra_ps_e_v3_2_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_3 +v_gamma_lut_v1_0_5=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_5 +bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0 +pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0 +tcc_encoder_3gpplte_v4_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_15 +polar_v1_0_3=$RDI_DATADIR/xsim/ip/polar_v1_0_3 +rxaui_v4_4_6=$RDI_DATADIR/xsim/ip/rxaui_v4_4_6 +xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6 +v_gamma_v7_0_15=$RDI_DATADIR/xsim/ip/v_gamma_v7_0_15 +ernic_v1_0_1=$RDI_DATADIR/xsim/ip/ernic_v1_0_1 +high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3 +mailbox_v2_1_11=$RDI_DATADIR/xsim/ip/mailbox_v2_1_11 +video_frame_crc_v1_0_1=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_1 +axi_sg_v4_1_12=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_12 +ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0 +lmb_bram_if_cntlr_v4_0_16=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_16 +l_ethernet_v2_4_3=$RDI_DATADIR/xsim/ip/l_ethernet_v2_4_3 +dft_v4_1_1=$RDI_DATADIR/xsim/ip/dft_v4_1_1 +rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0 +axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6 +v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0 +stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0 +lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0 +uhdsdi_gt_v1_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_3 +pc_cfr_v6_1_4=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_4 +lmb_v10_v3_0_9=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_9 +axis_interconnect_v1_1_17=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_17 +cordic_v6_0_15=$RDI_DATADIR/xsim/ip/cordic_v6_0_15 +axis_register_slice_v1_1_19=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_19 +axis_switch_v1_1_19=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_19 +axi_interconnect_v1_7_16=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_16 +mult_gen_v12_0_15=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_15 +spdif_v2_0_21=$RDI_DATADIR/xsim/ip/spdif_v2_0_21 +v_hscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_13 +ethernet_1_10_25g_v2_3_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_3_3 +xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6 +axi_quad_spi_v3_2_18=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_18 +axi_bram_ctrl_v4_1_1=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_1 +axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4 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+lte_ul_channel_decoder_v4_0_16=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_16 +soft_ecc_proxy_v1_0_0=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_0 +pr_bitstream_monitor_v1_0_1=$RDI_DATADIR/xsim/ip/pr_bitstream_monitor_v1_0_1 +sync_ip=$RDI_DATADIR/xsim/ip/sync_ip +v_frmbuf_rd_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_1_2 +c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6 +cmac_usplus_v2_6_2=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_6_2 +axi_mcdma_v1_0_5=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_5 +c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6 +g709_fec_v2_4_1=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_1 +lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0 +ai_pl=$RDI_DATADIR/xsim/ip/ai_pl +fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4 +v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0 +l_ethernet_v2_3_5=$RDI_DATADIR/xsim/ip/l_ethernet_v2_3_5 +microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6 +v_uhdsdi_audio_v2_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_1 +ldpc_v2_0_3=$RDI_DATADIR/xsim/ip/ldpc_v2_0_3 +xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6 +xpm=$RDI_DATADIR/xsim/ip/xpm +srio_gen2_v4_1_6=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_6 +g975_efec_i4_v1_0_17=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_17 +noc_na_v1_0_0=$RDI_DATADIR/xsim/ip/noc_na_v1_0_0 +roe_framer_v2_0_1=$RDI_DATADIR/xsim/ip/roe_framer_v2_0_1 +xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10 +generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0 +ten_gig_eth_pcs_pma_v6_0_15=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_15 +can_v5_0_22=$RDI_DATADIR/xsim/ip/can_v5_0_22 +av_pat_gen_v1_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_0 +fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1 +lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0 +axis_dwidth_converter_v1_1_18=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_18 +lte_rach_detector_v3_1_5=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_5 +xxv_ethernet_v3_0_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v3_0_3 +axi_iic_v2_0_22=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_22 +axi_pcie_v2_9_1=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_1 +util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4 +sim_trig_top_v1_0=$RDI_DATADIR/xsim/ip/sim_trig_top_v1_0 +v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0 +v_tpg_v7_0_13=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_13 +sd_fec_v1_1_3=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_3 +xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6 +lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2 +v_multi_scaler_v1_0_1=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_0_1 +axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0 +advanced_io_wizard_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_0 +mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8 +axi_pcie3_v3_0_9=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_9 +axi_vfifo_ctrl_v2_0_21=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_21 +xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0 diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1ad2c59fcdfd22ab/1ad2c59fcdfd22ab.xci b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1ad2c59fcdfd22ab/1ad2c59fcdfd22ab.xci new file mode 100644 index 00000000..522e90a5 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1ad2c59fcdfd22ab/1ad2c59fcdfd22ab.xci @@ -0,0 +1,89 @@ + + + xilinx.com + ipcache + 1ad2c59fcdfd22ab + 0 + + + selectio_lvds_tx + + + 100000000 + 100000000 + RISING + OUTPUTS + NONE + 0 + LVCMOS33 + NONE + 0 + SINGLE + NOT_APP + NOT_APP + BUFIO2 + NONE + false + false + LVCMOS33 + false + SINGLE + LVCMOS18 + SINGLE + 0 + false + selectio_lvds_tx + C0 + BUFR + false + false + ASYNC + false + true + true + NETWORKING + None + SDR + NONE + 0 + NONE + 0 + BUFIO + LVCMOS33 + SINGLE + SAME_EDGE_PIPELINED + ASYNC + NETWORKING + SAME_EDGE + 4 + 4 + 0 + false + false + Custom + kintex7 + xc7k410t + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 1ad2c59fcdfd22ab + selectio_lvds_tx + af96b0bc + 20 + IP_Unknown + 13 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1ad2c59fcdfd22ab/selectio_lvds_tx.dcp b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1ad2c59fcdfd22ab/selectio_lvds_tx.dcp new file mode 100644 index 00000000..3b076b1d Binary files /dev/null and b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1ad2c59fcdfd22ab/selectio_lvds_tx.dcp differ diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1ad2c59fcdfd22ab/selectio_lvds_tx_sim_netlist.v b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1ad2c59fcdfd22ab/selectio_lvds_tx_sim_netlist.v new file mode 100644 index 00000000..b92f03fe --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1ad2c59fcdfd22ab/selectio_lvds_tx_sim_netlist.v @@ -0,0 +1,227 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +// Date : Sun Mar 19 17:32:20 2023 +// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_sim_netlist.v +// Design : selectio_lvds_tx +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* DEV_W = "4" *) (* SYS_W = "4" *) +(* NotValidForBitStream *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix + (data_out_from_device, + data_out_to_pins, + clk_in, + clk_out, + io_reset); + input [3:0]data_out_from_device; + output [3:0]data_out_to_pins; + input clk_in; + output clk_out; + input io_reset; + + (* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire clk_in; + wire clk_out; + wire [3:0]data_out_from_device; + (* DRIVE = "12" *) (* IOSTANDARD = "LVCMOS33" *) (* SLEW = "SLOW" *) wire [3:0]data_out_to_pins; + wire io_reset; + + (* DEV_W = "4" *) + (* SYS_W = "4" *) + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz inst + (.clk_in(clk_in), + .clk_out(clk_out), + .data_out_from_device(data_out_from_device), + .data_out_to_pins(data_out_to_pins), + .io_reset(io_reset)); +endmodule + +(* DEV_W = "4" *) (* SYS_W = "4" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz + (data_out_from_device, + data_out_to_pins, + clk_in, + clk_out, + io_reset); + input [3:0]data_out_from_device; + output [3:0]data_out_to_pins; + input clk_in; + output clk_out; + input io_reset; + + wire clk_in; + wire clk_in_int; + wire clk_out; + wire [3:0]data_out_from_device; + wire [3:0]data_out_to_pins; + wire io_reset; + wire \pins[0].data_out_from_device_q ; + wire \pins[1].data_out_from_device_q ; + wire \pins[2].data_out_from_device_q ; + wire \pins[3].data_out_from_device_q ; + + (* BOX_TYPE = "PRIMITIVE" *) + BUFR #( + .BUFR_DIVIDE("BYPASS"), + .SIM_DEVICE("7SERIES")) + clkout_buf_inst + (.CE(1'b1), + .CLR(1'b0), + .I(clk_in_int), + .O(clk_out)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF ibuf_clk_inst + (.I(clk_in), + .O(clk_in_int)); + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[0].fdre_out_inst + (.C(clk_out), + .CE(1'b1), + .D(data_out_from_device[0]), + .Q(\pins[0].data_out_from_device_q ), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + OBUF \pins[0].obuf_inst + (.I(\pins[0].data_out_from_device_q ), + .O(data_out_to_pins[0])); + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[1].fdre_out_inst + (.C(clk_out), + .CE(1'b1), + .D(data_out_from_device[1]), + .Q(\pins[1].data_out_from_device_q ), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + OBUF \pins[1].obuf_inst + (.I(\pins[1].data_out_from_device_q ), + .O(data_out_to_pins[1])); + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[2].fdre_out_inst + (.C(clk_out), + .CE(1'b1), + .D(data_out_from_device[2]), + .Q(\pins[2].data_out_from_device_q ), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + OBUF \pins[2].obuf_inst + (.I(\pins[2].data_out_from_device_q ), + .O(data_out_to_pins[2])); + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[3].fdre_out_inst + (.C(clk_out), + .CE(1'b1), + .D(data_out_from_device[3]), + .Q(\pins[3].data_out_from_device_q ), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + OBUF \pins[3].obuf_inst + (.I(\pins[3].data_out_from_device_q ), + .O(data_out_to_pins[3])); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1ad2c59fcdfd22ab/selectio_lvds_tx_sim_netlist.vhdl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1ad2c59fcdfd22ab/selectio_lvds_tx_sim_netlist.vhdl new file mode 100644 index 00000000..ca24cb4a --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1ad2c59fcdfd22ab/selectio_lvds_tx_sim_netlist.vhdl @@ -0,0 +1,191 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Sun Mar 19 17:32:20 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_sim_netlist.vhdl +-- Design : selectio_lvds_tx +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz is + port ( + data_out_from_device : in STD_LOGIC_VECTOR ( 3 downto 0 ); + data_out_to_pins : out STD_LOGIC_VECTOR ( 3 downto 0 ); + clk_in : in STD_LOGIC; + clk_out : out STD_LOGIC; + io_reset : in STD_LOGIC + ); + attribute DEV_W : integer; + attribute DEV_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz : entity is 4; + attribute SYS_W : integer; + attribute SYS_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz : entity is 4; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz is + signal clk_in_int : STD_LOGIC; + signal \^clk_out\ : STD_LOGIC; + signal \pins[0].data_out_from_device_q\ : STD_LOGIC; + signal \pins[1].data_out_from_device_q\ : STD_LOGIC; + signal \pins[2].data_out_from_device_q\ : STD_LOGIC; + signal \pins[3].data_out_from_device_q\ : STD_LOGIC; + attribute BOX_TYPE : string; + attribute BOX_TYPE of clkout_buf_inst : label is "PRIMITIVE"; + attribute BOX_TYPE of ibuf_clk_inst : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of ibuf_clk_inst : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of ibuf_clk_inst : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of ibuf_clk_inst : label is "AUTO"; + attribute BOX_TYPE of \pins[0].fdre_out_inst\ : label is "PRIMITIVE"; + attribute IOB : string; + attribute IOB of \pins[0].fdre_out_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[0].obuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \pins[0].obuf_inst\ : label is "DONT_CARE"; + attribute BOX_TYPE of \pins[1].fdre_out_inst\ : label is "PRIMITIVE"; + attribute IOB of \pins[1].fdre_out_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[1].obuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \pins[1].obuf_inst\ : label is "DONT_CARE"; + attribute BOX_TYPE of \pins[2].fdre_out_inst\ : label is "PRIMITIVE"; + attribute IOB of \pins[2].fdre_out_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[2].obuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \pins[2].obuf_inst\ : label is "DONT_CARE"; + attribute BOX_TYPE of \pins[3].fdre_out_inst\ : label is "PRIMITIVE"; + attribute IOB of \pins[3].fdre_out_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[3].obuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \pins[3].obuf_inst\ : label is "DONT_CARE"; +begin + clk_out <= \^clk_out\; +clkout_buf_inst: unisim.vcomponents.BUFR + generic map( + BUFR_DIVIDE => "BYPASS", + SIM_DEVICE => "7SERIES" + ) + port map ( + CE => '1', + CLR => '0', + I => clk_in_int, + O => \^clk_out\ + ); +ibuf_clk_inst: unisim.vcomponents.IBUF + port map ( + I => clk_in, + O => clk_in_int + ); +\pins[0].fdre_out_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => \^clk_out\, + CE => '1', + D => data_out_from_device(0), + Q => \pins[0].data_out_from_device_q\, + R => io_reset + ); +\pins[0].obuf_inst\: unisim.vcomponents.OBUF + port map ( + I => \pins[0].data_out_from_device_q\, + O => data_out_to_pins(0) + ); +\pins[1].fdre_out_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => \^clk_out\, + CE => '1', + D => data_out_from_device(1), + Q => \pins[1].data_out_from_device_q\, + R => io_reset + ); +\pins[1].obuf_inst\: unisim.vcomponents.OBUF + port map ( + I => \pins[1].data_out_from_device_q\, + O => data_out_to_pins(1) + ); +\pins[2].fdre_out_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => \^clk_out\, + CE => '1', + D => data_out_from_device(2), + Q => \pins[2].data_out_from_device_q\, + R => io_reset + ); +\pins[2].obuf_inst\: unisim.vcomponents.OBUF + port map ( + I => \pins[2].data_out_from_device_q\, + O => data_out_to_pins(2) + ); +\pins[3].fdre_out_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => \^clk_out\, + CE => '1', + D => data_out_from_device(3), + Q => \pins[3].data_out_from_device_q\, + R => io_reset + ); +\pins[3].obuf_inst\: unisim.vcomponents.OBUF + port map ( + I => \pins[3].data_out_from_device_q\, + O => data_out_to_pins(3) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + port ( + data_out_from_device : in STD_LOGIC_VECTOR ( 3 downto 0 ); + data_out_to_pins : out STD_LOGIC_VECTOR ( 3 downto 0 ); + clk_in : in STD_LOGIC; + clk_out : out STD_LOGIC; + io_reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; + attribute DEV_W : integer; + attribute DEV_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is 4; + attribute SYS_W : integer; + attribute SYS_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is 4; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + attribute DEV_W of inst : label is 4; + attribute SYS_W of inst : label is 4; +begin +inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz + port map ( + clk_in => clk_in, + clk_out => clk_out, + data_out_from_device(3 downto 0) => data_out_from_device(3 downto 0), + data_out_to_pins(3 downto 0) => data_out_to_pins(3 downto 0), + io_reset => io_reset + ); +end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1ad2c59fcdfd22ab/selectio_lvds_tx_stub.v b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1ad2c59fcdfd22ab/selectio_lvds_tx_stub.v new file mode 100644 index 00000000..7f67ac5d --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1ad2c59fcdfd22ab/selectio_lvds_tx_stub.v @@ -0,0 +1,24 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +// Date : Sun Mar 19 17:32:20 2023 +// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_stub.v +// Design : selectio_lvds_tx +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(data_out_from_device, data_out_to_pins, + clk_in, clk_out, io_reset) +/* synthesis syn_black_box black_box_pad_pin="data_out_from_device[3:0],data_out_to_pins[3:0],clk_in,clk_out,io_reset" */; + input [3:0]data_out_from_device; + output [3:0]data_out_to_pins; + input clk_in; + output clk_out; + input io_reset; +endmodule diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1ad2c59fcdfd22ab/selectio_lvds_tx_stub.vhdl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1ad2c59fcdfd22ab/selectio_lvds_tx_stub.vhdl new file mode 100644 index 00000000..0edd62b5 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1ad2c59fcdfd22ab/selectio_lvds_tx_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Sun Mar 19 17:32:20 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_stub.vhdl +-- Design : selectio_lvds_tx +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + data_out_from_device : in STD_LOGIC_VECTOR ( 3 downto 0 ); + data_out_to_pins : out STD_LOGIC_VECTOR ( 3 downto 0 ); + clk_in : in STD_LOGIC; + clk_out : out STD_LOGIC; + io_reset : in STD_LOGIC + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "data_out_from_device[3:0],data_out_to_pins[3:0],clk_in,clk_out,io_reset"; +begin +end; diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/9a6afb606ad4ce08/9a6afb606ad4ce08.xci b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/9a6afb606ad4ce08/9a6afb606ad4ce08.xci new file mode 100644 index 00000000..64e1935b --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/9a6afb606ad4ce08/9a6afb606ad4ce08.xci @@ -0,0 +1,89 @@ + + + xilinx.com + ipcache + 9a6afb606ad4ce08 + 0 + + + selectio_lvds_rx + + + 100000000 + 100000000 + RISING + INPUTS + NONE + 0 + LVCMOS33 + NONE + 0 + SINGLE + NOT_APP + NOT_APP + BUFIO2 + NONE + false + false + LVCMOS33 + false + SINGLE + LVCMOS18 + SINGLE + 0 + false + selectio_lvds_rx + C0 + BUFR + false + false + ASYNC + false + true + true + NETWORKING + None + SDR + NONE + 0 + NONE + 0 + BUFIO + LVCMOS33 + SINGLE + SAME_EDGE_PIPELINED + ASYNC + NETWORKING + SAME_EDGE + 4 + 1 + 0 + false + false + Custom + kintex7 + xc7k410t + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 9a6afb606ad4ce08 + selectio_lvds_rx + af96b0bc + 20 + IP_Unknown + 13 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/9a6afb606ad4ce08/selectio_lvds_rx.dcp b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/9a6afb606ad4ce08/selectio_lvds_rx.dcp new file mode 100644 index 00000000..a567d5f1 Binary files /dev/null and b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/9a6afb606ad4ce08/selectio_lvds_rx.dcp differ diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/9a6afb606ad4ce08/selectio_lvds_rx_sim_netlist.v b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/9a6afb606ad4ce08/selectio_lvds_rx_sim_netlist.v new file mode 100644 index 00000000..6b02d1d1 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/9a6afb606ad4ce08/selectio_lvds_rx_sim_netlist.v @@ -0,0 +1,172 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +// Date : Sun Mar 19 17:32:20 2023 +// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_sim_netlist.v +// Design : selectio_lvds_rx +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* DEV_W = "1" *) (* SYS_W = "1" *) +(* NotValidForBitStream *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix + (data_in_from_pins, + data_in_to_device, + clk_in, + clk_out, + io_reset); + input [0:0]data_in_from_pins; + output [0:0]data_in_to_device; + input clk_in; + output clk_out; + input io_reset; + + (* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire clk_in; + wire clk_out; + (* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire [0:0]data_in_from_pins; + wire [0:0]data_in_to_device; + wire io_reset; + + (* DEV_W = "1" *) + (* SYS_W = "1" *) + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz inst + (.clk_in(clk_in), + .clk_out(clk_out), + .data_in_from_pins(data_in_from_pins), + .data_in_to_device(data_in_to_device), + .io_reset(io_reset)); +endmodule + +(* DEV_W = "1" *) (* SYS_W = "1" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz + (data_in_from_pins, + data_in_to_device, + clk_in, + clk_out, + io_reset); + input [0:0]data_in_from_pins; + output [0:0]data_in_to_device; + input clk_in; + output clk_out; + input io_reset; + + wire clk_in; + wire clk_in_int; + wire clk_out; + wire [0:0]data_in_from_pins; + wire data_in_from_pins_int; + wire [0:0]data_in_to_device; + wire io_reset; + + (* BOX_TYPE = "PRIMITIVE" *) + BUFR #( + .BUFR_DIVIDE("BYPASS"), + .SIM_DEVICE("7SERIES")) + clkout_buf_inst + (.CE(1'b1), + .CLR(1'b0), + .I(clk_in_int), + .O(clk_out)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF ibuf_clk_inst + (.I(clk_in), + .O(clk_in_int)); + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[0].fdre_in_inst + (.C(clk_out), + .CE(1'b1), + .D(data_in_from_pins_int), + .Q(data_in_to_device), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF \pins[0].ibuf_inst + (.I(data_in_from_pins), + .O(data_in_from_pins_int)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/9a6afb606ad4ce08/selectio_lvds_rx_sim_netlist.vhdl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/9a6afb606ad4ce08/selectio_lvds_rx_sim_netlist.vhdl new file mode 100644 index 00000000..3aff4705 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/9a6afb606ad4ce08/selectio_lvds_rx_sim_netlist.vhdl @@ -0,0 +1,121 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Sun Mar 19 17:32:20 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_sim_netlist.vhdl +-- Design : selectio_lvds_rx +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz is + port ( + data_in_from_pins : in STD_LOGIC_VECTOR ( 0 to 0 ); + data_in_to_device : out STD_LOGIC_VECTOR ( 0 to 0 ); + clk_in : in STD_LOGIC; + clk_out : out STD_LOGIC; + io_reset : in STD_LOGIC + ); + attribute DEV_W : integer; + attribute DEV_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz : entity is 1; + attribute SYS_W : integer; + attribute SYS_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz : entity is 1; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz is + signal clk_in_int : STD_LOGIC; + signal \^clk_out\ : STD_LOGIC; + signal data_in_from_pins_int : STD_LOGIC; + attribute BOX_TYPE : string; + attribute BOX_TYPE of clkout_buf_inst : label is "PRIMITIVE"; + attribute BOX_TYPE of ibuf_clk_inst : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of ibuf_clk_inst : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of ibuf_clk_inst : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of ibuf_clk_inst : label is "AUTO"; + attribute BOX_TYPE of \pins[0].fdre_in_inst\ : label is "PRIMITIVE"; + attribute IOB : string; + attribute IOB of \pins[0].fdre_in_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[0].ibuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \pins[0].ibuf_inst\ : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "0"; + attribute IFD_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "AUTO"; +begin + clk_out <= \^clk_out\; +clkout_buf_inst: unisim.vcomponents.BUFR + generic map( + BUFR_DIVIDE => "BYPASS", + SIM_DEVICE => "7SERIES" + ) + port map ( + CE => '1', + CLR => '0', + I => clk_in_int, + O => \^clk_out\ + ); +ibuf_clk_inst: unisim.vcomponents.IBUF + port map ( + I => clk_in, + O => clk_in_int + ); +\pins[0].fdre_in_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => \^clk_out\, + CE => '1', + D => data_in_from_pins_int, + Q => data_in_to_device(0), + R => io_reset + ); +\pins[0].ibuf_inst\: unisim.vcomponents.IBUF + port map ( + I => data_in_from_pins(0), + O => data_in_from_pins_int + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + port ( + data_in_from_pins : in STD_LOGIC_VECTOR ( 0 to 0 ); + data_in_to_device : out STD_LOGIC_VECTOR ( 0 to 0 ); + clk_in : in STD_LOGIC; + clk_out : out STD_LOGIC; + io_reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; + attribute DEV_W : integer; + attribute DEV_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is 1; + attribute SYS_W : integer; + attribute SYS_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is 1; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + attribute DEV_W of inst : label is 1; + attribute SYS_W of inst : label is 1; +begin +inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz + port map ( + clk_in => clk_in, + clk_out => clk_out, + data_in_from_pins(0) => data_in_from_pins(0), + data_in_to_device(0) => data_in_to_device(0), + io_reset => io_reset + ); +end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/9a6afb606ad4ce08/selectio_lvds_rx_stub.v b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/9a6afb606ad4ce08/selectio_lvds_rx_stub.v new file mode 100644 index 00000000..ecbb847c --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/9a6afb606ad4ce08/selectio_lvds_rx_stub.v @@ -0,0 +1,24 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +// Date : Sun Mar 19 17:32:20 2023 +// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_stub.v +// Design : selectio_lvds_rx +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(data_in_from_pins, data_in_to_device, clk_in, + clk_out, io_reset) +/* synthesis syn_black_box black_box_pad_pin="data_in_from_pins[0:0],data_in_to_device[0:0],clk_in,clk_out,io_reset" */; + input [0:0]data_in_from_pins; + output [0:0]data_in_to_device; + input clk_in; + output clk_out; + input io_reset; +endmodule diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/9a6afb606ad4ce08/selectio_lvds_rx_stub.vhdl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/9a6afb606ad4ce08/selectio_lvds_rx_stub.vhdl new file mode 100644 index 00000000..236bc0a3 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/9a6afb606ad4ce08/selectio_lvds_rx_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Sun Mar 19 17:32:20 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_stub.vhdl +-- Design : selectio_lvds_rx +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + data_in_from_pins : in STD_LOGIC_VECTOR ( 0 to 0 ); + data_in_to_device : out STD_LOGIC_VECTOR ( 0 to 0 ); + clk_in : in STD_LOGIC; + clk_out : out STD_LOGIC; + io_reset : in STD_LOGIC + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "data_in_from_pins[0:0],data_in_to_device[0:0],clk_in,clk_out,io_reset"; +begin +end; diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/a60812ed144d9d97/stats.txt b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/a60812ed144d9d97/stats.txt new file mode 100644 index 00000000..a843dc45 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/a60812ed144d9d97/stats.txt @@ -0,0 +1,2 @@ +NumberHits:1 +Timestamp: Sun Mar 19 09:31:54 UTC 2023 diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c2b0e4781c06dae9/c2b0e4781c06dae9.xci b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c2b0e4781c06dae9/c2b0e4781c06dae9.xci new file mode 100644 index 00000000..4c4813f1 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c2b0e4781c06dae9/c2b0e4781c06dae9.xci @@ -0,0 +1,89 @@ + + + xilinx.com + ipcache + c2b0e4781c06dae9 + 0 + + + selectio_lvds_rx + + + 100000000 + 100000000 + RISING + INPUTS + NONE + 0 + LVCMOS33 + NONE + 0 + SINGLE + NOT_APP + NOT_APP + BUFIO2 + NONE + false + false + LVCMOS33 + false + SINGLE + LVCMOS18 + SINGLE + 0 + false + selectio_lvds_rx + C0 + BUFR + false + false + ASYNC + false + true + true + NETWORKING + None + SDR + NONE + 0 + NONE + 0 + BUFIO + LVCMOS33 + SINGLE + SAME_EDGE_PIPELINED + ASYNC + NETWORKING + SAME_EDGE + 4 + 2 + 0 + false + false + Custom + kintex7 + xc7k410t + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + c2b0e4781c06dae9 + selectio_lvds_rx + af96b0bc + 19 + IP_Unknown + 13 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c2b0e4781c06dae9/selectio_lvds_rx.dcp b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c2b0e4781c06dae9/selectio_lvds_rx.dcp new file mode 100644 index 00000000..4dee4331 Binary files /dev/null and b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c2b0e4781c06dae9/selectio_lvds_rx.dcp differ diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c2b0e4781c06dae9/selectio_lvds_rx_sim_netlist.v b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c2b0e4781c06dae9/selectio_lvds_rx_sim_netlist.v new file mode 100644 index 00000000..fc68628a --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c2b0e4781c06dae9/selectio_lvds_rx_sim_netlist.v @@ -0,0 +1,192 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +// Date : Sun Mar 19 18:02:10 2023 +// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_sim_netlist.v +// Design : selectio_lvds_rx +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* DEV_W = "2" *) (* SYS_W = "2" *) +(* NotValidForBitStream *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix + (data_in_from_pins, + data_in_to_device, + clk_in, + clk_out, + io_reset); + input [1:0]data_in_from_pins; + output [1:0]data_in_to_device; + input clk_in; + output clk_out; + input io_reset; + + (* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire clk_in; + wire clk_out; + (* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire [1:0]data_in_from_pins; + wire [1:0]data_in_to_device; + wire io_reset; + + (* DEV_W = "2" *) + (* SYS_W = "2" *) + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz inst + (.clk_in(clk_in), + .clk_out(clk_out), + .data_in_from_pins(data_in_from_pins), + .data_in_to_device(data_in_to_device), + .io_reset(io_reset)); +endmodule + +(* DEV_W = "2" *) (* SYS_W = "2" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz + (data_in_from_pins, + data_in_to_device, + clk_in, + clk_out, + io_reset); + input [1:0]data_in_from_pins; + output [1:0]data_in_to_device; + input clk_in; + output clk_out; + input io_reset; + + wire clk_in; + wire clk_in_int; + wire clk_out; + wire [1:0]data_in_from_pins; + wire [1:0]data_in_from_pins_int; + wire [1:0]data_in_to_device; + wire io_reset; + + (* BOX_TYPE = "PRIMITIVE" *) + BUFR #( + .BUFR_DIVIDE("BYPASS"), + .SIM_DEVICE("7SERIES")) + clkout_buf_inst + (.CE(1'b1), + .CLR(1'b0), + .I(clk_in_int), + .O(clk_out)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF ibuf_clk_inst + (.I(clk_in), + .O(clk_in_int)); + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[0].fdre_in_inst + (.C(clk_out), + .CE(1'b1), + .D(data_in_from_pins_int[0]), + .Q(data_in_to_device[0]), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF \pins[0].ibuf_inst + (.I(data_in_from_pins[0]), + .O(data_in_from_pins_int[0])); + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[1].fdre_in_inst + (.C(clk_out), + .CE(1'b1), + .D(data_in_from_pins_int[1]), + .Q(data_in_to_device[1]), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF \pins[1].ibuf_inst + (.I(data_in_from_pins[1]), + .O(data_in_from_pins_int[1])); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c2b0e4781c06dae9/selectio_lvds_rx_sim_netlist.vhdl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c2b0e4781c06dae9/selectio_lvds_rx_sim_netlist.vhdl new file mode 100644 index 00000000..3b9edd64 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c2b0e4781c06dae9/selectio_lvds_rx_sim_netlist.vhdl @@ -0,0 +1,146 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Sun Mar 19 18:02:10 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_sim_netlist.vhdl +-- Design : selectio_lvds_rx +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz is + port ( + data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 ); + data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 ); + clk_in : in STD_LOGIC; + clk_out : out STD_LOGIC; + io_reset : in STD_LOGIC + ); + attribute DEV_W : integer; + attribute DEV_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz : entity is 2; + attribute SYS_W : integer; + attribute SYS_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz : entity is 2; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz is + signal clk_in_int : STD_LOGIC; + signal \^clk_out\ : STD_LOGIC; + signal data_in_from_pins_int : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of clkout_buf_inst : label is "PRIMITIVE"; + attribute BOX_TYPE of ibuf_clk_inst : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of ibuf_clk_inst : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of ibuf_clk_inst : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of ibuf_clk_inst : label is "AUTO"; + attribute BOX_TYPE of \pins[0].fdre_in_inst\ : label is "PRIMITIVE"; + attribute IOB : string; + attribute IOB of \pins[0].fdre_in_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[0].ibuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \pins[0].ibuf_inst\ : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "0"; + attribute IFD_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "AUTO"; + attribute BOX_TYPE of \pins[1].fdre_in_inst\ : label is "PRIMITIVE"; + attribute IOB of \pins[1].fdre_in_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[1].ibuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \pins[1].ibuf_inst\ : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE of \pins[1].ibuf_inst\ : label is "0"; + attribute IFD_DELAY_VALUE of \pins[1].ibuf_inst\ : label is "AUTO"; +begin + clk_out <= \^clk_out\; +clkout_buf_inst: unisim.vcomponents.BUFR + generic map( + BUFR_DIVIDE => "BYPASS", + SIM_DEVICE => "7SERIES" + ) + port map ( + CE => '1', + CLR => '0', + I => clk_in_int, + O => \^clk_out\ + ); +ibuf_clk_inst: unisim.vcomponents.IBUF + port map ( + I => clk_in, + O => clk_in_int + ); +\pins[0].fdre_in_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => \^clk_out\, + CE => '1', + D => data_in_from_pins_int(0), + Q => data_in_to_device(0), + R => io_reset + ); +\pins[0].ibuf_inst\: unisim.vcomponents.IBUF + port map ( + I => data_in_from_pins(0), + O => data_in_from_pins_int(0) + ); +\pins[1].fdre_in_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => \^clk_out\, + CE => '1', + D => data_in_from_pins_int(1), + Q => data_in_to_device(1), + R => io_reset + ); +\pins[1].ibuf_inst\: unisim.vcomponents.IBUF + port map ( + I => data_in_from_pins(1), + O => data_in_from_pins_int(1) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + port ( + data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 ); + data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 ); + clk_in : in STD_LOGIC; + clk_out : out STD_LOGIC; + io_reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; + attribute DEV_W : integer; + attribute DEV_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is 2; + attribute SYS_W : integer; + attribute SYS_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is 2; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + attribute DEV_W of inst : label is 2; + attribute SYS_W of inst : label is 2; +begin +inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz + port map ( + clk_in => clk_in, + clk_out => clk_out, + data_in_from_pins(1 downto 0) => data_in_from_pins(1 downto 0), + data_in_to_device(1 downto 0) => data_in_to_device(1 downto 0), + io_reset => io_reset + ); +end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c2b0e4781c06dae9/selectio_lvds_rx_stub.v b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c2b0e4781c06dae9/selectio_lvds_rx_stub.v new file mode 100644 index 00000000..3835ef0e --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c2b0e4781c06dae9/selectio_lvds_rx_stub.v @@ -0,0 +1,24 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +// Date : Sun Mar 19 18:02:10 2023 +// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_stub.v +// Design : selectio_lvds_rx +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(data_in_from_pins, data_in_to_device, clk_in, + clk_out, io_reset) +/* synthesis syn_black_box black_box_pad_pin="data_in_from_pins[1:0],data_in_to_device[1:0],clk_in,clk_out,io_reset" */; + input [1:0]data_in_from_pins; + output [1:0]data_in_to_device; + input clk_in; + output clk_out; + input io_reset; +endmodule diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c2b0e4781c06dae9/selectio_lvds_rx_stub.vhdl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c2b0e4781c06dae9/selectio_lvds_rx_stub.vhdl new file mode 100644 index 00000000..66f541cb --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c2b0e4781c06dae9/selectio_lvds_rx_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Sun Mar 19 18:02:10 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_stub.vhdl +-- Design : selectio_lvds_rx +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 ); + data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 ); + clk_in : in STD_LOGIC; + clk_out : out STD_LOGIC; + io_reset : in STD_LOGIC + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "data_in_from_pins[1:0],data_in_to_device[1:0],clk_in,clk_out,io_reset"; +begin +end; diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/fffcbdb43410d449/fffcbdb43410d449.xci b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/fffcbdb43410d449/fffcbdb43410d449.xci new file mode 100644 index 00000000..a33b759e --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/fffcbdb43410d449/fffcbdb43410d449.xci @@ -0,0 +1,88 @@ + + + xilinx.com + ipcache + fffcbdb43410d449 + 0 + + + selectio_lvds_rx + + + 100000000 + RISING + INPUTS + NONE + 0 + LVCMOS33 + NONE + 0 + SINGLE + NOT_APP + NOT_APP + BUFIO2 + NONE + false + false + LVCMOS33 + false + SINGLE + LVCMOS18 + SINGLE + 0 + false + selectio_lvds_rx + C0 + BUFR + false + false + ASYNC + false + true + true + NETWORKING + None + SDR + NONE + 0 + NONE + 0 + MMCM + LVCMOS33 + SINGLE + SAME_EDGE_PIPELINED + ASYNC + NETWORKING + SAME_EDGE + 4 + 2 + 0 + false + false + Custom + kintex7 + xc7k410t + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + fffcbdb43410d449 + selectio_lvds_rx + af96b0bc + 19 + IP_Unknown + 13 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/fffcbdb43410d449/selectio_lvds_rx.dcp b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/fffcbdb43410d449/selectio_lvds_rx.dcp new file mode 100644 index 00000000..cff080d8 Binary files /dev/null and b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/fffcbdb43410d449/selectio_lvds_rx.dcp differ diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/fffcbdb43410d449/selectio_lvds_rx_sim_netlist.v b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/fffcbdb43410d449/selectio_lvds_rx_sim_netlist.v new file mode 100644 index 00000000..17ca1a18 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/fffcbdb43410d449/selectio_lvds_rx_sim_netlist.v @@ -0,0 +1,168 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +// Date : Sun Mar 19 18:25:55 2023 +// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_sim_netlist.v +// Design : selectio_lvds_rx +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* DEV_W = "2" *) (* SYS_W = "2" *) +(* NotValidForBitStream *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix + (data_in_from_pins, + data_in_to_device, + clk_in, + io_reset); + input [1:0]data_in_from_pins; + output [1:0]data_in_to_device; + input clk_in; + input io_reset; + + wire clk_in; + (* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire [1:0]data_in_from_pins; + wire [1:0]data_in_to_device; + wire io_reset; + + (* DEV_W = "2" *) + (* SYS_W = "2" *) + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz inst + (.clk_in(clk_in), + .data_in_from_pins(data_in_from_pins), + .data_in_to_device(data_in_to_device), + .io_reset(io_reset)); +endmodule + +(* DEV_W = "2" *) (* SYS_W = "2" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz + (data_in_from_pins, + data_in_to_device, + clk_in, + io_reset); + input [1:0]data_in_from_pins; + output [1:0]data_in_to_device; + input clk_in; + input io_reset; + + wire clk_in; + wire [1:0]data_in_from_pins; + wire [1:0]data_in_from_pins_int; + wire [1:0]data_in_to_device; + wire io_reset; + + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[0].fdre_in_inst + (.C(clk_in), + .CE(1'b1), + .D(data_in_from_pins_int[0]), + .Q(data_in_to_device[0]), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF \pins[0].ibuf_inst + (.I(data_in_from_pins[0]), + .O(data_in_from_pins_int[0])); + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[1].fdre_in_inst + (.C(clk_in), + .CE(1'b1), + .D(data_in_from_pins_int[1]), + .Q(data_in_to_device[1]), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF \pins[1].ibuf_inst + (.I(data_in_from_pins[1]), + .O(data_in_from_pins_int[1])); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/fffcbdb43410d449/selectio_lvds_rx_sim_netlist.vhdl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/fffcbdb43410d449/selectio_lvds_rx_sim_netlist.vhdl new file mode 100644 index 00000000..6afbe0fe --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/fffcbdb43410d449/selectio_lvds_rx_sim_netlist.vhdl @@ -0,0 +1,119 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Sun Mar 19 18:25:55 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_sim_netlist.vhdl +-- Design : selectio_lvds_rx +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz is + port ( + data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 ); + data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 ); + clk_in : in STD_LOGIC; + io_reset : in STD_LOGIC + ); + attribute DEV_W : integer; + attribute DEV_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz : entity is 2; + attribute SYS_W : integer; + attribute SYS_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz : entity is 2; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz is + signal data_in_from_pins_int : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of \pins[0].fdre_in_inst\ : label is "PRIMITIVE"; + attribute IOB : string; + attribute IOB of \pins[0].fdre_in_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[0].ibuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of \pins[0].ibuf_inst\ : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "AUTO"; + attribute BOX_TYPE of \pins[1].fdre_in_inst\ : label is "PRIMITIVE"; + attribute IOB of \pins[1].fdre_in_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[1].ibuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \pins[1].ibuf_inst\ : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE of \pins[1].ibuf_inst\ : label is "0"; + attribute IFD_DELAY_VALUE of \pins[1].ibuf_inst\ : label is "AUTO"; +begin +\pins[0].fdre_in_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => clk_in, + CE => '1', + D => data_in_from_pins_int(0), + Q => data_in_to_device(0), + R => io_reset + ); +\pins[0].ibuf_inst\: unisim.vcomponents.IBUF + port map ( + I => data_in_from_pins(0), + O => data_in_from_pins_int(0) + ); +\pins[1].fdre_in_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => clk_in, + CE => '1', + D => data_in_from_pins_int(1), + Q => data_in_to_device(1), + R => io_reset + ); +\pins[1].ibuf_inst\: unisim.vcomponents.IBUF + port map ( + I => data_in_from_pins(1), + O => data_in_from_pins_int(1) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + port ( + data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 ); + data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 ); + clk_in : in STD_LOGIC; + io_reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; + attribute DEV_W : integer; + attribute DEV_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is 2; + attribute SYS_W : integer; + attribute SYS_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is 2; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + attribute DEV_W of inst : label is 2; + attribute SYS_W of inst : label is 2; +begin +inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz + port map ( + clk_in => clk_in, + data_in_from_pins(1 downto 0) => data_in_from_pins(1 downto 0), + data_in_to_device(1 downto 0) => data_in_to_device(1 downto 0), + io_reset => io_reset + ); +end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/fffcbdb43410d449/selectio_lvds_rx_stub.v b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/fffcbdb43410d449/selectio_lvds_rx_stub.v new file mode 100644 index 00000000..bc718007 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/fffcbdb43410d449/selectio_lvds_rx_stub.v @@ -0,0 +1,23 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +// Date : Sun Mar 19 18:25:55 2023 +// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_stub.v +// Design : selectio_lvds_rx +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(data_in_from_pins, data_in_to_device, clk_in, + io_reset) +/* synthesis syn_black_box black_box_pad_pin="data_in_from_pins[1:0],data_in_to_device[1:0],clk_in,io_reset" */; + input [1:0]data_in_from_pins; + output [1:0]data_in_to_device; + input clk_in; + input io_reset; +endmodule diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/fffcbdb43410d449/selectio_lvds_rx_stub.vhdl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/fffcbdb43410d449/selectio_lvds_rx_stub.vhdl new file mode 100644 index 00000000..bb883204 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/fffcbdb43410d449/selectio_lvds_rx_stub.vhdl @@ -0,0 +1,31 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Sun Mar 19 18:25:55 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_stub.vhdl +-- Design : selectio_lvds_rx +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 ); + data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 ); + clk_in : in STD_LOGIC; + io_reset : in STD_LOGIC + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "data_in_from_pins[1:0],data_in_to_device[1:0],clk_in,io_reset"; +begin +end; diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf index d5a8b387..804c12cf 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf @@ -1,19 +1,37 @@ version:1 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:31:00:00 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a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf @@ -1,7 +1,11 @@ version:1 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6164646578697374696e67697068616e646c6572:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6164646578697374696e67697068616e646c6572:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:35:00:00 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+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:33:00:00 +eof:1295650939 diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc index 9b342093..0161c5dc 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc @@ -1,3 +1,3 @@ version:1 -6d6f64655f636f756e7465727c4755494d6f6465:1 +6d6f64655f636f756e7465727c4755494d6f6465:6 eof: diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf index 8ff85414..2601d715 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf @@ -1,7 +1,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863376b343130746666673930302d32:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:696c615f74785f7278:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:73656c656374696f5f6c7664735f7278:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 @@ -33,9 +33,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30363a333573:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313634332e3931304d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313233322e3035394d42:00:00 -eof:3774782289 -33 -0935 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313773:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313034332e3332384d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3635332e3430364d42:00:00 +eof:1985685470 diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml index 0998b98b..853a5270 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -17,35 +17,57 @@ This means code written to parse this file will need to be revisited each subseq - - + + + - - + + + + + - - + + + - - - - + + + + + + + + + + + + + + - + + + + + + + - - - + + + + - + - +
diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_2.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_2.xml new file mode 100644 index 00000000..e532533b --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_3.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_3.xml new file mode 100644 index 00000000..72d89256 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_4.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_4.xml new file mode 100644 index 00000000..72d89256 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/gen_run.xml index 446e206b..fffbc896 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/gen_run.xml index 4f110e18..f1a8d638 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/gen_run.xml index 7272da0b..6cb0e7c8 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ad9361_clk_gen_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ad9361_clk_gen_synth_1/gen_run.xml index b3f8ef28..ea9a01d9 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ad9361_clk_gen_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ad9361_clk_gen_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/add_s24_s32_s32_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/add_s24_s32_s32_synth_1/gen_run.xml index 62d685ff..3039caae 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/add_s24_s32_s32_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/add_s24_s32_s32_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg1_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg1_synth_1/gen_run.xml index 9b8bb4e1..6fcd85c2 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg1_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg1_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg2_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg2_synth_1/gen_run.xml index a6aa0ff6..206676ca 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg2_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg2_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/gen_run.xml index 5aa86975..b3fc9d28 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x12_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x12_synth_1/gen_run.xml index 800999c4..073e9c91 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x12_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x12_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/cmpy_16x12_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/cmpy_16x12_synth_1/gen_run.xml index cf410b12..db729118 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/cmpy_16x12_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/cmpy_16x12_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/gen_run.xml index 94954b4b..f43dfc70 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/dont_touch.xdc b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/dont_touch.xdc deleted file mode 100644 index a88cc87b..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/dont_touch.xdc +++ /dev/null @@ -1,32 +0,0 @@ -# This file is automatically generated. -# It contains project source information necessary for synthesis and implementation. - -# IP: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xci -# IP: The module: 'fifo_AntCtrl' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xdc -# XDC: The top module name and the constraint reference have the same name: 'fifo_AntCtrl'. Do not add the DONT_TOUCH constraint. -set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet - -# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_clocks.xdc -# XDC: The top module name and the constraint reference have the same name: 'fifo_AntCtrl'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet - -# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'fifo_AntCtrl'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet - -# IP: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xci -# IP: The module: 'fifo_AntCtrl' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xdc -# XDC: The top module name and the constraint reference have the same name: 'fifo_AntCtrl'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet - -# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_clocks.xdc -# XDC: The top module name and the constraint reference have the same name: 'fifo_AntCtrl'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet - -# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'fifo_AntCtrl'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl.dcp b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl.dcp deleted file mode 100644 index 2581eed2..00000000 Binary files a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl.dcp and /dev/null differ diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl.tcl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl.tcl deleted file mode 100644 index d1d478e4..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl.tcl +++ /dev/null @@ -1,158 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param general.maxThreads 20 -set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64 -set_param project.vivado.isBlockSynthRun true -set_msg_config -msgmgr_mode ooc_run -create_project -in_memory -part xc7k410tffg900-2 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] -set_property parent.project_path D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.xpr [current_project] -set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language Verilog [current_project] -set_property ip_output_repo d:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xci -set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xdc] -set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_clocks.xdc] -set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_ooc.xdc] - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -read_xdc dont_touch.xdc -set_property used_in_implementation false [get_files dont_touch.xdc] -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1 -new_name fifo_AntCtrl -ip [get_ips fifo_AntCtrl]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top fifo_AntCtrl -part xc7k410tffg900-2 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix fifo_AntCtrl_ fifo_AntCtrl.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_AntCtrl_stub.v - lappend ipCachedFiles fifo_AntCtrl_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_AntCtrl_stub.vhdl - lappend ipCachedFiles fifo_AntCtrl_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_AntCtrl_sim_netlist.v - lappend ipCachedFiles fifo_AntCtrl_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_AntCtrl_sim_netlist.vhdl - lappend ipCachedFiles fifo_AntCtrl_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp fifo_AntCtrl.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips fifo_AntCtrl] -} - -rename_ref -prefix_all fifo_AntCtrl_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef fifo_AntCtrl.dcp -create_report "fifo_AntCtrl_synth_1_synth_report_utilization_0" "report_utilization -file fifo_AntCtrl_utilization_synth.rpt -pb fifo_AntCtrl_utilization_synth.pb" - -if { [catch { - write_verilog -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -}; # end if cached_ip - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl.dcp -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xci] - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/fifo_AntCtrl]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.v D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/fifo_AntCtrl - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/fifo_AntCtrl]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.vhdl D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/fifo_AntCtrl - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/fifo_AntCtrl]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.v D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/fifo_AntCtrl - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/fifo_AntCtrl]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.vhdl D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/fifo_AntCtrl - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl.vds b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl.vds deleted file mode 100644 index caf8f911..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl.vds +++ /dev/null @@ -1,742 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Sat Mar 18 23:32:54 2023 -# Process ID: 26592 -# Current directory: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1 -# Command line: vivado.exe -log fifo_AntCtrl.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source fifo_AntCtrl.tcl -# Log file: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl.vds -# Journal file: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1\vivado.jou -#----------------------------------------------------------- -Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl' -source fifo_AntCtrl.tcl -notrace -Command: synth_design -top fifo_AntCtrl -part xc7k410tffg900-2 -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' -INFO: [Device 21-403] Loading part xc7k410tffg900-2 -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 33764 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 886.301 ; gain = 177.375 ---------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'fifo_AntCtrl' [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/synth/fifo_AntCtrl.vhd:73] - Parameter C_COMMON_CLOCK bound to: 0 - type: integer - Parameter C_SELECT_XPM bound to: 0 - type: integer - Parameter C_COUNT_TYPE bound to: 0 - type: integer - Parameter C_DATA_COUNT_WIDTH bound to: 10 - type: integer - Parameter C_DEFAULT_VALUE bound to: BlankString - type: string - Parameter C_DIN_WIDTH bound to: 4 - type: integer - Parameter C_DOUT_RST_VAL bound to: 0 - type: string - Parameter C_DOUT_WIDTH bound to: 4 - type: integer - Parameter C_ENABLE_RLOCS bound to: 0 - type: integer - Parameter C_FAMILY bound to: kintex7 - type: string - Parameter C_FULL_FLAGS_RST_VAL bound to: 1 - type: integer - Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer - Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer - Parameter C_HAS_BACKUP bound to: 0 - type: integer - Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer - Parameter C_HAS_INT_CLK bound to: 0 - type: integer - Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer - Parameter C_HAS_OVERFLOW bound to: 0 - type: integer - Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer - Parameter C_HAS_RD_RST bound to: 0 - type: integer - Parameter C_HAS_RST bound to: 1 - type: integer - Parameter C_HAS_SRST bound to: 0 - type: integer - Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer - Parameter C_HAS_VALID bound to: 0 - type: integer - Parameter C_HAS_WR_ACK bound to: 0 - type: integer - Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer - Parameter C_HAS_WR_RST bound to: 0 - type: integer - Parameter C_IMPLEMENTATION_TYPE bound to: 2 - type: integer - Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer - Parameter C_MEMORY_TYPE bound to: 2 - type: integer - Parameter C_MIF_FILE_NAME bound to: BlankString - type: string - Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer - Parameter C_OVERFLOW_LOW bound to: 0 - type: integer - Parameter C_PRELOAD_LATENCY bound to: 1 - type: integer - Parameter C_PRELOAD_REGS bound to: 0 - type: integer - Parameter C_PRIM_FIFO_TYPE bound to: 1kx18 - type: string - Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 2 - type: integer - Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 3 - type: integer - Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer - Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 1021 - type: integer - Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 1020 - type: integer - Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer - Parameter C_RD_DATA_COUNT_WIDTH bound to: 10 - type: integer - Parameter C_RD_DEPTH bound to: 1024 - type: integer - Parameter C_RD_FREQ bound to: 1 - type: integer - Parameter C_RD_PNTR_WIDTH bound to: 10 - type: integer - Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer - Parameter C_USE_DOUT_RST bound to: 1 - type: integer - Parameter C_USE_ECC bound to: 0 - type: integer - Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer - Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer - Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer - Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer - Parameter C_USE_FWFT_DATA_COUNT bound to: 0 - type: integer - Parameter C_VALID_LOW bound to: 0 - type: integer - Parameter C_WR_ACK_LOW bound to: 0 - type: integer - Parameter C_WR_DATA_COUNT_WIDTH bound to: 10 - type: integer - Parameter C_WR_DEPTH bound to: 1024 - type: integer - Parameter C_WR_FREQ bound to: 1 - type: integer - Parameter C_WR_PNTR_WIDTH bound to: 10 - type: integer - Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer - Parameter C_MSGON_VAL bound to: 1 - type: integer - Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer - Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer - Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer - Parameter C_SYNCHRONIZER_STAGE bound to: 2 - type: integer - Parameter C_INTERFACE_TYPE bound to: 0 - type: integer - Parameter C_AXI_TYPE bound to: 1 - type: integer - Parameter C_HAS_AXI_WR_CHANNEL bound to: 1 - type: integer - Parameter C_HAS_AXI_RD_CHANNEL bound to: 1 - type: integer - Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer - Parameter C_HAS_MASTER_CE bound to: 0 - type: integer - Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer - Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer - Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer - Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer - Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer - Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer - Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer - Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer - Parameter C_AXI_LOCK_WIDTH bound to: 1 - type: integer - Parameter C_HAS_AXI_ID bound to: 0 - type: integer - Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer - Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer - Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer - Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer - Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer - Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer - Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer - Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer - Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer - Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer - Parameter C_HAS_AXIS_TDATA bound to: 1 - type: integer - Parameter C_HAS_AXIS_TID bound to: 0 - type: integer - Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer - Parameter C_HAS_AXIS_TUSER bound to: 1 - type: integer - Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer - Parameter C_HAS_AXIS_TLAST bound to: 0 - type: integer - Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer - Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer - Parameter C_AXIS_TDATA_WIDTH bound to: 8 - type: integer - Parameter C_AXIS_TID_WIDTH bound to: 1 - type: integer - Parameter C_AXIS_TDEST_WIDTH bound to: 1 - type: integer - Parameter C_AXIS_TUSER_WIDTH bound to: 4 - type: integer - Parameter C_AXIS_TSTRB_WIDTH bound to: 1 - type: integer - Parameter C_AXIS_TKEEP_WIDTH bound to: 1 - type: integer - Parameter C_WACH_TYPE bound to: 0 - type: integer - Parameter C_WDCH_TYPE bound to: 0 - type: integer - Parameter C_WRCH_TYPE bound to: 0 - type: integer - Parameter C_RACH_TYPE bound to: 0 - type: integer - Parameter C_RDCH_TYPE bound to: 0 - type: integer - Parameter C_AXIS_TYPE bound to: 0 - type: integer - Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 1 - type: integer - Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 1 - type: integer - Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 1 - type: integer - Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 1 - type: integer - Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 1 - type: integer - Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 1 - type: integer - Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer - Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer - Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer - Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer - Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer - Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer - Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string - Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 1kx36 - type: string - Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string - Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string - Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 1kx36 - type: string - Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 1kx18 - type: string - Parameter C_USE_ECC_WACH bound to: 0 - type: integer - Parameter C_USE_ECC_WDCH bound to: 0 - type: integer - Parameter C_USE_ECC_WRCH bound to: 0 - type: integer - Parameter C_USE_ECC_RACH bound to: 0 - type: integer - Parameter C_USE_ECC_RDCH bound to: 0 - type: integer - Parameter C_USE_ECC_AXIS bound to: 0 - type: integer - Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer - Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer - Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer - Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer - Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer - Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer - Parameter C_DIN_WIDTH_WACH bound to: 1 - type: integer - Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer - Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer - Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer - Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer - Parameter C_DIN_WIDTH_AXIS bound to: 1 - type: integer - Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer - Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer - Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer - Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer - Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer - Parameter C_WR_DEPTH_AXIS bound to: 1024 - type: integer - Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer - Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer - Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer - Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer - Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer - Parameter C_WR_PNTR_WIDTH_AXIS bound to: 10 - type: integer - Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer - Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer - Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer - Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer - Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer - Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer - Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer - Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer - Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer - Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer - Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer - Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer - Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer - Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer - Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer - Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer - Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer - Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer - Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 1023 - type: integer - Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer - Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 1023 - type: integer - Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 1023 - type: integer - Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer - Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 1023 - type: integer - Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer - Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer - Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer - Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer - Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer - Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer - Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 1022 - type: integer - Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1022 - type: integer - Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 1022 - type: integer - Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 1022 - type: integer - Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1022 - type: integer - Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 1022 - type: integer - Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer - Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer - Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer - Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer - Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer - Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer -INFO: [Synth 8-3491] module 'fifo_generator_v13_2_4' declared at 'd:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd:38586' bound to instance 'U0' of component 'fifo_generator_v13_2_4' [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/synth/fifo_AntCtrl.vhd:543] -INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_async_rst' [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] -INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1226] -INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_async_rst' (1#1) [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] -INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] -INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:205] -INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (2#1) [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] -INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] -INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:358] -INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (7#1) [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] -INFO: [Synth 8-256] done synthesizing module 'fifo_AntCtrl' (21#1) [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/synth/fifo_AntCtrl.vhd:73] -WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_RST -WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port SRST -WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port SAFETY_CKT_WR_RST -WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[9] -WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[8] -WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[7] -WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[6] -WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[5] -WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[4] -WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[3] -WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[2] -WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[1] -WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[0] -WARNING: [Synth 8-3331] design wr_bin_cntr has unconnected port SRST -WARNING: [Synth 8-3331] design wr_logic has unconnected port WR_EN_INTO_LOGIC -WARNING: [Synth 8-3331] design wr_logic has unconnected port WR_RST_INTO_LOGIC -WARNING: [Synth 8-3331] design wr_logic has unconnected port RD_EN -WARNING: [Synth 8-3331] design wr_logic has unconnected port SRST_FULL_FF -WARNING: [Synth 8-3331] design wr_logic has unconnected port WR_RST_BUSY -WARNING: [Synth 8-3331] design wr_logic has unconnected port EMPTY -WARNING: [Synth 8-3331] design wr_logic has unconnected port RAM_RD_EN -WARNING: [Synth 8-3331] design wr_logic has unconnected port ALMOST_EMPTY -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[9] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[8] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[7] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[6] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[5] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[4] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[3] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[2] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[1] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[0] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[9] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[8] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[7] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[6] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[5] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[4] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[3] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[2] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[1] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[0] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[9] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[8] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[7] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[6] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[5] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[4] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[3] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[2] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[1] -WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[0] -WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port SRST -WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port SAFETY_CKT_RD_RST -WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[9] -WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[8] -WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[7] -WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[6] -WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[5] -WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[4] -WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[3] -WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[2] -WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[1] -WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[0] -WARNING: [Synth 8-3331] design rd_bin_cntr has unconnected port SRST -WARNING: [Synth 8-3331] design rd_logic has unconnected port RD_EN_INTO_LOGIC -WARNING: [Synth 8-3331] design rd_logic has unconnected port RD_RST_INTO_LOGIC -WARNING: [Synth 8-3331] design rd_logic has unconnected port RD_RST_BUSY -WARNING: [Synth 8-3331] design rd_logic has unconnected port RAM_WR_EN -WARNING: [Synth 8-3331] design rd_logic has unconnected port RST_FULL_FF -WARNING: [Synth 8-3331] design rd_logic has unconnected port ALMOST_FULL_FB -WARNING: [Synth 8-3331] design rd_logic has unconnected port FULL -WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[9] -WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[8] -WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[7] -WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[6] -WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[5] -WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[4] -WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[3] -WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[2] -WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[1] -WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[0] -WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[9] -WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[8] -WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[7] -WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[6] -WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[5] -WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[4] -WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[3] -WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[2] -WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[1] -WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[0] -WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[9] -WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[8] -WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[7] -WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[6] -WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[5] -WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[4] -WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[3] -WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[2] -INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 1056.262 ; gain = 347.336 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1056.262 ; gain = 347.336 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1056.262 ; gain = 347.336 ---------------------------------------------------------------------------------- -INFO: [Netlist 29-17] Analyzing 20 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization - -Processing XDC Constraints -Initializing timing engine -Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_ooc.xdc] for cell 'U0' -Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_ooc.xdc] for cell 'U0' -Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xdc] for cell 'U0' -Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xdc] for cell 'U0' -Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/dont_touch.xdc] -Finished Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/dont_touch.xdc] -Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_clocks.xdc] for cell 'U0' -Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_clocks.xdc] for cell 'U0' -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fifo_AntCtrl_propImpl.xdc]. -Resolution: To avoid this warning, move constraints listed in [.Xil/fifo_AntCtrl_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. -Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' -Finished Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' -Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' -Finished Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fifo_AntCtrl_propImpl.xdc]. -Resolution: To avoid this warning, move constraints listed in [.Xil/fifo_AntCtrl_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. -Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' -Finished Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' -Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' -Finished Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fifo_AntCtrl_propImpl.xdc]. -Resolution: To avoid this warning, move constraints listed in [.Xil/fifo_AntCtrl_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. -Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' -Finished Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' -Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' -Finished Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fifo_AntCtrl_propImpl.xdc]. -Resolution: To avoid this warning, move constraints listed in [.Xil/fifo_AntCtrl_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. -Completed Processing XDC Constraints - -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1078.977 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1089.344 ; gain = 10.367 ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1089.344 ; gain = 380.418 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7k410tffg900-2 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1089.344 ; gain = 380.418 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying 'set_property' XDC Constraints ---------------------------------------------------------------------------------- -Applied set_property DONT_TOUCH = true for U0. (constraint file D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/dont_touch.xdc, line 9). -Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint, line ). -Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint, line ). -Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint, line ). -Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint, line ). -Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint, line ). -Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint, line ). ---------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1089.344 ; gain = 380.418 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 1089.344 ; gain = 380.418 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : -+---Adders : - 2 Input 10 Bit Adders := 2 -+---XORs : - 2 Input 10 Bit XORs := 2 - 2 Input 1 Bit XORs := 58 -+---Registers : - 10 Bit Registers := 13 - 4 Bit Registers := 4 - 2 Bit Registers := 3 - 1 Bit Registers := 10 ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- -Hierarchical RTL Component report -Module xpm_cdc_async_rst -Detailed RTL Component Info : -+---Registers : - 2 Bit Registers := 1 -Module xpm_cdc_single -Detailed RTL Component Info : -+---Registers : - 4 Bit Registers := 1 -Module reset_blk_ramfifo -Detailed RTL Component Info : -+---Registers : - 4 Bit Registers := 1 - 2 Bit Registers := 1 - 1 Bit Registers := 6 -Module dmem -Detailed RTL Component Info : -+---Registers : - 4 Bit Registers := 1 -Module xpm_cdc_gray -Detailed RTL Component Info : -+---XORs : - 2 Input 10 Bit XORs := 1 - 2 Input 1 Bit XORs := 9 -+---Registers : - 10 Bit Registers := 4 -Module rd_bin_cntr -Detailed RTL Component Info : -+---Adders : - 2 Input 10 Bit Adders := 1 -+---Registers : - 10 Bit Registers := 2 -Module compare -Detailed RTL Component Info : -+---XORs : - 2 Input 1 Bit XORs := 10 -Module rd_status_flags_as -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 2 -Module wr_bin_cntr -Detailed RTL Component Info : -+---Adders : - 2 Input 10 Bit Adders := 1 -+---Registers : - 10 Bit Registers := 3 -Module wr_status_flags_as -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 2 ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 1540 (col length:140) -BRAMs: 1590 (col length: RAMB18 140 RAMB36 70) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 1089.344 ; gain = 380.418 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start ROM, RAM, DSP and Shift Register Reporting ---------------------------------------------------------------------------------- - -Distributed RAM: Preliminary Mapping Report (see note below) -+------------+-------------------------------------------------------------------------------+----------------+----------------------+------------------------------+ -|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | -+------------+-------------------------------------------------------------------------------+----------------+----------------------+------------------------------+ -|U0 | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 1 K x 4 | RAM64X1D x 16 RAM64M x 16 | -+------------+-------------------------------------------------------------------------------+----------------+----------------------+------------------------------+ - -Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. ---------------------------------------------------------------------------------- -Finished ROM, RAM, DSP and Shift Register Reporting ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Applying XDC Timing Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:34 . Memory (MB): peak = 1089.344 ; gain = 380.418 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:34 . Memory (MB): peak = 1089.344 ; gain = 380.418 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start ROM, RAM, DSP and Shift Register Reporting ---------------------------------------------------------------------------------- - -Distributed RAM: Final Mapping Report -+------------+-------------------------------------------------------------------------------+----------------+----------------------+------------------------------+ -|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | -+------------+-------------------------------------------------------------------------------+----------------+----------------------+------------------------------+ -|U0 | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 1 K x 4 | RAM64X1D x 16 RAM64M x 16 | -+------------+-------------------------------------------------------------------------------+----------------+----------------------+------------------------------+ - ---------------------------------------------------------------------------------- -Finished ROM, RAM, DSP and Shift Register Reporting ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:26 ; elapsed = 00:00:34 . Memory (MB): peak = 1089.344 ; gain = 380.418 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 1089.344 ; gain = 380.418 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 1089.344 ; gain = 380.418 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 1089.344 ; gain = 380.418 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 1089.344 ; gain = 380.418 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 1089.344 ; gain = 380.418 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 1089.344 ; gain = 380.418 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+---------+------+ -| |Cell |Count | -+------+---------+------+ -|1 |LUT1 | 2| -|2 |LUT2 | 30| -|3 |LUT3 | 9| -|4 |LUT4 | 29| -|5 |LUT5 | 10| -|6 |LUT6 | 38| -|7 |MUXCY | 20| -|8 |MUXF7 | 8| -|9 |MUXF8 | 4| -|10 |RAM64M | 16| -|11 |RAM64X1D | 16| -|12 |FDCE | 57| -|13 |FDPE | 17| -|14 |FDRE | 88| -+------+---------+------+ - -Report Instance Areas: -+------+-------------------------------------------------------------------------------------+-----------------------------+------+ -| |Instance |Module |Cells | -+------+-------------------------------------------------------------------------------------+-----------------------------+------+ -|1 |top | | 344| -|2 | U0 |fifo_generator_v13_2_4 | 344| -|3 | inst_fifo_gen |fifo_generator_v13_2_4_synth | 344| -|4 | \gconvfifo.rf |fifo_generator_top | 344| -|5 | \grf.rf |fifo_generator_ramfifo | 344| -|6 | \gntv_or_sync_fifo.gcx.clkx |clk_x_pntrs | 126| -|7 | wr_pntr_cdc_inst |xpm_cdc_gray__2 | 58| -|8 | rd_pntr_cdc_inst |xpm_cdc_gray | 58| -|9 | \gntv_or_sync_fifo.gl0.rd |rd_logic | 55| -|10 | \gras.rsts |rd_status_flags_as | 14| -|11 | c0 |compare_1 | 6| -|12 | c1 |compare_2 | 5| -|13 | rpntr |rd_bin_cntr | 41| -|14 | \gntv_or_sync_fifo.gl0.wr |wr_logic | 71| -|15 | \gwas.wsts |wr_status_flags_as | 14| -|16 | c1 |compare | 5| -|17 | c2 |compare_0 | 6| -|18 | wpntr |wr_bin_cntr | 57| -|19 | \gntv_or_sync_fifo.mem |memory | 64| -|20 | \gdm.dm_gen.dm |dmem | 64| -|21 | rstblk |reset_blk_ramfifo | 28| -|22 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst |xpm_cdc_async_rst__2 | 2| -|23 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst |xpm_cdc_async_rst | 2| -|24 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd |xpm_cdc_single__2 | 4| -|25 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr |xpm_cdc_single | 4| -+------+-------------------------------------------------------------------------------------+-----------------------------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 1089.344 ; gain = 380.418 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 475 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:00:33 . Memory (MB): peak = 1089.344 ; gain = 347.336 -Synthesis Optimization Complete : Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 1089.344 ; gain = 380.418 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 64 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1102.047 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: - A total of 40 instances were transformed. - (MUXCY,XORCY) => CARRY4: 8 instances - RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 16 instances - RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 16 instances - -INFO: [Common 17-83] Releasing license: Synthesis -30 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:45 . Memory (MB): peak = 1102.047 ; gain = 713.664 -INFO: [Common 17-600] The following parameters have non-default value. -general.maxThreads -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1102.047 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl.dcp' has been generated. -WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP fifo_AntCtrl, cache-ID = a60812ed144d9d97 -INFO: [Coretcl 2-1174] Renamed 24 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1102.047 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file fifo_AntCtrl_utilization_synth.rpt -pb fifo_AntCtrl_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sat Mar 18 23:33:47 2023... diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.v b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.v deleted file mode 100644 index 545c5234..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.v +++ /dev/null @@ -1,6225 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:33:47 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.v -// Design : fifo_AntCtrl -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* CHECK_LICENSE_TYPE = "fifo_AntCtrl,fifo_generator_v13_2_4,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v13_2_4,Vivado 2019.1.3" *) -(* NotValidForBitStream *) -module fifo_AntCtrl - (rst, - wr_clk, - rd_clk, - din, - wr_en, - rd_en, - dout, - full, - empty); - input rst; - (* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME write_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *) input wr_clk; - (* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME read_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *) input rd_clk; - (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [3:0]din; - (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en; - (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en; - (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [3:0]dout; - (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full; - (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty; - - wire [3:0]din; - wire [3:0]dout; - wire empty; - wire full; - wire rd_clk; - wire rd_en; - wire rst; - wire wr_clk; - wire wr_en; - wire NLW_U0_almost_empty_UNCONNECTED; - wire NLW_U0_almost_full_UNCONNECTED; - wire NLW_U0_axi_ar_dbiterr_UNCONNECTED; - wire NLW_U0_axi_ar_overflow_UNCONNECTED; - wire NLW_U0_axi_ar_prog_empty_UNCONNECTED; - wire NLW_U0_axi_ar_prog_full_UNCONNECTED; - wire NLW_U0_axi_ar_sbiterr_UNCONNECTED; - wire NLW_U0_axi_ar_underflow_UNCONNECTED; - wire NLW_U0_axi_aw_dbiterr_UNCONNECTED; - wire NLW_U0_axi_aw_overflow_UNCONNECTED; - wire NLW_U0_axi_aw_prog_empty_UNCONNECTED; - wire NLW_U0_axi_aw_prog_full_UNCONNECTED; - wire NLW_U0_axi_aw_sbiterr_UNCONNECTED; - wire NLW_U0_axi_aw_underflow_UNCONNECTED; - wire NLW_U0_axi_b_dbiterr_UNCONNECTED; - wire NLW_U0_axi_b_overflow_UNCONNECTED; - wire NLW_U0_axi_b_prog_empty_UNCONNECTED; - wire NLW_U0_axi_b_prog_full_UNCONNECTED; - wire NLW_U0_axi_b_sbiterr_UNCONNECTED; - wire NLW_U0_axi_b_underflow_UNCONNECTED; - wire NLW_U0_axi_r_dbiterr_UNCONNECTED; - wire NLW_U0_axi_r_overflow_UNCONNECTED; - wire NLW_U0_axi_r_prog_empty_UNCONNECTED; - wire NLW_U0_axi_r_prog_full_UNCONNECTED; - wire NLW_U0_axi_r_sbiterr_UNCONNECTED; - wire NLW_U0_axi_r_underflow_UNCONNECTED; - wire NLW_U0_axi_w_dbiterr_UNCONNECTED; - wire NLW_U0_axi_w_overflow_UNCONNECTED; - wire NLW_U0_axi_w_prog_empty_UNCONNECTED; - wire NLW_U0_axi_w_prog_full_UNCONNECTED; - wire NLW_U0_axi_w_sbiterr_UNCONNECTED; - wire NLW_U0_axi_w_underflow_UNCONNECTED; - wire NLW_U0_axis_dbiterr_UNCONNECTED; - wire NLW_U0_axis_overflow_UNCONNECTED; - wire NLW_U0_axis_prog_empty_UNCONNECTED; - wire NLW_U0_axis_prog_full_UNCONNECTED; - wire NLW_U0_axis_sbiterr_UNCONNECTED; - wire NLW_U0_axis_underflow_UNCONNECTED; - wire NLW_U0_dbiterr_UNCONNECTED; - wire NLW_U0_m_axi_arvalid_UNCONNECTED; - wire NLW_U0_m_axi_awvalid_UNCONNECTED; - wire NLW_U0_m_axi_bready_UNCONNECTED; - wire NLW_U0_m_axi_rready_UNCONNECTED; - wire NLW_U0_m_axi_wlast_UNCONNECTED; - wire NLW_U0_m_axi_wvalid_UNCONNECTED; - wire NLW_U0_m_axis_tlast_UNCONNECTED; - wire NLW_U0_m_axis_tvalid_UNCONNECTED; - wire NLW_U0_overflow_UNCONNECTED; - wire NLW_U0_prog_empty_UNCONNECTED; - wire NLW_U0_prog_full_UNCONNECTED; - wire NLW_U0_rd_rst_busy_UNCONNECTED; - wire NLW_U0_s_axi_arready_UNCONNECTED; - wire NLW_U0_s_axi_awready_UNCONNECTED; - wire NLW_U0_s_axi_bvalid_UNCONNECTED; - wire NLW_U0_s_axi_rlast_UNCONNECTED; - wire NLW_U0_s_axi_rvalid_UNCONNECTED; - wire NLW_U0_s_axi_wready_UNCONNECTED; - wire NLW_U0_s_axis_tready_UNCONNECTED; - wire NLW_U0_sbiterr_UNCONNECTED; - wire NLW_U0_underflow_UNCONNECTED; - wire NLW_U0_valid_UNCONNECTED; - wire NLW_U0_wr_ack_UNCONNECTED; - wire NLW_U0_wr_rst_busy_UNCONNECTED; - wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED; - wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED; - wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED; - wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED; - wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED; - wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED; - wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED; - wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED; - wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED; - wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED; - wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED; - wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED; - wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED; - wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED; - wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED; - wire [10:0]NLW_U0_axis_data_count_UNCONNECTED; - wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED; - wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED; - wire [9:0]NLW_U0_data_count_UNCONNECTED; - wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED; - wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED; - wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED; - wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED; - wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED; - wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED; - wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED; - wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED; - wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED; - wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED; - wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED; - wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED; - wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED; - wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED; - wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED; - wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED; - wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED; - wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED; - wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED; - wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED; - wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED; - wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED; - wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED; - wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED; - wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED; - wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED; - wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED; - wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED; - wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED; - wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED; - wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED; - wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED; - wire [9:0]NLW_U0_rd_data_count_UNCONNECTED; - wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED; - wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; - wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED; - wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED; - wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED; - wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; - wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED; - wire [9:0]NLW_U0_wr_data_count_UNCONNECTED; - - (* C_ADD_NGC_CONSTRAINT = "0" *) - (* C_APPLICATION_TYPE_AXIS = "0" *) - (* C_APPLICATION_TYPE_RACH = "0" *) - (* C_APPLICATION_TYPE_RDCH = "0" *) - (* C_APPLICATION_TYPE_WACH = "0" *) - (* C_APPLICATION_TYPE_WDCH = "0" *) - (* C_APPLICATION_TYPE_WRCH = "0" *) - (* C_AXIS_TDATA_WIDTH = "8" *) - (* C_AXIS_TDEST_WIDTH = "1" *) - (* C_AXIS_TID_WIDTH = "1" *) - (* C_AXIS_TKEEP_WIDTH = "1" *) - (* C_AXIS_TSTRB_WIDTH = "1" *) - (* C_AXIS_TUSER_WIDTH = "4" *) - (* C_AXIS_TYPE = "0" *) - (* C_AXI_ADDR_WIDTH = "32" *) - (* C_AXI_ARUSER_WIDTH = "1" *) - (* C_AXI_AWUSER_WIDTH = "1" *) - (* C_AXI_BUSER_WIDTH = "1" *) - (* C_AXI_DATA_WIDTH = "64" *) - (* C_AXI_ID_WIDTH = "1" *) - (* C_AXI_LEN_WIDTH = "8" *) - (* C_AXI_LOCK_WIDTH = "1" *) - (* C_AXI_RUSER_WIDTH = "1" *) - (* C_AXI_TYPE = "1" *) - (* C_AXI_WUSER_WIDTH = "1" *) - (* C_COMMON_CLOCK = "0" *) - (* C_COUNT_TYPE = "0" *) - (* C_DATA_COUNT_WIDTH = "10" *) - (* C_DEFAULT_VALUE = "BlankString" *) - (* C_DIN_WIDTH = "4" *) - (* C_DIN_WIDTH_AXIS = "1" *) - (* C_DIN_WIDTH_RACH = "32" *) - (* C_DIN_WIDTH_RDCH = "64" *) - (* C_DIN_WIDTH_WACH = "1" *) - (* C_DIN_WIDTH_WDCH = "64" *) - (* C_DIN_WIDTH_WRCH = "2" *) - (* C_DOUT_RST_VAL = "0" *) - (* C_DOUT_WIDTH = "4" *) - (* C_ENABLE_RLOCS = "0" *) - (* C_ENABLE_RST_SYNC = "1" *) - (* C_EN_SAFETY_CKT = "0" *) - (* C_ERROR_INJECTION_TYPE = "0" *) - (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) - (* C_ERROR_INJECTION_TYPE_RACH = "0" *) - (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) - (* C_ERROR_INJECTION_TYPE_WACH = "0" *) - (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) - (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) - (* C_FAMILY = "kintex7" *) - (* C_FULL_FLAGS_RST_VAL = "1" *) - (* C_HAS_ALMOST_EMPTY = "0" *) - (* C_HAS_ALMOST_FULL = "0" *) - (* C_HAS_AXIS_TDATA = "1" *) - (* C_HAS_AXIS_TDEST = "0" *) - (* C_HAS_AXIS_TID = "0" *) - (* C_HAS_AXIS_TKEEP = "0" *) - (* C_HAS_AXIS_TLAST = "0" *) - (* C_HAS_AXIS_TREADY = "1" *) - (* C_HAS_AXIS_TSTRB = "0" *) - (* C_HAS_AXIS_TUSER = "1" *) - (* C_HAS_AXI_ARUSER = "0" *) - (* C_HAS_AXI_AWUSER = "0" *) - (* C_HAS_AXI_BUSER = "0" *) - (* C_HAS_AXI_ID = "0" *) - (* C_HAS_AXI_RD_CHANNEL = "1" *) - (* C_HAS_AXI_RUSER = "0" *) - (* C_HAS_AXI_WR_CHANNEL = "1" *) - (* C_HAS_AXI_WUSER = "0" *) - (* C_HAS_BACKUP = "0" *) - (* C_HAS_DATA_COUNT = "0" *) - (* C_HAS_DATA_COUNTS_AXIS = "0" *) - (* C_HAS_DATA_COUNTS_RACH = "0" *) - (* C_HAS_DATA_COUNTS_RDCH = "0" *) - (* C_HAS_DATA_COUNTS_WACH = "0" *) - (* C_HAS_DATA_COUNTS_WDCH = "0" *) - (* C_HAS_DATA_COUNTS_WRCH = "0" *) - (* C_HAS_INT_CLK = "0" *) - (* C_HAS_MASTER_CE = "0" *) - (* C_HAS_MEMINIT_FILE = "0" *) - (* C_HAS_OVERFLOW = "0" *) - (* C_HAS_PROG_FLAGS_AXIS = "0" *) - (* C_HAS_PROG_FLAGS_RACH = "0" *) - (* C_HAS_PROG_FLAGS_RDCH = "0" *) - (* C_HAS_PROG_FLAGS_WACH = "0" *) - (* C_HAS_PROG_FLAGS_WDCH = "0" *) - (* C_HAS_PROG_FLAGS_WRCH = "0" *) - (* C_HAS_RD_DATA_COUNT = "0" *) - (* C_HAS_RD_RST = "0" *) - (* C_HAS_RST = "1" *) - (* C_HAS_SLAVE_CE = "0" *) - (* C_HAS_SRST = "0" *) - (* C_HAS_UNDERFLOW = "0" *) - (* C_HAS_VALID = "0" *) - (* C_HAS_WR_ACK = "0" *) - (* C_HAS_WR_DATA_COUNT = "0" *) - (* C_HAS_WR_RST = "0" *) - (* C_IMPLEMENTATION_TYPE = "2" *) - (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) - (* C_IMPLEMENTATION_TYPE_RACH = "1" *) - (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) - (* C_IMPLEMENTATION_TYPE_WACH = "1" *) - (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) - (* C_IMPLEMENTATION_TYPE_WRCH = "1" *) - (* C_INIT_WR_PNTR_VAL = "0" *) - (* C_INTERFACE_TYPE = "0" *) - (* C_MEMORY_TYPE = "2" *) - (* C_MIF_FILE_NAME = "BlankString" *) - (* C_MSGON_VAL = "1" *) - (* C_OPTIMIZATION_MODE = "0" *) - (* C_OVERFLOW_LOW = "0" *) - (* C_POWER_SAVING_MODE = "0" *) - (* C_PRELOAD_LATENCY = "1" *) - (* C_PRELOAD_REGS = "0" *) - (* C_PRIM_FIFO_TYPE = "1kx18" *) - (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) - (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) - (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) - (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) - (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) - (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) - (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) - (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) - (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) - (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) - (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) - (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) - (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) - (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) - (* C_PROG_EMPTY_TYPE = "0" *) - (* C_PROG_EMPTY_TYPE_AXIS = "0" *) - (* C_PROG_EMPTY_TYPE_RACH = "0" *) - (* C_PROG_EMPTY_TYPE_RDCH = "0" *) - (* C_PROG_EMPTY_TYPE_WACH = "0" *) - (* C_PROG_EMPTY_TYPE_WDCH = "0" *) - (* C_PROG_EMPTY_TYPE_WRCH = "0" *) - (* C_PROG_FULL_THRESH_ASSERT_VAL = "1021" *) - (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) - (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) - (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) - (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) - (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) - (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) - (* C_PROG_FULL_THRESH_NEGATE_VAL = "1020" *) - (* C_PROG_FULL_TYPE = "0" *) - (* C_PROG_FULL_TYPE_AXIS = "0" *) - (* C_PROG_FULL_TYPE_RACH = "0" *) - (* C_PROG_FULL_TYPE_RDCH = "0" *) - (* C_PROG_FULL_TYPE_WACH = "0" *) - (* C_PROG_FULL_TYPE_WDCH = "0" *) - (* C_PROG_FULL_TYPE_WRCH = "0" *) - (* C_RACH_TYPE = "0" *) - (* C_RDCH_TYPE = "0" *) - (* C_RD_DATA_COUNT_WIDTH = "10" *) - (* C_RD_DEPTH = "1024" *) - (* C_RD_FREQ = "1" *) - (* C_RD_PNTR_WIDTH = "10" *) - (* C_REG_SLICE_MODE_AXIS = "0" *) - (* C_REG_SLICE_MODE_RACH = "0" *) - (* C_REG_SLICE_MODE_RDCH = "0" *) - (* C_REG_SLICE_MODE_WACH = "0" *) - (* C_REG_SLICE_MODE_WDCH = "0" *) - (* C_REG_SLICE_MODE_WRCH = "0" *) - (* C_SELECT_XPM = "0" *) - (* C_SYNCHRONIZER_STAGE = "2" *) - (* C_UNDERFLOW_LOW = "0" *) - (* C_USE_COMMON_OVERFLOW = "0" *) - (* C_USE_COMMON_UNDERFLOW = "0" *) - (* C_USE_DEFAULT_SETTINGS = "0" *) - (* C_USE_DOUT_RST = "1" *) - (* C_USE_ECC = "0" *) - (* C_USE_ECC_AXIS = "0" *) - (* C_USE_ECC_RACH = "0" *) - (* C_USE_ECC_RDCH = "0" *) - (* C_USE_ECC_WACH = "0" *) - (* C_USE_ECC_WDCH = "0" *) - (* C_USE_ECC_WRCH = "0" *) - (* C_USE_EMBEDDED_REG = "0" *) - (* C_USE_FIFO16_FLAGS = "0" *) - (* C_USE_FWFT_DATA_COUNT = "0" *) - (* C_USE_PIPELINE_REG = "0" *) - (* C_VALID_LOW = "0" *) - (* C_WACH_TYPE = "0" *) - (* C_WDCH_TYPE = "0" *) - (* C_WRCH_TYPE = "0" *) - (* C_WR_ACK_LOW = "0" *) - (* C_WR_DATA_COUNT_WIDTH = "10" *) - (* C_WR_DEPTH = "1024" *) - (* C_WR_DEPTH_AXIS = "1024" *) - (* C_WR_DEPTH_RACH = "16" *) - (* C_WR_DEPTH_RDCH = "1024" *) - (* C_WR_DEPTH_WACH = "16" *) - (* C_WR_DEPTH_WDCH = "1024" *) - (* C_WR_DEPTH_WRCH = "16" *) - (* C_WR_FREQ = "1" *) - (* C_WR_PNTR_WIDTH = "10" *) - (* C_WR_PNTR_WIDTH_AXIS = "10" *) - (* C_WR_PNTR_WIDTH_RACH = "4" *) - (* C_WR_PNTR_WIDTH_RDCH = "10" *) - (* C_WR_PNTR_WIDTH_WACH = "4" *) - (* C_WR_PNTR_WIDTH_WDCH = "10" *) - (* C_WR_PNTR_WIDTH_WRCH = "4" *) - (* C_WR_RESPONSE_LATENCY = "1" *) - fifo_AntCtrl_fifo_generator_v13_2_4 U0 - (.almost_empty(NLW_U0_almost_empty_UNCONNECTED), - .almost_full(NLW_U0_almost_full_UNCONNECTED), - .axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]), - .axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED), - .axi_ar_injectdbiterr(1'b0), - .axi_ar_injectsbiterr(1'b0), - .axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED), - .axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED), - .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), - .axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED), - .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), - .axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]), - .axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED), - .axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED), - .axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]), - .axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]), - .axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED), - .axi_aw_injectdbiterr(1'b0), - .axi_aw_injectsbiterr(1'b0), - .axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED), - .axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED), - .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), - .axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED), - .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), - .axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]), - .axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED), - .axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED), - .axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]), - .axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]), - .axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED), - .axi_b_injectdbiterr(1'b0), - .axi_b_injectsbiterr(1'b0), - .axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED), - .axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED), - .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), - .axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED), - .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), - .axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]), - .axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED), - .axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED), - .axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]), - .axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]), - .axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED), - .axi_r_injectdbiterr(1'b0), - .axi_r_injectsbiterr(1'b0), - .axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED), - .axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED), - .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED), - .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]), - .axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED), - .axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED), - .axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]), - .axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]), - .axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED), - .axi_w_injectdbiterr(1'b0), - .axi_w_injectsbiterr(1'b0), - .axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED), - .axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED), - .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED), - .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]), - .axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED), - .axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED), - .axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]), - .axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]), - .axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED), - .axis_injectdbiterr(1'b0), - .axis_injectsbiterr(1'b0), - .axis_overflow(NLW_U0_axis_overflow_UNCONNECTED), - .axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED), - .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED), - .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]), - .axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED), - .axis_underflow(NLW_U0_axis_underflow_UNCONNECTED), - .axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]), - .backup(1'b0), - .backup_marker(1'b0), - .clk(1'b0), - .data_count(NLW_U0_data_count_UNCONNECTED[9:0]), - .dbiterr(NLW_U0_dbiterr_UNCONNECTED), - .din(din), - .dout(dout), - .empty(empty), - .full(full), - .injectdbiterr(1'b0), - .injectsbiterr(1'b0), - .int_clk(1'b0), - .m_aclk(1'b0), - .m_aclk_en(1'b0), - .m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]), - .m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]), - .m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]), - .m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]), - .m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]), - .m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]), - .m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]), - .m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]), - .m_axi_arready(1'b0), - .m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]), - .m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]), - .m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]), - .m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED), - .m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]), - .m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]), - .m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]), - .m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]), - .m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]), - .m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]), - .m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]), - .m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]), - .m_axi_awready(1'b0), - .m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]), - .m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]), - .m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]), - .m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED), - .m_axi_bid(1'b0), - .m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED), - .m_axi_bresp({1'b0,1'b0}), - .m_axi_buser(1'b0), - .m_axi_bvalid(1'b0), - .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .m_axi_rid(1'b0), - .m_axi_rlast(1'b0), - .m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED), - .m_axi_rresp({1'b0,1'b0}), - .m_axi_ruser(1'b0), - .m_axi_rvalid(1'b0), - .m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]), - .m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]), - .m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED), - .m_axi_wready(1'b0), - .m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]), - .m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]), - .m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED), - .m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]), - .m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]), - .m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]), - .m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]), - .m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED), - .m_axis_tready(1'b0), - .m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]), - .m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]), - .m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED), - .overflow(NLW_U0_overflow_UNCONNECTED), - .prog_empty(NLW_U0_prog_empty_UNCONNECTED), - .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .prog_full(NLW_U0_prog_full_UNCONNECTED), - .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .rd_clk(rd_clk), - .rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[9:0]), - .rd_en(rd_en), - .rd_rst(1'b0), - .rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED), - .rst(rst), - .s_aclk(1'b0), - .s_aclk_en(1'b0), - .s_aresetn(1'b0), - .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_arburst({1'b0,1'b0}), - .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}), - .s_axi_arid(1'b0), - .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_arlock(1'b0), - .s_axi_arprot({1'b0,1'b0,1'b0}), - .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}), - .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED), - .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}), - .s_axi_arsize({1'b0,1'b0,1'b0}), - .s_axi_aruser(1'b0), - .s_axi_arvalid(1'b0), - .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_awburst({1'b0,1'b0}), - .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}), - .s_axi_awid(1'b0), - .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_awlock(1'b0), - .s_axi_awprot({1'b0,1'b0,1'b0}), - .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), - .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED), - .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}), - .s_axi_awsize({1'b0,1'b0,1'b0}), - .s_axi_awuser(1'b0), - .s_axi_awvalid(1'b0), - .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]), - .s_axi_bready(1'b0), - .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]), - .s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]), - .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED), - .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]), - .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]), - .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED), - .s_axi_rready(1'b0), - .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]), - .s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]), - .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED), - .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_wid(1'b0), - .s_axi_wlast(1'b0), - .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED), - .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_wuser(1'b0), - .s_axi_wvalid(1'b0), - .s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axis_tdest(1'b0), - .s_axis_tid(1'b0), - .s_axis_tkeep(1'b0), - .s_axis_tlast(1'b0), - .s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED), - .s_axis_tstrb(1'b0), - .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}), - .s_axis_tvalid(1'b0), - .sbiterr(NLW_U0_sbiterr_UNCONNECTED), - .sleep(1'b0), - .srst(1'b0), - .underflow(NLW_U0_underflow_UNCONNECTED), - .valid(NLW_U0_valid_UNCONNECTED), - .wr_ack(NLW_U0_wr_ack_UNCONNECTED), - .wr_clk(wr_clk), - .wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[9:0]), - .wr_en(wr_en), - .wr_rst(1'b0), - .wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED)); -endmodule - -(* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) -(* INV_DEF_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_cdc_async_rst" *) (* RST_ACTIVE_HIGH = "1" *) -(* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* xpm_cdc = "ASYNC_RST" *) -module fifo_AntCtrl_xpm_cdc_async_rst - (src_arst, - dest_clk, - dest_arst); - input src_arst; - input dest_clk; - output dest_arst; - - (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "ASYNC_RST" *) wire [1:0]arststages_ff; - wire dest_clk; - wire src_arst; - - assign dest_arst = arststages_ff[1]; - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "ASYNC_RST" *) - FDPE #( - .INIT(1'b0)) - \arststages_ff_reg[0] - (.C(dest_clk), - .CE(1'b1), - .D(1'b0), - .PRE(src_arst), - .Q(arststages_ff[0])); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "ASYNC_RST" *) - FDPE #( - .INIT(1'b0)) - \arststages_ff_reg[1] - (.C(dest_clk), - .CE(1'b1), - .D(arststages_ff[0]), - .PRE(src_arst), - .Q(arststages_ff[1])); -endmodule - -(* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) -(* INV_DEF_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_cdc_async_rst" *) (* RST_ACTIVE_HIGH = "1" *) -(* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* xpm_cdc = "ASYNC_RST" *) -module fifo_AntCtrl_xpm_cdc_async_rst__2 - (src_arst, - dest_clk, - dest_arst); - input src_arst; - input dest_clk; - output dest_arst; - - (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "ASYNC_RST" *) wire [1:0]arststages_ff; - wire dest_clk; - wire src_arst; - - assign dest_arst = arststages_ff[1]; - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "ASYNC_RST" *) - FDPE #( - .INIT(1'b0)) - \arststages_ff_reg[0] - (.C(dest_clk), - .CE(1'b1), - .D(1'b0), - .PRE(src_arst), - .Q(arststages_ff[0])); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "ASYNC_RST" *) - FDPE #( - .INIT(1'b0)) - \arststages_ff_reg[1] - (.C(dest_clk), - .CE(1'b1), - .D(arststages_ff[0]), - .PRE(src_arst), - .Q(arststages_ff[1])); -endmodule - -(* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) -(* REG_OUTPUT = "1" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) -(* VERSION = "0" *) (* WIDTH = "10" *) (* XPM_MODULE = "TRUE" *) -(* xpm_cdc = "GRAY" *) -module fifo_AntCtrl_xpm_cdc_gray - (src_clk, - src_in_bin, - dest_clk, - dest_out_bin); - input src_clk; - input [9:0]src_in_bin; - input dest_clk; - output [9:0]dest_out_bin; - - wire [9:0]async_path; - wire [8:0]binval; - wire dest_clk; - (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[0] ; - (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[1] ; - wire [9:0]dest_out_bin; - wire [8:0]gray_enc; - wire src_clk; - wire [9:0]src_in_bin; - - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[0][0] - (.C(dest_clk), - .CE(1'b1), - .D(async_path[0]), - .Q(\dest_graysync_ff[0] [0]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[0][1] - (.C(dest_clk), - .CE(1'b1), - .D(async_path[1]), - .Q(\dest_graysync_ff[0] [1]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[0][2] - (.C(dest_clk), - .CE(1'b1), - .D(async_path[2]), - .Q(\dest_graysync_ff[0] [2]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[0][3] - (.C(dest_clk), - .CE(1'b1), - .D(async_path[3]), - .Q(\dest_graysync_ff[0] [3]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[0][4] - (.C(dest_clk), - .CE(1'b1), - .D(async_path[4]), - .Q(\dest_graysync_ff[0] [4]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[0][5] - (.C(dest_clk), - .CE(1'b1), - .D(async_path[5]), - .Q(\dest_graysync_ff[0] [5]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[0][6] - (.C(dest_clk), - .CE(1'b1), - .D(async_path[6]), - .Q(\dest_graysync_ff[0] [6]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[0][7] - (.C(dest_clk), - .CE(1'b1), - .D(async_path[7]), - .Q(\dest_graysync_ff[0] [7]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[0][8] - (.C(dest_clk), - .CE(1'b1), - .D(async_path[8]), - .Q(\dest_graysync_ff[0] [8]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[0][9] - (.C(dest_clk), - .CE(1'b1), - .D(async_path[9]), - .Q(\dest_graysync_ff[0] [9]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[1][0] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[0] [0]), - .Q(\dest_graysync_ff[1] [0]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[1][1] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[0] [1]), - .Q(\dest_graysync_ff[1] [1]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[1][2] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[0] [2]), - .Q(\dest_graysync_ff[1] [2]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[1][3] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[0] [3]), - .Q(\dest_graysync_ff[1] [3]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[1][4] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[0] [4]), - .Q(\dest_graysync_ff[1] [4]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[1][5] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[0] [5]), - .Q(\dest_graysync_ff[1] [5]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[1][6] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[0] [6]), - .Q(\dest_graysync_ff[1] [6]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[1][7] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[0] [7]), - .Q(\dest_graysync_ff[1] [7]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[1][8] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[0] [8]), - .Q(\dest_graysync_ff[1] [8]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[1][9] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[0] [9]), - .Q(\dest_graysync_ff[1] [9]), - .R(1'b0)); - LUT5 #( - .INIT(32'h96696996)) - \dest_out_bin_ff[0]_i_1 - (.I0(\dest_graysync_ff[1] [0]), - .I1(\dest_graysync_ff[1] [2]), - .I2(binval[4]), - .I3(\dest_graysync_ff[1] [3]), - .I4(\dest_graysync_ff[1] [1]), - .O(binval[0])); - LUT4 #( - .INIT(16'h6996)) - \dest_out_bin_ff[1]_i_1 - (.I0(\dest_graysync_ff[1] [1]), - .I1(\dest_graysync_ff[1] [3]), - .I2(binval[4]), - .I3(\dest_graysync_ff[1] [2]), - .O(binval[1])); - LUT3 #( - .INIT(8'h96)) - \dest_out_bin_ff[2]_i_1 - (.I0(\dest_graysync_ff[1] [2]), - .I1(binval[4]), - .I2(\dest_graysync_ff[1] [3]), - .O(binval[2])); - LUT2 #( - .INIT(4'h6)) - \dest_out_bin_ff[3]_i_1 - (.I0(\dest_graysync_ff[1] [3]), - .I1(binval[4]), - .O(binval[3])); - LUT6 #( - .INIT(64'h6996966996696996)) - \dest_out_bin_ff[4]_i_1 - (.I0(\dest_graysync_ff[1] [4]), - .I1(\dest_graysync_ff[1] [6]), - .I2(\dest_graysync_ff[1] [8]), - .I3(\dest_graysync_ff[1] [9]), - .I4(\dest_graysync_ff[1] [7]), - .I5(\dest_graysync_ff[1] [5]), - .O(binval[4])); - LUT5 #( - .INIT(32'h96696996)) - \dest_out_bin_ff[5]_i_1 - (.I0(\dest_graysync_ff[1] [5]), - .I1(\dest_graysync_ff[1] [7]), - .I2(\dest_graysync_ff[1] [9]), - .I3(\dest_graysync_ff[1] [8]), - .I4(\dest_graysync_ff[1] [6]), - .O(binval[5])); - LUT4 #( - .INIT(16'h6996)) - \dest_out_bin_ff[6]_i_1 - (.I0(\dest_graysync_ff[1] [6]), - .I1(\dest_graysync_ff[1] [8]), - .I2(\dest_graysync_ff[1] [9]), - .I3(\dest_graysync_ff[1] [7]), - .O(binval[6])); - LUT3 #( - .INIT(8'h96)) - \dest_out_bin_ff[7]_i_1 - (.I0(\dest_graysync_ff[1] [7]), - .I1(\dest_graysync_ff[1] [9]), - .I2(\dest_graysync_ff[1] [8]), - .O(binval[7])); - LUT2 #( - .INIT(4'h6)) - \dest_out_bin_ff[8]_i_1 - (.I0(\dest_graysync_ff[1] [8]), - .I1(\dest_graysync_ff[1] [9]), - .O(binval[8])); - FDRE \dest_out_bin_ff_reg[0] - (.C(dest_clk), - .CE(1'b1), - .D(binval[0]), - .Q(dest_out_bin[0]), - .R(1'b0)); - FDRE \dest_out_bin_ff_reg[1] - (.C(dest_clk), - .CE(1'b1), - .D(binval[1]), - .Q(dest_out_bin[1]), - .R(1'b0)); - FDRE \dest_out_bin_ff_reg[2] - (.C(dest_clk), - .CE(1'b1), - .D(binval[2]), - .Q(dest_out_bin[2]), - .R(1'b0)); - FDRE \dest_out_bin_ff_reg[3] - (.C(dest_clk), - .CE(1'b1), - .D(binval[3]), - .Q(dest_out_bin[3]), - .R(1'b0)); - FDRE \dest_out_bin_ff_reg[4] - (.C(dest_clk), - .CE(1'b1), - .D(binval[4]), - .Q(dest_out_bin[4]), - .R(1'b0)); - FDRE \dest_out_bin_ff_reg[5] - (.C(dest_clk), - .CE(1'b1), - .D(binval[5]), - .Q(dest_out_bin[5]), - .R(1'b0)); - FDRE \dest_out_bin_ff_reg[6] - (.C(dest_clk), - .CE(1'b1), - .D(binval[6]), - .Q(dest_out_bin[6]), - .R(1'b0)); - FDRE \dest_out_bin_ff_reg[7] - (.C(dest_clk), - .CE(1'b1), - .D(binval[7]), - .Q(dest_out_bin[7]), - .R(1'b0)); - FDRE \dest_out_bin_ff_reg[8] - (.C(dest_clk), - .CE(1'b1), - .D(binval[8]), - .Q(dest_out_bin[8]), - .R(1'b0)); - FDRE \dest_out_bin_ff_reg[9] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[1] [9]), - .Q(dest_out_bin[9]), - .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT2 #( - .INIT(4'h6)) - \src_gray_ff[0]_i_1 - (.I0(src_in_bin[1]), - .I1(src_in_bin[0]), - .O(gray_enc[0])); - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT2 #( - .INIT(4'h6)) - \src_gray_ff[1]_i_1 - (.I0(src_in_bin[2]), - .I1(src_in_bin[1]), - .O(gray_enc[1])); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT2 #( - .INIT(4'h6)) - \src_gray_ff[2]_i_1 - (.I0(src_in_bin[3]), - .I1(src_in_bin[2]), - .O(gray_enc[2])); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT2 #( - .INIT(4'h6)) - \src_gray_ff[3]_i_1 - (.I0(src_in_bin[4]), - .I1(src_in_bin[3]), - .O(gray_enc[3])); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT2 #( - .INIT(4'h6)) - \src_gray_ff[4]_i_1 - (.I0(src_in_bin[5]), - .I1(src_in_bin[4]), - .O(gray_enc[4])); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT2 #( - .INIT(4'h6)) - \src_gray_ff[5]_i_1 - (.I0(src_in_bin[6]), - .I1(src_in_bin[5]), - .O(gray_enc[5])); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT2 #( - .INIT(4'h6)) - \src_gray_ff[6]_i_1 - (.I0(src_in_bin[7]), - .I1(src_in_bin[6]), - .O(gray_enc[6])); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT2 #( - .INIT(4'h6)) - \src_gray_ff[7]_i_1 - (.I0(src_in_bin[8]), - .I1(src_in_bin[7]), - .O(gray_enc[7])); - LUT2 #( - .INIT(4'h6)) - \src_gray_ff[8]_i_1 - (.I0(src_in_bin[9]), - .I1(src_in_bin[8]), - .O(gray_enc[8])); - FDRE \src_gray_ff_reg[0] - (.C(src_clk), - .CE(1'b1), - .D(gray_enc[0]), - .Q(async_path[0]), - .R(1'b0)); - FDRE \src_gray_ff_reg[1] - (.C(src_clk), - .CE(1'b1), - .D(gray_enc[1]), - .Q(async_path[1]), - .R(1'b0)); - FDRE \src_gray_ff_reg[2] - (.C(src_clk), - .CE(1'b1), - .D(gray_enc[2]), - .Q(async_path[2]), - .R(1'b0)); - FDRE \src_gray_ff_reg[3] - (.C(src_clk), - .CE(1'b1), - .D(gray_enc[3]), - .Q(async_path[3]), - .R(1'b0)); - FDRE \src_gray_ff_reg[4] - (.C(src_clk), - .CE(1'b1), - .D(gray_enc[4]), - .Q(async_path[4]), - .R(1'b0)); - FDRE \src_gray_ff_reg[5] - (.C(src_clk), - .CE(1'b1), - .D(gray_enc[5]), - .Q(async_path[5]), - .R(1'b0)); - FDRE \src_gray_ff_reg[6] - (.C(src_clk), - .CE(1'b1), - .D(gray_enc[6]), - .Q(async_path[6]), - .R(1'b0)); - FDRE \src_gray_ff_reg[7] - (.C(src_clk), - .CE(1'b1), - .D(gray_enc[7]), - .Q(async_path[7]), - .R(1'b0)); - FDRE \src_gray_ff_reg[8] - (.C(src_clk), - .CE(1'b1), - .D(gray_enc[8]), - .Q(async_path[8]), - .R(1'b0)); - FDRE \src_gray_ff_reg[9] - (.C(src_clk), - .CE(1'b1), - .D(src_in_bin[9]), - .Q(async_path[9]), - .R(1'b0)); -endmodule - -(* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) -(* REG_OUTPUT = "1" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) -(* VERSION = "0" *) (* WIDTH = "10" *) (* XPM_MODULE = "TRUE" *) -(* xpm_cdc = "GRAY" *) -module fifo_AntCtrl_xpm_cdc_gray__2 - (src_clk, - src_in_bin, - dest_clk, - dest_out_bin); - input src_clk; - input [9:0]src_in_bin; - input dest_clk; - output [9:0]dest_out_bin; - - wire [9:0]async_path; - wire [8:0]binval; - wire dest_clk; - (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[0] ; - (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[1] ; - wire [9:0]dest_out_bin; - wire [8:0]gray_enc; - wire src_clk; - wire [9:0]src_in_bin; - - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[0][0] - (.C(dest_clk), - .CE(1'b1), - .D(async_path[0]), - .Q(\dest_graysync_ff[0] [0]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[0][1] - (.C(dest_clk), - .CE(1'b1), - .D(async_path[1]), - .Q(\dest_graysync_ff[0] [1]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[0][2] - (.C(dest_clk), - .CE(1'b1), - .D(async_path[2]), - .Q(\dest_graysync_ff[0] [2]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[0][3] - (.C(dest_clk), - .CE(1'b1), - .D(async_path[3]), - .Q(\dest_graysync_ff[0] [3]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[0][4] - (.C(dest_clk), - .CE(1'b1), - .D(async_path[4]), - .Q(\dest_graysync_ff[0] [4]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[0][5] - (.C(dest_clk), - .CE(1'b1), - .D(async_path[5]), - .Q(\dest_graysync_ff[0] [5]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[0][6] - (.C(dest_clk), - .CE(1'b1), - .D(async_path[6]), - .Q(\dest_graysync_ff[0] [6]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[0][7] - (.C(dest_clk), - .CE(1'b1), - .D(async_path[7]), - .Q(\dest_graysync_ff[0] [7]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[0][8] - (.C(dest_clk), - .CE(1'b1), - .D(async_path[8]), - .Q(\dest_graysync_ff[0] [8]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[0][9] - (.C(dest_clk), - .CE(1'b1), - .D(async_path[9]), - .Q(\dest_graysync_ff[0] [9]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[1][0] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[0] [0]), - .Q(\dest_graysync_ff[1] [0]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[1][1] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[0] [1]), - .Q(\dest_graysync_ff[1] [1]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[1][2] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[0] [2]), - .Q(\dest_graysync_ff[1] [2]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[1][3] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[0] [3]), - .Q(\dest_graysync_ff[1] [3]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[1][4] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[0] [4]), - .Q(\dest_graysync_ff[1] [4]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[1][5] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[0] [5]), - .Q(\dest_graysync_ff[1] [5]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[1][6] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[0] [6]), - .Q(\dest_graysync_ff[1] [6]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[1][7] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[0] [7]), - .Q(\dest_graysync_ff[1] [7]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[1][8] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[0] [8]), - .Q(\dest_graysync_ff[1] [8]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "GRAY" *) - FDRE \dest_graysync_ff_reg[1][9] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[0] [9]), - .Q(\dest_graysync_ff[1] [9]), - .R(1'b0)); - LUT5 #( - .INIT(32'h96696996)) - \dest_out_bin_ff[0]_i_1 - (.I0(\dest_graysync_ff[1] [0]), - .I1(\dest_graysync_ff[1] [2]), - .I2(binval[4]), - .I3(\dest_graysync_ff[1] [3]), - .I4(\dest_graysync_ff[1] [1]), - .O(binval[0])); - LUT4 #( - .INIT(16'h6996)) - \dest_out_bin_ff[1]_i_1 - (.I0(\dest_graysync_ff[1] [1]), - .I1(\dest_graysync_ff[1] [3]), - .I2(binval[4]), - .I3(\dest_graysync_ff[1] [2]), - .O(binval[1])); - LUT3 #( - .INIT(8'h96)) - \dest_out_bin_ff[2]_i_1 - (.I0(\dest_graysync_ff[1] [2]), - .I1(binval[4]), - .I2(\dest_graysync_ff[1] [3]), - .O(binval[2])); - LUT2 #( - .INIT(4'h6)) - \dest_out_bin_ff[3]_i_1 - (.I0(\dest_graysync_ff[1] [3]), - .I1(binval[4]), - .O(binval[3])); - LUT6 #( - .INIT(64'h6996966996696996)) - \dest_out_bin_ff[4]_i_1 - (.I0(\dest_graysync_ff[1] [4]), - .I1(\dest_graysync_ff[1] [6]), - .I2(\dest_graysync_ff[1] [8]), - .I3(\dest_graysync_ff[1] [9]), - .I4(\dest_graysync_ff[1] [7]), - .I5(\dest_graysync_ff[1] [5]), - .O(binval[4])); - LUT5 #( - .INIT(32'h96696996)) - \dest_out_bin_ff[5]_i_1 - (.I0(\dest_graysync_ff[1] [5]), - .I1(\dest_graysync_ff[1] [7]), - .I2(\dest_graysync_ff[1] [9]), - .I3(\dest_graysync_ff[1] [8]), - .I4(\dest_graysync_ff[1] [6]), - .O(binval[5])); - LUT4 #( - .INIT(16'h6996)) - \dest_out_bin_ff[6]_i_1 - (.I0(\dest_graysync_ff[1] [6]), - .I1(\dest_graysync_ff[1] [8]), - .I2(\dest_graysync_ff[1] [9]), - .I3(\dest_graysync_ff[1] [7]), - .O(binval[6])); - LUT3 #( - .INIT(8'h96)) - \dest_out_bin_ff[7]_i_1 - (.I0(\dest_graysync_ff[1] [7]), - .I1(\dest_graysync_ff[1] [9]), - .I2(\dest_graysync_ff[1] [8]), - .O(binval[7])); - LUT2 #( - .INIT(4'h6)) - \dest_out_bin_ff[8]_i_1 - (.I0(\dest_graysync_ff[1] [8]), - .I1(\dest_graysync_ff[1] [9]), - .O(binval[8])); - FDRE \dest_out_bin_ff_reg[0] - (.C(dest_clk), - .CE(1'b1), - .D(binval[0]), - .Q(dest_out_bin[0]), - .R(1'b0)); - FDRE \dest_out_bin_ff_reg[1] - (.C(dest_clk), - .CE(1'b1), - .D(binval[1]), - .Q(dest_out_bin[1]), - .R(1'b0)); - FDRE \dest_out_bin_ff_reg[2] - (.C(dest_clk), - .CE(1'b1), - .D(binval[2]), - .Q(dest_out_bin[2]), - .R(1'b0)); - FDRE \dest_out_bin_ff_reg[3] - (.C(dest_clk), - .CE(1'b1), - .D(binval[3]), - .Q(dest_out_bin[3]), - .R(1'b0)); - FDRE \dest_out_bin_ff_reg[4] - (.C(dest_clk), - .CE(1'b1), - .D(binval[4]), - .Q(dest_out_bin[4]), - .R(1'b0)); - FDRE \dest_out_bin_ff_reg[5] - (.C(dest_clk), - .CE(1'b1), - .D(binval[5]), - .Q(dest_out_bin[5]), - .R(1'b0)); - FDRE \dest_out_bin_ff_reg[6] - (.C(dest_clk), - .CE(1'b1), - .D(binval[6]), - .Q(dest_out_bin[6]), - .R(1'b0)); - FDRE \dest_out_bin_ff_reg[7] - (.C(dest_clk), - .CE(1'b1), - .D(binval[7]), - .Q(dest_out_bin[7]), - .R(1'b0)); - FDRE \dest_out_bin_ff_reg[8] - (.C(dest_clk), - .CE(1'b1), - .D(binval[8]), - .Q(dest_out_bin[8]), - .R(1'b0)); - FDRE \dest_out_bin_ff_reg[9] - (.C(dest_clk), - .CE(1'b1), - .D(\dest_graysync_ff[1] [9]), - .Q(dest_out_bin[9]), - .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT2 #( - .INIT(4'h6)) - \src_gray_ff[0]_i_1 - (.I0(src_in_bin[1]), - .I1(src_in_bin[0]), - .O(gray_enc[0])); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT2 #( - .INIT(4'h6)) - \src_gray_ff[1]_i_1 - (.I0(src_in_bin[2]), - .I1(src_in_bin[1]), - .O(gray_enc[1])); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT2 #( - .INIT(4'h6)) - \src_gray_ff[2]_i_1 - (.I0(src_in_bin[3]), - .I1(src_in_bin[2]), - .O(gray_enc[2])); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT2 #( - .INIT(4'h6)) - \src_gray_ff[3]_i_1 - (.I0(src_in_bin[4]), - .I1(src_in_bin[3]), - .O(gray_enc[3])); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT2 #( - .INIT(4'h6)) - \src_gray_ff[4]_i_1 - (.I0(src_in_bin[5]), - .I1(src_in_bin[4]), - .O(gray_enc[4])); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT2 #( - .INIT(4'h6)) - \src_gray_ff[5]_i_1 - (.I0(src_in_bin[6]), - .I1(src_in_bin[5]), - .O(gray_enc[5])); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT2 #( - .INIT(4'h6)) - \src_gray_ff[6]_i_1 - (.I0(src_in_bin[7]), - .I1(src_in_bin[6]), - .O(gray_enc[6])); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT2 #( - .INIT(4'h6)) - \src_gray_ff[7]_i_1 - (.I0(src_in_bin[8]), - .I1(src_in_bin[7]), - .O(gray_enc[7])); - LUT2 #( - .INIT(4'h6)) - \src_gray_ff[8]_i_1 - (.I0(src_in_bin[9]), - .I1(src_in_bin[8]), - .O(gray_enc[8])); - FDRE \src_gray_ff_reg[0] - (.C(src_clk), - .CE(1'b1), - .D(gray_enc[0]), - .Q(async_path[0]), - .R(1'b0)); - FDRE \src_gray_ff_reg[1] - (.C(src_clk), - .CE(1'b1), - .D(gray_enc[1]), - .Q(async_path[1]), - .R(1'b0)); - FDRE \src_gray_ff_reg[2] - (.C(src_clk), - .CE(1'b1), - .D(gray_enc[2]), - .Q(async_path[2]), - .R(1'b0)); - FDRE \src_gray_ff_reg[3] - (.C(src_clk), - .CE(1'b1), - .D(gray_enc[3]), - .Q(async_path[3]), - .R(1'b0)); - FDRE \src_gray_ff_reg[4] - (.C(src_clk), - .CE(1'b1), - .D(gray_enc[4]), - .Q(async_path[4]), - .R(1'b0)); - FDRE \src_gray_ff_reg[5] - (.C(src_clk), - .CE(1'b1), - .D(gray_enc[5]), - .Q(async_path[5]), - .R(1'b0)); - FDRE \src_gray_ff_reg[6] - (.C(src_clk), - .CE(1'b1), - .D(gray_enc[6]), - .Q(async_path[6]), - .R(1'b0)); - FDRE \src_gray_ff_reg[7] - (.C(src_clk), - .CE(1'b1), - .D(gray_enc[7]), - .Q(async_path[7]), - .R(1'b0)); - FDRE \src_gray_ff_reg[8] - (.C(src_clk), - .CE(1'b1), - .D(gray_enc[8]), - .Q(async_path[8]), - .R(1'b0)); - FDRE \src_gray_ff_reg[9] - (.C(src_clk), - .CE(1'b1), - .D(src_in_bin[9]), - .Q(async_path[9]), - .R(1'b0)); -endmodule - -(* DEST_SYNC_FF = "4" *) (* INIT_SYNC_FF = "0" *) (* ORIG_REF_NAME = "xpm_cdc_single" *) -(* SIM_ASSERT_CHK = "0" *) (* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) -(* XPM_MODULE = "TRUE" *) (* xpm_cdc = "SINGLE" *) -module fifo_AntCtrl_xpm_cdc_single - (src_clk, - src_in, - dest_clk, - dest_out); - input src_clk; - input src_in; - input dest_clk; - output dest_out; - - wire dest_clk; - wire src_in; - (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SINGLE" *) wire [3:0]syncstages_ff; - - assign dest_out = syncstages_ff[3]; - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "SINGLE" *) - FDRE \syncstages_ff_reg[0] - (.C(dest_clk), - .CE(1'b1), - .D(src_in), - .Q(syncstages_ff[0]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "SINGLE" *) - FDRE \syncstages_ff_reg[1] - (.C(dest_clk), - .CE(1'b1), - .D(syncstages_ff[0]), - .Q(syncstages_ff[1]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "SINGLE" *) - FDRE \syncstages_ff_reg[2] - (.C(dest_clk), - .CE(1'b1), - .D(syncstages_ff[1]), - .Q(syncstages_ff[2]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "SINGLE" *) - FDRE \syncstages_ff_reg[3] - (.C(dest_clk), - .CE(1'b1), - .D(syncstages_ff[2]), - .Q(syncstages_ff[3]), - .R(1'b0)); -endmodule - -(* DEST_SYNC_FF = "4" *) (* INIT_SYNC_FF = "0" *) (* ORIG_REF_NAME = "xpm_cdc_single" *) -(* SIM_ASSERT_CHK = "0" *) (* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) -(* XPM_MODULE = "TRUE" *) (* xpm_cdc = "SINGLE" *) -module fifo_AntCtrl_xpm_cdc_single__2 - (src_clk, - src_in, - dest_clk, - dest_out); - input src_clk; - input src_in; - input dest_clk; - output dest_out; - - wire dest_clk; - wire src_in; - (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SINGLE" *) wire [3:0]syncstages_ff; - - assign dest_out = syncstages_ff[3]; - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "SINGLE" *) - FDRE \syncstages_ff_reg[0] - (.C(dest_clk), - .CE(1'b1), - .D(src_in), - .Q(syncstages_ff[0]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "SINGLE" *) - FDRE \syncstages_ff_reg[1] - (.C(dest_clk), - .CE(1'b1), - .D(syncstages_ff[0]), - .Q(syncstages_ff[1]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "SINGLE" *) - FDRE \syncstages_ff_reg[2] - (.C(dest_clk), - .CE(1'b1), - .D(syncstages_ff[1]), - .Q(syncstages_ff[2]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "true" *) - (* XPM_CDC = "SINGLE" *) - FDRE \syncstages_ff_reg[3] - (.C(dest_clk), - .CE(1'b1), - .D(syncstages_ff[2]), - .Q(syncstages_ff[3]), - .R(1'b0)); -endmodule - -(* ORIG_REF_NAME = "clk_x_pntrs" *) -module fifo_AntCtrl_clk_x_pntrs - (v1_reg, - v1_reg_0, - WR_PNTR_RD, - Q, - \gmux.gm[4].gms.ms , - wr_clk, - \src_gray_ff_reg[9] , - rd_clk, - \src_gray_ff_reg[9]_0 ); - output [4:0]v1_reg; - output [4:0]v1_reg_0; - output [9:0]WR_PNTR_RD; - input [9:0]Q; - input [9:0]\gmux.gm[4].gms.ms ; - input wr_clk; - input [9:0]\src_gray_ff_reg[9] ; - input rd_clk; - input [9:0]\src_gray_ff_reg[9]_0 ; - - wire [9:0]Q; - wire [9:0]WR_PNTR_RD; - wire [9:0]\gmux.gm[4].gms.ms ; - wire [9:0]p_25_out; - wire rd_clk; - wire [9:0]\src_gray_ff_reg[9] ; - wire [9:0]\src_gray_ff_reg[9]_0 ; - wire [4:0]v1_reg; - wire [4:0]v1_reg_0; - wire wr_clk; - - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[0].gm1.m1_i_1 - (.I0(p_25_out[0]), - .I1(Q[0]), - .I2(p_25_out[1]), - .I3(Q[1]), - .O(v1_reg[0])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[0].gm1.m1_i_1__0 - (.I0(p_25_out[0]), - .I1(\gmux.gm[4].gms.ms [0]), - .I2(p_25_out[1]), - .I3(\gmux.gm[4].gms.ms [1]), - .O(v1_reg_0[0])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[1].gms.ms_i_1 - (.I0(p_25_out[2]), - .I1(Q[2]), - .I2(p_25_out[3]), - .I3(Q[3]), - .O(v1_reg[1])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[1].gms.ms_i_1__0 - (.I0(p_25_out[2]), - .I1(\gmux.gm[4].gms.ms [2]), - .I2(p_25_out[3]), - .I3(\gmux.gm[4].gms.ms [3]), - .O(v1_reg_0[1])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[2].gms.ms_i_1 - (.I0(p_25_out[4]), - .I1(Q[4]), - .I2(p_25_out[5]), - .I3(Q[5]), - .O(v1_reg[2])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[2].gms.ms_i_1__0 - (.I0(p_25_out[4]), - .I1(\gmux.gm[4].gms.ms [4]), - .I2(p_25_out[5]), - .I3(\gmux.gm[4].gms.ms [5]), - .O(v1_reg_0[2])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[3].gms.ms_i_1 - (.I0(p_25_out[6]), - .I1(Q[6]), - .I2(p_25_out[7]), - .I3(Q[7]), - .O(v1_reg[3])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[3].gms.ms_i_1__0 - (.I0(p_25_out[6]), - .I1(\gmux.gm[4].gms.ms [6]), - .I2(p_25_out[7]), - .I3(\gmux.gm[4].gms.ms [7]), - .O(v1_reg_0[3])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[4].gms.ms_i_1 - (.I0(p_25_out[8]), - .I1(Q[8]), - .I2(p_25_out[9]), - .I3(Q[9]), - .O(v1_reg[4])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[4].gms.ms_i_1__0 - (.I0(p_25_out[8]), - .I1(\gmux.gm[4].gms.ms [8]), - .I2(p_25_out[9]), - .I3(\gmux.gm[4].gms.ms [9]), - .O(v1_reg_0[4])); - (* DEST_SYNC_FF = "2" *) - (* INIT_SYNC_FF = "0" *) - (* REG_OUTPUT = "1" *) - (* SIM_ASSERT_CHK = "0" *) - (* SIM_LOSSLESS_GRAY_CHK = "0" *) - (* VERSION = "0" *) - (* WIDTH = "10" *) - (* XPM_CDC = "GRAY" *) - (* XPM_MODULE = "TRUE" *) - fifo_AntCtrl_xpm_cdc_gray rd_pntr_cdc_inst - (.dest_clk(wr_clk), - .dest_out_bin(p_25_out), - .src_clk(rd_clk), - .src_in_bin(\src_gray_ff_reg[9]_0 )); - (* DEST_SYNC_FF = "2" *) - (* INIT_SYNC_FF = "0" *) - (* REG_OUTPUT = "1" *) - (* SIM_ASSERT_CHK = "0" *) - (* SIM_LOSSLESS_GRAY_CHK = "0" *) - (* VERSION = "0" *) - (* WIDTH = "10" *) - (* XPM_CDC = "GRAY" *) - (* XPM_MODULE = "TRUE" *) - fifo_AntCtrl_xpm_cdc_gray__2 wr_pntr_cdc_inst - (.dest_clk(rd_clk), - .dest_out_bin(WR_PNTR_RD), - .src_clk(wr_clk), - .src_in_bin(\src_gray_ff_reg[9] )); -endmodule - -(* ORIG_REF_NAME = "compare" *) -module fifo_AntCtrl_compare - (comp1, - v1_reg); - output comp1; - input [4:0]v1_reg; - - wire carrynet_0; - wire carrynet_1; - wire carrynet_2; - wire carrynet_3; - wire comp1; - wire [4:0]v1_reg; - wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; - wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; - - (* OPT_MODIFIED = "MLO" *) - (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) - (* box_type = "PRIMITIVE" *) - CARRY4 \gmux.gm[0].gm1.m1_CARRY4 - (.CI(1'b0), - .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), - .CYINIT(1'b1), - .DI({1'b0,1'b0,1'b0,1'b0}), - .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), - .S(v1_reg[3:0])); - (* OPT_MODIFIED = "MLO" *) - (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) - (* box_type = "PRIMITIVE" *) - CARRY4 \gmux.gm[4].gms.ms_CARRY4 - (.CI(carrynet_3), - .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}), - .CYINIT(1'b0), - .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}), - .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), - .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]})); -endmodule - -(* ORIG_REF_NAME = "compare" *) -module fifo_AntCtrl_compare_0 - (ram_full_fb_i_reg, - v1_reg_0, - out, - wr_en, - comp1, - ram_full_fb_i_reg_0); - output ram_full_fb_i_reg; - input [4:0]v1_reg_0; - input out; - input wr_en; - input comp1; - input ram_full_fb_i_reg_0; - - wire carrynet_0; - wire carrynet_1; - wire carrynet_2; - wire carrynet_3; - wire comp1; - wire comp2; - wire out; - wire ram_full_fb_i_reg; - wire ram_full_fb_i_reg_0; - wire [4:0]v1_reg_0; - wire wr_en; - wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; - wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; - - (* OPT_MODIFIED = "MLO" *) - (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) - (* box_type = "PRIMITIVE" *) - CARRY4 \gmux.gm[0].gm1.m1_CARRY4 - (.CI(1'b0), - .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), - .CYINIT(1'b1), - .DI({1'b0,1'b0,1'b0,1'b0}), - .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), - .S(v1_reg_0[3:0])); - (* OPT_MODIFIED = "MLO" *) - (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) - (* box_type = "PRIMITIVE" *) - CARRY4 \gmux.gm[4].gms.ms_CARRY4 - (.CI(carrynet_3), - .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp2}), - .CYINIT(1'b0), - .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}), - .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), - .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0[4]})); - LUT5 #( - .INIT(32'h0000FF20)) - ram_full_i_i_1 - (.I0(comp2), - .I1(out), - .I2(wr_en), - .I3(comp1), - .I4(ram_full_fb_i_reg_0), - .O(ram_full_fb_i_reg)); -endmodule - -(* ORIG_REF_NAME = "compare" *) -module fifo_AntCtrl_compare_1 - (rd_en_0, - v1_reg, - rd_en, - out, - comp1); - output rd_en_0; - input [4:0]v1_reg; - input rd_en; - input out; - input comp1; - - wire carrynet_0; - wire carrynet_1; - wire carrynet_2; - wire carrynet_3; - wire comp0; - wire comp1; - wire out; - wire rd_en; - wire rd_en_0; - wire [4:0]v1_reg; - wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; - wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; - - (* OPT_MODIFIED = "MLO" *) - (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) - (* box_type = "PRIMITIVE" *) - CARRY4 \gmux.gm[0].gm1.m1_CARRY4 - (.CI(1'b0), - .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), - .CYINIT(1'b1), - .DI({1'b0,1'b0,1'b0,1'b0}), - .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), - .S(v1_reg[3:0])); - (* OPT_MODIFIED = "MLO" *) - (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) - (* box_type = "PRIMITIVE" *) - CARRY4 \gmux.gm[4].gms.ms_CARRY4 - (.CI(carrynet_3), - .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}), - .CYINIT(1'b0), - .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}), - .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), - .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]})); - LUT4 #( - .INIT(16'hAEAA)) - ram_empty_i_i_1 - (.I0(comp0), - .I1(rd_en), - .I2(out), - .I3(comp1), - .O(rd_en_0)); -endmodule - -(* ORIG_REF_NAME = "compare" *) -module fifo_AntCtrl_compare_2 - (comp1, - v1_reg_0); - output comp1; - input [4:0]v1_reg_0; - - wire carrynet_0; - wire carrynet_1; - wire carrynet_2; - wire carrynet_3; - wire comp1; - wire [4:0]v1_reg_0; - wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; - wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; - - (* OPT_MODIFIED = "MLO" *) - (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) - (* box_type = "PRIMITIVE" *) - CARRY4 \gmux.gm[0].gm1.m1_CARRY4 - (.CI(1'b0), - .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), - .CYINIT(1'b1), - .DI({1'b0,1'b0,1'b0,1'b0}), - .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), - .S(v1_reg_0[3:0])); - (* OPT_MODIFIED = "MLO" *) - (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) - (* box_type = "PRIMITIVE" *) - CARRY4 \gmux.gm[4].gms.ms_CARRY4 - (.CI(carrynet_3), - .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}), - .CYINIT(1'b0), - .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}), - .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), - .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0[4]})); -endmodule - -(* ORIG_REF_NAME = "dmem" *) -module fifo_AntCtrl_dmem - (dout, - wr_clk, - din, - \gpr1.dout_i[2]_i_4_0 , - Q, - \gpr1.dout_i[3]_i_8_0 , - \gpr1.dout_i[2]_i_4_1 , - \gpr1.dout_i[2]_i_4_2 , - \gpr1.dout_i[2]_i_4_3 , - \gpr1.dout_i[2]_i_5_0 , - \gpr1.dout_i[2]_i_5_1 , - \gpr1.dout_i[2]_i_5_2 , - \gpr1.dout_i[2]_i_5_3 , - \gpr1.dout_i[2]_i_6_0 , - \gpr1.dout_i[2]_i_6_1 , - \gpr1.dout_i[2]_i_6_2 , - \gpr1.dout_i[2]_i_6_3 , - \gpr1.dout_i[2]_i_7_0 , - \gpr1.dout_i[2]_i_7_1 , - \gpr1.dout_i[2]_i_7_2 , - \gpr1.dout_i[2]_i_7_3 , - E, - rd_clk, - AR); - output [3:0]dout; - input wr_clk; - input [3:0]din; - input \gpr1.dout_i[2]_i_4_0 ; - input [9:0]Q; - input [5:0]\gpr1.dout_i[3]_i_8_0 ; - input \gpr1.dout_i[2]_i_4_1 ; - input \gpr1.dout_i[2]_i_4_2 ; - input \gpr1.dout_i[2]_i_4_3 ; - input \gpr1.dout_i[2]_i_5_0 ; - input \gpr1.dout_i[2]_i_5_1 ; - input \gpr1.dout_i[2]_i_5_2 ; - input \gpr1.dout_i[2]_i_5_3 ; - input \gpr1.dout_i[2]_i_6_0 ; - input \gpr1.dout_i[2]_i_6_1 ; - input \gpr1.dout_i[2]_i_6_2 ; - input \gpr1.dout_i[2]_i_6_3 ; - input \gpr1.dout_i[2]_i_7_0 ; - input \gpr1.dout_i[2]_i_7_1 ; - input \gpr1.dout_i[2]_i_7_2 ; - input \gpr1.dout_i[2]_i_7_3 ; - input [0:0]E; - input rd_clk; - input [0:0]AR; - - wire [0:0]AR; - wire [0:0]E; - wire [9:0]Q; - wire RAM_reg_0_63_0_2_n_0; - wire RAM_reg_0_63_0_2_n_1; - wire RAM_reg_0_63_0_2_n_2; - wire RAM_reg_0_63_3_3_n_0; - wire RAM_reg_128_191_0_2_n_0; - wire RAM_reg_128_191_0_2_n_1; - wire RAM_reg_128_191_0_2_n_2; - wire RAM_reg_128_191_3_3_n_0; - wire RAM_reg_192_255_0_2_n_0; - wire RAM_reg_192_255_0_2_n_1; - wire RAM_reg_192_255_0_2_n_2; - wire RAM_reg_192_255_3_3_n_0; - wire RAM_reg_256_319_0_2_n_0; - wire RAM_reg_256_319_0_2_n_1; - wire RAM_reg_256_319_0_2_n_2; - wire RAM_reg_256_319_3_3_n_0; - wire RAM_reg_320_383_0_2_n_0; - wire RAM_reg_320_383_0_2_n_1; - wire RAM_reg_320_383_0_2_n_2; - wire RAM_reg_320_383_3_3_n_0; - wire RAM_reg_384_447_0_2_n_0; - wire RAM_reg_384_447_0_2_n_1; - wire RAM_reg_384_447_0_2_n_2; - wire RAM_reg_384_447_3_3_n_0; - wire RAM_reg_448_511_0_2_n_0; - wire RAM_reg_448_511_0_2_n_1; - wire RAM_reg_448_511_0_2_n_2; - wire RAM_reg_448_511_3_3_n_0; - wire RAM_reg_512_575_0_2_n_0; - wire RAM_reg_512_575_0_2_n_1; - wire RAM_reg_512_575_0_2_n_2; - wire RAM_reg_512_575_3_3_n_0; - wire RAM_reg_576_639_0_2_n_0; - wire RAM_reg_576_639_0_2_n_1; - wire RAM_reg_576_639_0_2_n_2; - wire RAM_reg_576_639_3_3_n_0; - wire RAM_reg_640_703_0_2_n_0; - wire RAM_reg_640_703_0_2_n_1; - wire RAM_reg_640_703_0_2_n_2; - wire RAM_reg_640_703_3_3_n_0; - wire RAM_reg_64_127_0_2_n_0; - wire RAM_reg_64_127_0_2_n_1; - wire RAM_reg_64_127_0_2_n_2; - wire RAM_reg_64_127_3_3_n_0; - wire RAM_reg_704_767_0_2_n_0; - wire RAM_reg_704_767_0_2_n_1; - wire RAM_reg_704_767_0_2_n_2; - wire RAM_reg_704_767_3_3_n_0; - wire RAM_reg_768_831_0_2_n_0; - wire RAM_reg_768_831_0_2_n_1; - wire RAM_reg_768_831_0_2_n_2; - wire RAM_reg_768_831_3_3_n_0; - wire RAM_reg_832_895_0_2_n_0; - wire RAM_reg_832_895_0_2_n_1; - wire RAM_reg_832_895_0_2_n_2; - wire RAM_reg_832_895_3_3_n_0; - wire RAM_reg_896_959_0_2_n_0; - wire RAM_reg_896_959_0_2_n_1; - wire RAM_reg_896_959_0_2_n_2; - wire RAM_reg_896_959_3_3_n_0; - wire RAM_reg_960_1023_0_2_n_0; - wire RAM_reg_960_1023_0_2_n_1; - wire RAM_reg_960_1023_0_2_n_2; - wire RAM_reg_960_1023_3_3_n_0; - wire [3:0]din; - wire [3:0]dout; - wire \gpr1.dout_i[0]_i_4_n_0 ; - wire \gpr1.dout_i[0]_i_5_n_0 ; - wire \gpr1.dout_i[0]_i_6_n_0 ; - wire \gpr1.dout_i[0]_i_7_n_0 ; - wire \gpr1.dout_i[1]_i_4_n_0 ; - wire \gpr1.dout_i[1]_i_5_n_0 ; - wire \gpr1.dout_i[1]_i_6_n_0 ; - wire \gpr1.dout_i[1]_i_7_n_0 ; - wire \gpr1.dout_i[2]_i_4_0 ; - wire \gpr1.dout_i[2]_i_4_1 ; - wire \gpr1.dout_i[2]_i_4_2 ; - wire \gpr1.dout_i[2]_i_4_3 ; - wire \gpr1.dout_i[2]_i_4_n_0 ; - wire \gpr1.dout_i[2]_i_5_0 ; - wire \gpr1.dout_i[2]_i_5_1 ; - wire \gpr1.dout_i[2]_i_5_2 ; - wire \gpr1.dout_i[2]_i_5_3 ; - wire \gpr1.dout_i[2]_i_5_n_0 ; - wire \gpr1.dout_i[2]_i_6_0 ; - wire \gpr1.dout_i[2]_i_6_1 ; - wire \gpr1.dout_i[2]_i_6_2 ; - wire \gpr1.dout_i[2]_i_6_3 ; - wire \gpr1.dout_i[2]_i_6_n_0 ; - wire \gpr1.dout_i[2]_i_7_0 ; - wire \gpr1.dout_i[2]_i_7_1 ; - wire \gpr1.dout_i[2]_i_7_2 ; - wire \gpr1.dout_i[2]_i_7_3 ; - wire \gpr1.dout_i[2]_i_7_n_0 ; - wire \gpr1.dout_i[3]_i_5_n_0 ; - wire \gpr1.dout_i[3]_i_6_n_0 ; - wire \gpr1.dout_i[3]_i_7_n_0 ; - wire [5:0]\gpr1.dout_i[3]_i_8_0 ; - wire \gpr1.dout_i[3]_i_8_n_0 ; - wire \gpr1.dout_i_reg[0]_i_2_n_0 ; - wire \gpr1.dout_i_reg[0]_i_3_n_0 ; - wire \gpr1.dout_i_reg[1]_i_2_n_0 ; - wire \gpr1.dout_i_reg[1]_i_3_n_0 ; - wire \gpr1.dout_i_reg[2]_i_2_n_0 ; - wire \gpr1.dout_i_reg[2]_i_3_n_0 ; - wire \gpr1.dout_i_reg[3]_i_3_n_0 ; - wire \gpr1.dout_i_reg[3]_i_4_n_0 ; - wire [3:0]p_0_out; - wire rd_clk; - wire wr_clk; - wire NLW_RAM_reg_0_63_0_2_DOD_UNCONNECTED; - wire NLW_RAM_reg_0_63_3_3_SPO_UNCONNECTED; - wire NLW_RAM_reg_128_191_0_2_DOD_UNCONNECTED; - wire NLW_RAM_reg_128_191_3_3_SPO_UNCONNECTED; - wire NLW_RAM_reg_192_255_0_2_DOD_UNCONNECTED; - wire NLW_RAM_reg_192_255_3_3_SPO_UNCONNECTED; - wire NLW_RAM_reg_256_319_0_2_DOD_UNCONNECTED; - wire NLW_RAM_reg_256_319_3_3_SPO_UNCONNECTED; - wire NLW_RAM_reg_320_383_0_2_DOD_UNCONNECTED; - wire NLW_RAM_reg_320_383_3_3_SPO_UNCONNECTED; - wire NLW_RAM_reg_384_447_0_2_DOD_UNCONNECTED; - wire NLW_RAM_reg_384_447_3_3_SPO_UNCONNECTED; - wire NLW_RAM_reg_448_511_0_2_DOD_UNCONNECTED; - wire NLW_RAM_reg_448_511_3_3_SPO_UNCONNECTED; - wire NLW_RAM_reg_512_575_0_2_DOD_UNCONNECTED; - wire NLW_RAM_reg_512_575_3_3_SPO_UNCONNECTED; - wire NLW_RAM_reg_576_639_0_2_DOD_UNCONNECTED; - wire NLW_RAM_reg_576_639_3_3_SPO_UNCONNECTED; - wire NLW_RAM_reg_640_703_0_2_DOD_UNCONNECTED; - wire NLW_RAM_reg_640_703_3_3_SPO_UNCONNECTED; - wire NLW_RAM_reg_64_127_0_2_DOD_UNCONNECTED; - wire NLW_RAM_reg_64_127_3_3_SPO_UNCONNECTED; - wire NLW_RAM_reg_704_767_0_2_DOD_UNCONNECTED; - wire NLW_RAM_reg_704_767_3_3_SPO_UNCONNECTED; - wire NLW_RAM_reg_768_831_0_2_DOD_UNCONNECTED; - wire NLW_RAM_reg_768_831_3_3_SPO_UNCONNECTED; - wire NLW_RAM_reg_832_895_0_2_DOD_UNCONNECTED; - wire NLW_RAM_reg_832_895_3_3_SPO_UNCONNECTED; - wire NLW_RAM_reg_896_959_0_2_DOD_UNCONNECTED; - wire NLW_RAM_reg_896_959_3_3_SPO_UNCONNECTED; - wire NLW_RAM_reg_960_1023_0_2_DOD_UNCONNECTED; - wire NLW_RAM_reg_960_1023_3_3_SPO_UNCONNECTED; - - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "4096" *) - (* RTL_RAM_NAME = "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM" *) - (* ram_addr_begin = "0" *) - (* ram_addr_end = "63" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "0" *) - (* ram_slice_end = "2" *) - RAM64M RAM_reg_0_63_0_2 - (.ADDRA(Q[5:0]), - .ADDRB(Q[5:0]), - .ADDRC(Q[5:0]), - .ADDRD(\gpr1.dout_i[3]_i_8_0 ), - .DIA(din[0]), - .DIB(din[1]), - .DIC(din[2]), - .DID(1'b0), - .DOA(RAM_reg_0_63_0_2_n_0), - .DOB(RAM_reg_0_63_0_2_n_1), - .DOC(RAM_reg_0_63_0_2_n_2), - .DOD(NLW_RAM_reg_0_63_0_2_DOD_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_4_0 )); - (* ram_addr_begin = "0" *) - (* ram_addr_end = "63" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "3" *) - (* ram_slice_end = "3" *) - RAM64X1D RAM_reg_0_63_3_3 - (.A0(\gpr1.dout_i[3]_i_8_0 [0]), - .A1(\gpr1.dout_i[3]_i_8_0 [1]), - .A2(\gpr1.dout_i[3]_i_8_0 [2]), - .A3(\gpr1.dout_i[3]_i_8_0 [3]), - .A4(\gpr1.dout_i[3]_i_8_0 [4]), - .A5(\gpr1.dout_i[3]_i_8_0 [5]), - .D(din[3]), - .DPO(RAM_reg_0_63_3_3_n_0), - .DPRA0(Q[0]), - .DPRA1(Q[1]), - .DPRA2(Q[2]), - .DPRA3(Q[3]), - .DPRA4(Q[4]), - .DPRA5(Q[5]), - .SPO(NLW_RAM_reg_0_63_3_3_SPO_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_4_0 )); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "4096" *) - (* RTL_RAM_NAME = "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM" *) - (* ram_addr_begin = "128" *) - (* ram_addr_end = "191" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "0" *) - (* ram_slice_end = "2" *) - RAM64M RAM_reg_128_191_0_2 - (.ADDRA(Q[5:0]), - .ADDRB(Q[5:0]), - .ADDRC(Q[5:0]), - .ADDRD(\gpr1.dout_i[3]_i_8_0 ), - .DIA(din[0]), - .DIB(din[1]), - .DIC(din[2]), - .DID(1'b0), - .DOA(RAM_reg_128_191_0_2_n_0), - .DOB(RAM_reg_128_191_0_2_n_1), - .DOC(RAM_reg_128_191_0_2_n_2), - .DOD(NLW_RAM_reg_128_191_0_2_DOD_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_4_2 )); - (* ram_addr_begin = "128" *) - (* ram_addr_end = "191" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "3" *) - (* ram_slice_end = "3" *) - RAM64X1D RAM_reg_128_191_3_3 - (.A0(\gpr1.dout_i[3]_i_8_0 [0]), - .A1(\gpr1.dout_i[3]_i_8_0 [1]), - .A2(\gpr1.dout_i[3]_i_8_0 [2]), - .A3(\gpr1.dout_i[3]_i_8_0 [3]), - .A4(\gpr1.dout_i[3]_i_8_0 [4]), - .A5(\gpr1.dout_i[3]_i_8_0 [5]), - .D(din[3]), - .DPO(RAM_reg_128_191_3_3_n_0), - .DPRA0(Q[0]), - .DPRA1(Q[1]), - .DPRA2(Q[2]), - .DPRA3(Q[3]), - .DPRA4(Q[4]), - .DPRA5(Q[5]), - .SPO(NLW_RAM_reg_128_191_3_3_SPO_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_4_2 )); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "4096" *) - (* RTL_RAM_NAME = "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM" *) - (* ram_addr_begin = "192" *) - (* ram_addr_end = "255" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "0" *) - (* ram_slice_end = "2" *) - RAM64M RAM_reg_192_255_0_2 - (.ADDRA(Q[5:0]), - .ADDRB(Q[5:0]), - .ADDRC(Q[5:0]), - .ADDRD(\gpr1.dout_i[3]_i_8_0 ), - .DIA(din[0]), - .DIB(din[1]), - .DIC(din[2]), - .DID(1'b0), - .DOA(RAM_reg_192_255_0_2_n_0), - .DOB(RAM_reg_192_255_0_2_n_1), - .DOC(RAM_reg_192_255_0_2_n_2), - .DOD(NLW_RAM_reg_192_255_0_2_DOD_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_4_3 )); - (* ram_addr_begin = "192" *) - (* ram_addr_end = "255" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "3" *) - (* ram_slice_end = "3" *) - RAM64X1D RAM_reg_192_255_3_3 - (.A0(\gpr1.dout_i[3]_i_8_0 [0]), - .A1(\gpr1.dout_i[3]_i_8_0 [1]), - .A2(\gpr1.dout_i[3]_i_8_0 [2]), - .A3(\gpr1.dout_i[3]_i_8_0 [3]), - .A4(\gpr1.dout_i[3]_i_8_0 [4]), - .A5(\gpr1.dout_i[3]_i_8_0 [5]), - .D(din[3]), - .DPO(RAM_reg_192_255_3_3_n_0), - .DPRA0(Q[0]), - .DPRA1(Q[1]), - .DPRA2(Q[2]), - .DPRA3(Q[3]), - .DPRA4(Q[4]), - .DPRA5(Q[5]), - .SPO(NLW_RAM_reg_192_255_3_3_SPO_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_4_3 )); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "4096" *) - (* RTL_RAM_NAME = "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM" *) - (* ram_addr_begin = "256" *) - (* ram_addr_end = "319" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "0" *) - (* ram_slice_end = "2" *) - RAM64M RAM_reg_256_319_0_2 - (.ADDRA(Q[5:0]), - .ADDRB(Q[5:0]), - .ADDRC(Q[5:0]), - .ADDRD(\gpr1.dout_i[3]_i_8_0 ), - .DIA(din[0]), - .DIB(din[1]), - .DIC(din[2]), - .DID(1'b0), - .DOA(RAM_reg_256_319_0_2_n_0), - .DOB(RAM_reg_256_319_0_2_n_1), - .DOC(RAM_reg_256_319_0_2_n_2), - .DOD(NLW_RAM_reg_256_319_0_2_DOD_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_5_0 )); - (* ram_addr_begin = "256" *) - (* ram_addr_end = "319" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "3" *) - (* ram_slice_end = "3" *) - RAM64X1D RAM_reg_256_319_3_3 - (.A0(\gpr1.dout_i[3]_i_8_0 [0]), - .A1(\gpr1.dout_i[3]_i_8_0 [1]), - .A2(\gpr1.dout_i[3]_i_8_0 [2]), - .A3(\gpr1.dout_i[3]_i_8_0 [3]), - .A4(\gpr1.dout_i[3]_i_8_0 [4]), - .A5(\gpr1.dout_i[3]_i_8_0 [5]), - .D(din[3]), - .DPO(RAM_reg_256_319_3_3_n_0), - .DPRA0(Q[0]), - .DPRA1(Q[1]), - .DPRA2(Q[2]), - .DPRA3(Q[3]), - .DPRA4(Q[4]), - .DPRA5(Q[5]), - .SPO(NLW_RAM_reg_256_319_3_3_SPO_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_5_0 )); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "4096" *) - (* RTL_RAM_NAME = "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM" *) - (* ram_addr_begin = "320" *) - (* ram_addr_end = "383" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "0" *) - (* ram_slice_end = "2" *) - RAM64M RAM_reg_320_383_0_2 - (.ADDRA(Q[5:0]), - .ADDRB(Q[5:0]), - .ADDRC(Q[5:0]), - .ADDRD(\gpr1.dout_i[3]_i_8_0 ), - .DIA(din[0]), - .DIB(din[1]), - .DIC(din[2]), - .DID(1'b0), - .DOA(RAM_reg_320_383_0_2_n_0), - .DOB(RAM_reg_320_383_0_2_n_1), - .DOC(RAM_reg_320_383_0_2_n_2), - .DOD(NLW_RAM_reg_320_383_0_2_DOD_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_5_1 )); - (* ram_addr_begin = "320" *) - (* ram_addr_end = "383" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "3" *) - (* ram_slice_end = "3" *) - RAM64X1D RAM_reg_320_383_3_3 - (.A0(\gpr1.dout_i[3]_i_8_0 [0]), - .A1(\gpr1.dout_i[3]_i_8_0 [1]), - .A2(\gpr1.dout_i[3]_i_8_0 [2]), - .A3(\gpr1.dout_i[3]_i_8_0 [3]), - .A4(\gpr1.dout_i[3]_i_8_0 [4]), - .A5(\gpr1.dout_i[3]_i_8_0 [5]), - .D(din[3]), - .DPO(RAM_reg_320_383_3_3_n_0), - .DPRA0(Q[0]), - .DPRA1(Q[1]), - .DPRA2(Q[2]), - .DPRA3(Q[3]), - .DPRA4(Q[4]), - .DPRA5(Q[5]), - .SPO(NLW_RAM_reg_320_383_3_3_SPO_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_5_1 )); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "4096" *) - (* RTL_RAM_NAME = "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM" *) - (* ram_addr_begin = "384" *) - (* ram_addr_end = "447" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "0" *) - (* ram_slice_end = "2" *) - RAM64M RAM_reg_384_447_0_2 - (.ADDRA(Q[5:0]), - .ADDRB(Q[5:0]), - .ADDRC(Q[5:0]), - .ADDRD(\gpr1.dout_i[3]_i_8_0 ), - .DIA(din[0]), - .DIB(din[1]), - .DIC(din[2]), - .DID(1'b0), - .DOA(RAM_reg_384_447_0_2_n_0), - .DOB(RAM_reg_384_447_0_2_n_1), - .DOC(RAM_reg_384_447_0_2_n_2), - .DOD(NLW_RAM_reg_384_447_0_2_DOD_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_5_2 )); - (* ram_addr_begin = "384" *) - (* ram_addr_end = "447" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "3" *) - (* ram_slice_end = "3" *) - RAM64X1D RAM_reg_384_447_3_3 - (.A0(\gpr1.dout_i[3]_i_8_0 [0]), - .A1(\gpr1.dout_i[3]_i_8_0 [1]), - .A2(\gpr1.dout_i[3]_i_8_0 [2]), - .A3(\gpr1.dout_i[3]_i_8_0 [3]), - .A4(\gpr1.dout_i[3]_i_8_0 [4]), - .A5(\gpr1.dout_i[3]_i_8_0 [5]), - .D(din[3]), - .DPO(RAM_reg_384_447_3_3_n_0), - .DPRA0(Q[0]), - .DPRA1(Q[1]), - .DPRA2(Q[2]), - .DPRA3(Q[3]), - .DPRA4(Q[4]), - .DPRA5(Q[5]), - .SPO(NLW_RAM_reg_384_447_3_3_SPO_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_5_2 )); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "4096" *) - (* RTL_RAM_NAME = "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM" *) - (* ram_addr_begin = "448" *) - (* ram_addr_end = "511" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "0" *) - (* ram_slice_end = "2" *) - RAM64M RAM_reg_448_511_0_2 - (.ADDRA(Q[5:0]), - .ADDRB(Q[5:0]), - .ADDRC(Q[5:0]), - .ADDRD(\gpr1.dout_i[3]_i_8_0 ), - .DIA(din[0]), - .DIB(din[1]), - .DIC(din[2]), - .DID(1'b0), - .DOA(RAM_reg_448_511_0_2_n_0), - .DOB(RAM_reg_448_511_0_2_n_1), - .DOC(RAM_reg_448_511_0_2_n_2), - .DOD(NLW_RAM_reg_448_511_0_2_DOD_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_5_3 )); - (* ram_addr_begin = "448" *) - (* ram_addr_end = "511" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "3" *) - (* ram_slice_end = "3" *) - RAM64X1D RAM_reg_448_511_3_3 - (.A0(\gpr1.dout_i[3]_i_8_0 [0]), - .A1(\gpr1.dout_i[3]_i_8_0 [1]), - .A2(\gpr1.dout_i[3]_i_8_0 [2]), - .A3(\gpr1.dout_i[3]_i_8_0 [3]), - .A4(\gpr1.dout_i[3]_i_8_0 [4]), - .A5(\gpr1.dout_i[3]_i_8_0 [5]), - .D(din[3]), - .DPO(RAM_reg_448_511_3_3_n_0), - .DPRA0(Q[0]), - .DPRA1(Q[1]), - .DPRA2(Q[2]), - .DPRA3(Q[3]), - .DPRA4(Q[4]), - .DPRA5(Q[5]), - .SPO(NLW_RAM_reg_448_511_3_3_SPO_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_5_3 )); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "4096" *) - (* RTL_RAM_NAME = "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM" *) - (* ram_addr_begin = "512" *) - (* ram_addr_end = "575" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "0" *) - (* ram_slice_end = "2" *) - RAM64M RAM_reg_512_575_0_2 - (.ADDRA(Q[5:0]), - .ADDRB(Q[5:0]), - .ADDRC(Q[5:0]), - .ADDRD(\gpr1.dout_i[3]_i_8_0 ), - .DIA(din[0]), - .DIB(din[1]), - .DIC(din[2]), - .DID(1'b0), - .DOA(RAM_reg_512_575_0_2_n_0), - .DOB(RAM_reg_512_575_0_2_n_1), - .DOC(RAM_reg_512_575_0_2_n_2), - .DOD(NLW_RAM_reg_512_575_0_2_DOD_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_6_0 )); - (* ram_addr_begin = "512" *) - (* ram_addr_end = "575" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "3" *) - (* ram_slice_end = "3" *) - RAM64X1D RAM_reg_512_575_3_3 - (.A0(\gpr1.dout_i[3]_i_8_0 [0]), - .A1(\gpr1.dout_i[3]_i_8_0 [1]), - .A2(\gpr1.dout_i[3]_i_8_0 [2]), - .A3(\gpr1.dout_i[3]_i_8_0 [3]), - .A4(\gpr1.dout_i[3]_i_8_0 [4]), - .A5(\gpr1.dout_i[3]_i_8_0 [5]), - .D(din[3]), - .DPO(RAM_reg_512_575_3_3_n_0), - .DPRA0(Q[0]), - .DPRA1(Q[1]), - .DPRA2(Q[2]), - .DPRA3(Q[3]), - .DPRA4(Q[4]), - .DPRA5(Q[5]), - .SPO(NLW_RAM_reg_512_575_3_3_SPO_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_6_0 )); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "4096" *) - (* RTL_RAM_NAME = "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM" *) - (* ram_addr_begin = "576" *) - (* ram_addr_end = "639" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "0" *) - (* ram_slice_end = "2" *) - RAM64M RAM_reg_576_639_0_2 - (.ADDRA(Q[5:0]), - .ADDRB(Q[5:0]), - .ADDRC(Q[5:0]), - .ADDRD(\gpr1.dout_i[3]_i_8_0 ), - .DIA(din[0]), - .DIB(din[1]), - .DIC(din[2]), - .DID(1'b0), - .DOA(RAM_reg_576_639_0_2_n_0), - .DOB(RAM_reg_576_639_0_2_n_1), - .DOC(RAM_reg_576_639_0_2_n_2), - .DOD(NLW_RAM_reg_576_639_0_2_DOD_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_6_1 )); - (* ram_addr_begin = "576" *) - (* ram_addr_end = "639" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "3" *) - (* ram_slice_end = "3" *) - RAM64X1D RAM_reg_576_639_3_3 - (.A0(\gpr1.dout_i[3]_i_8_0 [0]), - .A1(\gpr1.dout_i[3]_i_8_0 [1]), - .A2(\gpr1.dout_i[3]_i_8_0 [2]), - .A3(\gpr1.dout_i[3]_i_8_0 [3]), - .A4(\gpr1.dout_i[3]_i_8_0 [4]), - .A5(\gpr1.dout_i[3]_i_8_0 [5]), - .D(din[3]), - .DPO(RAM_reg_576_639_3_3_n_0), - .DPRA0(Q[0]), - .DPRA1(Q[1]), - .DPRA2(Q[2]), - .DPRA3(Q[3]), - .DPRA4(Q[4]), - .DPRA5(Q[5]), - .SPO(NLW_RAM_reg_576_639_3_3_SPO_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_6_1 )); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "4096" *) - (* RTL_RAM_NAME = "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM" *) - (* ram_addr_begin = "640" *) - (* ram_addr_end = "703" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "0" *) - (* ram_slice_end = "2" *) - RAM64M RAM_reg_640_703_0_2 - (.ADDRA(Q[5:0]), - .ADDRB(Q[5:0]), - .ADDRC(Q[5:0]), - .ADDRD(\gpr1.dout_i[3]_i_8_0 ), - .DIA(din[0]), - .DIB(din[1]), - .DIC(din[2]), - .DID(1'b0), - .DOA(RAM_reg_640_703_0_2_n_0), - .DOB(RAM_reg_640_703_0_2_n_1), - .DOC(RAM_reg_640_703_0_2_n_2), - .DOD(NLW_RAM_reg_640_703_0_2_DOD_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_6_2 )); - (* ram_addr_begin = "640" *) - (* ram_addr_end = "703" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "3" *) - (* ram_slice_end = "3" *) - RAM64X1D RAM_reg_640_703_3_3 - (.A0(\gpr1.dout_i[3]_i_8_0 [0]), - .A1(\gpr1.dout_i[3]_i_8_0 [1]), - .A2(\gpr1.dout_i[3]_i_8_0 [2]), - .A3(\gpr1.dout_i[3]_i_8_0 [3]), - .A4(\gpr1.dout_i[3]_i_8_0 [4]), - .A5(\gpr1.dout_i[3]_i_8_0 [5]), - .D(din[3]), - .DPO(RAM_reg_640_703_3_3_n_0), - .DPRA0(Q[0]), - .DPRA1(Q[1]), - .DPRA2(Q[2]), - .DPRA3(Q[3]), - .DPRA4(Q[4]), - .DPRA5(Q[5]), - .SPO(NLW_RAM_reg_640_703_3_3_SPO_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_6_2 )); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "4096" *) - (* RTL_RAM_NAME = "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM" *) - (* ram_addr_begin = "64" *) - (* ram_addr_end = "127" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "0" *) - (* ram_slice_end = "2" *) - RAM64M RAM_reg_64_127_0_2 - (.ADDRA(Q[5:0]), - .ADDRB(Q[5:0]), - .ADDRC(Q[5:0]), - .ADDRD(\gpr1.dout_i[3]_i_8_0 ), - .DIA(din[0]), - .DIB(din[1]), - .DIC(din[2]), - .DID(1'b0), - .DOA(RAM_reg_64_127_0_2_n_0), - .DOB(RAM_reg_64_127_0_2_n_1), - .DOC(RAM_reg_64_127_0_2_n_2), - .DOD(NLW_RAM_reg_64_127_0_2_DOD_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_4_1 )); - (* ram_addr_begin = "64" *) - (* ram_addr_end = "127" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "3" *) - (* ram_slice_end = "3" *) - RAM64X1D RAM_reg_64_127_3_3 - (.A0(\gpr1.dout_i[3]_i_8_0 [0]), - .A1(\gpr1.dout_i[3]_i_8_0 [1]), - .A2(\gpr1.dout_i[3]_i_8_0 [2]), - .A3(\gpr1.dout_i[3]_i_8_0 [3]), - .A4(\gpr1.dout_i[3]_i_8_0 [4]), - .A5(\gpr1.dout_i[3]_i_8_0 [5]), - .D(din[3]), - .DPO(RAM_reg_64_127_3_3_n_0), - .DPRA0(Q[0]), - .DPRA1(Q[1]), - .DPRA2(Q[2]), - .DPRA3(Q[3]), - .DPRA4(Q[4]), - .DPRA5(Q[5]), - .SPO(NLW_RAM_reg_64_127_3_3_SPO_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_4_1 )); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "4096" *) - (* RTL_RAM_NAME = "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM" *) - (* ram_addr_begin = "704" *) - (* ram_addr_end = "767" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "0" *) - (* ram_slice_end = "2" *) - RAM64M RAM_reg_704_767_0_2 - (.ADDRA(Q[5:0]), - .ADDRB(Q[5:0]), - .ADDRC(Q[5:0]), - .ADDRD(\gpr1.dout_i[3]_i_8_0 ), - .DIA(din[0]), - .DIB(din[1]), - .DIC(din[2]), - .DID(1'b0), - .DOA(RAM_reg_704_767_0_2_n_0), - .DOB(RAM_reg_704_767_0_2_n_1), - .DOC(RAM_reg_704_767_0_2_n_2), - .DOD(NLW_RAM_reg_704_767_0_2_DOD_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_6_3 )); - (* ram_addr_begin = "704" *) - (* ram_addr_end = "767" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "3" *) - (* ram_slice_end = "3" *) - RAM64X1D RAM_reg_704_767_3_3 - (.A0(\gpr1.dout_i[3]_i_8_0 [0]), - .A1(\gpr1.dout_i[3]_i_8_0 [1]), - .A2(\gpr1.dout_i[3]_i_8_0 [2]), - .A3(\gpr1.dout_i[3]_i_8_0 [3]), - .A4(\gpr1.dout_i[3]_i_8_0 [4]), - .A5(\gpr1.dout_i[3]_i_8_0 [5]), - .D(din[3]), - .DPO(RAM_reg_704_767_3_3_n_0), - .DPRA0(Q[0]), - .DPRA1(Q[1]), - .DPRA2(Q[2]), - .DPRA3(Q[3]), - .DPRA4(Q[4]), - .DPRA5(Q[5]), - .SPO(NLW_RAM_reg_704_767_3_3_SPO_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_6_3 )); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "4096" *) - (* RTL_RAM_NAME = "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM" *) - (* ram_addr_begin = "768" *) - (* ram_addr_end = "831" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "0" *) - (* ram_slice_end = "2" *) - RAM64M RAM_reg_768_831_0_2 - (.ADDRA(Q[5:0]), - .ADDRB(Q[5:0]), - .ADDRC(Q[5:0]), - .ADDRD(\gpr1.dout_i[3]_i_8_0 ), - .DIA(din[0]), - .DIB(din[1]), - .DIC(din[2]), - .DID(1'b0), - .DOA(RAM_reg_768_831_0_2_n_0), - .DOB(RAM_reg_768_831_0_2_n_1), - .DOC(RAM_reg_768_831_0_2_n_2), - .DOD(NLW_RAM_reg_768_831_0_2_DOD_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_7_0 )); - (* ram_addr_begin = "768" *) - (* ram_addr_end = "831" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "3" *) - (* ram_slice_end = "3" *) - RAM64X1D RAM_reg_768_831_3_3 - (.A0(\gpr1.dout_i[3]_i_8_0 [0]), - .A1(\gpr1.dout_i[3]_i_8_0 [1]), - .A2(\gpr1.dout_i[3]_i_8_0 [2]), - .A3(\gpr1.dout_i[3]_i_8_0 [3]), - .A4(\gpr1.dout_i[3]_i_8_0 [4]), - .A5(\gpr1.dout_i[3]_i_8_0 [5]), - .D(din[3]), - .DPO(RAM_reg_768_831_3_3_n_0), - .DPRA0(Q[0]), - .DPRA1(Q[1]), - .DPRA2(Q[2]), - .DPRA3(Q[3]), - .DPRA4(Q[4]), - .DPRA5(Q[5]), - .SPO(NLW_RAM_reg_768_831_3_3_SPO_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_7_0 )); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "4096" *) - (* RTL_RAM_NAME = "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM" *) - (* ram_addr_begin = "832" *) - (* ram_addr_end = "895" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "0" *) - (* ram_slice_end = "2" *) - RAM64M RAM_reg_832_895_0_2 - (.ADDRA(Q[5:0]), - .ADDRB(Q[5:0]), - .ADDRC(Q[5:0]), - .ADDRD(\gpr1.dout_i[3]_i_8_0 ), - .DIA(din[0]), - .DIB(din[1]), - .DIC(din[2]), - .DID(1'b0), - .DOA(RAM_reg_832_895_0_2_n_0), - .DOB(RAM_reg_832_895_0_2_n_1), - .DOC(RAM_reg_832_895_0_2_n_2), - .DOD(NLW_RAM_reg_832_895_0_2_DOD_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_7_1 )); - (* ram_addr_begin = "832" *) - (* ram_addr_end = "895" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "3" *) - (* ram_slice_end = "3" *) - RAM64X1D RAM_reg_832_895_3_3 - (.A0(\gpr1.dout_i[3]_i_8_0 [0]), - .A1(\gpr1.dout_i[3]_i_8_0 [1]), - .A2(\gpr1.dout_i[3]_i_8_0 [2]), - .A3(\gpr1.dout_i[3]_i_8_0 [3]), - .A4(\gpr1.dout_i[3]_i_8_0 [4]), - .A5(\gpr1.dout_i[3]_i_8_0 [5]), - .D(din[3]), - .DPO(RAM_reg_832_895_3_3_n_0), - .DPRA0(Q[0]), - .DPRA1(Q[1]), - .DPRA2(Q[2]), - .DPRA3(Q[3]), - .DPRA4(Q[4]), - .DPRA5(Q[5]), - .SPO(NLW_RAM_reg_832_895_3_3_SPO_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_7_1 )); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "4096" *) - (* RTL_RAM_NAME = "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM" *) - (* ram_addr_begin = "896" *) - (* ram_addr_end = "959" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "0" *) - (* ram_slice_end = "2" *) - RAM64M RAM_reg_896_959_0_2 - (.ADDRA(Q[5:0]), - .ADDRB(Q[5:0]), - .ADDRC(Q[5:0]), - .ADDRD(\gpr1.dout_i[3]_i_8_0 ), - .DIA(din[0]), - .DIB(din[1]), - .DIC(din[2]), - .DID(1'b0), - .DOA(RAM_reg_896_959_0_2_n_0), - .DOB(RAM_reg_896_959_0_2_n_1), - .DOC(RAM_reg_896_959_0_2_n_2), - .DOD(NLW_RAM_reg_896_959_0_2_DOD_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_7_2 )); - (* ram_addr_begin = "896" *) - (* ram_addr_end = "959" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "3" *) - (* ram_slice_end = "3" *) - RAM64X1D RAM_reg_896_959_3_3 - (.A0(\gpr1.dout_i[3]_i_8_0 [0]), - .A1(\gpr1.dout_i[3]_i_8_0 [1]), - .A2(\gpr1.dout_i[3]_i_8_0 [2]), - .A3(\gpr1.dout_i[3]_i_8_0 [3]), - .A4(\gpr1.dout_i[3]_i_8_0 [4]), - .A5(\gpr1.dout_i[3]_i_8_0 [5]), - .D(din[3]), - .DPO(RAM_reg_896_959_3_3_n_0), - .DPRA0(Q[0]), - .DPRA1(Q[1]), - .DPRA2(Q[2]), - .DPRA3(Q[3]), - .DPRA4(Q[4]), - .DPRA5(Q[5]), - .SPO(NLW_RAM_reg_896_959_3_3_SPO_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_7_2 )); - (* METHODOLOGY_DRC_VIOS = "" *) - (* RTL_RAM_BITS = "4096" *) - (* RTL_RAM_NAME = "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM" *) - (* ram_addr_begin = "960" *) - (* ram_addr_end = "1023" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "0" *) - (* ram_slice_end = "2" *) - RAM64M RAM_reg_960_1023_0_2 - (.ADDRA(Q[5:0]), - .ADDRB(Q[5:0]), - .ADDRC(Q[5:0]), - .ADDRD(\gpr1.dout_i[3]_i_8_0 ), - .DIA(din[0]), - .DIB(din[1]), - .DIC(din[2]), - .DID(1'b0), - .DOA(RAM_reg_960_1023_0_2_n_0), - .DOB(RAM_reg_960_1023_0_2_n_1), - .DOC(RAM_reg_960_1023_0_2_n_2), - .DOD(NLW_RAM_reg_960_1023_0_2_DOD_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_7_3 )); - (* ram_addr_begin = "960" *) - (* ram_addr_end = "1023" *) - (* ram_offset = "0" *) - (* ram_slice_begin = "3" *) - (* ram_slice_end = "3" *) - RAM64X1D RAM_reg_960_1023_3_3 - (.A0(\gpr1.dout_i[3]_i_8_0 [0]), - .A1(\gpr1.dout_i[3]_i_8_0 [1]), - .A2(\gpr1.dout_i[3]_i_8_0 [2]), - .A3(\gpr1.dout_i[3]_i_8_0 [3]), - .A4(\gpr1.dout_i[3]_i_8_0 [4]), - .A5(\gpr1.dout_i[3]_i_8_0 [5]), - .D(din[3]), - .DPO(RAM_reg_960_1023_3_3_n_0), - .DPRA0(Q[0]), - .DPRA1(Q[1]), - .DPRA2(Q[2]), - .DPRA3(Q[3]), - .DPRA4(Q[4]), - .DPRA5(Q[5]), - .SPO(NLW_RAM_reg_960_1023_3_3_SPO_UNCONNECTED), - .WCLK(wr_clk), - .WE(\gpr1.dout_i[2]_i_7_3 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \gpr1.dout_i[0]_i_4 - (.I0(RAM_reg_192_255_0_2_n_0), - .I1(RAM_reg_128_191_0_2_n_0), - .I2(Q[7]), - .I3(RAM_reg_64_127_0_2_n_0), - .I4(Q[6]), - .I5(RAM_reg_0_63_0_2_n_0), - .O(\gpr1.dout_i[0]_i_4_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \gpr1.dout_i[0]_i_5 - (.I0(RAM_reg_448_511_0_2_n_0), - .I1(RAM_reg_384_447_0_2_n_0), - .I2(Q[7]), - .I3(RAM_reg_320_383_0_2_n_0), - .I4(Q[6]), - .I5(RAM_reg_256_319_0_2_n_0), - .O(\gpr1.dout_i[0]_i_5_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \gpr1.dout_i[0]_i_6 - (.I0(RAM_reg_704_767_0_2_n_0), - .I1(RAM_reg_640_703_0_2_n_0), - .I2(Q[7]), - .I3(RAM_reg_576_639_0_2_n_0), - .I4(Q[6]), - .I5(RAM_reg_512_575_0_2_n_0), - .O(\gpr1.dout_i[0]_i_6_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \gpr1.dout_i[0]_i_7 - (.I0(RAM_reg_960_1023_0_2_n_0), - .I1(RAM_reg_896_959_0_2_n_0), - .I2(Q[7]), - .I3(RAM_reg_832_895_0_2_n_0), - .I4(Q[6]), - .I5(RAM_reg_768_831_0_2_n_0), - .O(\gpr1.dout_i[0]_i_7_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \gpr1.dout_i[1]_i_4 - (.I0(RAM_reg_192_255_0_2_n_1), - .I1(RAM_reg_128_191_0_2_n_1), - .I2(Q[7]), - .I3(RAM_reg_64_127_0_2_n_1), - .I4(Q[6]), - .I5(RAM_reg_0_63_0_2_n_1), - .O(\gpr1.dout_i[1]_i_4_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \gpr1.dout_i[1]_i_5 - (.I0(RAM_reg_448_511_0_2_n_1), - .I1(RAM_reg_384_447_0_2_n_1), - .I2(Q[7]), - .I3(RAM_reg_320_383_0_2_n_1), - .I4(Q[6]), - .I5(RAM_reg_256_319_0_2_n_1), - .O(\gpr1.dout_i[1]_i_5_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \gpr1.dout_i[1]_i_6 - (.I0(RAM_reg_704_767_0_2_n_1), - .I1(RAM_reg_640_703_0_2_n_1), - .I2(Q[7]), - .I3(RAM_reg_576_639_0_2_n_1), - .I4(Q[6]), - .I5(RAM_reg_512_575_0_2_n_1), - .O(\gpr1.dout_i[1]_i_6_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \gpr1.dout_i[1]_i_7 - (.I0(RAM_reg_960_1023_0_2_n_1), - .I1(RAM_reg_896_959_0_2_n_1), - .I2(Q[7]), - .I3(RAM_reg_832_895_0_2_n_1), - .I4(Q[6]), - .I5(RAM_reg_768_831_0_2_n_1), - .O(\gpr1.dout_i[1]_i_7_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \gpr1.dout_i[2]_i_4 - (.I0(RAM_reg_192_255_0_2_n_2), - .I1(RAM_reg_128_191_0_2_n_2), - .I2(Q[7]), - .I3(RAM_reg_64_127_0_2_n_2), - .I4(Q[6]), - .I5(RAM_reg_0_63_0_2_n_2), - .O(\gpr1.dout_i[2]_i_4_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \gpr1.dout_i[2]_i_5 - (.I0(RAM_reg_448_511_0_2_n_2), - .I1(RAM_reg_384_447_0_2_n_2), - .I2(Q[7]), - .I3(RAM_reg_320_383_0_2_n_2), - .I4(Q[6]), - .I5(RAM_reg_256_319_0_2_n_2), - .O(\gpr1.dout_i[2]_i_5_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \gpr1.dout_i[2]_i_6 - (.I0(RAM_reg_704_767_0_2_n_2), - .I1(RAM_reg_640_703_0_2_n_2), - .I2(Q[7]), - .I3(RAM_reg_576_639_0_2_n_2), - .I4(Q[6]), - .I5(RAM_reg_512_575_0_2_n_2), - .O(\gpr1.dout_i[2]_i_6_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \gpr1.dout_i[2]_i_7 - (.I0(RAM_reg_960_1023_0_2_n_2), - .I1(RAM_reg_896_959_0_2_n_2), - .I2(Q[7]), - .I3(RAM_reg_832_895_0_2_n_2), - .I4(Q[6]), - .I5(RAM_reg_768_831_0_2_n_2), - .O(\gpr1.dout_i[2]_i_7_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \gpr1.dout_i[3]_i_5 - (.I0(RAM_reg_192_255_3_3_n_0), - .I1(RAM_reg_128_191_3_3_n_0), - .I2(Q[7]), - .I3(RAM_reg_64_127_3_3_n_0), - .I4(Q[6]), - .I5(RAM_reg_0_63_3_3_n_0), - .O(\gpr1.dout_i[3]_i_5_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \gpr1.dout_i[3]_i_6 - (.I0(RAM_reg_448_511_3_3_n_0), - .I1(RAM_reg_384_447_3_3_n_0), - .I2(Q[7]), - .I3(RAM_reg_320_383_3_3_n_0), - .I4(Q[6]), - .I5(RAM_reg_256_319_3_3_n_0), - .O(\gpr1.dout_i[3]_i_6_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \gpr1.dout_i[3]_i_7 - (.I0(RAM_reg_704_767_3_3_n_0), - .I1(RAM_reg_640_703_3_3_n_0), - .I2(Q[7]), - .I3(RAM_reg_576_639_3_3_n_0), - .I4(Q[6]), - .I5(RAM_reg_512_575_3_3_n_0), - .O(\gpr1.dout_i[3]_i_7_n_0 )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \gpr1.dout_i[3]_i_8 - (.I0(RAM_reg_960_1023_3_3_n_0), - .I1(RAM_reg_896_959_3_3_n_0), - .I2(Q[7]), - .I3(RAM_reg_832_895_3_3_n_0), - .I4(Q[6]), - .I5(RAM_reg_768_831_3_3_n_0), - .O(\gpr1.dout_i[3]_i_8_n_0 )); - FDCE #( - .INIT(1'b0)) - \gpr1.dout_i_reg[0] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(p_0_out[0]), - .Q(dout[0])); - MUXF8 \gpr1.dout_i_reg[0]_i_1 - (.I0(\gpr1.dout_i_reg[0]_i_2_n_0 ), - .I1(\gpr1.dout_i_reg[0]_i_3_n_0 ), - .O(p_0_out[0]), - .S(Q[9])); - MUXF7 \gpr1.dout_i_reg[0]_i_2 - (.I0(\gpr1.dout_i[0]_i_4_n_0 ), - .I1(\gpr1.dout_i[0]_i_5_n_0 ), - .O(\gpr1.dout_i_reg[0]_i_2_n_0 ), - .S(Q[8])); - MUXF7 \gpr1.dout_i_reg[0]_i_3 - (.I0(\gpr1.dout_i[0]_i_6_n_0 ), - .I1(\gpr1.dout_i[0]_i_7_n_0 ), - .O(\gpr1.dout_i_reg[0]_i_3_n_0 ), - .S(Q[8])); - FDCE #( - .INIT(1'b0)) - \gpr1.dout_i_reg[1] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(p_0_out[1]), - .Q(dout[1])); - MUXF8 \gpr1.dout_i_reg[1]_i_1 - (.I0(\gpr1.dout_i_reg[1]_i_2_n_0 ), - .I1(\gpr1.dout_i_reg[1]_i_3_n_0 ), - .O(p_0_out[1]), - .S(Q[9])); - MUXF7 \gpr1.dout_i_reg[1]_i_2 - (.I0(\gpr1.dout_i[1]_i_4_n_0 ), - .I1(\gpr1.dout_i[1]_i_5_n_0 ), - .O(\gpr1.dout_i_reg[1]_i_2_n_0 ), - .S(Q[8])); - MUXF7 \gpr1.dout_i_reg[1]_i_3 - (.I0(\gpr1.dout_i[1]_i_6_n_0 ), - .I1(\gpr1.dout_i[1]_i_7_n_0 ), - .O(\gpr1.dout_i_reg[1]_i_3_n_0 ), - .S(Q[8])); - FDCE #( - .INIT(1'b0)) - \gpr1.dout_i_reg[2] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(p_0_out[2]), - .Q(dout[2])); - MUXF8 \gpr1.dout_i_reg[2]_i_1 - (.I0(\gpr1.dout_i_reg[2]_i_2_n_0 ), - .I1(\gpr1.dout_i_reg[2]_i_3_n_0 ), - .O(p_0_out[2]), - .S(Q[9])); - MUXF7 \gpr1.dout_i_reg[2]_i_2 - (.I0(\gpr1.dout_i[2]_i_4_n_0 ), - .I1(\gpr1.dout_i[2]_i_5_n_0 ), - .O(\gpr1.dout_i_reg[2]_i_2_n_0 ), - .S(Q[8])); - MUXF7 \gpr1.dout_i_reg[2]_i_3 - (.I0(\gpr1.dout_i[2]_i_6_n_0 ), - .I1(\gpr1.dout_i[2]_i_7_n_0 ), - .O(\gpr1.dout_i_reg[2]_i_3_n_0 ), - .S(Q[8])); - FDCE #( - .INIT(1'b0)) - \gpr1.dout_i_reg[3] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(p_0_out[3]), - .Q(dout[3])); - MUXF8 \gpr1.dout_i_reg[3]_i_2 - (.I0(\gpr1.dout_i_reg[3]_i_3_n_0 ), - .I1(\gpr1.dout_i_reg[3]_i_4_n_0 ), - .O(p_0_out[3]), - .S(Q[9])); - MUXF7 \gpr1.dout_i_reg[3]_i_3 - (.I0(\gpr1.dout_i[3]_i_5_n_0 ), - .I1(\gpr1.dout_i[3]_i_6_n_0 ), - .O(\gpr1.dout_i_reg[3]_i_3_n_0 ), - .S(Q[8])); - MUXF7 \gpr1.dout_i_reg[3]_i_4 - (.I0(\gpr1.dout_i[3]_i_7_n_0 ), - .I1(\gpr1.dout_i[3]_i_8_n_0 ), - .O(\gpr1.dout_i_reg[3]_i_4_n_0 ), - .S(Q[8])); -endmodule - -(* ORIG_REF_NAME = "fifo_generator_ramfifo" *) -module fifo_AntCtrl_fifo_generator_ramfifo - (wr_rst_busy, - AR, - empty, - full, - dout, - rst, - wr_clk, - rd_clk, - din, - wr_en, - rd_en); - output wr_rst_busy; - output [0:0]AR; - output empty; - output full; - output [3:0]dout; - input rst; - input wr_clk; - input rd_clk; - input [3:0]din; - input wr_en; - input rd_en; - - wire [0:0]AR; - wire [3:0]din; - wire [3:0]dout; - wire empty; - wire full; - wire \gntv_or_sync_fifo.gl0.wr_n_1 ; - wire \gntv_or_sync_fifo.gl0.wr_n_12 ; - wire \gntv_or_sync_fifo.gl0.wr_n_13 ; - wire \gntv_or_sync_fifo.gl0.wr_n_14 ; - wire \gntv_or_sync_fifo.gl0.wr_n_15 ; - wire \gntv_or_sync_fifo.gl0.wr_n_16 ; - wire \gntv_or_sync_fifo.gl0.wr_n_17 ; - wire \gntv_or_sync_fifo.gl0.wr_n_18 ; - wire \gntv_or_sync_fifo.gl0.wr_n_19 ; - wire \gntv_or_sync_fifo.gl0.wr_n_20 ; - wire \gntv_or_sync_fifo.gl0.wr_n_21 ; - wire \gntv_or_sync_fifo.gl0.wr_n_22 ; - wire \gntv_or_sync_fifo.gl0.wr_n_23 ; - wire \gntv_or_sync_fifo.gl0.wr_n_24 ; - wire \gntv_or_sync_fifo.gl0.wr_n_25 ; - wire \gntv_or_sync_fifo.gl0.wr_n_26 ; - wire [4:0]\gwas.wsts/c1/v1_reg ; - wire [4:0]\gwas.wsts/c2/v1_reg ; - wire [9:0]p_0_out_0; - wire [9:0]p_13_out; - wire [9:0]p_14_out; - wire [9:0]p_24_out; - wire ram_rd_en_i; - wire rd_clk; - wire rd_en; - wire rst; - wire rst_full_ff_i; - wire rst_full_gen_i; - wire rstblk_n_0; - wire wr_clk; - wire wr_en; - wire [9:0]wr_pntr_plus2; - wire wr_rst_busy; - - fifo_AntCtrl_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx - (.Q(p_14_out), - .WR_PNTR_RD(p_24_out), - .\gmux.gm[4].gms.ms (wr_pntr_plus2), - .rd_clk(rd_clk), - .\src_gray_ff_reg[9] (p_13_out), - .\src_gray_ff_reg[9]_0 (p_0_out_0), - .v1_reg(\gwas.wsts/c1/v1_reg ), - .v1_reg_0(\gwas.wsts/c2/v1_reg ), - .wr_clk(wr_clk)); - fifo_AntCtrl_rd_logic \gntv_or_sync_fifo.gl0.rd - (.AR(AR), - .E(ram_rd_en_i), - .Q(p_0_out_0), - .WR_PNTR_RD(p_24_out), - .empty(empty), - .rd_clk(rd_clk), - .rd_en(rd_en)); - fifo_AntCtrl_wr_logic \gntv_or_sync_fifo.gl0.wr - (.AR(rstblk_n_0), - .Q(p_13_out), - .full(full), - .\gic0.gc0.count_d1_reg[9] (p_14_out), - .\gic0.gc0.count_d2_reg[6] (\gntv_or_sync_fifo.gl0.wr_n_22 ), - .\gic0.gc0.count_d2_reg[7] (\gntv_or_sync_fifo.gl0.wr_n_20 ), - .\gic0.gc0.count_d2_reg[7]_0 (\gntv_or_sync_fifo.gl0.wr_n_26 ), - .\gic0.gc0.count_d2_reg[8] (\gntv_or_sync_fifo.gl0.wr_n_17 ), - .\gic0.gc0.count_d2_reg[8]_0 (\gntv_or_sync_fifo.gl0.wr_n_24 ), - .\gic0.gc0.count_d2_reg[8]_1 (\gntv_or_sync_fifo.gl0.wr_n_25 ), - .\gic0.gc0.count_d2_reg[9] (\gntv_or_sync_fifo.gl0.wr_n_16 ), - .\gic0.gc0.count_d2_reg[9]_0 (\gntv_or_sync_fifo.gl0.wr_n_19 ), - .\gic0.gc0.count_d2_reg[9]_1 (\gntv_or_sync_fifo.gl0.wr_n_21 ), - .\gic0.gc0.count_d2_reg[9]_2 (\gntv_or_sync_fifo.gl0.wr_n_23 ), - .\gic0.gc0.count_reg[9] (wr_pntr_plus2), - .out(rst_full_ff_i), - .ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_1 ), - .ram_full_fb_i_reg_0(\gntv_or_sync_fifo.gl0.wr_n_12 ), - .ram_full_fb_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_13 ), - .ram_full_fb_i_reg_2(\gntv_or_sync_fifo.gl0.wr_n_14 ), - .ram_full_fb_i_reg_3(\gntv_or_sync_fifo.gl0.wr_n_15 ), - .ram_full_fb_i_reg_4(\gntv_or_sync_fifo.gl0.wr_n_18 ), - .ram_full_fb_i_reg_5(rst_full_gen_i), - .v1_reg(\gwas.wsts/c1/v1_reg ), - .v1_reg_0(\gwas.wsts/c2/v1_reg ), - .wr_clk(wr_clk), - .wr_en(wr_en)); - fifo_AntCtrl_memory \gntv_or_sync_fifo.mem - (.AR(AR), - .E(ram_rd_en_i), - .Q(p_0_out_0), - .din(din), - .dout(dout), - .\gpr1.dout_i[2]_i_4 (\gntv_or_sync_fifo.gl0.wr_n_13 ), - .\gpr1.dout_i[2]_i_4_0 (\gntv_or_sync_fifo.gl0.wr_n_14 ), - .\gpr1.dout_i[2]_i_4_1 (\gntv_or_sync_fifo.gl0.wr_n_15 ), - .\gpr1.dout_i[2]_i_4_2 (\gntv_or_sync_fifo.gl0.wr_n_19 ), - .\gpr1.dout_i[2]_i_5 (\gntv_or_sync_fifo.gl0.wr_n_1 ), - .\gpr1.dout_i[2]_i_5_0 (\gntv_or_sync_fifo.gl0.wr_n_21 ), - .\gpr1.dout_i[2]_i_5_1 (\gntv_or_sync_fifo.gl0.wr_n_23 ), - .\gpr1.dout_i[2]_i_5_2 (\gntv_or_sync_fifo.gl0.wr_n_16 ), - .\gpr1.dout_i[2]_i_6 (\gntv_or_sync_fifo.gl0.wr_n_12 ), - .\gpr1.dout_i[2]_i_6_0 (\gntv_or_sync_fifo.gl0.wr_n_24 ), - .\gpr1.dout_i[2]_i_6_1 (\gntv_or_sync_fifo.gl0.wr_n_25 ), - .\gpr1.dout_i[2]_i_6_2 (\gntv_or_sync_fifo.gl0.wr_n_17 ), - .\gpr1.dout_i[2]_i_7 (\gntv_or_sync_fifo.gl0.wr_n_26 ), - .\gpr1.dout_i[2]_i_7_0 (\gntv_or_sync_fifo.gl0.wr_n_20 ), - .\gpr1.dout_i[2]_i_7_1 (\gntv_or_sync_fifo.gl0.wr_n_22 ), - .\gpr1.dout_i[2]_i_7_2 (\gntv_or_sync_fifo.gl0.wr_n_18 ), - .\gpr1.dout_i[3]_i_8 (p_13_out[5:0]), - .rd_clk(rd_clk), - .wr_clk(wr_clk)); - fifo_AntCtrl_reset_blk_ramfifo rstblk - (.AR(rstblk_n_0), - .\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_gen_i), - .\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 (AR), - .out(rst_full_ff_i), - .rd_clk(rd_clk), - .rst(rst), - .wr_clk(wr_clk), - .wr_rst_busy(wr_rst_busy)); -endmodule - -(* ORIG_REF_NAME = "fifo_generator_top" *) -module fifo_AntCtrl_fifo_generator_top - (wr_rst_busy, - AR, - empty, - full, - dout, - rst, - wr_clk, - rd_clk, - din, - wr_en, - rd_en); - output wr_rst_busy; - output [0:0]AR; - output empty; - output full; - output [3:0]dout; - input rst; - input wr_clk; - input rd_clk; - input [3:0]din; - input wr_en; - input rd_en; - - wire [0:0]AR; - wire [3:0]din; - wire [3:0]dout; - wire empty; - wire full; - wire rd_clk; - wire rd_en; - wire rst; - wire wr_clk; - wire wr_en; - wire wr_rst_busy; - - fifo_AntCtrl_fifo_generator_ramfifo \grf.rf - (.AR(AR), - .din(din), - .dout(dout), - .empty(empty), - .full(full), - .rd_clk(rd_clk), - .rd_en(rd_en), - .rst(rst), - .wr_clk(wr_clk), - .wr_en(wr_en), - .wr_rst_busy(wr_rst_busy)); -endmodule - -(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *) -(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *) -(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *) -(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *) -(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *) -(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) -(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *) -(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *) -(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *) -(* C_DATA_COUNT_WIDTH = "10" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "4" *) -(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) -(* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *) -(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "4" *) (* C_ENABLE_RLOCS = "0" *) -(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *) -(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) -(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) -(* C_FAMILY = "kintex7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *) -(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *) -(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *) -(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *) -(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *) -(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *) -(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *) -(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *) -(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) -(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *) -(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *) -(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *) -(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *) -(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *) -(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *) -(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *) -(* C_IMPLEMENTATION_TYPE = "2" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *) -(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) -(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *) -(* C_MEMORY_TYPE = "2" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *) -(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *) -(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "1kx18" *) -(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) -(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) -(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) -(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) -(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *) -(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) -(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) -(* C_PROG_FULL_THRESH_ASSERT_VAL = "1021" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) -(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) -(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "1020" *) (* C_PROG_FULL_TYPE = "0" *) -(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) -(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) -(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "10" *) -(* C_RD_DEPTH = "1024" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "10" *) -(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) -(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) -(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *) -(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *) -(* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *) -(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *) -(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *) -(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *) -(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) -(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "10" *) -(* C_WR_DEPTH = "1024" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) -(* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) -(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "10" *) -(* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) -(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) -(* C_WR_RESPONSE_LATENCY = "1" *) (* ORIG_REF_NAME = "fifo_generator_v13_2_4" *) -module fifo_AntCtrl_fifo_generator_v13_2_4 - (backup, - backup_marker, - clk, - rst, - srst, - wr_clk, - wr_rst, - rd_clk, - rd_rst, - din, - wr_en, - rd_en, - prog_empty_thresh, - prog_empty_thresh_assert, - prog_empty_thresh_negate, - prog_full_thresh, - prog_full_thresh_assert, - prog_full_thresh_negate, - int_clk, - injectdbiterr, - injectsbiterr, - sleep, - dout, - full, - almost_full, - wr_ack, - overflow, - empty, - almost_empty, - valid, - underflow, - data_count, - rd_data_count, - wr_data_count, - prog_full, - prog_empty, - sbiterr, - dbiterr, - wr_rst_busy, - rd_rst_busy, - m_aclk, - s_aclk, - s_aresetn, - m_aclk_en, - s_aclk_en, - s_axi_awid, - s_axi_awaddr, - s_axi_awlen, - s_axi_awsize, - s_axi_awburst, - s_axi_awlock, - s_axi_awcache, - s_axi_awprot, - s_axi_awqos, - s_axi_awregion, - s_axi_awuser, - s_axi_awvalid, - s_axi_awready, - s_axi_wid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wlast, - s_axi_wuser, - s_axi_wvalid, - s_axi_wready, - s_axi_bid, - s_axi_bresp, - s_axi_buser, - s_axi_bvalid, - s_axi_bready, - m_axi_awid, - m_axi_awaddr, - m_axi_awlen, - m_axi_awsize, - m_axi_awburst, - m_axi_awlock, - m_axi_awcache, - m_axi_awprot, - m_axi_awqos, - m_axi_awregion, - m_axi_awuser, - m_axi_awvalid, - m_axi_awready, - m_axi_wid, - m_axi_wdata, - m_axi_wstrb, - m_axi_wlast, - m_axi_wuser, - m_axi_wvalid, - m_axi_wready, - m_axi_bid, - m_axi_bresp, - m_axi_buser, - m_axi_bvalid, - m_axi_bready, - s_axi_arid, - s_axi_araddr, - s_axi_arlen, - s_axi_arsize, - s_axi_arburst, - s_axi_arlock, - s_axi_arcache, - s_axi_arprot, - s_axi_arqos, - s_axi_arregion, - s_axi_aruser, - s_axi_arvalid, - s_axi_arready, - s_axi_rid, - s_axi_rdata, - s_axi_rresp, - s_axi_rlast, - s_axi_ruser, - s_axi_rvalid, - s_axi_rready, - m_axi_arid, - m_axi_araddr, - m_axi_arlen, - m_axi_arsize, - m_axi_arburst, - m_axi_arlock, - m_axi_arcache, - m_axi_arprot, - m_axi_arqos, - m_axi_arregion, - m_axi_aruser, - m_axi_arvalid, - m_axi_arready, - m_axi_rid, - m_axi_rdata, - m_axi_rresp, - m_axi_rlast, - m_axi_ruser, - m_axi_rvalid, - m_axi_rready, - s_axis_tvalid, - s_axis_tready, - s_axis_tdata, - s_axis_tstrb, - s_axis_tkeep, - s_axis_tlast, - s_axis_tid, - s_axis_tdest, - s_axis_tuser, - m_axis_tvalid, - m_axis_tready, - m_axis_tdata, - m_axis_tstrb, - m_axis_tkeep, - m_axis_tlast, - m_axis_tid, - m_axis_tdest, - m_axis_tuser, - axi_aw_injectsbiterr, - axi_aw_injectdbiterr, - axi_aw_prog_full_thresh, - axi_aw_prog_empty_thresh, - axi_aw_data_count, - axi_aw_wr_data_count, - axi_aw_rd_data_count, - axi_aw_sbiterr, - axi_aw_dbiterr, - axi_aw_overflow, - axi_aw_underflow, - axi_aw_prog_full, - axi_aw_prog_empty, - axi_w_injectsbiterr, - axi_w_injectdbiterr, - axi_w_prog_full_thresh, - axi_w_prog_empty_thresh, - axi_w_data_count, - axi_w_wr_data_count, - axi_w_rd_data_count, - axi_w_sbiterr, - axi_w_dbiterr, - axi_w_overflow, - axi_w_underflow, - axi_w_prog_full, - axi_w_prog_empty, - axi_b_injectsbiterr, - axi_b_injectdbiterr, - axi_b_prog_full_thresh, - axi_b_prog_empty_thresh, - axi_b_data_count, - axi_b_wr_data_count, - axi_b_rd_data_count, - axi_b_sbiterr, - axi_b_dbiterr, - axi_b_overflow, - axi_b_underflow, - axi_b_prog_full, - axi_b_prog_empty, - axi_ar_injectsbiterr, - axi_ar_injectdbiterr, - axi_ar_prog_full_thresh, - axi_ar_prog_empty_thresh, - axi_ar_data_count, - axi_ar_wr_data_count, - axi_ar_rd_data_count, - axi_ar_sbiterr, - axi_ar_dbiterr, - axi_ar_overflow, - axi_ar_underflow, - axi_ar_prog_full, - axi_ar_prog_empty, - axi_r_injectsbiterr, - axi_r_injectdbiterr, - axi_r_prog_full_thresh, - axi_r_prog_empty_thresh, - axi_r_data_count, - axi_r_wr_data_count, - axi_r_rd_data_count, - axi_r_sbiterr, - axi_r_dbiterr, - axi_r_overflow, - axi_r_underflow, - axi_r_prog_full, - axi_r_prog_empty, - axis_injectsbiterr, - axis_injectdbiterr, - axis_prog_full_thresh, - axis_prog_empty_thresh, - axis_data_count, - axis_wr_data_count, - axis_rd_data_count, - axis_sbiterr, - axis_dbiterr, - axis_overflow, - axis_underflow, - axis_prog_full, - axis_prog_empty); - input backup; - input backup_marker; - input clk; - input rst; - input srst; - input wr_clk; - input wr_rst; - input rd_clk; - input rd_rst; - input [3:0]din; - input wr_en; - input rd_en; - input [9:0]prog_empty_thresh; - input [9:0]prog_empty_thresh_assert; - input [9:0]prog_empty_thresh_negate; - input [9:0]prog_full_thresh; - input [9:0]prog_full_thresh_assert; - input [9:0]prog_full_thresh_negate; - input int_clk; - input injectdbiterr; - input injectsbiterr; - input sleep; - output [3:0]dout; - output full; - output almost_full; - output wr_ack; - output overflow; - output empty; - output almost_empty; - output valid; - output underflow; - output [9:0]data_count; - output [9:0]rd_data_count; - output [9:0]wr_data_count; - output prog_full; - output prog_empty; - output sbiterr; - output dbiterr; - output wr_rst_busy; - output rd_rst_busy; - input m_aclk; - input s_aclk; - input s_aresetn; - input m_aclk_en; - input s_aclk_en; - input [0:0]s_axi_awid; - input [31:0]s_axi_awaddr; - input [7:0]s_axi_awlen; - input [2:0]s_axi_awsize; - input [1:0]s_axi_awburst; - input [0:0]s_axi_awlock; - input [3:0]s_axi_awcache; - input [2:0]s_axi_awprot; - input [3:0]s_axi_awqos; - input [3:0]s_axi_awregion; - input [0:0]s_axi_awuser; - input s_axi_awvalid; - output s_axi_awready; - input [0:0]s_axi_wid; - input [63:0]s_axi_wdata; - input [7:0]s_axi_wstrb; - input s_axi_wlast; - input [0:0]s_axi_wuser; - input s_axi_wvalid; - output s_axi_wready; - output [0:0]s_axi_bid; - output [1:0]s_axi_bresp; - output [0:0]s_axi_buser; - output s_axi_bvalid; - input s_axi_bready; - output [0:0]m_axi_awid; - output [31:0]m_axi_awaddr; - output [7:0]m_axi_awlen; - output [2:0]m_axi_awsize; - output [1:0]m_axi_awburst; - output [0:0]m_axi_awlock; - output [3:0]m_axi_awcache; - output [2:0]m_axi_awprot; - output [3:0]m_axi_awqos; - output [3:0]m_axi_awregion; - output [0:0]m_axi_awuser; - output m_axi_awvalid; - input m_axi_awready; - output [0:0]m_axi_wid; - output [63:0]m_axi_wdata; - output [7:0]m_axi_wstrb; - output m_axi_wlast; - output [0:0]m_axi_wuser; - output m_axi_wvalid; - input m_axi_wready; - input [0:0]m_axi_bid; - input [1:0]m_axi_bresp; - input [0:0]m_axi_buser; - input m_axi_bvalid; - output m_axi_bready; - input [0:0]s_axi_arid; - input [31:0]s_axi_araddr; - input [7:0]s_axi_arlen; - input [2:0]s_axi_arsize; - input [1:0]s_axi_arburst; - input [0:0]s_axi_arlock; - input [3:0]s_axi_arcache; - input [2:0]s_axi_arprot; - input [3:0]s_axi_arqos; - input [3:0]s_axi_arregion; - input [0:0]s_axi_aruser; - input s_axi_arvalid; - output s_axi_arready; - output [0:0]s_axi_rid; - output [63:0]s_axi_rdata; - output [1:0]s_axi_rresp; - output s_axi_rlast; - output [0:0]s_axi_ruser; - output s_axi_rvalid; - input s_axi_rready; - output [0:0]m_axi_arid; - output [31:0]m_axi_araddr; - output [7:0]m_axi_arlen; - output [2:0]m_axi_arsize; - output [1:0]m_axi_arburst; - output [0:0]m_axi_arlock; - output [3:0]m_axi_arcache; - output [2:0]m_axi_arprot; - output [3:0]m_axi_arqos; - output [3:0]m_axi_arregion; - output [0:0]m_axi_aruser; - output m_axi_arvalid; - input m_axi_arready; - input [0:0]m_axi_rid; - input [63:0]m_axi_rdata; - input [1:0]m_axi_rresp; - input m_axi_rlast; - input [0:0]m_axi_ruser; - input m_axi_rvalid; - output m_axi_rready; - input s_axis_tvalid; - output s_axis_tready; - input [7:0]s_axis_tdata; - input [0:0]s_axis_tstrb; - input [0:0]s_axis_tkeep; - input s_axis_tlast; - input [0:0]s_axis_tid; - input [0:0]s_axis_tdest; - input [3:0]s_axis_tuser; - output m_axis_tvalid; - input m_axis_tready; - output [7:0]m_axis_tdata; - output [0:0]m_axis_tstrb; - output [0:0]m_axis_tkeep; - output m_axis_tlast; - output [0:0]m_axis_tid; - output [0:0]m_axis_tdest; - output [3:0]m_axis_tuser; - input axi_aw_injectsbiterr; - input axi_aw_injectdbiterr; - input [3:0]axi_aw_prog_full_thresh; - input [3:0]axi_aw_prog_empty_thresh; - output [4:0]axi_aw_data_count; - output [4:0]axi_aw_wr_data_count; - output [4:0]axi_aw_rd_data_count; - output axi_aw_sbiterr; - output axi_aw_dbiterr; - output axi_aw_overflow; - output axi_aw_underflow; - output axi_aw_prog_full; - output axi_aw_prog_empty; - input axi_w_injectsbiterr; - input axi_w_injectdbiterr; - input [9:0]axi_w_prog_full_thresh; - input [9:0]axi_w_prog_empty_thresh; - output [10:0]axi_w_data_count; - output [10:0]axi_w_wr_data_count; - output [10:0]axi_w_rd_data_count; - output axi_w_sbiterr; - output axi_w_dbiterr; - output axi_w_overflow; - output axi_w_underflow; - output axi_w_prog_full; - output axi_w_prog_empty; - input axi_b_injectsbiterr; - input axi_b_injectdbiterr; - input [3:0]axi_b_prog_full_thresh; - input [3:0]axi_b_prog_empty_thresh; - output [4:0]axi_b_data_count; - output [4:0]axi_b_wr_data_count; - output [4:0]axi_b_rd_data_count; - output axi_b_sbiterr; - output axi_b_dbiterr; - output axi_b_overflow; - output axi_b_underflow; - output axi_b_prog_full; - output axi_b_prog_empty; - input axi_ar_injectsbiterr; - input axi_ar_injectdbiterr; - input [3:0]axi_ar_prog_full_thresh; - input [3:0]axi_ar_prog_empty_thresh; - output [4:0]axi_ar_data_count; - output [4:0]axi_ar_wr_data_count; - output [4:0]axi_ar_rd_data_count; - output axi_ar_sbiterr; - output axi_ar_dbiterr; - output axi_ar_overflow; - output axi_ar_underflow; - output axi_ar_prog_full; - output axi_ar_prog_empty; - input axi_r_injectsbiterr; - input axi_r_injectdbiterr; - input [9:0]axi_r_prog_full_thresh; - input [9:0]axi_r_prog_empty_thresh; - output [10:0]axi_r_data_count; - output [10:0]axi_r_wr_data_count; - output [10:0]axi_r_rd_data_count; - output axi_r_sbiterr; - output axi_r_dbiterr; - output axi_r_overflow; - output axi_r_underflow; - output axi_r_prog_full; - output axi_r_prog_empty; - input axis_injectsbiterr; - input axis_injectdbiterr; - input [9:0]axis_prog_full_thresh; - input [9:0]axis_prog_empty_thresh; - output [10:0]axis_data_count; - output [10:0]axis_wr_data_count; - output [10:0]axis_rd_data_count; - output axis_sbiterr; - output axis_dbiterr; - output axis_overflow; - output axis_underflow; - output axis_prog_full; - output axis_prog_empty; - - wire \ ; - wire \ ; - wire [3:0]din; - wire [3:0]dout; - wire empty; - wire full; - wire rd_clk; - wire rd_en; - wire rd_rst_busy; - wire rst; - wire wr_clk; - wire wr_en; - wire wr_rst_busy; - - assign almost_empty = \ ; - assign almost_full = \ ; - assign axi_ar_data_count[4] = \ ; - assign axi_ar_data_count[3] = \ ; - assign axi_ar_data_count[2] = \ ; - assign axi_ar_data_count[1] = \ ; - assign axi_ar_data_count[0] = \ ; - assign axi_ar_dbiterr = \ ; - assign axi_ar_overflow = \ ; - assign axi_ar_prog_empty = \ ; - assign axi_ar_prog_full = \ ; - assign axi_ar_rd_data_count[4] = \ ; - assign axi_ar_rd_data_count[3] = \ ; - assign axi_ar_rd_data_count[2] = \ ; - assign axi_ar_rd_data_count[1] = \ ; - assign axi_ar_rd_data_count[0] = \ ; - assign axi_ar_sbiterr = \ ; - assign axi_ar_underflow = \ ; - assign axi_ar_wr_data_count[4] = \ ; - assign axi_ar_wr_data_count[3] = \ ; - assign axi_ar_wr_data_count[2] = \ ; - assign axi_ar_wr_data_count[1] = \ ; - assign axi_ar_wr_data_count[0] = \ ; - assign axi_aw_data_count[4] = \ ; - assign axi_aw_data_count[3] = \ ; - assign axi_aw_data_count[2] = \ ; - assign axi_aw_data_count[1] = \ ; - assign axi_aw_data_count[0] = \ ; - assign axi_aw_dbiterr = \ ; - assign axi_aw_overflow = \ ; - assign axi_aw_prog_empty = \ ; - assign axi_aw_prog_full = \ ; - assign axi_aw_rd_data_count[4] = \ ; - assign axi_aw_rd_data_count[3] = \ ; - assign axi_aw_rd_data_count[2] = \ ; - assign axi_aw_rd_data_count[1] = \ ; - assign axi_aw_rd_data_count[0] = \ ; - assign axi_aw_sbiterr = \ ; - assign axi_aw_underflow = \ ; - assign axi_aw_wr_data_count[4] = \ ; - assign axi_aw_wr_data_count[3] = \ ; - assign axi_aw_wr_data_count[2] = \ ; - assign axi_aw_wr_data_count[1] = \ ; - assign axi_aw_wr_data_count[0] = \ ; - assign axi_b_data_count[4] = \ ; - assign axi_b_data_count[3] = \ ; - assign axi_b_data_count[2] = \ ; - assign axi_b_data_count[1] = \ ; - assign axi_b_data_count[0] = \ ; - assign axi_b_dbiterr = \ ; - assign axi_b_overflow = \ ; - assign axi_b_prog_empty = \ ; - assign axi_b_prog_full = \ ; - assign axi_b_rd_data_count[4] = \ ; - assign axi_b_rd_data_count[3] = \ ; - assign axi_b_rd_data_count[2] = \ ; - assign axi_b_rd_data_count[1] = \ ; - assign axi_b_rd_data_count[0] = \ ; - assign axi_b_sbiterr = \ ; - assign axi_b_underflow = \ ; - assign axi_b_wr_data_count[4] = \ ; - assign axi_b_wr_data_count[3] = \ ; - assign axi_b_wr_data_count[2] = \ ; - assign axi_b_wr_data_count[1] = \ ; - assign axi_b_wr_data_count[0] = \ ; - assign axi_r_data_count[10] = \ ; - assign axi_r_data_count[9] = \ ; - assign axi_r_data_count[8] = \ ; - assign axi_r_data_count[7] = \ ; - assign axi_r_data_count[6] = \ ; - assign axi_r_data_count[5] = \ ; - assign axi_r_data_count[4] = \ ; - assign axi_r_data_count[3] = \ ; - assign axi_r_data_count[2] = \ ; - assign axi_r_data_count[1] = \ ; - assign axi_r_data_count[0] = \ ; - assign axi_r_dbiterr = \ ; - assign axi_r_overflow = \ ; - assign axi_r_prog_empty = \ ; - assign axi_r_prog_full = \ ; - assign axi_r_rd_data_count[10] = \ ; - assign axi_r_rd_data_count[9] = \ ; - assign axi_r_rd_data_count[8] = \ ; - assign axi_r_rd_data_count[7] = \ ; - assign axi_r_rd_data_count[6] = \ ; - assign axi_r_rd_data_count[5] = \ ; - assign axi_r_rd_data_count[4] = \ ; - assign axi_r_rd_data_count[3] = \ ; - assign axi_r_rd_data_count[2] = \ ; - assign axi_r_rd_data_count[1] = \ ; - assign axi_r_rd_data_count[0] = \ ; - assign axi_r_sbiterr = \ ; - assign axi_r_underflow = \ ; - assign axi_r_wr_data_count[10] = \ ; - assign axi_r_wr_data_count[9] = \ ; - assign axi_r_wr_data_count[8] = \ ; - assign axi_r_wr_data_count[7] = \ ; - assign axi_r_wr_data_count[6] = \ ; - assign axi_r_wr_data_count[5] = \ ; - assign axi_r_wr_data_count[4] = \ ; - assign axi_r_wr_data_count[3] = \ ; - assign axi_r_wr_data_count[2] = \ ; - assign axi_r_wr_data_count[1] = \ ; - assign axi_r_wr_data_count[0] = \ ; - assign axi_w_data_count[10] = \ ; - assign axi_w_data_count[9] = \ ; - assign axi_w_data_count[8] = \ ; - assign axi_w_data_count[7] = \ ; - assign axi_w_data_count[6] = \ ; - assign axi_w_data_count[5] = \ ; - assign axi_w_data_count[4] = \ ; - assign axi_w_data_count[3] = \ ; - assign axi_w_data_count[2] = \ ; - assign axi_w_data_count[1] = \ ; - assign axi_w_data_count[0] = \ ; - assign axi_w_dbiterr = \ ; - assign axi_w_overflow = \ ; - assign axi_w_prog_empty = \ ; - assign axi_w_prog_full = \ ; - assign axi_w_rd_data_count[10] = \ ; - assign axi_w_rd_data_count[9] = \ ; - assign axi_w_rd_data_count[8] = \ ; - assign axi_w_rd_data_count[7] = \ ; - assign axi_w_rd_data_count[6] = \ ; - assign axi_w_rd_data_count[5] = \ ; - assign axi_w_rd_data_count[4] = \ ; - assign axi_w_rd_data_count[3] = \ ; - assign axi_w_rd_data_count[2] = \ ; - assign axi_w_rd_data_count[1] = \ ; - assign axi_w_rd_data_count[0] = \ ; - assign axi_w_sbiterr = \ ; - assign axi_w_underflow = \ ; - assign axi_w_wr_data_count[10] = \ ; - assign axi_w_wr_data_count[9] = \ ; - assign axi_w_wr_data_count[8] = \ ; - assign axi_w_wr_data_count[7] = \ ; - assign axi_w_wr_data_count[6] = \ ; - assign axi_w_wr_data_count[5] = \ ; - assign axi_w_wr_data_count[4] = \ ; - assign axi_w_wr_data_count[3] = \ ; - assign axi_w_wr_data_count[2] = \ ; - assign axi_w_wr_data_count[1] = \ ; - assign axi_w_wr_data_count[0] = \ ; - assign axis_data_count[10] = \ ; - assign axis_data_count[9] = \ ; - assign axis_data_count[8] = \ ; - assign axis_data_count[7] = \ ; - assign axis_data_count[6] = \ ; - assign axis_data_count[5] = \ ; - assign axis_data_count[4] = \ ; - assign axis_data_count[3] = \ ; - assign axis_data_count[2] = \ ; - assign axis_data_count[1] = \ ; - assign axis_data_count[0] = \ ; - assign axis_dbiterr = \ ; - assign axis_overflow = \ ; - assign axis_prog_empty = \ ; - assign axis_prog_full = \ ; - assign axis_rd_data_count[10] = \ ; - assign axis_rd_data_count[9] = \ ; - assign axis_rd_data_count[8] = \ ; - assign axis_rd_data_count[7] = \ ; - assign axis_rd_data_count[6] = \ ; - assign axis_rd_data_count[5] = \ ; - assign axis_rd_data_count[4] = \ ; - assign axis_rd_data_count[3] = \ ; - assign axis_rd_data_count[2] = \ ; - assign axis_rd_data_count[1] = \ ; - assign axis_rd_data_count[0] = \ ; - assign axis_sbiterr = \ ; - assign axis_underflow = \ ; - assign axis_wr_data_count[10] = \ ; - assign axis_wr_data_count[9] = \ ; - assign axis_wr_data_count[8] = \ ; - assign axis_wr_data_count[7] = \ ; - assign axis_wr_data_count[6] = \ ; - assign axis_wr_data_count[5] = \ ; - assign axis_wr_data_count[4] = \ ; - assign axis_wr_data_count[3] = \ ; - assign axis_wr_data_count[2] = \ ; - assign axis_wr_data_count[1] = \ ; - assign axis_wr_data_count[0] = \ ; - assign data_count[9] = \ ; - assign data_count[8] = \ ; - assign data_count[7] = \ ; - assign data_count[6] = \ ; - assign data_count[5] = \ ; - assign data_count[4] = \ ; - assign data_count[3] = \ ; - assign data_count[2] = \ ; - assign data_count[1] = \ ; - assign data_count[0] = \ ; - assign dbiterr = \ ; - assign m_axi_araddr[31] = \ ; - assign m_axi_araddr[30] = \ ; - assign m_axi_araddr[29] = \ ; - assign m_axi_araddr[28] = \ ; - assign m_axi_araddr[27] = \ ; - assign m_axi_araddr[26] = \ ; - assign m_axi_araddr[25] = \ ; - assign m_axi_araddr[24] = \ ; - assign m_axi_araddr[23] = \ ; - assign m_axi_araddr[22] = \ ; - assign m_axi_araddr[21] = \ ; - assign m_axi_araddr[20] = \ ; - assign m_axi_araddr[19] = \ ; - assign m_axi_araddr[18] = \ ; - assign m_axi_araddr[17] = \ ; - assign m_axi_araddr[16] = \ ; - assign m_axi_araddr[15] = \ ; - assign m_axi_araddr[14] = \ ; - assign m_axi_araddr[13] = \ ; - assign m_axi_araddr[12] = \ ; - assign m_axi_araddr[11] = \ ; - assign m_axi_araddr[10] = \ ; - assign m_axi_araddr[9] = \ ; - assign m_axi_araddr[8] = \ ; - assign m_axi_araddr[7] = \ ; - assign m_axi_araddr[6] = \ ; - assign m_axi_araddr[5] = \ ; - assign m_axi_araddr[4] = \ ; - assign m_axi_araddr[3] = \ ; - assign m_axi_araddr[2] = \ ; - assign m_axi_araddr[1] = \ ; - assign m_axi_araddr[0] = \ ; - assign m_axi_arburst[1] = \ ; - assign m_axi_arburst[0] = \ ; - assign m_axi_arcache[3] = \ ; - assign m_axi_arcache[2] = \ ; - assign m_axi_arcache[1] = \ ; - assign m_axi_arcache[0] = \ ; - assign m_axi_arid[0] = \ ; - assign m_axi_arlen[7] = \ ; - assign m_axi_arlen[6] = \ ; - assign m_axi_arlen[5] = \ ; - assign m_axi_arlen[4] = \ ; - assign m_axi_arlen[3] = \ ; - assign m_axi_arlen[2] = \ ; - assign m_axi_arlen[1] = \ ; - assign m_axi_arlen[0] = \ ; - assign m_axi_arlock[0] = \ ; - assign m_axi_arprot[2] = \ ; - assign m_axi_arprot[1] = \ ; - assign m_axi_arprot[0] = \ ; - assign m_axi_arqos[3] = \ ; - assign m_axi_arqos[2] = \ ; - assign m_axi_arqos[1] = \ ; - assign m_axi_arqos[0] = \ ; - assign m_axi_arregion[3] = \ ; - assign m_axi_arregion[2] = \ ; - assign m_axi_arregion[1] = \ ; - assign m_axi_arregion[0] = \ ; - assign m_axi_arsize[2] = \ ; - assign m_axi_arsize[1] = \ ; - assign m_axi_arsize[0] = \ ; - assign m_axi_aruser[0] = \ ; - assign m_axi_arvalid = \ ; - assign m_axi_awaddr[31] = \ ; - assign m_axi_awaddr[30] = \ ; - assign m_axi_awaddr[29] = \ ; - assign m_axi_awaddr[28] = \ ; - assign m_axi_awaddr[27] = \ ; - assign m_axi_awaddr[26] = \ ; - assign m_axi_awaddr[25] = \ ; - assign m_axi_awaddr[24] = \ ; - assign m_axi_awaddr[23] = \ ; - assign m_axi_awaddr[22] = \ ; - assign m_axi_awaddr[21] = \ ; - assign m_axi_awaddr[20] = \ ; - assign m_axi_awaddr[19] = \ ; - assign m_axi_awaddr[18] = \ ; - assign m_axi_awaddr[17] = \ ; - assign m_axi_awaddr[16] = \ ; - assign m_axi_awaddr[15] = \ ; - assign m_axi_awaddr[14] = \ ; - assign m_axi_awaddr[13] = \ ; - assign m_axi_awaddr[12] = \ ; - assign m_axi_awaddr[11] = \ ; - assign m_axi_awaddr[10] = \ ; - assign m_axi_awaddr[9] = \ ; - assign m_axi_awaddr[8] = \ ; - assign m_axi_awaddr[7] = \ ; - assign m_axi_awaddr[6] = \ ; - assign m_axi_awaddr[5] = \ ; - assign m_axi_awaddr[4] = \ ; - assign m_axi_awaddr[3] = \ ; - assign m_axi_awaddr[2] = \ ; - assign m_axi_awaddr[1] = \ ; - assign m_axi_awaddr[0] = \ ; - assign m_axi_awburst[1] = \ ; - assign m_axi_awburst[0] = \ ; - assign m_axi_awcache[3] = \ ; - assign m_axi_awcache[2] = \ ; - assign m_axi_awcache[1] = \ ; - assign m_axi_awcache[0] = \ ; - assign m_axi_awid[0] = \ ; - assign m_axi_awlen[7] = \ ; - assign m_axi_awlen[6] = \ ; - assign m_axi_awlen[5] = \ ; - assign m_axi_awlen[4] = \ ; - assign m_axi_awlen[3] = \ ; - assign m_axi_awlen[2] = \ ; - assign m_axi_awlen[1] = \ ; - assign m_axi_awlen[0] = \ ; - assign m_axi_awlock[0] = \ ; - assign m_axi_awprot[2] = \ ; - assign m_axi_awprot[1] = \ ; - assign m_axi_awprot[0] = \ ; - assign m_axi_awqos[3] = \ ; - assign m_axi_awqos[2] = \ ; - assign m_axi_awqos[1] = \ ; - assign m_axi_awqos[0] = \ ; - assign m_axi_awregion[3] = \ ; - assign m_axi_awregion[2] = \ ; - assign m_axi_awregion[1] = \ ; - assign m_axi_awregion[0] = \ ; - assign m_axi_awsize[2] = \ ; - assign m_axi_awsize[1] = \ ; - assign m_axi_awsize[0] = \ ; - assign m_axi_awuser[0] = \ ; - assign m_axi_awvalid = \ ; - assign m_axi_bready = \ ; - assign m_axi_rready = \ ; - assign m_axi_wdata[63] = \ ; - assign m_axi_wdata[62] = \ ; - assign m_axi_wdata[61] = \ ; - assign m_axi_wdata[60] = \ ; - assign m_axi_wdata[59] = \ ; - assign m_axi_wdata[58] = \ ; - assign m_axi_wdata[57] = \ ; - assign m_axi_wdata[56] = \ ; - assign m_axi_wdata[55] = \ ; - assign m_axi_wdata[54] = \ ; - assign m_axi_wdata[53] = \ ; - assign m_axi_wdata[52] = \ ; - assign m_axi_wdata[51] = \ ; - assign m_axi_wdata[50] = \ ; - assign m_axi_wdata[49] = \ ; - assign m_axi_wdata[48] = \ ; - assign m_axi_wdata[47] = \ ; - assign m_axi_wdata[46] = \ ; - assign m_axi_wdata[45] = \ ; - assign m_axi_wdata[44] = \ ; - assign m_axi_wdata[43] = \ ; - assign m_axi_wdata[42] = \ ; - assign m_axi_wdata[41] = \ ; - assign m_axi_wdata[40] = \ ; - assign m_axi_wdata[39] = \ ; - assign m_axi_wdata[38] = \ ; - assign m_axi_wdata[37] = \ ; - assign m_axi_wdata[36] = \ ; - assign m_axi_wdata[35] = \ ; - assign m_axi_wdata[34] = \ ; - assign m_axi_wdata[33] = \ ; - assign m_axi_wdata[32] = \ ; - assign m_axi_wdata[31] = \ ; - assign m_axi_wdata[30] = \ ; - assign m_axi_wdata[29] = \ ; - assign m_axi_wdata[28] = \ ; - assign m_axi_wdata[27] = \ ; - assign m_axi_wdata[26] = \ ; - assign m_axi_wdata[25] = \ ; - assign m_axi_wdata[24] = \ ; - assign m_axi_wdata[23] = \ ; - assign m_axi_wdata[22] = \ ; - assign m_axi_wdata[21] = \ ; - assign m_axi_wdata[20] = \ ; - assign m_axi_wdata[19] = \ ; - assign m_axi_wdata[18] = \ ; - assign m_axi_wdata[17] = \ ; - assign m_axi_wdata[16] = \ ; - assign m_axi_wdata[15] = \ ; - assign m_axi_wdata[14] = \ ; - assign m_axi_wdata[13] = \ ; - assign m_axi_wdata[12] = \ ; - assign m_axi_wdata[11] = \ ; - assign m_axi_wdata[10] = \ ; - assign m_axi_wdata[9] = \ ; - assign m_axi_wdata[8] = \ ; - assign m_axi_wdata[7] = \ ; - assign m_axi_wdata[6] = \ ; - assign m_axi_wdata[5] = \ ; - assign m_axi_wdata[4] = \ ; - assign m_axi_wdata[3] = \ ; - assign m_axi_wdata[2] = \ ; - assign m_axi_wdata[1] = \ ; - assign m_axi_wdata[0] = \ ; - assign m_axi_wid[0] = \ ; - assign m_axi_wlast = \ ; - assign m_axi_wstrb[7] = \ ; - assign m_axi_wstrb[6] = \ ; - assign m_axi_wstrb[5] = \ ; - assign m_axi_wstrb[4] = \ ; - assign m_axi_wstrb[3] = \ ; - assign m_axi_wstrb[2] = \ ; - assign m_axi_wstrb[1] = \ ; - assign m_axi_wstrb[0] = \ ; - assign m_axi_wuser[0] = \ ; - assign m_axi_wvalid = \ ; - assign m_axis_tdata[7] = \ ; - assign m_axis_tdata[6] = \ ; - assign m_axis_tdata[5] = \ ; - assign m_axis_tdata[4] = \ ; - assign m_axis_tdata[3] = \ ; - assign m_axis_tdata[2] = \ ; - assign m_axis_tdata[1] = \ ; - assign m_axis_tdata[0] = \ ; - assign m_axis_tdest[0] = \ ; - assign m_axis_tid[0] = \ ; - assign m_axis_tkeep[0] = \ ; - assign m_axis_tlast = \ ; - assign m_axis_tstrb[0] = \ ; - assign m_axis_tuser[3] = \ ; - assign m_axis_tuser[2] = \ ; - assign m_axis_tuser[1] = \ ; - assign m_axis_tuser[0] = \ ; - assign m_axis_tvalid = \ ; - assign overflow = \ ; - assign prog_empty = \ ; - assign prog_full = \ ; - assign rd_data_count[9] = \ ; - assign rd_data_count[8] = \ ; - assign rd_data_count[7] = \ ; - assign rd_data_count[6] = \ ; - assign rd_data_count[5] = \ ; - assign rd_data_count[4] = \ ; - assign rd_data_count[3] = \ ; - assign rd_data_count[2] = \ ; - assign rd_data_count[1] = \ ; - assign rd_data_count[0] = \ ; - assign s_axi_arready = \ ; - assign s_axi_awready = \ ; - assign s_axi_bid[0] = \ ; - assign s_axi_bresp[1] = \ ; - assign s_axi_bresp[0] = \ ; - assign s_axi_buser[0] = \ ; - assign s_axi_bvalid = \ ; - assign s_axi_rdata[63] = \ ; - assign s_axi_rdata[62] = \ ; - assign s_axi_rdata[61] = \ ; - assign s_axi_rdata[60] = \ ; - assign s_axi_rdata[59] = \ ; - assign s_axi_rdata[58] = \ ; - assign s_axi_rdata[57] = \ ; - assign s_axi_rdata[56] = \ ; - assign s_axi_rdata[55] = \ ; - assign s_axi_rdata[54] = \ ; - assign s_axi_rdata[53] = \ ; - assign s_axi_rdata[52] = \ ; - assign s_axi_rdata[51] = \ ; - assign s_axi_rdata[50] = \ ; - assign s_axi_rdata[49] = \ ; - assign s_axi_rdata[48] = \ ; - assign s_axi_rdata[47] = \ ; - assign s_axi_rdata[46] = \ ; - assign s_axi_rdata[45] = \ ; - assign s_axi_rdata[44] = \ ; - assign s_axi_rdata[43] = \ ; - assign s_axi_rdata[42] = \ ; - assign s_axi_rdata[41] = \ ; - assign s_axi_rdata[40] = \ ; - assign s_axi_rdata[39] = \ ; - assign s_axi_rdata[38] = \ ; - assign s_axi_rdata[37] = \ ; - assign s_axi_rdata[36] = \ ; - assign s_axi_rdata[35] = \ ; - assign s_axi_rdata[34] = \ ; - assign s_axi_rdata[33] = \ ; - assign s_axi_rdata[32] = \ ; - assign s_axi_rdata[31] = \ ; - assign s_axi_rdata[30] = \ ; - assign s_axi_rdata[29] = \ ; - assign s_axi_rdata[28] = \ ; - assign s_axi_rdata[27] = \ ; - assign s_axi_rdata[26] = \ ; - assign s_axi_rdata[25] = \ ; - assign s_axi_rdata[24] = \ ; - assign s_axi_rdata[23] = \ ; - assign s_axi_rdata[22] = \ ; - assign s_axi_rdata[21] = \ ; - assign s_axi_rdata[20] = \ ; - assign s_axi_rdata[19] = \ ; - assign s_axi_rdata[18] = \ ; - assign s_axi_rdata[17] = \ ; - assign s_axi_rdata[16] = \ ; - assign s_axi_rdata[15] = \ ; - assign s_axi_rdata[14] = \ ; - assign s_axi_rdata[13] = \ ; - assign s_axi_rdata[12] = \ ; - assign s_axi_rdata[11] = \ ; - assign s_axi_rdata[10] = \ ; - assign s_axi_rdata[9] = \ ; - assign s_axi_rdata[8] = \ ; - assign s_axi_rdata[7] = \ ; - assign s_axi_rdata[6] = \ ; - assign s_axi_rdata[5] = \ ; - assign s_axi_rdata[4] = \ ; - assign s_axi_rdata[3] = \ ; - assign s_axi_rdata[2] = \ ; - assign s_axi_rdata[1] = \ ; - assign s_axi_rdata[0] = \ ; - assign s_axi_rid[0] = \ ; - assign s_axi_rlast = \ ; - assign s_axi_rresp[1] = \ ; - assign s_axi_rresp[0] = \ ; - assign s_axi_ruser[0] = \ ; - assign s_axi_rvalid = \ ; - assign s_axi_wready = \ ; - assign s_axis_tready = \ ; - assign sbiterr = \ ; - assign underflow = \ ; - assign valid = \ ; - assign wr_ack = \ ; - assign wr_data_count[9] = \ ; - assign wr_data_count[8] = \ ; - assign wr_data_count[7] = \ ; - assign wr_data_count[6] = \ ; - assign wr_data_count[5] = \ ; - assign wr_data_count[4] = \ ; - assign wr_data_count[3] = \ ; - assign wr_data_count[2] = \ ; - assign wr_data_count[1] = \ ; - assign wr_data_count[0] = \ ; - GND GND - (.G(\ )); - VCC VCC - (.P(\ )); - fifo_AntCtrl_fifo_generator_v13_2_4_synth inst_fifo_gen - (.AR(rd_rst_busy), - .din(din), - .dout(dout), - .empty(empty), - .full(full), - .rd_clk(rd_clk), - .rd_en(rd_en), - .rst(rst), - .wr_clk(wr_clk), - .wr_en(wr_en), - .wr_rst_busy(wr_rst_busy)); -endmodule - -(* ORIG_REF_NAME = "fifo_generator_v13_2_4_synth" *) -module fifo_AntCtrl_fifo_generator_v13_2_4_synth - (wr_rst_busy, - AR, - empty, - full, - dout, - rst, - wr_clk, - rd_clk, - din, - wr_en, - rd_en); - output wr_rst_busy; - output [0:0]AR; - output empty; - output full; - output [3:0]dout; - input rst; - input wr_clk; - input rd_clk; - input [3:0]din; - input wr_en; - input rd_en; - - wire [0:0]AR; - wire [3:0]din; - wire [3:0]dout; - wire empty; - wire full; - wire rd_clk; - wire rd_en; - wire rst; - wire wr_clk; - wire wr_en; - wire wr_rst_busy; - - fifo_AntCtrl_fifo_generator_top \gconvfifo.rf - (.AR(AR), - .din(din), - .dout(dout), - .empty(empty), - .full(full), - .rd_clk(rd_clk), - .rd_en(rd_en), - .rst(rst), - .wr_clk(wr_clk), - .wr_en(wr_en), - .wr_rst_busy(wr_rst_busy)); -endmodule - -(* ORIG_REF_NAME = "memory" *) -module fifo_AntCtrl_memory - (dout, - wr_clk, - din, - \gpr1.dout_i[2]_i_4 , - Q, - \gpr1.dout_i[3]_i_8 , - \gpr1.dout_i[2]_i_4_0 , - \gpr1.dout_i[2]_i_4_1 , - \gpr1.dout_i[2]_i_4_2 , - \gpr1.dout_i[2]_i_5 , - \gpr1.dout_i[2]_i_5_0 , - \gpr1.dout_i[2]_i_5_1 , - \gpr1.dout_i[2]_i_5_2 , - \gpr1.dout_i[2]_i_6 , - \gpr1.dout_i[2]_i_6_0 , - \gpr1.dout_i[2]_i_6_1 , - \gpr1.dout_i[2]_i_6_2 , - \gpr1.dout_i[2]_i_7 , - \gpr1.dout_i[2]_i_7_0 , - \gpr1.dout_i[2]_i_7_1 , - \gpr1.dout_i[2]_i_7_2 , - E, - rd_clk, - AR); - output [3:0]dout; - input wr_clk; - input [3:0]din; - input \gpr1.dout_i[2]_i_4 ; - input [9:0]Q; - input [5:0]\gpr1.dout_i[3]_i_8 ; - input \gpr1.dout_i[2]_i_4_0 ; - input \gpr1.dout_i[2]_i_4_1 ; - input \gpr1.dout_i[2]_i_4_2 ; - input \gpr1.dout_i[2]_i_5 ; - input \gpr1.dout_i[2]_i_5_0 ; - input \gpr1.dout_i[2]_i_5_1 ; - input \gpr1.dout_i[2]_i_5_2 ; - input \gpr1.dout_i[2]_i_6 ; - input \gpr1.dout_i[2]_i_6_0 ; - input \gpr1.dout_i[2]_i_6_1 ; - input \gpr1.dout_i[2]_i_6_2 ; - input \gpr1.dout_i[2]_i_7 ; - input \gpr1.dout_i[2]_i_7_0 ; - input \gpr1.dout_i[2]_i_7_1 ; - input \gpr1.dout_i[2]_i_7_2 ; - input [0:0]E; - input rd_clk; - input [0:0]AR; - - wire [0:0]AR; - wire [0:0]E; - wire [9:0]Q; - wire [3:0]din; - wire [3:0]dout; - wire \gpr1.dout_i[2]_i_4 ; - wire \gpr1.dout_i[2]_i_4_0 ; - wire \gpr1.dout_i[2]_i_4_1 ; - wire \gpr1.dout_i[2]_i_4_2 ; - wire \gpr1.dout_i[2]_i_5 ; - wire \gpr1.dout_i[2]_i_5_0 ; - wire \gpr1.dout_i[2]_i_5_1 ; - wire \gpr1.dout_i[2]_i_5_2 ; - wire \gpr1.dout_i[2]_i_6 ; - wire \gpr1.dout_i[2]_i_6_0 ; - wire \gpr1.dout_i[2]_i_6_1 ; - wire \gpr1.dout_i[2]_i_6_2 ; - wire \gpr1.dout_i[2]_i_7 ; - wire \gpr1.dout_i[2]_i_7_0 ; - wire \gpr1.dout_i[2]_i_7_1 ; - wire \gpr1.dout_i[2]_i_7_2 ; - wire [5:0]\gpr1.dout_i[3]_i_8 ; - wire rd_clk; - wire wr_clk; - - fifo_AntCtrl_dmem \gdm.dm_gen.dm - (.AR(AR), - .E(E), - .Q(Q), - .din(din), - .dout(dout), - .\gpr1.dout_i[2]_i_4_0 (\gpr1.dout_i[2]_i_4 ), - .\gpr1.dout_i[2]_i_4_1 (\gpr1.dout_i[2]_i_4_0 ), - .\gpr1.dout_i[2]_i_4_2 (\gpr1.dout_i[2]_i_4_1 ), - .\gpr1.dout_i[2]_i_4_3 (\gpr1.dout_i[2]_i_4_2 ), - .\gpr1.dout_i[2]_i_5_0 (\gpr1.dout_i[2]_i_5 ), - .\gpr1.dout_i[2]_i_5_1 (\gpr1.dout_i[2]_i_5_0 ), - .\gpr1.dout_i[2]_i_5_2 (\gpr1.dout_i[2]_i_5_1 ), - .\gpr1.dout_i[2]_i_5_3 (\gpr1.dout_i[2]_i_5_2 ), - .\gpr1.dout_i[2]_i_6_0 (\gpr1.dout_i[2]_i_6 ), - .\gpr1.dout_i[2]_i_6_1 (\gpr1.dout_i[2]_i_6_0 ), - .\gpr1.dout_i[2]_i_6_2 (\gpr1.dout_i[2]_i_6_1 ), - .\gpr1.dout_i[2]_i_6_3 (\gpr1.dout_i[2]_i_6_2 ), - .\gpr1.dout_i[2]_i_7_0 (\gpr1.dout_i[2]_i_7 ), - .\gpr1.dout_i[2]_i_7_1 (\gpr1.dout_i[2]_i_7_0 ), - .\gpr1.dout_i[2]_i_7_2 (\gpr1.dout_i[2]_i_7_1 ), - .\gpr1.dout_i[2]_i_7_3 (\gpr1.dout_i[2]_i_7_2 ), - .\gpr1.dout_i[3]_i_8_0 (\gpr1.dout_i[3]_i_8 ), - .rd_clk(rd_clk), - .wr_clk(wr_clk)); -endmodule - -(* ORIG_REF_NAME = "rd_bin_cntr" *) -module fifo_AntCtrl_rd_bin_cntr - (v1_reg, - Q, - v1_reg_0, - WR_PNTR_RD, - E, - rd_clk, - AR); - output [4:0]v1_reg; - output [9:0]Q; - output [4:0]v1_reg_0; - input [9:0]WR_PNTR_RD; - input [0:0]E; - input rd_clk; - input [0:0]AR; - - wire [0:0]AR; - wire [0:0]E; - wire [9:0]Q; - wire [9:0]WR_PNTR_RD; - wire \gc0.count[9]_i_2_n_0 ; - wire [9:0]plusOp__0; - wire rd_clk; - wire [9:0]rd_pntr_plus1; - wire [4:0]v1_reg; - wire [4:0]v1_reg_0; - - LUT1 #( - .INIT(2'h1)) - \gc0.count[0]_i_1 - (.I0(rd_pntr_plus1[0]), - .O(plusOp__0[0])); - (* SOFT_HLUTNM = "soft_lutpair11" *) - LUT2 #( - .INIT(4'h6)) - \gc0.count[1]_i_1 - (.I0(rd_pntr_plus1[0]), - .I1(rd_pntr_plus1[1]), - .O(plusOp__0[1])); - (* SOFT_HLUTNM = "soft_lutpair11" *) - LUT3 #( - .INIT(8'h78)) - \gc0.count[2]_i_1 - (.I0(rd_pntr_plus1[0]), - .I1(rd_pntr_plus1[1]), - .I2(rd_pntr_plus1[2]), - .O(plusOp__0[2])); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT4 #( - .INIT(16'h7F80)) - \gc0.count[3]_i_1 - (.I0(rd_pntr_plus1[1]), - .I1(rd_pntr_plus1[0]), - .I2(rd_pntr_plus1[2]), - .I3(rd_pntr_plus1[3]), - .O(plusOp__0[3])); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT5 #( - .INIT(32'h7FFF8000)) - \gc0.count[4]_i_1 - (.I0(rd_pntr_plus1[2]), - .I1(rd_pntr_plus1[0]), - .I2(rd_pntr_plus1[1]), - .I3(rd_pntr_plus1[3]), - .I4(rd_pntr_plus1[4]), - .O(plusOp__0[4])); - LUT6 #( - .INIT(64'h7FFFFFFF80000000)) - \gc0.count[5]_i_1 - (.I0(rd_pntr_plus1[3]), - .I1(rd_pntr_plus1[1]), - .I2(rd_pntr_plus1[0]), - .I3(rd_pntr_plus1[2]), - .I4(rd_pntr_plus1[4]), - .I5(rd_pntr_plus1[5]), - .O(plusOp__0[5])); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT2 #( - .INIT(4'h6)) - \gc0.count[6]_i_1 - (.I0(\gc0.count[9]_i_2_n_0 ), - .I1(rd_pntr_plus1[6]), - .O(plusOp__0[6])); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT3 #( - .INIT(8'h78)) - \gc0.count[7]_i_1 - (.I0(\gc0.count[9]_i_2_n_0 ), - .I1(rd_pntr_plus1[6]), - .I2(rd_pntr_plus1[7]), - .O(plusOp__0[7])); - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT4 #( - .INIT(16'h7F80)) - \gc0.count[8]_i_1 - (.I0(rd_pntr_plus1[6]), - .I1(\gc0.count[9]_i_2_n_0 ), - .I2(rd_pntr_plus1[7]), - .I3(rd_pntr_plus1[8]), - .O(plusOp__0[8])); - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT5 #( - .INIT(32'h7FFF8000)) - \gc0.count[9]_i_1 - (.I0(rd_pntr_plus1[7]), - .I1(\gc0.count[9]_i_2_n_0 ), - .I2(rd_pntr_plus1[6]), - .I3(rd_pntr_plus1[8]), - .I4(rd_pntr_plus1[9]), - .O(plusOp__0[9])); - LUT6 #( - .INIT(64'h8000000000000000)) - \gc0.count[9]_i_2 - (.I0(rd_pntr_plus1[5]), - .I1(rd_pntr_plus1[3]), - .I2(rd_pntr_plus1[1]), - .I3(rd_pntr_plus1[0]), - .I4(rd_pntr_plus1[2]), - .I5(rd_pntr_plus1[4]), - .O(\gc0.count[9]_i_2_n_0 )); - FDCE #( - .INIT(1'b0)) - \gc0.count_d1_reg[0] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(rd_pntr_plus1[0]), - .Q(Q[0])); - FDCE #( - .INIT(1'b0)) - \gc0.count_d1_reg[1] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(rd_pntr_plus1[1]), - .Q(Q[1])); - FDCE #( - .INIT(1'b0)) - \gc0.count_d1_reg[2] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(rd_pntr_plus1[2]), - .Q(Q[2])); - FDCE #( - .INIT(1'b0)) - \gc0.count_d1_reg[3] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(rd_pntr_plus1[3]), - .Q(Q[3])); - FDCE #( - .INIT(1'b0)) - \gc0.count_d1_reg[4] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(rd_pntr_plus1[4]), - .Q(Q[4])); - FDCE #( - .INIT(1'b0)) - \gc0.count_d1_reg[5] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(rd_pntr_plus1[5]), - .Q(Q[5])); - FDCE #( - .INIT(1'b0)) - \gc0.count_d1_reg[6] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(rd_pntr_plus1[6]), - .Q(Q[6])); - FDCE #( - .INIT(1'b0)) - \gc0.count_d1_reg[7] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(rd_pntr_plus1[7]), - .Q(Q[7])); - FDCE #( - .INIT(1'b0)) - \gc0.count_d1_reg[8] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(rd_pntr_plus1[8]), - .Q(Q[8])); - FDCE #( - .INIT(1'b0)) - \gc0.count_d1_reg[9] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(rd_pntr_plus1[9]), - .Q(Q[9])); - FDPE #( - .INIT(1'b1)) - \gc0.count_reg[0] - (.C(rd_clk), - .CE(E), - .D(plusOp__0[0]), - .PRE(AR), - .Q(rd_pntr_plus1[0])); - FDCE #( - .INIT(1'b0)) - \gc0.count_reg[1] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(plusOp__0[1]), - .Q(rd_pntr_plus1[1])); - FDCE #( - .INIT(1'b0)) - \gc0.count_reg[2] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(plusOp__0[2]), - .Q(rd_pntr_plus1[2])); - FDCE #( - .INIT(1'b0)) - \gc0.count_reg[3] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(plusOp__0[3]), - .Q(rd_pntr_plus1[3])); - FDCE #( - .INIT(1'b0)) - \gc0.count_reg[4] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(plusOp__0[4]), - .Q(rd_pntr_plus1[4])); - FDCE #( - .INIT(1'b0)) - \gc0.count_reg[5] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(plusOp__0[5]), - .Q(rd_pntr_plus1[5])); - FDCE #( - .INIT(1'b0)) - \gc0.count_reg[6] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(plusOp__0[6]), - .Q(rd_pntr_plus1[6])); - FDCE #( - .INIT(1'b0)) - \gc0.count_reg[7] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(plusOp__0[7]), - .Q(rd_pntr_plus1[7])); - FDCE #( - .INIT(1'b0)) - \gc0.count_reg[8] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(plusOp__0[8]), - .Q(rd_pntr_plus1[8])); - FDCE #( - .INIT(1'b0)) - \gc0.count_reg[9] - (.C(rd_clk), - .CE(E), - .CLR(AR), - .D(plusOp__0[9]), - .Q(rd_pntr_plus1[9])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[0].gm1.m1_i_1__1 - (.I0(Q[0]), - .I1(WR_PNTR_RD[0]), - .I2(Q[1]), - .I3(WR_PNTR_RD[1]), - .O(v1_reg[0])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[0].gm1.m1_i_1__2 - (.I0(rd_pntr_plus1[0]), - .I1(WR_PNTR_RD[0]), - .I2(rd_pntr_plus1[1]), - .I3(WR_PNTR_RD[1]), - .O(v1_reg_0[0])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[1].gms.ms_i_1__1 - (.I0(Q[2]), - .I1(WR_PNTR_RD[2]), - .I2(Q[3]), - .I3(WR_PNTR_RD[3]), - .O(v1_reg[1])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[1].gms.ms_i_1__2 - (.I0(rd_pntr_plus1[2]), - .I1(WR_PNTR_RD[2]), - .I2(rd_pntr_plus1[3]), - .I3(WR_PNTR_RD[3]), - .O(v1_reg_0[1])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[2].gms.ms_i_1__1 - (.I0(Q[4]), - .I1(WR_PNTR_RD[4]), - .I2(Q[5]), - .I3(WR_PNTR_RD[5]), - .O(v1_reg[2])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[2].gms.ms_i_1__2 - (.I0(rd_pntr_plus1[4]), - .I1(WR_PNTR_RD[4]), - .I2(rd_pntr_plus1[5]), - .I3(WR_PNTR_RD[5]), - .O(v1_reg_0[2])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[3].gms.ms_i_1__1 - (.I0(Q[6]), - .I1(WR_PNTR_RD[6]), - .I2(Q[7]), - .I3(WR_PNTR_RD[7]), - .O(v1_reg[3])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[3].gms.ms_i_1__2 - (.I0(rd_pntr_plus1[6]), - .I1(WR_PNTR_RD[6]), - .I2(rd_pntr_plus1[7]), - .I3(WR_PNTR_RD[7]), - .O(v1_reg_0[3])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[4].gms.ms_i_1__1 - (.I0(Q[8]), - .I1(WR_PNTR_RD[8]), - .I2(Q[9]), - .I3(WR_PNTR_RD[9]), - .O(v1_reg[4])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[4].gms.ms_i_1__2 - (.I0(rd_pntr_plus1[8]), - .I1(WR_PNTR_RD[8]), - .I2(rd_pntr_plus1[9]), - .I3(WR_PNTR_RD[9]), - .O(v1_reg_0[4])); -endmodule - -(* ORIG_REF_NAME = "rd_logic" *) -module fifo_AntCtrl_rd_logic - (empty, - Q, - E, - rd_clk, - AR, - rd_en, - WR_PNTR_RD); - output empty; - output [9:0]Q; - output [0:0]E; - input rd_clk; - input [0:0]AR; - input rd_en; - input [9:0]WR_PNTR_RD; - - wire [0:0]AR; - wire [0:0]E; - wire [9:0]Q; - wire [9:0]WR_PNTR_RD; - wire [4:0]\c0/v1_reg ; - wire [4:0]\c1/v1_reg ; - wire empty; - wire rd_clk; - wire rd_en; - - fifo_AntCtrl_rd_status_flags_as \gras.rsts - (.AR(AR), - .E(E), - .empty(empty), - .rd_clk(rd_clk), - .rd_en(rd_en), - .v1_reg(\c0/v1_reg ), - .v1_reg_0(\c1/v1_reg )); - fifo_AntCtrl_rd_bin_cntr rpntr - (.AR(AR), - .E(E), - .Q(Q), - .WR_PNTR_RD(WR_PNTR_RD), - .rd_clk(rd_clk), - .v1_reg(\c0/v1_reg ), - .v1_reg_0(\c1/v1_reg )); -endmodule - -(* ORIG_REF_NAME = "rd_status_flags_as" *) -module fifo_AntCtrl_rd_status_flags_as - (empty, - E, - v1_reg, - v1_reg_0, - rd_clk, - AR, - rd_en); - output empty; - output [0:0]E; - input [4:0]v1_reg; - input [4:0]v1_reg_0; - input rd_clk; - input [0:0]AR; - input rd_en; - - wire [0:0]AR; - wire [0:0]E; - wire c0_n_0; - wire comp1; - (* DONT_TOUCH *) wire ram_empty_fb_i; - (* DONT_TOUCH *) wire ram_empty_i; - wire rd_clk; - wire rd_en; - wire [4:0]v1_reg; - wire [4:0]v1_reg_0; - - assign empty = ram_empty_i; - fifo_AntCtrl_compare_1 c0 - (.comp1(comp1), - .out(ram_empty_fb_i), - .rd_en(rd_en), - .rd_en_0(c0_n_0), - .v1_reg(v1_reg)); - fifo_AntCtrl_compare_2 c1 - (.comp1(comp1), - .v1_reg_0(v1_reg_0)); - LUT2 #( - .INIT(4'h2)) - \gpr1.dout_i[3]_i_1 - (.I0(rd_en), - .I1(ram_empty_fb_i), - .O(E)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* equivalent_register_removal = "no" *) - FDPE #( - .INIT(1'b1)) - ram_empty_fb_i_reg - (.C(rd_clk), - .CE(1'b1), - .D(c0_n_0), - .PRE(AR), - .Q(ram_empty_fb_i)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* equivalent_register_removal = "no" *) - FDPE #( - .INIT(1'b1)) - ram_empty_i_reg - (.C(rd_clk), - .CE(1'b1), - .D(c0_n_0), - .PRE(AR), - .Q(ram_empty_i)); -endmodule - -(* ORIG_REF_NAME = "reset_blk_ramfifo" *) -module fifo_AntCtrl_reset_blk_ramfifo - (AR, - \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 , - out, - \grstd1.grst_full.grst_f.rst_d3_reg_0 , - wr_rst_busy, - rst, - wr_clk, - rd_clk); - output [0:0]AR; - output [0:0]\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 ; - output out; - output \grstd1.grst_full.grst_f.rst_d3_reg_0 ; - output wr_rst_busy; - input rst; - input wr_clk; - input rd_clk; - - wire [0:0]AR; - wire dest_out; - wire \grstd1.grst_full.grst_f.rst_d3_i_1_n_0 ; - wire \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_i_1_n_0 ; - wire [0:0]\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 ; - wire \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_i_1_n_0 ; - wire \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_i_1_n_0 ; - wire rd_clk; - wire [3:0]rd_rst_wr_ext; - wire rst; - (* async_reg = "true" *) (* msgon = "true" *) wire rst_d1; - (* async_reg = "true" *) (* msgon = "true" *) wire rst_d2; - (* async_reg = "true" *) (* msgon = "true" *) wire rst_d3; - (* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2; - (* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2; - wire sckt_rd_rst_wr; - wire wr_clk; - wire wr_rst_busy; - wire [1:0]wr_rst_rd_ext; - - assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d3; - assign out = rst_d2; - (* ASYNC_REG *) - (* KEEP = "yes" *) - (* msgon = "true" *) - FDPE #( - .INIT(1'b1)) - \grstd1.grst_full.grst_f.rst_d1_reg - (.C(wr_clk), - .CE(1'b1), - .D(wr_rst_busy), - .PRE(rst_wr_reg2), - .Q(rst_d1)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - (* msgon = "true" *) - FDPE #( - .INIT(1'b1)) - \grstd1.grst_full.grst_f.rst_d2_reg - (.C(wr_clk), - .CE(1'b1), - .D(rst_d1), - .PRE(rst_wr_reg2), - .Q(rst_d2)); - LUT2 #( - .INIT(4'hE)) - \grstd1.grst_full.grst_f.rst_d3_i_1 - (.I0(rst_d2), - .I1(AR), - .O(\grstd1.grst_full.grst_f.rst_d3_i_1_n_0 )); - (* ASYNC_REG *) - (* KEEP = "yes" *) - (* msgon = "true" *) - FDPE #( - .INIT(1'b1)) - \grstd1.grst_full.grst_f.rst_d3_reg - (.C(wr_clk), - .CE(1'b1), - .D(\grstd1.grst_full.grst_f.rst_d3_i_1_n_0 ), - .PRE(rst_wr_reg2), - .Q(rst_d3)); - FDCE #( - .INIT(1'b0)) - \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[0] - (.C(wr_clk), - .CE(1'b1), - .CLR(rst_wr_reg2), - .D(sckt_rd_rst_wr), - .Q(rd_rst_wr_ext[0])); - FDCE #( - .INIT(1'b0)) - \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[1] - (.C(wr_clk), - .CE(1'b1), - .CLR(rst_wr_reg2), - .D(rd_rst_wr_ext[0]), - .Q(rd_rst_wr_ext[1])); - FDCE #( - .INIT(1'b0)) - \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[2] - (.C(wr_clk), - .CE(1'b1), - .CLR(rst_wr_reg2), - .D(rd_rst_wr_ext[1]), - .Q(rd_rst_wr_ext[2])); - FDCE #( - .INIT(1'b0)) - \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[3] - (.C(wr_clk), - .CE(1'b1), - .CLR(rst_wr_reg2), - .D(rd_rst_wr_ext[2]), - .Q(rd_rst_wr_ext[3])); - (* DEF_VAL = "1'b0" *) - (* DEST_SYNC_FF = "2" *) - (* INIT_SYNC_FF = "0" *) - (* INV_DEF_VAL = "1'b1" *) - (* RST_ACTIVE_HIGH = "1" *) - (* VERSION = "0" *) - (* XPM_CDC = "ASYNC_RST" *) - (* XPM_MODULE = "TRUE" *) - fifo_AntCtrl_xpm_cdc_async_rst \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst - (.dest_arst(rst_rd_reg2), - .dest_clk(rd_clk), - .src_arst(rst)); - LUT2 #( - .INIT(4'h2)) - \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_i_1 - (.I0(\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 ), - .I1(wr_rst_rd_ext[1]), - .O(\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_i_1_n_0 )); - FDPE #( - .INIT(1'b0)) - \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg - (.C(rd_clk), - .CE(1'b1), - .D(\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_i_1_n_0 ), - .PRE(rst_rd_reg2), - .Q(\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 )); - LUT3 #( - .INIT(8'h8A)) - \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_i_1 - (.I0(AR), - .I1(rd_rst_wr_ext[0]), - .I2(rd_rst_wr_ext[1]), - .O(\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_i_1_n_0 )); - FDPE #( - .INIT(1'b0)) - \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg - (.C(wr_clk), - .CE(1'b1), - .D(\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_i_1_n_0 ), - .PRE(rst_wr_reg2), - .Q(AR)); - LUT5 #( - .INIT(32'hAAAA08AA)) - \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_i_1 - (.I0(wr_rst_busy), - .I1(rd_rst_wr_ext[1]), - .I2(rd_rst_wr_ext[0]), - .I3(rd_rst_wr_ext[3]), - .I4(rd_rst_wr_ext[2]), - .O(\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_i_1_n_0 )); - FDPE #( - .INIT(1'b0)) - \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_reg - (.C(wr_clk), - .CE(1'b1), - .D(\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_i_1_n_0 ), - .PRE(rst_wr_reg2), - .Q(wr_rst_busy)); - FDCE #( - .INIT(1'b0)) - \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0] - (.C(rd_clk), - .CE(1'b1), - .CLR(rst_rd_reg2), - .D(dest_out), - .Q(wr_rst_rd_ext[0])); - FDCE #( - .INIT(1'b0)) - \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[1] - (.C(rd_clk), - .CE(1'b1), - .CLR(rst_rd_reg2), - .D(wr_rst_rd_ext[0]), - .Q(wr_rst_rd_ext[1])); - (* DEST_SYNC_FF = "4" *) - (* INIT_SYNC_FF = "0" *) - (* SIM_ASSERT_CHK = "0" *) - (* SRC_INPUT_REG = "0" *) - (* VERSION = "0" *) - (* XPM_CDC = "SINGLE" *) - (* XPM_MODULE = "TRUE" *) - fifo_AntCtrl_xpm_cdc_single \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr - (.dest_clk(wr_clk), - .dest_out(sckt_rd_rst_wr), - .src_clk(rd_clk), - .src_in(\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 )); - (* DEST_SYNC_FF = "4" *) - (* INIT_SYNC_FF = "0" *) - (* SIM_ASSERT_CHK = "0" *) - (* SRC_INPUT_REG = "0" *) - (* VERSION = "0" *) - (* XPM_CDC = "SINGLE" *) - (* XPM_MODULE = "TRUE" *) - fifo_AntCtrl_xpm_cdc_single__2 \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd - (.dest_clk(rd_clk), - .dest_out(dest_out), - .src_clk(wr_clk), - .src_in(AR)); - (* DEF_VAL = "1'b0" *) - (* DEST_SYNC_FF = "2" *) - (* INIT_SYNC_FF = "0" *) - (* INV_DEF_VAL = "1'b1" *) - (* RST_ACTIVE_HIGH = "1" *) - (* VERSION = "0" *) - (* XPM_CDC = "ASYNC_RST" *) - (* XPM_MODULE = "TRUE" *) - fifo_AntCtrl_xpm_cdc_async_rst__2 \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst - (.dest_arst(rst_wr_reg2), - .dest_clk(wr_clk), - .src_arst(rst)); -endmodule - -(* ORIG_REF_NAME = "wr_bin_cntr" *) -module fifo_AntCtrl_wr_bin_cntr - (ram_full_fb_i_reg, - Q, - ram_full_fb_i_reg_0, - ram_full_fb_i_reg_1, - ram_full_fb_i_reg_2, - ram_full_fb_i_reg_3, - \gic0.gc0.count_d2_reg[9]_0 , - \gic0.gc0.count_d2_reg[8]_0 , - ram_full_fb_i_reg_4, - \gic0.gc0.count_d2_reg[9]_1 , - \gic0.gc0.count_d2_reg[7]_0 , - \gic0.gc0.count_d2_reg[9]_2 , - \gic0.gc0.count_d2_reg[6]_0 , - \gic0.gc0.count_d2_reg[9]_3 , - \gic0.gc0.count_d2_reg[8]_1 , - \gic0.gc0.count_d2_reg[8]_2 , - \gic0.gc0.count_d2_reg[7]_1 , - \gic0.gc0.count_reg[9]_0 , - \gic0.gc0.count_d1_reg[9]_0 , - out, - wr_en, - E, - wr_clk, - AR); - output ram_full_fb_i_reg; - output [9:0]Q; - output ram_full_fb_i_reg_0; - output ram_full_fb_i_reg_1; - output ram_full_fb_i_reg_2; - output ram_full_fb_i_reg_3; - output \gic0.gc0.count_d2_reg[9]_0 ; - output \gic0.gc0.count_d2_reg[8]_0 ; - output ram_full_fb_i_reg_4; - output \gic0.gc0.count_d2_reg[9]_1 ; - output \gic0.gc0.count_d2_reg[7]_0 ; - output \gic0.gc0.count_d2_reg[9]_2 ; - output \gic0.gc0.count_d2_reg[6]_0 ; - output \gic0.gc0.count_d2_reg[9]_3 ; - output \gic0.gc0.count_d2_reg[8]_1 ; - output \gic0.gc0.count_d2_reg[8]_2 ; - output \gic0.gc0.count_d2_reg[7]_1 ; - output [9:0]\gic0.gc0.count_reg[9]_0 ; - output [9:0]\gic0.gc0.count_d1_reg[9]_0 ; - input out; - input wr_en; - input [0:0]E; - input wr_clk; - input [0:0]AR; - - wire [0:0]AR; - wire [0:0]E; - wire [9:0]Q; - wire \gic0.gc0.count[9]_i_2_n_0 ; - wire [9:0]\gic0.gc0.count_d1_reg[9]_0 ; - wire \gic0.gc0.count_d2_reg[6]_0 ; - wire \gic0.gc0.count_d2_reg[7]_0 ; - wire \gic0.gc0.count_d2_reg[7]_1 ; - wire \gic0.gc0.count_d2_reg[8]_0 ; - wire \gic0.gc0.count_d2_reg[8]_1 ; - wire \gic0.gc0.count_d2_reg[8]_2 ; - wire \gic0.gc0.count_d2_reg[9]_0 ; - wire \gic0.gc0.count_d2_reg[9]_1 ; - wire \gic0.gc0.count_d2_reg[9]_2 ; - wire \gic0.gc0.count_d2_reg[9]_3 ; - wire [9:0]\gic0.gc0.count_reg[9]_0 ; - wire out; - wire [9:0]plusOp; - wire ram_full_fb_i_reg; - wire ram_full_fb_i_reg_0; - wire ram_full_fb_i_reg_1; - wire ram_full_fb_i_reg_2; - wire ram_full_fb_i_reg_3; - wire ram_full_fb_i_reg_4; - wire wr_clk; - wire wr_en; - - LUT6 #( - .INIT(64'h0000000000000004)) - RAM_reg_0_63_0_2_i_1 - (.I0(out), - .I1(wr_en), - .I2(Q[7]), - .I3(Q[6]), - .I4(Q[9]), - .I5(Q[8]), - .O(ram_full_fb_i_reg_1)); - LUT6 #( - .INIT(64'h0000000400000000)) - RAM_reg_128_191_0_2_i_1 - (.I0(out), - .I1(wr_en), - .I2(Q[8]), - .I3(Q[6]), - .I4(Q[9]), - .I5(Q[7]), - .O(ram_full_fb_i_reg_3)); - LUT6 #( - .INIT(64'h0000004000000000)) - RAM_reg_192_255_0_2_i_1 - (.I0(Q[9]), - .I1(Q[7]), - .I2(Q[6]), - .I3(Q[8]), - .I4(out), - .I5(wr_en), - .O(\gic0.gc0.count_d2_reg[9]_1 )); - LUT6 #( - .INIT(64'h0000000400000000)) - RAM_reg_256_319_0_2_i_1 - (.I0(out), - .I1(wr_en), - .I2(Q[7]), - .I3(Q[6]), - .I4(Q[9]), - .I5(Q[8]), - .O(ram_full_fb_i_reg)); - LUT6 #( - .INIT(64'h0000004000000000)) - RAM_reg_320_383_0_2_i_1 - (.I0(Q[9]), - .I1(Q[8]), - .I2(Q[6]), - .I3(Q[7]), - .I4(out), - .I5(wr_en), - .O(\gic0.gc0.count_d2_reg[9]_2 )); - LUT6 #( - .INIT(64'h0000004000000000)) - RAM_reg_384_447_0_2_i_1 - (.I0(Q[9]), - .I1(Q[8]), - .I2(Q[7]), - .I3(Q[6]), - .I4(out), - .I5(wr_en), - .O(\gic0.gc0.count_d2_reg[9]_3 )); - LUT6 #( - .INIT(64'h0040000000000000)) - RAM_reg_448_511_0_2_i_1 - (.I0(Q[9]), - .I1(Q[7]), - .I2(Q[6]), - .I3(out), - .I4(wr_en), - .I5(Q[8]), - .O(\gic0.gc0.count_d2_reg[9]_0 )); - LUT6 #( - .INIT(64'h0000000400000000)) - RAM_reg_512_575_0_2_i_1 - (.I0(out), - .I1(wr_en), - .I2(Q[7]), - .I3(Q[6]), - .I4(Q[8]), - .I5(Q[9]), - .O(ram_full_fb_i_reg_0)); - LUT6 #( - .INIT(64'h0000004000000000)) - RAM_reg_576_639_0_2_i_1 - (.I0(Q[8]), - .I1(Q[9]), - .I2(Q[6]), - .I3(Q[7]), - .I4(out), - .I5(wr_en), - .O(\gic0.gc0.count_d2_reg[8]_1 )); - LUT6 #( - .INIT(64'h0000004000000000)) - RAM_reg_640_703_0_2_i_1 - (.I0(Q[8]), - .I1(Q[9]), - .I2(Q[7]), - .I3(Q[6]), - .I4(out), - .I5(wr_en), - .O(\gic0.gc0.count_d2_reg[8]_2 )); - LUT6 #( - .INIT(64'h0000000400000000)) - RAM_reg_64_127_0_2_i_1 - (.I0(out), - .I1(wr_en), - .I2(Q[8]), - .I3(Q[7]), - .I4(Q[9]), - .I5(Q[6]), - .O(ram_full_fb_i_reg_2)); - LUT6 #( - .INIT(64'h0040000000000000)) - RAM_reg_704_767_0_2_i_1 - (.I0(Q[8]), - .I1(Q[7]), - .I2(Q[6]), - .I3(out), - .I4(wr_en), - .I5(Q[9]), - .O(\gic0.gc0.count_d2_reg[8]_0 )); - LUT6 #( - .INIT(64'h0000004000000000)) - RAM_reg_768_831_0_2_i_1 - (.I0(Q[7]), - .I1(Q[9]), - .I2(Q[8]), - .I3(Q[6]), - .I4(out), - .I5(wr_en), - .O(\gic0.gc0.count_d2_reg[7]_1 )); - LUT6 #( - .INIT(64'h0040000000000000)) - RAM_reg_832_895_0_2_i_1 - (.I0(Q[7]), - .I1(Q[8]), - .I2(Q[6]), - .I3(out), - .I4(wr_en), - .I5(Q[9]), - .O(\gic0.gc0.count_d2_reg[7]_0 )); - LUT6 #( - .INIT(64'h0040000000000000)) - RAM_reg_896_959_0_2_i_1 - (.I0(Q[6]), - .I1(Q[8]), - .I2(Q[7]), - .I3(out), - .I4(wr_en), - .I5(Q[9]), - .O(\gic0.gc0.count_d2_reg[6]_0 )); - LUT6 #( - .INIT(64'h4000000000000000)) - RAM_reg_960_1023_0_2_i_1 - (.I0(out), - .I1(wr_en), - .I2(Q[7]), - .I3(Q[6]), - .I4(Q[9]), - .I5(Q[8]), - .O(ram_full_fb_i_reg_4)); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT1 #( - .INIT(2'h1)) - \gic0.gc0.count[0]_i_1 - (.I0(\gic0.gc0.count_reg[9]_0 [0]), - .O(plusOp[0])); - LUT2 #( - .INIT(4'h6)) - \gic0.gc0.count[1]_i_1 - (.I0(\gic0.gc0.count_reg[9]_0 [0]), - .I1(\gic0.gc0.count_reg[9]_0 [1]), - .O(plusOp[1])); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT3 #( - .INIT(8'h78)) - \gic0.gc0.count[2]_i_1 - (.I0(\gic0.gc0.count_reg[9]_0 [0]), - .I1(\gic0.gc0.count_reg[9]_0 [1]), - .I2(\gic0.gc0.count_reg[9]_0 [2]), - .O(plusOp[2])); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT4 #( - .INIT(16'h7F80)) - \gic0.gc0.count[3]_i_1 - (.I0(\gic0.gc0.count_reg[9]_0 [1]), - .I1(\gic0.gc0.count_reg[9]_0 [0]), - .I2(\gic0.gc0.count_reg[9]_0 [2]), - .I3(\gic0.gc0.count_reg[9]_0 [3]), - .O(plusOp[3])); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT5 #( - .INIT(32'h7FFF8000)) - \gic0.gc0.count[4]_i_1 - (.I0(\gic0.gc0.count_reg[9]_0 [2]), - .I1(\gic0.gc0.count_reg[9]_0 [0]), - .I2(\gic0.gc0.count_reg[9]_0 [1]), - .I3(\gic0.gc0.count_reg[9]_0 [3]), - .I4(\gic0.gc0.count_reg[9]_0 [4]), - .O(plusOp[4])); - LUT6 #( - .INIT(64'h7FFFFFFF80000000)) - \gic0.gc0.count[5]_i_1 - (.I0(\gic0.gc0.count_reg[9]_0 [3]), - .I1(\gic0.gc0.count_reg[9]_0 [1]), - .I2(\gic0.gc0.count_reg[9]_0 [0]), - .I3(\gic0.gc0.count_reg[9]_0 [2]), - .I4(\gic0.gc0.count_reg[9]_0 [4]), - .I5(\gic0.gc0.count_reg[9]_0 [5]), - .O(plusOp[5])); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT2 #( - .INIT(4'h6)) - \gic0.gc0.count[6]_i_1 - (.I0(\gic0.gc0.count[9]_i_2_n_0 ), - .I1(\gic0.gc0.count_reg[9]_0 [6]), - .O(plusOp[6])); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT3 #( - .INIT(8'h78)) - \gic0.gc0.count[7]_i_1 - (.I0(\gic0.gc0.count[9]_i_2_n_0 ), - .I1(\gic0.gc0.count_reg[9]_0 [6]), - .I2(\gic0.gc0.count_reg[9]_0 [7]), - .O(plusOp[7])); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT4 #( - .INIT(16'h7F80)) - \gic0.gc0.count[8]_i_1 - (.I0(\gic0.gc0.count_reg[9]_0 [6]), - .I1(\gic0.gc0.count[9]_i_2_n_0 ), - .I2(\gic0.gc0.count_reg[9]_0 [7]), - .I3(\gic0.gc0.count_reg[9]_0 [8]), - .O(plusOp[8])); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT5 #( - .INIT(32'h7FFF8000)) - \gic0.gc0.count[9]_i_1 - (.I0(\gic0.gc0.count_reg[9]_0 [7]), - .I1(\gic0.gc0.count[9]_i_2_n_0 ), - .I2(\gic0.gc0.count_reg[9]_0 [6]), - .I3(\gic0.gc0.count_reg[9]_0 [8]), - .I4(\gic0.gc0.count_reg[9]_0 [9]), - .O(plusOp[9])); - LUT6 #( - .INIT(64'h8000000000000000)) - \gic0.gc0.count[9]_i_2 - (.I0(\gic0.gc0.count_reg[9]_0 [5]), - .I1(\gic0.gc0.count_reg[9]_0 [3]), - .I2(\gic0.gc0.count_reg[9]_0 [1]), - .I3(\gic0.gc0.count_reg[9]_0 [0]), - .I4(\gic0.gc0.count_reg[9]_0 [2]), - .I5(\gic0.gc0.count_reg[9]_0 [4]), - .O(\gic0.gc0.count[9]_i_2_n_0 )); - FDPE #( - .INIT(1'b1)) - \gic0.gc0.count_d1_reg[0] - (.C(wr_clk), - .CE(E), - .D(\gic0.gc0.count_reg[9]_0 [0]), - .PRE(AR), - .Q(\gic0.gc0.count_d1_reg[9]_0 [0])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_d1_reg[1] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(\gic0.gc0.count_reg[9]_0 [1]), - .Q(\gic0.gc0.count_d1_reg[9]_0 [1])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_d1_reg[2] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(\gic0.gc0.count_reg[9]_0 [2]), - .Q(\gic0.gc0.count_d1_reg[9]_0 [2])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_d1_reg[3] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(\gic0.gc0.count_reg[9]_0 [3]), - .Q(\gic0.gc0.count_d1_reg[9]_0 [3])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_d1_reg[4] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(\gic0.gc0.count_reg[9]_0 [4]), - .Q(\gic0.gc0.count_d1_reg[9]_0 [4])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_d1_reg[5] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(\gic0.gc0.count_reg[9]_0 [5]), - .Q(\gic0.gc0.count_d1_reg[9]_0 [5])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_d1_reg[6] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(\gic0.gc0.count_reg[9]_0 [6]), - .Q(\gic0.gc0.count_d1_reg[9]_0 [6])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_d1_reg[7] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(\gic0.gc0.count_reg[9]_0 [7]), - .Q(\gic0.gc0.count_d1_reg[9]_0 [7])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_d1_reg[8] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(\gic0.gc0.count_reg[9]_0 [8]), - .Q(\gic0.gc0.count_d1_reg[9]_0 [8])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_d1_reg[9] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(\gic0.gc0.count_reg[9]_0 [9]), - .Q(\gic0.gc0.count_d1_reg[9]_0 [9])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_d2_reg[0] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(\gic0.gc0.count_d1_reg[9]_0 [0]), - .Q(Q[0])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_d2_reg[1] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(\gic0.gc0.count_d1_reg[9]_0 [1]), - .Q(Q[1])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_d2_reg[2] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(\gic0.gc0.count_d1_reg[9]_0 [2]), - .Q(Q[2])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_d2_reg[3] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(\gic0.gc0.count_d1_reg[9]_0 [3]), - .Q(Q[3])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_d2_reg[4] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(\gic0.gc0.count_d1_reg[9]_0 [4]), - .Q(Q[4])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_d2_reg[5] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(\gic0.gc0.count_d1_reg[9]_0 [5]), - .Q(Q[5])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_d2_reg[6] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(\gic0.gc0.count_d1_reg[9]_0 [6]), - .Q(Q[6])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_d2_reg[7] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(\gic0.gc0.count_d1_reg[9]_0 [7]), - .Q(Q[7])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_d2_reg[8] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(\gic0.gc0.count_d1_reg[9]_0 [8]), - .Q(Q[8])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_d2_reg[9] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(\gic0.gc0.count_d1_reg[9]_0 [9]), - .Q(Q[9])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_reg[0] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(plusOp[0]), - .Q(\gic0.gc0.count_reg[9]_0 [0])); - FDPE #( - .INIT(1'b1)) - \gic0.gc0.count_reg[1] - (.C(wr_clk), - .CE(E), - .D(plusOp[1]), - .PRE(AR), - .Q(\gic0.gc0.count_reg[9]_0 [1])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_reg[2] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(plusOp[2]), - .Q(\gic0.gc0.count_reg[9]_0 [2])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_reg[3] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(plusOp[3]), - .Q(\gic0.gc0.count_reg[9]_0 [3])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_reg[4] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(plusOp[4]), - .Q(\gic0.gc0.count_reg[9]_0 [4])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_reg[5] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(plusOp[5]), - .Q(\gic0.gc0.count_reg[9]_0 [5])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_reg[6] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(plusOp[6]), - .Q(\gic0.gc0.count_reg[9]_0 [6])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_reg[7] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(plusOp[7]), - .Q(\gic0.gc0.count_reg[9]_0 [7])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_reg[8] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(plusOp[8]), - .Q(\gic0.gc0.count_reg[9]_0 [8])); - FDCE #( - .INIT(1'b0)) - \gic0.gc0.count_reg[9] - (.C(wr_clk), - .CE(E), - .CLR(AR), - .D(plusOp[9]), - .Q(\gic0.gc0.count_reg[9]_0 [9])); -endmodule - -(* ORIG_REF_NAME = "wr_logic" *) -module fifo_AntCtrl_wr_logic - (full, - ram_full_fb_i_reg, - Q, - ram_full_fb_i_reg_0, - ram_full_fb_i_reg_1, - ram_full_fb_i_reg_2, - ram_full_fb_i_reg_3, - \gic0.gc0.count_d2_reg[9] , - \gic0.gc0.count_d2_reg[8] , - ram_full_fb_i_reg_4, - \gic0.gc0.count_d2_reg[9]_0 , - \gic0.gc0.count_d2_reg[7] , - \gic0.gc0.count_d2_reg[9]_1 , - \gic0.gc0.count_d2_reg[6] , - \gic0.gc0.count_d2_reg[9]_2 , - \gic0.gc0.count_d2_reg[8]_0 , - \gic0.gc0.count_d2_reg[8]_1 , - \gic0.gc0.count_d2_reg[7]_0 , - \gic0.gc0.count_reg[9] , - \gic0.gc0.count_d1_reg[9] , - v1_reg, - v1_reg_0, - wr_clk, - out, - wr_en, - ram_full_fb_i_reg_5, - AR); - output full; - output ram_full_fb_i_reg; - output [9:0]Q; - output ram_full_fb_i_reg_0; - output ram_full_fb_i_reg_1; - output ram_full_fb_i_reg_2; - output ram_full_fb_i_reg_3; - output \gic0.gc0.count_d2_reg[9] ; - output \gic0.gc0.count_d2_reg[8] ; - output ram_full_fb_i_reg_4; - output \gic0.gc0.count_d2_reg[9]_0 ; - output \gic0.gc0.count_d2_reg[7] ; - output \gic0.gc0.count_d2_reg[9]_1 ; - output \gic0.gc0.count_d2_reg[6] ; - output \gic0.gc0.count_d2_reg[9]_2 ; - output \gic0.gc0.count_d2_reg[8]_0 ; - output \gic0.gc0.count_d2_reg[8]_1 ; - output \gic0.gc0.count_d2_reg[7]_0 ; - output [9:0]\gic0.gc0.count_reg[9] ; - output [9:0]\gic0.gc0.count_d1_reg[9] ; - input [4:0]v1_reg; - input [4:0]v1_reg_0; - input wr_clk; - input out; - input wr_en; - input ram_full_fb_i_reg_5; - input [0:0]AR; - - wire [0:0]AR; - wire [9:0]Q; - wire full; - wire [9:0]\gic0.gc0.count_d1_reg[9] ; - wire \gic0.gc0.count_d2_reg[6] ; - wire \gic0.gc0.count_d2_reg[7] ; - wire \gic0.gc0.count_d2_reg[7]_0 ; - wire \gic0.gc0.count_d2_reg[8] ; - wire \gic0.gc0.count_d2_reg[8]_0 ; - wire \gic0.gc0.count_d2_reg[8]_1 ; - wire \gic0.gc0.count_d2_reg[9] ; - wire \gic0.gc0.count_d2_reg[9]_0 ; - wire \gic0.gc0.count_d2_reg[9]_1 ; - wire \gic0.gc0.count_d2_reg[9]_2 ; - wire [9:0]\gic0.gc0.count_reg[9] ; - wire \gwas.wsts_n_1 ; - wire out; - wire p_20_out; - wire ram_full_fb_i_reg; - wire ram_full_fb_i_reg_0; - wire ram_full_fb_i_reg_1; - wire ram_full_fb_i_reg_2; - wire ram_full_fb_i_reg_3; - wire ram_full_fb_i_reg_4; - wire ram_full_fb_i_reg_5; - wire [4:0]v1_reg; - wire [4:0]v1_reg_0; - wire wr_clk; - wire wr_en; - - fifo_AntCtrl_wr_status_flags_as \gwas.wsts - (.E(p_20_out), - .full(full), - .out(\gwas.wsts_n_1 ), - .ram_full_fb_i_reg_0(out), - .ram_full_fb_i_reg_1(ram_full_fb_i_reg_5), - .v1_reg(v1_reg), - .v1_reg_0(v1_reg_0), - .wr_clk(wr_clk), - .wr_en(wr_en)); - fifo_AntCtrl_wr_bin_cntr wpntr - (.AR(AR), - .E(p_20_out), - .Q(Q), - .\gic0.gc0.count_d1_reg[9]_0 (\gic0.gc0.count_d1_reg[9] ), - .\gic0.gc0.count_d2_reg[6]_0 (\gic0.gc0.count_d2_reg[6] ), - .\gic0.gc0.count_d2_reg[7]_0 (\gic0.gc0.count_d2_reg[7] ), - .\gic0.gc0.count_d2_reg[7]_1 (\gic0.gc0.count_d2_reg[7]_0 ), - .\gic0.gc0.count_d2_reg[8]_0 (\gic0.gc0.count_d2_reg[8] ), - .\gic0.gc0.count_d2_reg[8]_1 (\gic0.gc0.count_d2_reg[8]_0 ), - .\gic0.gc0.count_d2_reg[8]_2 (\gic0.gc0.count_d2_reg[8]_1 ), - .\gic0.gc0.count_d2_reg[9]_0 (\gic0.gc0.count_d2_reg[9] ), - .\gic0.gc0.count_d2_reg[9]_1 (\gic0.gc0.count_d2_reg[9]_0 ), - .\gic0.gc0.count_d2_reg[9]_2 (\gic0.gc0.count_d2_reg[9]_1 ), - .\gic0.gc0.count_d2_reg[9]_3 (\gic0.gc0.count_d2_reg[9]_2 ), - .\gic0.gc0.count_reg[9]_0 (\gic0.gc0.count_reg[9] ), - .out(\gwas.wsts_n_1 ), - .ram_full_fb_i_reg(ram_full_fb_i_reg), - .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), - .ram_full_fb_i_reg_1(ram_full_fb_i_reg_1), - .ram_full_fb_i_reg_2(ram_full_fb_i_reg_2), - .ram_full_fb_i_reg_3(ram_full_fb_i_reg_3), - .ram_full_fb_i_reg_4(ram_full_fb_i_reg_4), - .wr_clk(wr_clk), - .wr_en(wr_en)); -endmodule - -(* ORIG_REF_NAME = "wr_status_flags_as" *) -module fifo_AntCtrl_wr_status_flags_as - (full, - out, - E, - v1_reg, - v1_reg_0, - wr_clk, - ram_full_fb_i_reg_0, - wr_en, - ram_full_fb_i_reg_1); - output full; - output out; - output [0:0]E; - input [4:0]v1_reg; - input [4:0]v1_reg_0; - input wr_clk; - input ram_full_fb_i_reg_0; - input wr_en; - input ram_full_fb_i_reg_1; - - wire [0:0]E; - wire c2_n_0; - wire comp1; - (* DONT_TOUCH *) wire ram_full_fb_i; - wire ram_full_fb_i_reg_0; - wire ram_full_fb_i_reg_1; - (* DONT_TOUCH *) wire ram_full_i; - wire [4:0]v1_reg; - wire [4:0]v1_reg_0; - wire wr_clk; - wire wr_en; - - assign full = ram_full_i; - assign out = ram_full_fb_i; - fifo_AntCtrl_compare c1 - (.comp1(comp1), - .v1_reg(v1_reg)); - fifo_AntCtrl_compare_0 c2 - (.comp1(comp1), - .out(ram_full_fb_i), - .ram_full_fb_i_reg(c2_n_0), - .ram_full_fb_i_reg_0(ram_full_fb_i_reg_1), - .v1_reg_0(v1_reg_0), - .wr_en(wr_en)); - LUT2 #( - .INIT(4'h2)) - \gic0.gc0.count_d1[9]_i_1 - (.I0(wr_en), - .I1(ram_full_fb_i), - .O(E)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* equivalent_register_removal = "no" *) - FDPE #( - .INIT(1'b1)) - ram_full_fb_i_reg - (.C(wr_clk), - .CE(1'b1), - .D(c2_n_0), - .PRE(ram_full_fb_i_reg_0), - .Q(ram_full_fb_i)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* equivalent_register_removal = "no" *) - FDPE #( - .INIT(1'b1)) - ram_full_i_reg - (.C(wr_clk), - .CE(1'b1), - .D(c2_n_0), - .PRE(ram_full_fb_i_reg_0), - .Q(ram_full_i)); -endmodule -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.vhdl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.vhdl deleted file mode 100644 index b7d8709f..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.vhdl +++ /dev/null @@ -1,7376 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:33:47 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.vhdl --- Design : fifo_AntCtrl --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_xpm_cdc_async_rst is - port ( - src_arst : in STD_LOGIC; - dest_clk : in STD_LOGIC; - dest_arst : out STD_LOGIC - ); - attribute DEF_VAL : string; - attribute DEF_VAL of fifo_AntCtrl_xpm_cdc_async_rst : entity is "1'b0"; - attribute DEST_SYNC_FF : integer; - attribute DEST_SYNC_FF of fifo_AntCtrl_xpm_cdc_async_rst : entity is 2; - attribute INIT_SYNC_FF : integer; - attribute INIT_SYNC_FF of fifo_AntCtrl_xpm_cdc_async_rst : entity is 0; - attribute INV_DEF_VAL : string; - attribute INV_DEF_VAL of fifo_AntCtrl_xpm_cdc_async_rst : entity is "1'b1"; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_xpm_cdc_async_rst : entity is "xpm_cdc_async_rst"; - attribute RST_ACTIVE_HIGH : integer; - attribute RST_ACTIVE_HIGH of fifo_AntCtrl_xpm_cdc_async_rst : entity is 1; - attribute VERSION : integer; - attribute VERSION of fifo_AntCtrl_xpm_cdc_async_rst : entity is 0; - attribute XPM_MODULE : string; - attribute XPM_MODULE of fifo_AntCtrl_xpm_cdc_async_rst : entity is "TRUE"; - attribute xpm_cdc : string; - attribute xpm_cdc of fifo_AntCtrl_xpm_cdc_async_rst : entity is "ASYNC_RST"; -end fifo_AntCtrl_xpm_cdc_async_rst; - -architecture STRUCTURE of fifo_AntCtrl_xpm_cdc_async_rst is - signal arststages_ff : STD_LOGIC_VECTOR ( 1 downto 0 ); - attribute RTL_KEEP : string; - attribute RTL_KEEP of arststages_ff : signal is "true"; - attribute async_reg : string; - attribute async_reg of arststages_ff : signal is "true"; - attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST"; - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \arststages_ff_reg[0]\ : label is "true"; - attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST"; - attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true; - attribute KEEP of \arststages_ff_reg[1]\ : label is "true"; - attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST"; -begin - dest_arst <= arststages_ff(1); -\arststages_ff_reg[0]\: unisim.vcomponents.FDPE - generic map( - INIT => '0' - ) - port map ( - C => dest_clk, - CE => '1', - D => '0', - PRE => src_arst, - Q => arststages_ff(0) - ); -\arststages_ff_reg[1]\: unisim.vcomponents.FDPE - generic map( - INIT => '0' - ) - port map ( - C => dest_clk, - CE => '1', - D => arststages_ff(0), - PRE => src_arst, - Q => arststages_ff(1) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \fifo_AntCtrl_xpm_cdc_async_rst__2\ is - port ( - src_arst : in STD_LOGIC; - dest_clk : in STD_LOGIC; - dest_arst : out STD_LOGIC - ); - attribute DEF_VAL : string; - attribute DEF_VAL of \fifo_AntCtrl_xpm_cdc_async_rst__2\ : entity is "1'b0"; - attribute DEST_SYNC_FF : integer; - attribute DEST_SYNC_FF of \fifo_AntCtrl_xpm_cdc_async_rst__2\ : entity is 2; - attribute INIT_SYNC_FF : integer; - attribute INIT_SYNC_FF of \fifo_AntCtrl_xpm_cdc_async_rst__2\ : entity is 0; - attribute INV_DEF_VAL : string; - attribute INV_DEF_VAL of \fifo_AntCtrl_xpm_cdc_async_rst__2\ : entity is "1'b1"; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \fifo_AntCtrl_xpm_cdc_async_rst__2\ : entity is "xpm_cdc_async_rst"; - attribute RST_ACTIVE_HIGH : integer; - attribute RST_ACTIVE_HIGH of \fifo_AntCtrl_xpm_cdc_async_rst__2\ : entity is 1; - attribute VERSION : integer; - attribute VERSION of \fifo_AntCtrl_xpm_cdc_async_rst__2\ : entity is 0; - attribute XPM_MODULE : string; - attribute XPM_MODULE of \fifo_AntCtrl_xpm_cdc_async_rst__2\ : entity is "TRUE"; - attribute xpm_cdc : string; - attribute xpm_cdc of \fifo_AntCtrl_xpm_cdc_async_rst__2\ : entity is "ASYNC_RST"; -end \fifo_AntCtrl_xpm_cdc_async_rst__2\; - -architecture STRUCTURE of \fifo_AntCtrl_xpm_cdc_async_rst__2\ is - signal arststages_ff : STD_LOGIC_VECTOR ( 1 downto 0 ); - attribute RTL_KEEP : string; - attribute RTL_KEEP of arststages_ff : signal is "true"; - attribute async_reg : string; - attribute async_reg of arststages_ff : signal is "true"; - attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST"; - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \arststages_ff_reg[0]\ : label is "true"; - attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST"; - attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true; - attribute KEEP of \arststages_ff_reg[1]\ : label is "true"; - attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST"; -begin - dest_arst <= arststages_ff(1); -\arststages_ff_reg[0]\: unisim.vcomponents.FDPE - generic map( - INIT => '0' - ) - port map ( - C => dest_clk, - CE => '1', - D => '0', - PRE => src_arst, - Q => arststages_ff(0) - ); -\arststages_ff_reg[1]\: unisim.vcomponents.FDPE - generic map( - INIT => '0' - ) - port map ( - C => dest_clk, - CE => '1', - D => arststages_ff(0), - PRE => src_arst, - Q => arststages_ff(1) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_xpm_cdc_gray is - port ( - src_clk : in STD_LOGIC; - src_in_bin : in STD_LOGIC_VECTOR ( 9 downto 0 ); - dest_clk : in STD_LOGIC; - dest_out_bin : out STD_LOGIC_VECTOR ( 9 downto 0 ) - ); - attribute DEST_SYNC_FF : integer; - attribute DEST_SYNC_FF of fifo_AntCtrl_xpm_cdc_gray : entity is 2; - attribute INIT_SYNC_FF : integer; - attribute INIT_SYNC_FF of fifo_AntCtrl_xpm_cdc_gray : entity is 0; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_xpm_cdc_gray : entity is "xpm_cdc_gray"; - attribute REG_OUTPUT : integer; - attribute REG_OUTPUT of fifo_AntCtrl_xpm_cdc_gray : entity is 1; - attribute SIM_ASSERT_CHK : integer; - attribute SIM_ASSERT_CHK of fifo_AntCtrl_xpm_cdc_gray : entity is 0; - attribute SIM_LOSSLESS_GRAY_CHK : integer; - attribute SIM_LOSSLESS_GRAY_CHK of fifo_AntCtrl_xpm_cdc_gray : entity is 0; - attribute VERSION : integer; - attribute VERSION of fifo_AntCtrl_xpm_cdc_gray : entity is 0; - attribute WIDTH : integer; - attribute WIDTH of fifo_AntCtrl_xpm_cdc_gray : entity is 10; - attribute XPM_MODULE : string; - attribute XPM_MODULE of fifo_AntCtrl_xpm_cdc_gray : entity is "TRUE"; - attribute xpm_cdc : string; - attribute xpm_cdc of fifo_AntCtrl_xpm_cdc_gray : entity is "GRAY"; -end fifo_AntCtrl_xpm_cdc_gray; - -architecture STRUCTURE of fifo_AntCtrl_xpm_cdc_gray is - signal async_path : STD_LOGIC_VECTOR ( 9 downto 0 ); - signal binval : STD_LOGIC_VECTOR ( 8 downto 0 ); - signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); - attribute RTL_KEEP : string; - attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; - attribute async_reg : string; - attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; - attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; - signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); - attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; - attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; - attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; - signal gray_enc : STD_LOGIC_VECTOR ( 8 downto 0 ); - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][8]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[0][8]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[0][8]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][9]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[0][9]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[0][9]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][8]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[1][8]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[1][8]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][9]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[1][9]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[1][9]\ : label is "GRAY"; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair4"; - attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair4"; - attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair5"; - attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair5"; - attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair7"; - attribute SOFT_HLUTNM of \src_gray_ff[7]_i_1\ : label is "soft_lutpair7"; -begin -\dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => async_path(0), - Q => \dest_graysync_ff[0]\(0), - R => '0' - ); -\dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => async_path(1), - Q => \dest_graysync_ff[0]\(1), - R => '0' - ); -\dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => async_path(2), - Q => \dest_graysync_ff[0]\(2), - R => '0' - ); -\dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => async_path(3), - Q => \dest_graysync_ff[0]\(3), - R => '0' - ); -\dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => async_path(4), - Q => \dest_graysync_ff[0]\(4), - R => '0' - ); -\dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => async_path(5), - Q => \dest_graysync_ff[0]\(5), - R => '0' - ); -\dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => async_path(6), - Q => \dest_graysync_ff[0]\(6), - R => '0' - ); -\dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => async_path(7), - Q => \dest_graysync_ff[0]\(7), - R => '0' - ); -\dest_graysync_ff_reg[0][8]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => async_path(8), - Q => \dest_graysync_ff[0]\(8), - R => '0' - ); -\dest_graysync_ff_reg[0][9]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => async_path(9), - Q => \dest_graysync_ff[0]\(9), - R => '0' - ); -\dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[0]\(0), - Q => \dest_graysync_ff[1]\(0), - R => '0' - ); -\dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[0]\(1), - Q => \dest_graysync_ff[1]\(1), - R => '0' - ); -\dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[0]\(2), - Q => \dest_graysync_ff[1]\(2), - R => '0' - ); -\dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[0]\(3), - Q => \dest_graysync_ff[1]\(3), - R => '0' - ); -\dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[0]\(4), - Q => \dest_graysync_ff[1]\(4), - R => '0' - ); -\dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[0]\(5), - Q => \dest_graysync_ff[1]\(5), - R => '0' - ); -\dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[0]\(6), - Q => \dest_graysync_ff[1]\(6), - R => '0' - ); -\dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[0]\(7), - Q => \dest_graysync_ff[1]\(7), - R => '0' - ); -\dest_graysync_ff_reg[1][8]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[0]\(8), - Q => \dest_graysync_ff[1]\(8), - R => '0' - ); -\dest_graysync_ff_reg[1][9]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[0]\(9), - Q => \dest_graysync_ff[1]\(9), - R => '0' - ); -\dest_out_bin_ff[0]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"96696996" - ) - port map ( - I0 => \dest_graysync_ff[1]\(0), - I1 => \dest_graysync_ff[1]\(2), - I2 => binval(4), - I3 => \dest_graysync_ff[1]\(3), - I4 => \dest_graysync_ff[1]\(1), - O => binval(0) - ); -\dest_out_bin_ff[1]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"6996" - ) - port map ( - I0 => \dest_graysync_ff[1]\(1), - I1 => \dest_graysync_ff[1]\(3), - I2 => binval(4), - I3 => \dest_graysync_ff[1]\(2), - O => binval(1) - ); -\dest_out_bin_ff[2]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"96" - ) - port map ( - I0 => \dest_graysync_ff[1]\(2), - I1 => binval(4), - I2 => \dest_graysync_ff[1]\(3), - O => binval(2) - ); -\dest_out_bin_ff[3]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \dest_graysync_ff[1]\(3), - I1 => binval(4), - O => binval(3) - ); -\dest_out_bin_ff[4]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"6996966996696996" - ) - port map ( - I0 => \dest_graysync_ff[1]\(4), - I1 => \dest_graysync_ff[1]\(6), - I2 => \dest_graysync_ff[1]\(8), - I3 => \dest_graysync_ff[1]\(9), - I4 => \dest_graysync_ff[1]\(7), - I5 => \dest_graysync_ff[1]\(5), - O => binval(4) - ); -\dest_out_bin_ff[5]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"96696996" - ) - port map ( - I0 => \dest_graysync_ff[1]\(5), - I1 => \dest_graysync_ff[1]\(7), - I2 => \dest_graysync_ff[1]\(9), - I3 => \dest_graysync_ff[1]\(8), - I4 => \dest_graysync_ff[1]\(6), - O => binval(5) - ); -\dest_out_bin_ff[6]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"6996" - ) - port map ( - I0 => \dest_graysync_ff[1]\(6), - I1 => \dest_graysync_ff[1]\(8), - I2 => \dest_graysync_ff[1]\(9), - I3 => \dest_graysync_ff[1]\(7), - O => binval(6) - ); -\dest_out_bin_ff[7]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"96" - ) - port map ( - I0 => \dest_graysync_ff[1]\(7), - I1 => \dest_graysync_ff[1]\(9), - I2 => \dest_graysync_ff[1]\(8), - O => binval(7) - ); -\dest_out_bin_ff[8]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \dest_graysync_ff[1]\(8), - I1 => \dest_graysync_ff[1]\(9), - O => binval(8) - ); -\dest_out_bin_ff_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => binval(0), - Q => dest_out_bin(0), - R => '0' - ); -\dest_out_bin_ff_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => binval(1), - Q => dest_out_bin(1), - R => '0' - ); -\dest_out_bin_ff_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => binval(2), - Q => dest_out_bin(2), - R => '0' - ); -\dest_out_bin_ff_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => binval(3), - Q => dest_out_bin(3), - R => '0' - ); -\dest_out_bin_ff_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => binval(4), - Q => dest_out_bin(4), - R => '0' - ); -\dest_out_bin_ff_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => binval(5), - Q => dest_out_bin(5), - R => '0' - ); -\dest_out_bin_ff_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => binval(6), - Q => dest_out_bin(6), - R => '0' - ); -\dest_out_bin_ff_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => binval(7), - Q => dest_out_bin(7), - R => '0' - ); -\dest_out_bin_ff_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => binval(8), - Q => dest_out_bin(8), - R => '0' - ); -\dest_out_bin_ff_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[1]\(9), - Q => dest_out_bin(9), - R => '0' - ); -\src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => src_in_bin(1), - I1 => src_in_bin(0), - O => gray_enc(0) - ); -\src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => src_in_bin(2), - I1 => src_in_bin(1), - O => gray_enc(1) - ); -\src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => src_in_bin(3), - I1 => src_in_bin(2), - O => gray_enc(2) - ); -\src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => src_in_bin(4), - I1 => src_in_bin(3), - O => gray_enc(3) - ); -\src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => src_in_bin(5), - I1 => src_in_bin(4), - O => gray_enc(4) - ); -\src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => src_in_bin(6), - I1 => src_in_bin(5), - O => gray_enc(5) - ); -\src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => src_in_bin(7), - I1 => src_in_bin(6), - O => gray_enc(6) - ); -\src_gray_ff[7]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => src_in_bin(8), - I1 => src_in_bin(7), - O => gray_enc(7) - ); -\src_gray_ff[8]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => src_in_bin(9), - I1 => src_in_bin(8), - O => gray_enc(8) - ); -\src_gray_ff_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => src_clk, - CE => '1', - D => gray_enc(0), - Q => async_path(0), - R => '0' - ); -\src_gray_ff_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => src_clk, - CE => '1', - D => gray_enc(1), - Q => async_path(1), - R => '0' - ); -\src_gray_ff_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => src_clk, - CE => '1', - D => gray_enc(2), - Q => async_path(2), - R => '0' - ); -\src_gray_ff_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => src_clk, - CE => '1', - D => gray_enc(3), - Q => async_path(3), - R => '0' - ); -\src_gray_ff_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => src_clk, - CE => '1', - D => gray_enc(4), - Q => async_path(4), - R => '0' - ); -\src_gray_ff_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => src_clk, - CE => '1', - D => gray_enc(5), - Q => async_path(5), - R => '0' - ); -\src_gray_ff_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => src_clk, - CE => '1', - D => gray_enc(6), - Q => async_path(6), - R => '0' - ); -\src_gray_ff_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => src_clk, - CE => '1', - D => gray_enc(7), - Q => async_path(7), - R => '0' - ); -\src_gray_ff_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => src_clk, - CE => '1', - D => gray_enc(8), - Q => async_path(8), - R => '0' - ); -\src_gray_ff_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => src_clk, - CE => '1', - D => src_in_bin(9), - Q => async_path(9), - R => '0' - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \fifo_AntCtrl_xpm_cdc_gray__2\ is - port ( - src_clk : in STD_LOGIC; - src_in_bin : in STD_LOGIC_VECTOR ( 9 downto 0 ); - dest_clk : in STD_LOGIC; - dest_out_bin : out STD_LOGIC_VECTOR ( 9 downto 0 ) - ); - attribute DEST_SYNC_FF : integer; - attribute DEST_SYNC_FF of \fifo_AntCtrl_xpm_cdc_gray__2\ : entity is 2; - attribute INIT_SYNC_FF : integer; - attribute INIT_SYNC_FF of \fifo_AntCtrl_xpm_cdc_gray__2\ : entity is 0; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \fifo_AntCtrl_xpm_cdc_gray__2\ : entity is "xpm_cdc_gray"; - attribute REG_OUTPUT : integer; - attribute REG_OUTPUT of \fifo_AntCtrl_xpm_cdc_gray__2\ : entity is 1; - attribute SIM_ASSERT_CHK : integer; - attribute SIM_ASSERT_CHK of \fifo_AntCtrl_xpm_cdc_gray__2\ : entity is 0; - attribute SIM_LOSSLESS_GRAY_CHK : integer; - attribute SIM_LOSSLESS_GRAY_CHK of \fifo_AntCtrl_xpm_cdc_gray__2\ : entity is 0; - attribute VERSION : integer; - attribute VERSION of \fifo_AntCtrl_xpm_cdc_gray__2\ : entity is 0; - attribute WIDTH : integer; - attribute WIDTH of \fifo_AntCtrl_xpm_cdc_gray__2\ : entity is 10; - attribute XPM_MODULE : string; - attribute XPM_MODULE of \fifo_AntCtrl_xpm_cdc_gray__2\ : entity is "TRUE"; - attribute xpm_cdc : string; - attribute xpm_cdc of \fifo_AntCtrl_xpm_cdc_gray__2\ : entity is "GRAY"; -end \fifo_AntCtrl_xpm_cdc_gray__2\; - -architecture STRUCTURE of \fifo_AntCtrl_xpm_cdc_gray__2\ is - signal async_path : STD_LOGIC_VECTOR ( 9 downto 0 ); - signal binval : STD_LOGIC_VECTOR ( 8 downto 0 ); - signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); - attribute RTL_KEEP : string; - attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; - attribute async_reg : string; - attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; - attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; - signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); - attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; - attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; - attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; - signal gray_enc : STD_LOGIC_VECTOR ( 8 downto 0 ); - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][8]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[0][8]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[0][8]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][9]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[0][9]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[0][9]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][8]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[1][8]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[1][8]\ : label is "GRAY"; - attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][9]\ : label is std.standard.true; - attribute KEEP of \dest_graysync_ff_reg[1][9]\ : label is "true"; - attribute XPM_CDC of \dest_graysync_ff_reg[1][9]\ : label is "GRAY"; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair3"; - attribute SOFT_HLUTNM of \src_gray_ff[7]_i_1\ : label is "soft_lutpair3"; -begin -\dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => async_path(0), - Q => \dest_graysync_ff[0]\(0), - R => '0' - ); -\dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => async_path(1), - Q => \dest_graysync_ff[0]\(1), - R => '0' - ); -\dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => async_path(2), - Q => \dest_graysync_ff[0]\(2), - R => '0' - ); -\dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => async_path(3), - Q => \dest_graysync_ff[0]\(3), - R => '0' - ); -\dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => async_path(4), - Q => \dest_graysync_ff[0]\(4), - R => '0' - ); -\dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => async_path(5), - Q => \dest_graysync_ff[0]\(5), - R => '0' - ); -\dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => async_path(6), - Q => \dest_graysync_ff[0]\(6), - R => '0' - ); -\dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => async_path(7), - Q => \dest_graysync_ff[0]\(7), - R => '0' - ); -\dest_graysync_ff_reg[0][8]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => async_path(8), - Q => \dest_graysync_ff[0]\(8), - R => '0' - ); -\dest_graysync_ff_reg[0][9]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => async_path(9), - Q => \dest_graysync_ff[0]\(9), - R => '0' - ); -\dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[0]\(0), - Q => \dest_graysync_ff[1]\(0), - R => '0' - ); -\dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[0]\(1), - Q => \dest_graysync_ff[1]\(1), - R => '0' - ); -\dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[0]\(2), - Q => \dest_graysync_ff[1]\(2), - R => '0' - ); -\dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[0]\(3), - Q => \dest_graysync_ff[1]\(3), - R => '0' - ); -\dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[0]\(4), - Q => \dest_graysync_ff[1]\(4), - R => '0' - ); -\dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[0]\(5), - Q => \dest_graysync_ff[1]\(5), - R => '0' - ); -\dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[0]\(6), - Q => \dest_graysync_ff[1]\(6), - R => '0' - ); -\dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[0]\(7), - Q => \dest_graysync_ff[1]\(7), - R => '0' - ); -\dest_graysync_ff_reg[1][8]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[0]\(8), - Q => \dest_graysync_ff[1]\(8), - R => '0' - ); -\dest_graysync_ff_reg[1][9]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[0]\(9), - Q => \dest_graysync_ff[1]\(9), - R => '0' - ); -\dest_out_bin_ff[0]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"96696996" - ) - port map ( - I0 => \dest_graysync_ff[1]\(0), - I1 => \dest_graysync_ff[1]\(2), - I2 => binval(4), - I3 => \dest_graysync_ff[1]\(3), - I4 => \dest_graysync_ff[1]\(1), - O => binval(0) - ); -\dest_out_bin_ff[1]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"6996" - ) - port map ( - I0 => \dest_graysync_ff[1]\(1), - I1 => \dest_graysync_ff[1]\(3), - I2 => binval(4), - I3 => \dest_graysync_ff[1]\(2), - O => binval(1) - ); -\dest_out_bin_ff[2]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"96" - ) - port map ( - I0 => \dest_graysync_ff[1]\(2), - I1 => binval(4), - I2 => \dest_graysync_ff[1]\(3), - O => binval(2) - ); -\dest_out_bin_ff[3]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \dest_graysync_ff[1]\(3), - I1 => binval(4), - O => binval(3) - ); -\dest_out_bin_ff[4]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"6996966996696996" - ) - port map ( - I0 => \dest_graysync_ff[1]\(4), - I1 => \dest_graysync_ff[1]\(6), - I2 => \dest_graysync_ff[1]\(8), - I3 => \dest_graysync_ff[1]\(9), - I4 => \dest_graysync_ff[1]\(7), - I5 => \dest_graysync_ff[1]\(5), - O => binval(4) - ); -\dest_out_bin_ff[5]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"96696996" - ) - port map ( - I0 => \dest_graysync_ff[1]\(5), - I1 => \dest_graysync_ff[1]\(7), - I2 => \dest_graysync_ff[1]\(9), - I3 => \dest_graysync_ff[1]\(8), - I4 => \dest_graysync_ff[1]\(6), - O => binval(5) - ); -\dest_out_bin_ff[6]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"6996" - ) - port map ( - I0 => \dest_graysync_ff[1]\(6), - I1 => \dest_graysync_ff[1]\(8), - I2 => \dest_graysync_ff[1]\(9), - I3 => \dest_graysync_ff[1]\(7), - O => binval(6) - ); -\dest_out_bin_ff[7]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"96" - ) - port map ( - I0 => \dest_graysync_ff[1]\(7), - I1 => \dest_graysync_ff[1]\(9), - I2 => \dest_graysync_ff[1]\(8), - O => binval(7) - ); -\dest_out_bin_ff[8]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \dest_graysync_ff[1]\(8), - I1 => \dest_graysync_ff[1]\(9), - O => binval(8) - ); -\dest_out_bin_ff_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => binval(0), - Q => dest_out_bin(0), - R => '0' - ); -\dest_out_bin_ff_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => binval(1), - Q => dest_out_bin(1), - R => '0' - ); -\dest_out_bin_ff_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => binval(2), - Q => dest_out_bin(2), - R => '0' - ); -\dest_out_bin_ff_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => binval(3), - Q => dest_out_bin(3), - R => '0' - ); -\dest_out_bin_ff_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => binval(4), - Q => dest_out_bin(4), - R => '0' - ); -\dest_out_bin_ff_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => binval(5), - Q => dest_out_bin(5), - R => '0' - ); -\dest_out_bin_ff_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => binval(6), - Q => dest_out_bin(6), - R => '0' - ); -\dest_out_bin_ff_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => binval(7), - Q => dest_out_bin(7), - R => '0' - ); -\dest_out_bin_ff_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => binval(8), - Q => dest_out_bin(8), - R => '0' - ); -\dest_out_bin_ff_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => \dest_graysync_ff[1]\(9), - Q => dest_out_bin(9), - R => '0' - ); -\src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => src_in_bin(1), - I1 => src_in_bin(0), - O => gray_enc(0) - ); -\src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => src_in_bin(2), - I1 => src_in_bin(1), - O => gray_enc(1) - ); -\src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => src_in_bin(3), - I1 => src_in_bin(2), - O => gray_enc(2) - ); -\src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => src_in_bin(4), - I1 => src_in_bin(3), - O => gray_enc(3) - ); -\src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => src_in_bin(5), - I1 => src_in_bin(4), - O => gray_enc(4) - ); -\src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => src_in_bin(6), - I1 => src_in_bin(5), - O => gray_enc(5) - ); -\src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => src_in_bin(7), - I1 => src_in_bin(6), - O => gray_enc(6) - ); -\src_gray_ff[7]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => src_in_bin(8), - I1 => src_in_bin(7), - O => gray_enc(7) - ); -\src_gray_ff[8]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => src_in_bin(9), - I1 => src_in_bin(8), - O => gray_enc(8) - ); -\src_gray_ff_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => src_clk, - CE => '1', - D => gray_enc(0), - Q => async_path(0), - R => '0' - ); -\src_gray_ff_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => src_clk, - CE => '1', - D => gray_enc(1), - Q => async_path(1), - R => '0' - ); -\src_gray_ff_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => src_clk, - CE => '1', - D => gray_enc(2), - Q => async_path(2), - R => '0' - ); -\src_gray_ff_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => src_clk, - CE => '1', - D => gray_enc(3), - Q => async_path(3), - R => '0' - ); -\src_gray_ff_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => src_clk, - CE => '1', - D => gray_enc(4), - Q => async_path(4), - R => '0' - ); -\src_gray_ff_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => src_clk, - CE => '1', - D => gray_enc(5), - Q => async_path(5), - R => '0' - ); -\src_gray_ff_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => src_clk, - CE => '1', - D => gray_enc(6), - Q => async_path(6), - R => '0' - ); -\src_gray_ff_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => src_clk, - CE => '1', - D => gray_enc(7), - Q => async_path(7), - R => '0' - ); -\src_gray_ff_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => src_clk, - CE => '1', - D => gray_enc(8), - Q => async_path(8), - R => '0' - ); -\src_gray_ff_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => src_clk, - CE => '1', - D => src_in_bin(9), - Q => async_path(9), - R => '0' - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_xpm_cdc_single is - port ( - src_clk : in STD_LOGIC; - src_in : in STD_LOGIC; - dest_clk : in STD_LOGIC; - dest_out : out STD_LOGIC - ); - attribute DEST_SYNC_FF : integer; - attribute DEST_SYNC_FF of fifo_AntCtrl_xpm_cdc_single : entity is 4; - attribute INIT_SYNC_FF : integer; - attribute INIT_SYNC_FF of fifo_AntCtrl_xpm_cdc_single : entity is 0; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_xpm_cdc_single : entity is "xpm_cdc_single"; - attribute SIM_ASSERT_CHK : integer; - attribute SIM_ASSERT_CHK of fifo_AntCtrl_xpm_cdc_single : entity is 0; - attribute SRC_INPUT_REG : integer; - attribute SRC_INPUT_REG of fifo_AntCtrl_xpm_cdc_single : entity is 0; - attribute VERSION : integer; - attribute VERSION of fifo_AntCtrl_xpm_cdc_single : entity is 0; - attribute XPM_MODULE : string; - attribute XPM_MODULE of fifo_AntCtrl_xpm_cdc_single : entity is "TRUE"; - attribute xpm_cdc : string; - attribute xpm_cdc of fifo_AntCtrl_xpm_cdc_single : entity is "SINGLE"; -end fifo_AntCtrl_xpm_cdc_single; - -architecture STRUCTURE of fifo_AntCtrl_xpm_cdc_single is - signal syncstages_ff : STD_LOGIC_VECTOR ( 3 downto 0 ); - attribute RTL_KEEP : string; - attribute RTL_KEEP of syncstages_ff : signal is "true"; - attribute async_reg : string; - attribute async_reg of syncstages_ff : signal is "true"; - attribute xpm_cdc of syncstages_ff : signal is "SINGLE"; - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \syncstages_ff_reg[0]\ : label is "true"; - attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE"; - attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true; - attribute KEEP of \syncstages_ff_reg[1]\ : label is "true"; - attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE"; - attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true; - attribute KEEP of \syncstages_ff_reg[2]\ : label is "true"; - attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE"; - attribute ASYNC_REG_boolean of \syncstages_ff_reg[3]\ : label is std.standard.true; - attribute KEEP of \syncstages_ff_reg[3]\ : label is "true"; - attribute XPM_CDC of \syncstages_ff_reg[3]\ : label is "SINGLE"; -begin - dest_out <= syncstages_ff(3); -\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => src_in, - Q => syncstages_ff(0), - R => '0' - ); -\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => syncstages_ff(0), - Q => syncstages_ff(1), - R => '0' - ); -\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => syncstages_ff(1), - Q => syncstages_ff(2), - R => '0' - ); -\syncstages_ff_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => syncstages_ff(2), - Q => syncstages_ff(3), - R => '0' - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \fifo_AntCtrl_xpm_cdc_single__2\ is - port ( - src_clk : in STD_LOGIC; - src_in : in STD_LOGIC; - dest_clk : in STD_LOGIC; - dest_out : out STD_LOGIC - ); - attribute DEST_SYNC_FF : integer; - attribute DEST_SYNC_FF of \fifo_AntCtrl_xpm_cdc_single__2\ : entity is 4; - attribute INIT_SYNC_FF : integer; - attribute INIT_SYNC_FF of \fifo_AntCtrl_xpm_cdc_single__2\ : entity is 0; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \fifo_AntCtrl_xpm_cdc_single__2\ : entity is "xpm_cdc_single"; - attribute SIM_ASSERT_CHK : integer; - attribute SIM_ASSERT_CHK of \fifo_AntCtrl_xpm_cdc_single__2\ : entity is 0; - attribute SRC_INPUT_REG : integer; - attribute SRC_INPUT_REG of \fifo_AntCtrl_xpm_cdc_single__2\ : entity is 0; - attribute VERSION : integer; - attribute VERSION of \fifo_AntCtrl_xpm_cdc_single__2\ : entity is 0; - attribute XPM_MODULE : string; - attribute XPM_MODULE of \fifo_AntCtrl_xpm_cdc_single__2\ : entity is "TRUE"; - attribute xpm_cdc : string; - attribute xpm_cdc of \fifo_AntCtrl_xpm_cdc_single__2\ : entity is "SINGLE"; -end \fifo_AntCtrl_xpm_cdc_single__2\; - -architecture STRUCTURE of \fifo_AntCtrl_xpm_cdc_single__2\ is - signal syncstages_ff : STD_LOGIC_VECTOR ( 3 downto 0 ); - attribute RTL_KEEP : string; - attribute RTL_KEEP of syncstages_ff : signal is "true"; - attribute async_reg : string; - attribute async_reg of syncstages_ff : signal is "true"; - attribute xpm_cdc of syncstages_ff : signal is "SINGLE"; - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \syncstages_ff_reg[0]\ : label is "true"; - attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE"; - attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true; - attribute KEEP of \syncstages_ff_reg[1]\ : label is "true"; - attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE"; - attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true; - attribute KEEP of \syncstages_ff_reg[2]\ : label is "true"; - attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE"; - attribute ASYNC_REG_boolean of \syncstages_ff_reg[3]\ : label is std.standard.true; - attribute KEEP of \syncstages_ff_reg[3]\ : label is "true"; - attribute XPM_CDC of \syncstages_ff_reg[3]\ : label is "SINGLE"; -begin - dest_out <= syncstages_ff(3); -\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => src_in, - Q => syncstages_ff(0), - R => '0' - ); -\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => syncstages_ff(0), - Q => syncstages_ff(1), - R => '0' - ); -\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => syncstages_ff(1), - Q => syncstages_ff(2), - R => '0' - ); -\syncstages_ff_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => dest_clk, - CE => '1', - D => syncstages_ff(2), - Q => syncstages_ff(3), - R => '0' - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_compare is - port ( - comp1 : out STD_LOGIC; - v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_compare : entity is "compare"; -end fifo_AntCtrl_compare; - -architecture STRUCTURE of fifo_AntCtrl_compare is - signal carrynet_0 : STD_LOGIC; - signal carrynet_1 : STD_LOGIC; - signal carrynet_2 : STD_LOGIC; - signal carrynet_3 : STD_LOGIC; - signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - attribute OPT_MODIFIED : string; - attribute OPT_MODIFIED of \gmux.gm[0].gm1.m1_CARRY4\ : label is "MLO"; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)"; - attribute box_type : string; - attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE"; - attribute OPT_MODIFIED of \gmux.gm[4].gms.ms_CARRY4\ : label is "MLO"; - attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)"; - attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE"; -begin -\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => carrynet_3, - CO(2) => carrynet_2, - CO(1) => carrynet_1, - CO(0) => carrynet_0, - CYINIT => '1', - DI(3 downto 0) => B"0000", - O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0), - S(3 downto 0) => v1_reg(3 downto 0) - ); -\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4 - port map ( - CI => carrynet_3, - CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1), - CO(0) => comp1, - CYINIT => '0', - DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1), - DI(0) => '0', - O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0), - S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1), - S(0) => v1_reg(4) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_compare_0 is - port ( - ram_full_fb_i_reg : out STD_LOGIC; - v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 ); - \out\ : in STD_LOGIC; - wr_en : in STD_LOGIC; - comp1 : in STD_LOGIC; - ram_full_fb_i_reg_0 : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_compare_0 : entity is "compare"; -end fifo_AntCtrl_compare_0; - -architecture STRUCTURE of fifo_AntCtrl_compare_0 is - signal carrynet_0 : STD_LOGIC; - signal carrynet_1 : STD_LOGIC; - signal carrynet_2 : STD_LOGIC; - signal carrynet_3 : STD_LOGIC; - signal comp2 : STD_LOGIC; - signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - attribute OPT_MODIFIED : string; - attribute OPT_MODIFIED of \gmux.gm[0].gm1.m1_CARRY4\ : label is "MLO"; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)"; - attribute box_type : string; - attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE"; - attribute OPT_MODIFIED of \gmux.gm[4].gms.ms_CARRY4\ : label is "MLO"; - attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)"; - attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE"; -begin -\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => carrynet_3, - CO(2) => carrynet_2, - CO(1) => carrynet_1, - CO(0) => carrynet_0, - CYINIT => '1', - DI(3 downto 0) => B"0000", - O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0), - S(3 downto 0) => v1_reg_0(3 downto 0) - ); -\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4 - port map ( - CI => carrynet_3, - CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1), - CO(0) => comp2, - CYINIT => '0', - DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1), - DI(0) => '0', - O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0), - S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1), - S(0) => v1_reg_0(4) - ); -ram_full_i_i_1: unisim.vcomponents.LUT5 - generic map( - INIT => X"0000FF20" - ) - port map ( - I0 => comp2, - I1 => \out\, - I2 => wr_en, - I3 => comp1, - I4 => ram_full_fb_i_reg_0, - O => ram_full_fb_i_reg - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_compare_1 is - port ( - rd_en_0 : out STD_LOGIC; - v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 ); - rd_en : in STD_LOGIC; - \out\ : in STD_LOGIC; - comp1 : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_compare_1 : entity is "compare"; -end fifo_AntCtrl_compare_1; - -architecture STRUCTURE of fifo_AntCtrl_compare_1 is - signal carrynet_0 : STD_LOGIC; - signal carrynet_1 : STD_LOGIC; - signal carrynet_2 : STD_LOGIC; - signal carrynet_3 : STD_LOGIC; - signal comp0 : STD_LOGIC; - signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - attribute OPT_MODIFIED : string; - attribute OPT_MODIFIED of \gmux.gm[0].gm1.m1_CARRY4\ : label is "MLO"; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)"; - attribute box_type : string; - attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE"; - attribute OPT_MODIFIED of \gmux.gm[4].gms.ms_CARRY4\ : label is "MLO"; - attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)"; - attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE"; -begin -\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => carrynet_3, - CO(2) => carrynet_2, - CO(1) => carrynet_1, - CO(0) => carrynet_0, - CYINIT => '1', - DI(3 downto 0) => B"0000", - O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0), - S(3 downto 0) => v1_reg(3 downto 0) - ); -\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4 - port map ( - CI => carrynet_3, - CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1), - CO(0) => comp0, - CYINIT => '0', - DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1), - DI(0) => '0', - O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0), - S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1), - S(0) => v1_reg(4) - ); -ram_empty_i_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"AEAA" - ) - port map ( - I0 => comp0, - I1 => rd_en, - I2 => \out\, - I3 => comp1, - O => rd_en_0 - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_compare_2 is - port ( - comp1 : out STD_LOGIC; - v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_compare_2 : entity is "compare"; -end fifo_AntCtrl_compare_2; - -architecture STRUCTURE of fifo_AntCtrl_compare_2 is - signal carrynet_0 : STD_LOGIC; - signal carrynet_1 : STD_LOGIC; - signal carrynet_2 : STD_LOGIC; - signal carrynet_3 : STD_LOGIC; - signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - attribute OPT_MODIFIED : string; - attribute OPT_MODIFIED of \gmux.gm[0].gm1.m1_CARRY4\ : label is "MLO"; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)"; - attribute box_type : string; - attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE"; - attribute OPT_MODIFIED of \gmux.gm[4].gms.ms_CARRY4\ : label is "MLO"; - attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)"; - attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE"; -begin -\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => carrynet_3, - CO(2) => carrynet_2, - CO(1) => carrynet_1, - CO(0) => carrynet_0, - CYINIT => '1', - DI(3 downto 0) => B"0000", - O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0), - S(3 downto 0) => v1_reg_0(3 downto 0) - ); -\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4 - port map ( - CI => carrynet_3, - CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1), - CO(0) => comp1, - CYINIT => '0', - DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1), - DI(0) => '0', - O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0), - S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1), - S(0) => v1_reg_0(4) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_dmem is - port ( - dout : out STD_LOGIC_VECTOR ( 3 downto 0 ); - wr_clk : in STD_LOGIC; - din : in STD_LOGIC_VECTOR ( 3 downto 0 ); - \gpr1.dout_i[2]_i_4_0\ : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 9 downto 0 ); - \gpr1.dout_i[3]_i_8_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); - \gpr1.dout_i[2]_i_4_1\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_4_2\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_4_3\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_5_0\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_5_1\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_5_2\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_5_3\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_6_0\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_6_1\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_6_2\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_6_3\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_7_0\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_7_1\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_7_2\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_7_3\ : in STD_LOGIC; - E : in STD_LOGIC_VECTOR ( 0 to 0 ); - rd_clk : in STD_LOGIC; - AR : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_dmem : entity is "dmem"; -end fifo_AntCtrl_dmem; - -architecture STRUCTURE of fifo_AntCtrl_dmem is - signal RAM_reg_0_63_0_2_n_0 : STD_LOGIC; - signal RAM_reg_0_63_0_2_n_1 : STD_LOGIC; - signal RAM_reg_0_63_0_2_n_2 : STD_LOGIC; - signal RAM_reg_0_63_3_3_n_0 : STD_LOGIC; - signal RAM_reg_128_191_0_2_n_0 : STD_LOGIC; - signal RAM_reg_128_191_0_2_n_1 : STD_LOGIC; - signal RAM_reg_128_191_0_2_n_2 : STD_LOGIC; - signal RAM_reg_128_191_3_3_n_0 : STD_LOGIC; - signal RAM_reg_192_255_0_2_n_0 : STD_LOGIC; - signal RAM_reg_192_255_0_2_n_1 : STD_LOGIC; - signal RAM_reg_192_255_0_2_n_2 : STD_LOGIC; - signal RAM_reg_192_255_3_3_n_0 : STD_LOGIC; - signal RAM_reg_256_319_0_2_n_0 : STD_LOGIC; - signal RAM_reg_256_319_0_2_n_1 : STD_LOGIC; - signal RAM_reg_256_319_0_2_n_2 : STD_LOGIC; - signal RAM_reg_256_319_3_3_n_0 : STD_LOGIC; - signal RAM_reg_320_383_0_2_n_0 : STD_LOGIC; - signal RAM_reg_320_383_0_2_n_1 : STD_LOGIC; - signal RAM_reg_320_383_0_2_n_2 : STD_LOGIC; - signal RAM_reg_320_383_3_3_n_0 : STD_LOGIC; - signal RAM_reg_384_447_0_2_n_0 : STD_LOGIC; - signal RAM_reg_384_447_0_2_n_1 : STD_LOGIC; - signal RAM_reg_384_447_0_2_n_2 : STD_LOGIC; - signal RAM_reg_384_447_3_3_n_0 : STD_LOGIC; - signal RAM_reg_448_511_0_2_n_0 : STD_LOGIC; - signal RAM_reg_448_511_0_2_n_1 : STD_LOGIC; - signal RAM_reg_448_511_0_2_n_2 : STD_LOGIC; - signal RAM_reg_448_511_3_3_n_0 : STD_LOGIC; - signal RAM_reg_512_575_0_2_n_0 : STD_LOGIC; - signal RAM_reg_512_575_0_2_n_1 : STD_LOGIC; - signal RAM_reg_512_575_0_2_n_2 : STD_LOGIC; - signal RAM_reg_512_575_3_3_n_0 : STD_LOGIC; - signal RAM_reg_576_639_0_2_n_0 : STD_LOGIC; - signal RAM_reg_576_639_0_2_n_1 : STD_LOGIC; - signal RAM_reg_576_639_0_2_n_2 : STD_LOGIC; - signal RAM_reg_576_639_3_3_n_0 : STD_LOGIC; - signal RAM_reg_640_703_0_2_n_0 : STD_LOGIC; - signal RAM_reg_640_703_0_2_n_1 : STD_LOGIC; - signal RAM_reg_640_703_0_2_n_2 : STD_LOGIC; - signal RAM_reg_640_703_3_3_n_0 : STD_LOGIC; - signal RAM_reg_64_127_0_2_n_0 : STD_LOGIC; - signal RAM_reg_64_127_0_2_n_1 : STD_LOGIC; - signal RAM_reg_64_127_0_2_n_2 : STD_LOGIC; - signal RAM_reg_64_127_3_3_n_0 : STD_LOGIC; - signal RAM_reg_704_767_0_2_n_0 : STD_LOGIC; - signal RAM_reg_704_767_0_2_n_1 : STD_LOGIC; - signal RAM_reg_704_767_0_2_n_2 : STD_LOGIC; - signal RAM_reg_704_767_3_3_n_0 : STD_LOGIC; - signal RAM_reg_768_831_0_2_n_0 : STD_LOGIC; - signal RAM_reg_768_831_0_2_n_1 : STD_LOGIC; - signal RAM_reg_768_831_0_2_n_2 : STD_LOGIC; - signal RAM_reg_768_831_3_3_n_0 : STD_LOGIC; - signal RAM_reg_832_895_0_2_n_0 : STD_LOGIC; - signal RAM_reg_832_895_0_2_n_1 : STD_LOGIC; - signal RAM_reg_832_895_0_2_n_2 : STD_LOGIC; - signal RAM_reg_832_895_3_3_n_0 : STD_LOGIC; - signal RAM_reg_896_959_0_2_n_0 : STD_LOGIC; - signal RAM_reg_896_959_0_2_n_1 : STD_LOGIC; - signal RAM_reg_896_959_0_2_n_2 : STD_LOGIC; - signal RAM_reg_896_959_3_3_n_0 : STD_LOGIC; - signal RAM_reg_960_1023_0_2_n_0 : STD_LOGIC; - signal RAM_reg_960_1023_0_2_n_1 : STD_LOGIC; - signal RAM_reg_960_1023_0_2_n_2 : STD_LOGIC; - signal RAM_reg_960_1023_3_3_n_0 : STD_LOGIC; - signal \gpr1.dout_i[0]_i_4_n_0\ : STD_LOGIC; - signal \gpr1.dout_i[0]_i_5_n_0\ : STD_LOGIC; - signal \gpr1.dout_i[0]_i_6_n_0\ : STD_LOGIC; - signal \gpr1.dout_i[0]_i_7_n_0\ : STD_LOGIC; - signal \gpr1.dout_i[1]_i_4_n_0\ : STD_LOGIC; - signal \gpr1.dout_i[1]_i_5_n_0\ : STD_LOGIC; - signal \gpr1.dout_i[1]_i_6_n_0\ : STD_LOGIC; - signal \gpr1.dout_i[1]_i_7_n_0\ : STD_LOGIC; - signal \gpr1.dout_i[2]_i_4_n_0\ : STD_LOGIC; - signal \gpr1.dout_i[2]_i_5_n_0\ : STD_LOGIC; - signal \gpr1.dout_i[2]_i_6_n_0\ : STD_LOGIC; - signal \gpr1.dout_i[2]_i_7_n_0\ : STD_LOGIC; - signal \gpr1.dout_i[3]_i_5_n_0\ : STD_LOGIC; - signal \gpr1.dout_i[3]_i_6_n_0\ : STD_LOGIC; - signal \gpr1.dout_i[3]_i_7_n_0\ : STD_LOGIC; - signal \gpr1.dout_i[3]_i_8_n_0\ : STD_LOGIC; - signal \gpr1.dout_i_reg[0]_i_2_n_0\ : STD_LOGIC; - signal \gpr1.dout_i_reg[0]_i_3_n_0\ : STD_LOGIC; - signal \gpr1.dout_i_reg[1]_i_2_n_0\ : STD_LOGIC; - signal \gpr1.dout_i_reg[1]_i_3_n_0\ : STD_LOGIC; - signal \gpr1.dout_i_reg[2]_i_2_n_0\ : STD_LOGIC; - signal \gpr1.dout_i_reg[2]_i_3_n_0\ : STD_LOGIC; - signal \gpr1.dout_i_reg[3]_i_3_n_0\ : STD_LOGIC; - signal \gpr1.dout_i_reg[3]_i_4_n_0\ : STD_LOGIC; - signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_RAM_reg_0_63_0_2_DOD_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_0_63_3_3_SPO_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_128_191_0_2_DOD_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_128_191_3_3_SPO_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_192_255_0_2_DOD_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_192_255_3_3_SPO_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_256_319_0_2_DOD_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_256_319_3_3_SPO_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_320_383_0_2_DOD_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_320_383_3_3_SPO_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_384_447_0_2_DOD_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_384_447_3_3_SPO_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_448_511_0_2_DOD_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_448_511_3_3_SPO_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_512_575_0_2_DOD_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_512_575_3_3_SPO_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_576_639_0_2_DOD_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_576_639_3_3_SPO_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_640_703_0_2_DOD_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_640_703_3_3_SPO_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_64_127_0_2_DOD_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_64_127_3_3_SPO_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_704_767_0_2_DOD_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_704_767_3_3_SPO_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_768_831_0_2_DOD_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_768_831_3_3_SPO_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_832_895_0_2_DOD_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_832_895_3_3_SPO_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_896_959_0_2_DOD_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_896_959_3_3_SPO_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_960_1023_0_2_DOD_UNCONNECTED : STD_LOGIC; - signal NLW_RAM_reg_960_1023_3_3_SPO_UNCONNECTED : STD_LOGIC; - attribute METHODOLOGY_DRC_VIOS : string; - attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_63_0_2 : label is ""; - attribute RTL_RAM_BITS : integer; - attribute RTL_RAM_BITS of RAM_reg_0_63_0_2 : label is 4096; - attribute RTL_RAM_NAME : string; - attribute RTL_RAM_NAME of RAM_reg_0_63_0_2 : label is "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM"; - attribute ram_addr_begin : integer; - attribute ram_addr_begin of RAM_reg_0_63_0_2 : label is 0; - attribute ram_addr_end : integer; - attribute ram_addr_end of RAM_reg_0_63_0_2 : label is 63; - attribute ram_offset : integer; - attribute ram_offset of RAM_reg_0_63_0_2 : label is 0; - attribute ram_slice_begin : integer; - attribute ram_slice_begin of RAM_reg_0_63_0_2 : label is 0; - attribute ram_slice_end : integer; - attribute ram_slice_end of RAM_reg_0_63_0_2 : label is 2; - attribute ram_addr_begin of RAM_reg_0_63_3_3 : label is 0; - attribute ram_addr_end of RAM_reg_0_63_3_3 : label is 63; - attribute ram_offset of RAM_reg_0_63_3_3 : label is 0; - attribute ram_slice_begin of RAM_reg_0_63_3_3 : label is 3; - attribute ram_slice_end of RAM_reg_0_63_3_3 : label is 3; - attribute METHODOLOGY_DRC_VIOS of RAM_reg_128_191_0_2 : label is ""; - attribute RTL_RAM_BITS of RAM_reg_128_191_0_2 : label is 4096; - attribute RTL_RAM_NAME of RAM_reg_128_191_0_2 : label is "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM"; - attribute ram_addr_begin of RAM_reg_128_191_0_2 : label is 128; - attribute ram_addr_end of RAM_reg_128_191_0_2 : label is 191; - attribute ram_offset of RAM_reg_128_191_0_2 : label is 0; - attribute ram_slice_begin of RAM_reg_128_191_0_2 : label is 0; - attribute ram_slice_end of RAM_reg_128_191_0_2 : label is 2; - attribute ram_addr_begin of RAM_reg_128_191_3_3 : label is 128; - attribute ram_addr_end of RAM_reg_128_191_3_3 : label is 191; - attribute ram_offset of RAM_reg_128_191_3_3 : label is 0; - attribute ram_slice_begin of RAM_reg_128_191_3_3 : label is 3; - attribute ram_slice_end of RAM_reg_128_191_3_3 : label is 3; - attribute METHODOLOGY_DRC_VIOS of RAM_reg_192_255_0_2 : label is ""; - attribute RTL_RAM_BITS of RAM_reg_192_255_0_2 : label is 4096; - attribute RTL_RAM_NAME of RAM_reg_192_255_0_2 : label is "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM"; - attribute ram_addr_begin of RAM_reg_192_255_0_2 : label is 192; - attribute ram_addr_end of RAM_reg_192_255_0_2 : label is 255; - attribute ram_offset of RAM_reg_192_255_0_2 : label is 0; - attribute ram_slice_begin of RAM_reg_192_255_0_2 : label is 0; - attribute ram_slice_end of RAM_reg_192_255_0_2 : label is 2; - attribute ram_addr_begin of RAM_reg_192_255_3_3 : label is 192; - attribute ram_addr_end of RAM_reg_192_255_3_3 : label is 255; - attribute ram_offset of RAM_reg_192_255_3_3 : label is 0; - attribute ram_slice_begin of RAM_reg_192_255_3_3 : label is 3; - attribute ram_slice_end of RAM_reg_192_255_3_3 : label is 3; - attribute METHODOLOGY_DRC_VIOS of RAM_reg_256_319_0_2 : label is ""; - attribute RTL_RAM_BITS of RAM_reg_256_319_0_2 : label is 4096; - attribute RTL_RAM_NAME of RAM_reg_256_319_0_2 : label is "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM"; - attribute ram_addr_begin of RAM_reg_256_319_0_2 : label is 256; - attribute ram_addr_end of RAM_reg_256_319_0_2 : label is 319; - attribute ram_offset of RAM_reg_256_319_0_2 : label is 0; - attribute ram_slice_begin of RAM_reg_256_319_0_2 : label is 0; - attribute ram_slice_end of RAM_reg_256_319_0_2 : label is 2; - attribute ram_addr_begin of RAM_reg_256_319_3_3 : label is 256; - attribute ram_addr_end of RAM_reg_256_319_3_3 : label is 319; - attribute ram_offset of RAM_reg_256_319_3_3 : label is 0; - attribute ram_slice_begin of RAM_reg_256_319_3_3 : label is 3; - attribute ram_slice_end of RAM_reg_256_319_3_3 : label is 3; - attribute METHODOLOGY_DRC_VIOS of RAM_reg_320_383_0_2 : label is ""; - attribute RTL_RAM_BITS of RAM_reg_320_383_0_2 : label is 4096; - attribute RTL_RAM_NAME of RAM_reg_320_383_0_2 : label is "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM"; - attribute ram_addr_begin of RAM_reg_320_383_0_2 : label is 320; - attribute ram_addr_end of RAM_reg_320_383_0_2 : label is 383; - attribute ram_offset of RAM_reg_320_383_0_2 : label is 0; - attribute ram_slice_begin of RAM_reg_320_383_0_2 : label is 0; - attribute ram_slice_end of RAM_reg_320_383_0_2 : label is 2; - attribute ram_addr_begin of RAM_reg_320_383_3_3 : label is 320; - attribute ram_addr_end of RAM_reg_320_383_3_3 : label is 383; - attribute ram_offset of RAM_reg_320_383_3_3 : label is 0; - attribute ram_slice_begin of RAM_reg_320_383_3_3 : label is 3; - attribute ram_slice_end of RAM_reg_320_383_3_3 : label is 3; - attribute METHODOLOGY_DRC_VIOS of RAM_reg_384_447_0_2 : label is ""; - attribute RTL_RAM_BITS of RAM_reg_384_447_0_2 : label is 4096; - attribute RTL_RAM_NAME of RAM_reg_384_447_0_2 : label is "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM"; - attribute ram_addr_begin of RAM_reg_384_447_0_2 : label is 384; - attribute ram_addr_end of RAM_reg_384_447_0_2 : label is 447; - attribute ram_offset of RAM_reg_384_447_0_2 : label is 0; - attribute ram_slice_begin of RAM_reg_384_447_0_2 : label is 0; - attribute ram_slice_end of RAM_reg_384_447_0_2 : label is 2; - attribute ram_addr_begin of RAM_reg_384_447_3_3 : label is 384; - attribute ram_addr_end of RAM_reg_384_447_3_3 : label is 447; - attribute ram_offset of RAM_reg_384_447_3_3 : label is 0; - attribute ram_slice_begin of RAM_reg_384_447_3_3 : label is 3; - attribute ram_slice_end of RAM_reg_384_447_3_3 : label is 3; - attribute METHODOLOGY_DRC_VIOS of RAM_reg_448_511_0_2 : label is ""; - attribute RTL_RAM_BITS of RAM_reg_448_511_0_2 : label is 4096; - attribute RTL_RAM_NAME of RAM_reg_448_511_0_2 : label is "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM"; - attribute ram_addr_begin of RAM_reg_448_511_0_2 : label is 448; - attribute ram_addr_end of RAM_reg_448_511_0_2 : label is 511; - attribute ram_offset of RAM_reg_448_511_0_2 : label is 0; - attribute ram_slice_begin of RAM_reg_448_511_0_2 : label is 0; - attribute ram_slice_end of RAM_reg_448_511_0_2 : label is 2; - attribute ram_addr_begin of RAM_reg_448_511_3_3 : label is 448; - attribute ram_addr_end of RAM_reg_448_511_3_3 : label is 511; - attribute ram_offset of RAM_reg_448_511_3_3 : label is 0; - attribute ram_slice_begin of RAM_reg_448_511_3_3 : label is 3; - attribute ram_slice_end of RAM_reg_448_511_3_3 : label is 3; - attribute METHODOLOGY_DRC_VIOS of RAM_reg_512_575_0_2 : label is ""; - attribute RTL_RAM_BITS of RAM_reg_512_575_0_2 : label is 4096; - attribute RTL_RAM_NAME of RAM_reg_512_575_0_2 : label is "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM"; - attribute ram_addr_begin of RAM_reg_512_575_0_2 : label is 512; - attribute ram_addr_end of RAM_reg_512_575_0_2 : label is 575; - attribute ram_offset of RAM_reg_512_575_0_2 : label is 0; - attribute ram_slice_begin of RAM_reg_512_575_0_2 : label is 0; - attribute ram_slice_end of RAM_reg_512_575_0_2 : label is 2; - attribute ram_addr_begin of RAM_reg_512_575_3_3 : label is 512; - attribute ram_addr_end of RAM_reg_512_575_3_3 : label is 575; - attribute ram_offset of RAM_reg_512_575_3_3 : label is 0; - attribute ram_slice_begin of RAM_reg_512_575_3_3 : label is 3; - attribute ram_slice_end of RAM_reg_512_575_3_3 : label is 3; - attribute METHODOLOGY_DRC_VIOS of RAM_reg_576_639_0_2 : label is ""; - attribute RTL_RAM_BITS of RAM_reg_576_639_0_2 : label is 4096; - attribute RTL_RAM_NAME of RAM_reg_576_639_0_2 : label is "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM"; - attribute ram_addr_begin of RAM_reg_576_639_0_2 : label is 576; - attribute ram_addr_end of RAM_reg_576_639_0_2 : label is 639; - attribute ram_offset of RAM_reg_576_639_0_2 : label is 0; - attribute ram_slice_begin of RAM_reg_576_639_0_2 : label is 0; - attribute ram_slice_end of RAM_reg_576_639_0_2 : label is 2; - attribute ram_addr_begin of RAM_reg_576_639_3_3 : label is 576; - attribute ram_addr_end of RAM_reg_576_639_3_3 : label is 639; - attribute ram_offset of RAM_reg_576_639_3_3 : label is 0; - attribute ram_slice_begin of RAM_reg_576_639_3_3 : label is 3; - attribute ram_slice_end of RAM_reg_576_639_3_3 : label is 3; - attribute METHODOLOGY_DRC_VIOS of RAM_reg_640_703_0_2 : label is ""; - attribute RTL_RAM_BITS of RAM_reg_640_703_0_2 : label is 4096; - attribute RTL_RAM_NAME of RAM_reg_640_703_0_2 : label is "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM"; - attribute ram_addr_begin of RAM_reg_640_703_0_2 : label is 640; - attribute ram_addr_end of RAM_reg_640_703_0_2 : label is 703; - attribute ram_offset of RAM_reg_640_703_0_2 : label is 0; - attribute ram_slice_begin of RAM_reg_640_703_0_2 : label is 0; - attribute ram_slice_end of RAM_reg_640_703_0_2 : label is 2; - attribute ram_addr_begin of RAM_reg_640_703_3_3 : label is 640; - attribute ram_addr_end of RAM_reg_640_703_3_3 : label is 703; - attribute ram_offset of RAM_reg_640_703_3_3 : label is 0; - attribute ram_slice_begin of RAM_reg_640_703_3_3 : label is 3; - attribute ram_slice_end of RAM_reg_640_703_3_3 : label is 3; - attribute METHODOLOGY_DRC_VIOS of RAM_reg_64_127_0_2 : label is ""; - attribute RTL_RAM_BITS of RAM_reg_64_127_0_2 : label is 4096; - attribute RTL_RAM_NAME of RAM_reg_64_127_0_2 : label is "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM"; - attribute ram_addr_begin of RAM_reg_64_127_0_2 : label is 64; - attribute ram_addr_end of RAM_reg_64_127_0_2 : label is 127; - attribute ram_offset of RAM_reg_64_127_0_2 : label is 0; - attribute ram_slice_begin of RAM_reg_64_127_0_2 : label is 0; - attribute ram_slice_end of RAM_reg_64_127_0_2 : label is 2; - attribute ram_addr_begin of RAM_reg_64_127_3_3 : label is 64; - attribute ram_addr_end of RAM_reg_64_127_3_3 : label is 127; - attribute ram_offset of RAM_reg_64_127_3_3 : label is 0; - attribute ram_slice_begin of RAM_reg_64_127_3_3 : label is 3; - attribute ram_slice_end of RAM_reg_64_127_3_3 : label is 3; - attribute METHODOLOGY_DRC_VIOS of RAM_reg_704_767_0_2 : label is ""; - attribute RTL_RAM_BITS of RAM_reg_704_767_0_2 : label is 4096; - attribute RTL_RAM_NAME of RAM_reg_704_767_0_2 : label is "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM"; - attribute ram_addr_begin of RAM_reg_704_767_0_2 : label is 704; - attribute ram_addr_end of RAM_reg_704_767_0_2 : label is 767; - attribute ram_offset of RAM_reg_704_767_0_2 : label is 0; - attribute ram_slice_begin of RAM_reg_704_767_0_2 : label is 0; - attribute ram_slice_end of RAM_reg_704_767_0_2 : label is 2; - attribute ram_addr_begin of RAM_reg_704_767_3_3 : label is 704; - attribute ram_addr_end of RAM_reg_704_767_3_3 : label is 767; - attribute ram_offset of RAM_reg_704_767_3_3 : label is 0; - attribute ram_slice_begin of RAM_reg_704_767_3_3 : label is 3; - attribute ram_slice_end of RAM_reg_704_767_3_3 : label is 3; - attribute METHODOLOGY_DRC_VIOS of RAM_reg_768_831_0_2 : label is ""; - attribute RTL_RAM_BITS of RAM_reg_768_831_0_2 : label is 4096; - attribute RTL_RAM_NAME of RAM_reg_768_831_0_2 : label is "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM"; - attribute ram_addr_begin of RAM_reg_768_831_0_2 : label is 768; - attribute ram_addr_end of RAM_reg_768_831_0_2 : label is 831; - attribute ram_offset of RAM_reg_768_831_0_2 : label is 0; - attribute ram_slice_begin of RAM_reg_768_831_0_2 : label is 0; - attribute ram_slice_end of RAM_reg_768_831_0_2 : label is 2; - attribute ram_addr_begin of RAM_reg_768_831_3_3 : label is 768; - attribute ram_addr_end of RAM_reg_768_831_3_3 : label is 831; - attribute ram_offset of RAM_reg_768_831_3_3 : label is 0; - attribute ram_slice_begin of RAM_reg_768_831_3_3 : label is 3; - attribute ram_slice_end of RAM_reg_768_831_3_3 : label is 3; - attribute METHODOLOGY_DRC_VIOS of RAM_reg_832_895_0_2 : label is ""; - attribute RTL_RAM_BITS of RAM_reg_832_895_0_2 : label is 4096; - attribute RTL_RAM_NAME of RAM_reg_832_895_0_2 : label is "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM"; - attribute ram_addr_begin of RAM_reg_832_895_0_2 : label is 832; - attribute ram_addr_end of RAM_reg_832_895_0_2 : label is 895; - attribute ram_offset of RAM_reg_832_895_0_2 : label is 0; - attribute ram_slice_begin of RAM_reg_832_895_0_2 : label is 0; - attribute ram_slice_end of RAM_reg_832_895_0_2 : label is 2; - attribute ram_addr_begin of RAM_reg_832_895_3_3 : label is 832; - attribute ram_addr_end of RAM_reg_832_895_3_3 : label is 895; - attribute ram_offset of RAM_reg_832_895_3_3 : label is 0; - attribute ram_slice_begin of RAM_reg_832_895_3_3 : label is 3; - attribute ram_slice_end of RAM_reg_832_895_3_3 : label is 3; - attribute METHODOLOGY_DRC_VIOS of RAM_reg_896_959_0_2 : label is ""; - attribute RTL_RAM_BITS of RAM_reg_896_959_0_2 : label is 4096; - attribute RTL_RAM_NAME of RAM_reg_896_959_0_2 : label is "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM"; - attribute ram_addr_begin of RAM_reg_896_959_0_2 : label is 896; - attribute ram_addr_end of RAM_reg_896_959_0_2 : label is 959; - attribute ram_offset of RAM_reg_896_959_0_2 : label is 0; - attribute ram_slice_begin of RAM_reg_896_959_0_2 : label is 0; - attribute ram_slice_end of RAM_reg_896_959_0_2 : label is 2; - attribute ram_addr_begin of RAM_reg_896_959_3_3 : label is 896; - attribute ram_addr_end of RAM_reg_896_959_3_3 : label is 959; - attribute ram_offset of RAM_reg_896_959_3_3 : label is 0; - attribute ram_slice_begin of RAM_reg_896_959_3_3 : label is 3; - attribute ram_slice_end of RAM_reg_896_959_3_3 : label is 3; - attribute METHODOLOGY_DRC_VIOS of RAM_reg_960_1023_0_2 : label is ""; - attribute RTL_RAM_BITS of RAM_reg_960_1023_0_2 : label is 4096; - attribute RTL_RAM_NAME of RAM_reg_960_1023_0_2 : label is "inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM"; - attribute ram_addr_begin of RAM_reg_960_1023_0_2 : label is 960; - attribute ram_addr_end of RAM_reg_960_1023_0_2 : label is 1023; - attribute ram_offset of RAM_reg_960_1023_0_2 : label is 0; - attribute ram_slice_begin of RAM_reg_960_1023_0_2 : label is 0; - attribute ram_slice_end of RAM_reg_960_1023_0_2 : label is 2; - attribute ram_addr_begin of RAM_reg_960_1023_3_3 : label is 960; - attribute ram_addr_end of RAM_reg_960_1023_3_3 : label is 1023; - attribute ram_offset of RAM_reg_960_1023_3_3 : label is 0; - attribute ram_slice_begin of RAM_reg_960_1023_3_3 : label is 3; - attribute ram_slice_end of RAM_reg_960_1023_3_3 : label is 3; -begin -RAM_reg_0_63_0_2: unisim.vcomponents.RAM64M - port map ( - ADDRA(5 downto 0) => Q(5 downto 0), - ADDRB(5 downto 0) => Q(5 downto 0), - ADDRC(5 downto 0) => Q(5 downto 0), - ADDRD(5 downto 0) => \gpr1.dout_i[3]_i_8_0\(5 downto 0), - DIA => din(0), - DIB => din(1), - DIC => din(2), - DID => '0', - DOA => RAM_reg_0_63_0_2_n_0, - DOB => RAM_reg_0_63_0_2_n_1, - DOC => RAM_reg_0_63_0_2_n_2, - DOD => NLW_RAM_reg_0_63_0_2_DOD_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_4_0\ - ); -RAM_reg_0_63_3_3: unisim.vcomponents.RAM64X1D - port map ( - A0 => \gpr1.dout_i[3]_i_8_0\(0), - A1 => \gpr1.dout_i[3]_i_8_0\(1), - A2 => \gpr1.dout_i[3]_i_8_0\(2), - A3 => \gpr1.dout_i[3]_i_8_0\(3), - A4 => \gpr1.dout_i[3]_i_8_0\(4), - A5 => \gpr1.dout_i[3]_i_8_0\(5), - D => din(3), - DPO => RAM_reg_0_63_3_3_n_0, - DPRA0 => Q(0), - DPRA1 => Q(1), - DPRA2 => Q(2), - DPRA3 => Q(3), - DPRA4 => Q(4), - DPRA5 => Q(5), - SPO => NLW_RAM_reg_0_63_3_3_SPO_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_4_0\ - ); -RAM_reg_128_191_0_2: unisim.vcomponents.RAM64M - port map ( - ADDRA(5 downto 0) => Q(5 downto 0), - ADDRB(5 downto 0) => Q(5 downto 0), - ADDRC(5 downto 0) => Q(5 downto 0), - ADDRD(5 downto 0) => \gpr1.dout_i[3]_i_8_0\(5 downto 0), - DIA => din(0), - DIB => din(1), - DIC => din(2), - DID => '0', - DOA => RAM_reg_128_191_0_2_n_0, - DOB => RAM_reg_128_191_0_2_n_1, - DOC => RAM_reg_128_191_0_2_n_2, - DOD => NLW_RAM_reg_128_191_0_2_DOD_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_4_2\ - ); -RAM_reg_128_191_3_3: unisim.vcomponents.RAM64X1D - port map ( - A0 => \gpr1.dout_i[3]_i_8_0\(0), - A1 => \gpr1.dout_i[3]_i_8_0\(1), - A2 => \gpr1.dout_i[3]_i_8_0\(2), - A3 => \gpr1.dout_i[3]_i_8_0\(3), - A4 => \gpr1.dout_i[3]_i_8_0\(4), - A5 => \gpr1.dout_i[3]_i_8_0\(5), - D => din(3), - DPO => RAM_reg_128_191_3_3_n_0, - DPRA0 => Q(0), - DPRA1 => Q(1), - DPRA2 => Q(2), - DPRA3 => Q(3), - DPRA4 => Q(4), - DPRA5 => Q(5), - SPO => NLW_RAM_reg_128_191_3_3_SPO_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_4_2\ - ); -RAM_reg_192_255_0_2: unisim.vcomponents.RAM64M - port map ( - ADDRA(5 downto 0) => Q(5 downto 0), - ADDRB(5 downto 0) => Q(5 downto 0), - ADDRC(5 downto 0) => Q(5 downto 0), - ADDRD(5 downto 0) => \gpr1.dout_i[3]_i_8_0\(5 downto 0), - DIA => din(0), - DIB => din(1), - DIC => din(2), - DID => '0', - DOA => RAM_reg_192_255_0_2_n_0, - DOB => RAM_reg_192_255_0_2_n_1, - DOC => RAM_reg_192_255_0_2_n_2, - DOD => NLW_RAM_reg_192_255_0_2_DOD_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_4_3\ - ); -RAM_reg_192_255_3_3: unisim.vcomponents.RAM64X1D - port map ( - A0 => \gpr1.dout_i[3]_i_8_0\(0), - A1 => \gpr1.dout_i[3]_i_8_0\(1), - A2 => \gpr1.dout_i[3]_i_8_0\(2), - A3 => \gpr1.dout_i[3]_i_8_0\(3), - A4 => \gpr1.dout_i[3]_i_8_0\(4), - A5 => \gpr1.dout_i[3]_i_8_0\(5), - D => din(3), - DPO => RAM_reg_192_255_3_3_n_0, - DPRA0 => Q(0), - DPRA1 => Q(1), - DPRA2 => Q(2), - DPRA3 => Q(3), - DPRA4 => Q(4), - DPRA5 => Q(5), - SPO => NLW_RAM_reg_192_255_3_3_SPO_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_4_3\ - ); -RAM_reg_256_319_0_2: unisim.vcomponents.RAM64M - port map ( - ADDRA(5 downto 0) => Q(5 downto 0), - ADDRB(5 downto 0) => Q(5 downto 0), - ADDRC(5 downto 0) => Q(5 downto 0), - ADDRD(5 downto 0) => \gpr1.dout_i[3]_i_8_0\(5 downto 0), - DIA => din(0), - DIB => din(1), - DIC => din(2), - DID => '0', - DOA => RAM_reg_256_319_0_2_n_0, - DOB => RAM_reg_256_319_0_2_n_1, - DOC => RAM_reg_256_319_0_2_n_2, - DOD => NLW_RAM_reg_256_319_0_2_DOD_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_5_0\ - ); -RAM_reg_256_319_3_3: unisim.vcomponents.RAM64X1D - port map ( - A0 => \gpr1.dout_i[3]_i_8_0\(0), - A1 => \gpr1.dout_i[3]_i_8_0\(1), - A2 => \gpr1.dout_i[3]_i_8_0\(2), - A3 => \gpr1.dout_i[3]_i_8_0\(3), - A4 => \gpr1.dout_i[3]_i_8_0\(4), - A5 => \gpr1.dout_i[3]_i_8_0\(5), - D => din(3), - DPO => RAM_reg_256_319_3_3_n_0, - DPRA0 => Q(0), - DPRA1 => Q(1), - DPRA2 => Q(2), - DPRA3 => Q(3), - DPRA4 => Q(4), - DPRA5 => Q(5), - SPO => NLW_RAM_reg_256_319_3_3_SPO_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_5_0\ - ); -RAM_reg_320_383_0_2: unisim.vcomponents.RAM64M - port map ( - ADDRA(5 downto 0) => Q(5 downto 0), - ADDRB(5 downto 0) => Q(5 downto 0), - ADDRC(5 downto 0) => Q(5 downto 0), - ADDRD(5 downto 0) => \gpr1.dout_i[3]_i_8_0\(5 downto 0), - DIA => din(0), - DIB => din(1), - DIC => din(2), - DID => '0', - DOA => RAM_reg_320_383_0_2_n_0, - DOB => RAM_reg_320_383_0_2_n_1, - DOC => RAM_reg_320_383_0_2_n_2, - DOD => NLW_RAM_reg_320_383_0_2_DOD_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_5_1\ - ); -RAM_reg_320_383_3_3: unisim.vcomponents.RAM64X1D - port map ( - A0 => \gpr1.dout_i[3]_i_8_0\(0), - A1 => \gpr1.dout_i[3]_i_8_0\(1), - A2 => \gpr1.dout_i[3]_i_8_0\(2), - A3 => \gpr1.dout_i[3]_i_8_0\(3), - A4 => \gpr1.dout_i[3]_i_8_0\(4), - A5 => \gpr1.dout_i[3]_i_8_0\(5), - D => din(3), - DPO => RAM_reg_320_383_3_3_n_0, - DPRA0 => Q(0), - DPRA1 => Q(1), - DPRA2 => Q(2), - DPRA3 => Q(3), - DPRA4 => Q(4), - DPRA5 => Q(5), - SPO => NLW_RAM_reg_320_383_3_3_SPO_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_5_1\ - ); -RAM_reg_384_447_0_2: unisim.vcomponents.RAM64M - port map ( - ADDRA(5 downto 0) => Q(5 downto 0), - ADDRB(5 downto 0) => Q(5 downto 0), - ADDRC(5 downto 0) => Q(5 downto 0), - ADDRD(5 downto 0) => \gpr1.dout_i[3]_i_8_0\(5 downto 0), - DIA => din(0), - DIB => din(1), - DIC => din(2), - DID => '0', - DOA => RAM_reg_384_447_0_2_n_0, - DOB => RAM_reg_384_447_0_2_n_1, - DOC => RAM_reg_384_447_0_2_n_2, - DOD => NLW_RAM_reg_384_447_0_2_DOD_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_5_2\ - ); -RAM_reg_384_447_3_3: unisim.vcomponents.RAM64X1D - port map ( - A0 => \gpr1.dout_i[3]_i_8_0\(0), - A1 => \gpr1.dout_i[3]_i_8_0\(1), - A2 => \gpr1.dout_i[3]_i_8_0\(2), - A3 => \gpr1.dout_i[3]_i_8_0\(3), - A4 => \gpr1.dout_i[3]_i_8_0\(4), - A5 => \gpr1.dout_i[3]_i_8_0\(5), - D => din(3), - DPO => RAM_reg_384_447_3_3_n_0, - DPRA0 => Q(0), - DPRA1 => Q(1), - DPRA2 => Q(2), - DPRA3 => Q(3), - DPRA4 => Q(4), - DPRA5 => Q(5), - SPO => NLW_RAM_reg_384_447_3_3_SPO_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_5_2\ - ); -RAM_reg_448_511_0_2: unisim.vcomponents.RAM64M - port map ( - ADDRA(5 downto 0) => Q(5 downto 0), - ADDRB(5 downto 0) => Q(5 downto 0), - ADDRC(5 downto 0) => Q(5 downto 0), - ADDRD(5 downto 0) => \gpr1.dout_i[3]_i_8_0\(5 downto 0), - DIA => din(0), - DIB => din(1), - DIC => din(2), - DID => '0', - DOA => RAM_reg_448_511_0_2_n_0, - DOB => RAM_reg_448_511_0_2_n_1, - DOC => RAM_reg_448_511_0_2_n_2, - DOD => NLW_RAM_reg_448_511_0_2_DOD_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_5_3\ - ); -RAM_reg_448_511_3_3: unisim.vcomponents.RAM64X1D - port map ( - A0 => \gpr1.dout_i[3]_i_8_0\(0), - A1 => \gpr1.dout_i[3]_i_8_0\(1), - A2 => \gpr1.dout_i[3]_i_8_0\(2), - A3 => \gpr1.dout_i[3]_i_8_0\(3), - A4 => \gpr1.dout_i[3]_i_8_0\(4), - A5 => \gpr1.dout_i[3]_i_8_0\(5), - D => din(3), - DPO => RAM_reg_448_511_3_3_n_0, - DPRA0 => Q(0), - DPRA1 => Q(1), - DPRA2 => Q(2), - DPRA3 => Q(3), - DPRA4 => Q(4), - DPRA5 => Q(5), - SPO => NLW_RAM_reg_448_511_3_3_SPO_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_5_3\ - ); -RAM_reg_512_575_0_2: unisim.vcomponents.RAM64M - port map ( - ADDRA(5 downto 0) => Q(5 downto 0), - ADDRB(5 downto 0) => Q(5 downto 0), - ADDRC(5 downto 0) => Q(5 downto 0), - ADDRD(5 downto 0) => \gpr1.dout_i[3]_i_8_0\(5 downto 0), - DIA => din(0), - DIB => din(1), - DIC => din(2), - DID => '0', - DOA => RAM_reg_512_575_0_2_n_0, - DOB => RAM_reg_512_575_0_2_n_1, - DOC => RAM_reg_512_575_0_2_n_2, - DOD => NLW_RAM_reg_512_575_0_2_DOD_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_6_0\ - ); -RAM_reg_512_575_3_3: unisim.vcomponents.RAM64X1D - port map ( - A0 => \gpr1.dout_i[3]_i_8_0\(0), - A1 => \gpr1.dout_i[3]_i_8_0\(1), - A2 => \gpr1.dout_i[3]_i_8_0\(2), - A3 => \gpr1.dout_i[3]_i_8_0\(3), - A4 => \gpr1.dout_i[3]_i_8_0\(4), - A5 => \gpr1.dout_i[3]_i_8_0\(5), - D => din(3), - DPO => RAM_reg_512_575_3_3_n_0, - DPRA0 => Q(0), - DPRA1 => Q(1), - DPRA2 => Q(2), - DPRA3 => Q(3), - DPRA4 => Q(4), - DPRA5 => Q(5), - SPO => NLW_RAM_reg_512_575_3_3_SPO_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_6_0\ - ); -RAM_reg_576_639_0_2: unisim.vcomponents.RAM64M - port map ( - ADDRA(5 downto 0) => Q(5 downto 0), - ADDRB(5 downto 0) => Q(5 downto 0), - ADDRC(5 downto 0) => Q(5 downto 0), - ADDRD(5 downto 0) => \gpr1.dout_i[3]_i_8_0\(5 downto 0), - DIA => din(0), - DIB => din(1), - DIC => din(2), - DID => '0', - DOA => RAM_reg_576_639_0_2_n_0, - DOB => RAM_reg_576_639_0_2_n_1, - DOC => RAM_reg_576_639_0_2_n_2, - DOD => NLW_RAM_reg_576_639_0_2_DOD_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_6_1\ - ); -RAM_reg_576_639_3_3: unisim.vcomponents.RAM64X1D - port map ( - A0 => \gpr1.dout_i[3]_i_8_0\(0), - A1 => \gpr1.dout_i[3]_i_8_0\(1), - A2 => \gpr1.dout_i[3]_i_8_0\(2), - A3 => \gpr1.dout_i[3]_i_8_0\(3), - A4 => \gpr1.dout_i[3]_i_8_0\(4), - A5 => \gpr1.dout_i[3]_i_8_0\(5), - D => din(3), - DPO => RAM_reg_576_639_3_3_n_0, - DPRA0 => Q(0), - DPRA1 => Q(1), - DPRA2 => Q(2), - DPRA3 => Q(3), - DPRA4 => Q(4), - DPRA5 => Q(5), - SPO => NLW_RAM_reg_576_639_3_3_SPO_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_6_1\ - ); -RAM_reg_640_703_0_2: unisim.vcomponents.RAM64M - port map ( - ADDRA(5 downto 0) => Q(5 downto 0), - ADDRB(5 downto 0) => Q(5 downto 0), - ADDRC(5 downto 0) => Q(5 downto 0), - ADDRD(5 downto 0) => \gpr1.dout_i[3]_i_8_0\(5 downto 0), - DIA => din(0), - DIB => din(1), - DIC => din(2), - DID => '0', - DOA => RAM_reg_640_703_0_2_n_0, - DOB => RAM_reg_640_703_0_2_n_1, - DOC => RAM_reg_640_703_0_2_n_2, - DOD => NLW_RAM_reg_640_703_0_2_DOD_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_6_2\ - ); -RAM_reg_640_703_3_3: unisim.vcomponents.RAM64X1D - port map ( - A0 => \gpr1.dout_i[3]_i_8_0\(0), - A1 => \gpr1.dout_i[3]_i_8_0\(1), - A2 => \gpr1.dout_i[3]_i_8_0\(2), - A3 => \gpr1.dout_i[3]_i_8_0\(3), - A4 => \gpr1.dout_i[3]_i_8_0\(4), - A5 => \gpr1.dout_i[3]_i_8_0\(5), - D => din(3), - DPO => RAM_reg_640_703_3_3_n_0, - DPRA0 => Q(0), - DPRA1 => Q(1), - DPRA2 => Q(2), - DPRA3 => Q(3), - DPRA4 => Q(4), - DPRA5 => Q(5), - SPO => NLW_RAM_reg_640_703_3_3_SPO_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_6_2\ - ); -RAM_reg_64_127_0_2: unisim.vcomponents.RAM64M - port map ( - ADDRA(5 downto 0) => Q(5 downto 0), - ADDRB(5 downto 0) => Q(5 downto 0), - ADDRC(5 downto 0) => Q(5 downto 0), - ADDRD(5 downto 0) => \gpr1.dout_i[3]_i_8_0\(5 downto 0), - DIA => din(0), - DIB => din(1), - DIC => din(2), - DID => '0', - DOA => RAM_reg_64_127_0_2_n_0, - DOB => RAM_reg_64_127_0_2_n_1, - DOC => RAM_reg_64_127_0_2_n_2, - DOD => NLW_RAM_reg_64_127_0_2_DOD_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_4_1\ - ); -RAM_reg_64_127_3_3: unisim.vcomponents.RAM64X1D - port map ( - A0 => \gpr1.dout_i[3]_i_8_0\(0), - A1 => \gpr1.dout_i[3]_i_8_0\(1), - A2 => \gpr1.dout_i[3]_i_8_0\(2), - A3 => \gpr1.dout_i[3]_i_8_0\(3), - A4 => \gpr1.dout_i[3]_i_8_0\(4), - A5 => \gpr1.dout_i[3]_i_8_0\(5), - D => din(3), - DPO => RAM_reg_64_127_3_3_n_0, - DPRA0 => Q(0), - DPRA1 => Q(1), - DPRA2 => Q(2), - DPRA3 => Q(3), - DPRA4 => Q(4), - DPRA5 => Q(5), - SPO => NLW_RAM_reg_64_127_3_3_SPO_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_4_1\ - ); -RAM_reg_704_767_0_2: unisim.vcomponents.RAM64M - port map ( - ADDRA(5 downto 0) => Q(5 downto 0), - ADDRB(5 downto 0) => Q(5 downto 0), - ADDRC(5 downto 0) => Q(5 downto 0), - ADDRD(5 downto 0) => \gpr1.dout_i[3]_i_8_0\(5 downto 0), - DIA => din(0), - DIB => din(1), - DIC => din(2), - DID => '0', - DOA => RAM_reg_704_767_0_2_n_0, - DOB => RAM_reg_704_767_0_2_n_1, - DOC => RAM_reg_704_767_0_2_n_2, - DOD => NLW_RAM_reg_704_767_0_2_DOD_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_6_3\ - ); -RAM_reg_704_767_3_3: unisim.vcomponents.RAM64X1D - port map ( - A0 => \gpr1.dout_i[3]_i_8_0\(0), - A1 => \gpr1.dout_i[3]_i_8_0\(1), - A2 => \gpr1.dout_i[3]_i_8_0\(2), - A3 => \gpr1.dout_i[3]_i_8_0\(3), - A4 => \gpr1.dout_i[3]_i_8_0\(4), - A5 => \gpr1.dout_i[3]_i_8_0\(5), - D => din(3), - DPO => RAM_reg_704_767_3_3_n_0, - DPRA0 => Q(0), - DPRA1 => Q(1), - DPRA2 => Q(2), - DPRA3 => Q(3), - DPRA4 => Q(4), - DPRA5 => Q(5), - SPO => NLW_RAM_reg_704_767_3_3_SPO_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_6_3\ - ); -RAM_reg_768_831_0_2: unisim.vcomponents.RAM64M - port map ( - ADDRA(5 downto 0) => Q(5 downto 0), - ADDRB(5 downto 0) => Q(5 downto 0), - ADDRC(5 downto 0) => Q(5 downto 0), - ADDRD(5 downto 0) => \gpr1.dout_i[3]_i_8_0\(5 downto 0), - DIA => din(0), - DIB => din(1), - DIC => din(2), - DID => '0', - DOA => RAM_reg_768_831_0_2_n_0, - DOB => RAM_reg_768_831_0_2_n_1, - DOC => RAM_reg_768_831_0_2_n_2, - DOD => NLW_RAM_reg_768_831_0_2_DOD_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_7_0\ - ); -RAM_reg_768_831_3_3: unisim.vcomponents.RAM64X1D - port map ( - A0 => \gpr1.dout_i[3]_i_8_0\(0), - A1 => \gpr1.dout_i[3]_i_8_0\(1), - A2 => \gpr1.dout_i[3]_i_8_0\(2), - A3 => \gpr1.dout_i[3]_i_8_0\(3), - A4 => \gpr1.dout_i[3]_i_8_0\(4), - A5 => \gpr1.dout_i[3]_i_8_0\(5), - D => din(3), - DPO => RAM_reg_768_831_3_3_n_0, - DPRA0 => Q(0), - DPRA1 => Q(1), - DPRA2 => Q(2), - DPRA3 => Q(3), - DPRA4 => Q(4), - DPRA5 => Q(5), - SPO => NLW_RAM_reg_768_831_3_3_SPO_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_7_0\ - ); -RAM_reg_832_895_0_2: unisim.vcomponents.RAM64M - port map ( - ADDRA(5 downto 0) => Q(5 downto 0), - ADDRB(5 downto 0) => Q(5 downto 0), - ADDRC(5 downto 0) => Q(5 downto 0), - ADDRD(5 downto 0) => \gpr1.dout_i[3]_i_8_0\(5 downto 0), - DIA => din(0), - DIB => din(1), - DIC => din(2), - DID => '0', - DOA => RAM_reg_832_895_0_2_n_0, - DOB => RAM_reg_832_895_0_2_n_1, - DOC => RAM_reg_832_895_0_2_n_2, - DOD => NLW_RAM_reg_832_895_0_2_DOD_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_7_1\ - ); -RAM_reg_832_895_3_3: unisim.vcomponents.RAM64X1D - port map ( - A0 => \gpr1.dout_i[3]_i_8_0\(0), - A1 => \gpr1.dout_i[3]_i_8_0\(1), - A2 => \gpr1.dout_i[3]_i_8_0\(2), - A3 => \gpr1.dout_i[3]_i_8_0\(3), - A4 => \gpr1.dout_i[3]_i_8_0\(4), - A5 => \gpr1.dout_i[3]_i_8_0\(5), - D => din(3), - DPO => RAM_reg_832_895_3_3_n_0, - DPRA0 => Q(0), - DPRA1 => Q(1), - DPRA2 => Q(2), - DPRA3 => Q(3), - DPRA4 => Q(4), - DPRA5 => Q(5), - SPO => NLW_RAM_reg_832_895_3_3_SPO_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_7_1\ - ); -RAM_reg_896_959_0_2: unisim.vcomponents.RAM64M - port map ( - ADDRA(5 downto 0) => Q(5 downto 0), - ADDRB(5 downto 0) => Q(5 downto 0), - ADDRC(5 downto 0) => Q(5 downto 0), - ADDRD(5 downto 0) => \gpr1.dout_i[3]_i_8_0\(5 downto 0), - DIA => din(0), - DIB => din(1), - DIC => din(2), - DID => '0', - DOA => RAM_reg_896_959_0_2_n_0, - DOB => RAM_reg_896_959_0_2_n_1, - DOC => RAM_reg_896_959_0_2_n_2, - DOD => NLW_RAM_reg_896_959_0_2_DOD_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_7_2\ - ); -RAM_reg_896_959_3_3: unisim.vcomponents.RAM64X1D - port map ( - A0 => \gpr1.dout_i[3]_i_8_0\(0), - A1 => \gpr1.dout_i[3]_i_8_0\(1), - A2 => \gpr1.dout_i[3]_i_8_0\(2), - A3 => \gpr1.dout_i[3]_i_8_0\(3), - A4 => \gpr1.dout_i[3]_i_8_0\(4), - A5 => \gpr1.dout_i[3]_i_8_0\(5), - D => din(3), - DPO => RAM_reg_896_959_3_3_n_0, - DPRA0 => Q(0), - DPRA1 => Q(1), - DPRA2 => Q(2), - DPRA3 => Q(3), - DPRA4 => Q(4), - DPRA5 => Q(5), - SPO => NLW_RAM_reg_896_959_3_3_SPO_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_7_2\ - ); -RAM_reg_960_1023_0_2: unisim.vcomponents.RAM64M - port map ( - ADDRA(5 downto 0) => Q(5 downto 0), - ADDRB(5 downto 0) => Q(5 downto 0), - ADDRC(5 downto 0) => Q(5 downto 0), - ADDRD(5 downto 0) => \gpr1.dout_i[3]_i_8_0\(5 downto 0), - DIA => din(0), - DIB => din(1), - DIC => din(2), - DID => '0', - DOA => RAM_reg_960_1023_0_2_n_0, - DOB => RAM_reg_960_1023_0_2_n_1, - DOC => RAM_reg_960_1023_0_2_n_2, - DOD => NLW_RAM_reg_960_1023_0_2_DOD_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_7_3\ - ); -RAM_reg_960_1023_3_3: unisim.vcomponents.RAM64X1D - port map ( - A0 => \gpr1.dout_i[3]_i_8_0\(0), - A1 => \gpr1.dout_i[3]_i_8_0\(1), - A2 => \gpr1.dout_i[3]_i_8_0\(2), - A3 => \gpr1.dout_i[3]_i_8_0\(3), - A4 => \gpr1.dout_i[3]_i_8_0\(4), - A5 => \gpr1.dout_i[3]_i_8_0\(5), - D => din(3), - DPO => RAM_reg_960_1023_3_3_n_0, - DPRA0 => Q(0), - DPRA1 => Q(1), - DPRA2 => Q(2), - DPRA3 => Q(3), - DPRA4 => Q(4), - DPRA5 => Q(5), - SPO => NLW_RAM_reg_960_1023_3_3_SPO_UNCONNECTED, - WCLK => wr_clk, - WE => \gpr1.dout_i[2]_i_7_3\ - ); -\gpr1.dout_i[0]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => RAM_reg_192_255_0_2_n_0, - I1 => RAM_reg_128_191_0_2_n_0, - I2 => Q(7), - I3 => RAM_reg_64_127_0_2_n_0, - I4 => Q(6), - I5 => RAM_reg_0_63_0_2_n_0, - O => \gpr1.dout_i[0]_i_4_n_0\ - ); -\gpr1.dout_i[0]_i_5\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => RAM_reg_448_511_0_2_n_0, - I1 => RAM_reg_384_447_0_2_n_0, - I2 => Q(7), - I3 => RAM_reg_320_383_0_2_n_0, - I4 => Q(6), - I5 => RAM_reg_256_319_0_2_n_0, - O => \gpr1.dout_i[0]_i_5_n_0\ - ); -\gpr1.dout_i[0]_i_6\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => RAM_reg_704_767_0_2_n_0, - I1 => RAM_reg_640_703_0_2_n_0, - I2 => Q(7), - I3 => RAM_reg_576_639_0_2_n_0, - I4 => Q(6), - I5 => RAM_reg_512_575_0_2_n_0, - O => \gpr1.dout_i[0]_i_6_n_0\ - ); -\gpr1.dout_i[0]_i_7\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => RAM_reg_960_1023_0_2_n_0, - I1 => RAM_reg_896_959_0_2_n_0, - I2 => Q(7), - I3 => RAM_reg_832_895_0_2_n_0, - I4 => Q(6), - I5 => RAM_reg_768_831_0_2_n_0, - O => \gpr1.dout_i[0]_i_7_n_0\ - ); -\gpr1.dout_i[1]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => RAM_reg_192_255_0_2_n_1, - I1 => RAM_reg_128_191_0_2_n_1, - I2 => Q(7), - I3 => RAM_reg_64_127_0_2_n_1, - I4 => Q(6), - I5 => RAM_reg_0_63_0_2_n_1, - O => \gpr1.dout_i[1]_i_4_n_0\ - ); -\gpr1.dout_i[1]_i_5\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => RAM_reg_448_511_0_2_n_1, - I1 => RAM_reg_384_447_0_2_n_1, - I2 => Q(7), - I3 => RAM_reg_320_383_0_2_n_1, - I4 => Q(6), - I5 => RAM_reg_256_319_0_2_n_1, - O => \gpr1.dout_i[1]_i_5_n_0\ - ); -\gpr1.dout_i[1]_i_6\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => RAM_reg_704_767_0_2_n_1, - I1 => RAM_reg_640_703_0_2_n_1, - I2 => Q(7), - I3 => RAM_reg_576_639_0_2_n_1, - I4 => Q(6), - I5 => RAM_reg_512_575_0_2_n_1, - O => \gpr1.dout_i[1]_i_6_n_0\ - ); -\gpr1.dout_i[1]_i_7\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => RAM_reg_960_1023_0_2_n_1, - I1 => RAM_reg_896_959_0_2_n_1, - I2 => Q(7), - I3 => RAM_reg_832_895_0_2_n_1, - I4 => Q(6), - I5 => RAM_reg_768_831_0_2_n_1, - O => \gpr1.dout_i[1]_i_7_n_0\ - ); -\gpr1.dout_i[2]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => RAM_reg_192_255_0_2_n_2, - I1 => RAM_reg_128_191_0_2_n_2, - I2 => Q(7), - I3 => RAM_reg_64_127_0_2_n_2, - I4 => Q(6), - I5 => RAM_reg_0_63_0_2_n_2, - O => \gpr1.dout_i[2]_i_4_n_0\ - ); -\gpr1.dout_i[2]_i_5\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => RAM_reg_448_511_0_2_n_2, - I1 => RAM_reg_384_447_0_2_n_2, - I2 => Q(7), - I3 => RAM_reg_320_383_0_2_n_2, - I4 => Q(6), - I5 => RAM_reg_256_319_0_2_n_2, - O => \gpr1.dout_i[2]_i_5_n_0\ - ); -\gpr1.dout_i[2]_i_6\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => RAM_reg_704_767_0_2_n_2, - I1 => RAM_reg_640_703_0_2_n_2, - I2 => Q(7), - I3 => RAM_reg_576_639_0_2_n_2, - I4 => Q(6), - I5 => RAM_reg_512_575_0_2_n_2, - O => \gpr1.dout_i[2]_i_6_n_0\ - ); -\gpr1.dout_i[2]_i_7\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => RAM_reg_960_1023_0_2_n_2, - I1 => RAM_reg_896_959_0_2_n_2, - I2 => Q(7), - I3 => RAM_reg_832_895_0_2_n_2, - I4 => Q(6), - I5 => RAM_reg_768_831_0_2_n_2, - O => \gpr1.dout_i[2]_i_7_n_0\ - ); -\gpr1.dout_i[3]_i_5\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => RAM_reg_192_255_3_3_n_0, - I1 => RAM_reg_128_191_3_3_n_0, - I2 => Q(7), - I3 => RAM_reg_64_127_3_3_n_0, - I4 => Q(6), - I5 => RAM_reg_0_63_3_3_n_0, - O => \gpr1.dout_i[3]_i_5_n_0\ - ); -\gpr1.dout_i[3]_i_6\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => RAM_reg_448_511_3_3_n_0, - I1 => RAM_reg_384_447_3_3_n_0, - I2 => Q(7), - I3 => RAM_reg_320_383_3_3_n_0, - I4 => Q(6), - I5 => RAM_reg_256_319_3_3_n_0, - O => \gpr1.dout_i[3]_i_6_n_0\ - ); -\gpr1.dout_i[3]_i_7\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => RAM_reg_704_767_3_3_n_0, - I1 => RAM_reg_640_703_3_3_n_0, - I2 => Q(7), - I3 => RAM_reg_576_639_3_3_n_0, - I4 => Q(6), - I5 => RAM_reg_512_575_3_3_n_0, - O => \gpr1.dout_i[3]_i_7_n_0\ - ); -\gpr1.dout_i[3]_i_8\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => RAM_reg_960_1023_3_3_n_0, - I1 => RAM_reg_896_959_3_3_n_0, - I2 => Q(7), - I3 => RAM_reg_832_895_3_3_n_0, - I4 => Q(6), - I5 => RAM_reg_768_831_3_3_n_0, - O => \gpr1.dout_i[3]_i_8_n_0\ - ); -\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => p_0_out(0), - Q => dout(0) - ); -\gpr1.dout_i_reg[0]_i_1\: unisim.vcomponents.MUXF8 - port map ( - I0 => \gpr1.dout_i_reg[0]_i_2_n_0\, - I1 => \gpr1.dout_i_reg[0]_i_3_n_0\, - O => p_0_out(0), - S => Q(9) - ); -\gpr1.dout_i_reg[0]_i_2\: unisim.vcomponents.MUXF7 - port map ( - I0 => \gpr1.dout_i[0]_i_4_n_0\, - I1 => \gpr1.dout_i[0]_i_5_n_0\, - O => \gpr1.dout_i_reg[0]_i_2_n_0\, - S => Q(8) - ); -\gpr1.dout_i_reg[0]_i_3\: unisim.vcomponents.MUXF7 - port map ( - I0 => \gpr1.dout_i[0]_i_6_n_0\, - I1 => \gpr1.dout_i[0]_i_7_n_0\, - O => \gpr1.dout_i_reg[0]_i_3_n_0\, - S => Q(8) - ); -\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => p_0_out(1), - Q => dout(1) - ); -\gpr1.dout_i_reg[1]_i_1\: unisim.vcomponents.MUXF8 - port map ( - I0 => \gpr1.dout_i_reg[1]_i_2_n_0\, - I1 => \gpr1.dout_i_reg[1]_i_3_n_0\, - O => p_0_out(1), - S => Q(9) - ); -\gpr1.dout_i_reg[1]_i_2\: unisim.vcomponents.MUXF7 - port map ( - I0 => \gpr1.dout_i[1]_i_4_n_0\, - I1 => \gpr1.dout_i[1]_i_5_n_0\, - O => \gpr1.dout_i_reg[1]_i_2_n_0\, - S => Q(8) - ); -\gpr1.dout_i_reg[1]_i_3\: unisim.vcomponents.MUXF7 - port map ( - I0 => \gpr1.dout_i[1]_i_6_n_0\, - I1 => \gpr1.dout_i[1]_i_7_n_0\, - O => \gpr1.dout_i_reg[1]_i_3_n_0\, - S => Q(8) - ); -\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => p_0_out(2), - Q => dout(2) - ); -\gpr1.dout_i_reg[2]_i_1\: unisim.vcomponents.MUXF8 - port map ( - I0 => \gpr1.dout_i_reg[2]_i_2_n_0\, - I1 => \gpr1.dout_i_reg[2]_i_3_n_0\, - O => p_0_out(2), - S => Q(9) - ); -\gpr1.dout_i_reg[2]_i_2\: unisim.vcomponents.MUXF7 - port map ( - I0 => \gpr1.dout_i[2]_i_4_n_0\, - I1 => \gpr1.dout_i[2]_i_5_n_0\, - O => \gpr1.dout_i_reg[2]_i_2_n_0\, - S => Q(8) - ); -\gpr1.dout_i_reg[2]_i_3\: unisim.vcomponents.MUXF7 - port map ( - I0 => \gpr1.dout_i[2]_i_6_n_0\, - I1 => \gpr1.dout_i[2]_i_7_n_0\, - O => \gpr1.dout_i_reg[2]_i_3_n_0\, - S => Q(8) - ); -\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => p_0_out(3), - Q => dout(3) - ); -\gpr1.dout_i_reg[3]_i_2\: unisim.vcomponents.MUXF8 - port map ( - I0 => \gpr1.dout_i_reg[3]_i_3_n_0\, - I1 => \gpr1.dout_i_reg[3]_i_4_n_0\, - O => p_0_out(3), - S => Q(9) - ); -\gpr1.dout_i_reg[3]_i_3\: unisim.vcomponents.MUXF7 - port map ( - I0 => \gpr1.dout_i[3]_i_5_n_0\, - I1 => \gpr1.dout_i[3]_i_6_n_0\, - O => \gpr1.dout_i_reg[3]_i_3_n_0\, - S => Q(8) - ); -\gpr1.dout_i_reg[3]_i_4\: unisim.vcomponents.MUXF7 - port map ( - I0 => \gpr1.dout_i[3]_i_7_n_0\, - I1 => \gpr1.dout_i[3]_i_8_n_0\, - O => \gpr1.dout_i_reg[3]_i_4_n_0\, - S => Q(8) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_rd_bin_cntr is - port ( - v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 ); - Q : out STD_LOGIC_VECTOR ( 9 downto 0 ); - v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 ); - WR_PNTR_RD : in STD_LOGIC_VECTOR ( 9 downto 0 ); - E : in STD_LOGIC_VECTOR ( 0 to 0 ); - rd_clk : in STD_LOGIC; - AR : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_rd_bin_cntr : entity is "rd_bin_cntr"; -end fifo_AntCtrl_rd_bin_cntr; - -architecture STRUCTURE of fifo_AntCtrl_rd_bin_cntr is - signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 ); - signal \gc0.count[9]_i_2_n_0\ : STD_LOGIC; - signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 ); - signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 9 downto 0 ); - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair9"; - attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair9"; - attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair10"; - attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair10"; - attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair8"; - attribute SOFT_HLUTNM of \gc0.count[9]_i_1\ : label is "soft_lutpair8"; -begin - Q(9 downto 0) <= \^q\(9 downto 0); -\gc0.count[0]_i_1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => rd_pntr_plus1(0), - O => \plusOp__0\(0) - ); -\gc0.count[1]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => rd_pntr_plus1(0), - I1 => rd_pntr_plus1(1), - O => \plusOp__0\(1) - ); -\gc0.count[2]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"78" - ) - port map ( - I0 => rd_pntr_plus1(0), - I1 => rd_pntr_plus1(1), - I2 => rd_pntr_plus1(2), - O => \plusOp__0\(2) - ); -\gc0.count[3]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"7F80" - ) - port map ( - I0 => rd_pntr_plus1(1), - I1 => rd_pntr_plus1(0), - I2 => rd_pntr_plus1(2), - I3 => rd_pntr_plus1(3), - O => \plusOp__0\(3) - ); -\gc0.count[4]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"7FFF8000" - ) - port map ( - I0 => rd_pntr_plus1(2), - I1 => rd_pntr_plus1(0), - I2 => rd_pntr_plus1(1), - I3 => rd_pntr_plus1(3), - I4 => rd_pntr_plus1(4), - O => \plusOp__0\(4) - ); -\gc0.count[5]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"7FFFFFFF80000000" - ) - port map ( - I0 => rd_pntr_plus1(3), - I1 => rd_pntr_plus1(1), - I2 => rd_pntr_plus1(0), - I3 => rd_pntr_plus1(2), - I4 => rd_pntr_plus1(4), - I5 => rd_pntr_plus1(5), - O => \plusOp__0\(5) - ); -\gc0.count[6]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \gc0.count[9]_i_2_n_0\, - I1 => rd_pntr_plus1(6), - O => \plusOp__0\(6) - ); -\gc0.count[7]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"78" - ) - port map ( - I0 => \gc0.count[9]_i_2_n_0\, - I1 => rd_pntr_plus1(6), - I2 => rd_pntr_plus1(7), - O => \plusOp__0\(7) - ); -\gc0.count[8]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"7F80" - ) - port map ( - I0 => rd_pntr_plus1(6), - I1 => \gc0.count[9]_i_2_n_0\, - I2 => rd_pntr_plus1(7), - I3 => rd_pntr_plus1(8), - O => \plusOp__0\(8) - ); -\gc0.count[9]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"7FFF8000" - ) - port map ( - I0 => rd_pntr_plus1(7), - I1 => \gc0.count[9]_i_2_n_0\, - I2 => rd_pntr_plus1(6), - I3 => rd_pntr_plus1(8), - I4 => rd_pntr_plus1(9), - O => \plusOp__0\(9) - ); -\gc0.count[9]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"8000000000000000" - ) - port map ( - I0 => rd_pntr_plus1(5), - I1 => rd_pntr_plus1(3), - I2 => rd_pntr_plus1(1), - I3 => rd_pntr_plus1(0), - I4 => rd_pntr_plus1(2), - I5 => rd_pntr_plus1(4), - O => \gc0.count[9]_i_2_n_0\ - ); -\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => rd_pntr_plus1(0), - Q => \^q\(0) - ); -\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => rd_pntr_plus1(1), - Q => \^q\(1) - ); -\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => rd_pntr_plus1(2), - Q => \^q\(2) - ); -\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => rd_pntr_plus1(3), - Q => \^q\(3) - ); -\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => rd_pntr_plus1(4), - Q => \^q\(4) - ); -\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => rd_pntr_plus1(5), - Q => \^q\(5) - ); -\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => rd_pntr_plus1(6), - Q => \^q\(6) - ); -\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => rd_pntr_plus1(7), - Q => \^q\(7) - ); -\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => rd_pntr_plus1(8), - Q => \^q\(8) - ); -\gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => rd_pntr_plus1(9), - Q => \^q\(9) - ); -\gc0.count_reg[0]\: unisim.vcomponents.FDPE - generic map( - INIT => '1' - ) - port map ( - C => rd_clk, - CE => E(0), - D => \plusOp__0\(0), - PRE => AR(0), - Q => rd_pntr_plus1(0) - ); -\gc0.count_reg[1]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => \plusOp__0\(1), - Q => rd_pntr_plus1(1) - ); -\gc0.count_reg[2]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => \plusOp__0\(2), - Q => rd_pntr_plus1(2) - ); -\gc0.count_reg[3]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => \plusOp__0\(3), - Q => rd_pntr_plus1(3) - ); -\gc0.count_reg[4]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => \plusOp__0\(4), - Q => rd_pntr_plus1(4) - ); -\gc0.count_reg[5]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => \plusOp__0\(5), - Q => rd_pntr_plus1(5) - ); -\gc0.count_reg[6]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => \plusOp__0\(6), - Q => rd_pntr_plus1(6) - ); -\gc0.count_reg[7]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => \plusOp__0\(7), - Q => rd_pntr_plus1(7) - ); -\gc0.count_reg[8]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => \plusOp__0\(8), - Q => rd_pntr_plus1(8) - ); -\gc0.count_reg[9]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => E(0), - CLR => AR(0), - D => \plusOp__0\(9), - Q => rd_pntr_plus1(9) - ); -\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => \^q\(0), - I1 => WR_PNTR_RD(0), - I2 => \^q\(1), - I3 => WR_PNTR_RD(1), - O => v1_reg(0) - ); -\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => rd_pntr_plus1(0), - I1 => WR_PNTR_RD(0), - I2 => rd_pntr_plus1(1), - I3 => WR_PNTR_RD(1), - O => v1_reg_0(0) - ); -\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => \^q\(2), - I1 => WR_PNTR_RD(2), - I2 => \^q\(3), - I3 => WR_PNTR_RD(3), - O => v1_reg(1) - ); -\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => rd_pntr_plus1(2), - I1 => WR_PNTR_RD(2), - I2 => rd_pntr_plus1(3), - I3 => WR_PNTR_RD(3), - O => v1_reg_0(1) - ); -\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => \^q\(4), - I1 => WR_PNTR_RD(4), - I2 => \^q\(5), - I3 => WR_PNTR_RD(5), - O => v1_reg(2) - ); -\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => rd_pntr_plus1(4), - I1 => WR_PNTR_RD(4), - I2 => rd_pntr_plus1(5), - I3 => WR_PNTR_RD(5), - O => v1_reg_0(2) - ); -\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => \^q\(6), - I1 => WR_PNTR_RD(6), - I2 => \^q\(7), - I3 => WR_PNTR_RD(7), - O => v1_reg(3) - ); -\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => rd_pntr_plus1(6), - I1 => WR_PNTR_RD(6), - I2 => rd_pntr_plus1(7), - I3 => WR_PNTR_RD(7), - O => v1_reg_0(3) - ); -\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => \^q\(8), - I1 => WR_PNTR_RD(8), - I2 => \^q\(9), - I3 => WR_PNTR_RD(9), - O => v1_reg(4) - ); -\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => rd_pntr_plus1(8), - I1 => WR_PNTR_RD(8), - I2 => rd_pntr_plus1(9), - I3 => WR_PNTR_RD(9), - O => v1_reg_0(4) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_wr_bin_cntr is - port ( - ram_full_fb_i_reg : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 9 downto 0 ); - ram_full_fb_i_reg_0 : out STD_LOGIC; - ram_full_fb_i_reg_1 : out STD_LOGIC; - ram_full_fb_i_reg_2 : out STD_LOGIC; - ram_full_fb_i_reg_3 : out STD_LOGIC; - \gic0.gc0.count_d2_reg[9]_0\ : out STD_LOGIC; - \gic0.gc0.count_d2_reg[8]_0\ : out STD_LOGIC; - ram_full_fb_i_reg_4 : out STD_LOGIC; - \gic0.gc0.count_d2_reg[9]_1\ : out STD_LOGIC; - \gic0.gc0.count_d2_reg[7]_0\ : out STD_LOGIC; - \gic0.gc0.count_d2_reg[9]_2\ : out STD_LOGIC; - \gic0.gc0.count_d2_reg[6]_0\ : out STD_LOGIC; - \gic0.gc0.count_d2_reg[9]_3\ : out STD_LOGIC; - \gic0.gc0.count_d2_reg[8]_1\ : out STD_LOGIC; - \gic0.gc0.count_d2_reg[8]_2\ : out STD_LOGIC; - \gic0.gc0.count_d2_reg[7]_1\ : out STD_LOGIC; - \gic0.gc0.count_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 ); - \gic0.gc0.count_d1_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 ); - \out\ : in STD_LOGIC; - wr_en : in STD_LOGIC; - E : in STD_LOGIC_VECTOR ( 0 to 0 ); - wr_clk : in STD_LOGIC; - AR : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_wr_bin_cntr : entity is "wr_bin_cntr"; -end fifo_AntCtrl_wr_bin_cntr; - -architecture STRUCTURE of fifo_AntCtrl_wr_bin_cntr is - signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 ); - signal \gic0.gc0.count[9]_i_2_n_0\ : STD_LOGIC; - signal \^gic0.gc0.count_d1_reg[9]_0\ : STD_LOGIC_VECTOR ( 9 downto 0 ); - signal \^gic0.gc0.count_reg[9]_0\ : STD_LOGIC_VECTOR ( 9 downto 0 ); - signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 ); - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \gic0.gc0.count[0]_i_1\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair13"; - attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair13"; - attribute SOFT_HLUTNM of \gic0.gc0.count[6]_i_1\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \gic0.gc0.count[7]_i_1\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \gic0.gc0.count[8]_i_1\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of \gic0.gc0.count[9]_i_1\ : label is "soft_lutpair12"; -begin - Q(9 downto 0) <= \^q\(9 downto 0); - \gic0.gc0.count_d1_reg[9]_0\(9 downto 0) <= \^gic0.gc0.count_d1_reg[9]_0\(9 downto 0); - \gic0.gc0.count_reg[9]_0\(9 downto 0) <= \^gic0.gc0.count_reg[9]_0\(9 downto 0); -RAM_reg_0_63_0_2_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000000000004" - ) - port map ( - I0 => \out\, - I1 => wr_en, - I2 => \^q\(7), - I3 => \^q\(6), - I4 => \^q\(9), - I5 => \^q\(8), - O => ram_full_fb_i_reg_1 - ); -RAM_reg_128_191_0_2_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000400000000" - ) - port map ( - I0 => \out\, - I1 => wr_en, - I2 => \^q\(8), - I3 => \^q\(6), - I4 => \^q\(9), - I5 => \^q\(7), - O => ram_full_fb_i_reg_3 - ); -RAM_reg_192_255_0_2_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000004000000000" - ) - port map ( - I0 => \^q\(9), - I1 => \^q\(7), - I2 => \^q\(6), - I3 => \^q\(8), - I4 => \out\, - I5 => wr_en, - O => \gic0.gc0.count_d2_reg[9]_1\ - ); -RAM_reg_256_319_0_2_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000400000000" - ) - port map ( - I0 => \out\, - I1 => wr_en, - I2 => \^q\(7), - I3 => \^q\(6), - I4 => \^q\(9), - I5 => \^q\(8), - O => ram_full_fb_i_reg - ); -RAM_reg_320_383_0_2_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000004000000000" - ) - port map ( - I0 => \^q\(9), - I1 => \^q\(8), - I2 => \^q\(6), - I3 => \^q\(7), - I4 => \out\, - I5 => wr_en, - O => \gic0.gc0.count_d2_reg[9]_2\ - ); -RAM_reg_384_447_0_2_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000004000000000" - ) - port map ( - I0 => \^q\(9), - I1 => \^q\(8), - I2 => \^q\(7), - I3 => \^q\(6), - I4 => \out\, - I5 => wr_en, - O => \gic0.gc0.count_d2_reg[9]_3\ - ); -RAM_reg_448_511_0_2_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"0040000000000000" - ) - port map ( - I0 => \^q\(9), - I1 => \^q\(7), - I2 => \^q\(6), - I3 => \out\, - I4 => wr_en, - I5 => \^q\(8), - O => \gic0.gc0.count_d2_reg[9]_0\ - ); -RAM_reg_512_575_0_2_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000400000000" - ) - port map ( - I0 => \out\, - I1 => wr_en, - I2 => \^q\(7), - I3 => \^q\(6), - I4 => \^q\(8), - I5 => \^q\(9), - O => ram_full_fb_i_reg_0 - ); -RAM_reg_576_639_0_2_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000004000000000" - ) - port map ( - I0 => \^q\(8), - I1 => \^q\(9), - I2 => \^q\(6), - I3 => \^q\(7), - I4 => \out\, - I5 => wr_en, - O => \gic0.gc0.count_d2_reg[8]_1\ - ); -RAM_reg_640_703_0_2_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000004000000000" - ) - port map ( - I0 => \^q\(8), - I1 => \^q\(9), - I2 => \^q\(7), - I3 => \^q\(6), - I4 => \out\, - I5 => wr_en, - O => \gic0.gc0.count_d2_reg[8]_2\ - ); -RAM_reg_64_127_0_2_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000400000000" - ) - port map ( - I0 => \out\, - I1 => wr_en, - I2 => \^q\(8), - I3 => \^q\(7), - I4 => \^q\(9), - I5 => \^q\(6), - O => ram_full_fb_i_reg_2 - ); -RAM_reg_704_767_0_2_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"0040000000000000" - ) - port map ( - I0 => \^q\(8), - I1 => \^q\(7), - I2 => \^q\(6), - I3 => \out\, - I4 => wr_en, - I5 => \^q\(9), - O => \gic0.gc0.count_d2_reg[8]_0\ - ); -RAM_reg_768_831_0_2_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000004000000000" - ) - port map ( - I0 => \^q\(7), - I1 => \^q\(9), - I2 => \^q\(8), - I3 => \^q\(6), - I4 => \out\, - I5 => wr_en, - O => \gic0.gc0.count_d2_reg[7]_1\ - ); -RAM_reg_832_895_0_2_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"0040000000000000" - ) - port map ( - I0 => \^q\(7), - I1 => \^q\(8), - I2 => \^q\(6), - I3 => \out\, - I4 => wr_en, - I5 => \^q\(9), - O => \gic0.gc0.count_d2_reg[7]_0\ - ); -RAM_reg_896_959_0_2_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"0040000000000000" - ) - port map ( - I0 => \^q\(6), - I1 => \^q\(8), - I2 => \^q\(7), - I3 => \out\, - I4 => wr_en, - I5 => \^q\(9), - O => \gic0.gc0.count_d2_reg[6]_0\ - ); -RAM_reg_960_1023_0_2_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"4000000000000000" - ) - port map ( - I0 => \out\, - I1 => wr_en, - I2 => \^q\(7), - I3 => \^q\(6), - I4 => \^q\(9), - I5 => \^q\(8), - O => ram_full_fb_i_reg_4 - ); -\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \^gic0.gc0.count_reg[9]_0\(0), - O => plusOp(0) - ); -\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \^gic0.gc0.count_reg[9]_0\(0), - I1 => \^gic0.gc0.count_reg[9]_0\(1), - O => plusOp(1) - ); -\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"78" - ) - port map ( - I0 => \^gic0.gc0.count_reg[9]_0\(0), - I1 => \^gic0.gc0.count_reg[9]_0\(1), - I2 => \^gic0.gc0.count_reg[9]_0\(2), - O => plusOp(2) - ); -\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"7F80" - ) - port map ( - I0 => \^gic0.gc0.count_reg[9]_0\(1), - I1 => \^gic0.gc0.count_reg[9]_0\(0), - I2 => \^gic0.gc0.count_reg[9]_0\(2), - I3 => \^gic0.gc0.count_reg[9]_0\(3), - O => plusOp(3) - ); -\gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"7FFF8000" - ) - port map ( - I0 => \^gic0.gc0.count_reg[9]_0\(2), - I1 => \^gic0.gc0.count_reg[9]_0\(0), - I2 => \^gic0.gc0.count_reg[9]_0\(1), - I3 => \^gic0.gc0.count_reg[9]_0\(3), - I4 => \^gic0.gc0.count_reg[9]_0\(4), - O => plusOp(4) - ); -\gic0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"7FFFFFFF80000000" - ) - port map ( - I0 => \^gic0.gc0.count_reg[9]_0\(3), - I1 => \^gic0.gc0.count_reg[9]_0\(1), - I2 => \^gic0.gc0.count_reg[9]_0\(0), - I3 => \^gic0.gc0.count_reg[9]_0\(2), - I4 => \^gic0.gc0.count_reg[9]_0\(4), - I5 => \^gic0.gc0.count_reg[9]_0\(5), - O => plusOp(5) - ); -\gic0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \gic0.gc0.count[9]_i_2_n_0\, - I1 => \^gic0.gc0.count_reg[9]_0\(6), - O => plusOp(6) - ); -\gic0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"78" - ) - port map ( - I0 => \gic0.gc0.count[9]_i_2_n_0\, - I1 => \^gic0.gc0.count_reg[9]_0\(6), - I2 => \^gic0.gc0.count_reg[9]_0\(7), - O => plusOp(7) - ); -\gic0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"7F80" - ) - port map ( - I0 => \^gic0.gc0.count_reg[9]_0\(6), - I1 => \gic0.gc0.count[9]_i_2_n_0\, - I2 => \^gic0.gc0.count_reg[9]_0\(7), - I3 => \^gic0.gc0.count_reg[9]_0\(8), - O => plusOp(8) - ); -\gic0.gc0.count[9]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"7FFF8000" - ) - port map ( - I0 => \^gic0.gc0.count_reg[9]_0\(7), - I1 => \gic0.gc0.count[9]_i_2_n_0\, - I2 => \^gic0.gc0.count_reg[9]_0\(6), - I3 => \^gic0.gc0.count_reg[9]_0\(8), - I4 => \^gic0.gc0.count_reg[9]_0\(9), - O => plusOp(9) - ); -\gic0.gc0.count[9]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"8000000000000000" - ) - port map ( - I0 => \^gic0.gc0.count_reg[9]_0\(5), - I1 => \^gic0.gc0.count_reg[9]_0\(3), - I2 => \^gic0.gc0.count_reg[9]_0\(1), - I3 => \^gic0.gc0.count_reg[9]_0\(0), - I4 => \^gic0.gc0.count_reg[9]_0\(2), - I5 => \^gic0.gc0.count_reg[9]_0\(4), - O => \gic0.gc0.count[9]_i_2_n_0\ - ); -\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE - generic map( - INIT => '1' - ) - port map ( - C => wr_clk, - CE => E(0), - D => \^gic0.gc0.count_reg[9]_0\(0), - PRE => AR(0), - Q => \^gic0.gc0.count_d1_reg[9]_0\(0) - ); -\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => \^gic0.gc0.count_reg[9]_0\(1), - Q => \^gic0.gc0.count_d1_reg[9]_0\(1) - ); -\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => \^gic0.gc0.count_reg[9]_0\(2), - Q => \^gic0.gc0.count_d1_reg[9]_0\(2) - ); -\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => \^gic0.gc0.count_reg[9]_0\(3), - Q => \^gic0.gc0.count_d1_reg[9]_0\(3) - ); -\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => \^gic0.gc0.count_reg[9]_0\(4), - Q => \^gic0.gc0.count_d1_reg[9]_0\(4) - ); -\gic0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => \^gic0.gc0.count_reg[9]_0\(5), - Q => \^gic0.gc0.count_d1_reg[9]_0\(5) - ); -\gic0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => \^gic0.gc0.count_reg[9]_0\(6), - Q => \^gic0.gc0.count_d1_reg[9]_0\(6) - ); -\gic0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => \^gic0.gc0.count_reg[9]_0\(7), - Q => \^gic0.gc0.count_d1_reg[9]_0\(7) - ); -\gic0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => \^gic0.gc0.count_reg[9]_0\(8), - Q => \^gic0.gc0.count_d1_reg[9]_0\(8) - ); -\gic0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => \^gic0.gc0.count_reg[9]_0\(9), - Q => \^gic0.gc0.count_d1_reg[9]_0\(9) - ); -\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => \^gic0.gc0.count_d1_reg[9]_0\(0), - Q => \^q\(0) - ); -\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => \^gic0.gc0.count_d1_reg[9]_0\(1), - Q => \^q\(1) - ); -\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => \^gic0.gc0.count_d1_reg[9]_0\(2), - Q => \^q\(2) - ); -\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => \^gic0.gc0.count_d1_reg[9]_0\(3), - Q => \^q\(3) - ); -\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => \^gic0.gc0.count_d1_reg[9]_0\(4), - Q => \^q\(4) - ); -\gic0.gc0.count_d2_reg[5]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => \^gic0.gc0.count_d1_reg[9]_0\(5), - Q => \^q\(5) - ); -\gic0.gc0.count_d2_reg[6]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => \^gic0.gc0.count_d1_reg[9]_0\(6), - Q => \^q\(6) - ); -\gic0.gc0.count_d2_reg[7]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => \^gic0.gc0.count_d1_reg[9]_0\(7), - Q => \^q\(7) - ); -\gic0.gc0.count_d2_reg[8]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => \^gic0.gc0.count_d1_reg[9]_0\(8), - Q => \^q\(8) - ); -\gic0.gc0.count_d2_reg[9]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => \^gic0.gc0.count_d1_reg[9]_0\(9), - Q => \^q\(9) - ); -\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => plusOp(0), - Q => \^gic0.gc0.count_reg[9]_0\(0) - ); -\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE - generic map( - INIT => '1' - ) - port map ( - C => wr_clk, - CE => E(0), - D => plusOp(1), - PRE => AR(0), - Q => \^gic0.gc0.count_reg[9]_0\(1) - ); -\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => plusOp(2), - Q => \^gic0.gc0.count_reg[9]_0\(2) - ); -\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => plusOp(3), - Q => \^gic0.gc0.count_reg[9]_0\(3) - ); -\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => plusOp(4), - Q => \^gic0.gc0.count_reg[9]_0\(4) - ); -\gic0.gc0.count_reg[5]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => plusOp(5), - Q => \^gic0.gc0.count_reg[9]_0\(5) - ); -\gic0.gc0.count_reg[6]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => plusOp(6), - Q => \^gic0.gc0.count_reg[9]_0\(6) - ); -\gic0.gc0.count_reg[7]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => plusOp(7), - Q => \^gic0.gc0.count_reg[9]_0\(7) - ); -\gic0.gc0.count_reg[8]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => plusOp(8), - Q => \^gic0.gc0.count_reg[9]_0\(8) - ); -\gic0.gc0.count_reg[9]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => E(0), - CLR => AR(0), - D => plusOp(9), - Q => \^gic0.gc0.count_reg[9]_0\(9) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_clk_x_pntrs is - port ( - v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 ); - v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 ); - WR_PNTR_RD : out STD_LOGIC_VECTOR ( 9 downto 0 ); - Q : in STD_LOGIC_VECTOR ( 9 downto 0 ); - \gmux.gm[4].gms.ms\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); - wr_clk : in STD_LOGIC; - \src_gray_ff_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); - rd_clk : in STD_LOGIC; - \src_gray_ff_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_clk_x_pntrs : entity is "clk_x_pntrs"; -end fifo_AntCtrl_clk_x_pntrs; - -architecture STRUCTURE of fifo_AntCtrl_clk_x_pntrs is - signal p_25_out : STD_LOGIC_VECTOR ( 9 downto 0 ); - attribute DEST_SYNC_FF : integer; - attribute DEST_SYNC_FF of rd_pntr_cdc_inst : label is 2; - attribute INIT_SYNC_FF : integer; - attribute INIT_SYNC_FF of rd_pntr_cdc_inst : label is 0; - attribute REG_OUTPUT : integer; - attribute REG_OUTPUT of rd_pntr_cdc_inst : label is 1; - attribute SIM_ASSERT_CHK : integer; - attribute SIM_ASSERT_CHK of rd_pntr_cdc_inst : label is 0; - attribute SIM_LOSSLESS_GRAY_CHK : integer; - attribute SIM_LOSSLESS_GRAY_CHK of rd_pntr_cdc_inst : label is 0; - attribute VERSION : integer; - attribute VERSION of rd_pntr_cdc_inst : label is 0; - attribute WIDTH : integer; - attribute WIDTH of rd_pntr_cdc_inst : label is 10; - attribute XPM_CDC : string; - attribute XPM_CDC of rd_pntr_cdc_inst : label is "GRAY"; - attribute XPM_MODULE : string; - attribute XPM_MODULE of rd_pntr_cdc_inst : label is "TRUE"; - attribute DEST_SYNC_FF of wr_pntr_cdc_inst : label is 2; - attribute INIT_SYNC_FF of wr_pntr_cdc_inst : label is 0; - attribute REG_OUTPUT of wr_pntr_cdc_inst : label is 1; - attribute SIM_ASSERT_CHK of wr_pntr_cdc_inst : label is 0; - attribute SIM_LOSSLESS_GRAY_CHK of wr_pntr_cdc_inst : label is 0; - attribute VERSION of wr_pntr_cdc_inst : label is 0; - attribute WIDTH of wr_pntr_cdc_inst : label is 10; - attribute XPM_CDC of wr_pntr_cdc_inst : label is "GRAY"; - attribute XPM_MODULE of wr_pntr_cdc_inst : label is "TRUE"; -begin -\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => p_25_out(0), - I1 => Q(0), - I2 => p_25_out(1), - I3 => Q(1), - O => v1_reg(0) - ); -\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => p_25_out(0), - I1 => \gmux.gm[4].gms.ms\(0), - I2 => p_25_out(1), - I3 => \gmux.gm[4].gms.ms\(1), - O => v1_reg_0(0) - ); -\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => p_25_out(2), - I1 => Q(2), - I2 => p_25_out(3), - I3 => Q(3), - O => v1_reg(1) - ); -\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => p_25_out(2), - I1 => \gmux.gm[4].gms.ms\(2), - I2 => p_25_out(3), - I3 => \gmux.gm[4].gms.ms\(3), - O => v1_reg_0(1) - ); -\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => p_25_out(4), - I1 => Q(4), - I2 => p_25_out(5), - I3 => Q(5), - O => v1_reg(2) - ); -\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => p_25_out(4), - I1 => \gmux.gm[4].gms.ms\(4), - I2 => p_25_out(5), - I3 => \gmux.gm[4].gms.ms\(5), - O => v1_reg_0(2) - ); -\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => p_25_out(6), - I1 => Q(6), - I2 => p_25_out(7), - I3 => Q(7), - O => v1_reg(3) - ); -\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => p_25_out(6), - I1 => \gmux.gm[4].gms.ms\(6), - I2 => p_25_out(7), - I3 => \gmux.gm[4].gms.ms\(7), - O => v1_reg_0(3) - ); -\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => p_25_out(8), - I1 => Q(8), - I2 => p_25_out(9), - I3 => Q(9), - O => v1_reg(4) - ); -\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => p_25_out(8), - I1 => \gmux.gm[4].gms.ms\(8), - I2 => p_25_out(9), - I3 => \gmux.gm[4].gms.ms\(9), - O => v1_reg_0(4) - ); -rd_pntr_cdc_inst: entity work.fifo_AntCtrl_xpm_cdc_gray - port map ( - dest_clk => wr_clk, - dest_out_bin(9 downto 0) => p_25_out(9 downto 0), - src_clk => rd_clk, - src_in_bin(9 downto 0) => \src_gray_ff_reg[9]_0\(9 downto 0) - ); -wr_pntr_cdc_inst: entity work.\fifo_AntCtrl_xpm_cdc_gray__2\ - port map ( - dest_clk => rd_clk, - dest_out_bin(9 downto 0) => WR_PNTR_RD(9 downto 0), - src_clk => wr_clk, - src_in_bin(9 downto 0) => \src_gray_ff_reg[9]\(9 downto 0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_memory is - port ( - dout : out STD_LOGIC_VECTOR ( 3 downto 0 ); - wr_clk : in STD_LOGIC; - din : in STD_LOGIC_VECTOR ( 3 downto 0 ); - \gpr1.dout_i[2]_i_4\ : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 9 downto 0 ); - \gpr1.dout_i[3]_i_8\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); - \gpr1.dout_i[2]_i_4_0\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_4_1\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_4_2\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_5\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_5_0\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_5_1\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_5_2\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_6\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_6_0\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_6_1\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_6_2\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_7\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_7_0\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_7_1\ : in STD_LOGIC; - \gpr1.dout_i[2]_i_7_2\ : in STD_LOGIC; - E : in STD_LOGIC_VECTOR ( 0 to 0 ); - rd_clk : in STD_LOGIC; - AR : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_memory : entity is "memory"; -end fifo_AntCtrl_memory; - -architecture STRUCTURE of fifo_AntCtrl_memory is -begin -\gdm.dm_gen.dm\: entity work.fifo_AntCtrl_dmem - port map ( - AR(0) => AR(0), - E(0) => E(0), - Q(9 downto 0) => Q(9 downto 0), - din(3 downto 0) => din(3 downto 0), - dout(3 downto 0) => dout(3 downto 0), - \gpr1.dout_i[2]_i_4_0\ => \gpr1.dout_i[2]_i_4\, - \gpr1.dout_i[2]_i_4_1\ => \gpr1.dout_i[2]_i_4_0\, - \gpr1.dout_i[2]_i_4_2\ => \gpr1.dout_i[2]_i_4_1\, - \gpr1.dout_i[2]_i_4_3\ => \gpr1.dout_i[2]_i_4_2\, - \gpr1.dout_i[2]_i_5_0\ => \gpr1.dout_i[2]_i_5\, - \gpr1.dout_i[2]_i_5_1\ => \gpr1.dout_i[2]_i_5_0\, - \gpr1.dout_i[2]_i_5_2\ => \gpr1.dout_i[2]_i_5_1\, - \gpr1.dout_i[2]_i_5_3\ => \gpr1.dout_i[2]_i_5_2\, - \gpr1.dout_i[2]_i_6_0\ => \gpr1.dout_i[2]_i_6\, - \gpr1.dout_i[2]_i_6_1\ => \gpr1.dout_i[2]_i_6_0\, - \gpr1.dout_i[2]_i_6_2\ => \gpr1.dout_i[2]_i_6_1\, - \gpr1.dout_i[2]_i_6_3\ => \gpr1.dout_i[2]_i_6_2\, - \gpr1.dout_i[2]_i_7_0\ => \gpr1.dout_i[2]_i_7\, - \gpr1.dout_i[2]_i_7_1\ => \gpr1.dout_i[2]_i_7_0\, - \gpr1.dout_i[2]_i_7_2\ => \gpr1.dout_i[2]_i_7_1\, - \gpr1.dout_i[2]_i_7_3\ => \gpr1.dout_i[2]_i_7_2\, - \gpr1.dout_i[3]_i_8_0\(5 downto 0) => \gpr1.dout_i[3]_i_8\(5 downto 0), - rd_clk => rd_clk, - wr_clk => wr_clk - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_rd_status_flags_as is - port ( - empty : out STD_LOGIC; - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 ); - v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 ); - rd_clk : in STD_LOGIC; - AR : in STD_LOGIC_VECTOR ( 0 to 0 ); - rd_en : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_rd_status_flags_as : entity is "rd_status_flags_as"; -end fifo_AntCtrl_rd_status_flags_as; - -architecture STRUCTURE of fifo_AntCtrl_rd_status_flags_as is - signal c0_n_0 : STD_LOGIC; - signal comp1 : STD_LOGIC; - signal ram_empty_fb_i : STD_LOGIC; - attribute DONT_TOUCH : boolean; - attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true; - signal ram_empty_i : STD_LOGIC; - attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true; - attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of ram_empty_fb_i_reg : label is "yes"; - attribute equivalent_register_removal : string; - attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no"; - attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true; - attribute KEEP of ram_empty_i_reg : label is "yes"; - attribute equivalent_register_removal of ram_empty_i_reg : label is "no"; -begin - empty <= ram_empty_i; -c0: entity work.fifo_AntCtrl_compare_1 - port map ( - comp1 => comp1, - \out\ => ram_empty_fb_i, - rd_en => rd_en, - rd_en_0 => c0_n_0, - v1_reg(4 downto 0) => v1_reg(4 downto 0) - ); -c1: entity work.fifo_AntCtrl_compare_2 - port map ( - comp1 => comp1, - v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0) - ); -\gpr1.dout_i[3]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"2" - ) - port map ( - I0 => rd_en, - I1 => ram_empty_fb_i, - O => E(0) - ); -ram_empty_fb_i_reg: unisim.vcomponents.FDPE - generic map( - INIT => '1' - ) - port map ( - C => rd_clk, - CE => '1', - D => c0_n_0, - PRE => AR(0), - Q => ram_empty_fb_i - ); -ram_empty_i_reg: unisim.vcomponents.FDPE - generic map( - INIT => '1' - ) - port map ( - C => rd_clk, - CE => '1', - D => c0_n_0, - PRE => AR(0), - Q => ram_empty_i - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_reset_blk_ramfifo is - port ( - AR : out STD_LOGIC_VECTOR ( 0 to 0 ); - \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \out\ : out STD_LOGIC; - \grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC; - wr_rst_busy : out STD_LOGIC; - rst : in STD_LOGIC; - wr_clk : in STD_LOGIC; - rd_clk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_reset_blk_ramfifo : entity is "reset_blk_ramfifo"; -end fifo_AntCtrl_reset_blk_ramfifo; - -architecture STRUCTURE of fifo_AntCtrl_reset_blk_ramfifo is - signal \^ar\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal dest_out : STD_LOGIC; - signal \grstd1.grst_full.grst_f.rst_d3_i_1_n_0\ : STD_LOGIC; - signal \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_i_1_n_0\ : STD_LOGIC; - signal \^ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_i_1_n_0\ : STD_LOGIC; - signal \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_i_1_n_0\ : STD_LOGIC; - signal rd_rst_wr_ext : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal rst_d1 : STD_LOGIC; - attribute async_reg : string; - attribute async_reg of rst_d1 : signal is "true"; - attribute msgon : string; - attribute msgon of rst_d1 : signal is "true"; - signal rst_d2 : STD_LOGIC; - attribute async_reg of rst_d2 : signal is "true"; - attribute msgon of rst_d2 : signal is "true"; - signal rst_d3 : STD_LOGIC; - attribute async_reg of rst_d3 : signal is "true"; - attribute msgon of rst_d3 : signal is "true"; - signal rst_rd_reg2 : STD_LOGIC; - attribute async_reg of rst_rd_reg2 : signal is "true"; - attribute msgon of rst_rd_reg2 : signal is "true"; - signal rst_wr_reg2 : STD_LOGIC; - attribute async_reg of rst_wr_reg2 : signal is "true"; - attribute msgon of rst_wr_reg2 : signal is "true"; - signal sckt_rd_rst_wr : STD_LOGIC; - signal \^wr_rst_busy\ : STD_LOGIC; - signal wr_rst_rd_ext : STD_LOGIC_VECTOR ( 1 downto 0 ); - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes"; - attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true"; - attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true; - attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes"; - attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true"; - attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true; - attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes"; - attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true"; - attribute DEF_VAL : string; - attribute DEF_VAL of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst\ : label is "1'b0"; - attribute DEST_SYNC_FF : integer; - attribute DEST_SYNC_FF of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst\ : label is 2; - attribute INIT_SYNC_FF : integer; - attribute INIT_SYNC_FF of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst\ : label is 0; - attribute INV_DEF_VAL : string; - attribute INV_DEF_VAL of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst\ : label is "1'b1"; - attribute RST_ACTIVE_HIGH : integer; - attribute RST_ACTIVE_HIGH of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst\ : label is 1; - attribute VERSION : integer; - attribute VERSION of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst\ : label is 0; - attribute XPM_CDC : string; - attribute XPM_CDC of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst\ : label is "ASYNC_RST"; - attribute XPM_MODULE : string; - attribute XPM_MODULE of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst\ : label is "TRUE"; - attribute DEST_SYNC_FF of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr\ : label is 4; - attribute INIT_SYNC_FF of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr\ : label is 0; - attribute SIM_ASSERT_CHK : integer; - attribute SIM_ASSERT_CHK of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr\ : label is 0; - attribute SRC_INPUT_REG : integer; - attribute SRC_INPUT_REG of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr\ : label is 0; - attribute VERSION of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr\ : label is 0; - attribute XPM_CDC of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr\ : label is "SINGLE"; - attribute XPM_MODULE of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr\ : label is "TRUE"; - attribute DEST_SYNC_FF of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd\ : label is 4; - attribute INIT_SYNC_FF of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd\ : label is 0; - attribute SIM_ASSERT_CHK of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd\ : label is 0; - attribute SRC_INPUT_REG of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd\ : label is 0; - attribute VERSION of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd\ : label is 0; - attribute XPM_CDC of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd\ : label is "SINGLE"; - attribute XPM_MODULE of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd\ : label is "TRUE"; - attribute DEF_VAL of \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst\ : label is "1'b0"; - attribute DEST_SYNC_FF of \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst\ : label is 2; - attribute INIT_SYNC_FF of \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst\ : label is 0; - attribute INV_DEF_VAL of \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst\ : label is "1'b1"; - attribute RST_ACTIVE_HIGH of \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst\ : label is 1; - attribute VERSION of \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst\ : label is 0; - attribute XPM_CDC of \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst\ : label is "ASYNC_RST"; - attribute XPM_MODULE of \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst\ : label is "TRUE"; -begin - AR(0) <= \^ar\(0); - \grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d3; - \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0\(0) <= \^ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0\(0); - \out\ <= rst_d2; - wr_rst_busy <= \^wr_rst_busy\; -\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE - generic map( - INIT => '1' - ) - port map ( - C => wr_clk, - CE => '1', - D => \^wr_rst_busy\, - PRE => rst_wr_reg2, - Q => rst_d1 - ); -\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE - generic map( - INIT => '1' - ) - port map ( - C => wr_clk, - CE => '1', - D => rst_d1, - PRE => rst_wr_reg2, - Q => rst_d2 - ); -\grstd1.grst_full.grst_f.rst_d3_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"E" - ) - port map ( - I0 => rst_d2, - I1 => \^ar\(0), - O => \grstd1.grst_full.grst_f.rst_d3_i_1_n_0\ - ); -\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE - generic map( - INIT => '1' - ) - port map ( - C => wr_clk, - CE => '1', - D => \grstd1.grst_full.grst_f.rst_d3_i_1_n_0\, - PRE => rst_wr_reg2, - Q => rst_d3 - ); -\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[0]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => '1', - CLR => rst_wr_reg2, - D => sckt_rd_rst_wr, - Q => rd_rst_wr_ext(0) - ); -\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[1]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => '1', - CLR => rst_wr_reg2, - D => rd_rst_wr_ext(0), - Q => rd_rst_wr_ext(1) - ); -\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[2]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => '1', - CLR => rst_wr_reg2, - D => rd_rst_wr_ext(1), - Q => rd_rst_wr_ext(2) - ); -\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[3]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => '1', - CLR => rst_wr_reg2, - D => rd_rst_wr_ext(2), - Q => rd_rst_wr_ext(3) - ); -\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst\: entity work.fifo_AntCtrl_xpm_cdc_async_rst - port map ( - dest_arst => rst_rd_reg2, - dest_clk => rd_clk, - src_arst => rst - ); -\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"2" - ) - port map ( - I0 => \^ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0\(0), - I1 => wr_rst_rd_ext(1), - O => \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_i_1_n_0\ - ); -\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg\: unisim.vcomponents.FDPE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => '1', - D => \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_i_1_n_0\, - PRE => rst_rd_reg2, - Q => \^ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0\(0) - ); -\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"8A" - ) - port map ( - I0 => \^ar\(0), - I1 => rd_rst_wr_ext(0), - I2 => rd_rst_wr_ext(1), - O => \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_i_1_n_0\ - ); -\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg\: unisim.vcomponents.FDPE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => '1', - D => \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_i_1_n_0\, - PRE => rst_wr_reg2, - Q => \^ar\(0) - ); -\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"AAAA08AA" - ) - port map ( - I0 => \^wr_rst_busy\, - I1 => rd_rst_wr_ext(1), - I2 => rd_rst_wr_ext(0), - I3 => rd_rst_wr_ext(3), - I4 => rd_rst_wr_ext(2), - O => \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_i_1_n_0\ - ); -\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_reg\: unisim.vcomponents.FDPE - generic map( - INIT => '0' - ) - port map ( - C => wr_clk, - CE => '1', - D => \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_i_1_n_0\, - PRE => rst_wr_reg2, - Q => \^wr_rst_busy\ - ); -\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => '1', - CLR => rst_rd_reg2, - D => dest_out, - Q => wr_rst_rd_ext(0) - ); -\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[1]\: unisim.vcomponents.FDCE - generic map( - INIT => '0' - ) - port map ( - C => rd_clk, - CE => '1', - CLR => rst_rd_reg2, - D => wr_rst_rd_ext(0), - Q => wr_rst_rd_ext(1) - ); -\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr\: entity work.fifo_AntCtrl_xpm_cdc_single - port map ( - dest_clk => wr_clk, - dest_out => sckt_rd_rst_wr, - src_clk => rd_clk, - src_in => \^ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0\(0) - ); -\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd\: entity work.\fifo_AntCtrl_xpm_cdc_single__2\ - port map ( - dest_clk => rd_clk, - dest_out => dest_out, - src_clk => wr_clk, - src_in => \^ar\(0) - ); -\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst\: entity work.\fifo_AntCtrl_xpm_cdc_async_rst__2\ - port map ( - dest_arst => rst_wr_reg2, - dest_clk => wr_clk, - src_arst => rst - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_wr_status_flags_as is - port ( - full : out STD_LOGIC; - \out\ : out STD_LOGIC; - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 ); - v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 ); - wr_clk : in STD_LOGIC; - ram_full_fb_i_reg_0 : in STD_LOGIC; - wr_en : in STD_LOGIC; - ram_full_fb_i_reg_1 : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_wr_status_flags_as : entity is "wr_status_flags_as"; -end fifo_AntCtrl_wr_status_flags_as; - -architecture STRUCTURE of fifo_AntCtrl_wr_status_flags_as is - signal c2_n_0 : STD_LOGIC; - signal comp1 : STD_LOGIC; - signal ram_full_fb_i : STD_LOGIC; - attribute DONT_TOUCH : boolean; - attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true; - signal ram_full_i : STD_LOGIC; - attribute DONT_TOUCH of ram_full_i : signal is std.standard.true; - attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of ram_full_fb_i_reg : label is "yes"; - attribute equivalent_register_removal : string; - attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no"; - attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true; - attribute KEEP of ram_full_i_reg : label is "yes"; - attribute equivalent_register_removal of ram_full_i_reg : label is "no"; -begin - full <= ram_full_i; - \out\ <= ram_full_fb_i; -c1: entity work.fifo_AntCtrl_compare - port map ( - comp1 => comp1, - v1_reg(4 downto 0) => v1_reg(4 downto 0) - ); -c2: entity work.fifo_AntCtrl_compare_0 - port map ( - comp1 => comp1, - \out\ => ram_full_fb_i, - ram_full_fb_i_reg => c2_n_0, - ram_full_fb_i_reg_0 => ram_full_fb_i_reg_1, - v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0), - wr_en => wr_en - ); -\gic0.gc0.count_d1[9]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"2" - ) - port map ( - I0 => wr_en, - I1 => ram_full_fb_i, - O => E(0) - ); -ram_full_fb_i_reg: unisim.vcomponents.FDPE - generic map( - INIT => '1' - ) - port map ( - C => wr_clk, - CE => '1', - D => c2_n_0, - PRE => ram_full_fb_i_reg_0, - Q => ram_full_fb_i - ); -ram_full_i_reg: unisim.vcomponents.FDPE - generic map( - INIT => '1' - ) - port map ( - C => wr_clk, - CE => '1', - D => c2_n_0, - PRE => ram_full_fb_i_reg_0, - Q => ram_full_i - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_rd_logic is - port ( - empty : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 9 downto 0 ); - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - rd_clk : in STD_LOGIC; - AR : in STD_LOGIC_VECTOR ( 0 to 0 ); - rd_en : in STD_LOGIC; - WR_PNTR_RD : in STD_LOGIC_VECTOR ( 9 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_rd_logic : entity is "rd_logic"; -end fifo_AntCtrl_rd_logic; - -architecture STRUCTURE of fifo_AntCtrl_rd_logic is - signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 ); -begin - E(0) <= \^e\(0); -\gras.rsts\: entity work.fifo_AntCtrl_rd_status_flags_as - port map ( - AR(0) => AR(0), - E(0) => \^e\(0), - empty => empty, - rd_clk => rd_clk, - rd_en => rd_en, - v1_reg(4 downto 0) => \c0/v1_reg\(4 downto 0), - v1_reg_0(4 downto 0) => \c1/v1_reg\(4 downto 0) - ); -rpntr: entity work.fifo_AntCtrl_rd_bin_cntr - port map ( - AR(0) => AR(0), - E(0) => \^e\(0), - Q(9 downto 0) => Q(9 downto 0), - WR_PNTR_RD(9 downto 0) => WR_PNTR_RD(9 downto 0), - rd_clk => rd_clk, - v1_reg(4 downto 0) => \c0/v1_reg\(4 downto 0), - v1_reg_0(4 downto 0) => \c1/v1_reg\(4 downto 0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_wr_logic is - port ( - full : out STD_LOGIC; - ram_full_fb_i_reg : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 9 downto 0 ); - ram_full_fb_i_reg_0 : out STD_LOGIC; - ram_full_fb_i_reg_1 : out STD_LOGIC; - ram_full_fb_i_reg_2 : out STD_LOGIC; - ram_full_fb_i_reg_3 : out STD_LOGIC; - \gic0.gc0.count_d2_reg[9]\ : out STD_LOGIC; - \gic0.gc0.count_d2_reg[8]\ : out STD_LOGIC; - ram_full_fb_i_reg_4 : out STD_LOGIC; - \gic0.gc0.count_d2_reg[9]_0\ : out STD_LOGIC; - \gic0.gc0.count_d2_reg[7]\ : out STD_LOGIC; - \gic0.gc0.count_d2_reg[9]_1\ : out STD_LOGIC; - \gic0.gc0.count_d2_reg[6]\ : out STD_LOGIC; - \gic0.gc0.count_d2_reg[9]_2\ : out STD_LOGIC; - \gic0.gc0.count_d2_reg[8]_0\ : out STD_LOGIC; - \gic0.gc0.count_d2_reg[8]_1\ : out STD_LOGIC; - \gic0.gc0.count_d2_reg[7]_0\ : out STD_LOGIC; - \gic0.gc0.count_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 ); - \gic0.gc0.count_d1_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 ); - v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 ); - v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 ); - wr_clk : in STD_LOGIC; - \out\ : in STD_LOGIC; - wr_en : in STD_LOGIC; - ram_full_fb_i_reg_5 : in STD_LOGIC; - AR : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_wr_logic : entity is "wr_logic"; -end fifo_AntCtrl_wr_logic; - -architecture STRUCTURE of fifo_AntCtrl_wr_logic is - signal \gwas.wsts_n_1\ : STD_LOGIC; - signal p_20_out : STD_LOGIC; -begin -\gwas.wsts\: entity work.fifo_AntCtrl_wr_status_flags_as - port map ( - E(0) => p_20_out, - full => full, - \out\ => \gwas.wsts_n_1\, - ram_full_fb_i_reg_0 => \out\, - ram_full_fb_i_reg_1 => ram_full_fb_i_reg_5, - v1_reg(4 downto 0) => v1_reg(4 downto 0), - v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0), - wr_clk => wr_clk, - wr_en => wr_en - ); -wpntr: entity work.fifo_AntCtrl_wr_bin_cntr - port map ( - AR(0) => AR(0), - E(0) => p_20_out, - Q(9 downto 0) => Q(9 downto 0), - \gic0.gc0.count_d1_reg[9]_0\(9 downto 0) => \gic0.gc0.count_d1_reg[9]\(9 downto 0), - \gic0.gc0.count_d2_reg[6]_0\ => \gic0.gc0.count_d2_reg[6]\, - \gic0.gc0.count_d2_reg[7]_0\ => \gic0.gc0.count_d2_reg[7]\, - \gic0.gc0.count_d2_reg[7]_1\ => \gic0.gc0.count_d2_reg[7]_0\, - \gic0.gc0.count_d2_reg[8]_0\ => \gic0.gc0.count_d2_reg[8]\, - \gic0.gc0.count_d2_reg[8]_1\ => \gic0.gc0.count_d2_reg[8]_0\, - \gic0.gc0.count_d2_reg[8]_2\ => \gic0.gc0.count_d2_reg[8]_1\, - \gic0.gc0.count_d2_reg[9]_0\ => \gic0.gc0.count_d2_reg[9]\, - \gic0.gc0.count_d2_reg[9]_1\ => \gic0.gc0.count_d2_reg[9]_0\, - \gic0.gc0.count_d2_reg[9]_2\ => \gic0.gc0.count_d2_reg[9]_1\, - \gic0.gc0.count_d2_reg[9]_3\ => \gic0.gc0.count_d2_reg[9]_2\, - \gic0.gc0.count_reg[9]_0\(9 downto 0) => \gic0.gc0.count_reg[9]\(9 downto 0), - \out\ => \gwas.wsts_n_1\, - ram_full_fb_i_reg => ram_full_fb_i_reg, - ram_full_fb_i_reg_0 => ram_full_fb_i_reg_0, - ram_full_fb_i_reg_1 => ram_full_fb_i_reg_1, - ram_full_fb_i_reg_2 => ram_full_fb_i_reg_2, - ram_full_fb_i_reg_3 => ram_full_fb_i_reg_3, - ram_full_fb_i_reg_4 => ram_full_fb_i_reg_4, - wr_clk => wr_clk, - wr_en => wr_en - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_fifo_generator_ramfifo is - port ( - wr_rst_busy : out STD_LOGIC; - AR : out STD_LOGIC_VECTOR ( 0 to 0 ); - empty : out STD_LOGIC; - full : out STD_LOGIC; - dout : out STD_LOGIC_VECTOR ( 3 downto 0 ); - rst : in STD_LOGIC; - wr_clk : in STD_LOGIC; - rd_clk : in STD_LOGIC; - din : in STD_LOGIC_VECTOR ( 3 downto 0 ); - wr_en : in STD_LOGIC; - rd_en : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo"; -end fifo_AntCtrl_fifo_generator_ramfifo; - -architecture STRUCTURE of fifo_AntCtrl_fifo_generator_ramfifo is - signal \^ar\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \gntv_or_sync_fifo.gl0.wr_n_1\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_12\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_13\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_14\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_15\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_16\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_17\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_18\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_19\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_20\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_21\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_22\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_23\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_24\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_25\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_26\ : STD_LOGIC; - signal \gwas.wsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal \gwas.wsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal p_0_out_0 : STD_LOGIC_VECTOR ( 9 downto 0 ); - signal p_13_out : STD_LOGIC_VECTOR ( 9 downto 0 ); - signal p_14_out : STD_LOGIC_VECTOR ( 9 downto 0 ); - signal p_24_out : STD_LOGIC_VECTOR ( 9 downto 0 ); - signal ram_rd_en_i : STD_LOGIC; - signal rst_full_ff_i : STD_LOGIC; - signal rst_full_gen_i : STD_LOGIC; - signal rstblk_n_0 : STD_LOGIC; - signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 9 downto 0 ); -begin - AR(0) <= \^ar\(0); -\gntv_or_sync_fifo.gcx.clkx\: entity work.fifo_AntCtrl_clk_x_pntrs - port map ( - Q(9 downto 0) => p_14_out(9 downto 0), - WR_PNTR_RD(9 downto 0) => p_24_out(9 downto 0), - \gmux.gm[4].gms.ms\(9 downto 0) => wr_pntr_plus2(9 downto 0), - rd_clk => rd_clk, - \src_gray_ff_reg[9]\(9 downto 0) => p_13_out(9 downto 0), - \src_gray_ff_reg[9]_0\(9 downto 0) => p_0_out_0(9 downto 0), - v1_reg(4 downto 0) => \gwas.wsts/c1/v1_reg\(4 downto 0), - v1_reg_0(4 downto 0) => \gwas.wsts/c2/v1_reg\(4 downto 0), - wr_clk => wr_clk - ); -\gntv_or_sync_fifo.gl0.rd\: entity work.fifo_AntCtrl_rd_logic - port map ( - AR(0) => \^ar\(0), - E(0) => ram_rd_en_i, - Q(9 downto 0) => p_0_out_0(9 downto 0), - WR_PNTR_RD(9 downto 0) => p_24_out(9 downto 0), - empty => empty, - rd_clk => rd_clk, - rd_en => rd_en - ); -\gntv_or_sync_fifo.gl0.wr\: entity work.fifo_AntCtrl_wr_logic - port map ( - AR(0) => rstblk_n_0, - Q(9 downto 0) => p_13_out(9 downto 0), - full => full, - \gic0.gc0.count_d1_reg[9]\(9 downto 0) => p_14_out(9 downto 0), - \gic0.gc0.count_d2_reg[6]\ => \gntv_or_sync_fifo.gl0.wr_n_22\, - \gic0.gc0.count_d2_reg[7]\ => \gntv_or_sync_fifo.gl0.wr_n_20\, - \gic0.gc0.count_d2_reg[7]_0\ => \gntv_or_sync_fifo.gl0.wr_n_26\, - \gic0.gc0.count_d2_reg[8]\ => \gntv_or_sync_fifo.gl0.wr_n_17\, - \gic0.gc0.count_d2_reg[8]_0\ => \gntv_or_sync_fifo.gl0.wr_n_24\, - \gic0.gc0.count_d2_reg[8]_1\ => \gntv_or_sync_fifo.gl0.wr_n_25\, - \gic0.gc0.count_d2_reg[9]\ => \gntv_or_sync_fifo.gl0.wr_n_16\, - \gic0.gc0.count_d2_reg[9]_0\ => \gntv_or_sync_fifo.gl0.wr_n_19\, - \gic0.gc0.count_d2_reg[9]_1\ => \gntv_or_sync_fifo.gl0.wr_n_21\, - \gic0.gc0.count_d2_reg[9]_2\ => \gntv_or_sync_fifo.gl0.wr_n_23\, - \gic0.gc0.count_reg[9]\(9 downto 0) => wr_pntr_plus2(9 downto 0), - \out\ => rst_full_ff_i, - ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_1\, - ram_full_fb_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_12\, - ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_13\, - ram_full_fb_i_reg_2 => \gntv_or_sync_fifo.gl0.wr_n_14\, - ram_full_fb_i_reg_3 => \gntv_or_sync_fifo.gl0.wr_n_15\, - ram_full_fb_i_reg_4 => \gntv_or_sync_fifo.gl0.wr_n_18\, - ram_full_fb_i_reg_5 => rst_full_gen_i, - v1_reg(4 downto 0) => \gwas.wsts/c1/v1_reg\(4 downto 0), - v1_reg_0(4 downto 0) => \gwas.wsts/c2/v1_reg\(4 downto 0), - wr_clk => wr_clk, - wr_en => wr_en - ); -\gntv_or_sync_fifo.mem\: entity work.fifo_AntCtrl_memory - port map ( - AR(0) => \^ar\(0), - E(0) => ram_rd_en_i, - Q(9 downto 0) => p_0_out_0(9 downto 0), - din(3 downto 0) => din(3 downto 0), - dout(3 downto 0) => dout(3 downto 0), - \gpr1.dout_i[2]_i_4\ => \gntv_or_sync_fifo.gl0.wr_n_13\, - \gpr1.dout_i[2]_i_4_0\ => \gntv_or_sync_fifo.gl0.wr_n_14\, - \gpr1.dout_i[2]_i_4_1\ => \gntv_or_sync_fifo.gl0.wr_n_15\, - \gpr1.dout_i[2]_i_4_2\ => \gntv_or_sync_fifo.gl0.wr_n_19\, - \gpr1.dout_i[2]_i_5\ => \gntv_or_sync_fifo.gl0.wr_n_1\, - \gpr1.dout_i[2]_i_5_0\ => \gntv_or_sync_fifo.gl0.wr_n_21\, - \gpr1.dout_i[2]_i_5_1\ => \gntv_or_sync_fifo.gl0.wr_n_23\, - \gpr1.dout_i[2]_i_5_2\ => \gntv_or_sync_fifo.gl0.wr_n_16\, - \gpr1.dout_i[2]_i_6\ => \gntv_or_sync_fifo.gl0.wr_n_12\, - \gpr1.dout_i[2]_i_6_0\ => \gntv_or_sync_fifo.gl0.wr_n_24\, - \gpr1.dout_i[2]_i_6_1\ => \gntv_or_sync_fifo.gl0.wr_n_25\, - \gpr1.dout_i[2]_i_6_2\ => \gntv_or_sync_fifo.gl0.wr_n_17\, - \gpr1.dout_i[2]_i_7\ => \gntv_or_sync_fifo.gl0.wr_n_26\, - \gpr1.dout_i[2]_i_7_0\ => \gntv_or_sync_fifo.gl0.wr_n_20\, - \gpr1.dout_i[2]_i_7_1\ => \gntv_or_sync_fifo.gl0.wr_n_22\, - \gpr1.dout_i[2]_i_7_2\ => \gntv_or_sync_fifo.gl0.wr_n_18\, - \gpr1.dout_i[3]_i_8\(5 downto 0) => p_13_out(5 downto 0), - rd_clk => rd_clk, - wr_clk => wr_clk - ); -rstblk: entity work.fifo_AntCtrl_reset_blk_ramfifo - port map ( - AR(0) => rstblk_n_0, - \grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_gen_i, - \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0\(0) => \^ar\(0), - \out\ => rst_full_ff_i, - rd_clk => rd_clk, - rst => rst, - wr_clk => wr_clk, - wr_rst_busy => wr_rst_busy - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_fifo_generator_top is - port ( - wr_rst_busy : out STD_LOGIC; - AR : out STD_LOGIC_VECTOR ( 0 to 0 ); - empty : out STD_LOGIC; - full : out STD_LOGIC; - dout : out STD_LOGIC_VECTOR ( 3 downto 0 ); - rst : in STD_LOGIC; - wr_clk : in STD_LOGIC; - rd_clk : in STD_LOGIC; - din : in STD_LOGIC_VECTOR ( 3 downto 0 ); - wr_en : in STD_LOGIC; - rd_en : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_fifo_generator_top : entity is "fifo_generator_top"; -end fifo_AntCtrl_fifo_generator_top; - -architecture STRUCTURE of fifo_AntCtrl_fifo_generator_top is -begin -\grf.rf\: entity work.fifo_AntCtrl_fifo_generator_ramfifo - port map ( - AR(0) => AR(0), - din(3 downto 0) => din(3 downto 0), - dout(3 downto 0) => dout(3 downto 0), - empty => empty, - full => full, - rd_clk => rd_clk, - rd_en => rd_en, - rst => rst, - wr_clk => wr_clk, - wr_en => wr_en, - wr_rst_busy => wr_rst_busy - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_fifo_generator_v13_2_4_synth is - port ( - wr_rst_busy : out STD_LOGIC; - AR : out STD_LOGIC_VECTOR ( 0 to 0 ); - empty : out STD_LOGIC; - full : out STD_LOGIC; - dout : out STD_LOGIC_VECTOR ( 3 downto 0 ); - rst : in STD_LOGIC; - wr_clk : in STD_LOGIC; - rd_clk : in STD_LOGIC; - din : in STD_LOGIC_VECTOR ( 3 downto 0 ); - wr_en : in STD_LOGIC; - rd_en : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_fifo_generator_v13_2_4_synth : entity is "fifo_generator_v13_2_4_synth"; -end fifo_AntCtrl_fifo_generator_v13_2_4_synth; - -architecture STRUCTURE of fifo_AntCtrl_fifo_generator_v13_2_4_synth is -begin -\gconvfifo.rf\: entity work.fifo_AntCtrl_fifo_generator_top - port map ( - AR(0) => AR(0), - din(3 downto 0) => din(3 downto 0), - dout(3 downto 0) => dout(3 downto 0), - empty => empty, - full => full, - rd_clk => rd_clk, - rd_en => rd_en, - rst => rst, - wr_clk => wr_clk, - wr_en => wr_en, - wr_rst_busy => wr_rst_busy - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl_fifo_generator_v13_2_4 is - port ( - backup : in STD_LOGIC; - backup_marker : in STD_LOGIC; - clk : in STD_LOGIC; - rst : in STD_LOGIC; - srst : in STD_LOGIC; - wr_clk : in STD_LOGIC; - wr_rst : in STD_LOGIC; - rd_clk : in STD_LOGIC; - rd_rst : in STD_LOGIC; - din : in STD_LOGIC_VECTOR ( 3 downto 0 ); - wr_en : in STD_LOGIC; - rd_en : in STD_LOGIC; - prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); - prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 ); - prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 ); - prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); - prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 ); - prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 ); - int_clk : in STD_LOGIC; - injectdbiterr : in STD_LOGIC; - injectsbiterr : in STD_LOGIC; - sleep : in STD_LOGIC; - dout : out STD_LOGIC_VECTOR ( 3 downto 0 ); - full : out STD_LOGIC; - almost_full : out STD_LOGIC; - wr_ack : out STD_LOGIC; - overflow : out STD_LOGIC; - empty : out STD_LOGIC; - almost_empty : out STD_LOGIC; - valid : out STD_LOGIC; - underflow : out STD_LOGIC; - data_count : out STD_LOGIC_VECTOR ( 9 downto 0 ); - rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 ); - wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 ); - prog_full : out STD_LOGIC; - prog_empty : out STD_LOGIC; - sbiterr : out STD_LOGIC; - dbiterr : out STD_LOGIC; - wr_rst_busy : out STD_LOGIC; - rd_rst_busy : out STD_LOGIC; - m_aclk : in STD_LOGIC; - s_aclk : in STD_LOGIC; - s_aresetn : in STD_LOGIC; - m_aclk_en : in STD_LOGIC; - s_aclk_en : in STD_LOGIC; - s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_awvalid : in STD_LOGIC; - s_axi_awready : out STD_LOGIC; - s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); - s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axi_wlast : in STD_LOGIC; - s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_wvalid : in STD_LOGIC; - s_axi_wready : out STD_LOGIC; - s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_bvalid : out STD_LOGIC; - s_axi_bready : in STD_LOGIC; - m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); - m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); - m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); - m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_awvalid : out STD_LOGIC; - m_axi_awready : in STD_LOGIC; - m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); - m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); - m_axi_wlast : out STD_LOGIC; - m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_wvalid : out STD_LOGIC; - m_axi_wready : in STD_LOGIC; - m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_bvalid : in STD_LOGIC; - m_axi_bready : out STD_LOGIC; - s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_arvalid : in STD_LOGIC; - s_axi_arready : out STD_LOGIC; - s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); - s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_rlast : out STD_LOGIC; - s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_rvalid : out STD_LOGIC; - s_axi_rready : in STD_LOGIC; - m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); - m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); - m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); - m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_arvalid : out STD_LOGIC; - m_axi_arready : in STD_LOGIC; - m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); - m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_rlast : in STD_LOGIC; - m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_rvalid : in STD_LOGIC; - m_axi_rready : out STD_LOGIC; - s_axis_tvalid : in STD_LOGIC; - s_axis_tready : out STD_LOGIC; - s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axis_tlast : in STD_LOGIC; - s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axis_tvalid : out STD_LOGIC; - m_axis_tready : in STD_LOGIC; - m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); - m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_tlast : out STD_LOGIC; - m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 ); - axi_aw_injectsbiterr : in STD_LOGIC; - axi_aw_injectdbiterr : in STD_LOGIC; - axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); - axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); - axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); - axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); - axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); - axi_aw_sbiterr : out STD_LOGIC; - axi_aw_dbiterr : out STD_LOGIC; - axi_aw_overflow : out STD_LOGIC; - axi_aw_underflow : out STD_LOGIC; - axi_aw_prog_full : out STD_LOGIC; - axi_aw_prog_empty : out STD_LOGIC; - axi_w_injectsbiterr : in STD_LOGIC; - axi_w_injectdbiterr : in STD_LOGIC; - axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); - axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); - axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); - axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); - axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); - axi_w_sbiterr : out STD_LOGIC; - axi_w_dbiterr : out STD_LOGIC; - axi_w_overflow : out STD_LOGIC; - axi_w_underflow : out STD_LOGIC; - axi_w_prog_full : out STD_LOGIC; - axi_w_prog_empty : out STD_LOGIC; - axi_b_injectsbiterr : in STD_LOGIC; - axi_b_injectdbiterr : in STD_LOGIC; - axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); - axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); - axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); - axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); - axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); - axi_b_sbiterr : out STD_LOGIC; - axi_b_dbiterr : out STD_LOGIC; - axi_b_overflow : out STD_LOGIC; - axi_b_underflow : out STD_LOGIC; - axi_b_prog_full : out STD_LOGIC; - axi_b_prog_empty : out STD_LOGIC; - axi_ar_injectsbiterr : in STD_LOGIC; - axi_ar_injectdbiterr : in STD_LOGIC; - axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); - axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); - axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); - axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); - axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); - axi_ar_sbiterr : out STD_LOGIC; - axi_ar_dbiterr : out STD_LOGIC; - axi_ar_overflow : out STD_LOGIC; - axi_ar_underflow : out STD_LOGIC; - axi_ar_prog_full : out STD_LOGIC; - axi_ar_prog_empty : out STD_LOGIC; - axi_r_injectsbiterr : in STD_LOGIC; - axi_r_injectdbiterr : in STD_LOGIC; - axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); - axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); - axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); - axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); - axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); - axi_r_sbiterr : out STD_LOGIC; - axi_r_dbiterr : out STD_LOGIC; - axi_r_overflow : out STD_LOGIC; - axi_r_underflow : out STD_LOGIC; - axi_r_prog_full : out STD_LOGIC; - axi_r_prog_empty : out STD_LOGIC; - axis_injectsbiterr : in STD_LOGIC; - axis_injectdbiterr : in STD_LOGIC; - axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); - axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); - axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); - axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); - axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); - axis_sbiterr : out STD_LOGIC; - axis_dbiterr : out STD_LOGIC; - axis_overflow : out STD_LOGIC; - axis_underflow : out STD_LOGIC; - axis_prog_full : out STD_LOGIC; - axis_prog_empty : out STD_LOGIC - ); - attribute C_ADD_NGC_CONSTRAINT : integer; - attribute C_ADD_NGC_CONSTRAINT of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_APPLICATION_TYPE_AXIS : integer; - attribute C_APPLICATION_TYPE_AXIS of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_APPLICATION_TYPE_RACH : integer; - attribute C_APPLICATION_TYPE_RACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_APPLICATION_TYPE_RDCH : integer; - attribute C_APPLICATION_TYPE_RDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_APPLICATION_TYPE_WACH : integer; - attribute C_APPLICATION_TYPE_WACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_APPLICATION_TYPE_WDCH : integer; - attribute C_APPLICATION_TYPE_WDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_APPLICATION_TYPE_WRCH : integer; - attribute C_APPLICATION_TYPE_WRCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_AXIS_TDATA_WIDTH : integer; - attribute C_AXIS_TDATA_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 8; - attribute C_AXIS_TDEST_WIDTH : integer; - attribute C_AXIS_TDEST_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_AXIS_TID_WIDTH : integer; - attribute C_AXIS_TID_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_AXIS_TKEEP_WIDTH : integer; - attribute C_AXIS_TKEEP_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_AXIS_TSTRB_WIDTH : integer; - attribute C_AXIS_TSTRB_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_AXIS_TUSER_WIDTH : integer; - attribute C_AXIS_TUSER_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 4; - attribute C_AXIS_TYPE : integer; - attribute C_AXIS_TYPE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_AXI_ADDR_WIDTH : integer; - attribute C_AXI_ADDR_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 32; - attribute C_AXI_ARUSER_WIDTH : integer; - attribute C_AXI_ARUSER_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_AXI_AWUSER_WIDTH : integer; - attribute C_AXI_AWUSER_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_AXI_BUSER_WIDTH : integer; - attribute C_AXI_BUSER_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_AXI_DATA_WIDTH : integer; - attribute C_AXI_DATA_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 64; - attribute C_AXI_ID_WIDTH : integer; - attribute C_AXI_ID_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_AXI_LEN_WIDTH : integer; - attribute C_AXI_LEN_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 8; - attribute C_AXI_LOCK_WIDTH : integer; - attribute C_AXI_LOCK_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_AXI_RUSER_WIDTH : integer; - attribute C_AXI_RUSER_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_AXI_TYPE : integer; - attribute C_AXI_TYPE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_AXI_WUSER_WIDTH : integer; - attribute C_AXI_WUSER_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_COMMON_CLOCK : integer; - attribute C_COMMON_CLOCK of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_COUNT_TYPE : integer; - attribute C_COUNT_TYPE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_DATA_COUNT_WIDTH : integer; - attribute C_DATA_COUNT_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 10; - attribute C_DEFAULT_VALUE : string; - attribute C_DEFAULT_VALUE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is "BlankString"; - attribute C_DIN_WIDTH : integer; - attribute C_DIN_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 4; - attribute C_DIN_WIDTH_AXIS : integer; - attribute C_DIN_WIDTH_AXIS of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_DIN_WIDTH_RACH : integer; - attribute C_DIN_WIDTH_RACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 32; - attribute C_DIN_WIDTH_RDCH : integer; - attribute C_DIN_WIDTH_RDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 64; - attribute C_DIN_WIDTH_WACH : integer; - attribute C_DIN_WIDTH_WACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_DIN_WIDTH_WDCH : integer; - attribute C_DIN_WIDTH_WDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 64; - attribute C_DIN_WIDTH_WRCH : integer; - attribute C_DIN_WIDTH_WRCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 2; - attribute C_DOUT_RST_VAL : string; - attribute C_DOUT_RST_VAL of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is "0"; - attribute C_DOUT_WIDTH : integer; - attribute C_DOUT_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 4; - attribute C_ENABLE_RLOCS : integer; - attribute C_ENABLE_RLOCS of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_ENABLE_RST_SYNC : integer; - attribute C_ENABLE_RST_SYNC of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_EN_SAFETY_CKT : integer; - attribute C_EN_SAFETY_CKT of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_ERROR_INJECTION_TYPE : integer; - attribute C_ERROR_INJECTION_TYPE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_ERROR_INJECTION_TYPE_AXIS : integer; - attribute C_ERROR_INJECTION_TYPE_AXIS of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_ERROR_INJECTION_TYPE_RACH : integer; - attribute C_ERROR_INJECTION_TYPE_RACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_ERROR_INJECTION_TYPE_RDCH : integer; - attribute C_ERROR_INJECTION_TYPE_RDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_ERROR_INJECTION_TYPE_WACH : integer; - attribute C_ERROR_INJECTION_TYPE_WACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_ERROR_INJECTION_TYPE_WDCH : integer; - attribute C_ERROR_INJECTION_TYPE_WDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_ERROR_INJECTION_TYPE_WRCH : integer; - attribute C_ERROR_INJECTION_TYPE_WRCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_FAMILY : string; - attribute C_FAMILY of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is "kintex7"; - attribute C_FULL_FLAGS_RST_VAL : integer; - attribute C_FULL_FLAGS_RST_VAL of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_HAS_ALMOST_EMPTY : integer; - attribute C_HAS_ALMOST_EMPTY of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_ALMOST_FULL : integer; - attribute C_HAS_ALMOST_FULL of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_AXIS_TDATA : integer; - attribute C_HAS_AXIS_TDATA of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_HAS_AXIS_TDEST : integer; - attribute C_HAS_AXIS_TDEST of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_AXIS_TID : integer; - attribute C_HAS_AXIS_TID of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_AXIS_TKEEP : integer; - attribute C_HAS_AXIS_TKEEP of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_AXIS_TLAST : integer; - attribute C_HAS_AXIS_TLAST of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_AXIS_TREADY : integer; - attribute C_HAS_AXIS_TREADY of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_HAS_AXIS_TSTRB : integer; - attribute C_HAS_AXIS_TSTRB of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_AXIS_TUSER : integer; - attribute C_HAS_AXIS_TUSER of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_HAS_AXI_ARUSER : integer; - attribute C_HAS_AXI_ARUSER of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_AXI_AWUSER : integer; - attribute C_HAS_AXI_AWUSER of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_AXI_BUSER : integer; - attribute C_HAS_AXI_BUSER of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_AXI_ID : integer; - attribute C_HAS_AXI_ID of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_AXI_RD_CHANNEL : integer; - attribute C_HAS_AXI_RD_CHANNEL of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_HAS_AXI_RUSER : integer; - attribute C_HAS_AXI_RUSER of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_AXI_WR_CHANNEL : integer; - attribute C_HAS_AXI_WR_CHANNEL of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_HAS_AXI_WUSER : integer; - attribute C_HAS_AXI_WUSER of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_BACKUP : integer; - attribute C_HAS_BACKUP of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_DATA_COUNT : integer; - attribute C_HAS_DATA_COUNT of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_DATA_COUNTS_AXIS : integer; - attribute C_HAS_DATA_COUNTS_AXIS of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_DATA_COUNTS_RACH : integer; - attribute C_HAS_DATA_COUNTS_RACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_DATA_COUNTS_RDCH : integer; - attribute C_HAS_DATA_COUNTS_RDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_DATA_COUNTS_WACH : integer; - attribute C_HAS_DATA_COUNTS_WACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_DATA_COUNTS_WDCH : integer; - attribute C_HAS_DATA_COUNTS_WDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_DATA_COUNTS_WRCH : integer; - attribute C_HAS_DATA_COUNTS_WRCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_INT_CLK : integer; - attribute C_HAS_INT_CLK of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_MASTER_CE : integer; - attribute C_HAS_MASTER_CE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_MEMINIT_FILE : integer; - attribute C_HAS_MEMINIT_FILE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_OVERFLOW : integer; - attribute C_HAS_OVERFLOW of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_PROG_FLAGS_AXIS : integer; - attribute C_HAS_PROG_FLAGS_AXIS of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_PROG_FLAGS_RACH : integer; - attribute C_HAS_PROG_FLAGS_RACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_PROG_FLAGS_RDCH : integer; - attribute C_HAS_PROG_FLAGS_RDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_PROG_FLAGS_WACH : integer; - attribute C_HAS_PROG_FLAGS_WACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_PROG_FLAGS_WDCH : integer; - attribute C_HAS_PROG_FLAGS_WDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_PROG_FLAGS_WRCH : integer; - attribute C_HAS_PROG_FLAGS_WRCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_RD_DATA_COUNT : integer; - attribute C_HAS_RD_DATA_COUNT of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_RD_RST : integer; - attribute C_HAS_RD_RST of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_RST : integer; - attribute C_HAS_RST of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_HAS_SLAVE_CE : integer; - attribute C_HAS_SLAVE_CE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_SRST : integer; - attribute C_HAS_SRST of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_UNDERFLOW : integer; - attribute C_HAS_UNDERFLOW of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_VALID : integer; - attribute C_HAS_VALID of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_WR_ACK : integer; - attribute C_HAS_WR_ACK of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_WR_DATA_COUNT : integer; - attribute C_HAS_WR_DATA_COUNT of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_HAS_WR_RST : integer; - attribute C_HAS_WR_RST of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_IMPLEMENTATION_TYPE : integer; - attribute C_IMPLEMENTATION_TYPE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 2; - attribute C_IMPLEMENTATION_TYPE_AXIS : integer; - attribute C_IMPLEMENTATION_TYPE_AXIS of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_IMPLEMENTATION_TYPE_RACH : integer; - attribute C_IMPLEMENTATION_TYPE_RACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_IMPLEMENTATION_TYPE_RDCH : integer; - attribute C_IMPLEMENTATION_TYPE_RDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_IMPLEMENTATION_TYPE_WACH : integer; - attribute C_IMPLEMENTATION_TYPE_WACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_IMPLEMENTATION_TYPE_WDCH : integer; - attribute C_IMPLEMENTATION_TYPE_WDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_IMPLEMENTATION_TYPE_WRCH : integer; - attribute C_IMPLEMENTATION_TYPE_WRCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_INIT_WR_PNTR_VAL : integer; - attribute C_INIT_WR_PNTR_VAL of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_INTERFACE_TYPE : integer; - attribute C_INTERFACE_TYPE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_MEMORY_TYPE : integer; - attribute C_MEMORY_TYPE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 2; - attribute C_MIF_FILE_NAME : string; - attribute C_MIF_FILE_NAME of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is "BlankString"; - attribute C_MSGON_VAL : integer; - attribute C_MSGON_VAL of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_OPTIMIZATION_MODE : integer; - attribute C_OPTIMIZATION_MODE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_OVERFLOW_LOW : integer; - attribute C_OVERFLOW_LOW of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_POWER_SAVING_MODE : integer; - attribute C_POWER_SAVING_MODE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_PRELOAD_LATENCY : integer; - attribute C_PRELOAD_LATENCY of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_PRELOAD_REGS : integer; - attribute C_PRELOAD_REGS of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_PRIM_FIFO_TYPE : string; - attribute C_PRIM_FIFO_TYPE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is "1kx18"; - attribute C_PRIM_FIFO_TYPE_AXIS : string; - attribute C_PRIM_FIFO_TYPE_AXIS of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is "1kx18"; - attribute C_PRIM_FIFO_TYPE_RACH : string; - attribute C_PRIM_FIFO_TYPE_RACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is "512x36"; - attribute C_PRIM_FIFO_TYPE_RDCH : string; - attribute C_PRIM_FIFO_TYPE_RDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is "1kx36"; - attribute C_PRIM_FIFO_TYPE_WACH : string; - attribute C_PRIM_FIFO_TYPE_WACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is "512x36"; - attribute C_PRIM_FIFO_TYPE_WDCH : string; - attribute C_PRIM_FIFO_TYPE_WDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is "1kx36"; - attribute C_PRIM_FIFO_TYPE_WRCH : string; - attribute C_PRIM_FIFO_TYPE_WRCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is "512x36"; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 2; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1022; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1022; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1022; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1022; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1022; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1022; - attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer; - attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 3; - attribute C_PROG_EMPTY_TYPE : integer; - attribute C_PROG_EMPTY_TYPE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_PROG_EMPTY_TYPE_AXIS : integer; - attribute C_PROG_EMPTY_TYPE_AXIS of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_PROG_EMPTY_TYPE_RACH : integer; - attribute C_PROG_EMPTY_TYPE_RACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_PROG_EMPTY_TYPE_RDCH : integer; - attribute C_PROG_EMPTY_TYPE_RDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_PROG_EMPTY_TYPE_WACH : integer; - attribute C_PROG_EMPTY_TYPE_WACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_PROG_EMPTY_TYPE_WDCH : integer; - attribute C_PROG_EMPTY_TYPE_WDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_PROG_EMPTY_TYPE_WRCH : integer; - attribute C_PROG_EMPTY_TYPE_WRCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1021; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1023; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1023; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1023; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1023; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1023; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1023; - attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer; - attribute C_PROG_FULL_THRESH_NEGATE_VAL of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1020; - attribute C_PROG_FULL_TYPE : integer; - attribute C_PROG_FULL_TYPE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_PROG_FULL_TYPE_AXIS : integer; - attribute C_PROG_FULL_TYPE_AXIS of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_PROG_FULL_TYPE_RACH : integer; - attribute C_PROG_FULL_TYPE_RACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_PROG_FULL_TYPE_RDCH : integer; - attribute C_PROG_FULL_TYPE_RDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_PROG_FULL_TYPE_WACH : integer; - attribute C_PROG_FULL_TYPE_WACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_PROG_FULL_TYPE_WDCH : integer; - attribute C_PROG_FULL_TYPE_WDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_PROG_FULL_TYPE_WRCH : integer; - attribute C_PROG_FULL_TYPE_WRCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_RACH_TYPE : integer; - attribute C_RACH_TYPE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_RDCH_TYPE : integer; - attribute C_RDCH_TYPE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_RD_DATA_COUNT_WIDTH : integer; - attribute C_RD_DATA_COUNT_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 10; - attribute C_RD_DEPTH : integer; - attribute C_RD_DEPTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1024; - attribute C_RD_FREQ : integer; - attribute C_RD_FREQ of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_RD_PNTR_WIDTH : integer; - attribute C_RD_PNTR_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 10; - attribute C_REG_SLICE_MODE_AXIS : integer; - attribute C_REG_SLICE_MODE_AXIS of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_REG_SLICE_MODE_RACH : integer; - attribute C_REG_SLICE_MODE_RACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_REG_SLICE_MODE_RDCH : integer; - attribute C_REG_SLICE_MODE_RDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_REG_SLICE_MODE_WACH : integer; - attribute C_REG_SLICE_MODE_WACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_REG_SLICE_MODE_WDCH : integer; - attribute C_REG_SLICE_MODE_WDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_REG_SLICE_MODE_WRCH : integer; - attribute C_REG_SLICE_MODE_WRCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_SELECT_XPM : integer; - attribute C_SELECT_XPM of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_SYNCHRONIZER_STAGE : integer; - attribute C_SYNCHRONIZER_STAGE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 2; - attribute C_UNDERFLOW_LOW : integer; - attribute C_UNDERFLOW_LOW of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_USE_COMMON_OVERFLOW : integer; - attribute C_USE_COMMON_OVERFLOW of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_USE_COMMON_UNDERFLOW : integer; - attribute C_USE_COMMON_UNDERFLOW of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_USE_DEFAULT_SETTINGS : integer; - attribute C_USE_DEFAULT_SETTINGS of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_USE_DOUT_RST : integer; - attribute C_USE_DOUT_RST of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_USE_ECC : integer; - attribute C_USE_ECC of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_USE_ECC_AXIS : integer; - attribute C_USE_ECC_AXIS of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_USE_ECC_RACH : integer; - attribute C_USE_ECC_RACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_USE_ECC_RDCH : integer; - attribute C_USE_ECC_RDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_USE_ECC_WACH : integer; - attribute C_USE_ECC_WACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_USE_ECC_WDCH : integer; - attribute C_USE_ECC_WDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_USE_ECC_WRCH : integer; - attribute C_USE_ECC_WRCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_USE_EMBEDDED_REG : integer; - attribute C_USE_EMBEDDED_REG of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_USE_FIFO16_FLAGS : integer; - attribute C_USE_FIFO16_FLAGS of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_USE_FWFT_DATA_COUNT : integer; - attribute C_USE_FWFT_DATA_COUNT of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_USE_PIPELINE_REG : integer; - attribute C_USE_PIPELINE_REG of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_VALID_LOW : integer; - attribute C_VALID_LOW of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_WACH_TYPE : integer; - attribute C_WACH_TYPE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_WDCH_TYPE : integer; - attribute C_WDCH_TYPE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_WRCH_TYPE : integer; - attribute C_WRCH_TYPE of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_WR_ACK_LOW : integer; - attribute C_WR_ACK_LOW of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 0; - attribute C_WR_DATA_COUNT_WIDTH : integer; - attribute C_WR_DATA_COUNT_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 10; - attribute C_WR_DEPTH : integer; - attribute C_WR_DEPTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1024; - attribute C_WR_DEPTH_AXIS : integer; - attribute C_WR_DEPTH_AXIS of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1024; - attribute C_WR_DEPTH_RACH : integer; - attribute C_WR_DEPTH_RACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 16; - attribute C_WR_DEPTH_RDCH : integer; - attribute C_WR_DEPTH_RDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1024; - attribute C_WR_DEPTH_WACH : integer; - attribute C_WR_DEPTH_WACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 16; - attribute C_WR_DEPTH_WDCH : integer; - attribute C_WR_DEPTH_WDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1024; - attribute C_WR_DEPTH_WRCH : integer; - attribute C_WR_DEPTH_WRCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 16; - attribute C_WR_FREQ : integer; - attribute C_WR_FREQ of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute C_WR_PNTR_WIDTH : integer; - attribute C_WR_PNTR_WIDTH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 10; - attribute C_WR_PNTR_WIDTH_AXIS : integer; - attribute C_WR_PNTR_WIDTH_AXIS of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 10; - attribute C_WR_PNTR_WIDTH_RACH : integer; - attribute C_WR_PNTR_WIDTH_RACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 4; - attribute C_WR_PNTR_WIDTH_RDCH : integer; - attribute C_WR_PNTR_WIDTH_RDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 10; - attribute C_WR_PNTR_WIDTH_WACH : integer; - attribute C_WR_PNTR_WIDTH_WACH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 4; - attribute C_WR_PNTR_WIDTH_WDCH : integer; - attribute C_WR_PNTR_WIDTH_WDCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 10; - attribute C_WR_PNTR_WIDTH_WRCH : integer; - attribute C_WR_PNTR_WIDTH_WRCH of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 4; - attribute C_WR_RESPONSE_LATENCY : integer; - attribute C_WR_RESPONSE_LATENCY of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is 1; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of fifo_AntCtrl_fifo_generator_v13_2_4 : entity is "fifo_generator_v13_2_4"; -end fifo_AntCtrl_fifo_generator_v13_2_4; - -architecture STRUCTURE of fifo_AntCtrl_fifo_generator_v13_2_4 is - signal \\ : STD_LOGIC; - signal \\ : STD_LOGIC; -begin - almost_empty <= \\; - almost_full <= \\; - axi_ar_data_count(4) <= \\; - axi_ar_data_count(3) <= \\; - axi_ar_data_count(2) <= \\; - axi_ar_data_count(1) <= \\; - axi_ar_data_count(0) <= \\; - axi_ar_dbiterr <= \\; - axi_ar_overflow <= \\; - axi_ar_prog_empty <= \\; - axi_ar_prog_full <= \\; - axi_ar_rd_data_count(4) <= \\; - axi_ar_rd_data_count(3) <= \\; - axi_ar_rd_data_count(2) <= \\; - axi_ar_rd_data_count(1) <= \\; - axi_ar_rd_data_count(0) <= \\; - axi_ar_sbiterr <= \\; - axi_ar_underflow <= \\; - axi_ar_wr_data_count(4) <= \\; - axi_ar_wr_data_count(3) <= \\; - axi_ar_wr_data_count(2) <= \\; - axi_ar_wr_data_count(1) <= \\; - axi_ar_wr_data_count(0) <= \\; - axi_aw_data_count(4) <= \\; - axi_aw_data_count(3) <= \\; - axi_aw_data_count(2) <= \\; - axi_aw_data_count(1) <= \\; - axi_aw_data_count(0) <= \\; - axi_aw_dbiterr <= \\; - axi_aw_overflow <= \\; - axi_aw_prog_empty <= \\; - axi_aw_prog_full <= \\; - axi_aw_rd_data_count(4) <= \\; - axi_aw_rd_data_count(3) <= \\; - axi_aw_rd_data_count(2) <= \\; - axi_aw_rd_data_count(1) <= \\; - axi_aw_rd_data_count(0) <= \\; - axi_aw_sbiterr <= \\; - axi_aw_underflow <= \\; - axi_aw_wr_data_count(4) <= \\; - axi_aw_wr_data_count(3) <= \\; - axi_aw_wr_data_count(2) <= \\; - axi_aw_wr_data_count(1) <= \\; - axi_aw_wr_data_count(0) <= \\; - axi_b_data_count(4) <= \\; - axi_b_data_count(3) <= \\; - axi_b_data_count(2) <= \\; - axi_b_data_count(1) <= \\; - axi_b_data_count(0) <= \\; - axi_b_dbiterr <= \\; - axi_b_overflow <= \\; - axi_b_prog_empty <= \\; - axi_b_prog_full <= \\; - axi_b_rd_data_count(4) <= \\; - axi_b_rd_data_count(3) <= \\; - axi_b_rd_data_count(2) <= \\; - axi_b_rd_data_count(1) <= \\; - axi_b_rd_data_count(0) <= \\; - axi_b_sbiterr <= \\; - axi_b_underflow <= \\; - axi_b_wr_data_count(4) <= \\; - axi_b_wr_data_count(3) <= \\; - axi_b_wr_data_count(2) <= \\; - axi_b_wr_data_count(1) <= \\; - axi_b_wr_data_count(0) <= \\; - axi_r_data_count(10) <= \\; - axi_r_data_count(9) <= \\; - axi_r_data_count(8) <= \\; - axi_r_data_count(7) <= \\; - axi_r_data_count(6) <= \\; - axi_r_data_count(5) <= \\; - axi_r_data_count(4) <= \\; - axi_r_data_count(3) <= \\; - axi_r_data_count(2) <= \\; - axi_r_data_count(1) <= \\; - axi_r_data_count(0) <= \\; - axi_r_dbiterr <= \\; - axi_r_overflow <= \\; - axi_r_prog_empty <= \\; - axi_r_prog_full <= \\; - axi_r_rd_data_count(10) <= \\; - axi_r_rd_data_count(9) <= \\; - axi_r_rd_data_count(8) <= \\; - axi_r_rd_data_count(7) <= \\; - axi_r_rd_data_count(6) <= \\; - axi_r_rd_data_count(5) <= \\; - axi_r_rd_data_count(4) <= \\; - axi_r_rd_data_count(3) <= \\; - axi_r_rd_data_count(2) <= \\; - axi_r_rd_data_count(1) <= \\; - axi_r_rd_data_count(0) <= \\; - axi_r_sbiterr <= \\; - axi_r_underflow <= \\; - axi_r_wr_data_count(10) <= \\; - axi_r_wr_data_count(9) <= \\; - axi_r_wr_data_count(8) <= \\; - axi_r_wr_data_count(7) <= \\; - axi_r_wr_data_count(6) <= \\; - axi_r_wr_data_count(5) <= \\; - axi_r_wr_data_count(4) <= \\; - axi_r_wr_data_count(3) <= \\; - axi_r_wr_data_count(2) <= \\; - axi_r_wr_data_count(1) <= \\; - axi_r_wr_data_count(0) <= \\; - axi_w_data_count(10) <= \\; - axi_w_data_count(9) <= \\; - axi_w_data_count(8) <= \\; - axi_w_data_count(7) <= \\; - axi_w_data_count(6) <= \\; - axi_w_data_count(5) <= \\; - axi_w_data_count(4) <= \\; - axi_w_data_count(3) <= \\; - axi_w_data_count(2) <= \\; - axi_w_data_count(1) <= \\; - axi_w_data_count(0) <= \\; - axi_w_dbiterr <= \\; - axi_w_overflow <= \\; - axi_w_prog_empty <= \\; - axi_w_prog_full <= \\; - axi_w_rd_data_count(10) <= \\; - axi_w_rd_data_count(9) <= \\; - axi_w_rd_data_count(8) <= \\; - axi_w_rd_data_count(7) <= \\; - axi_w_rd_data_count(6) <= \\; - axi_w_rd_data_count(5) <= \\; - axi_w_rd_data_count(4) <= \\; - axi_w_rd_data_count(3) <= \\; - axi_w_rd_data_count(2) <= \\; - axi_w_rd_data_count(1) <= \\; - axi_w_rd_data_count(0) <= \\; - axi_w_sbiterr <= \\; - axi_w_underflow <= \\; - axi_w_wr_data_count(10) <= \\; - axi_w_wr_data_count(9) <= \\; - axi_w_wr_data_count(8) <= \\; - axi_w_wr_data_count(7) <= \\; - axi_w_wr_data_count(6) <= \\; - axi_w_wr_data_count(5) <= \\; - axi_w_wr_data_count(4) <= \\; - axi_w_wr_data_count(3) <= \\; - axi_w_wr_data_count(2) <= \\; - axi_w_wr_data_count(1) <= \\; - axi_w_wr_data_count(0) <= \\; - axis_data_count(10) <= \\; - axis_data_count(9) <= \\; - axis_data_count(8) <= \\; - axis_data_count(7) <= \\; - axis_data_count(6) <= \\; - axis_data_count(5) <= \\; - axis_data_count(4) <= \\; - axis_data_count(3) <= \\; - axis_data_count(2) <= \\; - axis_data_count(1) <= \\; - axis_data_count(0) <= \\; - axis_dbiterr <= \\; - axis_overflow <= \\; - axis_prog_empty <= \\; - axis_prog_full <= \\; - axis_rd_data_count(10) <= \\; - axis_rd_data_count(9) <= \\; - axis_rd_data_count(8) <= \\; - axis_rd_data_count(7) <= \\; - axis_rd_data_count(6) <= \\; - axis_rd_data_count(5) <= \\; - axis_rd_data_count(4) <= \\; - axis_rd_data_count(3) <= \\; - axis_rd_data_count(2) <= \\; - axis_rd_data_count(1) <= \\; - axis_rd_data_count(0) <= \\; - axis_sbiterr <= \\; - axis_underflow <= \\; - axis_wr_data_count(10) <= \\; - axis_wr_data_count(9) <= \\; - axis_wr_data_count(8) <= \\; - axis_wr_data_count(7) <= \\; - axis_wr_data_count(6) <= \\; - axis_wr_data_count(5) <= \\; - axis_wr_data_count(4) <= \\; - axis_wr_data_count(3) <= \\; - axis_wr_data_count(2) <= \\; - axis_wr_data_count(1) <= \\; - axis_wr_data_count(0) <= \\; - data_count(9) <= \\; - data_count(8) <= \\; - data_count(7) <= \\; - data_count(6) <= \\; - data_count(5) <= \\; - data_count(4) <= \\; - data_count(3) <= \\; - data_count(2) <= \\; - data_count(1) <= \\; - data_count(0) <= \\; - dbiterr <= \\; - m_axi_araddr(31) <= \\; - m_axi_araddr(30) <= \\; - m_axi_araddr(29) <= \\; - m_axi_araddr(28) <= \\; - m_axi_araddr(27) <= \\; - m_axi_araddr(26) <= \\; - m_axi_araddr(25) <= \\; - m_axi_araddr(24) <= \\; - m_axi_araddr(23) <= \\; - m_axi_araddr(22) <= \\; - m_axi_araddr(21) <= \\; - m_axi_araddr(20) <= \\; - m_axi_araddr(19) <= \\; - m_axi_araddr(18) <= \\; - m_axi_araddr(17) <= \\; - m_axi_araddr(16) <= \\; - m_axi_araddr(15) <= \\; - m_axi_araddr(14) <= \\; - m_axi_araddr(13) <= \\; - m_axi_araddr(12) <= \\; - m_axi_araddr(11) <= \\; - m_axi_araddr(10) <= \\; - m_axi_araddr(9) <= \\; - m_axi_araddr(8) <= \\; - m_axi_araddr(7) <= \\; - m_axi_araddr(6) <= \\; - m_axi_araddr(5) <= \\; - m_axi_araddr(4) <= \\; - m_axi_araddr(3) <= \\; - m_axi_araddr(2) <= \\; - m_axi_araddr(1) <= \\; - m_axi_araddr(0) <= \\; - m_axi_arburst(1) <= \\; - m_axi_arburst(0) <= \\; - m_axi_arcache(3) <= \\; - m_axi_arcache(2) <= \\; - m_axi_arcache(1) <= \\; - m_axi_arcache(0) <= \\; - m_axi_arid(0) <= \\; - m_axi_arlen(7) <= \\; - m_axi_arlen(6) <= \\; - m_axi_arlen(5) <= \\; - m_axi_arlen(4) <= \\; - m_axi_arlen(3) <= \\; - m_axi_arlen(2) <= \\; - m_axi_arlen(1) <= \\; - m_axi_arlen(0) <= \\; - m_axi_arlock(0) <= \\; - m_axi_arprot(2) <= \\; - m_axi_arprot(1) <= \\; - m_axi_arprot(0) <= \\; - m_axi_arqos(3) <= \\; - m_axi_arqos(2) <= \\; - m_axi_arqos(1) <= \\; - m_axi_arqos(0) <= \\; - m_axi_arregion(3) <= \\; - m_axi_arregion(2) <= \\; - m_axi_arregion(1) <= \\; - m_axi_arregion(0) <= \\; - m_axi_arsize(2) <= \\; - m_axi_arsize(1) <= \\; - m_axi_arsize(0) <= \\; - m_axi_aruser(0) <= \\; - m_axi_arvalid <= \\; - m_axi_awaddr(31) <= \\; - m_axi_awaddr(30) <= \\; - m_axi_awaddr(29) <= \\; - m_axi_awaddr(28) <= \\; - m_axi_awaddr(27) <= \\; - m_axi_awaddr(26) <= \\; - m_axi_awaddr(25) <= \\; - m_axi_awaddr(24) <= \\; - m_axi_awaddr(23) <= \\; - m_axi_awaddr(22) <= \\; - m_axi_awaddr(21) <= \\; - m_axi_awaddr(20) <= \\; - m_axi_awaddr(19) <= \\; - m_axi_awaddr(18) <= \\; - m_axi_awaddr(17) <= \\; - m_axi_awaddr(16) <= \\; - m_axi_awaddr(15) <= \\; - m_axi_awaddr(14) <= \\; - m_axi_awaddr(13) <= \\; - m_axi_awaddr(12) <= \\; - m_axi_awaddr(11) <= \\; - m_axi_awaddr(10) <= \\; - m_axi_awaddr(9) <= \\; - m_axi_awaddr(8) <= \\; - m_axi_awaddr(7) <= \\; - m_axi_awaddr(6) <= \\; - m_axi_awaddr(5) <= \\; - m_axi_awaddr(4) <= \\; - m_axi_awaddr(3) <= \\; - m_axi_awaddr(2) <= \\; - m_axi_awaddr(1) <= \\; - m_axi_awaddr(0) <= \\; - m_axi_awburst(1) <= \\; - m_axi_awburst(0) <= \\; - m_axi_awcache(3) <= \\; - m_axi_awcache(2) <= \\; - m_axi_awcache(1) <= \\; - m_axi_awcache(0) <= \\; - m_axi_awid(0) <= \\; - m_axi_awlen(7) <= \\; - m_axi_awlen(6) <= \\; - m_axi_awlen(5) <= \\; - m_axi_awlen(4) <= \\; - m_axi_awlen(3) <= \\; - m_axi_awlen(2) <= \\; - m_axi_awlen(1) <= \\; - m_axi_awlen(0) <= \\; - m_axi_awlock(0) <= \\; - m_axi_awprot(2) <= \\; - m_axi_awprot(1) <= \\; - m_axi_awprot(0) <= \\; - m_axi_awqos(3) <= \\; - m_axi_awqos(2) <= \\; - m_axi_awqos(1) <= \\; - m_axi_awqos(0) <= \\; - m_axi_awregion(3) <= \\; - m_axi_awregion(2) <= \\; - m_axi_awregion(1) <= \\; - m_axi_awregion(0) <= \\; - m_axi_awsize(2) <= \\; - m_axi_awsize(1) <= \\; - m_axi_awsize(0) <= \\; - m_axi_awuser(0) <= \\; - m_axi_awvalid <= \\; - m_axi_bready <= \\; - m_axi_rready <= \\; - m_axi_wdata(63) <= \\; - m_axi_wdata(62) <= \\; - m_axi_wdata(61) <= \\; - m_axi_wdata(60) <= \\; - m_axi_wdata(59) <= \\; - m_axi_wdata(58) <= \\; - m_axi_wdata(57) <= \\; - m_axi_wdata(56) <= \\; - m_axi_wdata(55) <= \\; - m_axi_wdata(54) <= \\; - m_axi_wdata(53) <= \\; - m_axi_wdata(52) <= \\; - m_axi_wdata(51) <= \\; - m_axi_wdata(50) <= \\; - m_axi_wdata(49) <= \\; - m_axi_wdata(48) <= \\; - m_axi_wdata(47) <= \\; - m_axi_wdata(46) <= \\; - m_axi_wdata(45) <= \\; - m_axi_wdata(44) <= \\; - m_axi_wdata(43) <= \\; - m_axi_wdata(42) <= \\; - m_axi_wdata(41) <= \\; - m_axi_wdata(40) <= \\; - m_axi_wdata(39) <= \\; - m_axi_wdata(38) <= \\; - m_axi_wdata(37) <= \\; - m_axi_wdata(36) <= \\; - m_axi_wdata(35) <= \\; - m_axi_wdata(34) <= \\; - m_axi_wdata(33) <= \\; - m_axi_wdata(32) <= \\; - m_axi_wdata(31) <= \\; - m_axi_wdata(30) <= \\; - m_axi_wdata(29) <= \\; - m_axi_wdata(28) <= \\; - m_axi_wdata(27) <= \\; - m_axi_wdata(26) <= \\; - m_axi_wdata(25) <= \\; - m_axi_wdata(24) <= \\; - m_axi_wdata(23) <= \\; - m_axi_wdata(22) <= \\; - m_axi_wdata(21) <= \\; - m_axi_wdata(20) <= \\; - m_axi_wdata(19) <= \\; - m_axi_wdata(18) <= \\; - m_axi_wdata(17) <= \\; - m_axi_wdata(16) <= \\; - m_axi_wdata(15) <= \\; - m_axi_wdata(14) <= \\; - m_axi_wdata(13) <= \\; - m_axi_wdata(12) <= \\; - m_axi_wdata(11) <= \\; - m_axi_wdata(10) <= \\; - m_axi_wdata(9) <= \\; - m_axi_wdata(8) <= \\; - m_axi_wdata(7) <= \\; - m_axi_wdata(6) <= \\; - m_axi_wdata(5) <= \\; - m_axi_wdata(4) <= \\; - m_axi_wdata(3) <= \\; - m_axi_wdata(2) <= \\; - m_axi_wdata(1) <= \\; - m_axi_wdata(0) <= \\; - m_axi_wid(0) <= \\; - m_axi_wlast <= \\; - m_axi_wstrb(7) <= \\; - m_axi_wstrb(6) <= \\; - m_axi_wstrb(5) <= \\; - m_axi_wstrb(4) <= \\; - m_axi_wstrb(3) <= \\; - m_axi_wstrb(2) <= \\; - m_axi_wstrb(1) <= \\; - m_axi_wstrb(0) <= \\; - m_axi_wuser(0) <= \\; - m_axi_wvalid <= \\; - m_axis_tdata(7) <= \\; - m_axis_tdata(6) <= \\; - m_axis_tdata(5) <= \\; - m_axis_tdata(4) <= \\; - m_axis_tdata(3) <= \\; - m_axis_tdata(2) <= \\; - m_axis_tdata(1) <= \\; - m_axis_tdata(0) <= \\; - m_axis_tdest(0) <= \\; - m_axis_tid(0) <= \\; - m_axis_tkeep(0) <= \\; - m_axis_tlast <= \\; - m_axis_tstrb(0) <= \\; - m_axis_tuser(3) <= \\; - m_axis_tuser(2) <= \\; - m_axis_tuser(1) <= \\; - m_axis_tuser(0) <= \\; - m_axis_tvalid <= \\; - overflow <= \\; - prog_empty <= \\; - prog_full <= \\; - rd_data_count(9) <= \\; - rd_data_count(8) <= \\; - rd_data_count(7) <= \\; - rd_data_count(6) <= \\; - rd_data_count(5) <= \\; - rd_data_count(4) <= \\; - rd_data_count(3) <= \\; - rd_data_count(2) <= \\; - rd_data_count(1) <= \\; - rd_data_count(0) <= \\; - s_axi_arready <= \\; - s_axi_awready <= \\; - s_axi_bid(0) <= \\; - s_axi_bresp(1) <= \\; - s_axi_bresp(0) <= \\; - s_axi_buser(0) <= \\; - s_axi_bvalid <= \\; - s_axi_rdata(63) <= \\; - s_axi_rdata(62) <= \\; - s_axi_rdata(61) <= \\; - s_axi_rdata(60) <= \\; - s_axi_rdata(59) <= \\; - s_axi_rdata(58) <= \\; - s_axi_rdata(57) <= \\; - s_axi_rdata(56) <= \\; - s_axi_rdata(55) <= \\; - s_axi_rdata(54) <= \\; - s_axi_rdata(53) <= \\; - s_axi_rdata(52) <= \\; - s_axi_rdata(51) <= \\; - s_axi_rdata(50) <= \\; - s_axi_rdata(49) <= \\; - s_axi_rdata(48) <= \\; - s_axi_rdata(47) <= \\; - s_axi_rdata(46) <= \\; - s_axi_rdata(45) <= \\; - s_axi_rdata(44) <= \\; - s_axi_rdata(43) <= \\; - s_axi_rdata(42) <= \\; - s_axi_rdata(41) <= \\; - s_axi_rdata(40) <= \\; - s_axi_rdata(39) <= \\; - s_axi_rdata(38) <= \\; - s_axi_rdata(37) <= \\; - s_axi_rdata(36) <= \\; - s_axi_rdata(35) <= \\; - s_axi_rdata(34) <= \\; - s_axi_rdata(33) <= \\; - s_axi_rdata(32) <= \\; - s_axi_rdata(31) <= \\; - s_axi_rdata(30) <= \\; - s_axi_rdata(29) <= \\; - s_axi_rdata(28) <= \\; - s_axi_rdata(27) <= \\; - s_axi_rdata(26) <= \\; - s_axi_rdata(25) <= \\; - s_axi_rdata(24) <= \\; - s_axi_rdata(23) <= \\; - s_axi_rdata(22) <= \\; - s_axi_rdata(21) <= \\; - s_axi_rdata(20) <= \\; - s_axi_rdata(19) <= \\; - s_axi_rdata(18) <= \\; - s_axi_rdata(17) <= \\; - s_axi_rdata(16) <= \\; - s_axi_rdata(15) <= \\; - s_axi_rdata(14) <= \\; - s_axi_rdata(13) <= \\; - s_axi_rdata(12) <= \\; - s_axi_rdata(11) <= \\; - s_axi_rdata(10) <= \\; - s_axi_rdata(9) <= \\; - s_axi_rdata(8) <= \\; - s_axi_rdata(7) <= \\; - s_axi_rdata(6) <= \\; - s_axi_rdata(5) <= \\; - s_axi_rdata(4) <= \\; - s_axi_rdata(3) <= \\; - s_axi_rdata(2) <= \\; - s_axi_rdata(1) <= \\; - s_axi_rdata(0) <= \\; - s_axi_rid(0) <= \\; - s_axi_rlast <= \\; - s_axi_rresp(1) <= \\; - s_axi_rresp(0) <= \\; - s_axi_ruser(0) <= \\; - s_axi_rvalid <= \\; - s_axi_wready <= \\; - s_axis_tready <= \\; - sbiterr <= \\; - underflow <= \\; - valid <= \\; - wr_ack <= \\; - wr_data_count(9) <= \\; - wr_data_count(8) <= \\; - wr_data_count(7) <= \\; - wr_data_count(6) <= \\; - wr_data_count(5) <= \\; - wr_data_count(4) <= \\; - wr_data_count(3) <= \\; - wr_data_count(2) <= \\; - wr_data_count(1) <= \\; - wr_data_count(0) <= \\; -GND: unisim.vcomponents.GND - port map ( - G => \\ - ); -VCC: unisim.vcomponents.VCC - port map ( - P => \\ - ); -inst_fifo_gen: entity work.fifo_AntCtrl_fifo_generator_v13_2_4_synth - port map ( - AR(0) => rd_rst_busy, - din(3 downto 0) => din(3 downto 0), - dout(3 downto 0) => dout(3 downto 0), - empty => empty, - full => full, - rd_clk => rd_clk, - rd_en => rd_en, - rst => rst, - wr_clk => wr_clk, - wr_en => wr_en, - wr_rst_busy => wr_rst_busy - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity fifo_AntCtrl is - port ( - rst : in STD_LOGIC; - wr_clk : in STD_LOGIC; - rd_clk : in STD_LOGIC; - din : in STD_LOGIC_VECTOR ( 3 downto 0 ); - wr_en : in STD_LOGIC; - rd_en : in STD_LOGIC; - dout : out STD_LOGIC_VECTOR ( 3 downto 0 ); - full : out STD_LOGIC; - empty : out STD_LOGIC - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of fifo_AntCtrl : entity is true; - attribute CHECK_LICENSE_TYPE : string; - attribute CHECK_LICENSE_TYPE of fifo_AntCtrl : entity is "fifo_AntCtrl,fifo_generator_v13_2_4,{}"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of fifo_AntCtrl : entity is "yes"; - attribute x_core_info : string; - attribute x_core_info of fifo_AntCtrl : entity is "fifo_generator_v13_2_4,Vivado 2019.1.3"; -end fifo_AntCtrl; - -architecture STRUCTURE of fifo_AntCtrl is - signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC; - signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC; - signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC; - signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC; - signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC; - signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC; - signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC; - signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC; - signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC; - signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC; - signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC; - signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC; - signal NLW_U0_valid_UNCONNECTED : STD_LOGIC; - signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC; - signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC; - signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); - signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); - signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); - signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); - signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); - signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); - signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); - signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); - signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); - signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); - signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); - signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); - signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); - signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); - attribute C_ADD_NGC_CONSTRAINT : integer; - attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0; - attribute C_APPLICATION_TYPE_AXIS : integer; - attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0; - attribute C_APPLICATION_TYPE_RACH : integer; - attribute C_APPLICATION_TYPE_RACH of U0 : label is 0; - attribute C_APPLICATION_TYPE_RDCH : integer; - attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0; - attribute C_APPLICATION_TYPE_WACH : integer; - attribute C_APPLICATION_TYPE_WACH of U0 : label is 0; - attribute C_APPLICATION_TYPE_WDCH : integer; - attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0; - attribute C_APPLICATION_TYPE_WRCH : integer; - attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0; - attribute C_AXIS_TDATA_WIDTH : integer; - attribute C_AXIS_TDATA_WIDTH of U0 : label is 8; - attribute C_AXIS_TDEST_WIDTH : integer; - attribute C_AXIS_TDEST_WIDTH of U0 : label is 1; - attribute C_AXIS_TID_WIDTH : integer; - attribute C_AXIS_TID_WIDTH of U0 : label is 1; - attribute C_AXIS_TKEEP_WIDTH : integer; - attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1; - attribute C_AXIS_TSTRB_WIDTH : integer; - attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1; - attribute C_AXIS_TUSER_WIDTH : integer; - attribute C_AXIS_TUSER_WIDTH of U0 : label is 4; - attribute C_AXIS_TYPE : integer; - attribute C_AXIS_TYPE of U0 : label is 0; - attribute C_AXI_ADDR_WIDTH : integer; - attribute C_AXI_ADDR_WIDTH of U0 : label is 32; - attribute C_AXI_ARUSER_WIDTH : integer; - attribute C_AXI_ARUSER_WIDTH of U0 : label is 1; - attribute C_AXI_AWUSER_WIDTH : integer; - attribute C_AXI_AWUSER_WIDTH of U0 : label is 1; - attribute C_AXI_BUSER_WIDTH : integer; - attribute C_AXI_BUSER_WIDTH of U0 : label is 1; - attribute C_AXI_DATA_WIDTH : integer; - attribute C_AXI_DATA_WIDTH of U0 : label is 64; - attribute C_AXI_ID_WIDTH : integer; - attribute C_AXI_ID_WIDTH of U0 : label is 1; - attribute C_AXI_LEN_WIDTH : integer; - attribute C_AXI_LEN_WIDTH of U0 : label is 8; - attribute C_AXI_LOCK_WIDTH : integer; - attribute C_AXI_LOCK_WIDTH of U0 : label is 1; - attribute C_AXI_RUSER_WIDTH : integer; - attribute C_AXI_RUSER_WIDTH of U0 : label is 1; - attribute C_AXI_TYPE : integer; - attribute C_AXI_TYPE of U0 : label is 1; - attribute C_AXI_WUSER_WIDTH : integer; - attribute C_AXI_WUSER_WIDTH of U0 : label is 1; - attribute C_COMMON_CLOCK : integer; - attribute C_COMMON_CLOCK of U0 : label is 0; - attribute C_COUNT_TYPE : integer; - attribute C_COUNT_TYPE of U0 : label is 0; - attribute C_DATA_COUNT_WIDTH : integer; - attribute C_DATA_COUNT_WIDTH of U0 : label is 10; - attribute C_DEFAULT_VALUE : string; - attribute C_DEFAULT_VALUE of U0 : label is "BlankString"; - attribute C_DIN_WIDTH : integer; - attribute C_DIN_WIDTH of U0 : label is 4; - attribute C_DIN_WIDTH_AXIS : integer; - attribute C_DIN_WIDTH_AXIS of U0 : label is 1; - attribute C_DIN_WIDTH_RACH : integer; - attribute C_DIN_WIDTH_RACH of U0 : label is 32; - attribute C_DIN_WIDTH_RDCH : integer; - attribute C_DIN_WIDTH_RDCH of U0 : label is 64; - attribute C_DIN_WIDTH_WACH : integer; - attribute C_DIN_WIDTH_WACH of U0 : label is 1; - attribute C_DIN_WIDTH_WDCH : integer; - attribute C_DIN_WIDTH_WDCH of U0 : label is 64; - attribute C_DIN_WIDTH_WRCH : integer; - attribute C_DIN_WIDTH_WRCH of U0 : label is 2; - attribute C_DOUT_RST_VAL : string; - attribute C_DOUT_RST_VAL of U0 : label is "0"; - attribute C_DOUT_WIDTH : integer; - attribute C_DOUT_WIDTH of U0 : label is 4; - attribute C_ENABLE_RLOCS : integer; - attribute C_ENABLE_RLOCS of U0 : label is 0; - attribute C_ENABLE_RST_SYNC : integer; - attribute C_ENABLE_RST_SYNC of U0 : label is 1; - attribute C_EN_SAFETY_CKT : integer; - attribute C_EN_SAFETY_CKT of U0 : label is 0; - attribute C_ERROR_INJECTION_TYPE : integer; - attribute C_ERROR_INJECTION_TYPE of U0 : label is 0; - attribute C_ERROR_INJECTION_TYPE_AXIS : integer; - attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0; - attribute C_ERROR_INJECTION_TYPE_RACH : integer; - attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0; - attribute C_ERROR_INJECTION_TYPE_RDCH : integer; - attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0; - attribute C_ERROR_INJECTION_TYPE_WACH : integer; - attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0; - attribute C_ERROR_INJECTION_TYPE_WDCH : integer; - attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0; - attribute C_ERROR_INJECTION_TYPE_WRCH : integer; - attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0; - attribute C_FAMILY : string; - attribute C_FAMILY of U0 : label is "kintex7"; - attribute C_FULL_FLAGS_RST_VAL : integer; - attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1; - attribute C_HAS_ALMOST_EMPTY : integer; - attribute C_HAS_ALMOST_EMPTY of U0 : label is 0; - attribute C_HAS_ALMOST_FULL : integer; - attribute C_HAS_ALMOST_FULL of U0 : label is 0; - attribute C_HAS_AXIS_TDATA : integer; - attribute C_HAS_AXIS_TDATA of U0 : label is 1; - attribute C_HAS_AXIS_TDEST : integer; - attribute C_HAS_AXIS_TDEST of U0 : label is 0; - attribute C_HAS_AXIS_TID : integer; - attribute C_HAS_AXIS_TID of U0 : label is 0; - attribute C_HAS_AXIS_TKEEP : integer; - attribute C_HAS_AXIS_TKEEP of U0 : label is 0; - attribute C_HAS_AXIS_TLAST : integer; - attribute C_HAS_AXIS_TLAST of U0 : label is 0; - attribute C_HAS_AXIS_TREADY : integer; - attribute C_HAS_AXIS_TREADY of U0 : label is 1; - attribute C_HAS_AXIS_TSTRB : integer; - attribute C_HAS_AXIS_TSTRB of U0 : label is 0; - attribute C_HAS_AXIS_TUSER : integer; - attribute C_HAS_AXIS_TUSER of U0 : label is 1; - attribute C_HAS_AXI_ARUSER : integer; - attribute C_HAS_AXI_ARUSER of U0 : label is 0; - attribute C_HAS_AXI_AWUSER : integer; - attribute C_HAS_AXI_AWUSER of U0 : label is 0; - attribute C_HAS_AXI_BUSER : integer; - attribute C_HAS_AXI_BUSER of U0 : label is 0; - attribute C_HAS_AXI_ID : integer; - attribute C_HAS_AXI_ID of U0 : label is 0; - attribute C_HAS_AXI_RD_CHANNEL : integer; - attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1; - attribute C_HAS_AXI_RUSER : integer; - attribute C_HAS_AXI_RUSER of U0 : label is 0; - attribute C_HAS_AXI_WR_CHANNEL : integer; - attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1; - attribute C_HAS_AXI_WUSER : integer; - attribute C_HAS_AXI_WUSER of U0 : label is 0; - attribute C_HAS_BACKUP : integer; - attribute C_HAS_BACKUP of U0 : label is 0; - attribute C_HAS_DATA_COUNT : integer; - attribute C_HAS_DATA_COUNT of U0 : label is 0; - attribute C_HAS_DATA_COUNTS_AXIS : integer; - attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0; - attribute C_HAS_DATA_COUNTS_RACH : integer; - attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0; - attribute C_HAS_DATA_COUNTS_RDCH : integer; - attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0; - attribute C_HAS_DATA_COUNTS_WACH : integer; - attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0; - attribute C_HAS_DATA_COUNTS_WDCH : integer; - attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0; - attribute C_HAS_DATA_COUNTS_WRCH : integer; - attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0; - attribute C_HAS_INT_CLK : integer; - attribute C_HAS_INT_CLK of U0 : label is 0; - attribute C_HAS_MASTER_CE : integer; - attribute C_HAS_MASTER_CE of U0 : label is 0; - attribute C_HAS_MEMINIT_FILE : integer; - attribute C_HAS_MEMINIT_FILE of U0 : label is 0; - attribute C_HAS_OVERFLOW : integer; - attribute C_HAS_OVERFLOW of U0 : label is 0; - attribute C_HAS_PROG_FLAGS_AXIS : integer; - attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0; - attribute C_HAS_PROG_FLAGS_RACH : integer; - attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0; - attribute C_HAS_PROG_FLAGS_RDCH : integer; - attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0; - attribute C_HAS_PROG_FLAGS_WACH : integer; - attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0; - attribute C_HAS_PROG_FLAGS_WDCH : integer; - attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0; - attribute C_HAS_PROG_FLAGS_WRCH : integer; - attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0; - attribute C_HAS_RD_DATA_COUNT : integer; - attribute C_HAS_RD_DATA_COUNT of U0 : label is 0; - attribute C_HAS_RD_RST : integer; - attribute C_HAS_RD_RST of U0 : label is 0; - attribute C_HAS_RST : integer; - attribute C_HAS_RST of U0 : label is 1; - attribute C_HAS_SLAVE_CE : integer; - attribute C_HAS_SLAVE_CE of U0 : label is 0; - attribute C_HAS_SRST : integer; - attribute C_HAS_SRST of U0 : label is 0; - attribute C_HAS_UNDERFLOW : integer; - attribute C_HAS_UNDERFLOW of U0 : label is 0; - attribute C_HAS_VALID : integer; - attribute C_HAS_VALID of U0 : label is 0; - attribute C_HAS_WR_ACK : integer; - attribute C_HAS_WR_ACK of U0 : label is 0; - attribute C_HAS_WR_DATA_COUNT : integer; - attribute C_HAS_WR_DATA_COUNT of U0 : label is 0; - attribute C_HAS_WR_RST : integer; - attribute C_HAS_WR_RST of U0 : label is 0; - attribute C_IMPLEMENTATION_TYPE : integer; - attribute C_IMPLEMENTATION_TYPE of U0 : label is 2; - attribute C_IMPLEMENTATION_TYPE_AXIS : integer; - attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1; - attribute C_IMPLEMENTATION_TYPE_RACH : integer; - attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1; - attribute C_IMPLEMENTATION_TYPE_RDCH : integer; - attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1; - attribute C_IMPLEMENTATION_TYPE_WACH : integer; - attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1; - attribute C_IMPLEMENTATION_TYPE_WDCH : integer; - attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1; - attribute C_IMPLEMENTATION_TYPE_WRCH : integer; - attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1; - attribute C_INIT_WR_PNTR_VAL : integer; - attribute C_INIT_WR_PNTR_VAL of U0 : label is 0; - attribute C_INTERFACE_TYPE : integer; - attribute C_INTERFACE_TYPE of U0 : label is 0; - attribute C_MEMORY_TYPE : integer; - attribute C_MEMORY_TYPE of U0 : label is 2; - attribute C_MIF_FILE_NAME : string; - attribute C_MIF_FILE_NAME of U0 : label is "BlankString"; - attribute C_MSGON_VAL : integer; - attribute C_MSGON_VAL of U0 : label is 1; - attribute C_OPTIMIZATION_MODE : integer; - attribute C_OPTIMIZATION_MODE of U0 : label is 0; - attribute C_OVERFLOW_LOW : integer; - attribute C_OVERFLOW_LOW of U0 : label is 0; - attribute C_POWER_SAVING_MODE : integer; - attribute C_POWER_SAVING_MODE of U0 : label is 0; - attribute C_PRELOAD_LATENCY : integer; - attribute C_PRELOAD_LATENCY of U0 : label is 1; - attribute C_PRELOAD_REGS : integer; - attribute C_PRELOAD_REGS of U0 : label is 0; - attribute C_PRIM_FIFO_TYPE : string; - attribute C_PRIM_FIFO_TYPE of U0 : label is "1kx18"; - attribute C_PRIM_FIFO_TYPE_AXIS : string; - attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18"; - attribute C_PRIM_FIFO_TYPE_RACH : string; - attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36"; - attribute C_PRIM_FIFO_TYPE_RDCH : string; - attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36"; - attribute C_PRIM_FIFO_TYPE_WACH : string; - attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36"; - attribute C_PRIM_FIFO_TYPE_WDCH : string; - attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36"; - attribute C_PRIM_FIFO_TYPE_WRCH : string; - attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36"; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022; - attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer; - attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3; - attribute C_PROG_EMPTY_TYPE : integer; - attribute C_PROG_EMPTY_TYPE of U0 : label is 0; - attribute C_PROG_EMPTY_TYPE_AXIS : integer; - attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0; - attribute C_PROG_EMPTY_TYPE_RACH : integer; - attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0; - attribute C_PROG_EMPTY_TYPE_RDCH : integer; - attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0; - attribute C_PROG_EMPTY_TYPE_WACH : integer; - attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0; - attribute C_PROG_EMPTY_TYPE_WDCH : integer; - attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0; - attribute C_PROG_EMPTY_TYPE_WRCH : integer; - attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0; - attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 1021; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023; - attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer; - attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 1020; - attribute C_PROG_FULL_TYPE : integer; - attribute C_PROG_FULL_TYPE of U0 : label is 0; - attribute C_PROG_FULL_TYPE_AXIS : integer; - attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0; - attribute C_PROG_FULL_TYPE_RACH : integer; - attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0; - attribute C_PROG_FULL_TYPE_RDCH : integer; - attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0; - attribute C_PROG_FULL_TYPE_WACH : integer; - attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0; - attribute C_PROG_FULL_TYPE_WDCH : integer; - attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0; - attribute C_PROG_FULL_TYPE_WRCH : integer; - attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0; - attribute C_RACH_TYPE : integer; - attribute C_RACH_TYPE of U0 : label is 0; - attribute C_RDCH_TYPE : integer; - attribute C_RDCH_TYPE of U0 : label is 0; - attribute C_RD_DATA_COUNT_WIDTH : integer; - attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 10; - attribute C_RD_DEPTH : integer; - attribute C_RD_DEPTH of U0 : label is 1024; - attribute C_RD_FREQ : integer; - attribute C_RD_FREQ of U0 : label is 1; - attribute C_RD_PNTR_WIDTH : integer; - attribute C_RD_PNTR_WIDTH of U0 : label is 10; - attribute C_REG_SLICE_MODE_AXIS : integer; - attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0; - attribute C_REG_SLICE_MODE_RACH : integer; - attribute C_REG_SLICE_MODE_RACH of U0 : label is 0; - attribute C_REG_SLICE_MODE_RDCH : integer; - attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0; - attribute C_REG_SLICE_MODE_WACH : integer; - attribute C_REG_SLICE_MODE_WACH of U0 : label is 0; - attribute C_REG_SLICE_MODE_WDCH : integer; - attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0; - attribute C_REG_SLICE_MODE_WRCH : integer; - attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0; - attribute C_SELECT_XPM : integer; - attribute C_SELECT_XPM of U0 : label is 0; - attribute C_SYNCHRONIZER_STAGE : integer; - attribute C_SYNCHRONIZER_STAGE of U0 : label is 2; - attribute C_UNDERFLOW_LOW : integer; - attribute C_UNDERFLOW_LOW of U0 : label is 0; - attribute C_USE_COMMON_OVERFLOW : integer; - attribute C_USE_COMMON_OVERFLOW of U0 : label is 0; - attribute C_USE_COMMON_UNDERFLOW : integer; - attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0; - attribute C_USE_DEFAULT_SETTINGS : integer; - attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0; - attribute C_USE_DOUT_RST : integer; - attribute C_USE_DOUT_RST of U0 : label is 1; - attribute C_USE_ECC : integer; - attribute C_USE_ECC of U0 : label is 0; - attribute C_USE_ECC_AXIS : integer; - attribute C_USE_ECC_AXIS of U0 : label is 0; - attribute C_USE_ECC_RACH : integer; - attribute C_USE_ECC_RACH of U0 : label is 0; - attribute C_USE_ECC_RDCH : integer; - attribute C_USE_ECC_RDCH of U0 : label is 0; - attribute C_USE_ECC_WACH : integer; - attribute C_USE_ECC_WACH of U0 : label is 0; - attribute C_USE_ECC_WDCH : integer; - attribute C_USE_ECC_WDCH of U0 : label is 0; - attribute C_USE_ECC_WRCH : integer; - attribute C_USE_ECC_WRCH of U0 : label is 0; - attribute C_USE_EMBEDDED_REG : integer; - attribute C_USE_EMBEDDED_REG of U0 : label is 0; - attribute C_USE_FIFO16_FLAGS : integer; - attribute C_USE_FIFO16_FLAGS of U0 : label is 0; - attribute C_USE_FWFT_DATA_COUNT : integer; - attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0; - attribute C_USE_PIPELINE_REG : integer; - attribute C_USE_PIPELINE_REG of U0 : label is 0; - attribute C_VALID_LOW : integer; - attribute C_VALID_LOW of U0 : label is 0; - attribute C_WACH_TYPE : integer; - attribute C_WACH_TYPE of U0 : label is 0; - attribute C_WDCH_TYPE : integer; - attribute C_WDCH_TYPE of U0 : label is 0; - attribute C_WRCH_TYPE : integer; - attribute C_WRCH_TYPE of U0 : label is 0; - attribute C_WR_ACK_LOW : integer; - attribute C_WR_ACK_LOW of U0 : label is 0; - attribute C_WR_DATA_COUNT_WIDTH : integer; - attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 10; - attribute C_WR_DEPTH : integer; - attribute C_WR_DEPTH of U0 : label is 1024; - attribute C_WR_DEPTH_AXIS : integer; - attribute C_WR_DEPTH_AXIS of U0 : label is 1024; - attribute C_WR_DEPTH_RACH : integer; - attribute C_WR_DEPTH_RACH of U0 : label is 16; - attribute C_WR_DEPTH_RDCH : integer; - attribute C_WR_DEPTH_RDCH of U0 : label is 1024; - attribute C_WR_DEPTH_WACH : integer; - attribute C_WR_DEPTH_WACH of U0 : label is 16; - attribute C_WR_DEPTH_WDCH : integer; - attribute C_WR_DEPTH_WDCH of U0 : label is 1024; - attribute C_WR_DEPTH_WRCH : integer; - attribute C_WR_DEPTH_WRCH of U0 : label is 16; - attribute C_WR_FREQ : integer; - attribute C_WR_FREQ of U0 : label is 1; - attribute C_WR_PNTR_WIDTH : integer; - attribute C_WR_PNTR_WIDTH of U0 : label is 10; - attribute C_WR_PNTR_WIDTH_AXIS : integer; - attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10; - attribute C_WR_PNTR_WIDTH_RACH : integer; - attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4; - attribute C_WR_PNTR_WIDTH_RDCH : integer; - attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10; - attribute C_WR_PNTR_WIDTH_WACH : integer; - attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4; - attribute C_WR_PNTR_WIDTH_WDCH : integer; - attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10; - attribute C_WR_PNTR_WIDTH_WRCH : integer; - attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4; - attribute C_WR_RESPONSE_LATENCY : integer; - attribute C_WR_RESPONSE_LATENCY of U0 : label is 1; - attribute x_interface_info : string; - attribute x_interface_info of empty : signal is "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; - attribute x_interface_info of full : signal is "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; - attribute x_interface_info of rd_clk : signal is "xilinx.com:signal:clock:1.0 read_clk CLK"; - attribute x_interface_parameter : string; - attribute x_interface_parameter of rd_clk : signal is "XIL_INTERFACENAME read_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0"; - attribute x_interface_info of rd_en : signal is "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; - attribute x_interface_info of wr_clk : signal is "xilinx.com:signal:clock:1.0 write_clk CLK"; - attribute x_interface_parameter of wr_clk : signal is "XIL_INTERFACENAME write_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0"; - attribute x_interface_info of wr_en : signal is "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; - attribute x_interface_info of din : signal is "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; - attribute x_interface_info of dout : signal is "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; -begin -U0: entity work.fifo_AntCtrl_fifo_generator_v13_2_4 - port map ( - almost_empty => NLW_U0_almost_empty_UNCONNECTED, - almost_full => NLW_U0_almost_full_UNCONNECTED, - axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0), - axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED, - axi_ar_injectdbiterr => '0', - axi_ar_injectsbiterr => '0', - axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED, - axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED, - axi_ar_prog_empty_thresh(3 downto 0) => B"0000", - axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED, - axi_ar_prog_full_thresh(3 downto 0) => B"0000", - axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0), - axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED, - axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED, - axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0), - axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0), - axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED, - axi_aw_injectdbiterr => '0', - axi_aw_injectsbiterr => '0', - axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED, - axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED, - axi_aw_prog_empty_thresh(3 downto 0) => B"0000", - axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED, - axi_aw_prog_full_thresh(3 downto 0) => B"0000", - axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0), - axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED, - axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED, - axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0), - axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0), - axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED, - axi_b_injectdbiterr => '0', - axi_b_injectsbiterr => '0', - axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED, - axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED, - axi_b_prog_empty_thresh(3 downto 0) => B"0000", - axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED, - axi_b_prog_full_thresh(3 downto 0) => B"0000", - axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0), - axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED, - axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED, - axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0), - axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0), - axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED, - axi_r_injectdbiterr => '0', - axi_r_injectsbiterr => '0', - axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED, - axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED, - axi_r_prog_empty_thresh(9 downto 0) => B"0000000000", - axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED, - axi_r_prog_full_thresh(9 downto 0) => B"0000000000", - axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0), - axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED, - axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED, - axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0), - axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0), - axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED, - axi_w_injectdbiterr => '0', - axi_w_injectsbiterr => '0', - axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED, - axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED, - axi_w_prog_empty_thresh(9 downto 0) => B"0000000000", - axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED, - axi_w_prog_full_thresh(9 downto 0) => B"0000000000", - axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0), - axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED, - axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED, - axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0), - axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0), - axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED, - axis_injectdbiterr => '0', - axis_injectsbiterr => '0', - axis_overflow => NLW_U0_axis_overflow_UNCONNECTED, - axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED, - axis_prog_empty_thresh(9 downto 0) => B"0000000000", - axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED, - axis_prog_full_thresh(9 downto 0) => B"0000000000", - axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0), - axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED, - axis_underflow => NLW_U0_axis_underflow_UNCONNECTED, - axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0), - backup => '0', - backup_marker => '0', - clk => '0', - data_count(9 downto 0) => NLW_U0_data_count_UNCONNECTED(9 downto 0), - dbiterr => NLW_U0_dbiterr_UNCONNECTED, - din(3 downto 0) => din(3 downto 0), - dout(3 downto 0) => dout(3 downto 0), - empty => empty, - full => full, - injectdbiterr => '0', - injectsbiterr => '0', - int_clk => '0', - m_aclk => '0', - m_aclk_en => '0', - m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0), - m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0), - m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0), - m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0), - m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0), - m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0), - m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0), - m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0), - m_axi_arready => '0', - m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0), - m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0), - m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0), - m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED, - m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0), - m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0), - m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0), - m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0), - m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0), - m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0), - m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0), - m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0), - m_axi_awready => '0', - m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0), - m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0), - m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0), - m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED, - m_axi_bid(0) => '0', - m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED, - m_axi_bresp(1 downto 0) => B"00", - m_axi_buser(0) => '0', - m_axi_bvalid => '0', - m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", - m_axi_rid(0) => '0', - m_axi_rlast => '0', - m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED, - m_axi_rresp(1 downto 0) => B"00", - m_axi_ruser(0) => '0', - m_axi_rvalid => '0', - m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0), - m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0), - m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED, - m_axi_wready => '0', - m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0), - m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0), - m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED, - m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0), - m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0), - m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0), - m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0), - m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED, - m_axis_tready => '0', - m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0), - m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0), - m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED, - overflow => NLW_U0_overflow_UNCONNECTED, - prog_empty => NLW_U0_prog_empty_UNCONNECTED, - prog_empty_thresh(9 downto 0) => B"0000000000", - prog_empty_thresh_assert(9 downto 0) => B"0000000000", - prog_empty_thresh_negate(9 downto 0) => B"0000000000", - prog_full => NLW_U0_prog_full_UNCONNECTED, - prog_full_thresh(9 downto 0) => B"0000000000", - prog_full_thresh_assert(9 downto 0) => B"0000000000", - prog_full_thresh_negate(9 downto 0) => B"0000000000", - rd_clk => rd_clk, - rd_data_count(9 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(9 downto 0), - rd_en => rd_en, - rd_rst => '0', - rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED, - rst => rst, - s_aclk => '0', - s_aclk_en => '0', - s_aresetn => '0', - s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", - s_axi_arburst(1 downto 0) => B"00", - s_axi_arcache(3 downto 0) => B"0000", - s_axi_arid(0) => '0', - s_axi_arlen(7 downto 0) => B"00000000", - s_axi_arlock(0) => '0', - s_axi_arprot(2 downto 0) => B"000", - s_axi_arqos(3 downto 0) => B"0000", - s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, - s_axi_arregion(3 downto 0) => B"0000", - s_axi_arsize(2 downto 0) => B"000", - s_axi_aruser(0) => '0', - s_axi_arvalid => '0', - s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", - s_axi_awburst(1 downto 0) => B"00", - s_axi_awcache(3 downto 0) => B"0000", - s_axi_awid(0) => '0', - s_axi_awlen(7 downto 0) => B"00000000", - s_axi_awlock(0) => '0', - s_axi_awprot(2 downto 0) => B"000", - s_axi_awqos(3 downto 0) => B"0000", - s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, - s_axi_awregion(3 downto 0) => B"0000", - s_axi_awsize(2 downto 0) => B"000", - s_axi_awuser(0) => '0', - s_axi_awvalid => '0', - s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0), - s_axi_bready => '0', - s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), - s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0), - s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, - s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0), - s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0), - s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, - s_axi_rready => '0', - s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), - s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0), - s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, - s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", - s_axi_wid(0) => '0', - s_axi_wlast => '0', - s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, - s_axi_wstrb(7 downto 0) => B"00000000", - s_axi_wuser(0) => '0', - s_axi_wvalid => '0', - s_axis_tdata(7 downto 0) => B"00000000", - s_axis_tdest(0) => '0', - s_axis_tid(0) => '0', - s_axis_tkeep(0) => '0', - s_axis_tlast => '0', - s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED, - s_axis_tstrb(0) => '0', - s_axis_tuser(3 downto 0) => B"0000", - s_axis_tvalid => '0', - sbiterr => NLW_U0_sbiterr_UNCONNECTED, - sleep => '0', - srst => '0', - underflow => NLW_U0_underflow_UNCONNECTED, - valid => NLW_U0_valid_UNCONNECTED, - wr_ack => NLW_U0_wr_ack_UNCONNECTED, - wr_clk => wr_clk, - wr_data_count(9 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(9 downto 0), - wr_en => wr_en, - wr_rst => '0', - wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED - ); -end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.vhdl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.vhdl deleted file mode 100644 index 294c6912..00000000 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.vhdl +++ /dev/null @@ -1,38 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:33:47 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.vhdl --- Design : fifo_AntCtrl --- Purpose : Stub declaration of top-level module interface --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity fifo_AntCtrl is - Port ( - rst : in STD_LOGIC; - wr_clk : in STD_LOGIC; - rd_clk : in STD_LOGIC; - din : in STD_LOGIC_VECTOR ( 3 downto 0 ); - wr_en : in STD_LOGIC; - rd_en : in STD_LOGIC; - dout : out STD_LOGIC_VECTOR ( 3 downto 0 ); - full : out STD_LOGIC; - empty : out STD_LOGIC - ); - -end fifo_AntCtrl; - -architecture stub of fifo_AntCtrl is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[3:0],wr_en,rd_en,dout[3:0],full,empty"; -attribute x_core_info : string; -attribute x_core_info of stub : architecture is "fifo_generator_v13_2_4,Vivado 2019.1.3"; -begin -end; diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_utilization_synth.pb b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_utilization_synth.pb deleted file mode 100644 index 9f50d5e5..00000000 Binary files a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_utilization_synth.pb and /dev/null differ diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/vivado.pb b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/vivado.pb deleted file mode 100644 index a43d6688..00000000 Binary files a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/vivado.pb and /dev/null differ diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_accor_cdc_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_accor_cdc_synth_1/gen_run.xml index d24987ce..d02d7867 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_accor_cdc_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_accor_cdc_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/gen_run.xml index fed5a2ee..1cfad34a 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ila_AntCtrl_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ila_AntCtrl_synth_1/gen_run.xml index 2ed45e28..e68e80a1 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ila_AntCtrl_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ila_AntCtrl_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ila_cal_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ila_cal_synth_1/gen_run.xml index ee2ef10f..fac2087b 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ila_cal_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ila_cal_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ila_rfcontrl_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ila_rfcontrl_synth_1/gen_run.xml index bd68af29..5d420b62 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ila_rfcontrl_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ila_rfcontrl_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ila_rx_pre_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ila_rx_pre_synth_1/gen_run.xml index b643f7cb..f955b5df 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ila_rx_pre_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ila_rx_pre_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ila_tx_rx_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ila_tx_rx_synth_1/gen_run.xml index 4879c56a..b75b3082 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ila_tx_rx_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ila_tx_rx_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ram_hop_data_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ram_hop_data_synth_1/gen_run.xml index a17ac080..ebfcf629 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ram_hop_data_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/ram_hop_data_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/gen_run.xml index ee1ab771..86c1b784 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/.Vivado_Synthesis.queue.rst b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/.vivado.begin.rst b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/.vivado.begin.rst similarity index 72% rename from projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/.vivado.begin.rst rename to projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/.vivado.begin.rst index 63a82c17..2b4da80c 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/.vivado.begin.rst +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/.vivado.end.rst b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/ISEWrap.js b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/ISEWrap.js similarity index 100% rename from projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/ISEWrap.js rename to projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/ISEWrap.js diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/ISEWrap.sh b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/ISEWrap.sh similarity index 100% rename from projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/ISEWrap.sh rename to projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/ISEWrap.sh diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/__synthesis_is_complete__ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/dont_touch.xdc b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/dont_touch.xdc new file mode 100644 index 00000000..7791a77c --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/dont_touch.xdc @@ -0,0 +1,24 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci +# IP: The module: 'selectio_lvds_rx' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_rx'. Do not add the DONT_TOUCH constraint. +set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xdc +# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_rx'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# IP: D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci +# IP: The module: 'selectio_lvds_rx' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_rx'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xdc +# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_rx'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/gen_run.xml new file mode 100644 index 00000000..1bfd60c2 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/gen_run.xml @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/htr.txt b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/htr.txt similarity index 68% rename from projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/htr.txt rename to projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/htr.txt index 757e9cc0..21b2764f 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/htr.txt +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/htr.txt @@ -6,4 +6,4 @@ REM to be invoked for Vivado to track run status. REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. REM -vivado -log fifo_AntCtrl.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fifo_AntCtrl.tcl +vivado -log selectio_lvds_rx.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_rx.tcl diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/project.wdf b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/project.wdf similarity index 88% rename from projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/project.wdf rename to projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/project.wdf index 9507bcd5..556f4b3b 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/project.wdf +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/project.wdf @@ -1,13 +1,13 @@ version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:38:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:36:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3239:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3239:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3330:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3330:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 @@ -34,6 +34,8 @@ version:1 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f74785f7278:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c72616d5f686f705f64617461:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c636f726469635f76365f305f31355c726f746174655f313662:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c73656c656374696f5f77697a5f76355f315f31335c73656c656374696f5f6c7664735f7278:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c73656c656374696f5f77697a5f76355f315f31335c73656c656374696f5f6c7664735f7478:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f616e745f7264:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f616e745f74657374:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f63616c:636f72655f636f6e7461696e6572:74727565:00:00 @@ -48,12 +50,12 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3238:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3633:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3633:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3633:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3633:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3633:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3633:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3633:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3661346264366134396337643466636438383330333461376438356536303661:506172656e742050412070726f6a656374204944:00 -eof:3863841633 +eof:3953027363 diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/rundef.js b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/rundef.js similarity index 89% rename from projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/rundef.js rename to projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/rundef.js index 1316dda9..834f3a85 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/rundef.js +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/rundef.js @@ -23,7 +23,7 @@ eval( EAInclude(ISEJScriptLib) ); ISEStep( "vivado", - "-log fifo_AntCtrl.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fifo_AntCtrl.tcl" ); + "-log selectio_lvds_rx.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_rx.tcl" ); diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/runme.bat b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/runme.bat similarity index 100% rename from projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/runme.bat rename to projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/runme.bat diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/runme.sh b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/runme.sh similarity index 79% rename from projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/runme.sh rename to projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/runme.sh index 2a0318ba..a040db07 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/runme.sh +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1' +HD_PWD='D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1' cd "$HD_PWD" HD_LOG=runme.log @@ -40,4 +40,4 @@ EAStep() fi } -EAStep vivado -log fifo_AntCtrl.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fifo_AntCtrl.tcl +EAStep vivado -log selectio_lvds_rx.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_rx.tcl diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.dcp b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.dcp new file mode 100644 index 00000000..d8aeb5d1 Binary files /dev/null and b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.dcp differ diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.tcl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.tcl new file mode 100644 index 00000000..7965001b --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.tcl @@ -0,0 +1,156 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64 +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7k410tffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo d:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci +set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_ooc.xdc] +set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1 -new_name selectio_lvds_rx -ip [get_ips selectio_lvds_rx]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top selectio_lvds_rx -part xc7k410tffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix selectio_lvds_rx_ selectio_lvds_rx.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_stub.v + lappend ipCachedFiles selectio_lvds_rx_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_stub.vhdl + lappend ipCachedFiles selectio_lvds_rx_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_sim_netlist.v + lappend ipCachedFiles selectio_lvds_rx_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_sim_netlist.vhdl + lappend ipCachedFiles selectio_lvds_rx_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp selectio_lvds_rx.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips selectio_lvds_rx] +} + +rename_ref -prefix_all selectio_lvds_rx_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef selectio_lvds_rx.dcp +create_report "selectio_lvds_rx_synth_1_synth_report_utilization_0" "report_utilization -file selectio_lvds_rx_utilization_synth.rpt -pb selectio_lvds_rx_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci] + +add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci] + +add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci] + +add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci] + +add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.dcp -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci] + +if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx]} { + catch { + file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.v D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx + } +} + +if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx]} { + catch { + file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.vhdl D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx + } +} + +if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx]} { + catch { + file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.v D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx + } +} + +if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx]} { + catch { + file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.vhdl D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.vds b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.vds new file mode 100644 index 00000000..09ad1655 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.vds @@ -0,0 +1,289 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Sun Mar 19 18:25:34 2023 +# Process ID: 30212 +# Current directory: D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1 +# Command line: vivado.exe -log selectio_lvds_rx.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_rx.tcl +# Log file: D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.vds +# Journal file: D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1\vivado.jou +#----------------------------------------------------------- +Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl' +source selectio_lvds_rx.tcl -notrace +Command: synth_design -top selectio_lvds_rx -part xc7k410tffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' +INFO: [Device 21-403] Loading part xc7k410tffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 26720 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 884.641 ; gain = 176.336 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'selectio_lvds_rx' [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.v:58] + Parameter SYS_W bound to: 2 - type: integer + Parameter DEV_W bound to: 2 - type: integer +INFO: [Synth 8-6157] synthesizing module 'selectio_lvds_rx_selectio_wiz' [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v:56] + Parameter SYS_W bound to: 2 - type: integer + Parameter DEV_W bound to: 2 - type: integer +INFO: [Synth 8-6157] synthesizing module 'IBUF' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:32856] + Parameter CAPACITANCE bound to: DONT_CARE - type: string + Parameter IBUF_DELAY_VALUE bound to: 0 - type: string + Parameter IBUF_LOW_PWR bound to: TRUE - type: string + Parameter IFD_DELAY_VALUE bound to: AUTO - type: string + Parameter IOSTANDARD bound to: LVCMOS33 - type: string +INFO: [Synth 8-6155] done synthesizing module 'IBUF' (1#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:32856] +INFO: [Synth 8-6157] synthesizing module 'FDRE' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] + Parameter INIT bound to: 1'b0 + Parameter IS_C_INVERTED bound to: 1'b0 + Parameter IS_D_INVERTED bound to: 1'b0 + Parameter IS_R_INVERTED bound to: 1'b0 +INFO: [Synth 8-6155] done synthesizing module 'FDRE' (2#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] +INFO: [Synth 8-6155] done synthesizing module 'selectio_lvds_rx_selectio_wiz' (3#1) [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v:56] +INFO: [Synth 8-6155] done synthesizing module 'selectio_lvds_rx' (4#1) [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.v:58] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 952.234 ; gain = 243.930 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:00 ; elapsed = 00:00:03 . Memory (MB): peak = 952.234 ; gain = 243.930 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:00 ; elapsed = 00:00:03 . Memory (MB): peak = 952.234 ; gain = 243.930 +--------------------------------------------------------------------------------- +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_ooc.xdc] for cell 'inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_ooc.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/selectio_lvds_rx_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/selectio_lvds_rx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xdc] for cell 'inst' +Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xdc] for cell 'inst' +Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/dont_touch.xdc] +Finished Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 995.320 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1007.500 ; gain = 12.180 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1007.500 ; gain = 299.195 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k410tffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1007.500 ; gain = 299.195 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for inst. (constraint file D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1007.500 ; gain = 299.195 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1007.500 ; gain = 299.195 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 1540 (col length:140) +BRAMs: 1590 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1007.500 ; gain = 299.195 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 1018.660 ; gain = 310.355 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 1018.660 ; gain = 310.355 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 1028.504 ; gain = 320.199 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |FDRE | 2| +|2 |IBUF | 2| ++------+-----+------+ + +Report Instance Areas: ++------+---------+------------------------------+------+ +| |Instance |Module |Cells | ++------+---------+------------------------------+------+ +|1 |top | | 4| +|2 | inst |selectio_lvds_rx_selectio_wiz | 4| ++------+---------+------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:01 ; elapsed = 00:00:10 . Memory (MB): peak = 1043.328 ; gain = 279.758 +Synthesis Optimization Complete : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1070.727 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +18 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:17 . Memory (MB): peak = 1070.727 ; gain = 683.102 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1070.727 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP selectio_lvds_rx, cache-ID = fffcbdb43410d449 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1070.727 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file selectio_lvds_rx_utilization_synth.rpt -pb selectio_lvds_rx_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Sun Mar 19 18:25:55 2023... diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.v b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.v new file mode 100644 index 00000000..925586ae --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.v @@ -0,0 +1,168 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +// Date : Sun Mar 19 18:25:55 2023 +// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.v +// Design : selectio_lvds_rx +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* DEV_W = "2" *) (* SYS_W = "2" *) +(* NotValidForBitStream *) +module selectio_lvds_rx + (data_in_from_pins, + data_in_to_device, + clk_in, + io_reset); + input [1:0]data_in_from_pins; + output [1:0]data_in_to_device; + input clk_in; + input io_reset; + + wire clk_in; + (* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire [1:0]data_in_from_pins; + wire [1:0]data_in_to_device; + wire io_reset; + + (* DEV_W = "2" *) + (* SYS_W = "2" *) + selectio_lvds_rx_selectio_lvds_rx_selectio_wiz inst + (.clk_in(clk_in), + .data_in_from_pins(data_in_from_pins), + .data_in_to_device(data_in_to_device), + .io_reset(io_reset)); +endmodule + +(* DEV_W = "2" *) (* ORIG_REF_NAME = "selectio_lvds_rx_selectio_wiz" *) (* SYS_W = "2" *) +module selectio_lvds_rx_selectio_lvds_rx_selectio_wiz + (data_in_from_pins, + data_in_to_device, + clk_in, + io_reset); + input [1:0]data_in_from_pins; + output [1:0]data_in_to_device; + input clk_in; + input io_reset; + + wire clk_in; + wire [1:0]data_in_from_pins; + wire [1:0]data_in_from_pins_int; + wire [1:0]data_in_to_device; + wire io_reset; + + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[0].fdre_in_inst + (.C(clk_in), + .CE(1'b1), + .D(data_in_from_pins_int[0]), + .Q(data_in_to_device[0]), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF \pins[0].ibuf_inst + (.I(data_in_from_pins[0]), + .O(data_in_from_pins_int[0])); + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[1].fdre_in_inst + (.C(clk_in), + .CE(1'b1), + .D(data_in_from_pins_int[1]), + .Q(data_in_to_device[1]), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF \pins[1].ibuf_inst + (.I(data_in_from_pins[1]), + .O(data_in_from_pins_int[1])); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.vhdl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.vhdl new file mode 100644 index 00000000..8998975d --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.vhdl @@ -0,0 +1,121 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Sun Mar 19 18:25:55 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim +-- D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.vhdl +-- Design : selectio_lvds_rx +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity selectio_lvds_rx_selectio_lvds_rx_selectio_wiz is + port ( + data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 ); + data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 ); + clk_in : in STD_LOGIC; + io_reset : in STD_LOGIC + ); + attribute DEV_W : integer; + attribute DEV_W of selectio_lvds_rx_selectio_lvds_rx_selectio_wiz : entity is 2; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of selectio_lvds_rx_selectio_lvds_rx_selectio_wiz : entity is "selectio_lvds_rx_selectio_wiz"; + attribute SYS_W : integer; + attribute SYS_W of selectio_lvds_rx_selectio_lvds_rx_selectio_wiz : entity is 2; +end selectio_lvds_rx_selectio_lvds_rx_selectio_wiz; + +architecture STRUCTURE of selectio_lvds_rx_selectio_lvds_rx_selectio_wiz is + signal data_in_from_pins_int : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of \pins[0].fdre_in_inst\ : label is "PRIMITIVE"; + attribute IOB : string; + attribute IOB of \pins[0].fdre_in_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[0].ibuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of \pins[0].ibuf_inst\ : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "AUTO"; + attribute BOX_TYPE of \pins[1].fdre_in_inst\ : label is "PRIMITIVE"; + attribute IOB of \pins[1].fdre_in_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[1].ibuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \pins[1].ibuf_inst\ : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE of \pins[1].ibuf_inst\ : label is "0"; + attribute IFD_DELAY_VALUE of \pins[1].ibuf_inst\ : label is "AUTO"; +begin +\pins[0].fdre_in_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => clk_in, + CE => '1', + D => data_in_from_pins_int(0), + Q => data_in_to_device(0), + R => io_reset + ); +\pins[0].ibuf_inst\: unisim.vcomponents.IBUF + port map ( + I => data_in_from_pins(0), + O => data_in_from_pins_int(0) + ); +\pins[1].fdre_in_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => clk_in, + CE => '1', + D => data_in_from_pins_int(1), + Q => data_in_to_device(1), + R => io_reset + ); +\pins[1].ibuf_inst\: unisim.vcomponents.IBUF + port map ( + I => data_in_from_pins(1), + O => data_in_from_pins_int(1) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity selectio_lvds_rx is + port ( + data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 ); + data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 ); + clk_in : in STD_LOGIC; + io_reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of selectio_lvds_rx : entity is true; + attribute DEV_W : integer; + attribute DEV_W of selectio_lvds_rx : entity is 2; + attribute SYS_W : integer; + attribute SYS_W of selectio_lvds_rx : entity is 2; +end selectio_lvds_rx; + +architecture STRUCTURE of selectio_lvds_rx is + attribute DEV_W of inst : label is 2; + attribute SYS_W of inst : label is 2; +begin +inst: entity work.selectio_lvds_rx_selectio_lvds_rx_selectio_wiz + port map ( + clk_in => clk_in, + data_in_from_pins(1 downto 0) => data_in_from_pins(1 downto 0), + data_in_to_device(1 downto 0) => data_in_to_device(1 downto 0), + io_reset => io_reset + ); +end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.v b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.v new file mode 100644 index 00000000..eadd56c4 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.v @@ -0,0 +1,23 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +// Date : Sun Mar 19 18:25:55 2023 +// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.v +// Design : selectio_lvds_rx +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module selectio_lvds_rx(data_in_from_pins, data_in_to_device, clk_in, + io_reset) +/* synthesis syn_black_box black_box_pad_pin="data_in_from_pins[1:0],data_in_to_device[1:0],clk_in,io_reset" */; + input [1:0]data_in_from_pins; + output [1:0]data_in_to_device; + input clk_in; + input io_reset; +endmodule diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.vhdl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.vhdl new file mode 100644 index 00000000..681e6822 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.vhdl @@ -0,0 +1,31 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Sun Mar 19 18:25:55 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub +-- D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.vhdl +-- Design : selectio_lvds_rx +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity selectio_lvds_rx is + Port ( + data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 ); + data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 ); + clk_in : in STD_LOGIC; + io_reset : in STD_LOGIC + ); + +end selectio_lvds_rx; + +architecture stub of selectio_lvds_rx is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "data_in_from_pins[1:0],data_in_to_device[1:0],clk_in,io_reset"; +begin +end; diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_utilization_synth.pb b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_utilization_synth.pb new file mode 100644 index 00000000..ac67e098 Binary files /dev/null and b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_utilization_synth.pb differ diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_utilization_synth.rpt b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_utilization_synth.rpt similarity index 73% rename from projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_utilization_synth.rpt rename to projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_utilization_synth.rpt index 3696bc6e..879d224b 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_utilization_synth.rpt +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_utilization_synth.rpt @@ -1,13 +1,13 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -| Date : Sat Mar 18 23:33:47 2023 +| Date : Sun Mar 19 18:25:55 2023 | Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -| Command : report_utilization -file fifo_AntCtrl_utilization_synth.rpt -pb fifo_AntCtrl_utilization_synth.pb -| Design : fifo_AntCtrl +| Command : report_utilization -file selectio_lvds_rx_utilization_synth.rpt -pb selectio_lvds_rx_utilization_synth.pb +| Design : selectio_lvds_rx | Device : 7k410tffg900-2 | Design State : Synthesized -------------------------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------------------------------------- Utilization Design Information @@ -27,20 +27,18 @@ Table of Contents 1. Slice Logic -------------- -+----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 198 | 0 | 254200 | 0.08 | -| LUT as Logic | 102 | 0 | 254200 | 0.04 | -| LUT as Memory | 96 | 0 | 90600 | 0.11 | -| LUT as Distributed RAM | 96 | 0 | | | -| LUT as Shift Register | 0 | 0 | | | -| Slice Registers | 162 | 0 | 508400 | 0.03 | -| Register as Flip Flop | 162 | 0 | 508400 | 0.03 | -| Register as Latch | 0 | 0 | 508400 | 0.00 | -| F7 Muxes | 8 | 0 | 127100 | <0.01 | -| F8 Muxes | 4 | 0 | 63550 | <0.01 | -+----------------------------+------+-------+-----------+-------+ ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 0 | 0 | 254200 | 0.00 | +| LUT as Logic | 0 | 0 | 254200 | 0.00 | +| LUT as Memory | 0 | 0 | 90600 | 0.00 | +| Slice Registers | 2 | 2 | 508400 | <0.01 | +| Register as Flip Flop | 2 | 2 | 508400 | <0.01 | +| Register as Latch | 0 | 0 | 508400 | 0.00 | +| F7 Muxes | 0 | 0 | 127100 | 0.00 | +| F8 Muxes | 0 | 0 | 63550 | 0.00 | ++-------------------------+------+-------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. @@ -56,10 +54,10 @@ Table of Contents | 0 | _ | Set | - | | 0 | _ | Reset | - | | 0 | Yes | - | - | -| 17 | Yes | - | Set | -| 57 | Yes | - | Reset | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | | 0 | Yes | Set | - | -| 88 | Yes | Reset | - | +| 2 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -92,7 +90,7 @@ Table of Contents +-----------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 0 | 0 | 500 | 0.00 | +| Bonded IOB | 2 | 0 | 500 | 0.40 | | Bonded IPADs | 0 | 0 | 50 | 0.00 | | Bonded OPADs | 0 | 0 | 32 | 0.00 | | PHY_CONTROL | 0 | 0 | 10 | 0.00 | @@ -153,19 +151,8 @@ Table of Contents +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| RAMD64E | 96 | Distributed Memory | -| FDRE | 88 | Flop & Latch | -| FDCE | 57 | Flop & Latch | -| LUT6 | 38 | LUT | -| LUT2 | 30 | LUT | -| LUT4 | 29 | LUT | -| FDPE | 17 | Flop & Latch | -| LUT5 | 10 | LUT | -| LUT3 | 9 | LUT | -| MUXF7 | 8 | MuxFx | -| CARRY4 | 8 | CarryLogic | -| MUXF8 | 4 | MuxFx | -| LUT1 | 2 | LUT | +| IBUF | 2 | IO | +| FDRE | 2 | Flop & Latch | +----------+------+---------------------+ diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/vivado.pb b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/vivado.pb new file mode 100644 index 00000000..81f52aab Binary files /dev/null and b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/vivado.pb differ diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/.Vivado_Synthesis.queue.rst b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/.vivado.begin.rst b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/.vivado.begin.rst new file mode 100644 index 00000000..9888d76d --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/.vivado.end.rst b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/ISEWrap.js b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/ISEWrap.js new file mode 100644 index 00000000..97a2ecbc --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/ISEWrap.sh b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/ISEWrap.sh new file mode 100644 index 00000000..f679f2e8 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/__synthesis_is_complete__ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/dont_touch.xdc b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/dont_touch.xdc new file mode 100644 index 00000000..00cea94d --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/dont_touch.xdc @@ -0,0 +1,24 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci +# IP: The module: 'selectio_lvds_tx' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_tx'. Do not add the DONT_TOUCH constraint. +set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xdc +# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_tx'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# IP: D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci +# IP: The module: 'selectio_lvds_tx' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_tx'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xdc +# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_tx'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/gen_run.xml similarity index 54% rename from projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/gen_run.xml rename to projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/gen_run.xml index 53a153fc..5808da1a 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/gen_run.xml @@ -1,23 +1,20 @@ - - - - - - - - - - - - + + + + + + + + + - + @@ -25,19 +22,19 @@ - - - + + - + @@ -45,7 +42,7 @@ - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/htr.txt b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/htr.txt new file mode 100644 index 00000000..6f803f89 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log selectio_lvds_tx.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_tx.tcl diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/project.wdf b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/project.wdf new file mode 100644 index 00000000..bec260d7 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/project.wdf @@ -0,0 +1,61 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:36:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3539:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3539:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3661346264366134396337643466636438383330333461376438356536303661:506172656e742050412070726f6a656374204944:00 +eof:1501154971 diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/rundef.js b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/rundef.js new file mode 100644 index 00000000..99169c8a --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/rundef.js @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log selectio_lvds_tx.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_tx.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/runme.bat b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/runme.bat new file mode 100644 index 00000000..1760626b --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/runme.sh b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/runme.sh new file mode 100644 index 00000000..d2e2a879 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin +else + PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log selectio_lvds_tx.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_tx.tcl diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.dcp b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.dcp new file mode 100644 index 00000000..0b9175b0 Binary files /dev/null and b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.dcp differ diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.tcl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.tcl new file mode 100644 index 00000000..2a7aa66d --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.tcl @@ -0,0 +1,156 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64 +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7k410tffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo d:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci +set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx_ooc.xdc] +set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1 -new_name selectio_lvds_tx -ip [get_ips selectio_lvds_tx]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top selectio_lvds_tx -part xc7k410tffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix selectio_lvds_tx_ selectio_lvds_tx.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_stub.v + lappend ipCachedFiles selectio_lvds_tx_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_stub.vhdl + lappend ipCachedFiles selectio_lvds_tx_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_sim_netlist.v + lappend ipCachedFiles selectio_lvds_tx_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_sim_netlist.vhdl + lappend ipCachedFiles selectio_lvds_tx_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp selectio_lvds_tx.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips selectio_lvds_tx] +} + +rename_ref -prefix_all selectio_lvds_tx_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef selectio_lvds_tx.dcp +create_report "selectio_lvds_tx_synth_1_synth_report_utilization_0" "report_utilization -file selectio_lvds_tx_utilization_synth.rpt -pb selectio_lvds_tx_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci] + +add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci] + +add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci] + +add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci] + +add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.dcp -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci] + +if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx]} { + catch { + file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx + } +} + +if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx]} { + catch { + file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx + } +} + +if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx]} { + catch { + file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx + } +} + +if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx]} { + catch { + file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.vds b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.vds new file mode 100644 index 00000000..d97a62cc --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.vds @@ -0,0 +1,305 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Sun Mar 19 17:31:58 2023 +# Process ID: 14484 +# Current directory: D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1 +# Command line: vivado.exe -log selectio_lvds_tx.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_tx.tcl +# Log file: D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.vds +# Journal file: D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1\vivado.jou +#----------------------------------------------------------- +Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl' +source selectio_lvds_tx.tcl -notrace +Command: synth_design -top selectio_lvds_tx -part xc7k410tffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' +INFO: [Device 21-403] Loading part xc7k410tffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 4804 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 883.914 ; gain = 177.477 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'selectio_lvds_tx' [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.v:58] + Parameter SYS_W bound to: 4 - type: integer + Parameter DEV_W bound to: 4 - type: integer +INFO: [Synth 8-6157] synthesizing module 'selectio_lvds_tx_selectio_wiz' [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v:56] + Parameter SYS_W bound to: 4 - type: integer + Parameter DEV_W bound to: 4 - type: integer +INFO: [Synth 8-6157] synthesizing module 'OBUF' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:45998] + Parameter CAPACITANCE bound to: DONT_CARE - type: string + Parameter DRIVE bound to: 12 - type: integer + Parameter IOSTANDARD bound to: LVCMOS33 - type: string + Parameter SLEW bound to: SLOW - type: string +INFO: [Synth 8-6155] done synthesizing module 'OBUF' (1#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:45998] +INFO: [Synth 8-6157] synthesizing module 'FDRE' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] + Parameter INIT bound to: 1'b0 + Parameter IS_C_INVERTED bound to: 1'b0 + Parameter IS_D_INVERTED bound to: 1'b0 + Parameter IS_R_INVERTED bound to: 1'b0 +INFO: [Synth 8-6155] done synthesizing module 'FDRE' (2#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] +INFO: [Synth 8-6157] synthesizing module 'IBUF' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:32856] + Parameter CAPACITANCE bound to: DONT_CARE - type: string + Parameter IBUF_DELAY_VALUE bound to: 0 - type: string + Parameter IBUF_LOW_PWR bound to: TRUE - type: string + Parameter IFD_DELAY_VALUE bound to: AUTO - type: string + Parameter IOSTANDARD bound to: LVCMOS33 - type: string +INFO: [Synth 8-6155] done synthesizing module 'IBUF' (3#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:32856] +INFO: [Synth 8-6157] synthesizing module 'BUFR' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1402] + Parameter BUFR_DIVIDE bound to: BYPASS - type: string + Parameter SIM_DEVICE bound to: 7SERIES - type: string +INFO: [Synth 8-6155] done synthesizing module 'BUFR' (4#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1402] +INFO: [Synth 8-6155] done synthesizing module 'selectio_lvds_tx_selectio_wiz' (5#1) [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v:56] +INFO: [Synth 8-6155] done synthesizing module 'selectio_lvds_tx' (6#1) [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.v:58] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 950.152 ; gain = 243.715 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:00 ; elapsed = 00:00:03 . Memory (MB): peak = 950.152 ; gain = 243.715 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:00 ; elapsed = 00:00:03 . Memory (MB): peak = 950.152 ; gain = 243.715 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx_ooc.xdc] for cell 'inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx_ooc.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/selectio_lvds_tx_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/selectio_lvds_tx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xdc] for cell 'inst' +Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xdc] for cell 'inst' +Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/dont_touch.xdc] +Finished Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1012.727 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1024.238 ; gain = 11.512 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1024.238 ; gain = 317.801 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k410tffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1024.238 ; gain = 317.801 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for inst. (constraint file D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1024.238 ; gain = 317.801 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1024.238 ; gain = 317.801 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 1540 (col length:140) +BRAMs: 1590 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1024.238 ; gain = 317.801 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 1024.238 ; gain = 317.801 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 1024.238 ; gain = 317.801 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 1024.535 ; gain = 318.098 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1040.312 ; gain = 333.875 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1040.312 ; gain = 333.875 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1040.312 ; gain = 333.875 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1040.312 ; gain = 333.875 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1040.312 ; gain = 333.875 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1040.312 ; gain = 333.875 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |BUFR | 1| +|2 |FDRE | 4| +|3 |IBUF | 1| +|4 |OBUF | 4| ++------+-----+------+ + +Report Instance Areas: ++------+---------+------------------------------+------+ +| |Instance |Module |Cells | ++------+---------+------------------------------+------+ +|1 |top | | 10| +|2 | inst |selectio_lvds_tx_selectio_wiz | 10| ++------+---------+------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1040.312 ; gain = 333.875 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 1040.312 ; gain = 259.789 +Synthesis Optimization Complete : Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.312 ; gain = 333.875 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1068.441 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:03 ; elapsed = 00:00:18 . Memory (MB): peak = 1068.441 ; gain = 681.945 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1068.441 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP selectio_lvds_tx, cache-ID = 1ad2c59fcdfd22ab +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1068.441 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file selectio_lvds_tx_utilization_synth.rpt -pb selectio_lvds_tx_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Sun Mar 19 17:32:20 2023... diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v new file mode 100644 index 00000000..9cf47661 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v @@ -0,0 +1,227 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +// Date : Sun Mar 19 17:32:20 2023 +// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v +// Design : selectio_lvds_tx +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* DEV_W = "4" *) (* SYS_W = "4" *) +(* NotValidForBitStream *) +module selectio_lvds_tx + (data_out_from_device, + data_out_to_pins, + clk_in, + clk_out, + io_reset); + input [3:0]data_out_from_device; + output [3:0]data_out_to_pins; + input clk_in; + output clk_out; + input io_reset; + + (* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire clk_in; + wire clk_out; + wire [3:0]data_out_from_device; + (* DRIVE = "12" *) (* IOSTANDARD = "LVCMOS33" *) (* SLEW = "SLOW" *) wire [3:0]data_out_to_pins; + wire io_reset; + + (* DEV_W = "4" *) + (* SYS_W = "4" *) + selectio_lvds_tx_selectio_lvds_tx_selectio_wiz inst + (.clk_in(clk_in), + .clk_out(clk_out), + .data_out_from_device(data_out_from_device), + .data_out_to_pins(data_out_to_pins), + .io_reset(io_reset)); +endmodule + +(* DEV_W = "4" *) (* ORIG_REF_NAME = "selectio_lvds_tx_selectio_wiz" *) (* SYS_W = "4" *) +module selectio_lvds_tx_selectio_lvds_tx_selectio_wiz + (data_out_from_device, + data_out_to_pins, + clk_in, + clk_out, + io_reset); + input [3:0]data_out_from_device; + output [3:0]data_out_to_pins; + input clk_in; + output clk_out; + input io_reset; + + wire clk_in; + wire clk_in_int; + wire clk_out; + wire [3:0]data_out_from_device; + wire [3:0]data_out_to_pins; + wire io_reset; + wire \pins[0].data_out_from_device_q ; + wire \pins[1].data_out_from_device_q ; + wire \pins[2].data_out_from_device_q ; + wire \pins[3].data_out_from_device_q ; + + (* BOX_TYPE = "PRIMITIVE" *) + BUFR #( + .BUFR_DIVIDE("BYPASS"), + .SIM_DEVICE("7SERIES")) + clkout_buf_inst + (.CE(1'b1), + .CLR(1'b0), + .I(clk_in_int), + .O(clk_out)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF ibuf_clk_inst + (.I(clk_in), + .O(clk_in_int)); + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[0].fdre_out_inst + (.C(clk_out), + .CE(1'b1), + .D(data_out_from_device[0]), + .Q(\pins[0].data_out_from_device_q ), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + OBUF \pins[0].obuf_inst + (.I(\pins[0].data_out_from_device_q ), + .O(data_out_to_pins[0])); + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[1].fdre_out_inst + (.C(clk_out), + .CE(1'b1), + .D(data_out_from_device[1]), + .Q(\pins[1].data_out_from_device_q ), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + OBUF \pins[1].obuf_inst + (.I(\pins[1].data_out_from_device_q ), + .O(data_out_to_pins[1])); + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[2].fdre_out_inst + (.C(clk_out), + .CE(1'b1), + .D(data_out_from_device[2]), + .Q(\pins[2].data_out_from_device_q ), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + OBUF \pins[2].obuf_inst + (.I(\pins[2].data_out_from_device_q ), + .O(data_out_to_pins[2])); + (* BOX_TYPE = "PRIMITIVE" *) + (* IOB = "TRUE" *) + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_R_INVERTED(1'b0)) + \pins[3].fdre_out_inst + (.C(clk_out), + .CE(1'b1), + .D(data_out_from_device[3]), + .Q(\pins[3].data_out_from_device_q ), + .R(io_reset)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + OBUF \pins[3].obuf_inst + (.I(\pins[3].data_out_from_device_q ), + .O(data_out_to_pins[3])); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl new file mode 100644 index 00000000..196d3869 --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl @@ -0,0 +1,193 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Sun Mar 19 17:32:20 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim +-- D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl +-- Design : selectio_lvds_tx +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity selectio_lvds_tx_selectio_lvds_tx_selectio_wiz is + port ( + data_out_from_device : in STD_LOGIC_VECTOR ( 3 downto 0 ); + data_out_to_pins : out STD_LOGIC_VECTOR ( 3 downto 0 ); + clk_in : in STD_LOGIC; + clk_out : out STD_LOGIC; + io_reset : in STD_LOGIC + ); + attribute DEV_W : integer; + attribute DEV_W of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz : entity is 4; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz : entity is "selectio_lvds_tx_selectio_wiz"; + attribute SYS_W : integer; + attribute SYS_W of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz : entity is 4; +end selectio_lvds_tx_selectio_lvds_tx_selectio_wiz; + +architecture STRUCTURE of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz is + signal clk_in_int : STD_LOGIC; + signal \^clk_out\ : STD_LOGIC; + signal \pins[0].data_out_from_device_q\ : STD_LOGIC; + signal \pins[1].data_out_from_device_q\ : STD_LOGIC; + signal \pins[2].data_out_from_device_q\ : STD_LOGIC; + signal \pins[3].data_out_from_device_q\ : STD_LOGIC; + attribute BOX_TYPE : string; + attribute BOX_TYPE of clkout_buf_inst : label is "PRIMITIVE"; + attribute BOX_TYPE of ibuf_clk_inst : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of ibuf_clk_inst : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of ibuf_clk_inst : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of ibuf_clk_inst : label is "AUTO"; + attribute BOX_TYPE of \pins[0].fdre_out_inst\ : label is "PRIMITIVE"; + attribute IOB : string; + attribute IOB of \pins[0].fdre_out_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[0].obuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \pins[0].obuf_inst\ : label is "DONT_CARE"; + attribute BOX_TYPE of \pins[1].fdre_out_inst\ : label is "PRIMITIVE"; + attribute IOB of \pins[1].fdre_out_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[1].obuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \pins[1].obuf_inst\ : label is "DONT_CARE"; + attribute BOX_TYPE of \pins[2].fdre_out_inst\ : label is "PRIMITIVE"; + attribute IOB of \pins[2].fdre_out_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[2].obuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \pins[2].obuf_inst\ : label is "DONT_CARE"; + attribute BOX_TYPE of \pins[3].fdre_out_inst\ : label is "PRIMITIVE"; + attribute IOB of \pins[3].fdre_out_inst\ : label is "TRUE"; + attribute BOX_TYPE of \pins[3].obuf_inst\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \pins[3].obuf_inst\ : label is "DONT_CARE"; +begin + clk_out <= \^clk_out\; +clkout_buf_inst: unisim.vcomponents.BUFR + generic map( + BUFR_DIVIDE => "BYPASS", + SIM_DEVICE => "7SERIES" + ) + port map ( + CE => '1', + CLR => '0', + I => clk_in_int, + O => \^clk_out\ + ); +ibuf_clk_inst: unisim.vcomponents.IBUF + port map ( + I => clk_in, + O => clk_in_int + ); +\pins[0].fdre_out_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => \^clk_out\, + CE => '1', + D => data_out_from_device(0), + Q => \pins[0].data_out_from_device_q\, + R => io_reset + ); +\pins[0].obuf_inst\: unisim.vcomponents.OBUF + port map ( + I => \pins[0].data_out_from_device_q\, + O => data_out_to_pins(0) + ); +\pins[1].fdre_out_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => \^clk_out\, + CE => '1', + D => data_out_from_device(1), + Q => \pins[1].data_out_from_device_q\, + R => io_reset + ); +\pins[1].obuf_inst\: unisim.vcomponents.OBUF + port map ( + I => \pins[1].data_out_from_device_q\, + O => data_out_to_pins(1) + ); +\pins[2].fdre_out_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => \^clk_out\, + CE => '1', + D => data_out_from_device(2), + Q => \pins[2].data_out_from_device_q\, + R => io_reset + ); +\pins[2].obuf_inst\: unisim.vcomponents.OBUF + port map ( + I => \pins[2].data_out_from_device_q\, + O => data_out_to_pins(2) + ); +\pins[3].fdre_out_inst\: unisim.vcomponents.FDRE + generic map( + INIT => '0', + IS_C_INVERTED => '0', + IS_D_INVERTED => '0', + IS_R_INVERTED => '0' + ) + port map ( + C => \^clk_out\, + CE => '1', + D => data_out_from_device(3), + Q => \pins[3].data_out_from_device_q\, + R => io_reset + ); +\pins[3].obuf_inst\: unisim.vcomponents.OBUF + port map ( + I => \pins[3].data_out_from_device_q\, + O => data_out_to_pins(3) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity selectio_lvds_tx is + port ( + data_out_from_device : in STD_LOGIC_VECTOR ( 3 downto 0 ); + data_out_to_pins : out STD_LOGIC_VECTOR ( 3 downto 0 ); + clk_in : in STD_LOGIC; + clk_out : out STD_LOGIC; + io_reset : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of selectio_lvds_tx : entity is true; + attribute DEV_W : integer; + attribute DEV_W of selectio_lvds_tx : entity is 4; + attribute SYS_W : integer; + attribute SYS_W of selectio_lvds_tx : entity is 4; +end selectio_lvds_tx; + +architecture STRUCTURE of selectio_lvds_tx is + attribute DEV_W of inst : label is 4; + attribute SYS_W of inst : label is 4; +begin +inst: entity work.selectio_lvds_tx_selectio_lvds_tx_selectio_wiz + port map ( + clk_in => clk_in, + clk_out => clk_out, + data_out_from_device(3 downto 0) => data_out_from_device(3 downto 0), + data_out_to_pins(3 downto 0) => data_out_to_pins(3 downto 0), + io_reset => io_reset + ); +end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v new file mode 100644 index 00000000..b520abfc --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v @@ -0,0 +1,24 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +// Date : Sun Mar 19 17:32:20 2023 +// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v +// Design : selectio_lvds_tx +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module selectio_lvds_tx(data_out_from_device, data_out_to_pins, + clk_in, clk_out, io_reset) +/* synthesis syn_black_box black_box_pad_pin="data_out_from_device[3:0],data_out_to_pins[3:0],clk_in,clk_out,io_reset" */; + input [3:0]data_out_from_device; + output [3:0]data_out_to_pins; + input clk_in; + output clk_out; + input io_reset; +endmodule diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl new file mode 100644 index 00000000..9591245e --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Sun Mar 19 17:32:20 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub +-- D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl +-- Design : selectio_lvds_tx +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity selectio_lvds_tx is + Port ( + data_out_from_device : in STD_LOGIC_VECTOR ( 3 downto 0 ); + data_out_to_pins : out STD_LOGIC_VECTOR ( 3 downto 0 ); + clk_in : in STD_LOGIC; + clk_out : out STD_LOGIC; + io_reset : in STD_LOGIC + ); + +end selectio_lvds_tx; + +architecture stub of selectio_lvds_tx is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "data_out_from_device[3:0],data_out_to_pins[3:0],clk_in,clk_out,io_reset"; +begin +end; diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_utilization_synth.pb b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_utilization_synth.pb new file mode 100644 index 00000000..661a3ce6 Binary files /dev/null and b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_utilization_synth.pb differ diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_utilization_synth.rpt b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_utilization_synth.rpt new file mode 100644 index 00000000..93bff00e --- /dev/null +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_utilization_synth.rpt @@ -0,0 +1,176 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +| Date : Sun Mar 19 17:32:20 2023 +| Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +| Command : report_utilization -file selectio_lvds_tx_utilization_synth.rpt -pb selectio_lvds_tx_utilization_synth.pb +| Design : selectio_lvds_tx +| Device : 7k410tffg900-2 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 0 | 0 | 254200 | 0.00 | +| LUT as Logic | 0 | 0 | 254200 | 0.00 | +| LUT as Memory | 0 | 0 | 90600 | 0.00 | +| Slice Registers | 4 | 4 | 508400 | <0.01 | +| Register as Flip Flop | 4 | 4 | 508400 | <0.01 | +| Register as Latch | 0 | 0 | 508400 | 0.00 | +| F7 Muxes | 0 | 0 | 127100 | 0.00 | +| F8 Muxes | 0 | 0 | 63550 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 4 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 795 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 795 | 0.00 | +| RAMB18 | 0 | 0 | 1590 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 1540 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 5 | 0 | 500 | 1.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| PHY_CONTROL | 0 | 0 | 10 | 0.00 | +| PHASER_REF | 0 | 0 | 10 | 0.00 | +| OUT_FIFO | 0 | 0 | 40 | 0.00 | +| IN_FIFO | 0 | 0 | 40 | 0.00 | +| IDELAYCTRL | 0 | 0 | 10 | 0.00 | +| IBUFDS | 0 | 0 | 480 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 500 | 0.00 | +| OLOGIC | 0 | 0 | 500 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 40 | 0.00 | +| MMCME2_ADV | 0 | 0 | 10 | 0.00 | +| PLLE2_ADV | 0 | 0 | 10 | 0.00 | +| BUFMRCE | 0 | 0 | 20 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 1 | 0 | 40 | 2.50 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUF | 4 | IO | +| FDRE | 4 | Flop & Latch | +| IBUF | 1 | IO | +| BUFR | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/vivado.pb b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/vivado.pb new file mode 100644 index 00000000..6c6a53e3 Binary files /dev/null and b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/vivado.pb differ diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_ant_rd_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_ant_rd_synth_1/gen_run.xml index fa882428..d28b5c3b 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_ant_rd_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_ant_rd_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_ant_test_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_ant_test_synth_1/gen_run.xml index 94ce7ff3..7ad89693 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_ant_test_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_ant_test_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_cal_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_cal_synth_1/gen_run.xml index 0afb598e..db1bd7e2 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_cal_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_cal_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_clk_ld_rd_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_clk_ld_rd_synth_1/gen_run.xml index 3933be00..f62cc565 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_clk_ld_rd_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_clk_ld_rd_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml index 69bfd87c..5cc301ee 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_rf_rd_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_rf_rd_synth_1/gen_run.xml index d779d3f0..9cf95b7a 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_rf_rd_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_rf_rd_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml index be09dd20..566eb21a 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.xpr b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.xpr index 18bbf680..2987bd60 100644 --- a/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.xpr +++ b/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.xpr @@ -3,7 +3,7 @@ - +