diff --git a/projects/datalink_814/dl814_k7_cal_coarse/constraints/k7410t_ad9516_2ad9361_timing.xdc b/projects/datalink_814/dl814_k7_cal_coarse/constraints/k7410t_ad9516_2ad9361_timing.xdc index cd739c97..e709e01d 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/constraints/k7410t_ad9516_2ad9361_timing.xdc +++ b/projects/datalink_814/dl814_k7_cal_coarse/constraints/k7410t_ad9516_2ad9361_timing.xdc @@ -1,4 +1,3 @@ set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[8]/C}] -to [get_pins u_ad9361_phase_cal/ad9361_recal_d1_reg/D] set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[10]/C}] -to [get_pins u_ad9361_phase_cal/ad9361_1_cal_start_d1_reg/D] -set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[7]/C}] -to [get_pins u_tx_pre_process/ad9361_tx_switch_d1_reg/D] set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[9]/C}] -to [get_pins u_ad9361_phase_cal/ad9361_2_cal_start_d1_reg/D] \ No newline at end of file diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit.veo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit.veo deleted file mode 100644 index 0a92ed05..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit.veo +++ /dev/null @@ -1,70 +0,0 @@ -// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 -// IP Revision: 3 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -COSLUT_10_16bit your_instance_name ( - .clka(clka), // input wire clka - .addra(addra), // input wire [12 : 0] addra - .douta(douta), // output wire [17 : 0] douta - .clkb(clkb), // input wire clkb - .addrb(addrb), // input wire [12 : 0] addrb - .doutb(doutb) // output wire [17 : 0] doutb -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file COSLUT_10_16bit.v when simulating -// the core, COSLUT_10_16bit. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit.vho b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit.vho deleted file mode 100644 index 9235e5fa..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit.vho +++ /dev/null @@ -1,85 +0,0 @@ --- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 --- IP Revision: 3 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT COSLUT_10_16bit - PORT ( - clka : IN STD_LOGIC; - addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0); - douta : OUT STD_LOGIC_VECTOR(17 DOWNTO 0); - clkb : IN STD_LOGIC; - addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0); - doutb : OUT STD_LOGIC_VECTOR(17 DOWNTO 0) - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : COSLUT_10_16bit - PORT MAP ( - clka => clka, - addra => addra, - douta => douta, - clkb => clkb, - addrb => addrb, - doutb => doutb - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file COSLUT_10_16bit.vhd when simulating --- the core, COSLUT_10_16bit. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit_sim_netlist.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit_sim_netlist.v deleted file mode 100644 index b277c79f..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit_sim_netlist.v +++ /dev/null @@ -1,2445 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:34:22 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_sim_netlist.v -// Design : COSLUT_10_16bit -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* CHECK_LICENSE_TYPE = "COSLUT_10_16bit,blk_mem_gen_v8_4_3,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) -(* NotValidForBitStream *) -module COSLUT_10_16bit - (clka, - addra, - douta, - clkb, - addrb, - doutb); - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) input clka; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [12:0]addra; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [17:0]douta; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) input clkb; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input [12:0]addrb; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output [17:0]doutb; - - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [17:0]douta; - wire [17:0]doutb; - wire NLW_U0_dbiterr_UNCONNECTED; - wire NLW_U0_rsta_busy_UNCONNECTED; - wire NLW_U0_rstb_busy_UNCONNECTED; - wire NLW_U0_s_axi_arready_UNCONNECTED; - wire NLW_U0_s_axi_awready_UNCONNECTED; - wire NLW_U0_s_axi_bvalid_UNCONNECTED; - wire NLW_U0_s_axi_dbiterr_UNCONNECTED; - wire NLW_U0_s_axi_rlast_UNCONNECTED; - wire NLW_U0_s_axi_rvalid_UNCONNECTED; - wire NLW_U0_s_axi_sbiterr_UNCONNECTED; - wire NLW_U0_s_axi_wready_UNCONNECTED; - wire NLW_U0_sbiterr_UNCONNECTED; - wire [12:0]NLW_U0_rdaddrecc_UNCONNECTED; - wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED; - wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; - wire [12:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED; - wire [17:0]NLW_U0_s_axi_rdata_UNCONNECTED; - wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED; - wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; - - (* C_ADDRA_WIDTH = "13" *) - (* C_ADDRB_WIDTH = "13" *) - (* C_ALGORITHM = "1" *) - (* C_AXI_ID_WIDTH = "4" *) - (* C_AXI_SLAVE_TYPE = "0" *) - (* C_AXI_TYPE = "1" *) - (* C_BYTE_SIZE = "9" *) - (* C_COMMON_CLK = "0" *) - (* C_COUNT_18K_BRAM = "0" *) - (* C_COUNT_36K_BRAM = "4" *) - (* C_CTRL_ECC_ALGO = "NONE" *) - (* C_DEFAULT_DATA = "0" *) - (* C_DISABLE_WARN_BHV_COLL = "0" *) - (* C_DISABLE_WARN_BHV_RANGE = "0" *) - (* C_ELABORATION_DIR = "./" *) - (* C_ENABLE_32BIT_ADDRESS = "0" *) - (* C_EN_DEEPSLEEP_PIN = "0" *) - (* C_EN_ECC_PIPE = "0" *) - (* C_EN_RDADDRA_CHG = "0" *) - (* C_EN_RDADDRB_CHG = "0" *) - (* C_EN_SAFETY_CKT = "0" *) - (* C_EN_SHUTDOWN_PIN = "0" *) - (* C_EN_SLEEP_PIN = "0" *) - (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 9.414399 mW" *) - (* C_FAMILY = "kintex7" *) - (* C_HAS_AXI_ID = "0" *) - (* C_HAS_ENA = "0" *) - (* C_HAS_ENB = "0" *) - (* C_HAS_INJECTERR = "0" *) - (* C_HAS_MEM_OUTPUT_REGS_A = "1" *) - (* C_HAS_MEM_OUTPUT_REGS_B = "1" *) - (* C_HAS_MUX_OUTPUT_REGS_A = "1" *) - (* C_HAS_MUX_OUTPUT_REGS_B = "1" *) - (* C_HAS_REGCEA = "0" *) - (* C_HAS_REGCEB = "0" *) - (* C_HAS_RSTA = "0" *) - (* C_HAS_RSTB = "0" *) - (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) - (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) - (* C_INITA_VAL = "0" *) - (* C_INITB_VAL = "0" *) - (* C_INIT_FILE = "COSLUT_10_16bit.mem" *) - (* C_INIT_FILE_NAME = "COSLUT_10_16bit.mif" *) - (* C_INTERFACE_TYPE = "0" *) - (* C_LOAD_INIT_FILE = "1" *) - (* C_MEM_TYPE = "4" *) - (* C_MUX_PIPELINE_STAGES = "0" *) - (* C_PRIM_TYPE = "1" *) - (* C_READ_DEPTH_A = "8192" *) - (* C_READ_DEPTH_B = "8192" *) - (* C_READ_LATENCY_A = "1" *) - (* C_READ_LATENCY_B = "1" *) - (* C_READ_WIDTH_A = "18" *) - (* C_READ_WIDTH_B = "18" *) - (* C_RSTRAM_A = "0" *) - (* C_RSTRAM_B = "0" *) - (* C_RST_PRIORITY_A = "CE" *) - (* C_RST_PRIORITY_B = "CE" *) - (* C_SIM_COLLISION_CHECK = "ALL" *) - (* C_USE_BRAM_BLOCK = "0" *) - (* C_USE_BYTE_WEA = "0" *) - (* C_USE_BYTE_WEB = "0" *) - (* C_USE_DEFAULT_DATA = "0" *) - (* C_USE_ECC = "0" *) - (* C_USE_SOFTECC = "0" *) - (* C_USE_URAM = "0" *) - (* C_WEA_WIDTH = "1" *) - (* C_WEB_WIDTH = "1" *) - (* C_WRITE_DEPTH_A = "8192" *) - (* C_WRITE_DEPTH_B = "8192" *) - (* C_WRITE_MODE_A = "WRITE_FIRST" *) - (* C_WRITE_MODE_B = "WRITE_FIRST" *) - (* C_WRITE_WIDTH_A = "18" *) - (* C_WRITE_WIDTH_B = "18" *) - (* C_XDEVICEFAMILY = "kintex7" *) - (* downgradeipidentifiedwarnings = "yes" *) - COSLUT_10_16bit_blk_mem_gen_v8_4_3 U0 - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .dbiterr(NLW_U0_dbiterr_UNCONNECTED), - .deepsleep(1'b0), - .dina({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .douta(douta), - .doutb(doutb), - .eccpipece(1'b0), - .ena(1'b0), - .enb(1'b0), - .injectdbiterr(1'b0), - .injectsbiterr(1'b0), - .rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[12:0]), - .regcea(1'b0), - .regceb(1'b0), - .rsta(1'b0), - .rsta_busy(NLW_U0_rsta_busy_UNCONNECTED), - .rstb(1'b0), - .rstb_busy(NLW_U0_rstb_busy_UNCONNECTED), - .s_aclk(1'b0), - .s_aresetn(1'b0), - .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_arburst({1'b0,1'b0}), - .s_axi_arid({1'b0,1'b0,1'b0,1'b0}), - .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED), - .s_axi_arsize({1'b0,1'b0,1'b0}), - .s_axi_arvalid(1'b0), - .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_awburst({1'b0,1'b0}), - .s_axi_awid({1'b0,1'b0,1'b0,1'b0}), - .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED), - .s_axi_awsize({1'b0,1'b0,1'b0}), - .s_axi_awvalid(1'b0), - .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]), - .s_axi_bready(1'b0), - .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]), - .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED), - .s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED), - .s_axi_injectdbiterr(1'b0), - .s_axi_injectsbiterr(1'b0), - .s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[12:0]), - .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[17:0]), - .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]), - .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED), - .s_axi_rready(1'b0), - .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]), - .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED), - .s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED), - .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_wlast(1'b0), - .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED), - .s_axi_wstrb(1'b0), - .s_axi_wvalid(1'b0), - .sbiterr(NLW_U0_sbiterr_UNCONNECTED), - .shutdown(1'b0), - .sleep(1'b0), - .wea(1'b0), - .web(1'b0)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) -module COSLUT_10_16bit_blk_mem_gen_generic_cstr - (douta, - doutb, - clka, - clkb, - addra, - addrb); - output [17:0]douta; - output [17:0]doutb; - input clka; - input clkb; - input [12:0]addra; - input [12:0]addrb; - - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [17:0]douta; - wire [35:0]douta_array; - wire [17:0]doutb; - wire [35:0]doutb_array; - wire [0:0]ena_array; - wire [0:0]enb_array; - - COSLUT_10_16bit_blk_mem_gen_mux \has_mux_a.A - (.addra(addra[12]), - .clka(clka), - .douta(douta), - .douta_array(douta_array)); - COSLUT_10_16bit_blk_mem_gen_mux__parameterized0 \has_mux_b.B - (.addrb(addrb[12]), - .clkb(clkb), - .doutb(doutb), - .doutb_array(doutb_array)); - COSLUT_10_16bit_blk_mem_gen_prim_width \ramloop[0].ram.r - (.addra(addra[11:0]), - .addrb(addrb[11:0]), - .clka(clka), - .clkb(clkb), - .douta_array(douta_array[8:0]), - .doutb_array(doutb_array[8:0]), - .ena_array(ena_array), - .enb_array(enb_array)); - COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .douta_array(douta_array[26:18]), - .doutb_array(doutb_array[26:18])); - COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .douta_array(douta_array[17:9]), - .doutb_array(doutb_array[17:9]), - .ena_array(ena_array), - .enb_array(enb_array)); - COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .douta_array(douta_array[35:27]), - .doutb_array(doutb_array[35:27])); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_mux" *) -module COSLUT_10_16bit_blk_mem_gen_mux - (douta, - addra, - clka, - douta_array); - output [17:0]douta; - input [0:0]addra; - input clka; - input [35:0]douta_array; - - wire [0:0]addra; - wire clka; - wire [17:0]dout_pipe; - wire [17:0]douta; - wire [35:0]douta_array; - wire sel_pipe; - wire sel_pipe_d1; - - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[0]_i_1 - (.I0(douta_array[18]), - .I1(sel_pipe_d1), - .I2(douta_array[0]), - .O(dout_pipe[0])); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[10]_i_1 - (.I0(douta_array[28]), - .I1(sel_pipe_d1), - .I2(douta_array[10]), - .O(dout_pipe[10])); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[11]_i_1 - (.I0(douta_array[29]), - .I1(sel_pipe_d1), - .I2(douta_array[11]), - .O(dout_pipe[11])); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[12]_i_1 - (.I0(douta_array[30]), - .I1(sel_pipe_d1), - .I2(douta_array[12]), - .O(dout_pipe[12])); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[13]_i_1 - (.I0(douta_array[31]), - .I1(sel_pipe_d1), - .I2(douta_array[13]), - .O(dout_pipe[13])); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[14]_i_1 - (.I0(douta_array[32]), - .I1(sel_pipe_d1), - .I2(douta_array[14]), - .O(dout_pipe[14])); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[15]_i_1 - (.I0(douta_array[33]), - .I1(sel_pipe_d1), - .I2(douta_array[15]), - .O(dout_pipe[15])); - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[16]_i_1 - (.I0(douta_array[34]), - .I1(sel_pipe_d1), - .I2(douta_array[16]), - .O(dout_pipe[16])); - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[17]_i_1 - (.I0(douta_array[35]), - .I1(sel_pipe_d1), - .I2(douta_array[17]), - .O(dout_pipe[17])); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[1]_i_1 - (.I0(douta_array[19]), - .I1(sel_pipe_d1), - .I2(douta_array[1]), - .O(dout_pipe[1])); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[2]_i_1 - (.I0(douta_array[20]), - .I1(sel_pipe_d1), - .I2(douta_array[2]), - .O(dout_pipe[2])); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[3]_i_1 - (.I0(douta_array[21]), - .I1(sel_pipe_d1), - .I2(douta_array[3]), - .O(dout_pipe[3])); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[4]_i_1 - (.I0(douta_array[22]), - .I1(sel_pipe_d1), - .I2(douta_array[4]), - .O(dout_pipe[4])); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[5]_i_1 - (.I0(douta_array[23]), - .I1(sel_pipe_d1), - .I2(douta_array[5]), - .O(dout_pipe[5])); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[6]_i_1 - (.I0(douta_array[24]), - .I1(sel_pipe_d1), - .I2(douta_array[6]), - .O(dout_pipe[6])); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[7]_i_1 - (.I0(douta_array[25]), - .I1(sel_pipe_d1), - .I2(douta_array[7]), - .O(dout_pipe[7])); - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[8]_i_1 - (.I0(douta_array[26]), - .I1(sel_pipe_d1), - .I2(douta_array[8]), - .O(dout_pipe[8])); - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[9]_i_1 - (.I0(douta_array[27]), - .I1(sel_pipe_d1), - .I2(douta_array[9]), - .O(dout_pipe[9])); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[0] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[0]), - .Q(douta[0]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[10] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[10]), - .Q(douta[10]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[11] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[11]), - .Q(douta[11]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[12] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[12]), - .Q(douta[12]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[13] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[13]), - .Q(douta[13]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[14] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[14]), - .Q(douta[14]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[15] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[15]), - .Q(douta[15]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[16] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[16]), - .Q(douta[16]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[17] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[17]), - .Q(douta[17]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[1] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[1]), - .Q(douta[1]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[2] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[2]), - .Q(douta[2]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[3] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[3]), - .Q(douta[3]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[4] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[4]), - .Q(douta[4]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[5] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[5]), - .Q(douta[5]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[6] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[6]), - .Q(douta[6]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[7] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[7]), - .Q(douta[7]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[8] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[8]), - .Q(douta[8]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[9] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[9]), - .Q(douta[9]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0] - (.C(clka), - .CE(1'b1), - .D(sel_pipe), - .Q(sel_pipe_d1), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] - (.C(clka), - .CE(1'b1), - .D(addra), - .Q(sel_pipe), - .R(1'b0)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_mux" *) -module COSLUT_10_16bit_blk_mem_gen_mux__parameterized0 - (doutb, - addrb, - clkb, - doutb_array); - output [17:0]doutb; - input [0:0]addrb; - input clkb; - input [35:0]doutb_array; - - wire [0:0]addrb; - wire clkb; - wire [17:0]doutb; - wire [35:0]doutb_array; - wire \no_softecc_gmuxr.ce_pri.dout_i[0]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[10]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[11]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[12]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[13]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[14]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[15]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[16]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[17]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[1]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[2]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[3]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[4]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[5]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[6]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[7]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[8]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[9]_i_1_n_0 ; - wire \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ; - wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0] ; - - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[0]_i_1 - (.I0(doutb_array[18]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[0]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[10]_i_1 - (.I0(doutb_array[28]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[10]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[10]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[11]_i_1 - (.I0(doutb_array[29]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[11]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[11]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[12]_i_1 - (.I0(doutb_array[30]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[12]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[12]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[13]_i_1 - (.I0(doutb_array[31]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[13]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[13]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair16" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[14]_i_1 - (.I0(doutb_array[32]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[14]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[14]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair16" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[15]_i_1 - (.I0(doutb_array[33]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[15]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[15]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair17" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[16]_i_1 - (.I0(doutb_array[34]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[16]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[16]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair17" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[17]_i_1 - (.I0(doutb_array[35]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[17]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[17]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[1]_i_1 - (.I0(doutb_array[19]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[1]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[1]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[2]_i_1 - (.I0(doutb_array[20]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[2]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[2]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[3]_i_1 - (.I0(doutb_array[21]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[3]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[3]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair11" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[4]_i_1 - (.I0(doutb_array[22]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[4]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[4]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair11" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[5]_i_1 - (.I0(doutb_array[23]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[5]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[5]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[6]_i_1 - (.I0(doutb_array[24]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[6]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[6]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[7]_i_1 - (.I0(doutb_array[25]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[7]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[7]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[8]_i_1 - (.I0(doutb_array[26]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[8]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[8]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[9]_i_1 - (.I0(doutb_array[27]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[9]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[9]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[0] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[0]_i_1_n_0 ), - .Q(doutb[0]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[10] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[10]_i_1_n_0 ), - .Q(doutb[10]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[11] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[11]_i_1_n_0 ), - .Q(doutb[11]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[12] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[12]_i_1_n_0 ), - .Q(doutb[12]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[13] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[13]_i_1_n_0 ), - .Q(doutb[13]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[14] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[14]_i_1_n_0 ), - .Q(doutb[14]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[15] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[15]_i_1_n_0 ), - .Q(doutb[15]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[16] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[16]_i_1_n_0 ), - .Q(doutb[16]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[17] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[17]_i_1_n_0 ), - .Q(doutb[17]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[1] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[1]_i_1_n_0 ), - .Q(doutb[1]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[2] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[2]_i_1_n_0 ), - .Q(doutb[2]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[3] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[3]_i_1_n_0 ), - .Q(doutb[3]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[4] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[4]_i_1_n_0 ), - .Q(doutb[4]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[5] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[5]_i_1_n_0 ), - .Q(doutb[5]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[6] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[6]_i_1_n_0 ), - .Q(doutb[6]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[7] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[7]_i_1_n_0 ), - .Q(doutb[7]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[8] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[8]_i_1_n_0 ), - .Q(doutb[8]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[9] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[9]_i_1_n_0 ), - .Q(doutb[9]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0] ), - .Q(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] - (.C(clkb), - .CE(1'b1), - .D(addrb), - .Q(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0] ), - .R(1'b0)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) -module COSLUT_10_16bit_blk_mem_gen_prim_width - (douta_array, - doutb_array, - clka, - clkb, - ena_array, - enb_array, - addra, - addrb); - output [8:0]douta_array; - output [8:0]doutb_array; - input clka; - input clkb; - input [0:0]ena_array; - input [0:0]enb_array; - input [11:0]addra; - input [11:0]addrb; - - wire [11:0]addra; - wire [11:0]addrb; - wire clka; - wire clkb; - wire [8:0]douta_array; - wire [8:0]doutb_array; - wire [0:0]ena_array; - wire [0:0]enb_array; - - COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init \prim_init.ram - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .douta_array(douta_array), - .doutb_array(doutb_array), - .ena_array(ena_array), - .enb_array(enb_array)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) -module COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized0 - (douta_array, - doutb_array, - clka, - clkb, - addra, - addrb); - output [8:0]douta_array; - output [8:0]doutb_array; - input clka; - input clkb; - input [12:0]addra; - input [12:0]addrb; - - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [8:0]douta_array; - wire [8:0]doutb_array; - - COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized0 \prim_init.ram - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .douta_array(douta_array), - .doutb_array(doutb_array)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) -module COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized1 - (douta_array, - doutb_array, - ena_array, - enb_array, - clka, - clkb, - addra, - addrb); - output [8:0]douta_array; - output [8:0]doutb_array; - output [0:0]ena_array; - output [0:0]enb_array; - input clka; - input clkb; - input [12:0]addra; - input [12:0]addrb; - - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [8:0]douta_array; - wire [8:0]doutb_array; - wire [0:0]ena_array; - wire [0:0]enb_array; - - COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized1 \prim_init.ram - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .douta_array(douta_array), - .doutb_array(doutb_array), - .ena_array(ena_array), - .enb_array(enb_array)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) -module COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized2 - (douta_array, - doutb_array, - clka, - clkb, - addra, - addrb); - output [8:0]douta_array; - output [8:0]doutb_array; - input clka; - input clkb; - input [12:0]addra; - input [12:0]addrb; - - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [8:0]douta_array; - wire [8:0]doutb_array; - - COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized2 \prim_init.ram - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .douta_array(douta_array), - .doutb_array(doutb_array)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) -module COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init - (douta_array, - doutb_array, - clka, - clkb, - ena_array, - enb_array, - addra, - addrb); - output [8:0]douta_array; - output [8:0]doutb_array; - input clka; - input clkb; - input [0:0]ena_array; - input [0:0]enb_array; - input [11:0]addra; - input [11:0]addrb; - - wire [11:0]addra; - wire [11:0]addrb; - wire clka; - wire clkb; - wire [8:0]douta_array; - wire [8:0]doutb_array; - wire [0:0]ena_array; - wire [0:0]enb_array; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; - wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; - wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; - wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; - wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; - wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; - - (* box_type = "PRIMITIVE" *) - RAMB36E1 #( - .DOA_REG(1), - .DOB_REG(1), - .EN_ECC_READ("FALSE"), - .EN_ECC_WRITE("FALSE"), - .INITP_00(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INITP_01(256'hFFFFFFFFFFFFE0000000000000000000000000000000003FFFFFFFFFFFFFFFFF), - .INITP_02(256'h0000000003FFFFFFFFFFFFFFFFFFE0000000000000000000001FFFFFFFFFFFFF), - .INITP_03(256'h00000000000FFFFFFFFFFFFFF800000000000000FFFFFFFFFFFFFFFF80000000), - .INITP_04(256'h0003FFFFFFFFFF800000000003FFFFFFFFFFF0000000000007FFFFFFFFFFFE00), - .INITP_05(256'h8000000007FFFFFFFF8000000001FFFFFFFFF8000000000FFFFFFFFFF8000000), - .INITP_06(256'h0000000FFFFFFFE00000001FFFFFFFE00000001FFFFFFFF800000001FFFFFFFF), - .INITP_07(256'hFFFFFFC0000007FFFFFF0000000FFFFFFF80000007FFFFFFC0000000FFFFFFFC), - .INITP_08(256'h0FFFFFF000000FFFFFF0000007FFFFFC000001FFFFFF8000001FFFFFF8000001), - .INITP_09(256'hFFC00001FFFFF800000FFFFFC00000FFFFFE000003FFFFF800000FFFFFF00000), - .INITP_0A(256'hFFFF800007FFFF800007FFFF800003FFFFE00001FFFFF000007FFFFE00000FFF), - .INITP_0B(256'hF80000FFFFC00007FFFE00003FFFF80000FFFFE00001FFFFC00007FFFF800007), - .INITP_0C(256'hFFF80003FFFE00007FFFC0000FFFF80001FFFF80001FFFF00001FFFF80001FFF), - .INITP_0D(256'hE0000FFFF0000FFFF00007FFF80007FFFC0001FFFE0000FFFF80003FFFE0000F), - .INITP_0E(256'hFFC0007FFF0001FFFE0003FFFC0007FFF8000FFFF0000FFFF0000FFFE0001FFF), - .INITP_0F(256'h0003FFF0001FFF8000FFFE0007FFF0001FFFC000FFFE0003FFF8000FFFE0003F), - .INIT_00(256'hFDFDFDFDFDFDFDFEFEFEFEFEFEFEFEFEFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_01(256'hF5F6F6F6F7F7F7F7F8F8F8F8F9F9F9F9FAFAFAFAFBFBFBFBFBFCFCFCFCFCFCFD), - .INIT_02(256'hE9EAEAEBEBEBECECEDEDEEEEEEEFEFF0F0F0F1F1F1F2F2F3F3F3F4F4F4F5F5F5), - .INIT_03(256'hD8D9D9DADBDBDCDCDDDDDEDFDFE0E0E1E1E2E2E3E3E4E4E5E5E6E6E7E7E8E8E9), - .INIT_04(256'hC2C3C4C4C5C6C7C7C8C9C9CACBCCCCCDCECECFD0D0D1D2D2D3D4D4D5D6D6D7D8), - .INIT_05(256'hA7A8A9AAABACADADAEAFB0B1B2B3B3B4B5B6B7B8B9B9BABBBCBDBDBEBFC0C1C1), - .INIT_06(256'h8788898A8B8C8E8F909192939495969798999A9B9C9D9E9FA0A1A1A2A3A4A5A6), - .INIT_07(256'h6264656667686A6B6C6D6E7071727374757778797A7B7C7D7E80818283848586), - .INIT_08(256'h393A3B3D3E3F414243454647494A4B4D4E4F515253555657585A5B5C5D5F6061), - .INIT_09(256'h0A0B0D0E101113141617191A1C1D1F202223252628292A2C2D2F303233343637), - .INIT_0A(256'hD6D8DADBDDDFE0E2E4E5E7E8EAECEDEFF1F2F4F5F7F9FAFCFDFF010204050708), - .INIT_0B(256'h9E9FA1A3A5A7A9AAACAEB0B2B3B5B7B9BBBCBEC0C2C3C5C7C9CACCCECFD1D3D4), - .INIT_0C(256'h60626466686A6C6E70727476787A7C7E7F81838587898B8D8F91929496989A9C), - .INIT_0D(256'h1E20222426282B2D2F31333537393B3D40424446484A4C4E50525456585A5C5E), - .INIT_0E(256'hD6D9DBDDE0E2E4E6E9EBEDEFF2F4F6F8FBFDFF010406080A0C0F11131517191C), - .INIT_0F(256'h8A8D8F929496999B9EA0A3A5A7AAACAFB1B3B6B8BABDBFC1C4C6C8CBCDCFD2D4), - .INIT_10(256'h393C3E414346494B4E505355585B5D606265676A6C6F717476797B7E80838588), - .INIT_11(256'hE3E6E8EBEEF1F3F6F9FCFE010407090C0F111417191C1F212427292C2F313436), - .INIT_12(256'h888B8E919497999C9FA2A5A8ABAEB0B3B6B9BCBFC1C4C7CACDCFD2D5D8DBDDE0), - .INIT_13(256'h282B2E3134373A3E4144474A4D505356595C5F6265686B6E707376797C7F8285), - .INIT_14(256'hC3C7CACDD0D3D7DADDE0E3E7EAEDF0F3F6F9FD000306090C0F1216191C1F2225), - .INIT_15(256'h5A5D6064676B6E7175787B7F8285898C8F9296999CA0A3A6A9ADB0B3B6BABDC0), - .INIT_16(256'hEBEFF2F6F9FD0004070B0E1215191C2023262A2D3134383B3F4245494C505356), - .INIT_17(256'h787B7F83868A8E9195999CA0A4A7ABAEB2B6B9BDC0C4C8CBCFD2D6D9DDE1E4E8), - .INIT_18(256'hFF03070B0F12161A1E2225292D3135383C4044474B4F53565A5E6265696D7074), - .INIT_19(256'h82868A8E92969A9EA2A6AAAEB2B6BABDC1C5C9CDD1D5D9DDE1E4E8ECF0F4F8FC), - .INIT_1A(256'h0004080C1115191D2125292D31363A3E42464A4E52565A5E62666A6E72767A7E), - .INIT_1B(256'h797D82868A8F93979BA0A4A8ACB1B5B9BDC1C6CACED2D6DBDFE3E7EBEFF4F8FC), - .INIT_1C(256'hEDF2F6FBFF04080C11151A1E22272B2F34383D41454A4E52575B5F64686C7175), - .INIT_1D(256'h5D61666A6F74787D81868A8F93989DA1A6AAAFB3B8BCC1C5CACED3D7DCE0E4E9), - .INIT_1E(256'hC7CCD1D5DADFE4E8EDF2F6FB0004090E13171C21252A2E33383C41464A4F5358), - .INIT_1F(256'h2D32373B40454A4F54595E62676C71767B7F84898E93979CA1A6ABAFB4B9BEC2), - .INIT_20(256'h8E93989DA2A7ACB1B6BBC0C5CACFD4D9DEE3E8EDF2F7FC01050A0F14191E2328), - .INIT_21(256'hEAEFF4F9FE03090E13181D22282D32373C41464C51565B60656A6F74797E8389), - .INIT_22(256'h41464B51565B61666B71767B81868B90969BA0A6ABB0B5BBC0C5CACFD5DADFE4), - .INIT_23(256'h93989EA3A9AEB4B9BFC4CACFD5DAE0E5EAF0F5FB00060B10161B20262B31363B), - .INIT_24(256'hE0E6ECF1F7FD02080E13191E242A2F353A40454B51565C61676C72777D82888D), - .INIT_25(256'h292F353B40464C52575D63696E747A80858B91979CA2A8ADB3B9BEC4CACFD5DB), - .INIT_26(256'h6D73797F858B91979DA2A8AEB4BAC0C6CCD2D7DDE3E9EFF5FB00060C12181E23), - .INIT_27(256'hACB2B8BEC4CBD1D7DDE3E9EFF5FB01070D13191F252B31373D43494F555B6167), - .INIT_28(256'hE6EDF3F9FF060C12181F252B31373D444A50565C63696F757B81878E949AA0A6), - .INIT_29(256'h1C22292F353C42494F555C62686F757B82888E959BA1A8AEB4BBC1C7CDD4DAE0), - .INIT_2A(256'h4D535A60676D747A81878E949BA1A8AEB5BBC2C8CFD5DCE2E9EFF5FC02090F16), - .INIT_2B(256'h797F868D939AA1A7AEB5BBC2C9CFD6DDE3EAF0F7FE040B12181F252C32394046), - .INIT_2C(256'hA0A7AEB4BBC2C9D0D7DDE4EBF2F9FF060D141A21282F353C434A50575E656B72), - .INIT_2D(256'hC2C9D0D7DEE5ECF3FA01080F161D242B323940464D545B626970777E848B9299), - .INIT_2E(256'hE0E7EEF5FD040B121920272E353D444B525960676E757C838A91989FA6ADB4BB), - .INIT_2F(256'hF900080F161D252C333B424950575F666D747C838A9198A0A7AEB5BCC3CBD2D9), - .INIT_30(256'h0D151C242B323A414950575F666E757C848B939AA1A9B0B7BFC6CDD5DCE3EAF2), - .INIT_31(256'h1D242C343B434A5259616970787F878E969DA5ACB4BBC3CAD2D9E1E8F0F7FE06), - .INIT_32(256'h282F373F474E565E656D757D848C949BA3ABB2BAC2C9D1D8E0E8EFF7FE060E15), - .INIT_33(256'h2E363E464D555D656D757C848C949CA4ABB3BBC3CBD2DAE2EAF1F90109111820), - .INIT_34(256'h2F373F474F575F676F777F878F979FA7AFB7BFC7CFD7DFE7EFF7FF060E161E26), - .INIT_35(256'h2C343C454D555D656D767E868E969EA6AEB6BFC7CFD7DFE7EFF7FF070F171F27), - .INIT_36(256'h242D353D464E565E676F7780889098A1A9B1B9C2CAD2DAE2EBF3FB030B141C24), - .INIT_37(256'h182029313A424A535B646C757D858E969FA7AFB8C0C8D1D9E2EAF2FB030B141C), - .INIT_38(256'h070F182029323A434B545C656E767F879098A1A9B2BAC3CBD4DCE5EDF6FE070F), - .INIT_39(256'hF1F9020B141C252E373F485159626B747C858E969FA8B0B9C2CAD3DBE4EDF5FE), - .INIT_3A(256'hD6DFE8F1FA030C141D262F38414A525B646D767F879099A2ABB3BCC5CED6DFE8), - .INIT_3B(256'hB7C0C9D2DBE4EDF6FF08111A232C353E475059626B747D868F98A1AAB3BCC4CD), - .INIT_3C(256'h949DA6AFB8C1CBD4DDE6EFF8010B141D262F38414A535D666F78818A939CA5AE), - .INIT_3D(256'h6B757E87919AA3ACB6BFC8D2DBE4EDF70009131C252E37414A535C666F78818A), - .INIT_3E(256'h3E48515B646E77818A949DA6B0B9C3CCD5DFE8F2FB040E17212A333D464F5962), - .INIT_3F(256'h0D17202A333D47505A636D77808A939DA6B0B9C3CCD6DFE9F3FC060F19222B35), - .INIT_40(256'hD7E1EBF4FE08121B252F38424C565F69737C869099A3ADB6C0CAD3DDE7F0FA03), - .INIT_41(256'h9DA6B0BAC4CED8E2ECF5FF09131D27313A444E58626B757F89939CA6B0BAC4CD), - .INIT_42(256'h5D67727C86909AA4AEB8C2CCD6E0EAF4FE08111B252F39434D57616B757F8993), - .INIT_43(256'h1A242E38434D57616B757F8A949EA8B2BCC6D0DBE5EFF9030D17212B353F4953), - .INIT_44(256'hD2DCE6F1FB05101A242E39434D58626C76818B959FAAB4BEC8D2DDE7F1FB0510), - .INIT_45(256'h85909AA5AFB9C4CED9E3EEF8020D17222C36414B56606A757F89949EA8B3BDC7), - .INIT_46(256'h343F49545E69747E89939EA8B3BEC8D3DDE8F2FD07121C27313C46515B66707B), - .INIT_47(256'hDFE9F4FF09141F2A343F4A545F6A747F8A959FAAB5BFCAD4DFEAF4FF0A141F29), - .INIT_48(256'h848F9AA5B0BBC6D1DBE6F1FC07121C27323D48525D68737E88939EA9B3BEC9D4), - .INIT_49(256'h26313C47525D68737E89949FAAB5C0CBD6E1ECF7020C17222D38434E59646F7A), - .INIT_4A(256'hC3CED9E5F0FB06111C27323E49545F6A75808B96A1ACB8C3CED9E4EFFA05101B), - .INIT_4B(256'h5C67727E89949FABB6C1CDD8E3EEFA05101B26323D48535E6A75808B96A2ADB8), - .INIT_4C(256'hF0FB07121E2935404B57626E7984909BA6B2BDC9D4DFEBF6010D18232F3A4550), - .INIT_4D(256'h808B97A3AEBAC5D1DCE8F3FF0A16212D38444F5B66727D8994A0ABB7C2CED9E5), - .INIT_4E(256'h0B17232E3A46525D6975808C98A3AFBBC6D2DDE9F5000C18232F3A46525D6974), - .INIT_4F(256'h929EAAB6C2CED9E5F1FD0914202C38444F5B67737F8A96A2AEB9C5D1DCE8F400), - .INIT_50(256'h15212D3945515D6975818D99A5B1BDC8D4E0ECF804101C28343F4B57636F7B87), - .INIT_51(256'h94A0ACB8C4D0DCE8F4010D1925313D4955616D7985919DA9B5C1CDD9E5F1FD09), - .INIT_52(256'h0E1A26323F4B5763707C8894A0ADB9C5D1DDEAF6020E1A26333F4B57636F7B88), - .INIT_53(256'h83909CA9B5C1CEDAE6F3FF0B1824303D4955626E7A87939FACB8C4D0DDE9F501), - .INIT_54(256'hF5020E1B2734404D5965727E8B97A4B0BDC9D6E2EFFB0714202D3946525E6B77), - .INIT_55(256'h626F7B8895A1AEBBC7D4E1EDFA0613202C3945525E6B7884919DAAB6C3CFDCE8), - .INIT_56(256'hCBD8E5F1FE0B1825313E4B5864717E8A97A4B1BDCAD7E3F0FD0A1623303C4956), - .INIT_57(256'h303D4A5763707D8A97A4B1BECBD7E4F1FE0B1825313E4B5865727E8B98A5B2BE), - .INIT_58(256'h909DAAB7C4D1DFECF90613202D3A4754616E7B8894A1AEBBC8D5E2EFFC091623), - .INIT_59(256'hEDFA0714212E3C495663707D8A98A5B2BFCCD9E6F3000E1B2835424F5C697683), - .INIT_5A(256'h45525F6C7A8794A2AFBCCAD7E4F1FF0C192634414E5B687683909DABB8C5D2DF), - .INIT_5B(256'h98A6B3C1CEDCE9F604111F2C394754626F7C8A97A4B2BFCDDAE7F5020F1D2A37), - .INIT_5C(256'hE8F603111E2C39475562707D8B98A6B3C1CEDCE9F704121F2D3A485563707E8B), - .INIT_5D(256'h34414F5D6A788693A1AFBCCAD8E5F3010E1C2A374553606E7B8997A4B2BFCDDB), - .INIT_5E(256'h7B8997A4B2C0CEDCEAF70513212F3C4A586673818F9DAAB8C6D4E1EFFD0A1826), - .INIT_5F(256'hBECCDAE8F60412202E3C4A586673818F9DABB9C7D5E3F0FE0C1A283644515F6D), - .INIT_60(256'hFD0C1A28364452606E7C8A98A6B4C2D0DEECFA08162432404E5C6A788694A2B0), - .INIT_61(256'h3947556371808E9CAAB8C6D5E3F1FF0D1B2A38465462707E8D9BA9B7C5D3E1EF), - .INIT_62(256'h707E8C9BA9B7C6D4E2F0FF0D1B2A38465563717F8E9CAAB8C7D5E3F1000E1C2A), - .INIT_63(256'hA2B1BFCEDCEBF90816253341505E6D7B8A98A6B5C3D1E0EEFD0B192836445361), - .INIT_64(256'hD1E0EFFD0C1A293746556372808F9DACBAC9D7E6F50312202F3D4C5A69778694), - .INIT_65(256'hFC0B1A283746556372818F9EADBBCAD9E7F6051322313F4E5C6B7A8897A6B4C3), - .INIT_66(256'h233241505F6D7C8B9AA9B7C6D5E4F301101F2E3D4B5A69788695A4B3C1D0DFEE), - .INIT_67(256'h465564738291A0AFBECDDCEBF90817263544536271808F9DACBBCAD9E8F70514), - .INIT_68(256'h65748392A1B0C0CFDEEDFC0B1A2938475665748392A1B0BFCEDDECFB0A192837), - .INIT_69(256'h808F9EAEBDCCDBEAFA09182736465564738291A0B0BFCEDDECFB0A1A29384756), - .INIT_6A(256'h97A6B6C5D4E4F302122130404F5E6E7D8C9BABBAC9D8E8F70615253443526271), - .INIT_6B(256'hAABAC9D9E8F807162635455464738292A1B1C0CFDFEEFE0D1C2C3B4A5A697888), - .INIT_6C(256'hBAC9D9E8F807172736465565748493A3B2C2D1E1F0000F1F2E3E4D5D6C7C8B9B), - .INIT_6D(256'hC5D5E4F404132333425262718191A0B0C0CFDFEFFE0E1E2D3D4C5C6C7B8B9AAA), - .INIT_6E(256'hCDDCECFC0C1C2B3B4B5B6B7A8A9AAAB9C9D9E9F808182837475767768696A6B5), - .INIT_6F(256'hD0E0F0001020304050606F7F8F9FAFBFCFDFEFFE0E1E2E3E4E5E6D7D8D9DADBD), - .INIT_70(256'hD0E0F000102030405061718191A1B1C1D1E1F101112131415161708090A0B0C0), - .INIT_71(256'hCCDCEDFD0D1D2D3D4E5E6E7E8E9EAEBFCFDFEFFF0F1F2F3F4F60708090A0B0C0), - .INIT_72(256'hC5D5E5F506162637475767788898A8B9C9D9E9FA0A1A2A3A4B5B6B7B8B9CACBC), - .INIT_73(256'hB9CADAEAFB0B1C2C3C4D5D6D7E8E9FAFBFD0E0F001112132425263738394A4B4), - .INIT_74(256'hAABACBDCECFD0D1E2E3F4F60708191A2B2C2D3E3F404152536465767778898A9), - .INIT_75(256'h97A8B8C9DAEAFB0B1C2D3D4E5F6F8090A1B2C2D3E3F404152636475768788999), - .INIT_76(256'h8091A2B3C3D4E5F606172839495A6B7B8C9DAEBECFE0F0011222334454657686), - .INIT_77(256'h66778899AABBCBDCEDFE0F2030415263748595A6B7C8D9E9FA0B1C2D3D4E5F70), - .INIT_78(256'h48596A7B8C9DAEBFD0E1F2031425364758697A8A9BACBDCEDFF0011223344455), - .INIT_79(256'h2738495A6B7C8D9EAFC0D2E3F405162738495A6B7C8D9EAFC0D1E2F304152637), - .INIT_7A(256'h021324354658697A8B9CAEBFD0E1F20315263748596A7B8D9EAFC0D1E2F30416), - .INIT_7B(256'hD9EAFB0D1E2F415263758697A8BACBDCEEFF10213344556678899AABBDCEDFF0), - .INIT_7C(256'hACBECFE1F204152638495B6C7D8FA0B2C3D4E6F7091A2B3D4E5F718293A5B6C7), - .INIT_7D(256'h7C8EA0B1C3D4E6F7091A2C3D4F60728395A6B8C9DBECFE0F213244556778899B), - .INIT_7E(256'h495B6C7E90A1B3C5D6E8F90B1D2E405263758698AABBCDDEF00213253648596B), - .INIT_7F(256'h12243647596B7D8EA0B2C4D5E7F90B1C2E405163758798AABCCDDFF102142637), - .INIT_A(36'h000000000), - .INIT_B(36'h000000000), - .INIT_FILE("NONE"), - .IS_CLKARDCLK_INVERTED(1'b0), - .IS_CLKBWRCLK_INVERTED(1'b0), - .IS_ENARDEN_INVERTED(1'b0), - .IS_ENBWREN_INVERTED(1'b0), - .IS_RSTRAMARSTRAM_INVERTED(1'b0), - .IS_RSTRAMB_INVERTED(1'b0), - .IS_RSTREGARSTREG_INVERTED(1'b0), - .IS_RSTREGB_INVERTED(1'b0), - .RAM_EXTENSION_A("NONE"), - .RAM_EXTENSION_B("NONE"), - .RAM_MODE("TDP"), - .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), - .READ_WIDTH_A(9), - .READ_WIDTH_B(9), - .RSTREG_PRIORITY_A("REGCE"), - .RSTREG_PRIORITY_B("REGCE"), - .SIM_COLLISION_CHECK("ALL"), - .SIM_DEVICE("7SERIES"), - .SRVAL_A(36'h000000000), - .SRVAL_B(36'h000000000), - .WRITE_MODE_A("WRITE_FIRST"), - .WRITE_MODE_B("WRITE_FIRST"), - .WRITE_WIDTH_A(9), - .WRITE_WIDTH_B(9)) - \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram - (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}), - .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}), - .CASCADEINA(1'b0), - .CASCADEINB(1'b0), - .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), - .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), - .CLKARDCLK(clka), - .CLKBWRCLK(clkb), - .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), - .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIPADIP({1'b0,1'b0,1'b0,1'b0}), - .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), - .DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],douta_array[7:0]}), - .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}), - .DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],douta_array[8]}), - .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}), - .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), - .ENARDEN(ena_array), - .ENBWREN(enb_array), - .INJECTDBITERR(1'b0), - .INJECTSBITERR(1'b0), - .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), - .REGCEAREGCE(1'b1), - .REGCEB(1'b1), - .RSTRAMARSTRAM(1'b0), - .RSTRAMB(1'b0), - .RSTREGARSTREG(1'b0), - .RSTREGB(1'b0), - .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), - .WEA({1'b0,1'b0,1'b0,1'b0}), - .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) -module COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized0 - (douta_array, - doutb_array, - clka, - clkb, - addra, - addrb); - output [8:0]douta_array; - output [8:0]doutb_array; - input clka; - input clkb; - input [12:0]addra; - input [12:0]addrb; - - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [8:0]douta_array; - wire [8:0]doutb_array; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; - wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; - wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; - wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; - wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; - wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; - - (* box_type = "PRIMITIVE" *) - RAMB36E1 #( - .DOA_REG(1), - .DOB_REG(1), - .EN_ECC_READ("FALSE"), - .EN_ECC_WRITE("FALSE"), - .INITP_00(256'hC000FFFC000FFFC001FFF8001FFF8001FFF8000FFFC000FFFC000FFFE0007FFE), - .INITP_01(256'h1FFF0007FFC000FFF8003FFF0007FFC000FFF8001FFF0003FFF0007FFE0007FF), - .INITP_02(256'hFFF8003FFC001FFF0007FF8003FFE000FFF8003FFE000FFF8003FFE000FFF800), - .INITP_03(256'h01FFE001FFF000FFF0007FF8003FFC003FFE001FFF000FFF8003FFC001FFE000), - .INITP_04(256'hFF8007FF8007FF8007FF8007FF8007FF8007FF8007FF8003FFC003FFC003FFE0), - .INITP_05(256'hFF001FFE003FFC003FF8007FF800FFF000FFE001FFE001FFC003FFC003FFC003), - .INITP_06(256'h7FF800FFE003FFC007FF000FFE001FFC007FF800FFF001FFE003FFC007FF800F), - .INITP_07(256'h800FFE003FF800FFE003FF8007FF001FFC007FF001FFE003FF800FFE001FFC00), - .INITP_08(256'h03FF801FFC007FF001FFC007FF003FF800FFE003FF800FFE003FF800FFE003FF), - .INITP_09(256'h0FFE003FF001FFC00FFE003FF001FFC007FE003FF800FFC007FF001FF800FFE0), - .INITP_0A(256'h01FF800FFC007FE003FF001FF800FFC007FF003FF801FFC007FE003FF001FFC0), - .INITP_0B(256'hC00FFC007FE003FF003FF801FFC00FFC007FE003FF001FF800FFC007FE003FF0), - .INITP_0C(256'hFF800FFC00FFE007FE003FF003FF801FF800FFC00FFE007FE003FF003FF801FF), - .INITP_0D(256'h007FE007FE003FF003FF001FF801FF800FFC00FFE007FE007FF003FF001FF801), - .INITP_0E(256'hFF800FFC00FFC00FFE007FE007FE003FF003FF001FF801FF801FFC00FFC00FFE), - .INITP_0F(256'h001FF801FF801FFC00FFC00FFC007FE007FE007FE003FF003FF003FF801FF801), - .INIT_00(256'hD8EAFB0D1F31435567788A9CAEC0D2E3F507192B3D4E60728496A7B9CBDDEF00), - .INIT_01(256'h9AACBED0E2F406182A3B4D5F718395A7B9CBDDEF01132537485A6C7E90A2B4C6), - .INIT_02(256'h586A7D8FA1B3C5D7E9FB0D1F31435567798C9EB0C2D4E6F80A1C2E4052647688), - .INIT_03(256'h1426384A5C6F8193A5B7C9DCEE00122436495B6D7F91A3B5C7DAECFE10223446), - .INIT_04(256'hCBDEF0021527394B5E708295A7B9CBDEF0021427394B5D708294A6B9CBDDEF01), - .INIT_05(256'h8092A5B7C9DCEE011325384A5D6F8194A6B8CBDDEF021426394B5D708294A7B9), - .INIT_06(256'h314356687B8DA0B2C5D7EAFC0F213446596B7E90A3B5C8DAECFF112436495B6D), - .INIT_07(256'hDFF10416293C4E61748699ABBED0E3F6081B2D405265788A9DAFC2D4E7F90C1E), - .INIT_08(256'h899CAEC1D4E7F90C1F3144576A7C8FA2B4C7DAECFF1224374A5C6F8194A7B9CC), - .INIT_09(256'h304356697B8EA1B4C7DAECFF1225374A5D708395A8BBCEE0F306192B3E516476), - .INIT_0A(256'hD4E7FA0D203346586B7E91A4B7CADDF00315283B4E61748799ACBFD2E5F80B1D), - .INIT_0B(256'h75889BAEC1D4E7FA0D203346596C7F92A5B8CBDEF104172A3C4F6275889BAEC1), - .INIT_0C(256'h1225384B5F728598ABBED1E4F70A1E3144576A7D90A3B6C9DCEF0215283C4F62), - .INIT_0D(256'hACBFD3E6F90C203346596C8093A6B9CCE0F306192C3F5366798C9FB2C5D9ECFF), - .INIT_0E(256'h43576A7D91A4B7CADEF104182B3E5265788B9FB2C5D8ECFF1226394C5F728699), - .INIT_0F(256'hD7EAFE1125384C5F728699ADC0D3E7FA0E2134485B6E8295A8BCCFE3F6091D30), - .INIT_10(256'h687B8FA2B6C9DDF004172B3E5265798CA0B3C7DAEE0115283C4F6276899DB0C4), - .INIT_11(256'hF5091D3044576B7F92A6B9CDE1F4081B2F43566A7D91A4B8CBDFF3061A2D4154), - .INIT_12(256'h8094A7BBCFE2F60A1E3145596C8094A7BBCFE2F60A1D3145586C8093A7BBCEE2), - .INIT_13(256'h071B2F43576A7E92A6BACDE1F5091C3044586C7F93A7BBCEE2F60A1D3145586C), - .INIT_14(256'h8CA0B4C8DBEF03172B3F53677B8EA2B6CADEF206192D4155697D90A4B8CCE0F4), - .INIT_15(256'h0D2135495D718599ADC1D5E9FD1125394D6175899DB1C5D9EC0014283C506478), - .INIT_16(256'h8CA0B4C8DCF004182C4054697D91A5B9CDE1F5091D3145596D8195A9BDD1E5F9), - .INIT_17(256'h071B2F44586C8094A9BDD1E5F90D21364A5E72869AAEC3D7EBFF13273B4F6378), - .INIT_18(256'h8094A8BCD1E5F90E22364A5F73879BAFC4D8EC0015293D51667A8EA2B6CBDFF3), - .INIT_19(256'hF50A1E32475B6F8498ACC1D5E9FE12263B4F63788CA0B5C9DDF2061A2E43576B), - .INIT_1A(256'h687C91A5BACEE3F70C2034495D72869BAFC3D8EC0115293E52677B8FA4B8CCE1), - .INIT_1B(256'hD8EC01152A3E53687C91A5BACEE3F70C2035495E72879BB0C4D9ED02162B3F53), - .INIT_1C(256'h45596E8397ACC1D5EAFE13283C51657A8FA3B8CCE1F60A1F33485C71869AAFC3), - .INIT_1D(256'hAFC4D8ED02172B4055697E93A7BCD1E6FA0F24384D62768BA0B4C9DEF2071C30), - .INIT_1E(256'h162B40556A7E93A8BDD2E6FB1025394E63788DA1B6CBE0F4091E33475C71869A), - .INIT_1F(256'h7B90A5BACFE3F80D22374C61768A9FB4C9DEF3081C31465B708599AEC3D8ED02), - .INIT_20(256'hDDF2071C31465B70859AAFC4D8ED02172C41566B8095AABFD4E9FE12273C5166), - .INIT_21(256'h3C51667B90A5BACFE4FA0F24394E63788DA2B7CCE1F60B20354A5F74899EB3C8), - .INIT_22(256'h98AEC3D8ED02172C42576C8196ABC0D5EB00152A3F54697E93A8BED3E8FD1227), - .INIT_23(256'hF2081D32475C72879CB1C7DCF1061B31465B70859AB0C5DAEF041A2F44596E83), - .INIT_24(256'h495F74899FB4C9DFF4091F34495E74899EB3C9DEF3091E33485E73889DB3C8DD), - .INIT_25(256'h9EB3C9DEF4091E34495F74899FB4C9DFF4091F34495F748A9FB4CADFF40A1F34), - .INIT_26(256'hF0051B30465B71869CB1C7DCF2071C32475D72889DB2C8DDF3081E33485E7389), - .INIT_27(256'h3F556A8096ABC1D6EC01172C42576D8298AEC3D9EE04192F445A6F859AB0C5DA), - .INIT_28(256'h8CA2B7CDE3F80E24394F647A90A5BBD1E6FC11273C52687D93A8BED4E9FF142A), - .INIT_29(256'hD7EC02182D43596F849AB0C5DBF1061C32475D73889EB4C9DFF50A20364B6177), - .INIT_2A(256'h1E344A60768BA1B7CDE2F80E243A4F657B91A6BCD2E8FD13293F546A8095ABC1), - .INIT_2B(256'h647A90A5BBD1E7FD13293E546A8096ACC1D7ED03192F445A70869CB1C7DDF309), - .INIT_2C(256'hA7BDD3E9FF142A40566C8298AEC4DAF0061C31475D73899FB5CBE1F60C22384E), - .INIT_2D(256'hE7FD13293F556B8197ADC3D9EF051B31475D73899FB5CBE1F70D23394F657B91), - .INIT_2E(256'h263C52687E94AAC0D6EC02182F455B71879DB3C9DFF50B21374D63798FA5BBD1), - .INIT_2F(256'h61788EA4BAD0E6FC13293F556B8197AEC4DAF0061C32485F758BA1B7CDE3F90F), - .INIT_30(256'h9BB1C7DEF40A20364D63798FA6BCD2E8FE152B41576D849AB0C6DCF3091F354B), - .INIT_31(256'hD2E8FF152B42586E849BB1C7DEF40A20374D637A90A6BCD3E9FF152C42586E85), - .INIT_32(256'h071D344A61778DA4BAD0E7FD132A40566D839AB0C6DDF30920364C62798FA5BC), - .INIT_33(256'h3A50677D93AAC0D7ED041A31475D748AA1B7CDE4FA11273D546A8197ADC4DAF1), - .INIT_34(256'h6A8197AEC4DBF1081E354B62788FA5BCD2E9FF162C435970869CB3C9E0F60D23), - .INIT_35(256'h98AFC6DCF30920364D647A91A7BED4EB02182F455C72899FB6CCE3FA10273D54), - .INIT_36(256'hC5DBF2081F364C637A90A7BED4EB01182F455C7389A0B6CDE4FA11273E556B82), - .INIT_37(256'hEE051C334960778DA4BBD2E8FF162C435A70879EB4CBE2F90F263D536A8197AE), - .INIT_38(256'h162D445B71889FB6CDE3FA11283E556C8399B0C7DEF40B22394F667D94AAC1D8), - .INIT_39(256'h3C536A8197AEC5DCF30A21374E657C93A9C0D7EE051C324960778EA4BBD2E900), - .INIT_3A(256'h60778EA5BBD2E900172E455C738AA0B7CEE5FC132A41576E859CB3CAE1F80E25), - .INIT_3B(256'h8198AFC6DDF40B223950677E95ACC3DAF1081F364D647B91A8BFD6ED041B3249), - .INIT_3C(256'hA1B8CFE6FD142B425970879FB6CDE4FB122940576E859CB3CAE1F80F263D546B), - .INIT_3D(256'hBFD6ED041B324961788FA6BDD4EB021930475E758DA4BBD2E900172E455C738A), - .INIT_3E(256'hDBF20920374E667D94ABC2D9F0081F364D647B92AAC1D8EF061D344B627A91A8), - .INIT_3F(256'hF50C233A51698097AEC5DDF40B223951687F96ADC5DCF30A213850677E95ACC3), - .INIT_40(256'h0C243B526A8198AFC7DEF50C243B52698198AFC6DEF50C233B52698098AFC6DD), - .INIT_41(256'h233A51698097AFC6DDF50C233A52698098AFC6DEF50C243B52698198AFC7DEF5), - .INIT_42(256'h374E667D94ACC3DBF20921384F677E96ADC4DCF30A223950687F97AEC5DDF40B), - .INIT_43(256'h49617890A7BFD6ED051C344B637A91A9C0D8EF071E354D647C93AAC2D9F1081F), - .INIT_44(256'h5A7189A0B8CFE7FE162D455C748BA3BAD2E9011830475F768EA5BDD4EB031A32), - .INIT_45(256'h698098B0C7DFF60E253D546C849BB3CAE2F9112840576F869EB5CDE4FC132B42), - .INIT_46(256'h768EA5BDD5EC041B334B627A91A9C1D8F0071F364E667D95ACC4DCF30B223A51), - .INIT_47(256'h8299B1C9E0F810273F576E869EB5CDE4FC142B435B728AA2B9D1E800182F475F), - .INIT_48(256'h8CA3BBD3EA021A3249617990A8C0D7EF071E364E667D95ADC4DCF40B233B526A), - .INIT_49(256'h94ACC3DBF30B223A526A8199B1C9E0F810283F576F879EB6CEE5FD152D445C74), - .INIT_4A(256'h9AB2CAE2FA112941597188A0B8D0E8FF172F475F768EA6BED6ED051D354C647C), - .INIT_4B(256'h9FB7CFE7FF172F465E768EA6BED6ED051D354D657C94ACC4DCF40B233B536B83), - .INIT_4C(256'hA3BBD3EB031A324A627A92AAC2DAF209213951698199B1C9E0F8102840587088), - .INIT_4D(256'hA5BDD5ED051D354D657C94ACC4DCF40C243C546C849CB4CCE4FB132B435B738B), - .INIT_4E(256'hA5BDD5ED051D354D657D95ADC5DDF50D253D556D859DB5CDE5FD152D455D758D), - .INIT_4F(256'hA4BCD5ED051D354D657D95ADC5DDF50D253D556D859DB5CDE5FD152D455D758D), - .INIT_50(256'hA2BAD2EA021A334B637B93ABC3DBF30B233B546C849CB4CCE4FC142C445C748C), - .INIT_51(256'h9EB6CEE7FF172F475F7790A8C0D8F008203851698199B1C9E1F9112A425A728A), - .INIT_52(256'h99B1C9E2FA122A425A738BA3BBD3EB041C344C647C95ADC5DDF50D253E566E86), - .INIT_53(256'h92ABC3DBF30C243C546C859DB5CDE5FE162E465F778FA7BFD7F0082038506981), - .INIT_54(256'h8BA3BBD3EC041C344D657D95AEC6DEF60F273F577088A0B8D1E90119324A627A), - .INIT_55(256'h819AB2CAE3FB132C445C748DA5BDD6EE061E374F678098B0C8E1F9112A425A72), - .INIT_56(256'h778FA8C0D8F109213A526A839BB3CCE4FC152D455E768EA7BFD7F00820395169), - .INIT_57(256'h6B849CB5CDE5FE162E475F7890A8C1D9F10A223B536B849CB4CDE5FD162E465F), - .INIT_58(256'h5F778FA8C0D9F10A223A536B849CB4CDE5FE162E475F7890A8C1D9F20A223B53), - .INIT_59(256'h5169829AB2CBE3FC142D455E768EA7BFD8F009213A526A839BB4CCE5FD152E46), - .INIT_5A(256'h425A728BA3BCD4ED051E364F678098B1C9E2FA132B445C758DA5BED6EF072038), - .INIT_5B(256'h314A627B93ACC4DDF50E263F577089A1BAD2EB031C344D657E96AFC7E0F81129), - .INIT_5C(256'h2038516A829BB3CCE4FD152E475F7890A9C1DAF20B233C556D869EB7CFE80019), - .INIT_5D(256'h0E263F577089A1BAD2EB031C354D667E97AFC8E1F9122A435B748DA5BED6EF07), - .INIT_5E(256'hFA132B445D758EA6BFD8F009223A536B849DB5CEE6FF183049617A93ABC4DCF5), - .INIT_5F(256'hE6FE173048617A92ABC4DCF50E263F577089A1BAD3EB041D354E667F98B0C9E2), - .INIT_60(256'hD0E9021A334C647D96AFC7E0F9112A435B748DA5BED7EF082139526A839CB4CD), - .INIT_61(256'hBAD3EC041D364E678098B1CAE3FB142D455E778FA8C1DAF20B243C556E869FB8), - .INIT_62(256'hA3BCD4ED061F375069829AB3CCE4FD162F47607992AAC3DCF40D263F577089A1), - .INIT_63(256'h8BA4BCD5EE071F38516A829BB4CDE5FE173048617A93ABC4DDF60E274059718A), - .INIT_64(256'h728BA4BCD5EE071F38516A839BB4CDE6FF173049627A93ACC5DDF60F28415972), - .INIT_65(256'h58718AA3BBD4ED061F385069829BB4CCE5FE173048617A93ACC4DDF60F284059), - .INIT_66(256'h3E576F88A1BAD3EC041D364F688199B2CBE4FD162E47607992AAC3DCF50E273F), - .INIT_67(256'h223B546D869FB8D0E9021B344D667E97B0C9E2FB142C455E7790A9C1DAF30C25), - .INIT_68(256'h061F38516A839CB5CEE6FF18314A637C95ADC6DFF8112A435C748DA6BFD8F10A), - .INIT_69(256'hEA031C344D667F98B1CAE3FC152E465F7891AAC3DCF50E263F58718AA3BCD5EE), - .INIT_6A(256'hCCE5FE173049627B94ADC6DFF81029425B748DA6BFD8F10A223B546D869FB8D1), - .INIT_6B(256'hAEC7E0F9122B445D768FA8C1DAF30C253E566F88A1BAD3EC051E375069829BB3), - .INIT_6C(256'h90A9C2DBF40D263F587189A2BBD4ED061F38516A839CB5CEE70019324B647D95), - .INIT_6D(256'h718AA3BCD5EE072039526A839CB5CEE70019324B647D96AFC8E1FA132C455E77), - .INIT_6E(256'h516A839CB5CEE70019324B647D96AFC8E1FA132C455E7790A9C2DBF40D263F58), - .INIT_6F(256'h314A637C95AEC7E0F9122B445D768FA8C1DAF30C253E577089A2BBD4ED061F38), - .INIT_70(256'h1029425B748DA6BFD8F10A233C556E87A0B9D3EC051E375069829BB4CDE6FF18), - .INIT_71(256'hEF08213A536C859EB7D0E9021B344D678099B2CBE4FD162F48617A93ACC5DEF7), - .INIT_72(256'hCDE6FF18324B647D96AFC8E1FA132C455E7790A9C2DBF40E274059728BA4BDD6), - .INIT_73(256'hABC4DDF71029425B748DA6BFD8F10A233C556F88A1BAD3EC051E375069829BB4), - .INIT_74(256'h89A2BBD4ED061F39526B849DB6CFE8011A334C657F98B1CAE3FC152E47607992), - .INIT_75(256'h667F99B2CBE4FD162F48617A93ACC6DFF8112A435C758EA7C0D9F30C253E5770), - .INIT_76(256'h435C768FA8C1DAF30C253E57718AA3BCD5EE072039526B859EB7D0E9021B344D), - .INIT_77(256'h2039526B859EB7D0E9021B344D668099B2CBE4FD162F48617B94ADC6DFF8112A), - .INIT_78(256'hFD162F48617A93ACC6DFF8112A435C758EA8C1DAF30C253E577089A3BCD5EE07), - .INIT_79(256'hD9F20B243D577089A2BBD4ED061F39526B849DB6CFE8021B344D667F98B1CAE4), - .INIT_7A(256'hB5CEE7001A334C657E97B0C9E3FC152E47607992ACC5DEF71029425B748EA7C0), - .INIT_7B(256'h91AAC3DCF60F28415A738CA5BFD8F10A233C556E88A1BAD3EC051E37516A839C), - .INIT_7C(256'h6D869FB8D1EB041D364F68819AB4CDE6FF18314A637D96AFC8E1FA132D465F78), - .INIT_7D(256'h49627B94ADC6DFF9122B445D768FA9C2DBF40D263F58728BA4BDD6EF08213B54), - .INIT_7E(256'h243D577089A2BBD4ED072039526B849DB6D0E9021B344D668099B2CBE4FD1630), - .INIT_7F(256'h0019324B657E97B0C9E2FB142E47607992ABC4DEF71029425B748EA7C0D9F20B), - .INIT_A(36'h000000000), - .INIT_B(36'h000000000), - .INIT_FILE("NONE"), - .IS_CLKARDCLK_INVERTED(1'b0), - .IS_CLKBWRCLK_INVERTED(1'b0), - .IS_ENARDEN_INVERTED(1'b0), - .IS_ENBWREN_INVERTED(1'b0), - .IS_RSTRAMARSTRAM_INVERTED(1'b0), - .IS_RSTRAMB_INVERTED(1'b0), - .IS_RSTREGARSTREG_INVERTED(1'b0), - .IS_RSTREGB_INVERTED(1'b0), - .RAM_EXTENSION_A("NONE"), - .RAM_EXTENSION_B("NONE"), - .RAM_MODE("TDP"), - .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), - .READ_WIDTH_A(9), - .READ_WIDTH_B(9), - .RSTREG_PRIORITY_A("REGCE"), - .RSTREG_PRIORITY_B("REGCE"), - .SIM_COLLISION_CHECK("ALL"), - .SIM_DEVICE("7SERIES"), - .SRVAL_A(36'h000000000), - .SRVAL_B(36'h000000000), - .WRITE_MODE_A("WRITE_FIRST"), - .WRITE_MODE_B("WRITE_FIRST"), - .WRITE_WIDTH_A(9), - .WRITE_WIDTH_B(9)) - \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram - (.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}), - .ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}), - .CASCADEINA(1'b0), - .CASCADEINB(1'b0), - .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), - .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), - .CLKARDCLK(clka), - .CLKBWRCLK(clkb), - .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), - .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIPADIP({1'b0,1'b0,1'b0,1'b0}), - .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), - .DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],douta_array[7:0]}), - .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}), - .DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],douta_array[8]}), - .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}), - .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), - .ENARDEN(addra[12]), - .ENBWREN(addrb[12]), - .INJECTDBITERR(1'b0), - .INJECTSBITERR(1'b0), - .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), - .REGCEAREGCE(1'b1), - .REGCEB(1'b1), - .RSTRAMARSTRAM(1'b0), - .RSTRAMB(1'b0), - .RSTREGARSTREG(1'b0), - .RSTREGB(1'b0), - .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), - .WEA({1'b0,1'b0,1'b0,1'b0}), - .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) -module COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized1 - (douta_array, - doutb_array, - ena_array, - enb_array, - clka, - clkb, - addra, - addrb); - output [8:0]douta_array; - output [8:0]doutb_array; - output [0:0]ena_array; - output [0:0]enb_array; - input clka; - input clkb; - input [12:0]addra; - input [12:0]addrb; - - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [8:0]douta_array; - wire [8:0]doutb_array; - wire [0:0]ena_array; - wire [0:0]enb_array; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; - wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; - wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; - wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; - wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; - wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; - - (* box_type = "PRIMITIVE" *) - RAMB36E1 #( - .DOA_REG(1), - .DOB_REG(1), - .EN_ECC_READ("FALSE"), - .EN_ECC_WRITE("FALSE"), - .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_00(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_01(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_02(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_04(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_06(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_07(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_08(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_09(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_0E(256'hFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_0F(256'hFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE), - .INIT_10(256'hFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE), - .INIT_11(256'hFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE), - .INIT_12(256'hFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE), - .INIT_13(256'hFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE), - .INIT_14(256'hFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFEFEFEFEFEFEFEFEFEFEFEFEFE), - .INIT_15(256'hFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFD), - .INIT_16(256'hFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFD), - .INIT_17(256'hFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFD), - .INIT_18(256'hFCFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFD), - .INIT_19(256'hFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFC), - .INIT_1A(256'hFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFC), - .INIT_1B(256'hFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFC), - .INIT_1C(256'hFBFBFBFBFBFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFC), - .INIT_1D(256'hFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFB), - .INIT_1E(256'hFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFB), - .INIT_1F(256'hFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFB), - .INIT_20(256'hFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFBFBFBFBFBFBFBFBFB), - .INIT_21(256'hFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFA), - .INIT_22(256'hFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFA), - .INIT_23(256'hF9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9FAFAFAFAFAFAFAFAFAFAFAFA), - .INIT_24(256'hF9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9), - .INIT_25(256'hF9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9), - .INIT_26(256'hF8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F9F9F9F9F9F9F9), - .INIT_27(256'hF8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8), - .INIT_28(256'hF7F7F7F7F7F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8), - .INIT_29(256'hF7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7), - .INIT_2A(256'hF7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7), - .INIT_2B(256'hF6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F7F7F7F7F7F7F7F7F7F7F7), - .INIT_2C(256'hF6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6), - .INIT_2D(256'hF5F5F5F5F5F5F5F5F5F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6), - .INIT_2E(256'hF5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5), - .INIT_2F(256'hF4F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5), - .INIT_30(256'hF4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4), - .INIT_31(256'hF4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4), - .INIT_32(256'hF3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F4F4F4), - .INIT_33(256'hF3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3), - .INIT_34(256'hF2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F3F3F3F3F3), - .INIT_35(256'hF2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2), - .INIT_36(256'hF1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F2F2F2F2F2), - .INIT_37(256'hF1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1), - .INIT_38(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F1F1), - .INIT_39(256'hEFEFF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0), - .INIT_3A(256'hEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEF), - .INIT_3B(256'hEEEEEEEEEEEEEEEEEEEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEF), - .INIT_3C(256'hEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE), - .INIT_3D(256'hEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE), - .INIT_3E(256'hEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDED), - .INIT_3F(256'hECECECECECECECECECECECECECECECECECECECECECECECECECECEDEDEDEDEDED), - .INIT_40(256'hEBEBEBEBEBECECECECECECECECECECECECECECECECECECECECECECECECECECEC), - .INIT_41(256'hEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEB), - .INIT_42(256'hEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEBEBEBEBEBEBEBEBEBEBEBEBEBEBEB), - .INIT_43(256'hEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEA), - .INIT_44(256'hE9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EAEA), - .INIT_45(256'hE8E8E8E8E8E8E8E8E8E8E8E8E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9), - .INIT_46(256'hE8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8), - .INIT_47(256'hE7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E8E8E8E8), - .INIT_48(256'hE6E6E6E6E6E6E6E6E6E6E6E6E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7), - .INIT_49(256'hE6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6), - .INIT_4A(256'hE5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E6E6E6), - .INIT_4B(256'hE4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5), - .INIT_4C(256'hE3E3E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4), - .INIT_4D(256'hE3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3), - .INIT_4E(256'hE2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E3E3E3E3E3E3E3E3E3E3E3), - .INIT_4F(256'hE1E1E1E1E1E1E1E1E1E1E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2), - .INIT_50(256'hE1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1), - .INIT_51(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E1), - .INIT_52(256'hDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFE0E0E0E0E0E0E0E0E0E0E0E0), - .INIT_53(256'hDEDEDEDEDEDEDEDEDEDEDEDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDF), - .INIT_54(256'hDDDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDE), - .INIT_55(256'hDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD), - .INIT_56(256'hDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDDDDDDDDDDDDDD), - .INIT_57(256'hDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDCDCDCDCDCDCDCDCDCDCDCDCDCDCDC), - .INIT_58(256'hDADADADADADADADADADBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDB), - .INIT_59(256'hD9D9DADADADADADADADADADADADADADADADADADADADADADADADADADADADADADA), - .INIT_5A(256'hD9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9), - .INIT_5B(256'hD8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D9D9D9D9D9), - .INIT_5C(256'hD7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D8D8D8D8D8D8D8D8D8D8D8), - .INIT_5D(256'hD6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7), - .INIT_5E(256'hD5D5D5D5D5D5D5D5D5D5D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6), - .INIT_5F(256'hD4D4D4D4D4D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5), - .INIT_60(256'hD3D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4), - .INIT_61(256'hD3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3), - .INIT_62(256'hD2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D3D3D3D3), - .INIT_63(256'hD1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D2D2D2D2D2D2D2), - .INIT_64(256'hD0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D1D1D1D1D1D1D1D1D1D1D1), - .INIT_65(256'hCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFD0D0D0D0D0D0D0D0D0D0D0D0D0D0), - .INIT_66(256'hCECECECECECECECECECECECECECECECFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCF), - .INIT_67(256'hCDCDCDCDCDCDCDCDCDCDCDCDCDCECECECECECECECECECECECECECECECECECECE), - .INIT_68(256'hCCCCCCCCCCCCCCCCCCCCCCCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCD), - .INIT_69(256'hCBCBCBCBCBCBCBCBCBCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC), - .INIT_6A(256'hCACACACACACACACBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCB), - .INIT_6B(256'hC9C9C9C9C9C9CACACACACACACACACACACACACACACACACACACACACACACACACACA), - .INIT_6C(256'hC8C8C8C8C8C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9), - .INIT_6D(256'hC7C7C7C7C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8), - .INIT_6E(256'hC6C6C6C6C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7), - .INIT_6F(256'hC5C5C5C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6), - .INIT_70(256'hC4C4C4C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5), - .INIT_71(256'hC3C3C3C3C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4), - .INIT_72(256'hC2C2C2C2C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3), - .INIT_73(256'hC1C1C1C1C1C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2), - .INIT_74(256'hC0C0C0C0C0C0C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1), - .INIT_75(256'hBFBFBFBFBFBFBFC0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0), - .INIT_76(256'hBEBEBEBEBEBEBEBEBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBF), - .INIT_77(256'hBDBDBDBDBDBDBDBDBDBDBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBE), - .INIT_78(256'hBCBCBCBCBCBCBCBCBCBCBCBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBD), - .INIT_79(256'hBBBBBBBBBBBBBBBBBBBBBBBBBBBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBC), - .INIT_7A(256'hBABABABABABABABABABABABABABABABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB), - .INIT_7B(256'hB9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9BABABABABABABABABABABABABABA), - .INIT_7C(256'hB8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B9B9B9B9B9B9B9B9B9B9B9B9), - .INIT_7D(256'hB7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B8B8B8B8B8B8B8B8B8), - .INIT_7E(256'hB6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B7B7B7B7B7B7B7), - .INIT_7F(256'hB5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B6B6B6B6), - .INIT_A(36'h000000000), - .INIT_B(36'h000000000), - .INIT_FILE("NONE"), - .IS_CLKARDCLK_INVERTED(1'b0), - .IS_CLKBWRCLK_INVERTED(1'b0), - .IS_ENARDEN_INVERTED(1'b0), - .IS_ENBWREN_INVERTED(1'b0), - .IS_RSTRAMARSTRAM_INVERTED(1'b0), - .IS_RSTRAMB_INVERTED(1'b0), - .IS_RSTREGARSTREG_INVERTED(1'b0), - .IS_RSTREGB_INVERTED(1'b0), - .RAM_EXTENSION_A("NONE"), - .RAM_EXTENSION_B("NONE"), - .RAM_MODE("TDP"), - .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), - .READ_WIDTH_A(9), - .READ_WIDTH_B(9), - .RSTREG_PRIORITY_A("REGCE"), - .RSTREG_PRIORITY_B("REGCE"), - .SIM_COLLISION_CHECK("ALL"), - .SIM_DEVICE("7SERIES"), - .SRVAL_A(36'h000000000), - .SRVAL_B(36'h000000000), - .WRITE_MODE_A("WRITE_FIRST"), - .WRITE_MODE_B("WRITE_FIRST"), - .WRITE_WIDTH_A(9), - .WRITE_WIDTH_B(9)) - \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram - (.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}), - .ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}), - .CASCADEINA(1'b0), - .CASCADEINB(1'b0), - .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), - .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), - .CLKARDCLK(clka), - .CLKBWRCLK(clkb), - .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), - .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIPADIP({1'b0,1'b0,1'b0,1'b0}), - .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), - .DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],douta_array[7:0]}), - .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}), - .DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],douta_array[8]}), - .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}), - .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), - .ENARDEN(ena_array), - .ENBWREN(enb_array), - .INJECTDBITERR(1'b0), - .INJECTSBITERR(1'b0), - .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), - .REGCEAREGCE(1'b1), - .REGCEB(1'b1), - .RSTRAMARSTRAM(1'b0), - .RSTRAMB(1'b0), - .RSTREGARSTREG(1'b0), - .RSTREGB(1'b0), - .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), - .WEA({1'b0,1'b0,1'b0,1'b0}), - .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); - LUT1 #( - .INIT(2'h1)) - \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1 - (.I0(addra[12]), - .O(ena_array)); - LUT1 #( - .INIT(2'h1)) - \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2 - (.I0(addrb[12]), - .O(enb_array)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) -module COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized2 - (douta_array, - doutb_array, - clka, - clkb, - addra, - addrb); - output [8:0]douta_array; - output [8:0]doutb_array; - input clka; - input clkb; - input [12:0]addra; - input [12:0]addrb; - - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [8:0]douta_array; - wire [8:0]doutb_array; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; - wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; - wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; - wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; - wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; - wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; - - (* box_type = "PRIMITIVE" *) - RAMB36E1 #( - .DOA_REG(1), - .DOB_REG(1), - .EN_ECC_READ("FALSE"), - .EN_ECC_WRITE("FALSE"), - .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_00(256'hB3B3B3B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B5), - .INIT_01(256'hB2B2B2B2B2B2B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3), - .INIT_02(256'hB1B1B1B1B1B1B1B1B1B1B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2), - .INIT_03(256'hB0B0B0B0B0B0B0B0B0B0B0B0B0B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1), - .INIT_04(256'hAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFB0B0B0B0B0B0B0B0B0B0B0B0B0B0B0), - .INIT_05(256'hAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAFAFAFAFAFAFAFAFAFAFAF), - .INIT_06(256'hADADADADADADADADADADADADADADADADADADADADADADADADADADAEAEAEAEAEAE), - .INIT_07(256'hABABACACACACACACACACACACACACACACACACACACACACACACACACACACACACADAD), - .INIT_08(256'hAAAAAAAAAAAAAAABABABABABABABABABABABABABABABABABABABABABABABABAB), - .INIT_09(256'hA9A9A9A9A9A9A9A9A9A9A9A9AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA), - .INIT_0A(256'hA8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9), - .INIT_0B(256'hA7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A8A8A8A8A8A8A8A8A8A8A8), - .INIT_0C(256'hA6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A7A7A7A7A7A7), - .INIT_0D(256'hA4A4A4A4A4A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5), - .INIT_0E(256'hA3A3A3A3A3A3A3A3A3A3A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4), - .INIT_0F(256'hA2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3), - .INIT_10(256'hA1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A2A2A2A2A2A2A2A2A2A2A2), - .INIT_11(256'h9FA0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A1A1A1A1A1), - .INIT_12(256'h9E9E9E9E9E9E9E9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F), - .INIT_13(256'h9D9D9D9D9D9D9D9D9D9D9D9D9D9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E), - .INIT_14(256'h9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9D9D9D9D9D9D9D9D9D9D9D9D9D), - .INIT_15(256'h9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9C9C9C9C9C9C9C), - .INIT_16(256'h9999999999999A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A), - .INIT_17(256'h9898989898989898989898989899999999999999999999999999999999999999), - .INIT_18(256'h9797979797979797979797979797979797979798989898989898989898989898), - .INIT_19(256'h9596969696969696969696969696969696969696969696969696979797979797), - .INIT_1A(256'h9494949494949494959595959595959595959595959595959595959595959595), - .INIT_1B(256'h9393939393939393939393939393939494949494949494949494949494949494), - .INIT_1C(256'h9292929292929292929292929292929292929292929293939393939393939393), - .INIT_1D(256'h9090909091919191919191919191919191919191919191919191919191929292), - .INIT_1E(256'h8F8F8F8F8F8F8F8F8F8F8F8F9090909090909090909090909090909090909090), - .INIT_1F(256'h8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8F8F8F8F8F8F8F8F8F8F8F8F8F), - .INIT_20(256'h8C8C8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8E8E8E8E8E), - .INIT_21(256'h8B8B8B8B8B8B8B8B8B8B8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C), - .INIT_22(256'h8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B), - .INIT_23(256'h888989898989898989898989898989898989898989898989898A8A8A8A8A8A8A), - .INIT_24(256'h8787878787878787878888888888888888888888888888888888888888888888), - .INIT_25(256'h8686868686868686868686868686868686878787878787878787878787878787), - .INIT_26(256'h8485858585858585858585858585858585858585858585858586868686868686), - .INIT_27(256'h8383838383838383838484848484848484848484848484848484848484848484), - .INIT_28(256'h8282828282828282828282828282828282828383838383838383838383838383), - .INIT_29(256'h8080818181818181818181818181818181818181818181818181828282828282), - .INIT_2A(256'h7F7F7F7F7F7F7F7F7F7F7F808080808080808080808080808080808080808080), - .INIT_2B(256'h7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7F7F7F7F7F7F7F7F7F7F7F7F7F), - .INIT_2C(256'h7C7C7C7C7C7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7E7E7E7E), - .INIT_2D(256'h7B7B7B7B7B7B7B7B7B7B7B7B7B7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C), - .INIT_2E(256'h7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7B7B7B7B7B7B7B7B7B7B), - .INIT_2F(256'h787878787878787879797979797979797979797979797979797979797979797A), - .INIT_30(256'h7777777777777777777777777777777777787878787878787878787878787878), - .INIT_31(256'h7575757676767676767676767676767676767676767676767676777777777777), - .INIT_32(256'h7474747474747474747474747575757575757575757575757575757575757575), - .INIT_33(256'h7373737373737373737373737373737373737373737474747474747474747474), - .INIT_34(256'h7171717171717172727272727272727272727272727272727272727272727373), - .INIT_35(256'h7070707070707070707070707070707071717171717171717171717171717171), - .INIT_36(256'h6E6E6E6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F707070707070), - .INIT_37(256'h6D6D6D6D6D6D6D6D6D6D6D6D6D6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E), - .INIT_38(256'h6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6D6D6D6D6D6D6D6D6D6D), - .INIT_39(256'h6A6A6A6A6A6A6A6A6A6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6C), - .INIT_3A(256'h696969696969696969696969696969696969696A6A6A6A6A6A6A6A6A6A6A6A6A), - .INIT_3B(256'h6767676767676868686868686868686868686868686868686868686869696969), - .INIT_3C(256'h6666666666666666666666666666666667676767676767676767676767676767), - .INIT_3D(256'h6464646565656565656565656565656565656565656565656566666666666666), - .INIT_3E(256'h6363636363636363636363636364646464646464646464646464646464646464), - .INIT_3F(256'h6162626262626262626262626262626262626262626262636363636363636363), - .INIT_40(256'h6060606060606060606060616161616161616161616161616161616161616161), - .INIT_41(256'h5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F6060606060606060606060), - .INIT_42(256'h5D5D5D5D5D5D5D5D5D5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5F), - .INIT_43(256'h5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5D5D5D5D5D5D5D5D5D5D5D5D5D), - .INIT_44(256'h5A5A5A5A5A5A5A5A5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5C5C5C), - .INIT_45(256'h5959595959595959595959595959595959595A5A5A5A5A5A5A5A5A5A5A5A5A5A), - .INIT_46(256'h5757575757575858585858585858585858585858585858585858585859595959), - .INIT_47(256'h5656565656565656565656565656565656575757575757575757575757575757), - .INIT_48(256'h5454545454555555555555555555555555555555555555555555555656565656), - .INIT_49(256'h5353535353535353535353535353535354545454545454545454545454545454), - .INIT_4A(256'h5151515151525252525252525252525252525252525252525252535353535353), - .INIT_4B(256'h5050505050505050505050505050505151515151515151515151515151515151), - .INIT_4C(256'h4E4E4E4E4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F505050505050), - .INIT_4D(256'h4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E), - .INIT_4E(256'h4B4B4B4B4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4D4D4D4D4D4D), - .INIT_4F(256'h4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B), - .INIT_50(256'h48484848494949494949494949494949494949494949494949494A4A4A4A4A4A), - .INIT_51(256'h4747474747474747474747474747474848484848484848484848484848484848), - .INIT_52(256'h4545454545464646464646464646464646464646464646464646474747474747), - .INIT_53(256'h4444444444444444444444444444444445454545454545454545454545454545), - .INIT_54(256'h4242424242434343434343434343434343434343434343434343444444444444), - .INIT_55(256'h4141414141414141414141414141414142424242424242424242424242424242), - .INIT_56(256'h3F3F3F3F3F3F4040404040404040404040404040404040404040404141414141), - .INIT_57(256'h3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F), - .INIT_58(256'h3C3C3C3C3C3C3C3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3E3E3E3E), - .INIT_59(256'h3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3C3C3C3C3C3C3C3C3C3C3C3C3C3C), - .INIT_5A(256'h39393939393939393A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3B3B3B), - .INIT_5B(256'h3838383838383838383838383838383838383839393939393939393939393939), - .INIT_5C(256'h3636363636363636363637373737373737373737373737373737373737373838), - .INIT_5D(256'h3535353535353535353535353535353535353535353636363636363636363636), - .INIT_5E(256'h3333333333333333333333343434343434343434343434343434343434343434), - .INIT_5F(256'h3131323232323232323232323232323232323232323233333333333333333333), - .INIT_60(256'h3030303030303030303030303031313131313131313131313131313131313131), - .INIT_61(256'h2E2E2E2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F3030303030303030), - .INIT_62(256'h2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E), - .INIT_63(256'h2B2B2B2B2B2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2D2D2D2D2D2D), - .INIT_64(256'h2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B), - .INIT_65(256'h282828282828282929292929292929292929292929292929292929292A2A2A2A), - .INIT_66(256'h2727272727272727272727272727272727272728282828282828282828282828), - .INIT_67(256'h2525252525252525252626262626262626262626262626262626262626262727), - .INIT_68(256'h2424242424242424242424242424242424242424242525252525252525252525), - .INIT_69(256'h2222222222222222222222222323232323232323232323232323232323232323), - .INIT_6A(256'h2020202121212121212121212121212121212121212121222222222222222222), - .INIT_6B(256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F202020202020202020202020202020202020), - .INIT_6C(256'h1D1D1D1D1D1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1F1F1F1F1F1F1F), - .INIT_6D(256'h1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D), - .INIT_6E(256'h1A1A1A1A1A1A1A1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1C1C1C1C), - .INIT_6F(256'h191919191919191919191919191919191919191A1A1A1A1A1A1A1A1A1A1A1A1A), - .INIT_70(256'h1717171717171717171718181818181818181818181818181818181818181819), - .INIT_71(256'h1516161616161616161616161616161616161616161617171717171717171717), - .INIT_72(256'h1414141414141414141414141415151515151515151515151515151515151515), - .INIT_73(256'h1212121213131313131313131313131313131313131313131414141414141414), - .INIT_74(256'h1111111111111111111111111111111212121212121212121212121212121212), - .INIT_75(256'h0F0F0F0F0F0F0F10101010101010101010101010101010101010101111111111), - .INIT_76(256'h0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0F0F0F0F0F0F0F0F0F0F0F0F0F0F), - .INIT_77(256'h0C0C0C0C0C0C0C0C0C0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0E0E), - .INIT_78(256'h0A0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0C0C0C0C0C0C0C0C0C0C0C), - .INIT_79(256'h0909090909090909090909090A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A), - .INIT_7A(256'h0707070808080808080808080808080808080808080808080909090909090909), - .INIT_7B(256'h0606060606060606060606060606060707070707070707070707070707070707), - .INIT_7C(256'h0404040404040505050505050505050505050505050505050505050606060606), - .INIT_7D(256'h0303030303030303030303030303030303030404040404040404040404040404), - .INIT_7E(256'h0101010101010101010202020202020202020202020202020202020202020303), - .INIT_7F(256'h0000000000000000000000000000000000000000000101010101010101010101), - .INIT_A(36'h000000000), - .INIT_B(36'h000000000), - .INIT_FILE("NONE"), - .IS_CLKARDCLK_INVERTED(1'b0), - .IS_CLKBWRCLK_INVERTED(1'b0), - .IS_ENARDEN_INVERTED(1'b0), - .IS_ENBWREN_INVERTED(1'b0), - .IS_RSTRAMARSTRAM_INVERTED(1'b0), - .IS_RSTRAMB_INVERTED(1'b0), - .IS_RSTREGARSTREG_INVERTED(1'b0), - .IS_RSTREGB_INVERTED(1'b0), - .RAM_EXTENSION_A("NONE"), - .RAM_EXTENSION_B("NONE"), - .RAM_MODE("TDP"), - .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), - .READ_WIDTH_A(9), - .READ_WIDTH_B(9), - .RSTREG_PRIORITY_A("REGCE"), - .RSTREG_PRIORITY_B("REGCE"), - .SIM_COLLISION_CHECK("ALL"), - .SIM_DEVICE("7SERIES"), - .SRVAL_A(36'h000000000), - .SRVAL_B(36'h000000000), - .WRITE_MODE_A("WRITE_FIRST"), - .WRITE_MODE_B("WRITE_FIRST"), - .WRITE_WIDTH_A(9), - .WRITE_WIDTH_B(9)) - \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram - (.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}), - .ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}), - .CASCADEINA(1'b0), - .CASCADEINB(1'b0), - .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), - .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), - .CLKARDCLK(clka), - .CLKBWRCLK(clkb), - .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), - .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIPADIP({1'b0,1'b0,1'b0,1'b0}), - .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), - .DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],douta_array[7:0]}), - .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}), - .DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],douta_array[8]}), - .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}), - .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), - .ENARDEN(addra[12]), - .ENBWREN(addrb[12]), - .INJECTDBITERR(1'b0), - .INJECTSBITERR(1'b0), - .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), - .REGCEAREGCE(1'b1), - .REGCEB(1'b1), - .RSTRAMARSTRAM(1'b0), - .RSTRAMB(1'b0), - .RSTREGARSTREG(1'b0), - .RSTREGB(1'b0), - .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), - .WEA({1'b0,1'b0,1'b0,1'b0}), - .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_top" *) -module COSLUT_10_16bit_blk_mem_gen_top - (douta, - doutb, - clka, - clkb, - addra, - addrb); - output [17:0]douta; - output [17:0]doutb; - input clka; - input clkb; - input [12:0]addra; - input [12:0]addrb; - - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [17:0]douta; - wire [17:0]doutb; - - COSLUT_10_16bit_blk_mem_gen_generic_cstr \valid.cstr - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .douta(douta), - .doutb(doutb)); -endmodule - -(* C_ADDRA_WIDTH = "13" *) (* C_ADDRB_WIDTH = "13" *) (* C_ALGORITHM = "1" *) -(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *) -(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "0" *) -(* C_COUNT_36K_BRAM = "4" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *) -(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *) -(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *) -(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *) -(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 9.414399 mW" *) -(* C_FAMILY = "kintex7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *) -(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *) -(* C_HAS_MEM_OUTPUT_REGS_B = "1" *) (* C_HAS_MUX_OUTPUT_REGS_A = "1" *) (* C_HAS_MUX_OUTPUT_REGS_B = "1" *) -(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *) -(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) -(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "COSLUT_10_16bit.mem" *) -(* C_INIT_FILE_NAME = "COSLUT_10_16bit.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *) -(* C_MEM_TYPE = "4" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *) -(* C_READ_DEPTH_A = "8192" *) (* C_READ_DEPTH_B = "8192" *) (* C_READ_LATENCY_A = "1" *) -(* C_READ_LATENCY_B = "1" *) (* C_READ_WIDTH_A = "18" *) (* C_READ_WIDTH_B = "18" *) -(* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *) -(* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *) -(* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *) -(* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *) -(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "8192" *) -(* C_WRITE_DEPTH_B = "8192" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) -(* C_WRITE_WIDTH_A = "18" *) (* C_WRITE_WIDTH_B = "18" *) (* C_XDEVICEFAMILY = "kintex7" *) -(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3" *) (* downgradeipidentifiedwarnings = "yes" *) -module COSLUT_10_16bit_blk_mem_gen_v8_4_3 - (clka, - rsta, - ena, - regcea, - wea, - addra, - dina, - douta, - clkb, - rstb, - enb, - regceb, - web, - addrb, - dinb, - doutb, - injectsbiterr, - injectdbiterr, - eccpipece, - sbiterr, - dbiterr, - rdaddrecc, - sleep, - deepsleep, - shutdown, - rsta_busy, - rstb_busy, - s_aclk, - s_aresetn, - s_axi_awid, - s_axi_awaddr, - s_axi_awlen, - s_axi_awsize, - s_axi_awburst, - s_axi_awvalid, - s_axi_awready, - s_axi_wdata, - s_axi_wstrb, - s_axi_wlast, - s_axi_wvalid, - s_axi_wready, - s_axi_bid, - s_axi_bresp, - s_axi_bvalid, - s_axi_bready, - s_axi_arid, - s_axi_araddr, - s_axi_arlen, - s_axi_arsize, - s_axi_arburst, - s_axi_arvalid, - s_axi_arready, - s_axi_rid, - s_axi_rdata, - s_axi_rresp, - s_axi_rlast, - s_axi_rvalid, - s_axi_rready, - s_axi_injectsbiterr, - s_axi_injectdbiterr, - s_axi_sbiterr, - s_axi_dbiterr, - s_axi_rdaddrecc); - input clka; - input rsta; - input ena; - input regcea; - input [0:0]wea; - input [12:0]addra; - input [17:0]dina; - output [17:0]douta; - input clkb; - input rstb; - input enb; - input regceb; - input [0:0]web; - input [12:0]addrb; - input [17:0]dinb; - output [17:0]doutb; - input injectsbiterr; - input injectdbiterr; - input eccpipece; - output sbiterr; - output dbiterr; - output [12:0]rdaddrecc; - input sleep; - input deepsleep; - input shutdown; - output rsta_busy; - output rstb_busy; - input s_aclk; - input s_aresetn; - input [3:0]s_axi_awid; - input [31:0]s_axi_awaddr; - input [7:0]s_axi_awlen; - input [2:0]s_axi_awsize; - input [1:0]s_axi_awburst; - input s_axi_awvalid; - output s_axi_awready; - input [17:0]s_axi_wdata; - input [0:0]s_axi_wstrb; - input s_axi_wlast; - input s_axi_wvalid; - output s_axi_wready; - output [3:0]s_axi_bid; - output [1:0]s_axi_bresp; - output s_axi_bvalid; - input s_axi_bready; - input [3:0]s_axi_arid; - input [31:0]s_axi_araddr; - input [7:0]s_axi_arlen; - input [2:0]s_axi_arsize; - input [1:0]s_axi_arburst; - input s_axi_arvalid; - output s_axi_arready; - output [3:0]s_axi_rid; - output [17:0]s_axi_rdata; - output [1:0]s_axi_rresp; - output s_axi_rlast; - output s_axi_rvalid; - input s_axi_rready; - input s_axi_injectsbiterr; - input s_axi_injectdbiterr; - output s_axi_sbiterr; - output s_axi_dbiterr; - output [12:0]s_axi_rdaddrecc; - - wire \ ; - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [17:0]douta; - wire [17:0]doutb; - - assign dbiterr = \ ; - assign rdaddrecc[12] = \ ; - assign rdaddrecc[11] = \ ; - assign rdaddrecc[10] = \ ; - assign rdaddrecc[9] = \ ; - assign rdaddrecc[8] = \ ; - assign rdaddrecc[7] = \ ; - assign rdaddrecc[6] = \ ; - assign rdaddrecc[5] = \ ; - assign rdaddrecc[4] = \ ; - assign rdaddrecc[3] = \ ; - assign rdaddrecc[2] = \ ; - assign rdaddrecc[1] = \ ; - assign rdaddrecc[0] = \ ; - assign rsta_busy = \ ; - assign rstb_busy = \ ; - assign s_axi_arready = \ ; - assign s_axi_awready = \ ; - assign s_axi_bid[3] = \ ; - assign s_axi_bid[2] = \ ; - assign s_axi_bid[1] = \ ; - assign s_axi_bid[0] = \ ; - assign s_axi_bresp[1] = \ ; - assign s_axi_bresp[0] = \ ; - assign s_axi_bvalid = \ ; - assign s_axi_dbiterr = \ ; - assign s_axi_rdaddrecc[12] = \ ; - assign s_axi_rdaddrecc[11] = \ ; - assign s_axi_rdaddrecc[10] = \ ; - assign s_axi_rdaddrecc[9] = \ ; - assign s_axi_rdaddrecc[8] = \ ; - assign s_axi_rdaddrecc[7] = \ ; - assign s_axi_rdaddrecc[6] = \ ; - assign s_axi_rdaddrecc[5] = \ ; - assign s_axi_rdaddrecc[4] = \ ; - assign s_axi_rdaddrecc[3] = \ ; - assign s_axi_rdaddrecc[2] = \ ; - assign s_axi_rdaddrecc[1] = \ ; - assign s_axi_rdaddrecc[0] = \ ; - assign s_axi_rdata[17] = \ ; - assign s_axi_rdata[16] = \ ; - assign s_axi_rdata[15] = \ ; - assign s_axi_rdata[14] = \ ; - assign s_axi_rdata[13] = \ ; - assign s_axi_rdata[12] = \ ; - assign s_axi_rdata[11] = \ ; - assign s_axi_rdata[10] = \ ; - assign s_axi_rdata[9] = \ ; - assign s_axi_rdata[8] = \ ; - assign s_axi_rdata[7] = \ ; - assign s_axi_rdata[6] = \ ; - assign s_axi_rdata[5] = \ ; - assign s_axi_rdata[4] = \ ; - assign s_axi_rdata[3] = \ ; - assign s_axi_rdata[2] = \ ; - assign s_axi_rdata[1] = \ ; - assign s_axi_rdata[0] = \ ; - assign s_axi_rid[3] = \ ; - assign s_axi_rid[2] = \ ; - assign s_axi_rid[1] = \ ; - assign s_axi_rid[0] = \ ; - assign s_axi_rlast = \ ; - assign s_axi_rresp[1] = \ ; - assign s_axi_rresp[0] = \ ; - assign s_axi_rvalid = \ ; - assign s_axi_sbiterr = \ ; - assign s_axi_wready = \ ; - assign sbiterr = \ ; - GND GND - (.G(\ )); - COSLUT_10_16bit_blk_mem_gen_v8_4_3_synth inst_blk_mem_gen - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .douta(douta), - .doutb(doutb)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3_synth" *) -module COSLUT_10_16bit_blk_mem_gen_v8_4_3_synth - (douta, - doutb, - clka, - clkb, - addra, - addrb); - output [17:0]douta; - output [17:0]doutb; - input clka; - input clkb; - input [12:0]addra; - input [12:0]addrb; - - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [17:0]douta; - wire [17:0]doutb; - - COSLUT_10_16bit_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .douta(douta), - .doutb(doutb)); -endmodule -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit_sim_netlist.vhdl deleted file mode 100644 index 117bed13..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit_sim_netlist.vhdl +++ /dev/null @@ -1,2784 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:34:22 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_sim_netlist.vhdl --- Design : COSLUT_10_16bit --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity COSLUT_10_16bit_blk_mem_gen_mux is - port ( - douta : out STD_LOGIC_VECTOR ( 17 downto 0 ); - addra : in STD_LOGIC_VECTOR ( 0 to 0 ); - clka : in STD_LOGIC; - douta_array : in STD_LOGIC_VECTOR ( 35 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of COSLUT_10_16bit_blk_mem_gen_mux : entity is "blk_mem_gen_mux"; -end COSLUT_10_16bit_blk_mem_gen_mux; - -architecture STRUCTURE of COSLUT_10_16bit_blk_mem_gen_mux is - signal dout_pipe : STD_LOGIC_VECTOR ( 17 downto 0 ); - signal sel_pipe : STD_LOGIC; - signal sel_pipe_d1 : STD_LOGIC; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[0]_i_1\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[10]_i_1\ : label is "soft_lutpair5"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[11]_i_1\ : label is "soft_lutpair5"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[12]_i_1\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[13]_i_1\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[14]_i_1\ : label is "soft_lutpair7"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[15]_i_1\ : label is "soft_lutpair7"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[16]_i_1\ : label is "soft_lutpair8"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[17]_i_1\ : label is "soft_lutpair8"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[1]_i_1\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[2]_i_1\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[3]_i_1\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[4]_i_1\ : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[5]_i_1\ : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[6]_i_1\ : label is "soft_lutpair3"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[7]_i_1\ : label is "soft_lutpair3"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[8]_i_1\ : label is "soft_lutpair4"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[9]_i_1\ : label is "soft_lutpair4"; -begin -\no_softecc_gmuxr.ce_pri.dout_i[0]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(18), - I1 => sel_pipe_d1, - I2 => douta_array(0), - O => dout_pipe(0) - ); -\no_softecc_gmuxr.ce_pri.dout_i[10]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(28), - I1 => sel_pipe_d1, - I2 => douta_array(10), - O => dout_pipe(10) - ); -\no_softecc_gmuxr.ce_pri.dout_i[11]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(29), - I1 => sel_pipe_d1, - I2 => douta_array(11), - O => dout_pipe(11) - ); -\no_softecc_gmuxr.ce_pri.dout_i[12]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(30), - I1 => sel_pipe_d1, - I2 => douta_array(12), - O => dout_pipe(12) - ); -\no_softecc_gmuxr.ce_pri.dout_i[13]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(31), - I1 => sel_pipe_d1, - I2 => douta_array(13), - O => dout_pipe(13) - ); -\no_softecc_gmuxr.ce_pri.dout_i[14]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(32), - I1 => sel_pipe_d1, - I2 => douta_array(14), - O => dout_pipe(14) - ); -\no_softecc_gmuxr.ce_pri.dout_i[15]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(33), - I1 => sel_pipe_d1, - I2 => douta_array(15), - O => dout_pipe(15) - ); -\no_softecc_gmuxr.ce_pri.dout_i[16]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(34), - I1 => sel_pipe_d1, - I2 => douta_array(16), - O => dout_pipe(16) - ); -\no_softecc_gmuxr.ce_pri.dout_i[17]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(35), - I1 => sel_pipe_d1, - I2 => douta_array(17), - O => dout_pipe(17) - ); -\no_softecc_gmuxr.ce_pri.dout_i[1]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(19), - I1 => sel_pipe_d1, - I2 => douta_array(1), - O => dout_pipe(1) - ); -\no_softecc_gmuxr.ce_pri.dout_i[2]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(20), - I1 => sel_pipe_d1, - I2 => douta_array(2), - O => dout_pipe(2) - ); -\no_softecc_gmuxr.ce_pri.dout_i[3]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(21), - I1 => sel_pipe_d1, - I2 => douta_array(3), - O => dout_pipe(3) - ); -\no_softecc_gmuxr.ce_pri.dout_i[4]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(22), - I1 => sel_pipe_d1, - I2 => douta_array(4), - O => dout_pipe(4) - ); -\no_softecc_gmuxr.ce_pri.dout_i[5]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(23), - I1 => sel_pipe_d1, - I2 => douta_array(5), - O => dout_pipe(5) - ); -\no_softecc_gmuxr.ce_pri.dout_i[6]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(24), - I1 => sel_pipe_d1, - I2 => douta_array(6), - O => dout_pipe(6) - ); -\no_softecc_gmuxr.ce_pri.dout_i[7]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(25), - I1 => sel_pipe_d1, - I2 => douta_array(7), - O => dout_pipe(7) - ); -\no_softecc_gmuxr.ce_pri.dout_i[8]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(26), - I1 => sel_pipe_d1, - I2 => douta_array(8), - O => dout_pipe(8) - ); -\no_softecc_gmuxr.ce_pri.dout_i[9]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(27), - I1 => sel_pipe_d1, - I2 => douta_array(9), - O => dout_pipe(9) - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(0), - Q => douta(0), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[10]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(10), - Q => douta(10), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[11]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(11), - Q => douta(11), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[12]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(12), - Q => douta(12), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[13]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(13), - Q => douta(13), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[14]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(14), - Q => douta(14), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[15]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(15), - Q => douta(15), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[16]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(16), - Q => douta(16), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[17]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(17), - Q => douta(17), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(1), - Q => douta(1), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(2), - Q => douta(2), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(3), - Q => douta(3), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(4), - Q => douta(4), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(5), - Q => douta(5), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(6), - Q => douta(6), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(7), - Q => douta(7), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(8), - Q => douta(8), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[9]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(9), - Q => douta(9), - R => '0' - ); -\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => sel_pipe, - Q => sel_pipe_d1, - R => '0' - ); -\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => addra(0), - Q => sel_pipe, - R => '0' - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \COSLUT_10_16bit_blk_mem_gen_mux__parameterized0\ is - port ( - doutb : out STD_LOGIC_VECTOR ( 17 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 0 to 0 ); - clkb : in STD_LOGIC; - doutb_array : in STD_LOGIC_VECTOR ( 35 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \COSLUT_10_16bit_blk_mem_gen_mux__parameterized0\ : entity is "blk_mem_gen_mux"; -end \COSLUT_10_16bit_blk_mem_gen_mux__parameterized0\; - -architecture STRUCTURE of \COSLUT_10_16bit_blk_mem_gen_mux__parameterized0\ is - signal \no_softecc_gmuxr.ce_pri.dout_i[0]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[10]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[11]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[12]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[13]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[14]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[15]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[16]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[17]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[1]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[2]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[3]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[4]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[5]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[6]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[7]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[8]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[9]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\ : STD_LOGIC; - signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\ : STD_LOGIC; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[0]_i_1\ : label is "soft_lutpair9"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[10]_i_1\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[11]_i_1\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[12]_i_1\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[13]_i_1\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[14]_i_1\ : label is "soft_lutpair16"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[15]_i_1\ : label is "soft_lutpair16"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[16]_i_1\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[17]_i_1\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[1]_i_1\ : label is "soft_lutpair9"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[2]_i_1\ : label is "soft_lutpair10"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[3]_i_1\ : label is "soft_lutpair10"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[4]_i_1\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[5]_i_1\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[6]_i_1\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[7]_i_1\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[8]_i_1\ : label is "soft_lutpair13"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[9]_i_1\ : label is "soft_lutpair13"; -begin -\no_softecc_gmuxr.ce_pri.dout_i[0]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(18), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(0), - O => \no_softecc_gmuxr.ce_pri.dout_i[0]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[10]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(28), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(10), - O => \no_softecc_gmuxr.ce_pri.dout_i[10]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[11]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(29), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(11), - O => \no_softecc_gmuxr.ce_pri.dout_i[11]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[12]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(30), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(12), - O => \no_softecc_gmuxr.ce_pri.dout_i[12]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[13]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(31), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(13), - O => \no_softecc_gmuxr.ce_pri.dout_i[13]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[14]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(32), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(14), - O => \no_softecc_gmuxr.ce_pri.dout_i[14]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[15]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(33), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(15), - O => \no_softecc_gmuxr.ce_pri.dout_i[15]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[16]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(34), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(16), - O => \no_softecc_gmuxr.ce_pri.dout_i[16]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[17]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(35), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(17), - O => \no_softecc_gmuxr.ce_pri.dout_i[17]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[1]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(19), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(1), - O => \no_softecc_gmuxr.ce_pri.dout_i[1]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[2]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(20), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(2), - O => \no_softecc_gmuxr.ce_pri.dout_i[2]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[3]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(21), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(3), - O => \no_softecc_gmuxr.ce_pri.dout_i[3]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[4]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(22), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(4), - O => \no_softecc_gmuxr.ce_pri.dout_i[4]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[5]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(23), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(5), - O => \no_softecc_gmuxr.ce_pri.dout_i[5]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[6]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(24), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(6), - O => \no_softecc_gmuxr.ce_pri.dout_i[6]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[7]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(25), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(7), - O => \no_softecc_gmuxr.ce_pri.dout_i[7]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[8]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(26), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(8), - O => \no_softecc_gmuxr.ce_pri.dout_i[8]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[9]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(27), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(9), - O => \no_softecc_gmuxr.ce_pri.dout_i[9]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[0]_i_1_n_0\, - Q => doutb(0), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[10]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[10]_i_1_n_0\, - Q => doutb(10), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[11]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[11]_i_1_n_0\, - Q => doutb(11), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[12]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[12]_i_1_n_0\, - Q => doutb(12), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[13]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[13]_i_1_n_0\, - Q => doutb(13), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[14]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[14]_i_1_n_0\, - Q => doutb(14), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[15]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[15]_i_1_n_0\, - Q => doutb(15), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[16]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[16]_i_1_n_0\, - Q => doutb(16), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[17]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[17]_i_1_n_0\, - Q => doutb(17), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[1]_i_1_n_0\, - Q => doutb(1), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[2]_i_1_n_0\, - Q => doutb(2), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[3]_i_1_n_0\, - Q => doutb(3), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[4]_i_1_n_0\, - Q => doutb(4), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[5]_i_1_n_0\, - Q => doutb(5), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[6]_i_1_n_0\, - Q => doutb(6), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[7]_i_1_n_0\, - Q => doutb(7), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[8]_i_1_n_0\, - Q => doutb(8), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[9]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[9]_i_1_n_0\, - Q => doutb(9), - R => '0' - ); -\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\, - Q => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - R => '0' - ); -\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => addrb(0), - Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\, - R => '0' - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init is - port ( - douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - doutb_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena_array : in STD_LOGIC_VECTOR ( 0 to 0 ); - enb_array : in STD_LOGIC_VECTOR ( 0 to 0 ); - addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 11 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; -end COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init; - -architecture STRUCTURE of COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init is - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); - attribute box_type : string; - attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; -begin -\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 - generic map( - DOA_REG => 1, - DOB_REG => 1, - EN_ECC_READ => false, - EN_ECC_WRITE => false, - INITP_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INITP_01 => X"FFFFFFFFFFFFE0000000000000000000000000000000003FFFFFFFFFFFFFFFFF", - INITP_02 => X"0000000003FFFFFFFFFFFFFFFFFFE0000000000000000000001FFFFFFFFFFFFF", - INITP_03 => X"00000000000FFFFFFFFFFFFFF800000000000000FFFFFFFFFFFFFFFF80000000", - INITP_04 => X"0003FFFFFFFFFF800000000003FFFFFFFFFFF0000000000007FFFFFFFFFFFE00", - INITP_05 => X"8000000007FFFFFFFF8000000001FFFFFFFFF8000000000FFFFFFFFFF8000000", - INITP_06 => X"0000000FFFFFFFE00000001FFFFFFFE00000001FFFFFFFF800000001FFFFFFFF", - INITP_07 => X"FFFFFFC0000007FFFFFF0000000FFFFFFF80000007FFFFFFC0000000FFFFFFFC", - INITP_08 => X"0FFFFFF000000FFFFFF0000007FFFFFC000001FFFFFF8000001FFFFFF8000001", - INITP_09 => X"FFC00001FFFFF800000FFFFFC00000FFFFFE000003FFFFF800000FFFFFF00000", - INITP_0A => X"FFFF800007FFFF800007FFFF800003FFFFE00001FFFFF000007FFFFE00000FFF", - INITP_0B => X"F80000FFFFC00007FFFE00003FFFF80000FFFFE00001FFFFC00007FFFF800007", - INITP_0C => X"FFF80003FFFE00007FFFC0000FFFF80001FFFF80001FFFF00001FFFF80001FFF", - INITP_0D => X"E0000FFFF0000FFFF00007FFF80007FFFC0001FFFE0000FFFF80003FFFE0000F", - INITP_0E => X"FFC0007FFF0001FFFE0003FFFC0007FFF8000FFFF0000FFFF0000FFFE0001FFF", - INITP_0F => X"0003FFF0001FFF8000FFFE0007FFF0001FFFC000FFFE0003FFF8000FFFE0003F", - INIT_00 => X"FDFDFDFDFDFDFDFEFEFEFEFEFEFEFEFEFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_01 => X"F5F6F6F6F7F7F7F7F8F8F8F8F9F9F9F9FAFAFAFAFBFBFBFBFBFCFCFCFCFCFCFD", - INIT_02 => X"E9EAEAEBEBEBECECEDEDEEEEEEEFEFF0F0F0F1F1F1F2F2F3F3F3F4F4F4F5F5F5", - INIT_03 => X"D8D9D9DADBDBDCDCDDDDDEDFDFE0E0E1E1E2E2E3E3E4E4E5E5E6E6E7E7E8E8E9", - INIT_04 => X"C2C3C4C4C5C6C7C7C8C9C9CACBCCCCCDCECECFD0D0D1D2D2D3D4D4D5D6D6D7D8", - INIT_05 => X"A7A8A9AAABACADADAEAFB0B1B2B3B3B4B5B6B7B8B9B9BABBBCBDBDBEBFC0C1C1", - INIT_06 => X"8788898A8B8C8E8F909192939495969798999A9B9C9D9E9FA0A1A1A2A3A4A5A6", - INIT_07 => X"6264656667686A6B6C6D6E7071727374757778797A7B7C7D7E80818283848586", - INIT_08 => X"393A3B3D3E3F414243454647494A4B4D4E4F515253555657585A5B5C5D5F6061", - INIT_09 => X"0A0B0D0E101113141617191A1C1D1F202223252628292A2C2D2F303233343637", - INIT_0A => X"D6D8DADBDDDFE0E2E4E5E7E8EAECEDEFF1F2F4F5F7F9FAFCFDFF010204050708", - INIT_0B => X"9E9FA1A3A5A7A9AAACAEB0B2B3B5B7B9BBBCBEC0C2C3C5C7C9CACCCECFD1D3D4", - INIT_0C => X"60626466686A6C6E70727476787A7C7E7F81838587898B8D8F91929496989A9C", - INIT_0D => X"1E20222426282B2D2F31333537393B3D40424446484A4C4E50525456585A5C5E", - INIT_0E => X"D6D9DBDDE0E2E4E6E9EBEDEFF2F4F6F8FBFDFF010406080A0C0F11131517191C", - INIT_0F => X"8A8D8F929496999B9EA0A3A5A7AAACAFB1B3B6B8BABDBFC1C4C6C8CBCDCFD2D4", - INIT_10 => X"393C3E414346494B4E505355585B5D606265676A6C6F717476797B7E80838588", - INIT_11 => X"E3E6E8EBEEF1F3F6F9FCFE010407090C0F111417191C1F212427292C2F313436", - INIT_12 => X"888B8E919497999C9FA2A5A8ABAEB0B3B6B9BCBFC1C4C7CACDCFD2D5D8DBDDE0", - INIT_13 => X"282B2E3134373A3E4144474A4D505356595C5F6265686B6E707376797C7F8285", - INIT_14 => X"C3C7CACDD0D3D7DADDE0E3E7EAEDF0F3F6F9FD000306090C0F1216191C1F2225", - INIT_15 => X"5A5D6064676B6E7175787B7F8285898C8F9296999CA0A3A6A9ADB0B3B6BABDC0", - INIT_16 => X"EBEFF2F6F9FD0004070B0E1215191C2023262A2D3134383B3F4245494C505356", - INIT_17 => X"787B7F83868A8E9195999CA0A4A7ABAEB2B6B9BDC0C4C8CBCFD2D6D9DDE1E4E8", - INIT_18 => X"FF03070B0F12161A1E2225292D3135383C4044474B4F53565A5E6265696D7074", - INIT_19 => X"82868A8E92969A9EA2A6AAAEB2B6BABDC1C5C9CDD1D5D9DDE1E4E8ECF0F4F8FC", - INIT_1A => X"0004080C1115191D2125292D31363A3E42464A4E52565A5E62666A6E72767A7E", - INIT_1B => X"797D82868A8F93979BA0A4A8ACB1B5B9BDC1C6CACED2D6DBDFE3E7EBEFF4F8FC", - INIT_1C => X"EDF2F6FBFF04080C11151A1E22272B2F34383D41454A4E52575B5F64686C7175", - INIT_1D => X"5D61666A6F74787D81868A8F93989DA1A6AAAFB3B8BCC1C5CACED3D7DCE0E4E9", - INIT_1E => X"C7CCD1D5DADFE4E8EDF2F6FB0004090E13171C21252A2E33383C41464A4F5358", - INIT_1F => X"2D32373B40454A4F54595E62676C71767B7F84898E93979CA1A6ABAFB4B9BEC2", - INIT_20 => X"8E93989DA2A7ACB1B6BBC0C5CACFD4D9DEE3E8EDF2F7FC01050A0F14191E2328", - INIT_21 => X"EAEFF4F9FE03090E13181D22282D32373C41464C51565B60656A6F74797E8389", - INIT_22 => X"41464B51565B61666B71767B81868B90969BA0A6ABB0B5BBC0C5CACFD5DADFE4", - INIT_23 => X"93989EA3A9AEB4B9BFC4CACFD5DAE0E5EAF0F5FB00060B10161B20262B31363B", - INIT_24 => X"E0E6ECF1F7FD02080E13191E242A2F353A40454B51565C61676C72777D82888D", - INIT_25 => X"292F353B40464C52575D63696E747A80858B91979CA2A8ADB3B9BEC4CACFD5DB", - INIT_26 => X"6D73797F858B91979DA2A8AEB4BAC0C6CCD2D7DDE3E9EFF5FB00060C12181E23", - INIT_27 => X"ACB2B8BEC4CBD1D7DDE3E9EFF5FB01070D13191F252B31373D43494F555B6167", - INIT_28 => X"E6EDF3F9FF060C12181F252B31373D444A50565C63696F757B81878E949AA0A6", - INIT_29 => X"1C22292F353C42494F555C62686F757B82888E959BA1A8AEB4BBC1C7CDD4DAE0", - INIT_2A => X"4D535A60676D747A81878E949BA1A8AEB5BBC2C8CFD5DCE2E9EFF5FC02090F16", - INIT_2B => X"797F868D939AA1A7AEB5BBC2C9CFD6DDE3EAF0F7FE040B12181F252C32394046", - INIT_2C => X"A0A7AEB4BBC2C9D0D7DDE4EBF2F9FF060D141A21282F353C434A50575E656B72", - INIT_2D => X"C2C9D0D7DEE5ECF3FA01080F161D242B323940464D545B626970777E848B9299", - INIT_2E => X"E0E7EEF5FD040B121920272E353D444B525960676E757C838A91989FA6ADB4BB", - INIT_2F => X"F900080F161D252C333B424950575F666D747C838A9198A0A7AEB5BCC3CBD2D9", - INIT_30 => X"0D151C242B323A414950575F666E757C848B939AA1A9B0B7BFC6CDD5DCE3EAF2", - INIT_31 => X"1D242C343B434A5259616970787F878E969DA5ACB4BBC3CAD2D9E1E8F0F7FE06", - INIT_32 => X"282F373F474E565E656D757D848C949BA3ABB2BAC2C9D1D8E0E8EFF7FE060E15", - INIT_33 => X"2E363E464D555D656D757C848C949CA4ABB3BBC3CBD2DAE2EAF1F90109111820", - INIT_34 => X"2F373F474F575F676F777F878F979FA7AFB7BFC7CFD7DFE7EFF7FF060E161E26", - INIT_35 => X"2C343C454D555D656D767E868E969EA6AEB6BFC7CFD7DFE7EFF7FF070F171F27", - INIT_36 => X"242D353D464E565E676F7780889098A1A9B1B9C2CAD2DAE2EBF3FB030B141C24", - INIT_37 => X"182029313A424A535B646C757D858E969FA7AFB8C0C8D1D9E2EAF2FB030B141C", - INIT_38 => X"070F182029323A434B545C656E767F879098A1A9B2BAC3CBD4DCE5EDF6FE070F", - INIT_39 => X"F1F9020B141C252E373F485159626B747C858E969FA8B0B9C2CAD3DBE4EDF5FE", - INIT_3A => X"D6DFE8F1FA030C141D262F38414A525B646D767F879099A2ABB3BCC5CED6DFE8", - INIT_3B => X"B7C0C9D2DBE4EDF6FF08111A232C353E475059626B747D868F98A1AAB3BCC4CD", - INIT_3C => X"949DA6AFB8C1CBD4DDE6EFF8010B141D262F38414A535D666F78818A939CA5AE", - INIT_3D => X"6B757E87919AA3ACB6BFC8D2DBE4EDF70009131C252E37414A535C666F78818A", - INIT_3E => X"3E48515B646E77818A949DA6B0B9C3CCD5DFE8F2FB040E17212A333D464F5962", - INIT_3F => X"0D17202A333D47505A636D77808A939DA6B0B9C3CCD6DFE9F3FC060F19222B35", - INIT_40 => X"D7E1EBF4FE08121B252F38424C565F69737C869099A3ADB6C0CAD3DDE7F0FA03", - INIT_41 => X"9DA6B0BAC4CED8E2ECF5FF09131D27313A444E58626B757F89939CA6B0BAC4CD", - INIT_42 => X"5D67727C86909AA4AEB8C2CCD6E0EAF4FE08111B252F39434D57616B757F8993", - INIT_43 => X"1A242E38434D57616B757F8A949EA8B2BCC6D0DBE5EFF9030D17212B353F4953", - INIT_44 => X"D2DCE6F1FB05101A242E39434D58626C76818B959FAAB4BEC8D2DDE7F1FB0510", - INIT_45 => X"85909AA5AFB9C4CED9E3EEF8020D17222C36414B56606A757F89949EA8B3BDC7", - INIT_46 => X"343F49545E69747E89939EA8B3BEC8D3DDE8F2FD07121C27313C46515B66707B", - INIT_47 => X"DFE9F4FF09141F2A343F4A545F6A747F8A959FAAB5BFCAD4DFEAF4FF0A141F29", - INIT_48 => X"848F9AA5B0BBC6D1DBE6F1FC07121C27323D48525D68737E88939EA9B3BEC9D4", - INIT_49 => X"26313C47525D68737E89949FAAB5C0CBD6E1ECF7020C17222D38434E59646F7A", - INIT_4A => X"C3CED9E5F0FB06111C27323E49545F6A75808B96A1ACB8C3CED9E4EFFA05101B", - INIT_4B => X"5C67727E89949FABB6C1CDD8E3EEFA05101B26323D48535E6A75808B96A2ADB8", - INIT_4C => X"F0FB07121E2935404B57626E7984909BA6B2BDC9D4DFEBF6010D18232F3A4550", - INIT_4D => X"808B97A3AEBAC5D1DCE8F3FF0A16212D38444F5B66727D8994A0ABB7C2CED9E5", - INIT_4E => X"0B17232E3A46525D6975808C98A3AFBBC6D2DDE9F5000C18232F3A46525D6974", - INIT_4F => X"929EAAB6C2CED9E5F1FD0914202C38444F5B67737F8A96A2AEB9C5D1DCE8F400", - INIT_50 => X"15212D3945515D6975818D99A5B1BDC8D4E0ECF804101C28343F4B57636F7B87", - INIT_51 => X"94A0ACB8C4D0DCE8F4010D1925313D4955616D7985919DA9B5C1CDD9E5F1FD09", - INIT_52 => X"0E1A26323F4B5763707C8894A0ADB9C5D1DDEAF6020E1A26333F4B57636F7B88", - INIT_53 => X"83909CA9B5C1CEDAE6F3FF0B1824303D4955626E7A87939FACB8C4D0DDE9F501", - INIT_54 => X"F5020E1B2734404D5965727E8B97A4B0BDC9D6E2EFFB0714202D3946525E6B77", - INIT_55 => X"626F7B8895A1AEBBC7D4E1EDFA0613202C3945525E6B7884919DAAB6C3CFDCE8", - INIT_56 => X"CBD8E5F1FE0B1825313E4B5864717E8A97A4B1BDCAD7E3F0FD0A1623303C4956", - INIT_57 => X"303D4A5763707D8A97A4B1BECBD7E4F1FE0B1825313E4B5865727E8B98A5B2BE", - INIT_58 => X"909DAAB7C4D1DFECF90613202D3A4754616E7B8894A1AEBBC8D5E2EFFC091623", - INIT_59 => X"EDFA0714212E3C495663707D8A98A5B2BFCCD9E6F3000E1B2835424F5C697683", - INIT_5A => X"45525F6C7A8794A2AFBCCAD7E4F1FF0C192634414E5B687683909DABB8C5D2DF", - INIT_5B => X"98A6B3C1CEDCE9F604111F2C394754626F7C8A97A4B2BFCDDAE7F5020F1D2A37", - INIT_5C => X"E8F603111E2C39475562707D8B98A6B3C1CEDCE9F704121F2D3A485563707E8B", - INIT_5D => X"34414F5D6A788693A1AFBCCAD8E5F3010E1C2A374553606E7B8997A4B2BFCDDB", - INIT_5E => X"7B8997A4B2C0CEDCEAF70513212F3C4A586673818F9DAAB8C6D4E1EFFD0A1826", - INIT_5F => X"BECCDAE8F60412202E3C4A586673818F9DABB9C7D5E3F0FE0C1A283644515F6D", - INIT_60 => X"FD0C1A28364452606E7C8A98A6B4C2D0DEECFA08162432404E5C6A788694A2B0", - INIT_61 => X"3947556371808E9CAAB8C6D5E3F1FF0D1B2A38465462707E8D9BA9B7C5D3E1EF", - INIT_62 => X"707E8C9BA9B7C6D4E2F0FF0D1B2A38465563717F8E9CAAB8C7D5E3F1000E1C2A", - INIT_63 => X"A2B1BFCEDCEBF90816253341505E6D7B8A98A6B5C3D1E0EEFD0B192836445361", - INIT_64 => X"D1E0EFFD0C1A293746556372808F9DACBAC9D7E6F50312202F3D4C5A69778694", - INIT_65 => X"FC0B1A283746556372818F9EADBBCAD9E7F6051322313F4E5C6B7A8897A6B4C3", - INIT_66 => X"233241505F6D7C8B9AA9B7C6D5E4F301101F2E3D4B5A69788695A4B3C1D0DFEE", - INIT_67 => X"465564738291A0AFBECDDCEBF90817263544536271808F9DACBBCAD9E8F70514", - INIT_68 => X"65748392A1B0C0CFDEEDFC0B1A2938475665748392A1B0BFCEDDECFB0A192837", - INIT_69 => X"808F9EAEBDCCDBEAFA09182736465564738291A0B0BFCEDDECFB0A1A29384756", - INIT_6A => X"97A6B6C5D4E4F302122130404F5E6E7D8C9BABBAC9D8E8F70615253443526271", - INIT_6B => X"AABAC9D9E8F807162635455464738292A1B1C0CFDFEEFE0D1C2C3B4A5A697888", - INIT_6C => X"BAC9D9E8F807172736465565748493A3B2C2D1E1F0000F1F2E3E4D5D6C7C8B9B", - INIT_6D => X"C5D5E4F404132333425262718191A0B0C0CFDFEFFE0E1E2D3D4C5C6C7B8B9AAA", - INIT_6E => X"CDDCECFC0C1C2B3B4B5B6B7A8A9AAAB9C9D9E9F808182837475767768696A6B5", - INIT_6F => X"D0E0F0001020304050606F7F8F9FAFBFCFDFEFFE0E1E2E3E4E5E6D7D8D9DADBD", - INIT_70 => X"D0E0F000102030405061718191A1B1C1D1E1F101112131415161708090A0B0C0", - INIT_71 => X"CCDCEDFD0D1D2D3D4E5E6E7E8E9EAEBFCFDFEFFF0F1F2F3F4F60708090A0B0C0", - INIT_72 => X"C5D5E5F506162637475767788898A8B9C9D9E9FA0A1A2A3A4B5B6B7B8B9CACBC", - INIT_73 => X"B9CADAEAFB0B1C2C3C4D5D6D7E8E9FAFBFD0E0F001112132425263738394A4B4", - INIT_74 => X"AABACBDCECFD0D1E2E3F4F60708191A2B2C2D3E3F404152536465767778898A9", - INIT_75 => X"97A8B8C9DAEAFB0B1C2D3D4E5F6F8090A1B2C2D3E3F404152636475768788999", - INIT_76 => X"8091A2B3C3D4E5F606172839495A6B7B8C9DAEBECFE0F0011222334454657686", - INIT_77 => X"66778899AABBCBDCEDFE0F2030415263748595A6B7C8D9E9FA0B1C2D3D4E5F70", - INIT_78 => X"48596A7B8C9DAEBFD0E1F2031425364758697A8A9BACBDCEDFF0011223344455", - INIT_79 => X"2738495A6B7C8D9EAFC0D2E3F405162738495A6B7C8D9EAFC0D1E2F304152637", - INIT_7A => X"021324354658697A8B9CAEBFD0E1F20315263748596A7B8D9EAFC0D1E2F30416", - INIT_7B => X"D9EAFB0D1E2F415263758697A8BACBDCEEFF10213344556678899AABBDCEDFF0", - INIT_7C => X"ACBECFE1F204152638495B6C7D8FA0B2C3D4E6F7091A2B3D4E5F718293A5B6C7", - INIT_7D => X"7C8EA0B1C3D4E6F7091A2C3D4F60728395A6B8C9DBECFE0F213244556778899B", - INIT_7E => X"495B6C7E90A1B3C5D6E8F90B1D2E405263758698AABBCDDEF00213253648596B", - INIT_7F => X"12243647596B7D8EA0B2C4D5E7F90B1C2E405163758798AABCCDDFF102142637", - INIT_A => X"000000000", - INIT_B => X"000000000", - INIT_FILE => "NONE", - IS_CLKARDCLK_INVERTED => '0', - IS_CLKBWRCLK_INVERTED => '0', - IS_ENARDEN_INVERTED => '0', - IS_ENBWREN_INVERTED => '0', - IS_RSTRAMARSTRAM_INVERTED => '0', - IS_RSTRAMB_INVERTED => '0', - IS_RSTREGARSTREG_INVERTED => '0', - IS_RSTREGB_INVERTED => '0', - RAM_EXTENSION_A => "NONE", - RAM_EXTENSION_B => "NONE", - RAM_MODE => "TDP", - RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", - READ_WIDTH_A => 9, - READ_WIDTH_B => 9, - RSTREG_PRIORITY_A => "REGCE", - RSTREG_PRIORITY_B => "REGCE", - SIM_COLLISION_CHECK => "ALL", - SIM_DEVICE => "7SERIES", - SRVAL_A => X"000000000", - SRVAL_B => X"000000000", - WRITE_MODE_A => "WRITE_FIRST", - WRITE_MODE_B => "WRITE_FIRST", - WRITE_WIDTH_A => 9, - WRITE_WIDTH_B => 9 - ) - port map ( - ADDRARDADDR(15) => '1', - ADDRARDADDR(14 downto 3) => addra(11 downto 0), - ADDRARDADDR(2 downto 0) => B"111", - ADDRBWRADDR(15) => '1', - ADDRBWRADDR(14 downto 3) => addrb(11 downto 0), - ADDRBWRADDR(2 downto 0) => B"111", - CASCADEINA => '0', - CASCADEINB => '0', - CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, - CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, - CLKARDCLK => clka, - CLKBWRCLK => clkb, - DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, - DIADI(31 downto 0) => B"00000000000000000000000000000000", - DIBDI(31 downto 0) => B"00000000000000000000000000000000", - DIPADIP(3 downto 0) => B"0000", - DIPBDIP(3 downto 0) => B"0000", - DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8), - DOADO(7 downto 0) => douta_array(7 downto 0), - DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8), - DOBDO(7 downto 0) => doutb_array(7 downto 0), - DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1), - DOPADOP(0) => douta_array(8), - DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1), - DOPBDOP(0) => doutb_array(8), - ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), - ENARDEN => ena_array(0), - ENBWREN => enb_array(0), - INJECTDBITERR => '0', - INJECTSBITERR => '0', - RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), - REGCEAREGCE => '1', - REGCEB => '1', - RSTRAMARSTRAM => '0', - RSTRAMB => '0', - RSTREGARSTREG => '0', - RSTREGB => '0', - SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, - WEA(3 downto 0) => B"0000", - WEBWE(7 downto 0) => B"00000000" - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized0\ is - port ( - douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - doutb_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init"; -end \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized0\; - -architecture STRUCTURE of \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized0\ is - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); - attribute box_type : string; - attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; -begin -\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 - generic map( - DOA_REG => 1, - DOB_REG => 1, - EN_ECC_READ => false, - EN_ECC_WRITE => false, - INITP_00 => X"C000FFFC000FFFC001FFF8001FFF8001FFF8000FFFC000FFFC000FFFE0007FFE", - INITP_01 => X"1FFF0007FFC000FFF8003FFF0007FFC000FFF8001FFF0003FFF0007FFE0007FF", - INITP_02 => X"FFF8003FFC001FFF0007FF8003FFE000FFF8003FFE000FFF8003FFE000FFF800", - INITP_03 => X"01FFE001FFF000FFF0007FF8003FFC003FFE001FFF000FFF8003FFC001FFE000", - INITP_04 => X"FF8007FF8007FF8007FF8007FF8007FF8007FF8007FF8003FFC003FFC003FFE0", - INITP_05 => X"FF001FFE003FFC003FF8007FF800FFF000FFE001FFE001FFC003FFC003FFC003", - INITP_06 => X"7FF800FFE003FFC007FF000FFE001FFC007FF800FFF001FFE003FFC007FF800F", - INITP_07 => X"800FFE003FF800FFE003FF8007FF001FFC007FF001FFE003FF800FFE001FFC00", - INITP_08 => X"03FF801FFC007FF001FFC007FF003FF800FFE003FF800FFE003FF800FFE003FF", - INITP_09 => X"0FFE003FF001FFC00FFE003FF001FFC007FE003FF800FFC007FF001FF800FFE0", - INITP_0A => X"01FF800FFC007FE003FF001FF800FFC007FF003FF801FFC007FE003FF001FFC0", - INITP_0B => X"C00FFC007FE003FF003FF801FFC00FFC007FE003FF001FF800FFC007FE003FF0", - INITP_0C => X"FF800FFC00FFE007FE003FF003FF801FF800FFC00FFE007FE003FF003FF801FF", - INITP_0D => X"007FE007FE003FF003FF001FF801FF800FFC00FFE007FE007FF003FF001FF801", - INITP_0E => X"FF800FFC00FFC00FFE007FE007FE003FF003FF001FF801FF801FFC00FFC00FFE", - INITP_0F => X"001FF801FF801FFC00FFC00FFC007FE007FE007FE003FF003FF003FF801FF801", - INIT_00 => X"D8EAFB0D1F31435567788A9CAEC0D2E3F507192B3D4E60728496A7B9CBDDEF00", - INIT_01 => X"9AACBED0E2F406182A3B4D5F718395A7B9CBDDEF01132537485A6C7E90A2B4C6", - INIT_02 => X"586A7D8FA1B3C5D7E9FB0D1F31435567798C9EB0C2D4E6F80A1C2E4052647688", - INIT_03 => X"1426384A5C6F8193A5B7C9DCEE00122436495B6D7F91A3B5C7DAECFE10223446", - INIT_04 => X"CBDEF0021527394B5E708295A7B9CBDEF0021427394B5D708294A6B9CBDDEF01", - INIT_05 => X"8092A5B7C9DCEE011325384A5D6F8194A6B8CBDDEF021426394B5D708294A7B9", - INIT_06 => X"314356687B8DA0B2C5D7EAFC0F213446596B7E90A3B5C8DAECFF112436495B6D", - INIT_07 => X"DFF10416293C4E61748699ABBED0E3F6081B2D405265788A9DAFC2D4E7F90C1E", - INIT_08 => X"899CAEC1D4E7F90C1F3144576A7C8FA2B4C7DAECFF1224374A5C6F8194A7B9CC", - INIT_09 => X"304356697B8EA1B4C7DAECFF1225374A5D708395A8BBCEE0F306192B3E516476", - INIT_0A => X"D4E7FA0D203346586B7E91A4B7CADDF00315283B4E61748799ACBFD2E5F80B1D", - INIT_0B => X"75889BAEC1D4E7FA0D203346596C7F92A5B8CBDEF104172A3C4F6275889BAEC1", - INIT_0C => X"1225384B5F728598ABBED1E4F70A1E3144576A7D90A3B6C9DCEF0215283C4F62", - INIT_0D => X"ACBFD3E6F90C203346596C8093A6B9CCE0F306192C3F5366798C9FB2C5D9ECFF", - INIT_0E => X"43576A7D91A4B7CADEF104182B3E5265788B9FB2C5D8ECFF1226394C5F728699", - INIT_0F => X"D7EAFE1125384C5F728699ADC0D3E7FA0E2134485B6E8295A8BCCFE3F6091D30", - INIT_10 => X"687B8FA2B6C9DDF004172B3E5265798CA0B3C7DAEE0115283C4F6276899DB0C4", - INIT_11 => X"F5091D3044576B7F92A6B9CDE1F4081B2F43566A7D91A4B8CBDFF3061A2D4154", - INIT_12 => X"8094A7BBCFE2F60A1E3145596C8094A7BBCFE2F60A1D3145586C8093A7BBCEE2", - INIT_13 => X"071B2F43576A7E92A6BACDE1F5091C3044586C7F93A7BBCEE2F60A1D3145586C", - INIT_14 => X"8CA0B4C8DBEF03172B3F53677B8EA2B6CADEF206192D4155697D90A4B8CCE0F4", - INIT_15 => X"0D2135495D718599ADC1D5E9FD1125394D6175899DB1C5D9EC0014283C506478", - INIT_16 => X"8CA0B4C8DCF004182C4054697D91A5B9CDE1F5091D3145596D8195A9BDD1E5F9", - INIT_17 => X"071B2F44586C8094A9BDD1E5F90D21364A5E72869AAEC3D7EBFF13273B4F6378", - INIT_18 => X"8094A8BCD1E5F90E22364A5F73879BAFC4D8EC0015293D51667A8EA2B6CBDFF3", - INIT_19 => X"F50A1E32475B6F8498ACC1D5E9FE12263B4F63788CA0B5C9DDF2061A2E43576B", - INIT_1A => X"687C91A5BACEE3F70C2034495D72869BAFC3D8EC0115293E52677B8FA4B8CCE1", - INIT_1B => X"D8EC01152A3E53687C91A5BACEE3F70C2035495E72879BB0C4D9ED02162B3F53", - INIT_1C => X"45596E8397ACC1D5EAFE13283C51657A8FA3B8CCE1F60A1F33485C71869AAFC3", - INIT_1D => X"AFC4D8ED02172B4055697E93A7BCD1E6FA0F24384D62768BA0B4C9DEF2071C30", - INIT_1E => X"162B40556A7E93A8BDD2E6FB1025394E63788DA1B6CBE0F4091E33475C71869A", - INIT_1F => X"7B90A5BACFE3F80D22374C61768A9FB4C9DEF3081C31465B708599AEC3D8ED02", - INIT_20 => X"DDF2071C31465B70859AAFC4D8ED02172C41566B8095AABFD4E9FE12273C5166", - INIT_21 => X"3C51667B90A5BACFE4FA0F24394E63788DA2B7CCE1F60B20354A5F74899EB3C8", - INIT_22 => X"98AEC3D8ED02172C42576C8196ABC0D5EB00152A3F54697E93A8BED3E8FD1227", - INIT_23 => X"F2081D32475C72879CB1C7DCF1061B31465B70859AB0C5DAEF041A2F44596E83", - INIT_24 => X"495F74899FB4C9DFF4091F34495E74899EB3C9DEF3091E33485E73889DB3C8DD", - INIT_25 => X"9EB3C9DEF4091E34495F74899FB4C9DFF4091F34495F748A9FB4CADFF40A1F34", - INIT_26 => X"F0051B30465B71869CB1C7DCF2071C32475D72889DB2C8DDF3081E33485E7389", - INIT_27 => X"3F556A8096ABC1D6EC01172C42576D8298AEC3D9EE04192F445A6F859AB0C5DA", - INIT_28 => X"8CA2B7CDE3F80E24394F647A90A5BBD1E6FC11273C52687D93A8BED4E9FF142A", - INIT_29 => X"D7EC02182D43596F849AB0C5DBF1061C32475D73889EB4C9DFF50A20364B6177", - INIT_2A => X"1E344A60768BA1B7CDE2F80E243A4F657B91A6BCD2E8FD13293F546A8095ABC1", - INIT_2B => X"647A90A5BBD1E7FD13293E546A8096ACC1D7ED03192F445A70869CB1C7DDF309", - INIT_2C => X"A7BDD3E9FF142A40566C8298AEC4DAF0061C31475D73899FB5CBE1F60C22384E", - INIT_2D => X"E7FD13293F556B8197ADC3D9EF051B31475D73899FB5CBE1F70D23394F657B91", - INIT_2E => X"263C52687E94AAC0D6EC02182F455B71879DB3C9DFF50B21374D63798FA5BBD1", - INIT_2F => X"61788EA4BAD0E6FC13293F556B8197AEC4DAF0061C32485F758BA1B7CDE3F90F", - INIT_30 => X"9BB1C7DEF40A20364D63798FA6BCD2E8FE152B41576D849AB0C6DCF3091F354B", - INIT_31 => X"D2E8FF152B42586E849BB1C7DEF40A20374D637A90A6BCD3E9FF152C42586E85", - INIT_32 => X"071D344A61778DA4BAD0E7FD132A40566D839AB0C6DDF30920364C62798FA5BC", - INIT_33 => X"3A50677D93AAC0D7ED041A31475D748AA1B7CDE4FA11273D546A8197ADC4DAF1", - INIT_34 => X"6A8197AEC4DBF1081E354B62788FA5BCD2E9FF162C435970869CB3C9E0F60D23", - INIT_35 => X"98AFC6DCF30920364D647A91A7BED4EB02182F455C72899FB6CCE3FA10273D54", - INIT_36 => X"C5DBF2081F364C637A90A7BED4EB01182F455C7389A0B6CDE4FA11273E556B82", - INIT_37 => X"EE051C334960778DA4BBD2E8FF162C435A70879EB4CBE2F90F263D536A8197AE", - INIT_38 => X"162D445B71889FB6CDE3FA11283E556C8399B0C7DEF40B22394F667D94AAC1D8", - INIT_39 => X"3C536A8197AEC5DCF30A21374E657C93A9C0D7EE051C324960778EA4BBD2E900", - INIT_3A => X"60778EA5BBD2E900172E455C738AA0B7CEE5FC132A41576E859CB3CAE1F80E25", - INIT_3B => X"8198AFC6DDF40B223950677E95ACC3DAF1081F364D647B91A8BFD6ED041B3249", - INIT_3C => X"A1B8CFE6FD142B425970879FB6CDE4FB122940576E859CB3CAE1F80F263D546B", - INIT_3D => X"BFD6ED041B324961788FA6BDD4EB021930475E758DA4BBD2E900172E455C738A", - INIT_3E => X"DBF20920374E667D94ABC2D9F0081F364D647B92AAC1D8EF061D344B627A91A8", - INIT_3F => X"F50C233A51698097AEC5DDF40B223951687F96ADC5DCF30A213850677E95ACC3", - INIT_40 => X"0C243B526A8198AFC7DEF50C243B52698198AFC6DEF50C233B52698098AFC6DD", - INIT_41 => X"233A51698097AFC6DDF50C233A52698098AFC6DEF50C243B52698198AFC7DEF5", - INIT_42 => X"374E667D94ACC3DBF20921384F677E96ADC4DCF30A223950687F97AEC5DDF40B", - INIT_43 => X"49617890A7BFD6ED051C344B637A91A9C0D8EF071E354D647C93AAC2D9F1081F", - INIT_44 => X"5A7189A0B8CFE7FE162D455C748BA3BAD2E9011830475F768EA5BDD4EB031A32", - INIT_45 => X"698098B0C7DFF60E253D546C849BB3CAE2F9112840576F869EB5CDE4FC132B42", - INIT_46 => X"768EA5BDD5EC041B334B627A91A9C1D8F0071F364E667D95ACC4DCF30B223A51", - INIT_47 => X"8299B1C9E0F810273F576E869EB5CDE4FC142B435B728AA2B9D1E800182F475F", - INIT_48 => X"8CA3BBD3EA021A3249617990A8C0D7EF071E364E667D95ADC4DCF40B233B526A", - INIT_49 => X"94ACC3DBF30B223A526A8199B1C9E0F810283F576F879EB6CEE5FD152D445C74", - INIT_4A => X"9AB2CAE2FA112941597188A0B8D0E8FF172F475F768EA6BED6ED051D354C647C", - INIT_4B => X"9FB7CFE7FF172F465E768EA6BED6ED051D354D657C94ACC4DCF40B233B536B83", - INIT_4C => X"A3BBD3EB031A324A627A92AAC2DAF209213951698199B1C9E0F8102840587088", - INIT_4D => X"A5BDD5ED051D354D657C94ACC4DCF40C243C546C849CB4CCE4FB132B435B738B", - INIT_4E => X"A5BDD5ED051D354D657D95ADC5DDF50D253D556D859DB5CDE5FD152D455D758D", - INIT_4F => X"A4BCD5ED051D354D657D95ADC5DDF50D253D556D859DB5CDE5FD152D455D758D", - INIT_50 => X"A2BAD2EA021A334B637B93ABC3DBF30B233B546C849CB4CCE4FC142C445C748C", - INIT_51 => X"9EB6CEE7FF172F475F7790A8C0D8F008203851698199B1C9E1F9112A425A728A", - INIT_52 => X"99B1C9E2FA122A425A738BA3BBD3EB041C344C647C95ADC5DDF50D253E566E86", - INIT_53 => X"92ABC3DBF30C243C546C859DB5CDE5FE162E465F778FA7BFD7F0082038506981", - INIT_54 => X"8BA3BBD3EC041C344D657D95AEC6DEF60F273F577088A0B8D1E90119324A627A", - INIT_55 => X"819AB2CAE3FB132C445C748DA5BDD6EE061E374F678098B0C8E1F9112A425A72", - INIT_56 => X"778FA8C0D8F109213A526A839BB3CCE4FC152D455E768EA7BFD7F00820395169", - INIT_57 => X"6B849CB5CDE5FE162E475F7890A8C1D9F10A223B536B849CB4CDE5FD162E465F", - INIT_58 => X"5F778FA8C0D9F10A223A536B849CB4CDE5FE162E475F7890A8C1D9F20A223B53", - INIT_59 => X"5169829AB2CBE3FC142D455E768EA7BFD8F009213A526A839BB4CCE5FD152E46", - INIT_5A => X"425A728BA3BCD4ED051E364F678098B1C9E2FA132B445C758DA5BED6EF072038", - INIT_5B => X"314A627B93ACC4DDF50E263F577089A1BAD2EB031C344D657E96AFC7E0F81129", - INIT_5C => X"2038516A829BB3CCE4FD152E475F7890A9C1DAF20B233C556D869EB7CFE80019", - INIT_5D => X"0E263F577089A1BAD2EB031C354D667E97AFC8E1F9122A435B748DA5BED6EF07", - INIT_5E => X"FA132B445D758EA6BFD8F009223A536B849DB5CEE6FF183049617A93ABC4DCF5", - INIT_5F => X"E6FE173048617A92ABC4DCF50E263F577089A1BAD3EB041D354E667F98B0C9E2", - INIT_60 => X"D0E9021A334C647D96AFC7E0F9112A435B748DA5BED7EF082139526A839CB4CD", - INIT_61 => X"BAD3EC041D364E678098B1CAE3FB142D455E778FA8C1DAF20B243C556E869FB8", - INIT_62 => X"A3BCD4ED061F375069829AB3CCE4FD162F47607992AAC3DCF40D263F577089A1", - INIT_63 => X"8BA4BCD5EE071F38516A829BB4CDE5FE173048617A93ABC4DDF60E274059718A", - INIT_64 => X"728BA4BCD5EE071F38516A839BB4CDE6FF173049627A93ACC5DDF60F28415972", - INIT_65 => X"58718AA3BBD4ED061F385069829BB4CCE5FE173048617A93ACC4DDF60F284059", - INIT_66 => X"3E576F88A1BAD3EC041D364F688199B2CBE4FD162E47607992AAC3DCF50E273F", - INIT_67 => X"223B546D869FB8D0E9021B344D667E97B0C9E2FB142C455E7790A9C1DAF30C25", - INIT_68 => X"061F38516A839CB5CEE6FF18314A637C95ADC6DFF8112A435C748DA6BFD8F10A", - INIT_69 => X"EA031C344D667F98B1CAE3FC152E465F7891AAC3DCF50E263F58718AA3BCD5EE", - INIT_6A => X"CCE5FE173049627B94ADC6DFF81029425B748DA6BFD8F10A223B546D869FB8D1", - INIT_6B => X"AEC7E0F9122B445D768FA8C1DAF30C253E566F88A1BAD3EC051E375069829BB3", - INIT_6C => X"90A9C2DBF40D263F587189A2BBD4ED061F38516A839CB5CEE70019324B647D95", - INIT_6D => X"718AA3BCD5EE072039526A839CB5CEE70019324B647D96AFC8E1FA132C455E77", - INIT_6E => X"516A839CB5CEE70019324B647D96AFC8E1FA132C455E7790A9C2DBF40D263F58", - INIT_6F => X"314A637C95AEC7E0F9122B445D768FA8C1DAF30C253E577089A2BBD4ED061F38", - INIT_70 => X"1029425B748DA6BFD8F10A233C556E87A0B9D3EC051E375069829BB4CDE6FF18", - INIT_71 => X"EF08213A536C859EB7D0E9021B344D678099B2CBE4FD162F48617A93ACC5DEF7", - INIT_72 => X"CDE6FF18324B647D96AFC8E1FA132C455E7790A9C2DBF40E274059728BA4BDD6", - INIT_73 => X"ABC4DDF71029425B748DA6BFD8F10A233C556F88A1BAD3EC051E375069829BB4", - INIT_74 => X"89A2BBD4ED061F39526B849DB6CFE8011A334C657F98B1CAE3FC152E47607992", - INIT_75 => X"667F99B2CBE4FD162F48617A93ACC6DFF8112A435C758EA7C0D9F30C253E5770", - INIT_76 => X"435C768FA8C1DAF30C253E57718AA3BCD5EE072039526B859EB7D0E9021B344D", - INIT_77 => X"2039526B859EB7D0E9021B344D668099B2CBE4FD162F48617B94ADC6DFF8112A", - INIT_78 => X"FD162F48617A93ACC6DFF8112A435C758EA8C1DAF30C253E577089A3BCD5EE07", - INIT_79 => X"D9F20B243D577089A2BBD4ED061F39526B849DB6CFE8021B344D667F98B1CAE4", - INIT_7A => X"B5CEE7001A334C657E97B0C9E3FC152E47607992ACC5DEF71029425B748EA7C0", - INIT_7B => X"91AAC3DCF60F28415A738CA5BFD8F10A233C556E88A1BAD3EC051E37516A839C", - INIT_7C => X"6D869FB8D1EB041D364F68819AB4CDE6FF18314A637D96AFC8E1FA132D465F78", - INIT_7D => X"49627B94ADC6DFF9122B445D768FA9C2DBF40D263F58728BA4BDD6EF08213B54", - INIT_7E => X"243D577089A2BBD4ED072039526B849DB6D0E9021B344D668099B2CBE4FD1630", - INIT_7F => X"0019324B657E97B0C9E2FB142E47607992ABC4DEF71029425B748EA7C0D9F20B", - INIT_A => X"000000000", - INIT_B => X"000000000", - INIT_FILE => "NONE", - IS_CLKARDCLK_INVERTED => '0', - IS_CLKBWRCLK_INVERTED => '0', - IS_ENARDEN_INVERTED => '0', - IS_ENBWREN_INVERTED => '0', - IS_RSTRAMARSTRAM_INVERTED => '0', - IS_RSTRAMB_INVERTED => '0', - IS_RSTREGARSTREG_INVERTED => '0', - IS_RSTREGB_INVERTED => '0', - RAM_EXTENSION_A => "NONE", - RAM_EXTENSION_B => "NONE", - RAM_MODE => "TDP", - RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", - READ_WIDTH_A => 9, - READ_WIDTH_B => 9, - RSTREG_PRIORITY_A => "REGCE", - RSTREG_PRIORITY_B => "REGCE", - SIM_COLLISION_CHECK => "ALL", - SIM_DEVICE => "7SERIES", - SRVAL_A => X"000000000", - SRVAL_B => X"000000000", - WRITE_MODE_A => "WRITE_FIRST", - WRITE_MODE_B => "WRITE_FIRST", - WRITE_WIDTH_A => 9, - WRITE_WIDTH_B => 9 - ) - port map ( - ADDRARDADDR(15) => '1', - ADDRARDADDR(14 downto 3) => addra(11 downto 0), - ADDRARDADDR(2 downto 0) => B"111", - ADDRBWRADDR(15) => '1', - ADDRBWRADDR(14 downto 3) => addrb(11 downto 0), - ADDRBWRADDR(2 downto 0) => B"111", - CASCADEINA => '0', - CASCADEINB => '0', - CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, - CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, - CLKARDCLK => clka, - CLKBWRCLK => clkb, - DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, - DIADI(31 downto 0) => B"00000000000000000000000000000000", - DIBDI(31 downto 0) => B"00000000000000000000000000000000", - DIPADIP(3 downto 0) => B"0000", - DIPBDIP(3 downto 0) => B"0000", - DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8), - DOADO(7 downto 0) => douta_array(7 downto 0), - DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8), - DOBDO(7 downto 0) => doutb_array(7 downto 0), - DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1), - DOPADOP(0) => douta_array(8), - DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1), - DOPBDOP(0) => doutb_array(8), - ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), - ENARDEN => addra(12), - ENBWREN => addrb(12), - INJECTDBITERR => '0', - INJECTSBITERR => '0', - RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), - REGCEAREGCE => '1', - REGCEB => '1', - RSTRAMARSTRAM => '0', - RSTRAMB => '0', - RSTREGARSTREG => '0', - RSTREGB => '0', - SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, - WEA(3 downto 0) => B"0000", - WEBWE(7 downto 0) => B"00000000" - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized1\ is - port ( - douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - doutb_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - ena_array : out STD_LOGIC_VECTOR ( 0 to 0 ); - enb_array : out STD_LOGIC_VECTOR ( 0 to 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init"; -end \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized1\; - -architecture STRUCTURE of \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized1\ is - signal \^ena_array\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \^enb_array\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); - attribute box_type : string; - attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; -begin - ena_array(0) <= \^ena_array\(0); - enb_array(0) <= \^enb_array\(0); -\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 - generic map( - DOA_REG => 1, - DOB_REG => 1, - EN_ECC_READ => false, - EN_ECC_WRITE => false, - INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_0E => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_0F => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", - INIT_10 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", - INIT_11 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", - INIT_12 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", - INIT_13 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", - INIT_14 => X"FDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFEFEFEFEFEFEFEFEFEFEFEFEFE", - INIT_15 => X"FDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFD", - INIT_16 => X"FDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFD", - INIT_17 => X"FDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFD", - INIT_18 => X"FCFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFD", - INIT_19 => X"FCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFC", - INIT_1A => X"FCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFC", - INIT_1B => X"FCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFC", - INIT_1C => X"FBFBFBFBFBFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFC", - INIT_1D => X"FBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFB", - INIT_1E => X"FBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFB", - INIT_1F => X"FBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFB", - INIT_20 => X"FAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFBFBFBFBFBFBFBFBFB", - INIT_21 => X"FAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFA", - INIT_22 => X"FAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFA", - INIT_23 => X"F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9FAFAFAFAFAFAFAFAFAFAFAFA", - INIT_24 => X"F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9", - INIT_25 => X"F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9", - INIT_26 => X"F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F9F9F9F9F9F9F9", - INIT_27 => X"F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8", - INIT_28 => X"F7F7F7F7F7F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8", - INIT_29 => X"F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7", - INIT_2A => X"F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7", - INIT_2B => X"F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F7F7F7F7F7F7F7F7F7F7F7", - INIT_2C => X"F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6", - INIT_2D => X"F5F5F5F5F5F5F5F5F5F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6", - INIT_2E => X"F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5", - INIT_2F => X"F4F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5", - INIT_30 => X"F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4", - INIT_31 => X"F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4", - INIT_32 => X"F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F4F4F4", - INIT_33 => X"F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3", - INIT_34 => X"F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F3F3F3F3F3", - INIT_35 => X"F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2", - INIT_36 => X"F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F2F2F2F2F2", - INIT_37 => X"F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1", - INIT_38 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F1F1", - INIT_39 => X"EFEFF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0", - INIT_3A => X"EFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEF", - INIT_3B => X"EEEEEEEEEEEEEEEEEEEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEF", - INIT_3C => X"EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE", - INIT_3D => X"EDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE", - INIT_3E => X"EDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDED", - INIT_3F => X"ECECECECECECECECECECECECECECECECECECECECECECECECECECEDEDEDEDEDED", - INIT_40 => X"EBEBEBEBEBECECECECECECECECECECECECECECECECECECECECECECECECECECEC", - INIT_41 => X"EBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEB", - INIT_42 => X"EAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEBEBEBEBEBEBEBEBEBEBEBEBEBEBEB", - INIT_43 => X"EAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEA", - INIT_44 => X"E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EAEA", - INIT_45 => X"E8E8E8E8E8E8E8E8E8E8E8E8E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9", - INIT_46 => X"E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8", - INIT_47 => X"E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E8E8E8E8", - INIT_48 => X"E6E6E6E6E6E6E6E6E6E6E6E6E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7", - INIT_49 => X"E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6", - INIT_4A => X"E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E6E6E6", - INIT_4B => X"E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5", - INIT_4C => X"E3E3E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4", - INIT_4D => X"E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3", - INIT_4E => X"E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E3E3E3E3E3E3E3E3E3E3E3", - INIT_4F => X"E1E1E1E1E1E1E1E1E1E1E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2", - INIT_50 => X"E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1", - INIT_51 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E1", - INIT_52 => X"DFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFE0E0E0E0E0E0E0E0E0E0E0E0", - INIT_53 => X"DEDEDEDEDEDEDEDEDEDEDEDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDF", - INIT_54 => X"DDDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDE", - INIT_55 => X"DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD", - INIT_56 => X"DCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDDDDDDDDDDDDDD", - INIT_57 => X"DBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDCDCDCDCDCDCDCDCDCDCDCDCDCDCDC", - INIT_58 => X"DADADADADADADADADADBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDB", - INIT_59 => X"D9D9DADADADADADADADADADADADADADADADADADADADADADADADADADADADADADA", - INIT_5A => X"D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9", - INIT_5B => X"D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D9D9D9D9D9", - INIT_5C => X"D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D8D8D8D8D8D8D8D8D8D8D8", - INIT_5D => X"D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7", - INIT_5E => X"D5D5D5D5D5D5D5D5D5D5D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6", - INIT_5F => X"D4D4D4D4D4D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5", - INIT_60 => X"D3D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4", - INIT_61 => X"D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3", - INIT_62 => X"D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D3D3D3D3", - INIT_63 => X"D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D2D2D2D2D2D2D2", - INIT_64 => X"D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D1D1D1D1D1D1D1D1D1D1D1", - INIT_65 => X"CFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFD0D0D0D0D0D0D0D0D0D0D0D0D0D0", - INIT_66 => X"CECECECECECECECECECECECECECECECFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCF", - INIT_67 => X"CDCDCDCDCDCDCDCDCDCDCDCDCDCECECECECECECECECECECECECECECECECECECE", - INIT_68 => X"CCCCCCCCCCCCCCCCCCCCCCCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCD", - INIT_69 => X"CBCBCBCBCBCBCBCBCBCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC", - INIT_6A => X"CACACACACACACACBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCB", - INIT_6B => X"C9C9C9C9C9C9CACACACACACACACACACACACACACACACACACACACACACACACACACA", - INIT_6C => X"C8C8C8C8C8C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9", - INIT_6D => X"C7C7C7C7C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8", - INIT_6E => X"C6C6C6C6C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7", - INIT_6F => X"C5C5C5C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6", - INIT_70 => X"C4C4C4C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5", - INIT_71 => X"C3C3C3C3C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4", - INIT_72 => X"C2C2C2C2C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3", - INIT_73 => X"C1C1C1C1C1C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2", - INIT_74 => X"C0C0C0C0C0C0C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1", - INIT_75 => X"BFBFBFBFBFBFBFC0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0", - INIT_76 => X"BEBEBEBEBEBEBEBEBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBF", - INIT_77 => X"BDBDBDBDBDBDBDBDBDBDBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBE", - INIT_78 => X"BCBCBCBCBCBCBCBCBCBCBCBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBD", - INIT_79 => X"BBBBBBBBBBBBBBBBBBBBBBBBBBBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBC", - INIT_7A => X"BABABABABABABABABABABABABABABABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB", - INIT_7B => X"B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9BABABABABABABABABABABABABABA", - INIT_7C => X"B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B9B9B9B9B9B9B9B9B9B9B9B9", - INIT_7D => X"B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B8B8B8B8B8B8B8B8B8", - INIT_7E => X"B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B7B7B7B7B7B7B7", - INIT_7F => X"B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B6B6B6B6", - INIT_A => X"000000000", - INIT_B => X"000000000", - INIT_FILE => "NONE", - IS_CLKARDCLK_INVERTED => '0', - IS_CLKBWRCLK_INVERTED => '0', - IS_ENARDEN_INVERTED => '0', - IS_ENBWREN_INVERTED => '0', - IS_RSTRAMARSTRAM_INVERTED => '0', - IS_RSTRAMB_INVERTED => '0', - IS_RSTREGARSTREG_INVERTED => '0', - IS_RSTREGB_INVERTED => '0', - RAM_EXTENSION_A => "NONE", - RAM_EXTENSION_B => "NONE", - RAM_MODE => "TDP", - RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", - READ_WIDTH_A => 9, - READ_WIDTH_B => 9, - RSTREG_PRIORITY_A => "REGCE", - RSTREG_PRIORITY_B => "REGCE", - SIM_COLLISION_CHECK => "ALL", - SIM_DEVICE => "7SERIES", - SRVAL_A => X"000000000", - SRVAL_B => X"000000000", - WRITE_MODE_A => "WRITE_FIRST", - WRITE_MODE_B => "WRITE_FIRST", - WRITE_WIDTH_A => 9, - WRITE_WIDTH_B => 9 - ) - port map ( - ADDRARDADDR(15) => '1', - ADDRARDADDR(14 downto 3) => addra(11 downto 0), - ADDRARDADDR(2 downto 0) => B"111", - ADDRBWRADDR(15) => '1', - ADDRBWRADDR(14 downto 3) => addrb(11 downto 0), - ADDRBWRADDR(2 downto 0) => B"111", - CASCADEINA => '0', - CASCADEINB => '0', - CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, - CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, - CLKARDCLK => clka, - CLKBWRCLK => clkb, - DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, - DIADI(31 downto 0) => B"00000000000000000000000000000000", - DIBDI(31 downto 0) => B"00000000000000000000000000000000", - DIPADIP(3 downto 0) => B"0000", - DIPBDIP(3 downto 0) => B"0000", - DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8), - DOADO(7 downto 0) => douta_array(7 downto 0), - DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8), - DOBDO(7 downto 0) => doutb_array(7 downto 0), - DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1), - DOPADOP(0) => douta_array(8), - DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1), - DOPBDOP(0) => doutb_array(8), - ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), - ENARDEN => \^ena_array\(0), - ENBWREN => \^enb_array\(0), - INJECTDBITERR => '0', - INJECTSBITERR => '0', - RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), - REGCEAREGCE => '1', - REGCEB => '1', - RSTRAMARSTRAM => '0', - RSTRAMB => '0', - RSTREGARSTREG => '0', - RSTREGB => '0', - SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, - WEA(3 downto 0) => B"0000", - WEBWE(7 downto 0) => B"00000000" - ); -\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => addra(12), - O => \^ena_array\(0) - ); -\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => addrb(12), - O => \^enb_array\(0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized2\ is - port ( - douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - doutb_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init"; -end \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized2\; - -architecture STRUCTURE of \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized2\ is - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); - attribute box_type : string; - attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; -begin -\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 - generic map( - DOA_REG => 1, - DOB_REG => 1, - EN_ECC_READ => false, - EN_ECC_WRITE => false, - INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_00 => X"B3B3B3B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B5", - INIT_01 => X"B2B2B2B2B2B2B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3", - INIT_02 => X"B1B1B1B1B1B1B1B1B1B1B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2", - INIT_03 => X"B0B0B0B0B0B0B0B0B0B0B0B0B0B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1", - INIT_04 => X"AFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFB0B0B0B0B0B0B0B0B0B0B0B0B0B0B0", - INIT_05 => X"AEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAFAFAFAFAFAFAFAFAFAFAF", - INIT_06 => X"ADADADADADADADADADADADADADADADADADADADADADADADADADADAEAEAEAEAEAE", - INIT_07 => X"ABABACACACACACACACACACACACACACACACACACACACACACACACACACACACACADAD", - INIT_08 => X"AAAAAAAAAAAAAAABABABABABABABABABABABABABABABABABABABABABABABABAB", - INIT_09 => X"A9A9A9A9A9A9A9A9A9A9A9A9AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", - INIT_0A => X"A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9", - INIT_0B => X"A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A8A8A8A8A8A8A8A8A8A8A8", - INIT_0C => X"A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A7A7A7A7A7A7", - INIT_0D => X"A4A4A4A4A4A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5", - INIT_0E => X"A3A3A3A3A3A3A3A3A3A3A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4", - INIT_0F => X"A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3", - INIT_10 => X"A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A2A2A2A2A2A2A2A2A2A2A2", - INIT_11 => X"9FA0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A1A1A1A1A1", - INIT_12 => X"9E9E9E9E9E9E9E9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F", - INIT_13 => X"9D9D9D9D9D9D9D9D9D9D9D9D9D9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E", - INIT_14 => X"9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9D9D9D9D9D9D9D9D9D9D9D9D9D", - INIT_15 => X"9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9C9C9C9C9C9C9C", - INIT_16 => X"9999999999999A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A", - INIT_17 => X"9898989898989898989898989899999999999999999999999999999999999999", - INIT_18 => X"9797979797979797979797979797979797979798989898989898989898989898", - INIT_19 => X"9596969696969696969696969696969696969696969696969696979797979797", - INIT_1A => X"9494949494949494959595959595959595959595959595959595959595959595", - INIT_1B => X"9393939393939393939393939393939494949494949494949494949494949494", - INIT_1C => X"9292929292929292929292929292929292929292929293939393939393939393", - INIT_1D => X"9090909091919191919191919191919191919191919191919191919191929292", - INIT_1E => X"8F8F8F8F8F8F8F8F8F8F8F8F9090909090909090909090909090909090909090", - INIT_1F => X"8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8F8F8F8F8F8F8F8F8F8F8F8F8F", - INIT_20 => X"8C8C8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8E8E8E8E8E", - INIT_21 => X"8B8B8B8B8B8B8B8B8B8B8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C", - INIT_22 => X"8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B", - INIT_23 => X"888989898989898989898989898989898989898989898989898A8A8A8A8A8A8A", - INIT_24 => X"8787878787878787878888888888888888888888888888888888888888888888", - INIT_25 => X"8686868686868686868686868686868686878787878787878787878787878787", - INIT_26 => X"8485858585858585858585858585858585858585858585858586868686868686", - INIT_27 => X"8383838383838383838484848484848484848484848484848484848484848484", - INIT_28 => X"8282828282828282828282828282828282828383838383838383838383838383", - INIT_29 => X"8080818181818181818181818181818181818181818181818181828282828282", - INIT_2A => X"7F7F7F7F7F7F7F7F7F7F7F808080808080808080808080808080808080808080", - INIT_2B => X"7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7F7F7F7F7F7F7F7F7F7F7F7F7F", - INIT_2C => X"7C7C7C7C7C7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7E7E7E7E", - INIT_2D => X"7B7B7B7B7B7B7B7B7B7B7B7B7B7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C", - INIT_2E => X"7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7B7B7B7B7B7B7B7B7B7B", - INIT_2F => X"787878787878787879797979797979797979797979797979797979797979797A", - INIT_30 => X"7777777777777777777777777777777777787878787878787878787878787878", - INIT_31 => X"7575757676767676767676767676767676767676767676767676777777777777", - INIT_32 => X"7474747474747474747474747575757575757575757575757575757575757575", - INIT_33 => X"7373737373737373737373737373737373737373737474747474747474747474", - INIT_34 => X"7171717171717172727272727272727272727272727272727272727272727373", - INIT_35 => X"7070707070707070707070707070707071717171717171717171717171717171", - INIT_36 => X"6E6E6E6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F707070707070", - INIT_37 => X"6D6D6D6D6D6D6D6D6D6D6D6D6D6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E", - INIT_38 => X"6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6D6D6D6D6D6D6D6D6D6D", - INIT_39 => X"6A6A6A6A6A6A6A6A6A6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6C", - INIT_3A => X"696969696969696969696969696969696969696A6A6A6A6A6A6A6A6A6A6A6A6A", - INIT_3B => X"6767676767676868686868686868686868686868686868686868686869696969", - INIT_3C => X"6666666666666666666666666666666667676767676767676767676767676767", - INIT_3D => X"6464646565656565656565656565656565656565656565656566666666666666", - INIT_3E => X"6363636363636363636363636364646464646464646464646464646464646464", - INIT_3F => X"6162626262626262626262626262626262626262626262636363636363636363", - INIT_40 => X"6060606060606060606060616161616161616161616161616161616161616161", - INIT_41 => X"5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F6060606060606060606060", - INIT_42 => X"5D5D5D5D5D5D5D5D5D5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5F", - INIT_43 => X"5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5D5D5D5D5D5D5D5D5D5D5D5D5D", - INIT_44 => X"5A5A5A5A5A5A5A5A5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5C5C5C", - INIT_45 => X"5959595959595959595959595959595959595A5A5A5A5A5A5A5A5A5A5A5A5A5A", - INIT_46 => X"5757575757575858585858585858585858585858585858585858585859595959", - INIT_47 => X"5656565656565656565656565656565656575757575757575757575757575757", - INIT_48 => X"5454545454555555555555555555555555555555555555555555555656565656", - INIT_49 => X"5353535353535353535353535353535354545454545454545454545454545454", - INIT_4A => X"5151515151525252525252525252525252525252525252525252535353535353", - INIT_4B => X"5050505050505050505050505050505151515151515151515151515151515151", - INIT_4C => X"4E4E4E4E4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F505050505050", - INIT_4D => X"4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E", - INIT_4E => X"4B4B4B4B4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4D4D4D4D4D4D", - INIT_4F => X"4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B", - INIT_50 => X"48484848494949494949494949494949494949494949494949494A4A4A4A4A4A", - INIT_51 => X"4747474747474747474747474747474848484848484848484848484848484848", - INIT_52 => X"4545454545464646464646464646464646464646464646464646474747474747", - INIT_53 => X"4444444444444444444444444444444445454545454545454545454545454545", - INIT_54 => X"4242424242434343434343434343434343434343434343434343444444444444", - INIT_55 => X"4141414141414141414141414141414142424242424242424242424242424242", - INIT_56 => X"3F3F3F3F3F3F4040404040404040404040404040404040404040404141414141", - INIT_57 => X"3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F", - INIT_58 => X"3C3C3C3C3C3C3C3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3E3E3E3E", - INIT_59 => X"3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3C3C3C3C3C3C3C3C3C3C3C3C3C3C", - INIT_5A => X"39393939393939393A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3B3B3B", - INIT_5B => X"3838383838383838383838383838383838383839393939393939393939393939", - INIT_5C => X"3636363636363636363637373737373737373737373737373737373737373838", - INIT_5D => X"3535353535353535353535353535353535353535353636363636363636363636", - INIT_5E => X"3333333333333333333333343434343434343434343434343434343434343434", - INIT_5F => X"3131323232323232323232323232323232323232323233333333333333333333", - INIT_60 => X"3030303030303030303030303031313131313131313131313131313131313131", - INIT_61 => X"2E2E2E2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F3030303030303030", - INIT_62 => X"2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E", - INIT_63 => X"2B2B2B2B2B2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2D2D2D2D2D2D", - INIT_64 => X"2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B", - INIT_65 => X"282828282828282929292929292929292929292929292929292929292A2A2A2A", - INIT_66 => X"2727272727272727272727272727272727272728282828282828282828282828", - INIT_67 => X"2525252525252525252626262626262626262626262626262626262626262727", - INIT_68 => X"2424242424242424242424242424242424242424242525252525252525252525", - INIT_69 => X"2222222222222222222222222323232323232323232323232323232323232323", - INIT_6A => X"2020202121212121212121212121212121212121212121222222222222222222", - INIT_6B => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F202020202020202020202020202020202020", - INIT_6C => X"1D1D1D1D1D1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1F1F1F1F1F1F1F", - INIT_6D => X"1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D", - INIT_6E => X"1A1A1A1A1A1A1A1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1C1C1C1C", - INIT_6F => X"191919191919191919191919191919191919191A1A1A1A1A1A1A1A1A1A1A1A1A", - INIT_70 => X"1717171717171717171718181818181818181818181818181818181818181819", - INIT_71 => X"1516161616161616161616161616161616161616161617171717171717171717", - INIT_72 => X"1414141414141414141414141415151515151515151515151515151515151515", - INIT_73 => X"1212121213131313131313131313131313131313131313131414141414141414", - INIT_74 => X"1111111111111111111111111111111212121212121212121212121212121212", - INIT_75 => X"0F0F0F0F0F0F0F10101010101010101010101010101010101010101111111111", - INIT_76 => X"0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0F0F0F0F0F0F0F0F0F0F0F0F0F0F", - INIT_77 => X"0C0C0C0C0C0C0C0C0C0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0E0E", - INIT_78 => X"0A0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0C0C0C0C0C0C0C0C0C0C0C", - INIT_79 => X"0909090909090909090909090A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A", - INIT_7A => X"0707070808080808080808080808080808080808080808080909090909090909", - INIT_7B => X"0606060606060606060606060606060707070707070707070707070707070707", - INIT_7C => X"0404040404040505050505050505050505050505050505050505050606060606", - INIT_7D => X"0303030303030303030303030303030303030404040404040404040404040404", - INIT_7E => X"0101010101010101010202020202020202020202020202020202020202020303", - INIT_7F => X"0000000000000000000000000000000000000000000101010101010101010101", - INIT_A => X"000000000", - INIT_B => X"000000000", - INIT_FILE => "NONE", - IS_CLKARDCLK_INVERTED => '0', - IS_CLKBWRCLK_INVERTED => '0', - IS_ENARDEN_INVERTED => '0', - IS_ENBWREN_INVERTED => '0', - IS_RSTRAMARSTRAM_INVERTED => '0', - IS_RSTRAMB_INVERTED => '0', - IS_RSTREGARSTREG_INVERTED => '0', - IS_RSTREGB_INVERTED => '0', - RAM_EXTENSION_A => "NONE", - RAM_EXTENSION_B => "NONE", - RAM_MODE => "TDP", - RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", - READ_WIDTH_A => 9, - READ_WIDTH_B => 9, - RSTREG_PRIORITY_A => "REGCE", - RSTREG_PRIORITY_B => "REGCE", - SIM_COLLISION_CHECK => "ALL", - SIM_DEVICE => "7SERIES", - SRVAL_A => X"000000000", - SRVAL_B => X"000000000", - WRITE_MODE_A => "WRITE_FIRST", - WRITE_MODE_B => "WRITE_FIRST", - WRITE_WIDTH_A => 9, - WRITE_WIDTH_B => 9 - ) - port map ( - ADDRARDADDR(15) => '1', - ADDRARDADDR(14 downto 3) => addra(11 downto 0), - ADDRARDADDR(2 downto 0) => B"111", - ADDRBWRADDR(15) => '1', - ADDRBWRADDR(14 downto 3) => addrb(11 downto 0), - ADDRBWRADDR(2 downto 0) => B"111", - CASCADEINA => '0', - CASCADEINB => '0', - CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, - CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, - CLKARDCLK => clka, - CLKBWRCLK => clkb, - DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, - DIADI(31 downto 0) => B"00000000000000000000000000000000", - DIBDI(31 downto 0) => B"00000000000000000000000000000000", - DIPADIP(3 downto 0) => B"0000", - DIPBDIP(3 downto 0) => B"0000", - DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8), - DOADO(7 downto 0) => douta_array(7 downto 0), - DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8), - DOBDO(7 downto 0) => doutb_array(7 downto 0), - DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1), - DOPADOP(0) => douta_array(8), - DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1), - DOPBDOP(0) => doutb_array(8), - ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), - ENARDEN => addra(12), - ENBWREN => addrb(12), - INJECTDBITERR => '0', - INJECTSBITERR => '0', - RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), - REGCEAREGCE => '1', - REGCEB => '1', - RSTRAMARSTRAM => '0', - RSTRAMB => '0', - RSTREGARSTREG => '0', - RSTREGB => '0', - SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, - WEA(3 downto 0) => B"0000", - WEBWE(7 downto 0) => B"00000000" - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity COSLUT_10_16bit_blk_mem_gen_prim_width is - port ( - douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - doutb_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena_array : in STD_LOGIC_VECTOR ( 0 to 0 ); - enb_array : in STD_LOGIC_VECTOR ( 0 to 0 ); - addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 11 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of COSLUT_10_16bit_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; -end COSLUT_10_16bit_blk_mem_gen_prim_width; - -architecture STRUCTURE of COSLUT_10_16bit_blk_mem_gen_prim_width is -begin -\prim_init.ram\: entity work.COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init - port map ( - addra(11 downto 0) => addra(11 downto 0), - addrb(11 downto 0) => addrb(11 downto 0), - clka => clka, - clkb => clkb, - douta_array(8 downto 0) => douta_array(8 downto 0), - doutb_array(8 downto 0) => doutb_array(8 downto 0), - ena_array(0) => ena_array(0), - enb_array(0) => enb_array(0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized0\ is - port ( - douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - doutb_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width"; -end \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized0\; - -architecture STRUCTURE of \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized0\ is -begin -\prim_init.ram\: entity work.\COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized0\ - port map ( - addra(12 downto 0) => addra(12 downto 0), - addrb(12 downto 0) => addrb(12 downto 0), - clka => clka, - clkb => clkb, - douta_array(8 downto 0) => douta_array(8 downto 0), - doutb_array(8 downto 0) => doutb_array(8 downto 0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized1\ is - port ( - douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - doutb_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - ena_array : out STD_LOGIC_VECTOR ( 0 to 0 ); - enb_array : out STD_LOGIC_VECTOR ( 0 to 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width"; -end \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized1\; - -architecture STRUCTURE of \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized1\ is -begin -\prim_init.ram\: entity work.\COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized1\ - port map ( - addra(12 downto 0) => addra(12 downto 0), - addrb(12 downto 0) => addrb(12 downto 0), - clka => clka, - clkb => clkb, - douta_array(8 downto 0) => douta_array(8 downto 0), - doutb_array(8 downto 0) => doutb_array(8 downto 0), - ena_array(0) => ena_array(0), - enb_array(0) => enb_array(0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized2\ is - port ( - douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - doutb_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width"; -end \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized2\; - -architecture STRUCTURE of \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized2\ is -begin -\prim_init.ram\: entity work.\COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized2\ - port map ( - addra(12 downto 0) => addra(12 downto 0), - addrb(12 downto 0) => addrb(12 downto 0), - clka => clka, - clkb => clkb, - douta_array(8 downto 0) => douta_array(8 downto 0), - doutb_array(8 downto 0) => doutb_array(8 downto 0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity COSLUT_10_16bit_blk_mem_gen_generic_cstr is - port ( - douta : out STD_LOGIC_VECTOR ( 17 downto 0 ); - doutb : out STD_LOGIC_VECTOR ( 17 downto 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of COSLUT_10_16bit_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; -end COSLUT_10_16bit_blk_mem_gen_generic_cstr; - -architecture STRUCTURE of COSLUT_10_16bit_blk_mem_gen_generic_cstr is - signal douta_array : STD_LOGIC_VECTOR ( 35 downto 0 ); - signal doutb_array : STD_LOGIC_VECTOR ( 35 downto 0 ); - signal ena_array : STD_LOGIC_VECTOR ( 0 to 0 ); - signal enb_array : STD_LOGIC_VECTOR ( 0 to 0 ); -begin -\has_mux_a.A\: entity work.COSLUT_10_16bit_blk_mem_gen_mux - port map ( - addra(0) => addra(12), - clka => clka, - douta(17 downto 0) => douta(17 downto 0), - douta_array(35 downto 0) => douta_array(35 downto 0) - ); -\has_mux_b.B\: entity work.\COSLUT_10_16bit_blk_mem_gen_mux__parameterized0\ - port map ( - addrb(0) => addrb(12), - clkb => clkb, - doutb(17 downto 0) => doutb(17 downto 0), - doutb_array(35 downto 0) => doutb_array(35 downto 0) - ); -\ramloop[0].ram.r\: entity work.COSLUT_10_16bit_blk_mem_gen_prim_width - port map ( - addra(11 downto 0) => addra(11 downto 0), - addrb(11 downto 0) => addrb(11 downto 0), - clka => clka, - clkb => clkb, - douta_array(8 downto 0) => douta_array(8 downto 0), - doutb_array(8 downto 0) => doutb_array(8 downto 0), - ena_array(0) => ena_array(0), - enb_array(0) => enb_array(0) - ); -\ramloop[1].ram.r\: entity work.\COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized0\ - port map ( - addra(12 downto 0) => addra(12 downto 0), - addrb(12 downto 0) => addrb(12 downto 0), - clka => clka, - clkb => clkb, - douta_array(8 downto 0) => douta_array(26 downto 18), - doutb_array(8 downto 0) => doutb_array(26 downto 18) - ); -\ramloop[2].ram.r\: entity work.\COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized1\ - port map ( - addra(12 downto 0) => addra(12 downto 0), - addrb(12 downto 0) => addrb(12 downto 0), - clka => clka, - clkb => clkb, - douta_array(8 downto 0) => douta_array(17 downto 9), - doutb_array(8 downto 0) => doutb_array(17 downto 9), - ena_array(0) => ena_array(0), - enb_array(0) => enb_array(0) - ); -\ramloop[3].ram.r\: entity work.\COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized2\ - port map ( - addra(12 downto 0) => addra(12 downto 0), - addrb(12 downto 0) => addrb(12 downto 0), - clka => clka, - clkb => clkb, - douta_array(8 downto 0) => douta_array(35 downto 27), - doutb_array(8 downto 0) => doutb_array(35 downto 27) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity COSLUT_10_16bit_blk_mem_gen_top is - port ( - douta : out STD_LOGIC_VECTOR ( 17 downto 0 ); - doutb : out STD_LOGIC_VECTOR ( 17 downto 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of COSLUT_10_16bit_blk_mem_gen_top : entity is "blk_mem_gen_top"; -end COSLUT_10_16bit_blk_mem_gen_top; - -architecture STRUCTURE of COSLUT_10_16bit_blk_mem_gen_top is -begin -\valid.cstr\: entity work.COSLUT_10_16bit_blk_mem_gen_generic_cstr - port map ( - addra(12 downto 0) => addra(12 downto 0), - addrb(12 downto 0) => addrb(12 downto 0), - clka => clka, - clkb => clkb, - douta(17 downto 0) => douta(17 downto 0), - doutb(17 downto 0) => doutb(17 downto 0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity COSLUT_10_16bit_blk_mem_gen_v8_4_3_synth is - port ( - douta : out STD_LOGIC_VECTOR ( 17 downto 0 ); - doutb : out STD_LOGIC_VECTOR ( 17 downto 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of COSLUT_10_16bit_blk_mem_gen_v8_4_3_synth : entity is "blk_mem_gen_v8_4_3_synth"; -end COSLUT_10_16bit_blk_mem_gen_v8_4_3_synth; - -architecture STRUCTURE of COSLUT_10_16bit_blk_mem_gen_v8_4_3_synth is -begin -\gnbram.gnativebmg.native_blk_mem_gen\: entity work.COSLUT_10_16bit_blk_mem_gen_top - port map ( - addra(12 downto 0) => addra(12 downto 0), - addrb(12 downto 0) => addrb(12 downto 0), - clka => clka, - clkb => clkb, - douta(17 downto 0) => douta(17 downto 0), - doutb(17 downto 0) => doutb(17 downto 0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity COSLUT_10_16bit_blk_mem_gen_v8_4_3 is - port ( - clka : in STD_LOGIC; - rsta : in STD_LOGIC; - ena : in STD_LOGIC; - regcea : in STD_LOGIC; - wea : in STD_LOGIC_VECTOR ( 0 to 0 ); - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - dina : in STD_LOGIC_VECTOR ( 17 downto 0 ); - douta : out STD_LOGIC_VECTOR ( 17 downto 0 ); - clkb : in STD_LOGIC; - rstb : in STD_LOGIC; - enb : in STD_LOGIC; - regceb : in STD_LOGIC; - web : in STD_LOGIC_VECTOR ( 0 to 0 ); - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ); - dinb : in STD_LOGIC_VECTOR ( 17 downto 0 ); - doutb : out STD_LOGIC_VECTOR ( 17 downto 0 ); - injectsbiterr : in STD_LOGIC; - injectdbiterr : in STD_LOGIC; - eccpipece : in STD_LOGIC; - sbiterr : out STD_LOGIC; - dbiterr : out STD_LOGIC; - rdaddrecc : out STD_LOGIC_VECTOR ( 12 downto 0 ); - sleep : in STD_LOGIC; - deepsleep : in STD_LOGIC; - shutdown : in STD_LOGIC; - rsta_busy : out STD_LOGIC; - rstb_busy : out STD_LOGIC; - s_aclk : in STD_LOGIC; - s_aresetn : in STD_LOGIC; - s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_awvalid : in STD_LOGIC; - s_axi_awready : out STD_LOGIC; - s_axi_wdata : in STD_LOGIC_VECTOR ( 17 downto 0 ); - s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_wlast : in STD_LOGIC; - s_axi_wvalid : in STD_LOGIC; - s_axi_wready : out STD_LOGIC; - s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_bvalid : out STD_LOGIC; - s_axi_bready : in STD_LOGIC; - s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_arvalid : in STD_LOGIC; - s_axi_arready : out STD_LOGIC; - s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_rdata : out STD_LOGIC_VECTOR ( 17 downto 0 ); - s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_rlast : out STD_LOGIC; - s_axi_rvalid : out STD_LOGIC; - s_axi_rready : in STD_LOGIC; - s_axi_injectsbiterr : in STD_LOGIC; - s_axi_injectdbiterr : in STD_LOGIC; - s_axi_sbiterr : out STD_LOGIC; - s_axi_dbiterr : out STD_LOGIC; - s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 12 downto 0 ) - ); - attribute C_ADDRA_WIDTH : integer; - attribute C_ADDRA_WIDTH of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 13; - attribute C_ADDRB_WIDTH : integer; - attribute C_ADDRB_WIDTH of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 13; - attribute C_ALGORITHM : integer; - attribute C_ALGORITHM of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_AXI_ID_WIDTH : integer; - attribute C_AXI_ID_WIDTH of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 4; - attribute C_AXI_SLAVE_TYPE : integer; - attribute C_AXI_SLAVE_TYPE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_AXI_TYPE : integer; - attribute C_AXI_TYPE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_BYTE_SIZE : integer; - attribute C_BYTE_SIZE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 9; - attribute C_COMMON_CLK : integer; - attribute C_COMMON_CLK of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_COUNT_18K_BRAM : string; - attribute C_COUNT_18K_BRAM of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "0"; - attribute C_COUNT_36K_BRAM : string; - attribute C_COUNT_36K_BRAM of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "4"; - attribute C_CTRL_ECC_ALGO : string; - attribute C_CTRL_ECC_ALGO of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "NONE"; - attribute C_DEFAULT_DATA : string; - attribute C_DEFAULT_DATA of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "0"; - attribute C_DISABLE_WARN_BHV_COLL : integer; - attribute C_DISABLE_WARN_BHV_COLL of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_DISABLE_WARN_BHV_RANGE : integer; - attribute C_DISABLE_WARN_BHV_RANGE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_ELABORATION_DIR : string; - attribute C_ELABORATION_DIR of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "./"; - attribute C_ENABLE_32BIT_ADDRESS : integer; - attribute C_ENABLE_32BIT_ADDRESS of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_DEEPSLEEP_PIN : integer; - attribute C_EN_DEEPSLEEP_PIN of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_ECC_PIPE : integer; - attribute C_EN_ECC_PIPE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_RDADDRA_CHG : integer; - attribute C_EN_RDADDRA_CHG of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_RDADDRB_CHG : integer; - attribute C_EN_RDADDRB_CHG of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_SAFETY_CKT : integer; - attribute C_EN_SAFETY_CKT of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_SHUTDOWN_PIN : integer; - attribute C_EN_SHUTDOWN_PIN of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_SLEEP_PIN : integer; - attribute C_EN_SLEEP_PIN of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EST_POWER_SUMMARY : string; - attribute C_EST_POWER_SUMMARY of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "Estimated Power for IP : 9.414399 mW"; - attribute C_FAMILY : string; - attribute C_FAMILY of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "kintex7"; - attribute C_HAS_AXI_ID : integer; - attribute C_HAS_AXI_ID of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_ENA : integer; - attribute C_HAS_ENA of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_ENB : integer; - attribute C_HAS_ENB of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_INJECTERR : integer; - attribute C_HAS_INJECTERR of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_MEM_OUTPUT_REGS_A : integer; - attribute C_HAS_MEM_OUTPUT_REGS_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_HAS_MEM_OUTPUT_REGS_B : integer; - attribute C_HAS_MEM_OUTPUT_REGS_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_HAS_MUX_OUTPUT_REGS_A : integer; - attribute C_HAS_MUX_OUTPUT_REGS_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_HAS_MUX_OUTPUT_REGS_B : integer; - attribute C_HAS_MUX_OUTPUT_REGS_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_HAS_REGCEA : integer; - attribute C_HAS_REGCEA of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_REGCEB : integer; - attribute C_HAS_REGCEB of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_RSTA : integer; - attribute C_HAS_RSTA of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_RSTB : integer; - attribute C_HAS_RSTB of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; - attribute C_HAS_SOFTECC_INPUT_REGS_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; - attribute C_HAS_SOFTECC_OUTPUT_REGS_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_INITA_VAL : string; - attribute C_INITA_VAL of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "0"; - attribute C_INITB_VAL : string; - attribute C_INITB_VAL of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "0"; - attribute C_INIT_FILE : string; - attribute C_INIT_FILE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "COSLUT_10_16bit.mem"; - attribute C_INIT_FILE_NAME : string; - attribute C_INIT_FILE_NAME of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "COSLUT_10_16bit.mif"; - attribute C_INTERFACE_TYPE : integer; - attribute C_INTERFACE_TYPE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_LOAD_INIT_FILE : integer; - attribute C_LOAD_INIT_FILE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_MEM_TYPE : integer; - attribute C_MEM_TYPE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 4; - attribute C_MUX_PIPELINE_STAGES : integer; - attribute C_MUX_PIPELINE_STAGES of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_PRIM_TYPE : integer; - attribute C_PRIM_TYPE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_READ_DEPTH_A : integer; - attribute C_READ_DEPTH_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 8192; - attribute C_READ_DEPTH_B : integer; - attribute C_READ_DEPTH_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 8192; - attribute C_READ_LATENCY_A : integer; - attribute C_READ_LATENCY_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_READ_LATENCY_B : integer; - attribute C_READ_LATENCY_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_READ_WIDTH_A : integer; - attribute C_READ_WIDTH_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 18; - attribute C_READ_WIDTH_B : integer; - attribute C_READ_WIDTH_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 18; - attribute C_RSTRAM_A : integer; - attribute C_RSTRAM_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_RSTRAM_B : integer; - attribute C_RSTRAM_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_RST_PRIORITY_A : string; - attribute C_RST_PRIORITY_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "CE"; - attribute C_RST_PRIORITY_B : string; - attribute C_RST_PRIORITY_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "CE"; - attribute C_SIM_COLLISION_CHECK : string; - attribute C_SIM_COLLISION_CHECK of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "ALL"; - attribute C_USE_BRAM_BLOCK : integer; - attribute C_USE_BRAM_BLOCK of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_BYTE_WEA : integer; - attribute C_USE_BYTE_WEA of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_BYTE_WEB : integer; - attribute C_USE_BYTE_WEB of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_DEFAULT_DATA : integer; - attribute C_USE_DEFAULT_DATA of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_ECC : integer; - attribute C_USE_ECC of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_SOFTECC : integer; - attribute C_USE_SOFTECC of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_URAM : integer; - attribute C_USE_URAM of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_WEA_WIDTH : integer; - attribute C_WEA_WIDTH of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_WEB_WIDTH : integer; - attribute C_WEB_WIDTH of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_WRITE_DEPTH_A : integer; - attribute C_WRITE_DEPTH_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 8192; - attribute C_WRITE_DEPTH_B : integer; - attribute C_WRITE_DEPTH_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 8192; - attribute C_WRITE_MODE_A : string; - attribute C_WRITE_MODE_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "WRITE_FIRST"; - attribute C_WRITE_MODE_B : string; - attribute C_WRITE_MODE_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "WRITE_FIRST"; - attribute C_WRITE_WIDTH_A : integer; - attribute C_WRITE_WIDTH_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 18; - attribute C_WRITE_WIDTH_B : integer; - attribute C_WRITE_WIDTH_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 18; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "kintex7"; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "blk_mem_gen_v8_4_3"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "yes"; -end COSLUT_10_16bit_blk_mem_gen_v8_4_3; - -architecture STRUCTURE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 is - signal \\ : STD_LOGIC; -begin - dbiterr <= \\; - rdaddrecc(12) <= \\; - rdaddrecc(11) <= \\; - rdaddrecc(10) <= \\; - rdaddrecc(9) <= \\; - rdaddrecc(8) <= \\; - rdaddrecc(7) <= \\; - rdaddrecc(6) <= \\; - rdaddrecc(5) <= \\; - rdaddrecc(4) <= \\; - rdaddrecc(3) <= \\; - rdaddrecc(2) <= \\; - rdaddrecc(1) <= \\; - rdaddrecc(0) <= \\; - rsta_busy <= \\; - rstb_busy <= \\; - s_axi_arready <= \\; - s_axi_awready <= \\; - s_axi_bid(3) <= \\; - s_axi_bid(2) <= \\; - s_axi_bid(1) <= \\; - s_axi_bid(0) <= \\; - s_axi_bresp(1) <= \\; - s_axi_bresp(0) <= \\; - s_axi_bvalid <= \\; - s_axi_dbiterr <= \\; - s_axi_rdaddrecc(12) <= \\; - s_axi_rdaddrecc(11) <= \\; - s_axi_rdaddrecc(10) <= \\; - s_axi_rdaddrecc(9) <= \\; - s_axi_rdaddrecc(8) <= \\; - s_axi_rdaddrecc(7) <= \\; - s_axi_rdaddrecc(6) <= \\; - s_axi_rdaddrecc(5) <= \\; - s_axi_rdaddrecc(4) <= \\; - s_axi_rdaddrecc(3) <= \\; - s_axi_rdaddrecc(2) <= \\; - s_axi_rdaddrecc(1) <= \\; - s_axi_rdaddrecc(0) <= \\; - s_axi_rdata(17) <= \\; - s_axi_rdata(16) <= \\; - s_axi_rdata(15) <= \\; - s_axi_rdata(14) <= \\; - s_axi_rdata(13) <= \\; - s_axi_rdata(12) <= \\; - s_axi_rdata(11) <= \\; - s_axi_rdata(10) <= \\; - s_axi_rdata(9) <= \\; - s_axi_rdata(8) <= \\; - s_axi_rdata(7) <= \\; - s_axi_rdata(6) <= \\; - s_axi_rdata(5) <= \\; - s_axi_rdata(4) <= \\; - s_axi_rdata(3) <= \\; - s_axi_rdata(2) <= \\; - s_axi_rdata(1) <= \\; - s_axi_rdata(0) <= \\; - s_axi_rid(3) <= \\; - s_axi_rid(2) <= \\; - s_axi_rid(1) <= \\; - s_axi_rid(0) <= \\; - s_axi_rlast <= \\; - s_axi_rresp(1) <= \\; - s_axi_rresp(0) <= \\; - s_axi_rvalid <= \\; - s_axi_sbiterr <= \\; - s_axi_wready <= \\; - sbiterr <= \\; -GND: unisim.vcomponents.GND - port map ( - G => \\ - ); -inst_blk_mem_gen: entity work.COSLUT_10_16bit_blk_mem_gen_v8_4_3_synth - port map ( - addra(12 downto 0) => addra(12 downto 0), - addrb(12 downto 0) => addrb(12 downto 0), - clka => clka, - clkb => clkb, - douta(17 downto 0) => douta(17 downto 0), - doutb(17 downto 0) => doutb(17 downto 0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity COSLUT_10_16bit is - port ( - clka : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - douta : out STD_LOGIC_VECTOR ( 17 downto 0 ); - clkb : in STD_LOGIC; - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ); - doutb : out STD_LOGIC_VECTOR ( 17 downto 0 ) - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of COSLUT_10_16bit : entity is true; - attribute CHECK_LICENSE_TYPE : string; - attribute CHECK_LICENSE_TYPE of COSLUT_10_16bit : entity is "COSLUT_10_16bit,blk_mem_gen_v8_4_3,{}"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of COSLUT_10_16bit : entity is "yes"; - attribute x_core_info : string; - attribute x_core_info of COSLUT_10_16bit : entity is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; -end COSLUT_10_16bit; - -architecture STRUCTURE of COSLUT_10_16bit is - signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; - signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 ); - signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 ); - signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 ); - signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - attribute C_ADDRA_WIDTH : integer; - attribute C_ADDRA_WIDTH of U0 : label is 13; - attribute C_ADDRB_WIDTH : integer; - attribute C_ADDRB_WIDTH of U0 : label is 13; - attribute C_ALGORITHM : integer; - attribute C_ALGORITHM of U0 : label is 1; - attribute C_AXI_ID_WIDTH : integer; - attribute C_AXI_ID_WIDTH of U0 : label is 4; - attribute C_AXI_SLAVE_TYPE : integer; - attribute C_AXI_SLAVE_TYPE of U0 : label is 0; - attribute C_AXI_TYPE : integer; - attribute C_AXI_TYPE of U0 : label is 1; - attribute C_BYTE_SIZE : integer; - attribute C_BYTE_SIZE of U0 : label is 9; - attribute C_COMMON_CLK : integer; - attribute C_COMMON_CLK of U0 : label is 0; - attribute C_COUNT_18K_BRAM : string; - attribute C_COUNT_18K_BRAM of U0 : label is "0"; - attribute C_COUNT_36K_BRAM : string; - attribute C_COUNT_36K_BRAM of U0 : label is "4"; - attribute C_CTRL_ECC_ALGO : string; - attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; - attribute C_DEFAULT_DATA : string; - attribute C_DEFAULT_DATA of U0 : label is "0"; - attribute C_DISABLE_WARN_BHV_COLL : integer; - attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; - attribute C_DISABLE_WARN_BHV_RANGE : integer; - attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; - attribute C_ELABORATION_DIR : string; - attribute C_ELABORATION_DIR of U0 : label is "./"; - attribute C_ENABLE_32BIT_ADDRESS : integer; - attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; - attribute C_EN_DEEPSLEEP_PIN : integer; - attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; - attribute C_EN_ECC_PIPE : integer; - attribute C_EN_ECC_PIPE of U0 : label is 0; - attribute C_EN_RDADDRA_CHG : integer; - attribute C_EN_RDADDRA_CHG of U0 : label is 0; - attribute C_EN_RDADDRB_CHG : integer; - attribute C_EN_RDADDRB_CHG of U0 : label is 0; - attribute C_EN_SAFETY_CKT : integer; - attribute C_EN_SAFETY_CKT of U0 : label is 0; - attribute C_EN_SHUTDOWN_PIN : integer; - attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; - attribute C_EN_SLEEP_PIN : integer; - attribute C_EN_SLEEP_PIN of U0 : label is 0; - attribute C_EST_POWER_SUMMARY : string; - attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 9.414399 mW"; - attribute C_FAMILY : string; - attribute C_FAMILY of U0 : label is "kintex7"; - attribute C_HAS_AXI_ID : integer; - attribute C_HAS_AXI_ID of U0 : label is 0; - attribute C_HAS_ENA : integer; - attribute C_HAS_ENA of U0 : label is 0; - attribute C_HAS_ENB : integer; - attribute C_HAS_ENB of U0 : label is 0; - attribute C_HAS_INJECTERR : integer; - attribute C_HAS_INJECTERR of U0 : label is 0; - attribute C_HAS_MEM_OUTPUT_REGS_A : integer; - attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1; - attribute C_HAS_MEM_OUTPUT_REGS_B : integer; - attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 1; - attribute C_HAS_MUX_OUTPUT_REGS_A : integer; - attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 1; - attribute C_HAS_MUX_OUTPUT_REGS_B : integer; - attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 1; - attribute C_HAS_REGCEA : integer; - attribute C_HAS_REGCEA of U0 : label is 0; - attribute C_HAS_REGCEB : integer; - attribute C_HAS_REGCEB of U0 : label is 0; - attribute C_HAS_RSTA : integer; - attribute C_HAS_RSTA of U0 : label is 0; - attribute C_HAS_RSTB : integer; - attribute C_HAS_RSTB of U0 : label is 0; - attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; - attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; - attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; - attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; - attribute C_INITA_VAL : string; - attribute C_INITA_VAL of U0 : label is "0"; - attribute C_INITB_VAL : string; - attribute C_INITB_VAL of U0 : label is "0"; - attribute C_INIT_FILE : string; - attribute C_INIT_FILE of U0 : label is "COSLUT_10_16bit.mem"; - attribute C_INIT_FILE_NAME : string; - attribute C_INIT_FILE_NAME of U0 : label is "COSLUT_10_16bit.mif"; - attribute C_INTERFACE_TYPE : integer; - attribute C_INTERFACE_TYPE of U0 : label is 0; - attribute C_LOAD_INIT_FILE : integer; - attribute C_LOAD_INIT_FILE of U0 : label is 1; - attribute C_MEM_TYPE : integer; - attribute C_MEM_TYPE of U0 : label is 4; - attribute C_MUX_PIPELINE_STAGES : integer; - attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; - attribute C_PRIM_TYPE : integer; - attribute C_PRIM_TYPE of U0 : label is 1; - attribute C_READ_DEPTH_A : integer; - attribute C_READ_DEPTH_A of U0 : label is 8192; - attribute C_READ_DEPTH_B : integer; - attribute C_READ_DEPTH_B of U0 : label is 8192; - attribute C_READ_LATENCY_A : integer; - attribute C_READ_LATENCY_A of U0 : label is 1; - attribute C_READ_LATENCY_B : integer; - attribute C_READ_LATENCY_B of U0 : label is 1; - attribute C_READ_WIDTH_A : integer; - attribute C_READ_WIDTH_A of U0 : label is 18; - attribute C_READ_WIDTH_B : integer; - attribute C_READ_WIDTH_B of U0 : label is 18; - attribute C_RSTRAM_A : integer; - attribute C_RSTRAM_A of U0 : label is 0; - attribute C_RSTRAM_B : integer; - attribute C_RSTRAM_B of U0 : label is 0; - attribute C_RST_PRIORITY_A : string; - attribute C_RST_PRIORITY_A of U0 : label is "CE"; - attribute C_RST_PRIORITY_B : string; - attribute C_RST_PRIORITY_B of U0 : label is "CE"; - attribute C_SIM_COLLISION_CHECK : string; - attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; - attribute C_USE_BRAM_BLOCK : integer; - attribute C_USE_BRAM_BLOCK of U0 : label is 0; - attribute C_USE_BYTE_WEA : integer; - attribute C_USE_BYTE_WEA of U0 : label is 0; - attribute C_USE_BYTE_WEB : integer; - attribute C_USE_BYTE_WEB of U0 : label is 0; - attribute C_USE_DEFAULT_DATA : integer; - attribute C_USE_DEFAULT_DATA of U0 : label is 0; - attribute C_USE_ECC : integer; - attribute C_USE_ECC of U0 : label is 0; - attribute C_USE_SOFTECC : integer; - attribute C_USE_SOFTECC of U0 : label is 0; - attribute C_USE_URAM : integer; - attribute C_USE_URAM of U0 : label is 0; - attribute C_WEA_WIDTH : integer; - attribute C_WEA_WIDTH of U0 : label is 1; - attribute C_WEB_WIDTH : integer; - attribute C_WEB_WIDTH of U0 : label is 1; - attribute C_WRITE_DEPTH_A : integer; - attribute C_WRITE_DEPTH_A of U0 : label is 8192; - attribute C_WRITE_DEPTH_B : integer; - attribute C_WRITE_DEPTH_B of U0 : label is 8192; - attribute C_WRITE_MODE_A : string; - attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST"; - attribute C_WRITE_MODE_B : string; - attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; - attribute C_WRITE_WIDTH_A : integer; - attribute C_WRITE_WIDTH_A of U0 : label is 18; - attribute C_WRITE_WIDTH_B : integer; - attribute C_WRITE_WIDTH_B of U0 : label is 18; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of U0 : label is "kintex7"; - attribute downgradeipidentifiedwarnings of U0 : label is "yes"; - attribute x_interface_info : string; - attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; - attribute x_interface_parameter : string; - attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1"; - attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK"; - attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1"; - attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; - attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR"; - attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; - attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT"; -begin -U0: entity work.COSLUT_10_16bit_blk_mem_gen_v8_4_3 - port map ( - addra(12 downto 0) => addra(12 downto 0), - addrb(12 downto 0) => addrb(12 downto 0), - clka => clka, - clkb => clkb, - dbiterr => NLW_U0_dbiterr_UNCONNECTED, - deepsleep => '0', - dina(17 downto 0) => B"000000000000000000", - dinb(17 downto 0) => B"000000000000000000", - douta(17 downto 0) => douta(17 downto 0), - doutb(17 downto 0) => doutb(17 downto 0), - eccpipece => '0', - ena => '0', - enb => '0', - injectdbiterr => '0', - injectsbiterr => '0', - rdaddrecc(12 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(12 downto 0), - regcea => '0', - regceb => '0', - rsta => '0', - rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, - rstb => '0', - rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, - s_aclk => '0', - s_aresetn => '0', - s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", - s_axi_arburst(1 downto 0) => B"00", - s_axi_arid(3 downto 0) => B"0000", - s_axi_arlen(7 downto 0) => B"00000000", - s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, - s_axi_arsize(2 downto 0) => B"000", - s_axi_arvalid => '0', - s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", - s_axi_awburst(1 downto 0) => B"00", - s_axi_awid(3 downto 0) => B"0000", - s_axi_awlen(7 downto 0) => B"00000000", - s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, - s_axi_awsize(2 downto 0) => B"000", - s_axi_awvalid => '0', - s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), - s_axi_bready => '0', - s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), - s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, - s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, - s_axi_injectdbiterr => '0', - s_axi_injectsbiterr => '0', - s_axi_rdaddrecc(12 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(12 downto 0), - s_axi_rdata(17 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(17 downto 0), - s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), - s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, - s_axi_rready => '0', - s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), - s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, - s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, - s_axi_wdata(17 downto 0) => B"000000000000000000", - s_axi_wlast => '0', - s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, - s_axi_wstrb(0) => '0', - s_axi_wvalid => '0', - sbiterr => NLW_U0_sbiterr_UNCONNECTED, - shutdown => '0', - sleep => '0', - wea(0) => '0', - web(0) => '0' - ); -end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit_stub.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit_stub.vhdl deleted file mode 100644 index 6c6002c4..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit_stub.vhdl +++ /dev/null @@ -1,35 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:34:22 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.vhdl --- Design : COSLUT_10_16bit --- Purpose : Stub declaration of top-level module interface --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity COSLUT_10_16bit is - Port ( - clka : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - douta : out STD_LOGIC_VECTOR ( 17 downto 0 ); - clkb : in STD_LOGIC; - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ); - doutb : out STD_LOGIC_VECTOR ( 17 downto 0 ) - ); - -end COSLUT_10_16bit; - -architecture stub of COSLUT_10_16bit is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clka,addra[12:0],douta[17:0],clkb,addrb[12:0],doutb[17:0]"; -attribute x_core_info : string; -attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; -begin -end; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v deleted file mode 100644 index eae64edb..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v +++ /dev/null @@ -1,221 +0,0 @@ -// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - - -// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 -// IP Revision: 3 - -`timescale 1ns/1ps - -(* DowngradeIPIdentifiedWarnings = "yes" *) -module COSLUT_10_16bit ( - clka, - addra, - douta, - clkb, - addrb, - doutb -); - -(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) -input wire clka; -(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) -input wire [12 : 0] addra; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) -(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) -output wire [17 : 0] douta; -(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) -input wire clkb; -(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) -input wire [12 : 0] addrb; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) -(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) -output wire [17 : 0] doutb; - - blk_mem_gen_v8_4_3 #( - .C_FAMILY("kintex7"), - .C_XDEVICEFAMILY("kintex7"), - .C_ELABORATION_DIR("./"), - .C_INTERFACE_TYPE(0), - .C_AXI_TYPE(1), - .C_AXI_SLAVE_TYPE(0), - .C_USE_BRAM_BLOCK(0), - .C_ENABLE_32BIT_ADDRESS(0), - .C_CTRL_ECC_ALGO("NONE"), - .C_HAS_AXI_ID(0), - .C_AXI_ID_WIDTH(4), - .C_MEM_TYPE(4), - .C_BYTE_SIZE(9), - .C_ALGORITHM(1), - .C_PRIM_TYPE(1), - .C_LOAD_INIT_FILE(1), - .C_INIT_FILE_NAME("COSLUT_10_16bit.mif"), - .C_INIT_FILE("COSLUT_10_16bit.mem"), - .C_USE_DEFAULT_DATA(0), - .C_DEFAULT_DATA("0"), - .C_HAS_RSTA(0), - .C_RST_PRIORITY_A("CE"), - .C_RSTRAM_A(0), - .C_INITA_VAL("0"), - .C_HAS_ENA(0), - .C_HAS_REGCEA(0), - .C_USE_BYTE_WEA(0), - .C_WEA_WIDTH(1), - .C_WRITE_MODE_A("WRITE_FIRST"), - .C_WRITE_WIDTH_A(18), - .C_READ_WIDTH_A(18), - .C_WRITE_DEPTH_A(8192), - .C_READ_DEPTH_A(8192), - .C_ADDRA_WIDTH(13), - .C_HAS_RSTB(0), - .C_RST_PRIORITY_B("CE"), - .C_RSTRAM_B(0), - .C_INITB_VAL("0"), - .C_HAS_ENB(0), - .C_HAS_REGCEB(0), - .C_USE_BYTE_WEB(0), - .C_WEB_WIDTH(1), - .C_WRITE_MODE_B("WRITE_FIRST"), - .C_WRITE_WIDTH_B(18), - .C_READ_WIDTH_B(18), - .C_WRITE_DEPTH_B(8192), - .C_READ_DEPTH_B(8192), - .C_ADDRB_WIDTH(13), - .C_HAS_MEM_OUTPUT_REGS_A(1), - .C_HAS_MEM_OUTPUT_REGS_B(1), - .C_HAS_MUX_OUTPUT_REGS_A(1), - .C_HAS_MUX_OUTPUT_REGS_B(1), - .C_MUX_PIPELINE_STAGES(0), - .C_HAS_SOFTECC_INPUT_REGS_A(0), - .C_HAS_SOFTECC_OUTPUT_REGS_B(0), - .C_USE_SOFTECC(0), - .C_USE_ECC(0), - .C_EN_ECC_PIPE(0), - .C_READ_LATENCY_A(1), - .C_READ_LATENCY_B(1), - .C_HAS_INJECTERR(0), - .C_SIM_COLLISION_CHECK("ALL"), - .C_COMMON_CLK(0), - .C_DISABLE_WARN_BHV_COLL(0), - .C_EN_SLEEP_PIN(0), - .C_USE_URAM(0), - .C_EN_RDADDRA_CHG(0), - .C_EN_RDADDRB_CHG(0), - .C_EN_DEEPSLEEP_PIN(0), - .C_EN_SHUTDOWN_PIN(0), - .C_EN_SAFETY_CKT(0), - .C_DISABLE_WARN_BHV_RANGE(0), - .C_COUNT_36K_BRAM("4"), - .C_COUNT_18K_BRAM("0"), - .C_EST_POWER_SUMMARY("Estimated Power for IP : 9.414399 mW") - ) inst ( - .clka(clka), - .rsta(1'D0), - .ena(1'D0), - .regcea(1'D0), - .wea(1'B0), - .addra(addra), - .dina(18'B0), - .douta(douta), - .clkb(clkb), - .rstb(1'D0), - .enb(1'D0), - .regceb(1'D0), - .web(1'B0), - .addrb(addrb), - .dinb(18'B0), - .doutb(doutb), - .injectsbiterr(1'D0), - .injectdbiterr(1'D0), - .eccpipece(1'D0), - .sbiterr(), - .dbiterr(), - .rdaddrecc(), - .sleep(1'D0), - .deepsleep(1'D0), - .shutdown(1'D0), - .rsta_busy(), - .rstb_busy(), - .s_aclk(1'H0), - .s_aresetn(1'D0), - .s_axi_awid(4'B0), - .s_axi_awaddr(32'B0), - .s_axi_awlen(8'B0), - .s_axi_awsize(3'B0), - .s_axi_awburst(2'B0), - .s_axi_awvalid(1'D0), - .s_axi_awready(), - .s_axi_wdata(18'B0), - .s_axi_wstrb(1'B0), - .s_axi_wlast(1'D0), - .s_axi_wvalid(1'D0), - .s_axi_wready(), - .s_axi_bid(), - .s_axi_bresp(), - .s_axi_bvalid(), - .s_axi_bready(1'D0), - .s_axi_arid(4'B0), - .s_axi_araddr(32'B0), - .s_axi_arlen(8'B0), - .s_axi_arsize(3'B0), - .s_axi_arburst(2'B0), - .s_axi_arvalid(1'D0), - .s_axi_arready(), - .s_axi_rid(), - .s_axi_rdata(), - .s_axi_rresp(), - .s_axi_rlast(), - .s_axi_rvalid(), - .s_axi_rready(1'D0), - .s_axi_injectsbiterr(1'D0), - .s_axi_injectdbiterr(1'D0), - .s_axi_sbiterr(), - .s_axi_dbiterr(), - .s_axi_rdaddrecc() - ); -endmodule diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/GaussFir_12m.veo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/GaussFir_12m.veo deleted file mode 100644 index dc6893d6..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/GaussFir_12m.veo +++ /dev/null @@ -1,70 +0,0 @@ -// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:fir_compiler:7.2 -// IP Revision: 12 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -GaussFir_12m your_instance_name ( - .aclk(aclk), // input wire aclk - .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid - .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready - .s_axis_data_tdata(s_axis_data_tdata), // input wire [7 : 0] s_axis_data_tdata - .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid - .m_axis_data_tdata(m_axis_data_tdata) // output wire [15 : 0] m_axis_data_tdata -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file GaussFir_12m.v when simulating -// the core, GaussFir_12m. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/GaussFir_12m.vho b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/GaussFir_12m.vho deleted file mode 100644 index 04330f05..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/GaussFir_12m.vho +++ /dev/null @@ -1,85 +0,0 @@ --- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:fir_compiler:7.2 --- IP Revision: 12 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT GaussFir_12m - PORT ( - aclk : IN STD_LOGIC; - s_axis_data_tvalid : IN STD_LOGIC; - s_axis_data_tready : OUT STD_LOGIC; - s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - m_axis_data_tvalid : OUT STD_LOGIC; - m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : GaussFir_12m - PORT MAP ( - aclk => aclk, - s_axis_data_tvalid => s_axis_data_tvalid, - s_axis_data_tready => s_axis_data_tready, - s_axis_data_tdata => s_axis_data_tdata, - m_axis_data_tvalid => m_axis_data_tvalid, - m_axis_data_tdata => m_axis_data_tdata - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file GaussFir_12m.vhd when simulating --- the core, GaussFir_12m. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/GaussFir_12m_sim_netlist.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/GaussFir_12m_sim_netlist.v deleted file mode 100644 index 733517dd..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/GaussFir_12m_sim_netlist.v +++ /dev/null @@ -1,2400 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:33:48 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_sim_netlist.v -// Design : GaussFir_12m -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* CHECK_LICENSE_TYPE = "GaussFir_12m,fir_compiler_v7_2_12,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *) -(* NotValidForBitStream *) -module GaussFir_12m - (aclk, - s_axis_data_tvalid, - s_axis_data_tready, - s_axis_data_tdata, - m_axis_data_tvalid, - m_axis_data_tdata); - (* x_interface_info = "xilinx.com:signal:clock:1.0 aclk_intf CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *) input aclk; - (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) input s_axis_data_tvalid; - (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY" *) output s_axis_data_tready; - (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA" *) input [7:0]s_axis_data_tdata; - (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) output m_axis_data_tvalid; - (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA" *) output [15:0]m_axis_data_tdata; - - wire aclk; - wire [15:0]m_axis_data_tdata; - wire m_axis_data_tvalid; - wire [7:0]s_axis_data_tdata; - wire s_axis_data_tready; - wire s_axis_data_tvalid; - wire NLW_U0_event_s_config_tlast_missing_UNCONNECTED; - wire NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED; - wire NLW_U0_event_s_data_chanid_incorrect_UNCONNECTED; - wire NLW_U0_event_s_data_tlast_missing_UNCONNECTED; - wire NLW_U0_event_s_data_tlast_unexpected_UNCONNECTED; - wire NLW_U0_event_s_reload_tlast_missing_UNCONNECTED; - wire NLW_U0_event_s_reload_tlast_unexpected_UNCONNECTED; - wire NLW_U0_m_axis_data_tlast_UNCONNECTED; - wire NLW_U0_s_axis_config_tready_UNCONNECTED; - wire NLW_U0_s_axis_reload_tready_UNCONNECTED; - wire [0:0]NLW_U0_m_axis_data_tuser_UNCONNECTED; - - (* C_ACCUM_OP_PATH_WIDTHS = "15" *) - (* C_ACCUM_PATH_WIDTHS = "15" *) - (* C_CHANNEL_PATTERN = "fixed" *) - (* C_COEF_FILE = "GaussFir_12m.mif" *) - (* C_COEF_FILE_LINES = "20" *) - (* C_COEF_MEMTYPE = "2" *) - (* C_COEF_MEM_PACKING = "0" *) - (* C_COEF_PATH_SIGN = "1" *) - (* C_COEF_PATH_SRC = "0" *) - (* C_COEF_PATH_WIDTHS = "14" *) - (* C_COEF_RELOAD = "0" *) - (* C_COEF_WIDTH = "14" *) - (* C_COL_CONFIG = "5" *) - (* C_COL_MODE = "1" *) - (* C_COL_PIPE_LEN = "4" *) - (* C_COMPONENT_NAME = "GaussFir_12m" *) - (* C_CONFIG_PACKET_SIZE = "0" *) - (* C_CONFIG_SYNC_MODE = "0" *) - (* C_CONFIG_TDATA_WIDTH = "1" *) - (* C_DATAPATH_MEMTYPE = "0" *) - (* C_DATA_HAS_TLAST = "0" *) - (* C_DATA_IP_PATH_WIDTHS = "2" *) - (* C_DATA_MEMTYPE = "0" *) - (* C_DATA_MEM_PACKING = "0" *) - (* C_DATA_PATH_PSAMP_SRC = "0" *) - (* C_DATA_PATH_SIGN = "0" *) - (* C_DATA_PATH_SRC = "0" *) - (* C_DATA_PATH_WIDTHS = "2" *) - (* C_DATA_PX_PATH_WIDTHS = "2" *) - (* C_DATA_WIDTH = "2" *) - (* C_DECIM_RATE = "1" *) - (* C_ELABORATION_DIR = "./" *) - (* C_EXT_MULT_CNFG = "none" *) - (* C_FILTER_TYPE = "2" *) - (* C_FILTS_PACKED = "0" *) - (* C_HAS_ACLKEN = "0" *) - (* C_HAS_ARESETn = "0" *) - (* C_HAS_CONFIG_CHANNEL = "0" *) - (* C_INPUT_RATE = "4" *) - (* C_INTERP_RATE = "4" *) - (* C_IPBUFF_MEMTYPE = "0" *) - (* C_LATENCY = "11" *) - (* C_MEM_ARRANGEMENT = "2" *) - (* C_M_DATA_HAS_TREADY = "0" *) - (* C_M_DATA_HAS_TUSER = "0" *) - (* C_M_DATA_TDATA_WIDTH = "16" *) - (* C_M_DATA_TUSER_WIDTH = "1" *) - (* C_NUM_CHANNELS = "1" *) - (* C_NUM_FILTS = "1" *) - (* C_NUM_MADDS = "5" *) - (* C_NUM_RELOAD_SLOTS = "1" *) - (* C_NUM_TAPS = "17" *) - (* C_OPBUFF_MEMTYPE = "0" *) - (* C_OPTIMIZATION = "0" *) - (* C_OPT_MADDS = "none" *) - (* C_OP_PATH_PSAMP_SRC = "0" *) - (* C_OUTPUT_PATH_WIDTHS = "15" *) - (* C_OUTPUT_RATE = "1" *) - (* C_OUTPUT_WIDTH = "15" *) - (* C_OVERSAMPLING_RATE = "1" *) - (* C_PX_PATH_SRC = "0" *) - (* C_RELOAD_TDATA_WIDTH = "1" *) - (* C_ROUND_MODE = "0" *) - (* C_SYMMETRY = "0" *) - (* C_S_DATA_HAS_FIFO = "0" *) - (* C_S_DATA_HAS_TUSER = "0" *) - (* C_S_DATA_TDATA_WIDTH = "8" *) - (* C_S_DATA_TUSER_WIDTH = "1" *) - (* C_XDEVICEFAMILY = "kintex7" *) - (* C_ZERO_PACKING_FACTOR = "1" *) - (* downgradeipidentifiedwarnings = "yes" *) - GaussFir_12m_fir_compiler_v7_2_12 U0 - (.aclk(aclk), - .aclken(1'b1), - .aresetn(1'b1), - .event_s_config_tlast_missing(NLW_U0_event_s_config_tlast_missing_UNCONNECTED), - .event_s_config_tlast_unexpected(NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED), - .event_s_data_chanid_incorrect(NLW_U0_event_s_data_chanid_incorrect_UNCONNECTED), - .event_s_data_tlast_missing(NLW_U0_event_s_data_tlast_missing_UNCONNECTED), - .event_s_data_tlast_unexpected(NLW_U0_event_s_data_tlast_unexpected_UNCONNECTED), - .event_s_reload_tlast_missing(NLW_U0_event_s_reload_tlast_missing_UNCONNECTED), - .event_s_reload_tlast_unexpected(NLW_U0_event_s_reload_tlast_unexpected_UNCONNECTED), - .m_axis_data_tdata(m_axis_data_tdata), - .m_axis_data_tlast(NLW_U0_m_axis_data_tlast_UNCONNECTED), - .m_axis_data_tready(1'b1), - .m_axis_data_tuser(NLW_U0_m_axis_data_tuser_UNCONNECTED[0]), - .m_axis_data_tvalid(m_axis_data_tvalid), - .s_axis_config_tdata(1'b0), - .s_axis_config_tlast(1'b0), - .s_axis_config_tready(NLW_U0_s_axis_config_tready_UNCONNECTED), - .s_axis_config_tvalid(1'b0), - .s_axis_data_tdata(s_axis_data_tdata), - .s_axis_data_tlast(1'b0), - .s_axis_data_tready(s_axis_data_tready), - .s_axis_data_tuser(1'b0), - .s_axis_data_tvalid(s_axis_data_tvalid), - .s_axis_reload_tdata(1'b0), - .s_axis_reload_tlast(1'b0), - .s_axis_reload_tready(NLW_U0_s_axis_reload_tready_UNCONNECTED), - .s_axis_reload_tvalid(1'b0)); -endmodule - -(* C_ACCUM_OP_PATH_WIDTHS = "15" *) (* C_ACCUM_PATH_WIDTHS = "15" *) (* C_CHANNEL_PATTERN = "fixed" *) -(* C_COEF_FILE = "GaussFir_12m.mif" *) (* C_COEF_FILE_LINES = "20" *) (* C_COEF_MEMTYPE = "2" *) -(* C_COEF_MEM_PACKING = "0" *) (* C_COEF_PATH_SIGN = "1" *) (* C_COEF_PATH_SRC = "0" *) -(* C_COEF_PATH_WIDTHS = "14" *) (* C_COEF_RELOAD = "0" *) (* C_COEF_WIDTH = "14" *) -(* C_COL_CONFIG = "5" *) (* C_COL_MODE = "1" *) (* C_COL_PIPE_LEN = "4" *) -(* C_COMPONENT_NAME = "GaussFir_12m" *) (* C_CONFIG_PACKET_SIZE = "0" *) (* C_CONFIG_SYNC_MODE = "0" *) -(* C_CONFIG_TDATA_WIDTH = "1" *) (* C_DATAPATH_MEMTYPE = "0" *) (* C_DATA_HAS_TLAST = "0" *) -(* C_DATA_IP_PATH_WIDTHS = "2" *) (* C_DATA_MEMTYPE = "0" *) (* C_DATA_MEM_PACKING = "0" *) -(* C_DATA_PATH_PSAMP_SRC = "0" *) (* C_DATA_PATH_SIGN = "0" *) (* C_DATA_PATH_SRC = "0" *) -(* C_DATA_PATH_WIDTHS = "2" *) (* C_DATA_PX_PATH_WIDTHS = "2" *) (* C_DATA_WIDTH = "2" *) -(* C_DECIM_RATE = "1" *) (* C_ELABORATION_DIR = "./" *) (* C_EXT_MULT_CNFG = "none" *) -(* C_FILTER_TYPE = "2" *) (* C_FILTS_PACKED = "0" *) (* C_HAS_ACLKEN = "0" *) -(* C_HAS_ARESETn = "0" *) (* C_HAS_CONFIG_CHANNEL = "0" *) (* C_INPUT_RATE = "4" *) -(* C_INTERP_RATE = "4" *) (* C_IPBUFF_MEMTYPE = "0" *) (* C_LATENCY = "11" *) -(* C_MEM_ARRANGEMENT = "2" *) (* C_M_DATA_HAS_TREADY = "0" *) (* C_M_DATA_HAS_TUSER = "0" *) -(* C_M_DATA_TDATA_WIDTH = "16" *) (* C_M_DATA_TUSER_WIDTH = "1" *) (* C_NUM_CHANNELS = "1" *) -(* C_NUM_FILTS = "1" *) (* C_NUM_MADDS = "5" *) (* C_NUM_RELOAD_SLOTS = "1" *) -(* C_NUM_TAPS = "17" *) (* C_OPBUFF_MEMTYPE = "0" *) (* C_OPTIMIZATION = "0" *) -(* C_OPT_MADDS = "none" *) (* C_OP_PATH_PSAMP_SRC = "0" *) (* C_OUTPUT_PATH_WIDTHS = "15" *) -(* C_OUTPUT_RATE = "1" *) (* C_OUTPUT_WIDTH = "15" *) (* C_OVERSAMPLING_RATE = "1" *) -(* C_PX_PATH_SRC = "0" *) (* C_RELOAD_TDATA_WIDTH = "1" *) (* C_ROUND_MODE = "0" *) -(* C_SYMMETRY = "0" *) (* C_S_DATA_HAS_FIFO = "0" *) (* C_S_DATA_HAS_TUSER = "0" *) -(* C_S_DATA_TDATA_WIDTH = "8" *) (* C_S_DATA_TUSER_WIDTH = "1" *) (* C_XDEVICEFAMILY = "kintex7" *) -(* C_ZERO_PACKING_FACTOR = "1" *) (* ORIG_REF_NAME = "fir_compiler_v7_2_12" *) (* downgradeipidentifiedwarnings = "yes" *) -module GaussFir_12m_fir_compiler_v7_2_12 - (aresetn, - aclk, - aclken, - s_axis_data_tvalid, - s_axis_data_tready, - s_axis_data_tlast, - s_axis_data_tuser, - s_axis_data_tdata, - s_axis_config_tvalid, - s_axis_config_tready, - s_axis_config_tlast, - s_axis_config_tdata, - s_axis_reload_tvalid, - s_axis_reload_tready, - s_axis_reload_tlast, - s_axis_reload_tdata, - m_axis_data_tvalid, - m_axis_data_tready, - m_axis_data_tlast, - m_axis_data_tuser, - m_axis_data_tdata, - event_s_data_tlast_missing, - event_s_data_tlast_unexpected, - event_s_data_chanid_incorrect, - event_s_config_tlast_missing, - event_s_config_tlast_unexpected, - event_s_reload_tlast_missing, - event_s_reload_tlast_unexpected); - input aresetn; - input aclk; - input aclken; - input s_axis_data_tvalid; - output s_axis_data_tready; - input s_axis_data_tlast; - input [0:0]s_axis_data_tuser; - input [7:0]s_axis_data_tdata; - input s_axis_config_tvalid; - output s_axis_config_tready; - input s_axis_config_tlast; - input [0:0]s_axis_config_tdata; - input s_axis_reload_tvalid; - output s_axis_reload_tready; - input s_axis_reload_tlast; - input [0:0]s_axis_reload_tdata; - output m_axis_data_tvalid; - input m_axis_data_tready; - output m_axis_data_tlast; - output [0:0]m_axis_data_tuser; - output [15:0]m_axis_data_tdata; - output event_s_data_tlast_missing; - output event_s_data_tlast_unexpected; - output event_s_data_chanid_incorrect; - output event_s_config_tlast_missing; - output event_s_config_tlast_unexpected; - output event_s_reload_tlast_missing; - output event_s_reload_tlast_unexpected; - - wire \ ; - wire aclk; - wire [14:0]\^m_axis_data_tdata ; - wire m_axis_data_tvalid; - wire [7:0]s_axis_data_tdata; - wire s_axis_data_tready; - wire s_axis_data_tvalid; - wire NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED; - wire NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED; - wire NLW_i_synth_event_s_data_chanid_incorrect_UNCONNECTED; - wire NLW_i_synth_event_s_data_tlast_missing_UNCONNECTED; - wire NLW_i_synth_event_s_data_tlast_unexpected_UNCONNECTED; - wire NLW_i_synth_event_s_reload_tlast_missing_UNCONNECTED; - wire NLW_i_synth_event_s_reload_tlast_unexpected_UNCONNECTED; - wire NLW_i_synth_m_axis_data_tlast_UNCONNECTED; - wire NLW_i_synth_s_axis_config_tready_UNCONNECTED; - wire NLW_i_synth_s_axis_reload_tready_UNCONNECTED; - wire [14:14]NLW_i_synth_m_axis_data_tdata_UNCONNECTED; - wire [0:0]NLW_i_synth_m_axis_data_tuser_UNCONNECTED; - - assign event_s_config_tlast_missing = \ ; - assign event_s_config_tlast_unexpected = \ ; - assign event_s_data_chanid_incorrect = \ ; - assign event_s_data_tlast_missing = \ ; - assign event_s_data_tlast_unexpected = \ ; - assign event_s_reload_tlast_missing = \ ; - assign event_s_reload_tlast_unexpected = \ ; - assign m_axis_data_tdata[15] = \^m_axis_data_tdata [14]; - assign m_axis_data_tdata[14:0] = \^m_axis_data_tdata [14:0]; - assign m_axis_data_tlast = \ ; - assign m_axis_data_tuser[0] = \ ; - assign s_axis_config_tready = \ ; - assign s_axis_reload_tready = \ ; - GND GND - (.G(\ )); - (* C_ACCUM_OP_PATH_WIDTHS = "15" *) - (* C_ACCUM_PATH_WIDTHS = "15" *) - (* C_CHANNEL_PATTERN = "fixed" *) - (* C_COEF_FILE = "GaussFir_12m.mif" *) - (* C_COEF_FILE_LINES = "20" *) - (* C_COEF_MEMTYPE = "2" *) - (* C_COEF_MEM_PACKING = "0" *) - (* C_COEF_PATH_SIGN = "1" *) - (* C_COEF_PATH_SRC = "0" *) - (* C_COEF_PATH_WIDTHS = "14" *) - (* C_COEF_RELOAD = "0" *) - (* C_COEF_WIDTH = "14" *) - (* C_COL_CONFIG = "5" *) - (* C_COL_MODE = "1" *) - (* C_COL_PIPE_LEN = "4" *) - (* C_COMPONENT_NAME = "GaussFir_12m" *) - (* C_CONFIG_PACKET_SIZE = "0" *) - (* C_CONFIG_SYNC_MODE = "0" *) - (* C_CONFIG_TDATA_WIDTH = "1" *) - (* C_DATAPATH_MEMTYPE = "0" *) - (* C_DATA_HAS_TLAST = "0" *) - (* C_DATA_IP_PATH_WIDTHS = "2" *) - (* C_DATA_MEMTYPE = "0" *) - (* C_DATA_MEM_PACKING = "0" *) - (* C_DATA_PATH_PSAMP_SRC = "0" *) - (* C_DATA_PATH_SIGN = "0" *) - (* C_DATA_PATH_SRC = "0" *) - (* C_DATA_PATH_WIDTHS = "2" *) - (* C_DATA_PX_PATH_WIDTHS = "2" *) - (* C_DATA_WIDTH = "2" *) - (* C_DECIM_RATE = "1" *) - (* C_ELABORATION_DIR = "./" *) - (* C_EXT_MULT_CNFG = "none" *) - (* C_FILTER_TYPE = "2" *) - (* C_FILTS_PACKED = "0" *) - (* C_HAS_ACLKEN = "0" *) - (* C_HAS_ARESETn = "0" *) - (* C_HAS_CONFIG_CHANNEL = "0" *) - (* C_INPUT_RATE = "4" *) - (* C_INTERP_RATE = "4" *) - (* C_IPBUFF_MEMTYPE = "0" *) - (* C_LATENCY = "11" *) - (* C_MEM_ARRANGEMENT = "2" *) - (* C_M_DATA_HAS_TREADY = "0" *) - (* C_M_DATA_HAS_TUSER = "0" *) - (* C_M_DATA_TDATA_WIDTH = "16" *) - (* C_M_DATA_TUSER_WIDTH = "1" *) - (* C_NUM_CHANNELS = "1" *) - (* C_NUM_FILTS = "1" *) - (* C_NUM_MADDS = "5" *) - (* C_NUM_RELOAD_SLOTS = "1" *) - (* C_NUM_TAPS = "17" *) - (* C_OPBUFF_MEMTYPE = "0" *) - (* C_OPTIMIZATION = "0" *) - (* C_OPT_MADDS = "none" *) - (* C_OP_PATH_PSAMP_SRC = "0" *) - (* C_OUTPUT_PATH_WIDTHS = "15" *) - (* C_OUTPUT_RATE = "1" *) - (* C_OUTPUT_WIDTH = "15" *) - (* C_OVERSAMPLING_RATE = "1" *) - (* C_PX_PATH_SRC = "0" *) - (* C_RELOAD_TDATA_WIDTH = "1" *) - (* C_ROUND_MODE = "0" *) - (* C_SYMMETRY = "0" *) - (* C_S_DATA_HAS_FIFO = "0" *) - (* C_S_DATA_HAS_TUSER = "0" *) - (* C_S_DATA_TDATA_WIDTH = "8" *) - (* C_S_DATA_TUSER_WIDTH = "1" *) - (* C_XDEVICEFAMILY = "kintex7" *) - (* C_ZERO_PACKING_FACTOR = "1" *) - (* downgradeipidentifiedwarnings = "yes" *) - GaussFir_12m_fir_compiler_v7_2_12_viv i_synth - (.aclk(aclk), - .aclken(1'b0), - .aresetn(1'b0), - .event_s_config_tlast_missing(NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED), - .event_s_config_tlast_unexpected(NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED), - .event_s_data_chanid_incorrect(NLW_i_synth_event_s_data_chanid_incorrect_UNCONNECTED), - .event_s_data_tlast_missing(NLW_i_synth_event_s_data_tlast_missing_UNCONNECTED), - .event_s_data_tlast_unexpected(NLW_i_synth_event_s_data_tlast_unexpected_UNCONNECTED), - .event_s_reload_tlast_missing(NLW_i_synth_event_s_reload_tlast_missing_UNCONNECTED), - .event_s_reload_tlast_unexpected(NLW_i_synth_event_s_reload_tlast_unexpected_UNCONNECTED), - .m_axis_data_tdata({\^m_axis_data_tdata [14],NLW_i_synth_m_axis_data_tdata_UNCONNECTED[14],\^m_axis_data_tdata [13:0]}), - .m_axis_data_tlast(NLW_i_synth_m_axis_data_tlast_UNCONNECTED), - .m_axis_data_tready(1'b0), - .m_axis_data_tuser(NLW_i_synth_m_axis_data_tuser_UNCONNECTED[0]), - .m_axis_data_tvalid(m_axis_data_tvalid), - .s_axis_config_tdata(1'b0), - .s_axis_config_tlast(1'b0), - .s_axis_config_tready(NLW_i_synth_s_axis_config_tready_UNCONNECTED), - .s_axis_config_tvalid(1'b0), - .s_axis_data_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,s_axis_data_tdata[1:0]}), - .s_axis_data_tlast(1'b0), - .s_axis_data_tready(s_axis_data_tready), - .s_axis_data_tuser(1'b0), - .s_axis_data_tvalid(s_axis_data_tvalid), - .s_axis_reload_tdata(1'b0), - .s_axis_reload_tlast(1'b0), - .s_axis_reload_tready(NLW_i_synth_s_axis_reload_tready_UNCONNECTED), - .s_axis_reload_tvalid(1'b0)); -endmodule -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "XILINX" -`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" -`pragma protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=64) -`pragma protect key_block -I5jBxSA30qMppesbkWzApATD001KfSyiO/EXeiSfqG/mDp7bWT98b6O2aLKwO2KBiQHns7D4kNzR -1vJ+KztHDg== - -`pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128) -`pragma protect key_block -WMu7kFTLnidedbfVrZuh/7ca7CUttjqfOqFAqALtw+gkp4fPh7ZCC2c3FriF2MGJNdt0inCBZQ1w -ERGO+2E2lzKAF62aWczdna33VjhJbQEhVD66TE3XkcNa3kH5qqUhb+EgT0e6ErzcmqjyjnkFxoKK -XKvbLV/yC8Myvjbgd1A= - -`pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`pragma protect key_block -xD5n0VbWIE6P1VxF0RmDDu2TYD4jh2LNu0PcTQhqBRKitH0v3xG4GrD/vuHfz6qhNoYV25YBOEWi -7kVjcZSXNFtC5ITuwneS2ZMRryiXpM8fFiU2j9L4eELr2/mHrJrVvacPISdaWzzVZMaXZGjjLF31 -zK98DBrt3GchBNvrcOgQmuPVAvjrSEZ+P+LhtLFVfq/zmFgYzV3AELJD6jr7elUkLyTjsJWEFYcf -b43n7Hb0i+cIbRt6Dd+v0kyLoVGDXUE7IXud31zG1Rotvh/eF07hFqqllLHHu2UWUNW8RAWEy1Fo -3/0kdpsYoC+scwVlEiw6L4xm3ZvOMO3xLhlx9Q== - -`pragma protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`pragma protect key_block -fQrDOnMjpZojQhY1c1rw1hwuEu2Y2M8ofkmIyKutN5o3WWgs402wk38nunx4Rn3nJ4alOoXDi3N8 -wCK4FFFUnB/83xpx5yiE801fH9CrSpiGk2CFUTGUPQ2AKib6X7q/ypXzIE3Xi/Fp8v68pOYfzYgB -DWCJiGAer9WgqVkNoAOLB2B99+hjhpjUr+bqeFKCONh+smCJvnzi5NuFbGTw6NRi9XF/fOBJpA7N -7mSHNKQA9TZaG877TLVUYWhpu8Tllt4YOnNvOy5csoZO6jBxXCjuxWmM9dl9WSOXp2HX/onR6rpz -sNUbO2lQftIr2WNh0Jv073YUwDxDBpl586IEWg== - -`pragma protect key_keyowner="Xilinx", key_keyname="xilinxt_2019_02", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`pragma protect key_block -Yt/xtD+YwHpwIG7cpV+YFKRLELTuOpDyL++EbS2PSHkTTnkY+SDEglVSGBUkgEMCy4FK2fL2wt2N -qjVnO38YwcIpkFA3hdVylOufwvfkyXzLnO4I/oXAmiPI3b+yEyPArGvVOGpDgyd07VUs/V9x8yNF -fJU+AQwpZcLwvczmvjIU4/eR8fdXCMBV/C6JW2N+CHrwTU69ne3XstJaVfOIPupKIpZjLVLIrAYs -UQMdOWUz5FDENYd645Oho01vEbgtbLb+GrcpRedjCAIY2LgO42kQ9rDb7oVFFsUuoIPnWF4fLEjb -Pq5mb00fUdX1TzSueiRRmMIn69wkk/QkSb8jag== - -`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128) -`pragma protect key_block -S5Ng9U2ICFR2ATladKVkI9g1B4mI1wuXRMAnMNgbxvoijFO8db10A3+6fvjuey2Yzxp1Hf4dZcYN -c/lBn1GB/WXkp/IAC1a0hNWcvyknzHaPnT0XXAr2t5Xncs67wJ8pN5Gp2D1qrZQQzDnNoYG2S/bd -YiWvkcmY78GRhm+UXVk= - -`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`pragma protect key_block -HAhvjf08asX78hSz5fysjZpqt6weT/hM0aPw+9OZ6ZFgT2U7lNg0+xRLXb9nzh4EewIjMgSyWdbq -Irle9J+zY0NjMxQhF0AU4uZR3mjfrD6Ci+uFgn2FssxWd9BHXv/cqiRhCZU2ybiUWpzjYSU0dR0h -2hg5PlS+G3dlVbHVWfTO0k/13GXvSnwpugvkHI9jnHi2x1XT0gcm6G9Zhe1EI5PttaiCD/hIEpFy -dE9D4GBdwkisk7PYdWIuZlsBFWDWcbGou0FPnNgoQxkmsqJf2be0EcDmDksiH0SWYeS3S/ePy+eL -24oKZ31y2jK7rq17ZMr87dpRzRIdMsvbgjgGWg== - -`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`pragma protect key_block -gk4RqgvNIG8lEex3wtMa4M3v30L0l+y0oWcBfGNO5VPXpnehoIdIjw5AFsooYYK6yx/cu/p6GCeN -aMSJiQoAoQ7xMUrXydqyR/RwSiYJHx/ZSBG82BCdeguAEPkxJnSclcsGWIYwQ8hpp/KnJy76rcpT -/3DVh5izq0/GcLIfdvX/ICJATZonr/j6x6E3AhtcpNRnKsqS+e8VZYW/Qd8bW0uvSKj+oAE8tmnx -NYvINJVoxLBqNLglkjbSy+NvK9JD3Ey5ZeWlF2xgvhokwRZ1acR1EoFLQVfOv+XHhyxPGH6UGk2v -Jk5q6LM/RtcmcQaf3o/R/7IclGghBlOvx8I8sg== - -`pragma protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`pragma protect key_block -azfW/uH4+7na1c5MypPVAw0isPaeiRpvqTu5gnZ/xgQsRJZ3DoWAuFksom0Klkh1Y9xYdS6eGCBy -YPYA6c4SxFj9MPGHrd3C1FwUglmDt+OItxatr6U32tyuuNE5GIAG7733XZZ+lfsJbMIWg2MH4Qzh -mLAZucnBEQQKs2ZuIYHLD32RNzFSKPNiimhR9pHIAnDw6ft5ZHdrqylxMLB2r1cB4H3NJOpveE5k -3WDnLRjFtxrx0jp/0tZpRdYBfRdSQgUxC1t9hLs1earEA8dTEFobLLTVr6f7VeDZbfDu8XSGl9Pv -moSpUZt/XOaSxlyc2/Q43WZRnxlwoDxiuNFHtg== - -`pragma protect data_method = "AES128-CBC" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 107120) -`pragma protect data_block -QwwnHFx7ZAVop08/6t6jgmj3fWWCXece6Ud9dkZzPyPCzPo31gp1/dpMDuIDGQ4bJjzKEz7cn/zo -GsPptoqAdAG0igKYHKrmb3ppavdlwGfRXpBDS62Hl3HOJQvypTuCLZoIlmP0qxjFl33ZuYY3/xzl -Hh2X6DtIWRKffEwaHQ4TNjZyciaP4wWqVQlkWd8Z+9UQkkFaJa4D6n0hau0JoJuPUPkrVTk0Rp0K -Yn6joaNsrpFP7TF4aWWhX36JPS+PyaENJeficmh383mTQIbojuHAJic39UAi8wzRye1ompVmZT/p -yR/kEZfxebNFKd+tRwiG2qseJ6s/hm6G6CTdLqL3AD+HoolRAAncp0w6Hoe9kfbJewxA5bAsaPCT -vczeZuZfY2i58ujGD9uxrY6oLCPQf0JWbqv/u06vgNfmo+Mefw+e2T/mcxgEuc8rVSWiPxglY9wl -vtBtDHsI0gUF2AcLueFstFvPvOmit5FEsC0Odd0s7dRWM7sZUiW1kV23vAxh0YoT86n1imZQ0loZ -4INieQMhN9ilwBPZTGwKQQ3lO0SauACvzT8n27Eb7MfQnn+//Pv8UdWS5n67jqmqawG4kf55WFTN -JbH5kJnRPNRdeCntlfujT6YM7RiDz3bM+XyjfJyx32CXhmnip3U3+1xMaUI96UVridCV82tnm6TA -3jdTtD8fRvINwcfukSl1rWHHS5dL2pS8HJYXMRN1h6+JPuamSLd67HSNtIVVj44hM+Z5JT6lrsFS -mM7DHuY27tVioI9l6gT6Xuw9LPiiwUzQeLkt6XJKkL/0hePSHAN2H90D0/YYjPN+aUFFEhA24s3R -ZLhZaP0t7EU55LYQCXersEXjdF3dPOwPzrAksmShY2+A0Q0B4q3hKmBwn+EEzHzz5RYSSsm2Lia1 -+YyT0gN3JLoCFPrmJr1o6V2T3Q3prmrX2J4xC5MOWbvhhk60EAKZ3RGuwoox1q8U0YhF9EjTwmfD -0/7J2yEvtIVauriNycsbwfqIN4LaUV+ssd5r40PG5lrijK+Q3H2K9in2aRANCfUd3FR6lugUot8B -UpnuqQz8FbjzBto+5qgVe7Ilp8/XFcqFDeS3Gq11v3HUu8z+tDsl8vP8pQkrI7n0+4qJyKCJZ8Zs -2RJte6DLZCIwe3LhJJdFAToAzinU4MDkz/Mt17K3L6yyKVT+IxIaxa/b4HExGYQNHZop13BUwL4z -H09PQdRFj65DI1CmI5AvMcPsfSGkYlRaP58X8akTPZRZBFnwBn9w/6DwAWpTHkrwn/GKs9g3g49G -dYtoPerPoTSihyFcds4Z1Mk25sRTtZ7gduiNbo/DMj7qG5fZawJSX/YJqbD//+w6ezh6YPsp2nOf -rQi+64kShuFGLEb+QCdWmsT/pCNSC1rV5cBSQk8+/B17LwM+BHXy3hCWyuFdEbWNj5hFosR/Jywz -qBOenLkMKwhDImsAWnQZ1h7J5k/Qdc74wOPp0dKzmlYk2ttQA8h5p04SS3KonpbHj9VMqThI8H6l -a072WbOezIi6f5uRSAJwdSCSitdfgVO9jCYv0BkCUkmg7A4LgyeGryQGYq1nPQvyPWRjJ+/og6Ht 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-------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/GaussFir_12m_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/GaussFir_12m_sim_netlist.vhdl deleted file mode 100644 index 59601778..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/GaussFir_12m_sim_netlist.vhdl +++ /dev/null @@ -1,3344 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:33:48 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_sim_netlist.vhdl --- Design : GaussFir_12m --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -`protect begin_protected -`protect version = 1 -`protect encrypt_agent = "XILINX" -`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" -`protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=64) -`protect key_block -I5jBxSA30qMppesbkWzApATD001KfSyiO/EXeiSfqG/mDp7bWT98b6O2aLKwO2KBiQHns7D4kNzR -1vJ+KztHDg== - -`protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=128) -`protect key_block -WMu7kFTLnidedbfVrZuh/7ca7CUttjqfOqFAqALtw+gkp4fPh7ZCC2c3FriF2MGJNdt0inCBZQ1w -ERGO+2E2lzKAF62aWczdna33VjhJbQEhVD66TE3XkcNa3kH5qqUhb+EgT0e6ErzcmqjyjnkFxoKK -XKvbLV/yC8Myvjbgd1A= - -`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`protect key_block -xD5n0VbWIE6P1VxF0RmDDu2TYD4jh2LNu0PcTQhqBRKitH0v3xG4GrD/vuHfz6qhNoYV25YBOEWi -7kVjcZSXNFtC5ITuwneS2ZMRryiXpM8fFiU2j9L4eELr2/mHrJrVvacPISdaWzzVZMaXZGjjLF31 -zK98DBrt3GchBNvrcOgQmuPVAvjrSEZ+P+LhtLFVfq/zmFgYzV3AELJD6jr7elUkLyTjsJWEFYcf -b43n7Hb0i+cIbRt6Dd+v0kyLoVGDXUE7IXud31zG1Rotvh/eF07hFqqllLHHu2UWUNW8RAWEy1Fo -3/0kdpsYoC+scwVlEiw6L4xm3ZvOMO3xLhlx9Q== - -`protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`protect key_block -fQrDOnMjpZojQhY1c1rw1hwuEu2Y2M8ofkmIyKutN5o3WWgs402wk38nunx4Rn3nJ4alOoXDi3N8 -wCK4FFFUnB/83xpx5yiE801fH9CrSpiGk2CFUTGUPQ2AKib6X7q/ypXzIE3Xi/Fp8v68pOYfzYgB -DWCJiGAer9WgqVkNoAOLB2B99+hjhpjUr+bqeFKCONh+smCJvnzi5NuFbGTw6NRi9XF/fOBJpA7N -7mSHNKQA9TZaG877TLVUYWhpu8Tllt4YOnNvOy5csoZO6jBxXCjuxWmM9dl9WSOXp2HX/onR6rpz -sNUbO2lQftIr2WNh0Jv073YUwDxDBpl586IEWg== - -`protect key_keyowner="Xilinx", key_keyname="xilinxt_2019_02", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`protect key_block -Yt/xtD+YwHpwIG7cpV+YFKRLELTuOpDyL++EbS2PSHkTTnkY+SDEglVSGBUkgEMCy4FK2fL2wt2N -qjVnO38YwcIpkFA3hdVylOufwvfkyXzLnO4I/oXAmiPI3b+yEyPArGvVOGpDgyd07VUs/V9x8yNF -fJU+AQwpZcLwvczmvjIU4/eR8fdXCMBV/C6JW2N+CHrwTU69ne3XstJaVfOIPupKIpZjLVLIrAYs -UQMdOWUz5FDENYd645Oho01vEbgtbLb+GrcpRedjCAIY2LgO42kQ9rDb7oVFFsUuoIPnWF4fLEjb -Pq5mb00fUdX1TzSueiRRmMIn69wkk/QkSb8jag== - -`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=128) -`protect key_block -S5Ng9U2ICFR2ATladKVkI9g1B4mI1wuXRMAnMNgbxvoijFO8db10A3+6fvjuey2Yzxp1Hf4dZcYN -c/lBn1GB/WXkp/IAC1a0hNWcvyknzHaPnT0XXAr2t5Xncs67wJ8pN5Gp2D1qrZQQzDnNoYG2S/bd -YiWvkcmY78GRhm+UXVk= - -`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa" -`protect 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key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`protect key_block -c5C/t9DTEa5Jg9aiR4h8FvIAQU7KYufvKNXB0pBrGYBxk9wwEjz3uQJ4DrJy11F695oS8rO7IpYA -x+mKRKDoYvj5sSPdzhp8kXERhmzsRXlm63AWVk5EsZN7IW1+wd2SzYPe3rhyi/YJys6smwRbCEUz -l7ek0ZYa/b4i5jZ3j6WbNudzyvh8qzbit2/OGYiD3Gt1e85mR62T8XltQDnOsU+sQ2TYBGMSLC1t -JmBOARarj+ScUAZCIhY7SPB4OyfIXNptg7TFAaRoqLRmRQ42YrtwjOE4/iHiFywI/BV4ljEb6HK7 -4wwbrm04SQXYL4ECQCZ1ocxesbOPclth8NgfIA== - -`protect data_method = "AES128-CBC" -`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 154432) -`protect data_block -esa3DMaYPU+R/pNANap7uh4b4Gp8mXvPeDrr0g2xo34kcmobL3JYnKzlf9QS5c/C2/N+5ShteGG1 -q9KyIgsWlB802f1r6ENVQAzSBQTECYE0rp1Cs1Syl43DmfLXEzuxz2EsPTH47MMFZ10sfRcQblFD -7+3/YQBotHeMACNxTZan3RYMrvMfnXr6ZFZqk+hU2K9X8XSAYOLLQ5JyPnGnStizcS0Dl6tYZesd -nObf95qTE8gM0859UbTx5KiDeVqr2aJnbQ9489xbsy2TzLM/fJAX4SEW7Lmzk6vu0adHRQ5O0VbB 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-Kxyi0LEtuV0h0vM81pxIVbOtAQRH/hOKl6IpPersVuS2NT5n/6pf1pQg8KuofsYP+SDAi16ZgI0e -IY1WUWxgY+fX0D7qI9AJzx6J+SZyWVnQGILuq7/2b9GUboApWWIUZMCxBL6Nu7svBpKXYkZdI/f/ -a4zINogHhqo05q9sxch9BR0B3Eb6N/5PsZ2UE94Xth7+NndxbxT1kgfVXMiF540o1RhaaGThs6D5 -Po2cNEfJ0MF2AZnM/rv7q0xMeOqMeF8upotBhjTndSpC97ntsrlgTykbPFRCrn7eNS3KocQj9f4e -kJ8YhLmzTrc5OAb84Ld6VT0DLH9o6JdjeXP0APa3qX2+wwpIWQ9SjGa6Cny+IsiV4XZkGWNX/2Jj -0PafHhOoL/GwWIg13MLReQiLcQ== -`protect end_protected -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity GaussFir_12m_fir_compiler_v7_2_12 is - port ( - aresetn : in STD_LOGIC; - aclk : in STD_LOGIC; - aclken : in STD_LOGIC; - s_axis_data_tvalid : in STD_LOGIC; - s_axis_data_tready : out STD_LOGIC; - s_axis_data_tlast : in STD_LOGIC; - s_axis_data_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axis_config_tvalid : in STD_LOGIC; - s_axis_config_tready : out STD_LOGIC; - s_axis_config_tlast : in STD_LOGIC; - s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axis_reload_tvalid : in STD_LOGIC; - s_axis_reload_tready : out STD_LOGIC; - s_axis_reload_tlast : in STD_LOGIC; - s_axis_reload_tdata : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_data_tvalid : out STD_LOGIC; - m_axis_data_tready : in STD_LOGIC; - m_axis_data_tlast : out STD_LOGIC; - m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); - event_s_data_tlast_missing : out STD_LOGIC; - event_s_data_tlast_unexpected : out STD_LOGIC; - event_s_data_chanid_incorrect : out STD_LOGIC; - event_s_config_tlast_missing : out STD_LOGIC; - event_s_config_tlast_unexpected : out STD_LOGIC; - event_s_reload_tlast_missing : out STD_LOGIC; - event_s_reload_tlast_unexpected : out STD_LOGIC - ); - attribute C_ACCUM_OP_PATH_WIDTHS : string; - attribute C_ACCUM_OP_PATH_WIDTHS of GaussFir_12m_fir_compiler_v7_2_12 : entity is "15"; - attribute C_ACCUM_PATH_WIDTHS : string; - attribute C_ACCUM_PATH_WIDTHS of GaussFir_12m_fir_compiler_v7_2_12 : entity is "15"; - attribute C_CHANNEL_PATTERN : string; - attribute C_CHANNEL_PATTERN of GaussFir_12m_fir_compiler_v7_2_12 : entity is "fixed"; - attribute C_COEF_FILE : string; - attribute C_COEF_FILE of GaussFir_12m_fir_compiler_v7_2_12 : entity is "GaussFir_12m.mif"; - attribute C_COEF_FILE_LINES : integer; - attribute C_COEF_FILE_LINES of GaussFir_12m_fir_compiler_v7_2_12 : entity is 20; - attribute C_COEF_MEMTYPE : integer; - attribute C_COEF_MEMTYPE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 2; - attribute C_COEF_MEM_PACKING : integer; - attribute C_COEF_MEM_PACKING of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_COEF_PATH_SIGN : string; - attribute C_COEF_PATH_SIGN of GaussFir_12m_fir_compiler_v7_2_12 : entity is "1"; - attribute C_COEF_PATH_SRC : string; - attribute C_COEF_PATH_SRC of GaussFir_12m_fir_compiler_v7_2_12 : entity is "0"; - attribute C_COEF_PATH_WIDTHS : string; - attribute C_COEF_PATH_WIDTHS of GaussFir_12m_fir_compiler_v7_2_12 : entity is "14"; - attribute C_COEF_RELOAD : integer; - attribute C_COEF_RELOAD of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_COEF_WIDTH : integer; - attribute C_COEF_WIDTH of GaussFir_12m_fir_compiler_v7_2_12 : entity is 14; - attribute C_COL_CONFIG : string; - attribute C_COL_CONFIG of GaussFir_12m_fir_compiler_v7_2_12 : entity is "5"; - attribute C_COL_MODE : integer; - attribute C_COL_MODE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_COL_PIPE_LEN : integer; - attribute C_COL_PIPE_LEN of GaussFir_12m_fir_compiler_v7_2_12 : entity is 4; - attribute C_COMPONENT_NAME : string; - attribute C_COMPONENT_NAME of GaussFir_12m_fir_compiler_v7_2_12 : entity is "GaussFir_12m"; - attribute C_CONFIG_PACKET_SIZE : integer; - attribute C_CONFIG_PACKET_SIZE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_CONFIG_SYNC_MODE : integer; - attribute C_CONFIG_SYNC_MODE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_CONFIG_TDATA_WIDTH : integer; - attribute C_CONFIG_TDATA_WIDTH of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_DATAPATH_MEMTYPE : integer; - attribute C_DATAPATH_MEMTYPE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_DATA_HAS_TLAST : integer; - attribute C_DATA_HAS_TLAST of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_DATA_IP_PATH_WIDTHS : string; - attribute C_DATA_IP_PATH_WIDTHS of GaussFir_12m_fir_compiler_v7_2_12 : entity is "2"; - attribute C_DATA_MEMTYPE : integer; - attribute C_DATA_MEMTYPE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_DATA_MEM_PACKING : integer; - attribute C_DATA_MEM_PACKING of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_DATA_PATH_PSAMP_SRC : string; - attribute C_DATA_PATH_PSAMP_SRC of GaussFir_12m_fir_compiler_v7_2_12 : entity is "0"; - attribute C_DATA_PATH_SIGN : string; - attribute C_DATA_PATH_SIGN of GaussFir_12m_fir_compiler_v7_2_12 : entity is "0"; - attribute C_DATA_PATH_SRC : string; - attribute C_DATA_PATH_SRC of GaussFir_12m_fir_compiler_v7_2_12 : entity is "0"; - attribute C_DATA_PATH_WIDTHS : string; - attribute C_DATA_PATH_WIDTHS of GaussFir_12m_fir_compiler_v7_2_12 : entity is "2"; - attribute C_DATA_PX_PATH_WIDTHS : string; - attribute C_DATA_PX_PATH_WIDTHS of GaussFir_12m_fir_compiler_v7_2_12 : entity is "2"; - attribute C_DATA_WIDTH : integer; - attribute C_DATA_WIDTH of GaussFir_12m_fir_compiler_v7_2_12 : entity is 2; - attribute C_DECIM_RATE : integer; - attribute C_DECIM_RATE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_ELABORATION_DIR : string; - attribute C_ELABORATION_DIR of GaussFir_12m_fir_compiler_v7_2_12 : entity is "./"; - attribute C_EXT_MULT_CNFG : string; - attribute C_EXT_MULT_CNFG of GaussFir_12m_fir_compiler_v7_2_12 : entity is "none"; - attribute C_FILTER_TYPE : integer; - attribute C_FILTER_TYPE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 2; - attribute C_FILTS_PACKED : integer; - attribute C_FILTS_PACKED of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_HAS_ACLKEN : integer; - attribute C_HAS_ACLKEN of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_HAS_ARESETn : integer; - attribute C_HAS_ARESETn of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_HAS_CONFIG_CHANNEL : integer; - attribute C_HAS_CONFIG_CHANNEL of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_INPUT_RATE : integer; - attribute C_INPUT_RATE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 4; - attribute C_INTERP_RATE : integer; - attribute C_INTERP_RATE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 4; - attribute C_IPBUFF_MEMTYPE : integer; - attribute C_IPBUFF_MEMTYPE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_LATENCY : integer; - attribute C_LATENCY of GaussFir_12m_fir_compiler_v7_2_12 : entity is 11; - attribute C_MEM_ARRANGEMENT : integer; - attribute C_MEM_ARRANGEMENT of GaussFir_12m_fir_compiler_v7_2_12 : entity is 2; - attribute C_M_DATA_HAS_TREADY : integer; - attribute C_M_DATA_HAS_TREADY of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_M_DATA_HAS_TUSER : integer; - attribute C_M_DATA_HAS_TUSER of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_M_DATA_TDATA_WIDTH : integer; - attribute C_M_DATA_TDATA_WIDTH of GaussFir_12m_fir_compiler_v7_2_12 : entity is 16; - attribute C_M_DATA_TUSER_WIDTH : integer; - attribute C_M_DATA_TUSER_WIDTH of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_NUM_CHANNELS : integer; - attribute C_NUM_CHANNELS of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_NUM_FILTS : integer; - attribute C_NUM_FILTS of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_NUM_MADDS : integer; - attribute C_NUM_MADDS of GaussFir_12m_fir_compiler_v7_2_12 : entity is 5; - attribute C_NUM_RELOAD_SLOTS : integer; - attribute C_NUM_RELOAD_SLOTS of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_NUM_TAPS : integer; - attribute C_NUM_TAPS of GaussFir_12m_fir_compiler_v7_2_12 : entity is 17; - attribute C_OPBUFF_MEMTYPE : integer; - attribute C_OPBUFF_MEMTYPE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_OPTIMIZATION : integer; - attribute C_OPTIMIZATION of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_OPT_MADDS : string; - attribute C_OPT_MADDS of GaussFir_12m_fir_compiler_v7_2_12 : entity is "none"; - attribute C_OP_PATH_PSAMP_SRC : string; - attribute C_OP_PATH_PSAMP_SRC of GaussFir_12m_fir_compiler_v7_2_12 : entity is "0"; - attribute C_OUTPUT_PATH_WIDTHS : string; - attribute C_OUTPUT_PATH_WIDTHS of GaussFir_12m_fir_compiler_v7_2_12 : entity is "15"; - attribute C_OUTPUT_RATE : integer; - attribute C_OUTPUT_RATE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_OUTPUT_WIDTH : integer; - attribute C_OUTPUT_WIDTH of GaussFir_12m_fir_compiler_v7_2_12 : entity is 15; - attribute C_OVERSAMPLING_RATE : integer; - attribute C_OVERSAMPLING_RATE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_PX_PATH_SRC : string; - attribute C_PX_PATH_SRC of GaussFir_12m_fir_compiler_v7_2_12 : entity is "0"; - attribute C_RELOAD_TDATA_WIDTH : integer; - attribute C_RELOAD_TDATA_WIDTH of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_ROUND_MODE : integer; - attribute C_ROUND_MODE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_SYMMETRY : integer; - attribute C_SYMMETRY of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_S_DATA_HAS_FIFO : integer; - attribute C_S_DATA_HAS_FIFO of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_S_DATA_HAS_TUSER : integer; - attribute C_S_DATA_HAS_TUSER of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_S_DATA_TDATA_WIDTH : integer; - attribute C_S_DATA_TDATA_WIDTH of GaussFir_12m_fir_compiler_v7_2_12 : entity is 8; - attribute C_S_DATA_TUSER_WIDTH : integer; - attribute C_S_DATA_TUSER_WIDTH of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of GaussFir_12m_fir_compiler_v7_2_12 : entity is "kintex7"; - attribute C_ZERO_PACKING_FACTOR : integer; - attribute C_ZERO_PACKING_FACTOR of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of GaussFir_12m_fir_compiler_v7_2_12 : entity is "fir_compiler_v7_2_12"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of GaussFir_12m_fir_compiler_v7_2_12 : entity is "yes"; -end GaussFir_12m_fir_compiler_v7_2_12; - -architecture STRUCTURE of GaussFir_12m_fir_compiler_v7_2_12 is - signal \\ : STD_LOGIC; - signal \^m_axis_data_tdata\ : STD_LOGIC_VECTOR ( 14 downto 0 ); - signal NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_data_chanid_incorrect_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_data_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_data_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_reload_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_reload_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_m_axis_data_tlast_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_s_axis_config_tready_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_s_axis_reload_tready_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_m_axis_data_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 14 to 14 ); - signal NLW_i_synth_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - attribute C_ACCUM_OP_PATH_WIDTHS of i_synth : label is "15"; - attribute C_ACCUM_PATH_WIDTHS of i_synth : label is "15"; - attribute C_CHANNEL_PATTERN of i_synth : label is "fixed"; - attribute C_COEF_FILE of i_synth : label is "GaussFir_12m.mif"; - attribute C_COEF_FILE_LINES of i_synth : label is 20; - attribute C_COEF_MEMTYPE of i_synth : label is 2; - attribute C_COEF_MEM_PACKING of i_synth : label is 0; - attribute C_COEF_PATH_SIGN of i_synth : label is "1"; - attribute C_COEF_PATH_SRC of i_synth : label is "0"; - attribute C_COEF_PATH_WIDTHS of i_synth : label is "14"; - attribute C_COEF_RELOAD of i_synth : label is 0; - attribute C_COEF_WIDTH of i_synth : label is 14; - attribute C_COL_CONFIG of i_synth : label is "5"; - attribute C_COL_MODE of i_synth : label is 1; - attribute C_COL_PIPE_LEN of i_synth : label is 4; - attribute C_COMPONENT_NAME of i_synth : label is "GaussFir_12m"; - attribute C_CONFIG_PACKET_SIZE of i_synth : label is 0; - attribute C_CONFIG_SYNC_MODE of i_synth : label is 0; - attribute C_CONFIG_TDATA_WIDTH of i_synth : label is 1; - attribute C_DATAPATH_MEMTYPE of i_synth : label is 0; - attribute C_DATA_HAS_TLAST of i_synth : label is 0; - attribute C_DATA_IP_PATH_WIDTHS of i_synth : label is "2"; - attribute C_DATA_MEMTYPE of i_synth : label is 0; - attribute C_DATA_MEM_PACKING of i_synth : label is 0; - attribute C_DATA_PATH_PSAMP_SRC of i_synth : label is "0"; - attribute C_DATA_PATH_SIGN of i_synth : label is "0"; - attribute C_DATA_PATH_SRC of i_synth : label is "0"; - attribute C_DATA_PATH_WIDTHS of i_synth : label is "2"; - attribute C_DATA_PX_PATH_WIDTHS of i_synth : label is "2"; - attribute C_DATA_WIDTH of i_synth : label is 2; - attribute C_DECIM_RATE of i_synth : label is 1; - attribute C_ELABORATION_DIR of i_synth : label is "./"; - attribute C_EXT_MULT_CNFG of i_synth : label is "none"; - attribute C_FILTER_TYPE of i_synth : label is 2; - attribute C_FILTS_PACKED of i_synth : label is 0; - attribute C_HAS_ACLKEN of i_synth : label is 0; - attribute C_HAS_ARESETn of i_synth : label is 0; - attribute C_HAS_CONFIG_CHANNEL of i_synth : label is 0; - attribute C_INPUT_RATE of i_synth : label is 4; - attribute C_INTERP_RATE of i_synth : label is 4; - attribute C_IPBUFF_MEMTYPE of i_synth : label is 0; - attribute C_LATENCY of i_synth : label is 11; - attribute C_MEM_ARRANGEMENT of i_synth : label is 2; - attribute C_M_DATA_HAS_TREADY of i_synth : label is 0; - attribute C_M_DATA_HAS_TUSER of i_synth : label is 0; - attribute C_M_DATA_TDATA_WIDTH of i_synth : label is 16; - attribute C_M_DATA_TUSER_WIDTH of i_synth : label is 1; - attribute C_NUM_CHANNELS of i_synth : label is 1; - attribute C_NUM_FILTS of i_synth : label is 1; - attribute C_NUM_MADDS of i_synth : label is 5; - attribute C_NUM_RELOAD_SLOTS of i_synth : label is 1; - attribute C_NUM_TAPS of i_synth : label is 17; - attribute C_OPBUFF_MEMTYPE of i_synth : label is 0; - attribute C_OPTIMIZATION of i_synth : label is 0; - attribute C_OPT_MADDS of i_synth : label is "none"; - attribute C_OP_PATH_PSAMP_SRC of i_synth : label is "0"; - attribute C_OUTPUT_PATH_WIDTHS of i_synth : label is "15"; - attribute C_OUTPUT_RATE of i_synth : label is 1; - attribute C_OUTPUT_WIDTH of i_synth : label is 15; - attribute C_OVERSAMPLING_RATE of i_synth : label is 1; - attribute C_PX_PATH_SRC of i_synth : label is "0"; - attribute C_RELOAD_TDATA_WIDTH of i_synth : label is 1; - attribute C_ROUND_MODE of i_synth : label is 0; - attribute C_SYMMETRY of i_synth : label is 0; - attribute C_S_DATA_HAS_FIFO of i_synth : label is 0; - attribute C_S_DATA_HAS_TUSER of i_synth : label is 0; - attribute C_S_DATA_TDATA_WIDTH of i_synth : label is 8; - attribute C_S_DATA_TUSER_WIDTH of i_synth : label is 1; - attribute C_XDEVICEFAMILY of i_synth : label is "kintex7"; - attribute C_ZERO_PACKING_FACTOR of i_synth : label is 1; - attribute downgradeipidentifiedwarnings of i_synth : label is "yes"; -begin - event_s_config_tlast_missing <= \\; - event_s_config_tlast_unexpected <= \\; - event_s_data_chanid_incorrect <= \\; - event_s_data_tlast_missing <= \\; - event_s_data_tlast_unexpected <= \\; - event_s_reload_tlast_missing <= \\; - event_s_reload_tlast_unexpected <= \\; - m_axis_data_tdata(15) <= \^m_axis_data_tdata\(14); - m_axis_data_tdata(14 downto 0) <= \^m_axis_data_tdata\(14 downto 0); - m_axis_data_tlast <= \\; - m_axis_data_tuser(0) <= \\; - s_axis_config_tready <= \\; - s_axis_reload_tready <= \\; -GND: unisim.vcomponents.GND - port map ( - G => \\ - ); -i_synth: entity work.GaussFir_12m_fir_compiler_v7_2_12_viv - port map ( - aclk => aclk, - aclken => '0', - aresetn => '0', - event_s_config_tlast_missing => NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED, - event_s_config_tlast_unexpected => NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED, - event_s_data_chanid_incorrect => NLW_i_synth_event_s_data_chanid_incorrect_UNCONNECTED, - event_s_data_tlast_missing => NLW_i_synth_event_s_data_tlast_missing_UNCONNECTED, - event_s_data_tlast_unexpected => NLW_i_synth_event_s_data_tlast_unexpected_UNCONNECTED, - event_s_reload_tlast_missing => NLW_i_synth_event_s_reload_tlast_missing_UNCONNECTED, - event_s_reload_tlast_unexpected => NLW_i_synth_event_s_reload_tlast_unexpected_UNCONNECTED, - m_axis_data_tdata(15) => \^m_axis_data_tdata\(14), - m_axis_data_tdata(14) => NLW_i_synth_m_axis_data_tdata_UNCONNECTED(14), - m_axis_data_tdata(13 downto 0) => \^m_axis_data_tdata\(13 downto 0), - m_axis_data_tlast => NLW_i_synth_m_axis_data_tlast_UNCONNECTED, - m_axis_data_tready => '0', - m_axis_data_tuser(0) => NLW_i_synth_m_axis_data_tuser_UNCONNECTED(0), - m_axis_data_tvalid => m_axis_data_tvalid, - s_axis_config_tdata(0) => '0', - s_axis_config_tlast => '0', - s_axis_config_tready => NLW_i_synth_s_axis_config_tready_UNCONNECTED, - s_axis_config_tvalid => '0', - s_axis_data_tdata(7 downto 2) => B"000000", - s_axis_data_tdata(1 downto 0) => s_axis_data_tdata(1 downto 0), - s_axis_data_tlast => '0', - s_axis_data_tready => s_axis_data_tready, - s_axis_data_tuser(0) => '0', - s_axis_data_tvalid => s_axis_data_tvalid, - s_axis_reload_tdata(0) => '0', - s_axis_reload_tlast => '0', - s_axis_reload_tready => NLW_i_synth_s_axis_reload_tready_UNCONNECTED, - s_axis_reload_tvalid => '0' - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity GaussFir_12m is - port ( - aclk : in STD_LOGIC; - s_axis_data_tvalid : in STD_LOGIC; - s_axis_data_tready : out STD_LOGIC; - s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); - m_axis_data_tvalid : out STD_LOGIC; - m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ) - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of GaussFir_12m : entity is true; - attribute CHECK_LICENSE_TYPE : string; - attribute CHECK_LICENSE_TYPE of GaussFir_12m : entity is "GaussFir_12m,fir_compiler_v7_2_12,{}"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of GaussFir_12m : entity is "yes"; - attribute x_core_info : string; - attribute x_core_info of GaussFir_12m : entity is "fir_compiler_v7_2_12,Vivado 2019.1.3"; -end GaussFir_12m; - -architecture STRUCTURE of GaussFir_12m is - signal NLW_U0_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_data_chanid_incorrect_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_data_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_data_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_reload_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_reload_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_U0_m_axis_data_tlast_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axis_config_tready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axis_reload_tready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - attribute C_ACCUM_OP_PATH_WIDTHS : string; - attribute C_ACCUM_OP_PATH_WIDTHS of U0 : label is "15"; - attribute C_ACCUM_PATH_WIDTHS : string; - attribute C_ACCUM_PATH_WIDTHS of U0 : label is "15"; - attribute C_CHANNEL_PATTERN : string; - attribute C_CHANNEL_PATTERN of U0 : label is "fixed"; - attribute C_COEF_FILE : string; - attribute C_COEF_FILE of U0 : label is "GaussFir_12m.mif"; - attribute C_COEF_FILE_LINES : integer; - attribute C_COEF_FILE_LINES of U0 : label is 20; - attribute C_COEF_MEMTYPE : integer; - attribute C_COEF_MEMTYPE of U0 : label is 2; - attribute C_COEF_MEM_PACKING : integer; - attribute C_COEF_MEM_PACKING of U0 : label is 0; - attribute C_COEF_PATH_SIGN : string; - attribute C_COEF_PATH_SIGN of U0 : label is "1"; - attribute C_COEF_PATH_SRC : string; - attribute C_COEF_PATH_SRC of U0 : label is "0"; - attribute C_COEF_PATH_WIDTHS : string; - attribute C_COEF_PATH_WIDTHS of U0 : label is "14"; - attribute C_COEF_RELOAD : integer; - attribute C_COEF_RELOAD of U0 : label is 0; - attribute C_COEF_WIDTH : integer; - attribute C_COEF_WIDTH of U0 : label is 14; - attribute C_COL_CONFIG : string; - attribute C_COL_CONFIG of U0 : label is "5"; - attribute C_COL_MODE : integer; - attribute C_COL_MODE of U0 : label is 1; - attribute C_COL_PIPE_LEN : integer; - attribute C_COL_PIPE_LEN of U0 : label is 4; - attribute C_COMPONENT_NAME : string; - attribute C_COMPONENT_NAME of U0 : label is "GaussFir_12m"; - attribute C_CONFIG_PACKET_SIZE : integer; - attribute C_CONFIG_PACKET_SIZE of U0 : label is 0; - attribute C_CONFIG_SYNC_MODE : integer; - attribute C_CONFIG_SYNC_MODE of U0 : label is 0; - attribute C_CONFIG_TDATA_WIDTH : integer; - attribute C_CONFIG_TDATA_WIDTH of U0 : label is 1; - attribute C_DATAPATH_MEMTYPE : integer; - attribute C_DATAPATH_MEMTYPE of U0 : label is 0; - attribute C_DATA_HAS_TLAST : integer; - attribute C_DATA_HAS_TLAST of U0 : label is 0; - attribute C_DATA_IP_PATH_WIDTHS : string; - attribute C_DATA_IP_PATH_WIDTHS of U0 : label is "2"; - attribute C_DATA_MEMTYPE : integer; - attribute C_DATA_MEMTYPE of U0 : label is 0; - attribute C_DATA_MEM_PACKING : integer; - attribute C_DATA_MEM_PACKING of U0 : label is 0; - attribute C_DATA_PATH_PSAMP_SRC : string; - attribute C_DATA_PATH_PSAMP_SRC of U0 : label is "0"; - attribute C_DATA_PATH_SIGN : string; - attribute C_DATA_PATH_SIGN of U0 : label is "0"; - attribute C_DATA_PATH_SRC : string; - attribute C_DATA_PATH_SRC of U0 : label is "0"; - attribute C_DATA_PATH_WIDTHS : string; - attribute C_DATA_PATH_WIDTHS of U0 : label is "2"; - attribute C_DATA_PX_PATH_WIDTHS : string; - attribute C_DATA_PX_PATH_WIDTHS of U0 : label is "2"; - attribute C_DATA_WIDTH : integer; - attribute C_DATA_WIDTH of U0 : label is 2; - attribute C_DECIM_RATE : integer; - attribute C_DECIM_RATE of U0 : label is 1; - attribute C_ELABORATION_DIR : string; - attribute C_ELABORATION_DIR of U0 : label is "./"; - attribute C_EXT_MULT_CNFG : string; - attribute C_EXT_MULT_CNFG of U0 : label is "none"; - attribute C_FILTER_TYPE : integer; - attribute C_FILTER_TYPE of U0 : label is 2; - attribute C_FILTS_PACKED : integer; - attribute C_FILTS_PACKED of U0 : label is 0; - attribute C_HAS_ACLKEN : integer; - attribute C_HAS_ACLKEN of U0 : label is 0; - attribute C_HAS_ARESETn : integer; - attribute C_HAS_ARESETn of U0 : label is 0; - attribute C_HAS_CONFIG_CHANNEL : integer; - attribute C_HAS_CONFIG_CHANNEL of U0 : label is 0; - attribute C_INPUT_RATE : integer; - attribute C_INPUT_RATE of U0 : label is 4; - attribute C_INTERP_RATE : integer; - attribute C_INTERP_RATE of U0 : label is 4; - attribute C_IPBUFF_MEMTYPE : integer; - attribute C_IPBUFF_MEMTYPE of U0 : label is 0; - attribute C_LATENCY : integer; - attribute C_LATENCY of U0 : label is 11; - attribute C_MEM_ARRANGEMENT : integer; - attribute C_MEM_ARRANGEMENT of U0 : label is 2; - attribute C_M_DATA_HAS_TREADY : integer; - attribute C_M_DATA_HAS_TREADY of U0 : label is 0; - attribute C_M_DATA_HAS_TUSER : integer; - attribute C_M_DATA_HAS_TUSER of U0 : label is 0; - attribute C_M_DATA_TDATA_WIDTH : integer; - attribute C_M_DATA_TDATA_WIDTH of U0 : label is 16; - attribute C_M_DATA_TUSER_WIDTH : integer; - attribute C_M_DATA_TUSER_WIDTH of U0 : label is 1; - attribute C_NUM_CHANNELS : integer; - attribute C_NUM_CHANNELS of U0 : label is 1; - attribute C_NUM_FILTS : integer; - attribute C_NUM_FILTS of U0 : label is 1; - attribute C_NUM_MADDS : integer; - attribute C_NUM_MADDS of U0 : label is 5; - attribute C_NUM_RELOAD_SLOTS : integer; - attribute C_NUM_RELOAD_SLOTS of U0 : label is 1; - attribute C_NUM_TAPS : integer; - attribute C_NUM_TAPS of U0 : label is 17; - attribute C_OPBUFF_MEMTYPE : integer; - attribute C_OPBUFF_MEMTYPE of U0 : label is 0; - attribute C_OPTIMIZATION : integer; - attribute C_OPTIMIZATION of U0 : label is 0; - attribute C_OPT_MADDS : string; - attribute C_OPT_MADDS of U0 : label is "none"; - attribute C_OP_PATH_PSAMP_SRC : string; - attribute C_OP_PATH_PSAMP_SRC of U0 : label is "0"; - attribute C_OUTPUT_PATH_WIDTHS : string; - attribute C_OUTPUT_PATH_WIDTHS of U0 : label is "15"; - attribute C_OUTPUT_RATE : integer; - attribute C_OUTPUT_RATE of U0 : label is 1; - attribute C_OUTPUT_WIDTH : integer; - attribute C_OUTPUT_WIDTH of U0 : label is 15; - attribute C_OVERSAMPLING_RATE : integer; - attribute C_OVERSAMPLING_RATE of U0 : label is 1; - attribute C_PX_PATH_SRC : string; - attribute C_PX_PATH_SRC of U0 : label is "0"; - attribute C_RELOAD_TDATA_WIDTH : integer; - attribute C_RELOAD_TDATA_WIDTH of U0 : label is 1; - attribute C_ROUND_MODE : integer; - attribute C_ROUND_MODE of U0 : label is 0; - attribute C_SYMMETRY : integer; - attribute C_SYMMETRY of U0 : label is 0; - attribute C_S_DATA_HAS_FIFO : integer; - attribute C_S_DATA_HAS_FIFO of U0 : label is 0; - attribute C_S_DATA_HAS_TUSER : integer; - attribute C_S_DATA_HAS_TUSER of U0 : label is 0; - attribute C_S_DATA_TDATA_WIDTH : integer; - attribute C_S_DATA_TDATA_WIDTH of U0 : label is 8; - attribute C_S_DATA_TUSER_WIDTH : integer; - attribute C_S_DATA_TUSER_WIDTH of U0 : label is 1; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of U0 : label is "kintex7"; - attribute C_ZERO_PACKING_FACTOR : integer; - attribute C_ZERO_PACKING_FACTOR of U0 : label is 1; - attribute downgradeipidentifiedwarnings of U0 : label is "yes"; - attribute x_interface_info : string; - attribute x_interface_info of aclk : signal is "xilinx.com:signal:clock:1.0 aclk_intf CLK"; - attribute x_interface_parameter : string; - attribute x_interface_parameter of aclk : signal is "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0"; - attribute x_interface_info of m_axis_data_tvalid : signal is "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID"; - attribute x_interface_parameter of m_axis_data_tvalid : signal is "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; - attribute x_interface_info of s_axis_data_tready : signal is "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY"; - attribute x_interface_info of s_axis_data_tvalid : signal is "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID"; - attribute x_interface_parameter of s_axis_data_tvalid : signal is "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; - attribute x_interface_info of m_axis_data_tdata : signal is "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA"; - attribute x_interface_info of s_axis_data_tdata : signal is "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA"; -begin -U0: entity work.GaussFir_12m_fir_compiler_v7_2_12 - port map ( - aclk => aclk, - aclken => '1', - aresetn => '1', - event_s_config_tlast_missing => NLW_U0_event_s_config_tlast_missing_UNCONNECTED, - event_s_config_tlast_unexpected => NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED, - event_s_data_chanid_incorrect => NLW_U0_event_s_data_chanid_incorrect_UNCONNECTED, - event_s_data_tlast_missing => NLW_U0_event_s_data_tlast_missing_UNCONNECTED, - event_s_data_tlast_unexpected => NLW_U0_event_s_data_tlast_unexpected_UNCONNECTED, - event_s_reload_tlast_missing => NLW_U0_event_s_reload_tlast_missing_UNCONNECTED, - event_s_reload_tlast_unexpected => NLW_U0_event_s_reload_tlast_unexpected_UNCONNECTED, - m_axis_data_tdata(15 downto 0) => m_axis_data_tdata(15 downto 0), - m_axis_data_tlast => NLW_U0_m_axis_data_tlast_UNCONNECTED, - m_axis_data_tready => '1', - m_axis_data_tuser(0) => NLW_U0_m_axis_data_tuser_UNCONNECTED(0), - m_axis_data_tvalid => m_axis_data_tvalid, - s_axis_config_tdata(0) => '0', - s_axis_config_tlast => '0', - s_axis_config_tready => NLW_U0_s_axis_config_tready_UNCONNECTED, - s_axis_config_tvalid => '0', - s_axis_data_tdata(7 downto 0) => s_axis_data_tdata(7 downto 0), - s_axis_data_tlast => '0', - s_axis_data_tready => s_axis_data_tready, - s_axis_data_tuser(0) => '0', - s_axis_data_tvalid => s_axis_data_tvalid, - s_axis_reload_tdata(0) => '0', - s_axis_reload_tlast => '0', - s_axis_reload_tready => NLW_U0_s_axis_reload_tready_UNCONNECTED, - s_axis_reload_tvalid => '0' - ); -end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/GaussFir_12m_stub.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/GaussFir_12m_stub.v deleted file mode 100644 index 8d0a664c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/GaussFir_12m_stub.v +++ /dev/null @@ -1,26 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:33:48 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.v -// Design : GaussFir_12m -// Purpose : Stub declaration of top-level module interface -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *) -module GaussFir_12m(aclk, s_axis_data_tvalid, s_axis_data_tready, - s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata) -/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */; - input aclk; - input s_axis_data_tvalid; - output s_axis_data_tready; - input [7:0]s_axis_data_tdata; - output m_axis_data_tvalid; - output [15:0]m_axis_data_tdata; -endmodule diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/GaussFir_12m_stub.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/GaussFir_12m_stub.vhdl deleted file mode 100644 index 9caf0438..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/GaussFir_12m_stub.vhdl +++ /dev/null @@ -1,35 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:33:48 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.vhdl --- Design : GaussFir_12m --- Purpose : Stub declaration of top-level module interface --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity GaussFir_12m is - Port ( - aclk : in STD_LOGIC; - s_axis_data_tvalid : in STD_LOGIC; - s_axis_data_tready : out STD_LOGIC; - s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); - m_axis_data_tvalid : out STD_LOGIC; - m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ) - ); - -end GaussFir_12m; - -architecture stub of GaussFir_12m is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]"; -attribute x_core_info : string; -attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3"; -begin -end; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/demo_tb/tb_GaussFir_12m.vhd b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/demo_tb/tb_GaussFir_12m.vhd deleted file mode 100644 index 48ba0180..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/demo_tb/tb_GaussFir_12m.vhd +++ /dev/null @@ -1,261 +0,0 @@ --------------------------------------------------------------------------------- --- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --------------------------------------------------------------------------------- --- Description: --- This is an example testbench for the FIR Compiler IP core. --- The testbench has been generated by Vivado to accompany the IP core --- instance you have generated. --- --- This testbench is for demonstration purposes only. See note below for --- instructions on how to use it with your core. --- --- See the FIR Compiler product guide for further information --- about this core. --- --------------------------------------------------------------------------------- --- Using this testbench --- --- This testbench instantiates your generated FIR Compiler core --- instance named "GaussFir_12m". --- --- Use Vivado's Run Simulation flow to run this testbench. See the Vivado --- documentation for details. --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity tb_GaussFir_12m is -end tb_GaussFir_12m; - -architecture tb of tb_GaussFir_12m is - - ----------------------------------------------------------------------- - -- Timing constants - ----------------------------------------------------------------------- - constant CLOCK_PERIOD : time := 100 ns; - constant T_HOLD : time := 10 ns; - constant T_STROBE : time := CLOCK_PERIOD - (1 ns); - - ----------------------------------------------------------------------- - -- DUT signals - ----------------------------------------------------------------------- - - -- General signals - signal aclk : std_logic := '0'; -- the master clock - - -- Data slave channel signals - signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid - signal s_axis_data_tready : std_logic := '1'; -- slave is ready - signal s_axis_data_tdata : std_logic_vector(7 downto 0) := (others => '0'); -- data payload - - -- Data master channel signals - signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid - signal m_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload - - ----------------------------------------------------------------------- - -- Aliases for AXI channel TDATA and TUSER fields - -- These are a convenience for viewing data in a simulator waveform viewer. - -- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command - -- to prevent the simulator optimizing away these signals. - ----------------------------------------------------------------------- - - -- Data slave channel alias signals - signal s_axis_data_tdata_data : std_logic_vector(1 downto 0) := (others => '0'); - - -- Data master channel alias signals - signal m_axis_data_tdata_data : std_logic_vector(14 downto 0) := (others => '0'); - - -begin - - ----------------------------------------------------------------------- - -- Instantiate the DUT - ----------------------------------------------------------------------- - - dut : entity work.GaussFir_12m - port map ( - aclk => aclk, - s_axis_data_tvalid => s_axis_data_tvalid, - s_axis_data_tready => s_axis_data_tready, - s_axis_data_tdata => s_axis_data_tdata, - m_axis_data_tvalid => m_axis_data_tvalid, - m_axis_data_tdata => m_axis_data_tdata - ); - - ----------------------------------------------------------------------- - -- Generate clock - ----------------------------------------------------------------------- - - clock_gen : process - begin - aclk <= '0'; - wait for CLOCK_PERIOD; - loop - aclk <= '0'; - wait for CLOCK_PERIOD/2; - aclk <= '1'; - wait for CLOCK_PERIOD/2; - end loop; - end process clock_gen; - - ----------------------------------------------------------------------- - -- Generate inputs - ----------------------------------------------------------------------- - - stimuli : process - - -- Procedure to drive a number of input samples with specific data - -- data is the data value to drive on the tdata signal - -- samples is the number of zero-data input samples to drive - procedure drive_data ( data : std_logic_vector(7 downto 0); - samples : natural := 1 ) is - variable ip_count : integer := 0; - begin - ip_count := 0; - loop - s_axis_data_tvalid <= '1'; - s_axis_data_tdata <= data; - loop - wait until rising_edge(aclk); - exit when s_axis_data_tready = '1'; - end loop; - ip_count := ip_count + 1; - wait for T_HOLD; - -- Input rate is 1 input each 4 clock cycles: drive valid inputs at this rate - s_axis_data_tvalid <= '0'; - wait for CLOCK_PERIOD * 3; - exit when ip_count >= samples; - end loop; - end procedure drive_data; - - -- Procedure to drive a number of zero-data input samples - -- samples is the number of zero-data input samples to drive - procedure drive_zeros ( samples : natural := 1 ) is - begin - drive_data((others => '0'), samples); - end procedure drive_zeros; - - -- Procedure to drive an impulse and let the impulse response emerge on the data master channel - -- samples is the number of input samples to drive; default is enough for impulse response output to emerge - procedure drive_impulse ( samples : natural := 27 ) is - variable impulse : std_logic_vector(7 downto 0); - begin - impulse := (others => '0'); -- initialize unused bits to zero - impulse(1 downto 0) := "01"; - drive_data(impulse); - if samples > 1 then - drive_zeros(samples-1); - end if; - end procedure drive_impulse; - - begin - - -- Drive inputs T_HOLD time after rising edge of clock - wait until rising_edge(aclk); - wait for T_HOLD; - - -- Drive a single impulse and let the impulse response emerge - drive_impulse; - - -- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals - drive_impulse(2); -- start of impulse; data is now zero - s_axis_data_tvalid <= '0'; - wait for CLOCK_PERIOD * 20; -- provide no data for 5 input samples worth - drive_zeros(2); -- 2 normal input samples - s_axis_data_tvalid <= '1'; - wait for CLOCK_PERIOD * 20; -- provide data as fast as the core can accept it for 5 input samples worth - drive_zeros(18); -- back to normal operation - - -- End of test - report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure; - wait; - - end process stimuli; - - ----------------------------------------------------------------------- - -- Check outputs - ----------------------------------------------------------------------- - - check_outputs : process - variable check_ok : boolean := true; - begin - - -- Check outputs T_STROBE time after rising edge of clock - wait until rising_edge(aclk); - wait for T_STROBE; - - -- Do not check the output payload values, as this requires the behavioral model - -- which would make this demonstration testbench unwieldy. - -- Instead, check the protocol of the master DATA channel: - -- check that the payload is valid (not X) when TVALID is high - - if m_axis_data_tvalid = '1' then - if is_x(m_axis_data_tdata) then - report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error; - check_ok := false; - end if; - - end if; - - assert check_ok - report "ERROR: terminating test with failures." severity failure; - - end process check_outputs; - - ----------------------------------------------------------------------- - -- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing - ----------------------------------------------------------------------- - - -- Data slave channel alias signals - s_axis_data_tdata_data <= s_axis_data_tdata(1 downto 0); - - -- Data master channel alias signals: update these only when they are valid - m_axis_data_tdata_data <= m_axis_data_tdata(14 downto 0) when m_axis_data_tvalid = '1'; - -end tb; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/sim/GaussFir_12m.vhd b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/sim/GaussFir_12m.vhd deleted file mode 100644 index 0384c057..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/sim/GaussFir_12m.vhd +++ /dev/null @@ -1,281 +0,0 @@ --- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:fir_compiler:7.2 --- IP Revision: 12 - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -LIBRARY fir_compiler_v7_2_12; -USE fir_compiler_v7_2_12.fir_compiler_v7_2_12; - -ENTITY GaussFir_12m IS - PORT ( - aclk : IN STD_LOGIC; - s_axis_data_tvalid : IN STD_LOGIC; - s_axis_data_tready : OUT STD_LOGIC; - s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - m_axis_data_tvalid : OUT STD_LOGIC; - m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) - ); -END GaussFir_12m; - -ARCHITECTURE GaussFir_12m_arch OF GaussFir_12m IS - ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; - ATTRIBUTE DowngradeIPIdentifiedWarnings OF GaussFir_12m_arch: ARCHITECTURE IS "yes"; - COMPONENT fir_compiler_v7_2_12 IS - GENERIC ( - C_XDEVICEFAMILY : STRING; - C_ELABORATION_DIR : STRING; - C_COMPONENT_NAME : STRING; - C_COEF_FILE : STRING; - C_COEF_FILE_LINES : INTEGER; - C_FILTER_TYPE : INTEGER; - C_INTERP_RATE : INTEGER; - C_DECIM_RATE : INTEGER; - C_ZERO_PACKING_FACTOR : INTEGER; - C_SYMMETRY : INTEGER; - C_NUM_FILTS : INTEGER; - C_NUM_TAPS : INTEGER; - C_NUM_CHANNELS : INTEGER; - C_CHANNEL_PATTERN : STRING; - C_ROUND_MODE : INTEGER; - C_COEF_RELOAD : INTEGER; - C_NUM_RELOAD_SLOTS : INTEGER; - C_COL_MODE : INTEGER; - C_COL_PIPE_LEN : INTEGER; - C_COL_CONFIG : STRING; - C_OPTIMIZATION : INTEGER; - C_DATA_PATH_WIDTHS : STRING; - C_DATA_IP_PATH_WIDTHS : STRING; - C_DATA_PX_PATH_WIDTHS : STRING; - C_DATA_WIDTH : INTEGER; - C_COEF_PATH_WIDTHS : STRING; - C_COEF_WIDTH : INTEGER; - C_DATA_PATH_SRC : STRING; - C_COEF_PATH_SRC : STRING; - C_PX_PATH_SRC : STRING; - C_DATA_PATH_SIGN : STRING; - C_COEF_PATH_SIGN : STRING; - C_ACCUM_PATH_WIDTHS : STRING; - C_OUTPUT_WIDTH : INTEGER; - C_OUTPUT_PATH_WIDTHS : STRING; - C_ACCUM_OP_PATH_WIDTHS : STRING; - C_EXT_MULT_CNFG : STRING; - C_DATA_PATH_PSAMP_SRC : STRING; - C_OP_PATH_PSAMP_SRC : STRING; - C_NUM_MADDS : INTEGER; - C_OPT_MADDS : STRING; - C_OVERSAMPLING_RATE : INTEGER; - C_INPUT_RATE : INTEGER; - C_OUTPUT_RATE : INTEGER; - C_DATA_MEMTYPE : INTEGER; - C_COEF_MEMTYPE : INTEGER; - C_IPBUFF_MEMTYPE : INTEGER; - C_OPBUFF_MEMTYPE : INTEGER; - C_DATAPATH_MEMTYPE : INTEGER; - C_MEM_ARRANGEMENT : INTEGER; - C_DATA_MEM_PACKING : INTEGER; - C_COEF_MEM_PACKING : INTEGER; - C_FILTS_PACKED : INTEGER; - C_LATENCY : INTEGER; - C_HAS_ARESETn : INTEGER; - C_HAS_ACLKEN : INTEGER; - C_DATA_HAS_TLAST : INTEGER; - C_S_DATA_HAS_FIFO : INTEGER; - C_S_DATA_HAS_TUSER : INTEGER; - C_S_DATA_TDATA_WIDTH : INTEGER; - C_S_DATA_TUSER_WIDTH : INTEGER; - C_M_DATA_HAS_TREADY : INTEGER; - C_M_DATA_HAS_TUSER : INTEGER; - C_M_DATA_TDATA_WIDTH : INTEGER; - C_M_DATA_TUSER_WIDTH : INTEGER; - C_HAS_CONFIG_CHANNEL : INTEGER; - C_CONFIG_SYNC_MODE : INTEGER; - C_CONFIG_PACKET_SIZE : INTEGER; - C_CONFIG_TDATA_WIDTH : INTEGER; - C_RELOAD_TDATA_WIDTH : INTEGER - ); - PORT ( - aresetn : IN STD_LOGIC; - aclk : IN STD_LOGIC; - aclken : IN STD_LOGIC; - s_axis_data_tvalid : IN STD_LOGIC; - s_axis_data_tready : OUT STD_LOGIC; - s_axis_data_tlast : IN STD_LOGIC; - s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - s_axis_config_tvalid : IN STD_LOGIC; - s_axis_config_tready : OUT STD_LOGIC; - s_axis_config_tlast : IN STD_LOGIC; - s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - s_axis_reload_tvalid : IN STD_LOGIC; - s_axis_reload_tready : OUT STD_LOGIC; - s_axis_reload_tlast : IN STD_LOGIC; - s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - m_axis_data_tvalid : OUT STD_LOGIC; - m_axis_data_tready : IN STD_LOGIC; - m_axis_data_tlast : OUT STD_LOGIC; - m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - event_s_data_tlast_missing : OUT STD_LOGIC; - event_s_data_tlast_unexpected : OUT STD_LOGIC; - event_s_data_chanid_incorrect : OUT STD_LOGIC; - event_s_config_tlast_missing : OUT STD_LOGIC; - event_s_config_tlast_unexpected : OUT STD_LOGIC; - event_s_reload_tlast_missing : OUT STD_LOGIC; - event_s_reload_tlast_unexpected : OUT STD_LOGIC - ); - END COMPONENT fir_compiler_v7_2_12; - ATTRIBUTE X_INTERFACE_INFO : STRING; - ATTRIBUTE X_INTERFACE_PARAMETER : STRING; - ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA"; - ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID"; - ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA"; - ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY"; - ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID"; - ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; -BEGIN - U0 : fir_compiler_v7_2_12 - GENERIC MAP ( - C_XDEVICEFAMILY => "kintex7", - C_ELABORATION_DIR => "./", - C_COMPONENT_NAME => "GaussFir_12m", - C_COEF_FILE => "GaussFir_12m.mif", - C_COEF_FILE_LINES => 20, - C_FILTER_TYPE => 2, - C_INTERP_RATE => 4, - C_DECIM_RATE => 1, - C_ZERO_PACKING_FACTOR => 1, - C_SYMMETRY => 0, - C_NUM_FILTS => 1, - C_NUM_TAPS => 17, - C_NUM_CHANNELS => 1, - C_CHANNEL_PATTERN => "fixed", - C_ROUND_MODE => 0, - C_COEF_RELOAD => 0, - C_NUM_RELOAD_SLOTS => 1, - C_COL_MODE => 1, - C_COL_PIPE_LEN => 4, - C_COL_CONFIG => "5", - C_OPTIMIZATION => 0, - C_DATA_PATH_WIDTHS => "2", - C_DATA_IP_PATH_WIDTHS => "2", - C_DATA_PX_PATH_WIDTHS => "2", - C_DATA_WIDTH => 2, - C_COEF_PATH_WIDTHS => "14", - C_COEF_WIDTH => 14, - C_DATA_PATH_SRC => "0", - C_COEF_PATH_SRC => "0", - C_PX_PATH_SRC => "0", - C_DATA_PATH_SIGN => "0", - C_COEF_PATH_SIGN => "1", - C_ACCUM_PATH_WIDTHS => "15", - C_OUTPUT_WIDTH => 15, - C_OUTPUT_PATH_WIDTHS => "15", - C_ACCUM_OP_PATH_WIDTHS => "15", - C_EXT_MULT_CNFG => "none", - C_DATA_PATH_PSAMP_SRC => "0", - C_OP_PATH_PSAMP_SRC => "0", - C_NUM_MADDS => 5, - C_OPT_MADDS => "none", - C_OVERSAMPLING_RATE => 1, - C_INPUT_RATE => 4, - C_OUTPUT_RATE => 1, - C_DATA_MEMTYPE => 0, - C_COEF_MEMTYPE => 2, - C_IPBUFF_MEMTYPE => 0, - C_OPBUFF_MEMTYPE => 0, - C_DATAPATH_MEMTYPE => 0, - C_MEM_ARRANGEMENT => 2, - C_DATA_MEM_PACKING => 0, - C_COEF_MEM_PACKING => 0, - C_FILTS_PACKED => 0, - C_LATENCY => 11, - C_HAS_ARESETn => 0, - C_HAS_ACLKEN => 0, - C_DATA_HAS_TLAST => 0, - C_S_DATA_HAS_FIFO => 0, - C_S_DATA_HAS_TUSER => 0, - C_S_DATA_TDATA_WIDTH => 8, - C_S_DATA_TUSER_WIDTH => 1, - C_M_DATA_HAS_TREADY => 0, - C_M_DATA_HAS_TUSER => 0, - C_M_DATA_TDATA_WIDTH => 16, - C_M_DATA_TUSER_WIDTH => 1, - C_HAS_CONFIG_CHANNEL => 0, - C_CONFIG_SYNC_MODE => 0, - C_CONFIG_PACKET_SIZE => 0, - C_CONFIG_TDATA_WIDTH => 1, - C_RELOAD_TDATA_WIDTH => 1 - ) - PORT MAP ( - aresetn => '1', - aclk => aclk, - aclken => '1', - s_axis_data_tvalid => s_axis_data_tvalid, - s_axis_data_tready => s_axis_data_tready, - s_axis_data_tlast => '0', - s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), - s_axis_data_tdata => s_axis_data_tdata, - s_axis_config_tvalid => '0', - s_axis_config_tlast => '0', - s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), - s_axis_reload_tvalid => '0', - s_axis_reload_tlast => '0', - s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), - m_axis_data_tvalid => m_axis_data_tvalid, - m_axis_data_tready => '1', - m_axis_data_tdata => m_axis_data_tdata - ); -END GaussFir_12m_arch; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/GaussFir_1mp5.veo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/GaussFir_1mp5.veo deleted file mode 100644 index 0ec1b18e..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/GaussFir_1mp5.veo +++ /dev/null @@ -1,70 +0,0 @@ -// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:fir_compiler:7.2 -// IP Revision: 12 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -GaussFir_1mp5 your_instance_name ( - .aclk(aclk), // input wire aclk - .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid - .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready - .s_axis_data_tdata(s_axis_data_tdata), // input wire [7 : 0] s_axis_data_tdata - .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid - .m_axis_data_tdata(m_axis_data_tdata) // output wire [15 : 0] m_axis_data_tdata -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file GaussFir_1mp5.v when simulating -// the core, GaussFir_1mp5. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/GaussFir_1mp5.vho b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/GaussFir_1mp5.vho deleted file mode 100644 index 8b9ca7c2..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/GaussFir_1mp5.vho +++ /dev/null @@ -1,85 +0,0 @@ --- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:fir_compiler:7.2 --- IP Revision: 12 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT GaussFir_1mp5 - PORT ( - aclk : IN STD_LOGIC; - s_axis_data_tvalid : IN STD_LOGIC; - s_axis_data_tready : OUT STD_LOGIC; - s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - m_axis_data_tvalid : OUT STD_LOGIC; - m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : GaussFir_1mp5 - PORT MAP ( - aclk => aclk, - s_axis_data_tvalid => s_axis_data_tvalid, - s_axis_data_tready => s_axis_data_tready, - s_axis_data_tdata => s_axis_data_tdata, - m_axis_data_tvalid => m_axis_data_tvalid, - m_axis_data_tdata => m_axis_data_tdata - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file GaussFir_1mp5.vhd when simulating --- the core, GaussFir_1mp5. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/GaussFir_1mp5_sim_netlist.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/GaussFir_1mp5_sim_netlist.v deleted file mode 100644 index e0b32bda..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/GaussFir_1mp5_sim_netlist.v +++ /dev/null @@ -1,2607 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:33:47 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_sim_netlist.v -// Design : GaussFir_1mp5 -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* CHECK_LICENSE_TYPE = "GaussFir_1mp5,fir_compiler_v7_2_12,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *) -(* NotValidForBitStream *) -module GaussFir_1mp5 - (aclk, - s_axis_data_tvalid, - s_axis_data_tready, - s_axis_data_tdata, - m_axis_data_tvalid, - m_axis_data_tdata); - (* x_interface_info = "xilinx.com:signal:clock:1.0 aclk_intf CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *) input aclk; - (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) input s_axis_data_tvalid; - (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY" *) output s_axis_data_tready; - (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA" *) input [7:0]s_axis_data_tdata; - (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) output m_axis_data_tvalid; - (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA" *) output [15:0]m_axis_data_tdata; - - wire aclk; - wire [15:0]m_axis_data_tdata; - wire m_axis_data_tvalid; - wire [7:0]s_axis_data_tdata; - wire s_axis_data_tready; - wire s_axis_data_tvalid; - wire NLW_U0_event_s_config_tlast_missing_UNCONNECTED; - wire NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED; - wire NLW_U0_event_s_data_chanid_incorrect_UNCONNECTED; - wire NLW_U0_event_s_data_tlast_missing_UNCONNECTED; - wire NLW_U0_event_s_data_tlast_unexpected_UNCONNECTED; - wire NLW_U0_event_s_reload_tlast_missing_UNCONNECTED; - wire NLW_U0_event_s_reload_tlast_unexpected_UNCONNECTED; - wire NLW_U0_m_axis_data_tlast_UNCONNECTED; - wire NLW_U0_s_axis_config_tready_UNCONNECTED; - wire NLW_U0_s_axis_reload_tready_UNCONNECTED; - wire [0:0]NLW_U0_m_axis_data_tuser_UNCONNECTED; - - (* C_ACCUM_OP_PATH_WIDTHS = "13" *) - (* C_ACCUM_PATH_WIDTHS = "13" *) - (* C_CHANNEL_PATTERN = "fixed" *) - (* C_COEF_FILE = "GaussFir_1mp5.mif" *) - (* C_COEF_FILE_LINES = "160" *) - (* C_COEF_MEMTYPE = "2" *) - (* C_COEF_MEM_PACKING = "0" *) - (* C_COEF_PATH_SIGN = "1" *) - (* C_COEF_PATH_SRC = "0" *) - (* C_COEF_PATH_WIDTHS = "14" *) - (* C_COEF_RELOAD = "0" *) - (* C_COEF_WIDTH = "14" *) - (* C_COL_CONFIG = "5" *) - (* C_COL_MODE = "1" *) - (* C_COL_PIPE_LEN = "4" *) - (* C_COMPONENT_NAME = "GaussFir_1mp5" *) - (* C_CONFIG_PACKET_SIZE = "0" *) - (* C_CONFIG_SYNC_MODE = "0" *) - (* C_CONFIG_TDATA_WIDTH = "1" *) - (* C_DATAPATH_MEMTYPE = "0" *) - (* C_DATA_HAS_TLAST = "0" *) - (* C_DATA_IP_PATH_WIDTHS = "2" *) - (* C_DATA_MEMTYPE = "0" *) - (* C_DATA_MEM_PACKING = "0" *) - (* C_DATA_PATH_PSAMP_SRC = "0" *) - (* C_DATA_PATH_SIGN = "0" *) - (* C_DATA_PATH_SRC = "0" *) - (* C_DATA_PATH_WIDTHS = "2" *) - (* C_DATA_PX_PATH_WIDTHS = "2" *) - (* C_DATA_WIDTH = "2" *) - (* C_DECIM_RATE = "1" *) - (* C_ELABORATION_DIR = "./" *) - (* C_EXT_MULT_CNFG = "none" *) - (* C_FILTER_TYPE = "2" *) - (* C_FILTS_PACKED = "0" *) - (* C_HAS_ACLKEN = "0" *) - (* C_HAS_ARESETn = "0" *) - (* C_HAS_CONFIG_CHANNEL = "0" *) - (* C_INPUT_RATE = "32" *) - (* C_INTERP_RATE = "32" *) - (* C_IPBUFF_MEMTYPE = "0" *) - (* C_LATENCY = "11" *) - (* C_MEM_ARRANGEMENT = "2" *) - (* C_M_DATA_HAS_TREADY = "0" *) - (* C_M_DATA_HAS_TUSER = "0" *) - (* C_M_DATA_TDATA_WIDTH = "16" *) - (* C_M_DATA_TUSER_WIDTH = "1" *) - (* C_NUM_CHANNELS = "1" *) - (* C_NUM_FILTS = "1" *) - (* C_NUM_MADDS = "5" *) - (* C_NUM_RELOAD_SLOTS = "1" *) - (* C_NUM_TAPS = "129" *) - (* C_OPBUFF_MEMTYPE = "0" *) - (* C_OPTIMIZATION = "0" *) - (* C_OPT_MADDS = "none" *) - (* C_OP_PATH_PSAMP_SRC = "0" *) - (* C_OUTPUT_PATH_WIDTHS = "13" *) - (* C_OUTPUT_RATE = "1" *) - (* C_OUTPUT_WIDTH = "13" *) - (* C_OVERSAMPLING_RATE = "1" *) - (* C_PX_PATH_SRC = "0" *) - (* C_RELOAD_TDATA_WIDTH = "1" *) - (* C_ROUND_MODE = "0" *) - (* C_SYMMETRY = "0" *) - (* C_S_DATA_HAS_FIFO = "0" *) - (* C_S_DATA_HAS_TUSER = "0" *) - (* C_S_DATA_TDATA_WIDTH = "8" *) - (* C_S_DATA_TUSER_WIDTH = "1" *) - (* C_XDEVICEFAMILY = "kintex7" *) - (* C_ZERO_PACKING_FACTOR = "1" *) - (* downgradeipidentifiedwarnings = "yes" *) - GaussFir_1mp5_fir_compiler_v7_2_12 U0 - (.aclk(aclk), - .aclken(1'b1), - .aresetn(1'b1), - .event_s_config_tlast_missing(NLW_U0_event_s_config_tlast_missing_UNCONNECTED), - .event_s_config_tlast_unexpected(NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED), - .event_s_data_chanid_incorrect(NLW_U0_event_s_data_chanid_incorrect_UNCONNECTED), - .event_s_data_tlast_missing(NLW_U0_event_s_data_tlast_missing_UNCONNECTED), - .event_s_data_tlast_unexpected(NLW_U0_event_s_data_tlast_unexpected_UNCONNECTED), - .event_s_reload_tlast_missing(NLW_U0_event_s_reload_tlast_missing_UNCONNECTED), - .event_s_reload_tlast_unexpected(NLW_U0_event_s_reload_tlast_unexpected_UNCONNECTED), - .m_axis_data_tdata(m_axis_data_tdata), - .m_axis_data_tlast(NLW_U0_m_axis_data_tlast_UNCONNECTED), - .m_axis_data_tready(1'b1), - .m_axis_data_tuser(NLW_U0_m_axis_data_tuser_UNCONNECTED[0]), - .m_axis_data_tvalid(m_axis_data_tvalid), - .s_axis_config_tdata(1'b0), - .s_axis_config_tlast(1'b0), - .s_axis_config_tready(NLW_U0_s_axis_config_tready_UNCONNECTED), - .s_axis_config_tvalid(1'b0), - .s_axis_data_tdata(s_axis_data_tdata), - .s_axis_data_tlast(1'b0), - .s_axis_data_tready(s_axis_data_tready), - .s_axis_data_tuser(1'b0), - .s_axis_data_tvalid(s_axis_data_tvalid), - .s_axis_reload_tdata(1'b0), - .s_axis_reload_tlast(1'b0), - .s_axis_reload_tready(NLW_U0_s_axis_reload_tready_UNCONNECTED), - .s_axis_reload_tvalid(1'b0)); -endmodule - -(* C_ACCUM_OP_PATH_WIDTHS = "13" *) (* C_ACCUM_PATH_WIDTHS = "13" *) (* C_CHANNEL_PATTERN = "fixed" *) -(* C_COEF_FILE = "GaussFir_1mp5.mif" *) (* C_COEF_FILE_LINES = "160" *) (* C_COEF_MEMTYPE = "2" *) -(* C_COEF_MEM_PACKING = "0" *) (* C_COEF_PATH_SIGN = "1" *) (* C_COEF_PATH_SRC = "0" *) -(* C_COEF_PATH_WIDTHS = "14" *) (* C_COEF_RELOAD = "0" *) (* C_COEF_WIDTH = "14" *) -(* C_COL_CONFIG = "5" *) (* C_COL_MODE = "1" *) (* C_COL_PIPE_LEN = "4" *) -(* C_COMPONENT_NAME = "GaussFir_1mp5" *) (* C_CONFIG_PACKET_SIZE = "0" *) (* C_CONFIG_SYNC_MODE = "0" *) -(* C_CONFIG_TDATA_WIDTH = "1" *) (* C_DATAPATH_MEMTYPE = "0" *) (* C_DATA_HAS_TLAST = "0" *) -(* C_DATA_IP_PATH_WIDTHS = "2" *) (* C_DATA_MEMTYPE = "0" *) (* C_DATA_MEM_PACKING = "0" *) -(* C_DATA_PATH_PSAMP_SRC = "0" *) (* C_DATA_PATH_SIGN = "0" *) (* C_DATA_PATH_SRC = "0" *) -(* C_DATA_PATH_WIDTHS = "2" *) (* C_DATA_PX_PATH_WIDTHS = "2" *) (* C_DATA_WIDTH = "2" *) -(* C_DECIM_RATE = "1" *) (* C_ELABORATION_DIR = "./" *) (* C_EXT_MULT_CNFG = "none" *) -(* C_FILTER_TYPE = "2" *) (* C_FILTS_PACKED = "0" *) (* C_HAS_ACLKEN = "0" *) -(* C_HAS_ARESETn = "0" *) (* C_HAS_CONFIG_CHANNEL = "0" *) (* C_INPUT_RATE = "32" *) -(* C_INTERP_RATE = "32" *) (* C_IPBUFF_MEMTYPE = "0" *) (* C_LATENCY = "11" *) -(* C_MEM_ARRANGEMENT = "2" *) (* C_M_DATA_HAS_TREADY = "0" *) (* C_M_DATA_HAS_TUSER = "0" *) -(* C_M_DATA_TDATA_WIDTH = "16" *) (* C_M_DATA_TUSER_WIDTH = "1" *) (* C_NUM_CHANNELS = "1" *) -(* C_NUM_FILTS = "1" *) (* C_NUM_MADDS = "5" *) (* C_NUM_RELOAD_SLOTS = "1" *) -(* C_NUM_TAPS = "129" *) (* C_OPBUFF_MEMTYPE = "0" *) (* C_OPTIMIZATION = "0" *) -(* C_OPT_MADDS = "none" *) (* C_OP_PATH_PSAMP_SRC = "0" *) (* C_OUTPUT_PATH_WIDTHS = "13" *) -(* C_OUTPUT_RATE = "1" *) (* C_OUTPUT_WIDTH = "13" *) (* C_OVERSAMPLING_RATE = "1" *) -(* C_PX_PATH_SRC = "0" *) (* C_RELOAD_TDATA_WIDTH = "1" *) (* C_ROUND_MODE = "0" *) -(* C_SYMMETRY = "0" *) (* C_S_DATA_HAS_FIFO = "0" *) (* C_S_DATA_HAS_TUSER = "0" *) -(* C_S_DATA_TDATA_WIDTH = "8" *) (* C_S_DATA_TUSER_WIDTH = "1" *) (* C_XDEVICEFAMILY = "kintex7" *) -(* C_ZERO_PACKING_FACTOR = "1" *) (* ORIG_REF_NAME = "fir_compiler_v7_2_12" *) (* downgradeipidentifiedwarnings = "yes" *) -module GaussFir_1mp5_fir_compiler_v7_2_12 - (aresetn, - aclk, - aclken, - s_axis_data_tvalid, - s_axis_data_tready, - s_axis_data_tlast, - s_axis_data_tuser, - s_axis_data_tdata, - s_axis_config_tvalid, - s_axis_config_tready, - s_axis_config_tlast, - s_axis_config_tdata, - s_axis_reload_tvalid, - s_axis_reload_tready, - s_axis_reload_tlast, - s_axis_reload_tdata, - m_axis_data_tvalid, - m_axis_data_tready, - m_axis_data_tlast, - m_axis_data_tuser, - m_axis_data_tdata, - event_s_data_tlast_missing, - event_s_data_tlast_unexpected, - event_s_data_chanid_incorrect, - event_s_config_tlast_missing, - event_s_config_tlast_unexpected, - event_s_reload_tlast_missing, - event_s_reload_tlast_unexpected); - input aresetn; - input aclk; - input aclken; - input s_axis_data_tvalid; - output s_axis_data_tready; - input s_axis_data_tlast; - input [0:0]s_axis_data_tuser; - input [7:0]s_axis_data_tdata; - input s_axis_config_tvalid; - output s_axis_config_tready; - input s_axis_config_tlast; - input [0:0]s_axis_config_tdata; - input s_axis_reload_tvalid; - output s_axis_reload_tready; - input s_axis_reload_tlast; - input [0:0]s_axis_reload_tdata; - output m_axis_data_tvalid; - input m_axis_data_tready; - output m_axis_data_tlast; - output [0:0]m_axis_data_tuser; - output [15:0]m_axis_data_tdata; - output event_s_data_tlast_missing; - output event_s_data_tlast_unexpected; - output event_s_data_chanid_incorrect; - output event_s_config_tlast_missing; - output event_s_config_tlast_unexpected; - output event_s_reload_tlast_missing; - output event_s_reload_tlast_unexpected; - - wire \ ; - wire aclk; - wire [12:0]\^m_axis_data_tdata ; - wire m_axis_data_tvalid; - wire [7:0]s_axis_data_tdata; - wire s_axis_data_tready; - wire s_axis_data_tvalid; - wire NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED; - wire NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED; - wire NLW_i_synth_event_s_data_chanid_incorrect_UNCONNECTED; - wire NLW_i_synth_event_s_data_tlast_missing_UNCONNECTED; - wire NLW_i_synth_event_s_data_tlast_unexpected_UNCONNECTED; - wire NLW_i_synth_event_s_reload_tlast_missing_UNCONNECTED; - wire NLW_i_synth_event_s_reload_tlast_unexpected_UNCONNECTED; - wire NLW_i_synth_m_axis_data_tlast_UNCONNECTED; - wire NLW_i_synth_s_axis_config_tready_UNCONNECTED; - wire NLW_i_synth_s_axis_reload_tready_UNCONNECTED; - wire [14:12]NLW_i_synth_m_axis_data_tdata_UNCONNECTED; - wire [0:0]NLW_i_synth_m_axis_data_tuser_UNCONNECTED; - - assign event_s_config_tlast_missing = \ ; - assign event_s_config_tlast_unexpected = \ ; - assign event_s_data_chanid_incorrect = \ ; - assign event_s_data_tlast_missing = \ ; - assign event_s_data_tlast_unexpected = \ ; - assign event_s_reload_tlast_missing = \ ; - assign event_s_reload_tlast_unexpected = \ ; - assign m_axis_data_tdata[15] = \^m_axis_data_tdata [12]; - assign m_axis_data_tdata[14] = \^m_axis_data_tdata [12]; - assign m_axis_data_tdata[13] = \^m_axis_data_tdata [12]; - assign m_axis_data_tdata[12:0] = \^m_axis_data_tdata [12:0]; - assign m_axis_data_tlast = \ ; - assign m_axis_data_tuser[0] = \ ; - assign s_axis_config_tready = \ ; - assign s_axis_reload_tready = \ ; - GND GND - (.G(\ )); - (* C_ACCUM_OP_PATH_WIDTHS = "13" *) - (* C_ACCUM_PATH_WIDTHS = "13" *) - (* C_CHANNEL_PATTERN = "fixed" *) - (* C_COEF_FILE = "GaussFir_1mp5.mif" *) - (* C_COEF_FILE_LINES = "160" *) - (* C_COEF_MEMTYPE = "2" *) - (* C_COEF_MEM_PACKING = "0" *) - (* C_COEF_PATH_SIGN = "1" *) - (* C_COEF_PATH_SRC = "0" *) - (* C_COEF_PATH_WIDTHS = "14" *) - (* C_COEF_RELOAD = "0" *) - (* C_COEF_WIDTH = "14" *) - (* C_COL_CONFIG = "5" *) - (* C_COL_MODE = "1" *) - (* C_COL_PIPE_LEN = "4" *) - (* C_COMPONENT_NAME = "GaussFir_1mp5" *) - (* C_CONFIG_PACKET_SIZE = "0" *) - (* C_CONFIG_SYNC_MODE = "0" *) - (* C_CONFIG_TDATA_WIDTH = "1" *) - (* C_DATAPATH_MEMTYPE = "0" *) - (* C_DATA_HAS_TLAST = "0" *) - (* C_DATA_IP_PATH_WIDTHS = "2" *) - (* C_DATA_MEMTYPE = "0" *) - (* C_DATA_MEM_PACKING = "0" *) - (* C_DATA_PATH_PSAMP_SRC = "0" *) - (* C_DATA_PATH_SIGN = "0" *) - (* C_DATA_PATH_SRC = "0" *) - (* C_DATA_PATH_WIDTHS = "2" *) - (* C_DATA_PX_PATH_WIDTHS = "2" *) - (* C_DATA_WIDTH = "2" *) - (* C_DECIM_RATE = "1" *) - (* C_ELABORATION_DIR = "./" *) - (* C_EXT_MULT_CNFG = "none" *) - (* C_FILTER_TYPE = "2" *) - (* C_FILTS_PACKED = "0" *) - (* C_HAS_ACLKEN = "0" *) - (* C_HAS_ARESETn = "0" *) - (* C_HAS_CONFIG_CHANNEL = "0" *) - (* C_INPUT_RATE = "32" *) - (* C_INTERP_RATE = "32" *) - (* C_IPBUFF_MEMTYPE = "0" *) - (* C_LATENCY = "11" *) - (* C_MEM_ARRANGEMENT = "2" *) - (* C_M_DATA_HAS_TREADY = "0" *) - (* C_M_DATA_HAS_TUSER = "0" *) - (* C_M_DATA_TDATA_WIDTH = "16" *) - (* C_M_DATA_TUSER_WIDTH = "1" *) - (* C_NUM_CHANNELS = "1" *) - (* C_NUM_FILTS = "1" *) - (* C_NUM_MADDS = "5" *) - (* C_NUM_RELOAD_SLOTS = "1" *) - (* C_NUM_TAPS = "129" *) - (* C_OPBUFF_MEMTYPE = "0" *) - (* C_OPTIMIZATION = "0" *) - (* C_OPT_MADDS = "none" *) - (* C_OP_PATH_PSAMP_SRC = "0" *) - (* C_OUTPUT_PATH_WIDTHS = "13" *) - (* C_OUTPUT_RATE = "1" *) - (* C_OUTPUT_WIDTH = "13" *) - (* C_OVERSAMPLING_RATE = "1" *) - (* C_PX_PATH_SRC = "0" *) - (* C_RELOAD_TDATA_WIDTH = "1" *) - (* C_ROUND_MODE = "0" *) - (* C_SYMMETRY = "0" *) - (* C_S_DATA_HAS_FIFO = "0" *) - (* C_S_DATA_HAS_TUSER = "0" *) - (* C_S_DATA_TDATA_WIDTH = "8" *) - (* C_S_DATA_TUSER_WIDTH = "1" *) - (* C_XDEVICEFAMILY = "kintex7" *) - (* C_ZERO_PACKING_FACTOR = "1" *) - (* downgradeipidentifiedwarnings = "yes" *) - GaussFir_1mp5_fir_compiler_v7_2_12_viv i_synth - (.aclk(aclk), - .aclken(1'b0), - .aresetn(1'b0), - .event_s_config_tlast_missing(NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED), - .event_s_config_tlast_unexpected(NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED), - .event_s_data_chanid_incorrect(NLW_i_synth_event_s_data_chanid_incorrect_UNCONNECTED), - .event_s_data_tlast_missing(NLW_i_synth_event_s_data_tlast_missing_UNCONNECTED), - .event_s_data_tlast_unexpected(NLW_i_synth_event_s_data_tlast_unexpected_UNCONNECTED), - .event_s_reload_tlast_missing(NLW_i_synth_event_s_reload_tlast_missing_UNCONNECTED), - .event_s_reload_tlast_unexpected(NLW_i_synth_event_s_reload_tlast_unexpected_UNCONNECTED), - .m_axis_data_tdata({\^m_axis_data_tdata [12],NLW_i_synth_m_axis_data_tdata_UNCONNECTED[14:12],\^m_axis_data_tdata [11:0]}), - .m_axis_data_tlast(NLW_i_synth_m_axis_data_tlast_UNCONNECTED), - .m_axis_data_tready(1'b0), - .m_axis_data_tuser(NLW_i_synth_m_axis_data_tuser_UNCONNECTED[0]), - .m_axis_data_tvalid(m_axis_data_tvalid), - .s_axis_config_tdata(1'b0), - .s_axis_config_tlast(1'b0), - .s_axis_config_tready(NLW_i_synth_s_axis_config_tready_UNCONNECTED), - .s_axis_config_tvalid(1'b0), - .s_axis_data_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,s_axis_data_tdata[1:0]}), - .s_axis_data_tlast(1'b0), - .s_axis_data_tready(s_axis_data_tready), - .s_axis_data_tuser(1'b0), - .s_axis_data_tvalid(s_axis_data_tvalid), - .s_axis_reload_tdata(1'b0), - .s_axis_reload_tlast(1'b0), - .s_axis_reload_tready(NLW_i_synth_s_axis_reload_tready_UNCONNECTED), - .s_axis_reload_tvalid(1'b0)); -endmodule -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "XILINX" -`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" -`pragma protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=64) -`pragma protect key_block -I5jBxSA30qMppesbkWzApATD001KfSyiO/EXeiSfqG/mDp7bWT98b6O2aLKwO2KBiQHns7D4kNzR -1vJ+KztHDg== - -`pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128) -`pragma protect key_block -WMu7kFTLnidedbfVrZuh/7ca7CUttjqfOqFAqALtw+gkp4fPh7ZCC2c3FriF2MGJNdt0inCBZQ1w -ERGO+2E2lzKAF62aWczdna33VjhJbQEhVD66TE3XkcNa3kH5qqUhb+EgT0e6ErzcmqjyjnkFxoKK -XKvbLV/yC8Myvjbgd1A= - -`pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`pragma protect key_block -xD5n0VbWIE6P1VxF0RmDDu2TYD4jh2LNu0PcTQhqBRKitH0v3xG4GrD/vuHfz6qhNoYV25YBOEWi -7kVjcZSXNFtC5ITuwneS2ZMRryiXpM8fFiU2j9L4eELr2/mHrJrVvacPISdaWzzVZMaXZGjjLF31 -zK98DBrt3GchBNvrcOgQmuPVAvjrSEZ+P+LhtLFVfq/zmFgYzV3AELJD6jr7elUkLyTjsJWEFYcf -b43n7Hb0i+cIbRt6Dd+v0kyLoVGDXUE7IXud31zG1Rotvh/eF07hFqqllLHHu2UWUNW8RAWEy1Fo -3/0kdpsYoC+scwVlEiw6L4xm3ZvOMO3xLhlx9Q== - -`pragma protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`pragma protect key_block -fQrDOnMjpZojQhY1c1rw1hwuEu2Y2M8ofkmIyKutN5o3WWgs402wk38nunx4Rn3nJ4alOoXDi3N8 -wCK4FFFUnB/83xpx5yiE801fH9CrSpiGk2CFUTGUPQ2AKib6X7q/ypXzIE3Xi/Fp8v68pOYfzYgB -DWCJiGAer9WgqVkNoAOLB2B99+hjhpjUr+bqeFKCONh+smCJvnzi5NuFbGTw6NRi9XF/fOBJpA7N -7mSHNKQA9TZaG877TLVUYWhpu8Tllt4YOnNvOy5csoZO6jBxXCjuxWmM9dl9WSOXp2HX/onR6rpz -sNUbO2lQftIr2WNh0Jv073YUwDxDBpl586IEWg== - -`pragma protect key_keyowner="Xilinx", key_keyname="xilinxt_2019_02", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`pragma protect key_block -Yt/xtD+YwHpwIG7cpV+YFKRLELTuOpDyL++EbS2PSHkTTnkY+SDEglVSGBUkgEMCy4FK2fL2wt2N -qjVnO38YwcIpkFA3hdVylOufwvfkyXzLnO4I/oXAmiPI3b+yEyPArGvVOGpDgyd07VUs/V9x8yNF -fJU+AQwpZcLwvczmvjIU4/eR8fdXCMBV/C6JW2N+CHrwTU69ne3XstJaVfOIPupKIpZjLVLIrAYs -UQMdOWUz5FDENYd645Oho01vEbgtbLb+GrcpRedjCAIY2LgO42kQ9rDb7oVFFsUuoIPnWF4fLEjb -Pq5mb00fUdX1TzSueiRRmMIn69wkk/QkSb8jag== - -`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128) -`pragma protect key_block -S5Ng9U2ICFR2ATladKVkI9g1B4mI1wuXRMAnMNgbxvoijFO8db10A3+6fvjuey2Yzxp1Hf4dZcYN -c/lBn1GB/WXkp/IAC1a0hNWcvyknzHaPnT0XXAr2t5Xncs67wJ8pN5Gp2D1qrZQQzDnNoYG2S/bd -YiWvkcmY78GRhm+UXVk= - -`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`pragma protect key_block -HAhvjf08asX78hSz5fysjZpqt6weT/hM0aPw+9OZ6ZFgT2U7lNg0+xRLXb9nzh4EewIjMgSyWdbq -Irle9J+zY0NjMxQhF0AU4uZR3mjfrD6Ci+uFgn2FssxWd9BHXv/cqiRhCZU2ybiUWpzjYSU0dR0h -2hg5PlS+G3dlVbHVWfTO0k/13GXvSnwpugvkHI9jnHi2x1XT0gcm6G9Zhe1EI5PttaiCD/hIEpFy -dE9D4GBdwkisk7PYdWIuZlsBFWDWcbGou0FPnNgoQxkmsqJf2be0EcDmDksiH0SWYeS3S/ePy+eL -24oKZ31y2jK7rq17ZMr87dpRzRIdMsvbgjgGWg== - -`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`pragma protect key_block -btcBLREoCU/igGR/QFOar7vvya26XxuB61KkppFlAnzkpounYMRvjpm5+k2yevW8k8PzuO2wEhwB -YUCAVsZC61Nq+VX4UqTu37l4HqpxIovFYOO6bcEdNknZKXV6s+/Ett+dHIX8nSkTikn2kxLbKoX4 -CTbNAt73HqotRTGnfjZSAzuwDXVyogmGh3OssJmjM8W2P0I4QfLI45P34Z4m20KM7RzIRcRrtOao -BLSuYEPx0SbzpaYwG/0uEpvZnziP8WhXxmMzxW5IYyb2yYEfjL9oRdxLoaxPnctV7ZcepoPkDekr -8Crn30yBHu2Xj5jUQK2eK0SHGKr+nud/oi89YA== - -`pragma protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`pragma protect key_block -QOyk7aC5metmmMN1Vds1Mf8Gz+7qVWxdcITqDim4CJPbeb/KjUKbN5plGxhlhv59TDcnTdt4wfam -QoEwD3hDc2wJTpS8vZv3SMRV8v/AbWcYz85tb/vssNSXy4k3diA+TAZG8nVQ6Y5EcnkSfSdFKDzQ -PkXuJpCLIgSPNJqL78AUSX96EHqoTiXcPjQKTqDluBSaJNs5LhPF20Dzb3LDZQXom1uxRZMQUGVQ -Rwu0Ul5aLPr3qfstPotWvL/SQTM9B1HbrZcwaZL+bQUXj3gonkYIzgxLnXqDiXLG2TqjFg95Fbsi -rltgs35eCawt2CnDzCg1AD929foPsSymYxWJOQ== - -`pragma protect data_method = "AES128-CBC" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 118832) -`pragma protect data_block -xRkbFHYjHBL92y0nttsod96JEIQQo7pWjDqCbvr8+o9UvyWU41a5jrY6E23iS9MJ7Ux1XFnCAkUQ -UxL+vamJwWtefz4WDIXKlmXs5ifACqpKjTzi8P0lo9389LqogNJLifFafAGu/qGxXn90yHbeAUSA -AQ+7PVIwVRJjLiTRnGWFEwP358PmJBi98ZNpy8D0gby34pEHMmA3LlrS/wyFTQbtt/kExZ9wf1T6 -GOGIZt/akc3Tf0u9m8f+oJCQAf+hZEjRvKvo+X1TBobyH8LGa6Xb1B1qq76g9iChT633Yr0vfrwl -TkmCjO/qJNu5pZy2Fb+Tgrd993enk3nA8dkESNMqlNXi858GxqXkOvrrnIm25PRloITTgeT778ff -1HOgrV+rx2iPD6egb6AYhzx7RCulI0vm38TWtlaU+rt0Ch1qN8ndUGZXytQh9mZ/rpIextgTrSHn -6BvYNQ/Q66jjPBURGAwvMjwNFR0zSyS8e0Mw8VgTNyp8UiJLNVhtWHi+8Z6cE0ytLTBklYt/GkTM -kT/uzobbyyjOApzCp/We8rMOV/U4tY6GoDy8U5s+yGsAz1+olMfg/GFCXDsHP6qfpox5w+BRpGmh -DKc4RHqyIYQE+MJzWLCooch7u6Fuai838bTX2jeyfrAJNtOGF4eyBBsmyXMLTvj+EI91JC+gpsX0 -Ev6o/+qn9PXhdyqiWcTWslfjL6gWO8C3lcPG7R3hca12IBOjEw2dKMrOUm/auRY1cO4NidCHSdTs -x9ybyx3KhATzMev0t2VCVjh3veKA1bOCgclL9rQqcZ/l8ZyZATB/XK5YvCrjJp5OPb5+RdvZvU2v -JxIkHBNW/wCDag4YwQcBawL63pgkXf1Qu4E5n7pQBL6j5bDOmmuLGj9BxXdCuIdNsYxl7z34Re4B -L0uUMPJRcdmK34WnQq5h2bvApaRB2cbIPphg0RdAqZ3MXHYX6ejwxtEeV8lZ1eXcF9NXpKHb2AMy -vWbre6+OHUujqClwwLjiVRpLdPYJm63loqtbavmSmdmgyAwRDIquAtiDNarvW/b/dftjTmyc3LcA -o5u4DW2q4oOgPoo1WL+yoaZwFBXgUQq5Iuhwm/ExaaDycPnesE8ECvIBHL20JY6/bYOIAAlVROro -E+Od2zEh8FPOD8bq5IDBZY76nHb3/AK1k/pyR4o32LGK0a5p3gusO6ALxoILxJLL5/Pt2a6cz9O9 -1mXJOf6sFXwh8AEGB55iVooYexGBGHyHw60vxoFRdmh/10ZwBqgrBVBX0+5rWcVS3Ujca0NC5xRt -p1/Z4g38F/vcw9+lzsjQzecb6LJ6LaQgpvKUBcyvGo0gz6gaRAckFXNVU07GeJ1J1RB4EnRZZxMr -ZrvohEg5IHs+hBgGQDBvJwabQpLIO3v29BhIZBvE57EBuDMv9u0A/UdMducWOLg9ZTwDC+riSnEV -aCvQhN3zTA5/biMRVfQr+FjAHX8ivM4XNEBX94A6AOs/2pGdh9nYsQJr37T/jHsArLH80qwXy12T -xcgtFDHcxCluOBI80KA2XrxVG9t7WuBeOtod8crhcvKU6KglwZaHTxlkHraXH9IVOooGm2Xbp5vF -/SmKo/f9s746ftXnJxKDtsiRJgMxqOE1PTLNrc/acPlxkRnFCHT0NmclP4eSm9KjqOoVlJn/559c -9LHA6Jjy5FSlR3kfonN5AIh+Mf1W2D8b1oLfUG93bDeXvFwxtHeK2i2kx/5xn2bTQPdjwVshzS/D -f/2gsemN6llREi39nlCg4ZiiwJtbh9kt+lxqYekHNMq2IysdYKGXYqhgdavYtkNU3RIG5Fik7Wuq -Cm/kcR1fcBNn5/xO2y2NEq7DWnoAChtIppYE1z4lIB28vqS4X3TNKsm2aeVbEmjQMcI9fhRKzTBS -4YQKeI4rluf0rXs2Qkg9fI075rRkMw8yzzp52EJk5WEzVu8KbFOru3c9Lzp868/+vGb/R7iC0tPj -QpaAFhmq5Ir9nZrm6gQ5HhWuodyMmX4NwZlGP2SdHlSjgCB5lT6nXA5/544dliQ+1AdCOzuOdCTk -/pzBgc259SUIaQ9ea68yYSriddRcgLRfgajVZLGaXQOaBqASHpvsBoyVaR5W33LEBJXfVKRpOYVP -DKOXHsfrLT67BB/CW/YLPAQCEfxPc4FJalzqS1dg23n1lIqiQd1JxHu6O4+tbNHwLcz78oxzpRa+ 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-55niUjUH7aVk9dmlJ6LGEN5pCPCh1QOpDaIAEnbvwbD5DFIpJSiu1r7HLRKUimI5l5L5KcEEUSf3 -eNVU/IqkIEGFQceffezhFIhiV9BxCDglLtn97W21MRqsKwH5n/lW1Cn79+XbRwfZk+DouhocGwrX -1F2qMcdpVywPz9MiQIYadEyaiBD0/MNFBl8hedkw1QnJ5mu2vXrZ7km5RlHaKYwkMyPelFWzM5ZQ -fZj0YGLukXV9NzTqyc4C27b96cMO9Ry6J0e/4iEZINor+u1U9zQGo2+YBN8= -`pragma protect end_protected -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/GaussFir_1mp5_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/GaussFir_1mp5_sim_netlist.vhdl deleted file mode 100644 index 61e717d9..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/GaussFir_1mp5_sim_netlist.vhdl +++ /dev/null @@ -1,3562 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:33:47 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_sim_netlist.vhdl --- Design : GaussFir_1mp5 --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -`protect begin_protected -`protect version = 1 -`protect encrypt_agent = "XILINX" -`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" -`protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=64) -`protect key_block -I5jBxSA30qMppesbkWzApATD001KfSyiO/EXeiSfqG/mDp7bWT98b6O2aLKwO2KBiQHns7D4kNzR -1vJ+KztHDg== - -`protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=128) -`protect key_block -WMu7kFTLnidedbfVrZuh/7ca7CUttjqfOqFAqALtw+gkp4fPh7ZCC2c3FriF2MGJNdt0inCBZQ1w -ERGO+2E2lzKAF62aWczdna33VjhJbQEhVD66TE3XkcNa3kH5qqUhb+EgT0e6ErzcmqjyjnkFxoKK -XKvbLV/yC8Myvjbgd1A= - -`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`protect key_block -xD5n0VbWIE6P1VxF0RmDDu2TYD4jh2LNu0PcTQhqBRKitH0v3xG4GrD/vuHfz6qhNoYV25YBOEWi -7kVjcZSXNFtC5ITuwneS2ZMRryiXpM8fFiU2j9L4eELr2/mHrJrVvacPISdaWzzVZMaXZGjjLF31 -zK98DBrt3GchBNvrcOgQmuPVAvjrSEZ+P+LhtLFVfq/zmFgYzV3AELJD6jr7elUkLyTjsJWEFYcf -b43n7Hb0i+cIbRt6Dd+v0kyLoVGDXUE7IXud31zG1Rotvh/eF07hFqqllLHHu2UWUNW8RAWEy1Fo -3/0kdpsYoC+scwVlEiw6L4xm3ZvOMO3xLhlx9Q== - -`protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`protect key_block -fQrDOnMjpZojQhY1c1rw1hwuEu2Y2M8ofkmIyKutN5o3WWgs402wk38nunx4Rn3nJ4alOoXDi3N8 -wCK4FFFUnB/83xpx5yiE801fH9CrSpiGk2CFUTGUPQ2AKib6X7q/ypXzIE3Xi/Fp8v68pOYfzYgB -DWCJiGAer9WgqVkNoAOLB2B99+hjhpjUr+bqeFKCONh+smCJvnzi5NuFbGTw6NRi9XF/fOBJpA7N -7mSHNKQA9TZaG877TLVUYWhpu8Tllt4YOnNvOy5csoZO6jBxXCjuxWmM9dl9WSOXp2HX/onR6rpz -sNUbO2lQftIr2WNh0Jv073YUwDxDBpl586IEWg== - -`protect key_keyowner="Xilinx", key_keyname="xilinxt_2019_02", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`protect key_block -Yt/xtD+YwHpwIG7cpV+YFKRLELTuOpDyL++EbS2PSHkTTnkY+SDEglVSGBUkgEMCy4FK2fL2wt2N -qjVnO38YwcIpkFA3hdVylOufwvfkyXzLnO4I/oXAmiPI3b+yEyPArGvVOGpDgyd07VUs/V9x8yNF -fJU+AQwpZcLwvczmvjIU4/eR8fdXCMBV/C6JW2N+CHrwTU69ne3XstJaVfOIPupKIpZjLVLIrAYs -UQMdOWUz5FDENYd645Oho01vEbgtbLb+GrcpRedjCAIY2LgO42kQ9rDb7oVFFsUuoIPnWF4fLEjb -Pq5mb00fUdX1TzSueiRRmMIn69wkk/QkSb8jag== - -`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=128) -`protect key_block -S5Ng9U2ICFR2ATladKVkI9g1B4mI1wuXRMAnMNgbxvoijFO8db10A3+6fvjuey2Yzxp1Hf4dZcYN -c/lBn1GB/WXkp/IAC1a0hNWcvyknzHaPnT0XXAr2t5Xncs67wJ8pN5Gp2D1qrZQQzDnNoYG2S/bd -YiWvkcmY78GRhm+UXVk= - -`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`protect key_block -HAhvjf08asX78hSz5fysjZpqt6weT/hM0aPw+9OZ6ZFgT2U7lNg0+xRLXb9nzh4EewIjMgSyWdbq -Irle9J+zY0NjMxQhF0AU4uZR3mjfrD6Ci+uFgn2FssxWd9BHXv/cqiRhCZU2ybiUWpzjYSU0dR0h -2hg5PlS+G3dlVbHVWfTO0k/13GXvSnwpugvkHI9jnHi2x1XT0gcm6G9Zhe1EI5PttaiCD/hIEpFy -dE9D4GBdwkisk7PYdWIuZlsBFWDWcbGou0FPnNgoQxkmsqJf2be0EcDmDksiH0SWYeS3S/ePy+eL -24oKZ31y2jK7rq17ZMr87dpRzRIdMsvbgjgGWg== - -`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`protect key_block -gyGLEBcsOnacLzQUOxKDjcmw0ipdTrlPO280INIMNCYIbqlV3SsC+mrVyw7BL6oEWPCN570+1t7t -J3HJK7JLAkHwpYBipAjux2UhA+O/4Q2OoKuysoFFLHs0iTK2VT6wG+q+TQF+XaGI/kkFucaYSrE4 -FHkJkM+lA6pBOC3Uv2FWLr93XRKHfrXrYmJBznJjAX+w/OjTQgGLyBfXMLsOX1LcMnN/PbX7Sf3Y -pwDXz9gcasag0Dhwi6o9fHnW6oHs0Lz+SReJ71Useq01sgIA3JQwblUoQ1ElFaxaLPfBrtnE3p1w -GBtsbiyllYKzcOy6Crjmx6DlP1inj3IxuZ1+fg== - -`protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`protect key_block -3QkFB6pXKTzGzaqSXrV21Qo1VVeMZGyJDfKUAW0Gn/tLHF9wYMPIMyMsrg2CkuXEziMZfWf6brJ6 -1EhiPbi01ICAsikmkpI4l1U2LIXxzauoM3c5hw4hO+1HT4d+V235So/JfFc/gKvRdqFFIj3fghxO -W80Q9C2GqBBFjTs9skUZRrkDsi83EnML3jYAu4e/BN5O/Pss4b/RejqxYKqZlxl/bXKj1X7raVDc -cU/SFogloK+NYEmP+110ai081Mx/N+kmljZYe8JncRGR6Ljx2fJ6ECu23P3xVYP6NlIH6tOuKRba -DeY/TDtirLc5z86PUFgtRZ2RHw99Y9knKjZxQg== - -`protect data_method = "AES128-CBC" -`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 166752) -`protect data_block -xseTrOLIKfNEvJ4C1VfejwEJyeVkvCv6R0F79vqizmRwC+ZpIAIfcPaT3Cj2s/FDUcFkymiTN4sK -Cydd8vYeLrq/c3sx00VyrGfslrRw5125f4GYudhklLbfD/xqaNLDJI2IXRC1Ca6eQFifwr3JyTZ9 -kzxVMTPSuzg2rV5K9xYWaCf6B3qLJWoNeY5ESyPpM5GhCEbZiy1t3A8YOXVjpzyP1VXKICjEbYgD -HphaJvzaQy9EfS+vp7NCHhAuLyuDrt4iuKPuYsTU7E7MLYxw3IYj7E35uCA4eH50BCDll1zUe2bk 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-uPx473mDbh3kUcbOsuWeI05dGlT52137D8vhpheanCMb6xV0C5WyxcijlPrBzmTJTlqeqXG3gAU6 -qLCZ+mgbF3khX6ORzBimuX0BLKW8NGBCfT3PdsgGtEV9+Q81oYIyC7k9fuSTiBaivzQAwvfREGul -oukYPN8KSwXs75d5QnWW7PvaurOY1Mb7it8nwbyXSoXvcUbvh05pLnx31hciq4IArX2H3B6PJqru -dHyTRyo4A8M5YQUtRDbVw0gxSu+Wesb4rJ+UipENHRZhhxrIVu+b9QYnRGr9eYNtuShpptU8C8v8 -z6Bi4WlLoy3XHmfuvzkVLTrHSFoKFyNSKp5EUTFUKC7EYFLoT42IvktgHluKB6ltCmSPucH+JJ/j -RMjErXYuKrTxwrcBUYq2i3YcEOI7dY0eqosCQjmLLmNrm2seJ56l7lWiYO5liBux6rXh9MAdiRtS -njxIDEIuoGr0qBkceJYI0CI5UsLeM837chTyF2CXh73xv3Vqhn51UtCVvbFH8GNcpbJlFo43sHaQ -0WkBcOdSnN0GCsv9q7PudVVOlFr+wgVNAYWSsWOQA3HbM+AHTtnTJY+jTSUKRM1+iubqSwochLEY -fRwbQkQf+qFPHSrVT+bXGnhHBr+AHWZfl3AXbfz7QAvSp2XJViTB49SQ5N0Tt4tmgoyLuH7ZLVMG -v7Bj6kLjaqybOKpK27RmURt1tVhp/gO5yrVm9EHuF8A4SuHYMxQGZO4XEA1KHrW4DU8QU1tc6Pt1 -lEhguSRn5mWU9WDkVWTayQqR+syI/0nAiRn8GEBiLpXfPKrLalsNk1Hh6Bhxb1MJ7m86ARTeYa+y -wAbcWArTd82mSleu2tZZMyH9TZylL683S6FKiGDF/0vJw3BdD/KXHHtYeoNLLRQCkJHVviOLeYWb -srd8q0/+Hho4EUHhZqrAbuyYnpQsUlslRQpm1xlcMCLuP71ztpDOYhajQMSy/YIg9mkr3V2BMtFg -krHx+upU3QRGi7WGXlsWhbS4h2V93VChFODzwUWjDorR+Kn/6g3EXVl7tWISTggKtxQw6wOr+frV -zjnlhVB0Zm/qGp+9UogY0umlOhTv7VWSfc/RR9h5pQZ5K2NmyULvJJM82p0W8ipIkDhWPwNoK6s1 -9fAD7BiuP65GNTNMCZCkOD3r1vSSz8hQtT2YUVQ2bxJ7s+nmxgPlc4PCmy5ReKcUwVErYBw5D+Wj -YaRqj1Dpy6kf3pOLBDPnUA7nZT+dsvMm0SnKa+80FWUDWlQ8OOF+eSr3vNZifhZZSYBI6nG/n7pJ -oRyLLYfImRQRQTIBbIQ35bfFNoYcDCatDeXH -`protect end_protected -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity GaussFir_1mp5_fir_compiler_v7_2_12 is - port ( - aresetn : in STD_LOGIC; - aclk : in STD_LOGIC; - aclken : in STD_LOGIC; - s_axis_data_tvalid : in STD_LOGIC; - s_axis_data_tready : out STD_LOGIC; - s_axis_data_tlast : in STD_LOGIC; - s_axis_data_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axis_config_tvalid : in STD_LOGIC; - s_axis_config_tready : out STD_LOGIC; - s_axis_config_tlast : in STD_LOGIC; - s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axis_reload_tvalid : in STD_LOGIC; - s_axis_reload_tready : out STD_LOGIC; - s_axis_reload_tlast : in STD_LOGIC; - s_axis_reload_tdata : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_data_tvalid : out STD_LOGIC; - m_axis_data_tready : in STD_LOGIC; - m_axis_data_tlast : out STD_LOGIC; - m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); - event_s_data_tlast_missing : out STD_LOGIC; - event_s_data_tlast_unexpected : out STD_LOGIC; - event_s_data_chanid_incorrect : out STD_LOGIC; - event_s_config_tlast_missing : out STD_LOGIC; - event_s_config_tlast_unexpected : out STD_LOGIC; - event_s_reload_tlast_missing : out STD_LOGIC; - event_s_reload_tlast_unexpected : out STD_LOGIC - ); - attribute C_ACCUM_OP_PATH_WIDTHS : string; - attribute C_ACCUM_OP_PATH_WIDTHS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "13"; - attribute C_ACCUM_PATH_WIDTHS : string; - attribute C_ACCUM_PATH_WIDTHS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "13"; - attribute C_CHANNEL_PATTERN : string; - attribute C_CHANNEL_PATTERN of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "fixed"; - attribute C_COEF_FILE : string; - attribute C_COEF_FILE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "GaussFir_1mp5.mif"; - attribute C_COEF_FILE_LINES : integer; - attribute C_COEF_FILE_LINES of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 160; - attribute C_COEF_MEMTYPE : integer; - attribute C_COEF_MEMTYPE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 2; - attribute C_COEF_MEM_PACKING : integer; - attribute C_COEF_MEM_PACKING of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_COEF_PATH_SIGN : string; - attribute C_COEF_PATH_SIGN of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "1"; - attribute C_COEF_PATH_SRC : string; - attribute C_COEF_PATH_SRC of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "0"; - attribute C_COEF_PATH_WIDTHS : string; - attribute C_COEF_PATH_WIDTHS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "14"; - attribute C_COEF_RELOAD : integer; - attribute C_COEF_RELOAD of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_COEF_WIDTH : integer; - attribute C_COEF_WIDTH of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 14; - attribute C_COL_CONFIG : string; - attribute C_COL_CONFIG of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "5"; - attribute C_COL_MODE : integer; - attribute C_COL_MODE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_COL_PIPE_LEN : integer; - attribute C_COL_PIPE_LEN of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 4; - attribute C_COMPONENT_NAME : string; - attribute C_COMPONENT_NAME of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "GaussFir_1mp5"; - attribute C_CONFIG_PACKET_SIZE : integer; - attribute C_CONFIG_PACKET_SIZE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_CONFIG_SYNC_MODE : integer; - attribute C_CONFIG_SYNC_MODE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_CONFIG_TDATA_WIDTH : integer; - attribute C_CONFIG_TDATA_WIDTH of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_DATAPATH_MEMTYPE : integer; - attribute C_DATAPATH_MEMTYPE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_DATA_HAS_TLAST : integer; - attribute C_DATA_HAS_TLAST of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_DATA_IP_PATH_WIDTHS : string; - attribute C_DATA_IP_PATH_WIDTHS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "2"; - attribute C_DATA_MEMTYPE : integer; - attribute C_DATA_MEMTYPE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_DATA_MEM_PACKING : integer; - attribute C_DATA_MEM_PACKING of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_DATA_PATH_PSAMP_SRC : string; - attribute C_DATA_PATH_PSAMP_SRC of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "0"; - attribute C_DATA_PATH_SIGN : string; - attribute C_DATA_PATH_SIGN of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "0"; - attribute C_DATA_PATH_SRC : string; - attribute C_DATA_PATH_SRC of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "0"; - attribute C_DATA_PATH_WIDTHS : string; - attribute C_DATA_PATH_WIDTHS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "2"; - attribute C_DATA_PX_PATH_WIDTHS : string; - attribute C_DATA_PX_PATH_WIDTHS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "2"; - attribute C_DATA_WIDTH : integer; - attribute C_DATA_WIDTH of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 2; - attribute C_DECIM_RATE : integer; - attribute C_DECIM_RATE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_ELABORATION_DIR : string; - attribute C_ELABORATION_DIR of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "./"; - attribute C_EXT_MULT_CNFG : string; - attribute C_EXT_MULT_CNFG of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "none"; - attribute C_FILTER_TYPE : integer; - attribute C_FILTER_TYPE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 2; - attribute C_FILTS_PACKED : integer; - attribute C_FILTS_PACKED of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_HAS_ACLKEN : integer; - attribute C_HAS_ACLKEN of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_HAS_ARESETn : integer; - attribute C_HAS_ARESETn of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_HAS_CONFIG_CHANNEL : integer; - attribute C_HAS_CONFIG_CHANNEL of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_INPUT_RATE : integer; - attribute C_INPUT_RATE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 32; - attribute C_INTERP_RATE : integer; - attribute C_INTERP_RATE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 32; - attribute C_IPBUFF_MEMTYPE : integer; - attribute C_IPBUFF_MEMTYPE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_LATENCY : integer; - attribute C_LATENCY of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 11; - attribute C_MEM_ARRANGEMENT : integer; - attribute C_MEM_ARRANGEMENT of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 2; - attribute C_M_DATA_HAS_TREADY : integer; - attribute C_M_DATA_HAS_TREADY of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_M_DATA_HAS_TUSER : integer; - attribute C_M_DATA_HAS_TUSER of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_M_DATA_TDATA_WIDTH : integer; - attribute C_M_DATA_TDATA_WIDTH of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 16; - attribute C_M_DATA_TUSER_WIDTH : integer; - attribute C_M_DATA_TUSER_WIDTH of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_NUM_CHANNELS : integer; - attribute C_NUM_CHANNELS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_NUM_FILTS : integer; - attribute C_NUM_FILTS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_NUM_MADDS : integer; - attribute C_NUM_MADDS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 5; - attribute C_NUM_RELOAD_SLOTS : integer; - attribute C_NUM_RELOAD_SLOTS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_NUM_TAPS : integer; - attribute C_NUM_TAPS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 129; - attribute C_OPBUFF_MEMTYPE : integer; - attribute C_OPBUFF_MEMTYPE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_OPTIMIZATION : integer; - attribute C_OPTIMIZATION of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_OPT_MADDS : string; - attribute C_OPT_MADDS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "none"; - attribute C_OP_PATH_PSAMP_SRC : string; - attribute C_OP_PATH_PSAMP_SRC of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "0"; - attribute C_OUTPUT_PATH_WIDTHS : string; - attribute C_OUTPUT_PATH_WIDTHS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "13"; - attribute C_OUTPUT_RATE : integer; - attribute C_OUTPUT_RATE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_OUTPUT_WIDTH : integer; - attribute C_OUTPUT_WIDTH of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 13; - attribute C_OVERSAMPLING_RATE : integer; - attribute C_OVERSAMPLING_RATE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_PX_PATH_SRC : string; - attribute C_PX_PATH_SRC of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "0"; - attribute C_RELOAD_TDATA_WIDTH : integer; - attribute C_RELOAD_TDATA_WIDTH of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_ROUND_MODE : integer; - attribute C_ROUND_MODE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_SYMMETRY : integer; - attribute C_SYMMETRY of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_S_DATA_HAS_FIFO : integer; - attribute C_S_DATA_HAS_FIFO of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_S_DATA_HAS_TUSER : integer; - attribute C_S_DATA_HAS_TUSER of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_S_DATA_TDATA_WIDTH : integer; - attribute C_S_DATA_TDATA_WIDTH of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 8; - attribute C_S_DATA_TUSER_WIDTH : integer; - attribute C_S_DATA_TUSER_WIDTH of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "kintex7"; - attribute C_ZERO_PACKING_FACTOR : integer; - attribute C_ZERO_PACKING_FACTOR of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "fir_compiler_v7_2_12"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "yes"; -end GaussFir_1mp5_fir_compiler_v7_2_12; - -architecture STRUCTURE of GaussFir_1mp5_fir_compiler_v7_2_12 is - signal \\ : STD_LOGIC; - signal \^m_axis_data_tdata\ : STD_LOGIC_VECTOR ( 12 downto 0 ); - signal NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_data_chanid_incorrect_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_data_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_data_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_reload_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_reload_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_m_axis_data_tlast_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_s_axis_config_tready_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_s_axis_reload_tready_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_m_axis_data_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 12 ); - signal NLW_i_synth_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - attribute C_ACCUM_OP_PATH_WIDTHS of i_synth : label is "13"; - attribute C_ACCUM_PATH_WIDTHS of i_synth : label is "13"; - attribute C_CHANNEL_PATTERN of i_synth : label is "fixed"; - attribute C_COEF_FILE of i_synth : label is "GaussFir_1mp5.mif"; - attribute C_COEF_FILE_LINES of i_synth : label is 160; - attribute C_COEF_MEMTYPE of i_synth : label is 2; - attribute C_COEF_MEM_PACKING of i_synth : label is 0; - attribute C_COEF_PATH_SIGN of i_synth : label is "1"; - attribute C_COEF_PATH_SRC of i_synth : label is "0"; - attribute C_COEF_PATH_WIDTHS of i_synth : label is "14"; - attribute C_COEF_RELOAD of i_synth : label is 0; - attribute C_COEF_WIDTH of i_synth : label is 14; - attribute C_COL_CONFIG of i_synth : label is "5"; - attribute C_COL_MODE of i_synth : label is 1; - attribute C_COL_PIPE_LEN of i_synth : label is 4; - attribute C_COMPONENT_NAME of i_synth : label is "GaussFir_1mp5"; - attribute C_CONFIG_PACKET_SIZE of i_synth : label is 0; - attribute C_CONFIG_SYNC_MODE of i_synth : label is 0; - attribute C_CONFIG_TDATA_WIDTH of i_synth : label is 1; - attribute C_DATAPATH_MEMTYPE of i_synth : label is 0; - attribute C_DATA_HAS_TLAST of i_synth : label is 0; - attribute C_DATA_IP_PATH_WIDTHS of i_synth : label is "2"; - attribute C_DATA_MEMTYPE of i_synth : label is 0; - attribute C_DATA_MEM_PACKING of i_synth : label is 0; - attribute C_DATA_PATH_PSAMP_SRC of i_synth : label is "0"; - attribute C_DATA_PATH_SIGN of i_synth : label is "0"; - attribute C_DATA_PATH_SRC of i_synth : label is "0"; - attribute C_DATA_PATH_WIDTHS of i_synth : label is "2"; - attribute C_DATA_PX_PATH_WIDTHS of i_synth : label is "2"; - attribute C_DATA_WIDTH of i_synth : label is 2; - attribute C_DECIM_RATE of i_synth : label is 1; - attribute C_ELABORATION_DIR of i_synth : label is "./"; - attribute C_EXT_MULT_CNFG of i_synth : label is "none"; - attribute C_FILTER_TYPE of i_synth : label is 2; - attribute C_FILTS_PACKED of i_synth : label is 0; - attribute C_HAS_ACLKEN of i_synth : label is 0; - attribute C_HAS_ARESETn of i_synth : label is 0; - attribute C_HAS_CONFIG_CHANNEL of i_synth : label is 0; - attribute C_INPUT_RATE of i_synth : label is 32; - attribute C_INTERP_RATE of i_synth : label is 32; - attribute C_IPBUFF_MEMTYPE of i_synth : label is 0; - attribute C_LATENCY of i_synth : label is 11; - attribute C_MEM_ARRANGEMENT of i_synth : label is 2; - attribute C_M_DATA_HAS_TREADY of i_synth : label is 0; - attribute C_M_DATA_HAS_TUSER of i_synth : label is 0; - attribute C_M_DATA_TDATA_WIDTH of i_synth : label is 16; - attribute C_M_DATA_TUSER_WIDTH of i_synth : label is 1; - attribute C_NUM_CHANNELS of i_synth : label is 1; - attribute C_NUM_FILTS of i_synth : label is 1; - attribute C_NUM_MADDS of i_synth : label is 5; - attribute C_NUM_RELOAD_SLOTS of i_synth : label is 1; - attribute C_NUM_TAPS of i_synth : label is 129; - attribute C_OPBUFF_MEMTYPE of i_synth : label is 0; - attribute C_OPTIMIZATION of i_synth : label is 0; - attribute C_OPT_MADDS of i_synth : label is "none"; - attribute C_OP_PATH_PSAMP_SRC of i_synth : label is "0"; - attribute C_OUTPUT_PATH_WIDTHS of i_synth : label is "13"; - attribute C_OUTPUT_RATE of i_synth : label is 1; - attribute C_OUTPUT_WIDTH of i_synth : label is 13; - attribute C_OVERSAMPLING_RATE of i_synth : label is 1; - attribute C_PX_PATH_SRC of i_synth : label is "0"; - attribute C_RELOAD_TDATA_WIDTH of i_synth : label is 1; - attribute C_ROUND_MODE of i_synth : label is 0; - attribute C_SYMMETRY of i_synth : label is 0; - attribute C_S_DATA_HAS_FIFO of i_synth : label is 0; - attribute C_S_DATA_HAS_TUSER of i_synth : label is 0; - attribute C_S_DATA_TDATA_WIDTH of i_synth : label is 8; - attribute C_S_DATA_TUSER_WIDTH of i_synth : label is 1; - attribute C_XDEVICEFAMILY of i_synth : label is "kintex7"; - attribute C_ZERO_PACKING_FACTOR of i_synth : label is 1; - attribute downgradeipidentifiedwarnings of i_synth : label is "yes"; -begin - event_s_config_tlast_missing <= \\; - event_s_config_tlast_unexpected <= \\; - event_s_data_chanid_incorrect <= \\; - event_s_data_tlast_missing <= \\; - event_s_data_tlast_unexpected <= \\; - event_s_reload_tlast_missing <= \\; - event_s_reload_tlast_unexpected <= \\; - m_axis_data_tdata(15) <= \^m_axis_data_tdata\(12); - m_axis_data_tdata(14) <= \^m_axis_data_tdata\(12); - m_axis_data_tdata(13) <= \^m_axis_data_tdata\(12); - m_axis_data_tdata(12 downto 0) <= \^m_axis_data_tdata\(12 downto 0); - m_axis_data_tlast <= \\; - m_axis_data_tuser(0) <= \\; - s_axis_config_tready <= \\; - s_axis_reload_tready <= \\; -GND: unisim.vcomponents.GND - port map ( - G => \\ - ); -i_synth: entity work.GaussFir_1mp5_fir_compiler_v7_2_12_viv - port map ( - aclk => aclk, - aclken => '0', - aresetn => '0', - event_s_config_tlast_missing => NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED, - event_s_config_tlast_unexpected => NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED, - event_s_data_chanid_incorrect => NLW_i_synth_event_s_data_chanid_incorrect_UNCONNECTED, - event_s_data_tlast_missing => NLW_i_synth_event_s_data_tlast_missing_UNCONNECTED, - event_s_data_tlast_unexpected => NLW_i_synth_event_s_data_tlast_unexpected_UNCONNECTED, - event_s_reload_tlast_missing => NLW_i_synth_event_s_reload_tlast_missing_UNCONNECTED, - event_s_reload_tlast_unexpected => NLW_i_synth_event_s_reload_tlast_unexpected_UNCONNECTED, - m_axis_data_tdata(15) => \^m_axis_data_tdata\(12), - m_axis_data_tdata(14 downto 12) => NLW_i_synth_m_axis_data_tdata_UNCONNECTED(14 downto 12), - m_axis_data_tdata(11 downto 0) => \^m_axis_data_tdata\(11 downto 0), - m_axis_data_tlast => NLW_i_synth_m_axis_data_tlast_UNCONNECTED, - m_axis_data_tready => '0', - m_axis_data_tuser(0) => NLW_i_synth_m_axis_data_tuser_UNCONNECTED(0), - m_axis_data_tvalid => m_axis_data_tvalid, - s_axis_config_tdata(0) => '0', - s_axis_config_tlast => '0', - s_axis_config_tready => NLW_i_synth_s_axis_config_tready_UNCONNECTED, - s_axis_config_tvalid => '0', - s_axis_data_tdata(7 downto 2) => B"000000", - s_axis_data_tdata(1 downto 0) => s_axis_data_tdata(1 downto 0), - s_axis_data_tlast => '0', - s_axis_data_tready => s_axis_data_tready, - s_axis_data_tuser(0) => '0', - s_axis_data_tvalid => s_axis_data_tvalid, - s_axis_reload_tdata(0) => '0', - s_axis_reload_tlast => '0', - s_axis_reload_tready => NLW_i_synth_s_axis_reload_tready_UNCONNECTED, - s_axis_reload_tvalid => '0' - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity GaussFir_1mp5 is - port ( - aclk : in STD_LOGIC; - s_axis_data_tvalid : in STD_LOGIC; - s_axis_data_tready : out STD_LOGIC; - s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); - m_axis_data_tvalid : out STD_LOGIC; - m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ) - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of GaussFir_1mp5 : entity is true; - attribute CHECK_LICENSE_TYPE : string; - attribute CHECK_LICENSE_TYPE of GaussFir_1mp5 : entity is "GaussFir_1mp5,fir_compiler_v7_2_12,{}"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of GaussFir_1mp5 : entity is "yes"; - attribute x_core_info : string; - attribute x_core_info of GaussFir_1mp5 : entity is "fir_compiler_v7_2_12,Vivado 2019.1.3"; -end GaussFir_1mp5; - -architecture STRUCTURE of GaussFir_1mp5 is - signal NLW_U0_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_data_chanid_incorrect_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_data_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_data_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_reload_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_reload_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_U0_m_axis_data_tlast_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axis_config_tready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axis_reload_tready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - attribute C_ACCUM_OP_PATH_WIDTHS : string; - attribute C_ACCUM_OP_PATH_WIDTHS of U0 : label is "13"; - attribute C_ACCUM_PATH_WIDTHS : string; - attribute C_ACCUM_PATH_WIDTHS of U0 : label is "13"; - attribute C_CHANNEL_PATTERN : string; - attribute C_CHANNEL_PATTERN of U0 : label is "fixed"; - attribute C_COEF_FILE : string; - attribute C_COEF_FILE of U0 : label is "GaussFir_1mp5.mif"; - attribute C_COEF_FILE_LINES : integer; - attribute C_COEF_FILE_LINES of U0 : label is 160; - attribute C_COEF_MEMTYPE : integer; - attribute C_COEF_MEMTYPE of U0 : label is 2; - attribute C_COEF_MEM_PACKING : integer; - attribute C_COEF_MEM_PACKING of U0 : label is 0; - attribute C_COEF_PATH_SIGN : string; - attribute C_COEF_PATH_SIGN of U0 : label is "1"; - attribute C_COEF_PATH_SRC : string; - attribute C_COEF_PATH_SRC of U0 : label is "0"; - attribute C_COEF_PATH_WIDTHS : string; - attribute C_COEF_PATH_WIDTHS of U0 : label is "14"; - attribute C_COEF_RELOAD : integer; - attribute C_COEF_RELOAD of U0 : label is 0; - attribute C_COEF_WIDTH : integer; - attribute C_COEF_WIDTH of U0 : label is 14; - attribute C_COL_CONFIG : string; - attribute C_COL_CONFIG of U0 : label is "5"; - attribute C_COL_MODE : integer; - attribute C_COL_MODE of U0 : label is 1; - attribute C_COL_PIPE_LEN : integer; - attribute C_COL_PIPE_LEN of U0 : label is 4; - attribute C_COMPONENT_NAME : string; - attribute C_COMPONENT_NAME of U0 : label is "GaussFir_1mp5"; - attribute C_CONFIG_PACKET_SIZE : integer; - attribute C_CONFIG_PACKET_SIZE of U0 : label is 0; - attribute C_CONFIG_SYNC_MODE : integer; - attribute C_CONFIG_SYNC_MODE of U0 : label is 0; - attribute C_CONFIG_TDATA_WIDTH : integer; - attribute C_CONFIG_TDATA_WIDTH of U0 : label is 1; - attribute C_DATAPATH_MEMTYPE : integer; - attribute C_DATAPATH_MEMTYPE of U0 : label is 0; - attribute C_DATA_HAS_TLAST : integer; - attribute C_DATA_HAS_TLAST of U0 : label is 0; - attribute C_DATA_IP_PATH_WIDTHS : string; - attribute C_DATA_IP_PATH_WIDTHS of U0 : label is "2"; - attribute C_DATA_MEMTYPE : integer; - attribute C_DATA_MEMTYPE of U0 : label is 0; - attribute C_DATA_MEM_PACKING : integer; - attribute C_DATA_MEM_PACKING of U0 : label is 0; - attribute C_DATA_PATH_PSAMP_SRC : string; - attribute C_DATA_PATH_PSAMP_SRC of U0 : label is "0"; - attribute C_DATA_PATH_SIGN : string; - attribute C_DATA_PATH_SIGN of U0 : label is "0"; - attribute C_DATA_PATH_SRC : string; - attribute C_DATA_PATH_SRC of U0 : label is "0"; - attribute C_DATA_PATH_WIDTHS : string; - attribute C_DATA_PATH_WIDTHS of U0 : label is "2"; - attribute C_DATA_PX_PATH_WIDTHS : string; - attribute C_DATA_PX_PATH_WIDTHS of U0 : label is "2"; - attribute C_DATA_WIDTH : integer; - attribute C_DATA_WIDTH of U0 : label is 2; - attribute C_DECIM_RATE : integer; - attribute C_DECIM_RATE of U0 : label is 1; - attribute C_ELABORATION_DIR : string; - attribute C_ELABORATION_DIR of U0 : label is "./"; - attribute C_EXT_MULT_CNFG : string; - attribute C_EXT_MULT_CNFG of U0 : label is "none"; - attribute C_FILTER_TYPE : integer; - attribute C_FILTER_TYPE of U0 : label is 2; - attribute C_FILTS_PACKED : integer; - attribute C_FILTS_PACKED of U0 : label is 0; - attribute C_HAS_ACLKEN : integer; - attribute C_HAS_ACLKEN of U0 : label is 0; - attribute C_HAS_ARESETn : integer; - attribute C_HAS_ARESETn of U0 : label is 0; - attribute C_HAS_CONFIG_CHANNEL : integer; - attribute C_HAS_CONFIG_CHANNEL of U0 : label is 0; - attribute C_INPUT_RATE : integer; - attribute C_INPUT_RATE of U0 : label is 32; - attribute C_INTERP_RATE : integer; - attribute C_INTERP_RATE of U0 : label is 32; - attribute C_IPBUFF_MEMTYPE : integer; - attribute C_IPBUFF_MEMTYPE of U0 : label is 0; - attribute C_LATENCY : integer; - attribute C_LATENCY of U0 : label is 11; - attribute C_MEM_ARRANGEMENT : integer; - attribute C_MEM_ARRANGEMENT of U0 : label is 2; - attribute C_M_DATA_HAS_TREADY : integer; - attribute C_M_DATA_HAS_TREADY of U0 : label is 0; - attribute C_M_DATA_HAS_TUSER : integer; - attribute C_M_DATA_HAS_TUSER of U0 : label is 0; - attribute C_M_DATA_TDATA_WIDTH : integer; - attribute C_M_DATA_TDATA_WIDTH of U0 : label is 16; - attribute C_M_DATA_TUSER_WIDTH : integer; - attribute C_M_DATA_TUSER_WIDTH of U0 : label is 1; - attribute C_NUM_CHANNELS : integer; - attribute C_NUM_CHANNELS of U0 : label is 1; - attribute C_NUM_FILTS : integer; - attribute C_NUM_FILTS of U0 : label is 1; - attribute C_NUM_MADDS : integer; - attribute C_NUM_MADDS of U0 : label is 5; - attribute C_NUM_RELOAD_SLOTS : integer; - attribute C_NUM_RELOAD_SLOTS of U0 : label is 1; - attribute C_NUM_TAPS : integer; - attribute C_NUM_TAPS of U0 : label is 129; - attribute C_OPBUFF_MEMTYPE : integer; - attribute C_OPBUFF_MEMTYPE of U0 : label is 0; - attribute C_OPTIMIZATION : integer; - attribute C_OPTIMIZATION of U0 : label is 0; - attribute C_OPT_MADDS : string; - attribute C_OPT_MADDS of U0 : label is "none"; - attribute C_OP_PATH_PSAMP_SRC : string; - attribute C_OP_PATH_PSAMP_SRC of U0 : label is "0"; - attribute C_OUTPUT_PATH_WIDTHS : string; - attribute C_OUTPUT_PATH_WIDTHS of U0 : label is "13"; - attribute C_OUTPUT_RATE : integer; - attribute C_OUTPUT_RATE of U0 : label is 1; - attribute C_OUTPUT_WIDTH : integer; - attribute C_OUTPUT_WIDTH of U0 : label is 13; - attribute C_OVERSAMPLING_RATE : integer; - attribute C_OVERSAMPLING_RATE of U0 : label is 1; - attribute C_PX_PATH_SRC : string; - attribute C_PX_PATH_SRC of U0 : label is "0"; - attribute C_RELOAD_TDATA_WIDTH : integer; - attribute C_RELOAD_TDATA_WIDTH of U0 : label is 1; - attribute C_ROUND_MODE : integer; - attribute C_ROUND_MODE of U0 : label is 0; - attribute C_SYMMETRY : integer; - attribute C_SYMMETRY of U0 : label is 0; - attribute C_S_DATA_HAS_FIFO : integer; - attribute C_S_DATA_HAS_FIFO of U0 : label is 0; - attribute C_S_DATA_HAS_TUSER : integer; - attribute C_S_DATA_HAS_TUSER of U0 : label is 0; - attribute C_S_DATA_TDATA_WIDTH : integer; - attribute C_S_DATA_TDATA_WIDTH of U0 : label is 8; - attribute C_S_DATA_TUSER_WIDTH : integer; - attribute C_S_DATA_TUSER_WIDTH of U0 : label is 1; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of U0 : label is "kintex7"; - attribute C_ZERO_PACKING_FACTOR : integer; - attribute C_ZERO_PACKING_FACTOR of U0 : label is 1; - attribute downgradeipidentifiedwarnings of U0 : label is "yes"; - attribute x_interface_info : string; - attribute x_interface_info of aclk : signal is "xilinx.com:signal:clock:1.0 aclk_intf CLK"; - attribute x_interface_parameter : string; - attribute x_interface_parameter of aclk : signal is "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0"; - attribute x_interface_info of m_axis_data_tvalid : signal is "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID"; - attribute x_interface_parameter of m_axis_data_tvalid : signal is "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; - attribute x_interface_info of s_axis_data_tready : signal is "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY"; - attribute x_interface_info of s_axis_data_tvalid : signal is "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID"; - attribute x_interface_parameter of s_axis_data_tvalid : signal is "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; - attribute x_interface_info of m_axis_data_tdata : signal is "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA"; - attribute x_interface_info of s_axis_data_tdata : signal is "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA"; -begin -U0: entity work.GaussFir_1mp5_fir_compiler_v7_2_12 - port map ( - aclk => aclk, - aclken => '1', - aresetn => '1', - event_s_config_tlast_missing => NLW_U0_event_s_config_tlast_missing_UNCONNECTED, - event_s_config_tlast_unexpected => NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED, - event_s_data_chanid_incorrect => NLW_U0_event_s_data_chanid_incorrect_UNCONNECTED, - event_s_data_tlast_missing => NLW_U0_event_s_data_tlast_missing_UNCONNECTED, - event_s_data_tlast_unexpected => NLW_U0_event_s_data_tlast_unexpected_UNCONNECTED, - event_s_reload_tlast_missing => NLW_U0_event_s_reload_tlast_missing_UNCONNECTED, - event_s_reload_tlast_unexpected => NLW_U0_event_s_reload_tlast_unexpected_UNCONNECTED, - m_axis_data_tdata(15 downto 0) => m_axis_data_tdata(15 downto 0), - m_axis_data_tlast => NLW_U0_m_axis_data_tlast_UNCONNECTED, - m_axis_data_tready => '1', - m_axis_data_tuser(0) => NLW_U0_m_axis_data_tuser_UNCONNECTED(0), - m_axis_data_tvalid => m_axis_data_tvalid, - s_axis_config_tdata(0) => '0', - s_axis_config_tlast => '0', - s_axis_config_tready => NLW_U0_s_axis_config_tready_UNCONNECTED, - s_axis_config_tvalid => '0', - s_axis_data_tdata(7 downto 0) => s_axis_data_tdata(7 downto 0), - s_axis_data_tlast => '0', - s_axis_data_tready => s_axis_data_tready, - s_axis_data_tuser(0) => '0', - s_axis_data_tvalid => s_axis_data_tvalid, - s_axis_reload_tdata(0) => '0', - s_axis_reload_tlast => '0', - s_axis_reload_tready => NLW_U0_s_axis_reload_tready_UNCONNECTED, - s_axis_reload_tvalid => '0' - ); -end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/GaussFir_1mp5_stub.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/GaussFir_1mp5_stub.v deleted file mode 100644 index aea6fdf9..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/GaussFir_1mp5_stub.v +++ /dev/null @@ -1,26 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:33:47 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.v -// Design : GaussFir_1mp5 -// Purpose : Stub declaration of top-level module interface -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *) -module GaussFir_1mp5(aclk, s_axis_data_tvalid, s_axis_data_tready, - s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata) -/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */; - input aclk; - input s_axis_data_tvalid; - output s_axis_data_tready; - input [7:0]s_axis_data_tdata; - output m_axis_data_tvalid; - output [15:0]m_axis_data_tdata; -endmodule diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/GaussFir_1mp5_stub.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/GaussFir_1mp5_stub.vhdl deleted file mode 100644 index 0b7b836d..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/GaussFir_1mp5_stub.vhdl +++ /dev/null @@ -1,35 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:33:47 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.vhdl --- Design : GaussFir_1mp5 --- Purpose : Stub declaration of top-level module interface --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity GaussFir_1mp5 is - Port ( - aclk : in STD_LOGIC; - s_axis_data_tvalid : in STD_LOGIC; - s_axis_data_tready : out STD_LOGIC; - s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); - m_axis_data_tvalid : out STD_LOGIC; - m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ) - ); - -end GaussFir_1mp5; - -architecture stub of GaussFir_1mp5 is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]"; -attribute x_core_info : string; -attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3"; -begin -end; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/demo_tb/tb_GaussFir_1mp5.vhd b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/demo_tb/tb_GaussFir_1mp5.vhd deleted file mode 100644 index c1431eb2..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/demo_tb/tb_GaussFir_1mp5.vhd +++ /dev/null @@ -1,261 +0,0 @@ --------------------------------------------------------------------------------- --- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --------------------------------------------------------------------------------- --- Description: --- This is an example testbench for the FIR Compiler IP core. --- The testbench has been generated by Vivado to accompany the IP core --- instance you have generated. --- --- This testbench is for demonstration purposes only. See note below for --- instructions on how to use it with your core. --- --- See the FIR Compiler product guide for further information --- about this core. --- --------------------------------------------------------------------------------- --- Using this testbench --- --- This testbench instantiates your generated FIR Compiler core --- instance named "GaussFir_1mp5". --- --- Use Vivado's Run Simulation flow to run this testbench. See the Vivado --- documentation for details. --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity tb_GaussFir_1mp5 is -end tb_GaussFir_1mp5; - -architecture tb of tb_GaussFir_1mp5 is - - ----------------------------------------------------------------------- - -- Timing constants - ----------------------------------------------------------------------- - constant CLOCK_PERIOD : time := 100 ns; - constant T_HOLD : time := 10 ns; - constant T_STROBE : time := CLOCK_PERIOD - (1 ns); - - ----------------------------------------------------------------------- - -- DUT signals - ----------------------------------------------------------------------- - - -- General signals - signal aclk : std_logic := '0'; -- the master clock - - -- Data slave channel signals - signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid - signal s_axis_data_tready : std_logic := '1'; -- slave is ready - signal s_axis_data_tdata : std_logic_vector(7 downto 0) := (others => '0'); -- data payload - - -- Data master channel signals - signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid - signal m_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload - - ----------------------------------------------------------------------- - -- Aliases for AXI channel TDATA and TUSER fields - -- These are a convenience for viewing data in a simulator waveform viewer. - -- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command - -- to prevent the simulator optimizing away these signals. - ----------------------------------------------------------------------- - - -- Data slave channel alias signals - signal s_axis_data_tdata_data : std_logic_vector(1 downto 0) := (others => '0'); - - -- Data master channel alias signals - signal m_axis_data_tdata_data : std_logic_vector(12 downto 0) := (others => '0'); - - -begin - - ----------------------------------------------------------------------- - -- Instantiate the DUT - ----------------------------------------------------------------------- - - dut : entity work.GaussFir_1mp5 - port map ( - aclk => aclk, - s_axis_data_tvalid => s_axis_data_tvalid, - s_axis_data_tready => s_axis_data_tready, - s_axis_data_tdata => s_axis_data_tdata, - m_axis_data_tvalid => m_axis_data_tvalid, - m_axis_data_tdata => m_axis_data_tdata - ); - - ----------------------------------------------------------------------- - -- Generate clock - ----------------------------------------------------------------------- - - clock_gen : process - begin - aclk <= '0'; - wait for CLOCK_PERIOD; - loop - aclk <= '0'; - wait for CLOCK_PERIOD/2; - aclk <= '1'; - wait for CLOCK_PERIOD/2; - end loop; - end process clock_gen; - - ----------------------------------------------------------------------- - -- Generate inputs - ----------------------------------------------------------------------- - - stimuli : process - - -- Procedure to drive a number of input samples with specific data - -- data is the data value to drive on the tdata signal - -- samples is the number of zero-data input samples to drive - procedure drive_data ( data : std_logic_vector(7 downto 0); - samples : natural := 1 ) is - variable ip_count : integer := 0; - begin - ip_count := 0; - loop - s_axis_data_tvalid <= '1'; - s_axis_data_tdata <= data; - loop - wait until rising_edge(aclk); - exit when s_axis_data_tready = '1'; - end loop; - ip_count := ip_count + 1; - wait for T_HOLD; - -- Input rate is 1 input each 32 clock cycles: drive valid inputs at this rate - s_axis_data_tvalid <= '0'; - wait for CLOCK_PERIOD * 31; - exit when ip_count >= samples; - end loop; - end procedure drive_data; - - -- Procedure to drive a number of zero-data input samples - -- samples is the number of zero-data input samples to drive - procedure drive_zeros ( samples : natural := 1 ) is - begin - drive_data((others => '0'), samples); - end procedure drive_zeros; - - -- Procedure to drive an impulse and let the impulse response emerge on the data master channel - -- samples is the number of input samples to drive; default is enough for impulse response output to emerge - procedure drive_impulse ( samples : natural := 165 ) is - variable impulse : std_logic_vector(7 downto 0); - begin - impulse := (others => '0'); -- initialize unused bits to zero - impulse(1 downto 0) := "01"; - drive_data(impulse); - if samples > 1 then - drive_zeros(samples-1); - end if; - end procedure drive_impulse; - - begin - - -- Drive inputs T_HOLD time after rising edge of clock - wait until rising_edge(aclk); - wait for T_HOLD; - - -- Drive a single impulse and let the impulse response emerge - drive_impulse; - - -- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals - drive_impulse(2); -- start of impulse; data is now zero - s_axis_data_tvalid <= '0'; - wait for CLOCK_PERIOD * 160; -- provide no data for 5 input samples worth - drive_zeros(2); -- 2 normal input samples - s_axis_data_tvalid <= '1'; - wait for CLOCK_PERIOD * 160; -- provide data as fast as the core can accept it for 5 input samples worth - drive_zeros(156); -- back to normal operation - - -- End of test - report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure; - wait; - - end process stimuli; - - ----------------------------------------------------------------------- - -- Check outputs - ----------------------------------------------------------------------- - - check_outputs : process - variable check_ok : boolean := true; - begin - - -- Check outputs T_STROBE time after rising edge of clock - wait until rising_edge(aclk); - wait for T_STROBE; - - -- Do not check the output payload values, as this requires the behavioral model - -- which would make this demonstration testbench unwieldy. - -- Instead, check the protocol of the master DATA channel: - -- check that the payload is valid (not X) when TVALID is high - - if m_axis_data_tvalid = '1' then - if is_x(m_axis_data_tdata) then - report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error; - check_ok := false; - end if; - - end if; - - assert check_ok - report "ERROR: terminating test with failures." severity failure; - - end process check_outputs; - - ----------------------------------------------------------------------- - -- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing - ----------------------------------------------------------------------- - - -- Data slave channel alias signals - s_axis_data_tdata_data <= s_axis_data_tdata(1 downto 0); - - -- Data master channel alias signals: update these only when they are valid - m_axis_data_tdata_data <= m_axis_data_tdata(12 downto 0) when m_axis_data_tvalid = '1'; - -end tb; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/sim/GaussFir_1mp5.vhd b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/sim/GaussFir_1mp5.vhd deleted file mode 100644 index fe30ab36..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/sim/GaussFir_1mp5.vhd +++ /dev/null @@ -1,281 +0,0 @@ --- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:fir_compiler:7.2 --- IP Revision: 12 - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -LIBRARY fir_compiler_v7_2_12; -USE fir_compiler_v7_2_12.fir_compiler_v7_2_12; - -ENTITY GaussFir_1mp5 IS - PORT ( - aclk : IN STD_LOGIC; - s_axis_data_tvalid : IN STD_LOGIC; - s_axis_data_tready : OUT STD_LOGIC; - s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - m_axis_data_tvalid : OUT STD_LOGIC; - m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) - ); -END GaussFir_1mp5; - -ARCHITECTURE GaussFir_1mp5_arch OF GaussFir_1mp5 IS - ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; - ATTRIBUTE DowngradeIPIdentifiedWarnings OF GaussFir_1mp5_arch: ARCHITECTURE IS "yes"; - COMPONENT fir_compiler_v7_2_12 IS - GENERIC ( - C_XDEVICEFAMILY : STRING; - C_ELABORATION_DIR : STRING; - C_COMPONENT_NAME : STRING; - C_COEF_FILE : STRING; - C_COEF_FILE_LINES : INTEGER; - C_FILTER_TYPE : INTEGER; - C_INTERP_RATE : INTEGER; - C_DECIM_RATE : INTEGER; - C_ZERO_PACKING_FACTOR : INTEGER; - C_SYMMETRY : INTEGER; - C_NUM_FILTS : INTEGER; - C_NUM_TAPS : INTEGER; - C_NUM_CHANNELS : INTEGER; - C_CHANNEL_PATTERN : STRING; - C_ROUND_MODE : INTEGER; - C_COEF_RELOAD : INTEGER; - C_NUM_RELOAD_SLOTS : INTEGER; - C_COL_MODE : INTEGER; - C_COL_PIPE_LEN : INTEGER; - C_COL_CONFIG : STRING; - C_OPTIMIZATION : INTEGER; - C_DATA_PATH_WIDTHS : STRING; - C_DATA_IP_PATH_WIDTHS : STRING; - C_DATA_PX_PATH_WIDTHS : STRING; - C_DATA_WIDTH : INTEGER; - C_COEF_PATH_WIDTHS : STRING; - C_COEF_WIDTH : INTEGER; - C_DATA_PATH_SRC : STRING; - C_COEF_PATH_SRC : STRING; - C_PX_PATH_SRC : STRING; - C_DATA_PATH_SIGN : STRING; - C_COEF_PATH_SIGN : STRING; - C_ACCUM_PATH_WIDTHS : STRING; - C_OUTPUT_WIDTH : INTEGER; - C_OUTPUT_PATH_WIDTHS : STRING; - C_ACCUM_OP_PATH_WIDTHS : STRING; - C_EXT_MULT_CNFG : STRING; - C_DATA_PATH_PSAMP_SRC : STRING; - C_OP_PATH_PSAMP_SRC : STRING; - C_NUM_MADDS : INTEGER; - C_OPT_MADDS : STRING; - C_OVERSAMPLING_RATE : INTEGER; - C_INPUT_RATE : INTEGER; - C_OUTPUT_RATE : INTEGER; - C_DATA_MEMTYPE : INTEGER; - C_COEF_MEMTYPE : INTEGER; - C_IPBUFF_MEMTYPE : INTEGER; - C_OPBUFF_MEMTYPE : INTEGER; - C_DATAPATH_MEMTYPE : INTEGER; - C_MEM_ARRANGEMENT : INTEGER; - C_DATA_MEM_PACKING : INTEGER; - C_COEF_MEM_PACKING : INTEGER; - C_FILTS_PACKED : INTEGER; - C_LATENCY : INTEGER; - C_HAS_ARESETn : INTEGER; - C_HAS_ACLKEN : INTEGER; - C_DATA_HAS_TLAST : INTEGER; - C_S_DATA_HAS_FIFO : INTEGER; - C_S_DATA_HAS_TUSER : INTEGER; - C_S_DATA_TDATA_WIDTH : INTEGER; - C_S_DATA_TUSER_WIDTH : INTEGER; - C_M_DATA_HAS_TREADY : INTEGER; - C_M_DATA_HAS_TUSER : INTEGER; - C_M_DATA_TDATA_WIDTH : INTEGER; - C_M_DATA_TUSER_WIDTH : INTEGER; - C_HAS_CONFIG_CHANNEL : INTEGER; - C_CONFIG_SYNC_MODE : INTEGER; - C_CONFIG_PACKET_SIZE : INTEGER; - C_CONFIG_TDATA_WIDTH : INTEGER; - C_RELOAD_TDATA_WIDTH : INTEGER - ); - PORT ( - aresetn : IN STD_LOGIC; - aclk : IN STD_LOGIC; - aclken : IN STD_LOGIC; - s_axis_data_tvalid : IN STD_LOGIC; - s_axis_data_tready : OUT STD_LOGIC; - s_axis_data_tlast : IN STD_LOGIC; - s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - s_axis_config_tvalid : IN STD_LOGIC; - s_axis_config_tready : OUT STD_LOGIC; - s_axis_config_tlast : IN STD_LOGIC; - s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - s_axis_reload_tvalid : IN STD_LOGIC; - s_axis_reload_tready : OUT STD_LOGIC; - s_axis_reload_tlast : IN STD_LOGIC; - s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - m_axis_data_tvalid : OUT STD_LOGIC; - m_axis_data_tready : IN STD_LOGIC; - m_axis_data_tlast : OUT STD_LOGIC; - m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - event_s_data_tlast_missing : OUT STD_LOGIC; - event_s_data_tlast_unexpected : OUT STD_LOGIC; - event_s_data_chanid_incorrect : OUT STD_LOGIC; - event_s_config_tlast_missing : OUT STD_LOGIC; - event_s_config_tlast_unexpected : OUT STD_LOGIC; - event_s_reload_tlast_missing : OUT STD_LOGIC; - event_s_reload_tlast_unexpected : OUT STD_LOGIC - ); - END COMPONENT fir_compiler_v7_2_12; - ATTRIBUTE X_INTERFACE_INFO : STRING; - ATTRIBUTE X_INTERFACE_PARAMETER : STRING; - ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA"; - ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID"; - ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA"; - ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY"; - ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID"; - ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0"; - ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; -BEGIN - U0 : fir_compiler_v7_2_12 - GENERIC MAP ( - C_XDEVICEFAMILY => "kintex7", - C_ELABORATION_DIR => "./", - C_COMPONENT_NAME => "GaussFir_1mp5", - C_COEF_FILE => "GaussFir_1mp5.mif", - C_COEF_FILE_LINES => 160, - C_FILTER_TYPE => 2, - C_INTERP_RATE => 32, - C_DECIM_RATE => 1, - C_ZERO_PACKING_FACTOR => 1, - C_SYMMETRY => 0, - C_NUM_FILTS => 1, - C_NUM_TAPS => 129, - C_NUM_CHANNELS => 1, - C_CHANNEL_PATTERN => "fixed", - C_ROUND_MODE => 0, - C_COEF_RELOAD => 0, - C_NUM_RELOAD_SLOTS => 1, - C_COL_MODE => 1, - C_COL_PIPE_LEN => 4, - C_COL_CONFIG => "5", - C_OPTIMIZATION => 0, - C_DATA_PATH_WIDTHS => "2", - C_DATA_IP_PATH_WIDTHS => "2", - C_DATA_PX_PATH_WIDTHS => "2", - C_DATA_WIDTH => 2, - C_COEF_PATH_WIDTHS => "14", - C_COEF_WIDTH => 14, - C_DATA_PATH_SRC => "0", - C_COEF_PATH_SRC => "0", - C_PX_PATH_SRC => "0", - C_DATA_PATH_SIGN => "0", - C_COEF_PATH_SIGN => "1", - C_ACCUM_PATH_WIDTHS => "13", - C_OUTPUT_WIDTH => 13, - C_OUTPUT_PATH_WIDTHS => "13", - C_ACCUM_OP_PATH_WIDTHS => "13", - C_EXT_MULT_CNFG => "none", - C_DATA_PATH_PSAMP_SRC => "0", - C_OP_PATH_PSAMP_SRC => "0", - C_NUM_MADDS => 5, - C_OPT_MADDS => "none", - C_OVERSAMPLING_RATE => 1, - C_INPUT_RATE => 32, - C_OUTPUT_RATE => 1, - C_DATA_MEMTYPE => 0, - C_COEF_MEMTYPE => 2, - C_IPBUFF_MEMTYPE => 0, - C_OPBUFF_MEMTYPE => 0, - C_DATAPATH_MEMTYPE => 0, - C_MEM_ARRANGEMENT => 2, - C_DATA_MEM_PACKING => 0, - C_COEF_MEM_PACKING => 0, - C_FILTS_PACKED => 0, - C_LATENCY => 11, - C_HAS_ARESETn => 0, - C_HAS_ACLKEN => 0, - C_DATA_HAS_TLAST => 0, - C_S_DATA_HAS_FIFO => 0, - C_S_DATA_HAS_TUSER => 0, - C_S_DATA_TDATA_WIDTH => 8, - C_S_DATA_TUSER_WIDTH => 1, - C_M_DATA_HAS_TREADY => 0, - C_M_DATA_HAS_TUSER => 0, - C_M_DATA_TDATA_WIDTH => 16, - C_M_DATA_TUSER_WIDTH => 1, - C_HAS_CONFIG_CHANNEL => 0, - C_CONFIG_SYNC_MODE => 0, - C_CONFIG_PACKET_SIZE => 0, - C_CONFIG_TDATA_WIDTH => 1, - C_RELOAD_TDATA_WIDTH => 1 - ) - PORT MAP ( - aresetn => '1', - aclk => aclk, - aclken => '1', - s_axis_data_tvalid => s_axis_data_tvalid, - s_axis_data_tready => s_axis_data_tready, - s_axis_data_tlast => '0', - s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), - s_axis_data_tdata => s_axis_data_tdata, - s_axis_config_tvalid => '0', - s_axis_config_tlast => '0', - s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), - s_axis_reload_tvalid => '0', - s_axis_reload_tlast => '0', - s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), - m_axis_data_tvalid => m_axis_data_tvalid, - m_axis_data_tready => '1', - m_axis_data_tdata => m_axis_data_tdata - ); -END GaussFir_1mp5_arch; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/data_1p5m.veo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/data_1p5m.veo deleted file mode 100644 index ad5bf728..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/data_1p5m.veo +++ /dev/null @@ -1,68 +0,0 @@ -// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 -// IP Revision: 3 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -data_1p5m your_instance_name ( - .clka(clka), // input wire clka - .ena(ena), // input wire ena - .addra(addra), // input wire [10 : 0] addra - .douta(douta) // output wire [0 : 0] douta -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file data_1p5m.v when simulating -// the core, data_1p5m. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/data_1p5m.vho b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/data_1p5m.vho deleted file mode 100644 index e1b43435..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/data_1p5m.vho +++ /dev/null @@ -1,81 +0,0 @@ --- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 --- IP Revision: 3 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT data_1p5m - PORT ( - clka : IN STD_LOGIC; - ena : IN STD_LOGIC; - addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); - douta : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : data_1p5m - PORT MAP ( - clka => clka, - ena => ena, - addra => addra, - douta => douta - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file data_1p5m.vhd when simulating --- the core, data_1p5m. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/data_1p5m_sim_netlist.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/data_1p5m_sim_netlist.v deleted file mode 100644 index fb64abdb..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/data_1p5m_sim_netlist.v +++ /dev/null @@ -1,734 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:34:17 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_sim_netlist.v -// Design : data_1p5m -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* CHECK_LICENSE_TYPE = "data_1p5m,blk_mem_gen_v8_4_3,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) -(* NotValidForBitStream *) -module data_1p5m - (clka, - ena, - addra, - douta); - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) input clka; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [10:0]addra; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [0:0]douta; - - wire [10:0]addra; - wire clka; - wire [0:0]douta; - wire ena; - wire NLW_U0_dbiterr_UNCONNECTED; - wire NLW_U0_rsta_busy_UNCONNECTED; - wire NLW_U0_rstb_busy_UNCONNECTED; - wire NLW_U0_s_axi_arready_UNCONNECTED; - wire NLW_U0_s_axi_awready_UNCONNECTED; - wire NLW_U0_s_axi_bvalid_UNCONNECTED; - wire NLW_U0_s_axi_dbiterr_UNCONNECTED; - wire NLW_U0_s_axi_rlast_UNCONNECTED; - wire NLW_U0_s_axi_rvalid_UNCONNECTED; - wire NLW_U0_s_axi_sbiterr_UNCONNECTED; - wire NLW_U0_s_axi_wready_UNCONNECTED; - wire NLW_U0_sbiterr_UNCONNECTED; - wire [0:0]NLW_U0_doutb_UNCONNECTED; - wire [10:0]NLW_U0_rdaddrecc_UNCONNECTED; - wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED; - wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; - wire [10:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED; - wire [0:0]NLW_U0_s_axi_rdata_UNCONNECTED; - wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED; - wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; - - (* C_ADDRA_WIDTH = "11" *) - (* C_ADDRB_WIDTH = "11" *) - (* C_ALGORITHM = "1" *) - (* C_AXI_ID_WIDTH = "4" *) - (* C_AXI_SLAVE_TYPE = "0" *) - (* C_AXI_TYPE = "1" *) - (* C_BYTE_SIZE = "9" *) - (* C_COMMON_CLK = "0" *) - (* C_COUNT_18K_BRAM = "1" *) - (* C_COUNT_36K_BRAM = "0" *) - (* C_CTRL_ECC_ALGO = "NONE" *) - (* C_DEFAULT_DATA = "0" *) - (* C_DISABLE_WARN_BHV_COLL = "0" *) - (* C_DISABLE_WARN_BHV_RANGE = "0" *) - (* C_ELABORATION_DIR = "./" *) - (* C_ENABLE_32BIT_ADDRESS = "0" *) - (* C_EN_DEEPSLEEP_PIN = "0" *) - (* C_EN_ECC_PIPE = "0" *) - (* C_EN_RDADDRA_CHG = "0" *) - (* C_EN_RDADDRB_CHG = "0" *) - (* C_EN_SAFETY_CKT = "0" *) - (* C_EN_SHUTDOWN_PIN = "0" *) - (* C_EN_SLEEP_PIN = "0" *) - (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 0.990811 mW" *) - (* C_FAMILY = "kintex7" *) - (* C_HAS_AXI_ID = "0" *) - (* C_HAS_ENA = "1" *) - (* C_HAS_ENB = "0" *) - (* C_HAS_INJECTERR = "0" *) - (* C_HAS_MEM_OUTPUT_REGS_A = "1" *) - (* C_HAS_MEM_OUTPUT_REGS_B = "0" *) - (* C_HAS_MUX_OUTPUT_REGS_A = "1" *) - (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) - (* C_HAS_REGCEA = "0" *) - (* C_HAS_REGCEB = "0" *) - (* C_HAS_RSTA = "0" *) - (* C_HAS_RSTB = "0" *) - (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) - (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) - (* C_INITA_VAL = "0" *) - (* C_INITB_VAL = "0" *) - (* C_INIT_FILE = "data_1p5m.mem" *) - (* C_INIT_FILE_NAME = "data_1p5m.mif" *) - (* C_INTERFACE_TYPE = "0" *) - (* C_LOAD_INIT_FILE = "1" *) - (* C_MEM_TYPE = "3" *) - (* C_MUX_PIPELINE_STAGES = "0" *) - (* C_PRIM_TYPE = "1" *) - (* C_READ_DEPTH_A = "2048" *) - (* C_READ_DEPTH_B = "2048" *) - (* C_READ_LATENCY_A = "1" *) - (* C_READ_LATENCY_B = "1" *) - (* C_READ_WIDTH_A = "1" *) - (* C_READ_WIDTH_B = "1" *) - (* C_RSTRAM_A = "0" *) - (* C_RSTRAM_B = "0" *) - (* C_RST_PRIORITY_A = "CE" *) - (* C_RST_PRIORITY_B = "CE" *) - (* C_SIM_COLLISION_CHECK = "ALL" *) - (* C_USE_BRAM_BLOCK = "0" *) - (* C_USE_BYTE_WEA = "0" *) - (* C_USE_BYTE_WEB = "0" *) - (* C_USE_DEFAULT_DATA = "0" *) - (* C_USE_ECC = "0" *) - (* C_USE_SOFTECC = "0" *) - (* C_USE_URAM = "0" *) - (* C_WEA_WIDTH = "1" *) - (* C_WEB_WIDTH = "1" *) - (* C_WRITE_DEPTH_A = "2048" *) - (* C_WRITE_DEPTH_B = "2048" *) - (* C_WRITE_MODE_A = "WRITE_FIRST" *) - (* C_WRITE_MODE_B = "WRITE_FIRST" *) - (* C_WRITE_WIDTH_A = "1" *) - (* C_WRITE_WIDTH_B = "1" *) - (* C_XDEVICEFAMILY = "kintex7" *) - (* downgradeipidentifiedwarnings = "yes" *) - data_1p5m_blk_mem_gen_v8_4_3 U0 - (.addra(addra), - .addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .clka(clka), - .clkb(1'b0), - .dbiterr(NLW_U0_dbiterr_UNCONNECTED), - .deepsleep(1'b0), - .dina(1'b0), - .dinb(1'b0), - .douta(douta), - .doutb(NLW_U0_doutb_UNCONNECTED[0]), - .eccpipece(1'b0), - .ena(ena), - .enb(1'b0), - .injectdbiterr(1'b0), - .injectsbiterr(1'b0), - .rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[10:0]), - .regcea(1'b0), - .regceb(1'b0), - .rsta(1'b0), - .rsta_busy(NLW_U0_rsta_busy_UNCONNECTED), - .rstb(1'b0), - .rstb_busy(NLW_U0_rstb_busy_UNCONNECTED), - .s_aclk(1'b0), - .s_aresetn(1'b0), - .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_arburst({1'b0,1'b0}), - .s_axi_arid({1'b0,1'b0,1'b0,1'b0}), - .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED), - .s_axi_arsize({1'b0,1'b0,1'b0}), - .s_axi_arvalid(1'b0), - .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_awburst({1'b0,1'b0}), - .s_axi_awid({1'b0,1'b0,1'b0,1'b0}), - .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED), - .s_axi_awsize({1'b0,1'b0,1'b0}), - .s_axi_awvalid(1'b0), - .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]), - .s_axi_bready(1'b0), - .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]), - .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED), - .s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED), - .s_axi_injectdbiterr(1'b0), - .s_axi_injectsbiterr(1'b0), - .s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[10:0]), - .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[0]), - .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]), - .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED), - .s_axi_rready(1'b0), - .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]), - .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED), - .s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED), - .s_axi_wdata(1'b0), - .s_axi_wlast(1'b0), - .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED), - .s_axi_wstrb(1'b0), - .s_axi_wvalid(1'b0), - .sbiterr(NLW_U0_sbiterr_UNCONNECTED), - .shutdown(1'b0), - .sleep(1'b0), - .wea(1'b0), - .web(1'b0)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) -module data_1p5m_blk_mem_gen_generic_cstr - (douta, - clka, - ena, - addra); - output [0:0]douta; - input clka; - input ena; - input [10:0]addra; - - wire [10:0]addra; - wire clka; - wire [0:0]douta; - wire ena; - wire ram_douta; - - FDRE #( - .INIT(1'b0)) - \mux_a_wire.mux_reg.ce_pri.douta_i_reg[0] - (.C(clka), - .CE(ena), - .D(ram_douta), - .Q(douta), - .R(1'b0)); - data_1p5m_blk_mem_gen_prim_width \ramloop[0].ram.r - (.DOADO(ram_douta), - .addra(addra), - .clka(clka), - .ena(ena)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) -module data_1p5m_blk_mem_gen_prim_width - (DOADO, - clka, - ena, - addra); - output [0:0]DOADO; - input clka; - input ena; - input [10:0]addra; - - wire [0:0]DOADO; - wire [10:0]addra; - wire clka; - wire ena; - - data_1p5m_blk_mem_gen_prim_wrapper_init \prim_init.ram - (.DOADO(DOADO), - .addra(addra), - .clka(clka), - .ena(ena)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) -module data_1p5m_blk_mem_gen_prim_wrapper_init - (DOADO, - clka, - ena, - addra); - output [0:0]DOADO; - input clka; - input ena; - input [10:0]addra; - - wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_10 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_11 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_12 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_13 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_14 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_8 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_9 ; - wire [0:0]DOADO; - wire [10:0]addra; - wire clka; - wire ena; - wire [15:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ; - wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ; - wire [1:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ; - wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ; - - (* box_type = "PRIMITIVE" *) - RAMB18E1 #( - .DOA_REG(1), - .DOB_REG(0), - .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_00(256'h0101000001010101000101000001010100010100010101000101000100010001), - .INIT_01(256'h0000010001000000010100000100010100000100010101000100000100000101), - .INIT_02(256'h0001000000010001010000010101000100010100000000010100000001010001), - .INIT_03(256'h0100000101000100010000010000000101010000000001000000000101000001), - .INIT_04(256'h0001010101010000000001000100010100000001010000010001000101010000), - .INIT_05(256'h0101010100010000000101000101010101000100010000010001010000000101), - .INIT_06(256'h0101010100010100010001010001010000000001000001010100000000010101), - .INIT_07(256'h0000010100010000000101010001000000000100010000000100010001000001), - .INIT_08(256'h0101000101010101010000000000000001000000010001000001000100000100), - .INIT_09(256'h0000010000000101000100010001000000000101000001010001010100010001), - .INIT_0A(256'h0000000101000100000001000001000100000100000101010100010100000101), - .INIT_0B(256'h0100010001000000010101000101010001010000010101010101000001010100), - .INIT_0C(256'h0100010101010001000101010101000000010100010100000000000101010100), - .INIT_0D(256'h0001010001010000000000010000010100000000010100010001000001010101), - .INIT_0E(256'h0000010000010001000000000001000100000000010000000101000100000100), - .INIT_0F(256'h0000010101010100000000000000010101010001000001000100010101010101), - .INIT_10(256'h0101000100010001010100010101000101010000010101010000000001000000), - .INIT_11(256'h0101010100000000000001000000010000000100000001000001000001000001), - .INIT_12(256'h0000000101010101000001000100010100010000010000010100010101000101), - .INIT_13(256'h0100000000000000000100000100010000010000000101010101000101000100), - .INIT_14(256'h0101010101010100010001000100010001010100000100000101010101010001), - .INIT_15(256'h0100010000010101000000010001000001000100000001010001010000010000), - .INIT_16(256'h0100000001000101000101010100000100000101000101000101010000010001), - .INIT_17(256'h0100010001000100000101000000010000000000000000010000010001010000), - .INIT_18(256'h0000010100000100000101010101000000000101010101010001010100010100), - .INIT_19(256'h0100000100010001000100010000010000000100000000010001010001010100), - .INIT_1A(256'h0001010100010001000100000100000000010100010001010100010100010001), - .INIT_1B(256'h0100010000000101010000010101010100000000010001000000010000000001), - .INIT_1C(256'h0101000000010100000000010100010100000001000000000100000100010100), - .INIT_1D(256'h0101010101000101000100000100000000000001010001000101010100000001), - .INIT_1E(256'h0101010100010001010000010101000100000100000100000000000101000000), - .INIT_1F(256'h0101010000000100000001010001010001010001000001000001000001000101), - .INIT_20(256'h0101000100010000010001000101010100010000010001010101000100010001), - .INIT_21(256'h0001000001000100010000010101000001000100010101010100010100000101), - .INIT_22(256'h0101000100010101010101010001000100000100000001000000010101000100), - .INIT_23(256'h0000000000010101010100010001010100010101010001000001010100000000), - .INIT_24(256'h0100000000010000000100000100000101000100000100010001010000000001), - .INIT_25(256'h0001010100000001010000010000000001010000000100000100000101010100), - .INIT_26(256'h0001010101010000010101000001000000010001010101000000010000010100), - .INIT_27(256'h0001000000010100010101010001000100000000000000000001010000010101), - .INIT_28(256'h0101010101010001010101010100000100000100000000000001000100000000), - .INIT_29(256'h0100000100010101000001000101010001000001000000010001010001000100), - .INIT_2A(256'h0001000000010000010001000101000101000101010000000100000000000101), - .INIT_2B(256'h0100010101000000000101000101000001000101010101010100000001000101), - .INIT_2C(256'h0101010000000001000001000100010100000000000100010001000101010001), - .INIT_2D(256'h0001010000000101000100000101000000000001000100000100000000010001), - .INIT_2E(256'h0001010101010000010101010000010000000000010001000100000000000001), - .INIT_2F(256'h0000010101000100010000010000000000010101010100000001000001000000), - .INIT_30(256'h0101000100000100010000000000000101010001000100000100000101000101), - .INIT_31(256'h0000000000000001010001000100010001000000010101010001000100000001), - .INIT_32(256'h0101000100010001010101010101000100000101010100000101000101000101), - .INIT_33(256'h0000010101000101000101010001010001010101010000010101010001010101), - .INIT_34(256'h0101000000010001010100010000010100000001000000000101000001010100), - .INIT_35(256'h0001000001000100000101000001000101010001000100010101010100000000), - .INIT_36(256'h0000010100010000010101010001010101000001010101000001000001000101), - .INIT_37(256'h0001000101000101000000010101000101010100000100010101000000010001), - .INIT_38(256'h0000000001010101000000000100000101000001010001000100010100010001), - .INIT_39(256'h0000010101000001000000010000000100010001010100010001010101000101), - .INIT_3A(256'h0101010100000100000000000001000000010100010000010001000101010001), - .INIT_3B(256'h0001010100010101010100000001010101010101010000010001000100010001), - .INIT_3C(256'h0000000001010000000100000101000101000101010100000000010100010101), - .INIT_3D(256'h0001000101000000010000000100010100010101010001000000000000010001), - .INIT_3E(256'h0000000101000100000000010000010000010100010001000000010100000100), - .INIT_3F(256'h0100000000010001000100010100000101000000010100000101010100010000), - .INIT_A(18'h00000), - .INIT_B(18'h00000), - .INIT_FILE("NONE"), - .IS_CLKARDCLK_INVERTED(1'b0), - .IS_CLKBWRCLK_INVERTED(1'b0), - .IS_ENARDEN_INVERTED(1'b0), - .IS_ENBWREN_INVERTED(1'b0), - .IS_RSTRAMARSTRAM_INVERTED(1'b0), - .IS_RSTRAMB_INVERTED(1'b0), - .IS_RSTREGARSTREG_INVERTED(1'b0), - .IS_RSTREGB_INVERTED(1'b0), - .RAM_MODE("TDP"), - .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), - .READ_WIDTH_A(9), - .READ_WIDTH_B(9), - .RSTREG_PRIORITY_A("REGCE"), - .RSTREG_PRIORITY_B("REGCE"), - .SIM_COLLISION_CHECK("ALL"), - .SIM_DEVICE("7SERIES"), - .SRVAL_A(18'h00000), - .SRVAL_B(18'h00000), - .WRITE_MODE_A("WRITE_FIRST"), - .WRITE_MODE_B("WRITE_FIRST"), - .WRITE_WIDTH_A(9), - .WRITE_WIDTH_B(9)) - \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram - (.ADDRARDADDR({addra,1'b0,1'b0,1'b0}), - .ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .CLKARDCLK(clka), - .CLKBWRCLK(clka), - .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIPADIP({1'b0,1'b0}), - .DIPBDIP({1'b0,1'b0}), - .DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:8],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_8 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_9 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_10 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_11 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_12 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_13 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_14 ,DOADO}), - .DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]), - .DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33 }), - .DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]), - .ENARDEN(ena), - .ENBWREN(1'b0), - .REGCEAREGCE(ena), - .REGCEB(1'b0), - .RSTRAMARSTRAM(1'b0), - .RSTRAMB(1'b0), - .RSTREGARSTREG(1'b0), - .RSTREGB(1'b0), - .WEA({1'b0,1'b0}), - .WEBWE({1'b0,1'b0,1'b0,1'b0})); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_top" *) -module data_1p5m_blk_mem_gen_top - (douta, - clka, - ena, - addra); - output [0:0]douta; - input clka; - input ena; - input [10:0]addra; - - wire [10:0]addra; - wire clka; - wire [0:0]douta; - wire ena; - - data_1p5m_blk_mem_gen_generic_cstr \valid.cstr - (.addra(addra), - .clka(clka), - .douta(douta), - .ena(ena)); -endmodule - -(* C_ADDRA_WIDTH = "11" *) (* C_ADDRB_WIDTH = "11" *) (* C_ALGORITHM = "1" *) -(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *) -(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *) -(* C_COUNT_36K_BRAM = "0" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *) -(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *) -(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *) -(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *) -(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 0.990811 mW" *) -(* C_FAMILY = "kintex7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *) -(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *) -(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "1" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) -(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *) -(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) -(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "data_1p5m.mem" *) -(* C_INIT_FILE_NAME = "data_1p5m.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *) -(* C_MEM_TYPE = "3" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *) -(* C_READ_DEPTH_A = "2048" *) (* C_READ_DEPTH_B = "2048" *) (* C_READ_LATENCY_A = "1" *) -(* C_READ_LATENCY_B = "1" *) (* C_READ_WIDTH_A = "1" *) (* C_READ_WIDTH_B = "1" *) -(* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *) -(* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *) -(* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *) -(* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *) -(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "2048" *) -(* C_WRITE_DEPTH_B = "2048" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) -(* C_WRITE_WIDTH_A = "1" *) (* C_WRITE_WIDTH_B = "1" *) (* C_XDEVICEFAMILY = "kintex7" *) -(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3" *) (* downgradeipidentifiedwarnings = "yes" *) -module data_1p5m_blk_mem_gen_v8_4_3 - (clka, - rsta, - ena, - regcea, - wea, - addra, - dina, - douta, - clkb, - rstb, - enb, - regceb, - web, - addrb, - dinb, - doutb, - injectsbiterr, - injectdbiterr, - eccpipece, - sbiterr, - dbiterr, - rdaddrecc, - sleep, - deepsleep, - shutdown, - rsta_busy, - rstb_busy, - s_aclk, - s_aresetn, - s_axi_awid, - s_axi_awaddr, - s_axi_awlen, - s_axi_awsize, - s_axi_awburst, - s_axi_awvalid, - s_axi_awready, - s_axi_wdata, - s_axi_wstrb, - s_axi_wlast, - s_axi_wvalid, - s_axi_wready, - s_axi_bid, - s_axi_bresp, - s_axi_bvalid, - s_axi_bready, - s_axi_arid, - s_axi_araddr, - s_axi_arlen, - s_axi_arsize, - s_axi_arburst, - s_axi_arvalid, - s_axi_arready, - s_axi_rid, - s_axi_rdata, - s_axi_rresp, - s_axi_rlast, - s_axi_rvalid, - s_axi_rready, - s_axi_injectsbiterr, - s_axi_injectdbiterr, - s_axi_sbiterr, - s_axi_dbiterr, - s_axi_rdaddrecc); - input clka; - input rsta; - input ena; - input regcea; - input [0:0]wea; - input [10:0]addra; - input [0:0]dina; - output [0:0]douta; - input clkb; - input rstb; - input enb; - input regceb; - input [0:0]web; - input [10:0]addrb; - input [0:0]dinb; - output [0:0]doutb; - input injectsbiterr; - input injectdbiterr; - input eccpipece; - output sbiterr; - output dbiterr; - output [10:0]rdaddrecc; - input sleep; - input deepsleep; - input shutdown; - output rsta_busy; - output rstb_busy; - input s_aclk; - input s_aresetn; - input [3:0]s_axi_awid; - input [31:0]s_axi_awaddr; - input [7:0]s_axi_awlen; - input [2:0]s_axi_awsize; - input [1:0]s_axi_awburst; - input s_axi_awvalid; - output s_axi_awready; - input [0:0]s_axi_wdata; - input [0:0]s_axi_wstrb; - input s_axi_wlast; - input s_axi_wvalid; - output s_axi_wready; - output [3:0]s_axi_bid; - output [1:0]s_axi_bresp; - output s_axi_bvalid; - input s_axi_bready; - input [3:0]s_axi_arid; - input [31:0]s_axi_araddr; - input [7:0]s_axi_arlen; - input [2:0]s_axi_arsize; - input [1:0]s_axi_arburst; - input s_axi_arvalid; - output s_axi_arready; - output [3:0]s_axi_rid; - output [0:0]s_axi_rdata; - output [1:0]s_axi_rresp; - output s_axi_rlast; - output s_axi_rvalid; - input s_axi_rready; - input s_axi_injectsbiterr; - input s_axi_injectdbiterr; - output s_axi_sbiterr; - output s_axi_dbiterr; - output [10:0]s_axi_rdaddrecc; - - wire \ ; - wire [10:0]addra; - wire clka; - wire [0:0]douta; - wire ena; - - assign dbiterr = \ ; - assign doutb[0] = \ ; - assign rdaddrecc[10] = \ ; - assign rdaddrecc[9] = \ ; - assign rdaddrecc[8] = \ ; - assign rdaddrecc[7] = \ ; - assign rdaddrecc[6] = \ ; - assign rdaddrecc[5] = \ ; - assign rdaddrecc[4] = \ ; - assign rdaddrecc[3] = \ ; - assign rdaddrecc[2] = \ ; - assign rdaddrecc[1] = \ ; - assign rdaddrecc[0] = \ ; - assign rsta_busy = \ ; - assign rstb_busy = \ ; - assign s_axi_arready = \ ; - assign s_axi_awready = \ ; - assign s_axi_bid[3] = \ ; - assign s_axi_bid[2] = \ ; - assign s_axi_bid[1] = \ ; - assign s_axi_bid[0] = \ ; - assign s_axi_bresp[1] = \ ; - assign s_axi_bresp[0] = \ ; - assign s_axi_bvalid = \ ; - assign s_axi_dbiterr = \ ; - assign s_axi_rdaddrecc[10] = \ ; - assign s_axi_rdaddrecc[9] = \ ; - assign s_axi_rdaddrecc[8] = \ ; - assign s_axi_rdaddrecc[7] = \ ; - assign s_axi_rdaddrecc[6] = \ ; - assign s_axi_rdaddrecc[5] = \ ; - assign s_axi_rdaddrecc[4] = \ ; - assign s_axi_rdaddrecc[3] = \ ; - assign s_axi_rdaddrecc[2] = \ ; - assign s_axi_rdaddrecc[1] = \ ; - assign s_axi_rdaddrecc[0] = \ ; - assign s_axi_rdata[0] = \ ; - assign s_axi_rid[3] = \ ; - assign s_axi_rid[2] = \ ; - assign s_axi_rid[1] = \ ; - assign s_axi_rid[0] = \ ; - assign s_axi_rlast = \ ; - assign s_axi_rresp[1] = \ ; - assign s_axi_rresp[0] = \ ; - assign s_axi_rvalid = \ ; - assign s_axi_sbiterr = \ ; - assign s_axi_wready = \ ; - assign sbiterr = \ ; - GND GND - (.G(\ )); - data_1p5m_blk_mem_gen_v8_4_3_synth inst_blk_mem_gen - (.addra(addra), - .clka(clka), - .douta(douta), - .ena(ena)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3_synth" *) -module data_1p5m_blk_mem_gen_v8_4_3_synth - (douta, - clka, - ena, - addra); - output [0:0]douta; - input clka; - input ena; - input [10:0]addra; - - wire [10:0]addra; - wire clka; - wire [0:0]douta; - wire ena; - - data_1p5m_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen - (.addra(addra), - .clka(clka), - .douta(douta), - .ena(ena)); -endmodule -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/data_1p5m_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/data_1p5m_sim_netlist.vhdl deleted file mode 100644 index bcd24484..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/data_1p5m_sim_netlist.vhdl +++ /dev/null @@ -1,849 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:34:17 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_sim_netlist.vhdl --- Design : data_1p5m --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity data_1p5m_blk_mem_gen_prim_wrapper_init is - port ( - DOADO : out STD_LOGIC_VECTOR ( 0 to 0 ); - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of data_1p5m_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; -end data_1p5m_blk_mem_gen_prim_wrapper_init; - -architecture STRUCTURE of data_1p5m_blk_mem_gen_prim_wrapper_init is - signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_10\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_11\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_12\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_13\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_14\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_8\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_9\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); - attribute box_type : string; - attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE"; -begin -\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1 - generic map( - DOA_REG => 1, - DOB_REG => 0, - INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_00 => X"0101000001010101000101000001010100010100010101000101000100010001", - INIT_01 => X"0000010001000000010100000100010100000100010101000100000100000101", - INIT_02 => X"0001000000010001010000010101000100010100000000010100000001010001", - INIT_03 => X"0100000101000100010000010000000101010000000001000000000101000001", - INIT_04 => X"0001010101010000000001000100010100000001010000010001000101010000", - INIT_05 => X"0101010100010000000101000101010101000100010000010001010000000101", - INIT_06 => X"0101010100010100010001010001010000000001000001010100000000010101", - INIT_07 => X"0000010100010000000101010001000000000100010000000100010001000001", - INIT_08 => X"0101000101010101010000000000000001000000010001000001000100000100", - INIT_09 => X"0000010000000101000100010001000000000101000001010001010100010001", - INIT_0A => X"0000000101000100000001000001000100000100000101010100010100000101", - INIT_0B => X"0100010001000000010101000101010001010000010101010101000001010100", - INIT_0C => X"0100010101010001000101010101000000010100010100000000000101010100", - INIT_0D => X"0001010001010000000000010000010100000000010100010001000001010101", - INIT_0E => X"0000010000010001000000000001000100000000010000000101000100000100", - INIT_0F => X"0000010101010100000000000000010101010001000001000100010101010101", - INIT_10 => X"0101000100010001010100010101000101010000010101010000000001000000", - INIT_11 => X"0101010100000000000001000000010000000100000001000001000001000001", - INIT_12 => X"0000000101010101000001000100010100010000010000010100010101000101", - INIT_13 => X"0100000000000000000100000100010000010000000101010101000101000100", - INIT_14 => X"0101010101010100010001000100010001010100000100000101010101010001", - INIT_15 => X"0100010000010101000000010001000001000100000001010001010000010000", - INIT_16 => X"0100000001000101000101010100000100000101000101000101010000010001", - INIT_17 => X"0100010001000100000101000000010000000000000000010000010001010000", - INIT_18 => X"0000010100000100000101010101000000000101010101010001010100010100", - INIT_19 => X"0100000100010001000100010000010000000100000000010001010001010100", - INIT_1A => X"0001010100010001000100000100000000010100010001010100010100010001", - INIT_1B => X"0100010000000101010000010101010100000000010001000000010000000001", - INIT_1C => X"0101000000010100000000010100010100000001000000000100000100010100", - INIT_1D => X"0101010101000101000100000100000000000001010001000101010100000001", - INIT_1E => X"0101010100010001010000010101000100000100000100000000000101000000", - INIT_1F => X"0101010000000100000001010001010001010001000001000001000001000101", - INIT_20 => X"0101000100010000010001000101010100010000010001010101000100010001", - INIT_21 => X"0001000001000100010000010101000001000100010101010100010100000101", - INIT_22 => X"0101000100010101010101010001000100000100000001000000010101000100", - INIT_23 => X"0000000000010101010100010001010100010101010001000001010100000000", - INIT_24 => X"0100000000010000000100000100000101000100000100010001010000000001", - INIT_25 => X"0001010100000001010000010000000001010000000100000100000101010100", - INIT_26 => X"0001010101010000010101000001000000010001010101000000010000010100", - INIT_27 => X"0001000000010100010101010001000100000000000000000001010000010101", - INIT_28 => X"0101010101010001010101010100000100000100000000000001000100000000", - INIT_29 => X"0100000100010101000001000101010001000001000000010001010001000100", - INIT_2A => X"0001000000010000010001000101000101000101010000000100000000000101", - INIT_2B => X"0100010101000000000101000101000001000101010101010100000001000101", - INIT_2C => X"0101010000000001000001000100010100000000000100010001000101010001", - INIT_2D => X"0001010000000101000100000101000000000001000100000100000000010001", - INIT_2E => X"0001010101010000010101010000010000000000010001000100000000000001", - INIT_2F => X"0000010101000100010000010000000000010101010100000001000001000000", - INIT_30 => X"0101000100000100010000000000000101010001000100000100000101000101", - INIT_31 => X"0000000000000001010001000100010001000000010101010001000100000001", - INIT_32 => X"0101000100010001010101010101000100000101010100000101000101000101", - INIT_33 => X"0000010101000101000101010001010001010101010000010101010001010101", - INIT_34 => X"0101000000010001010100010000010100000001000000000101000001010100", - INIT_35 => X"0001000001000100000101000001000101010001000100010101010100000000", - INIT_36 => X"0000010100010000010101010001010101000001010101000001000001000101", - INIT_37 => X"0001000101000101000000010101000101010100000100010101000000010001", - INIT_38 => X"0000000001010101000000000100000101000001010001000100010100010001", - INIT_39 => X"0000010101000001000000010000000100010001010100010001010101000101", - INIT_3A => X"0101010100000100000000000001000000010100010000010001000101010001", - INIT_3B => X"0001010100010101010100000001010101010101010000010001000100010001", - INIT_3C => X"0000000001010000000100000101000101000101010100000000010100010101", - INIT_3D => X"0001000101000000010000000100010100010101010001000000000000010001", - INIT_3E => X"0000000101000100000000010000010000010100010001000000010100000100", - INIT_3F => X"0100000000010001000100010100000101000000010100000101010100010000", - INIT_A => X"00000", - INIT_B => X"00000", - INIT_FILE => "NONE", - IS_CLKARDCLK_INVERTED => '0', - IS_CLKBWRCLK_INVERTED => '0', - IS_ENARDEN_INVERTED => '0', - IS_ENBWREN_INVERTED => '0', - IS_RSTRAMARSTRAM_INVERTED => '0', - IS_RSTRAMB_INVERTED => '0', - IS_RSTREGARSTREG_INVERTED => '0', - IS_RSTREGB_INVERTED => '0', - RAM_MODE => "TDP", - RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", - READ_WIDTH_A => 9, - READ_WIDTH_B => 9, - RSTREG_PRIORITY_A => "REGCE", - RSTREG_PRIORITY_B => "REGCE", - SIM_COLLISION_CHECK => "ALL", - SIM_DEVICE => "7SERIES", - SRVAL_A => X"00000", - SRVAL_B => X"00000", - WRITE_MODE_A => "WRITE_FIRST", - WRITE_MODE_B => "WRITE_FIRST", - WRITE_WIDTH_A => 9, - WRITE_WIDTH_B => 9 - ) - port map ( - ADDRARDADDR(13 downto 3) => addra(10 downto 0), - ADDRARDADDR(2 downto 0) => B"000", - ADDRBWRADDR(13 downto 0) => B"00000000000000", - CLKARDCLK => clka, - CLKBWRCLK => clka, - DIADI(15 downto 0) => B"0000000000000000", - DIBDI(15 downto 0) => B"0000000000000000", - DIPADIP(1 downto 0) => B"00", - DIPBDIP(1 downto 0) => B"00", - DOADO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 8), - DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_8\, - DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_9\, - DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_10\, - DOADO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_11\, - DOADO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_12\, - DOADO(2) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_13\, - DOADO(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_14\, - DOADO(0) => DOADO(0), - DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0), - DOPADOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1), - DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33\, - DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0), - ENARDEN => ena, - ENBWREN => '0', - REGCEAREGCE => ena, - REGCEB => '0', - RSTRAMARSTRAM => '0', - RSTRAMB => '0', - RSTREGARSTREG => '0', - RSTREGB => '0', - WEA(1 downto 0) => B"00", - WEBWE(3 downto 0) => B"0000" - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity data_1p5m_blk_mem_gen_prim_width is - port ( - DOADO : out STD_LOGIC_VECTOR ( 0 to 0 ); - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of data_1p5m_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; -end data_1p5m_blk_mem_gen_prim_width; - -architecture STRUCTURE of data_1p5m_blk_mem_gen_prim_width is -begin -\prim_init.ram\: entity work.data_1p5m_blk_mem_gen_prim_wrapper_init - port map ( - DOADO(0) => DOADO(0), - addra(10 downto 0) => addra(10 downto 0), - clka => clka, - ena => ena - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity data_1p5m_blk_mem_gen_generic_cstr is - port ( - douta : out STD_LOGIC_VECTOR ( 0 to 0 ); - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of data_1p5m_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; -end data_1p5m_blk_mem_gen_generic_cstr; - -architecture STRUCTURE of data_1p5m_blk_mem_gen_generic_cstr is - signal ram_douta : STD_LOGIC; -begin -\mux_a_wire.mux_reg.ce_pri.douta_i_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => ena, - D => ram_douta, - Q => douta(0), - R => '0' - ); -\ramloop[0].ram.r\: entity work.data_1p5m_blk_mem_gen_prim_width - port map ( - DOADO(0) => ram_douta, - addra(10 downto 0) => addra(10 downto 0), - clka => clka, - ena => ena - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity data_1p5m_blk_mem_gen_top is - port ( - douta : out STD_LOGIC_VECTOR ( 0 to 0 ); - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of data_1p5m_blk_mem_gen_top : entity is "blk_mem_gen_top"; -end data_1p5m_blk_mem_gen_top; - -architecture STRUCTURE of data_1p5m_blk_mem_gen_top is -begin -\valid.cstr\: entity work.data_1p5m_blk_mem_gen_generic_cstr - port map ( - addra(10 downto 0) => addra(10 downto 0), - clka => clka, - douta(0) => douta(0), - ena => ena - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity data_1p5m_blk_mem_gen_v8_4_3_synth is - port ( - douta : out STD_LOGIC_VECTOR ( 0 to 0 ); - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of data_1p5m_blk_mem_gen_v8_4_3_synth : entity is "blk_mem_gen_v8_4_3_synth"; -end data_1p5m_blk_mem_gen_v8_4_3_synth; - -architecture STRUCTURE of data_1p5m_blk_mem_gen_v8_4_3_synth is -begin -\gnbram.gnativebmg.native_blk_mem_gen\: entity work.data_1p5m_blk_mem_gen_top - port map ( - addra(10 downto 0) => addra(10 downto 0), - clka => clka, - douta(0) => douta(0), - ena => ena - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity data_1p5m_blk_mem_gen_v8_4_3 is - port ( - clka : in STD_LOGIC; - rsta : in STD_LOGIC; - ena : in STD_LOGIC; - regcea : in STD_LOGIC; - wea : in STD_LOGIC_VECTOR ( 0 to 0 ); - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); - dina : in STD_LOGIC_VECTOR ( 0 to 0 ); - douta : out STD_LOGIC_VECTOR ( 0 to 0 ); - clkb : in STD_LOGIC; - rstb : in STD_LOGIC; - enb : in STD_LOGIC; - regceb : in STD_LOGIC; - web : in STD_LOGIC_VECTOR ( 0 to 0 ); - addrb : in STD_LOGIC_VECTOR ( 10 downto 0 ); - dinb : in STD_LOGIC_VECTOR ( 0 to 0 ); - doutb : out STD_LOGIC_VECTOR ( 0 to 0 ); - injectsbiterr : in STD_LOGIC; - injectdbiterr : in STD_LOGIC; - eccpipece : in STD_LOGIC; - sbiterr : out STD_LOGIC; - dbiterr : out STD_LOGIC; - rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 ); - sleep : in STD_LOGIC; - deepsleep : in STD_LOGIC; - shutdown : in STD_LOGIC; - rsta_busy : out STD_LOGIC; - rstb_busy : out STD_LOGIC; - s_aclk : in STD_LOGIC; - s_aresetn : in STD_LOGIC; - s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_awvalid : in STD_LOGIC; - s_axi_awready : out STD_LOGIC; - s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_wlast : in STD_LOGIC; - s_axi_wvalid : in STD_LOGIC; - s_axi_wready : out STD_LOGIC; - s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_bvalid : out STD_LOGIC; - s_axi_bready : in STD_LOGIC; - s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_arvalid : in STD_LOGIC; - s_axi_arready : out STD_LOGIC; - s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_rdata : out STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_rlast : out STD_LOGIC; - s_axi_rvalid : out STD_LOGIC; - s_axi_rready : in STD_LOGIC; - s_axi_injectsbiterr : in STD_LOGIC; - s_axi_injectdbiterr : in STD_LOGIC; - s_axi_sbiterr : out STD_LOGIC; - s_axi_dbiterr : out STD_LOGIC; - s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 ) - ); - attribute C_ADDRA_WIDTH : integer; - attribute C_ADDRA_WIDTH of data_1p5m_blk_mem_gen_v8_4_3 : entity is 11; - attribute C_ADDRB_WIDTH : integer; - attribute C_ADDRB_WIDTH of data_1p5m_blk_mem_gen_v8_4_3 : entity is 11; - attribute C_ALGORITHM : integer; - attribute C_ALGORITHM of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_AXI_ID_WIDTH : integer; - attribute C_AXI_ID_WIDTH of data_1p5m_blk_mem_gen_v8_4_3 : entity is 4; - attribute C_AXI_SLAVE_TYPE : integer; - attribute C_AXI_SLAVE_TYPE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_AXI_TYPE : integer; - attribute C_AXI_TYPE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_BYTE_SIZE : integer; - attribute C_BYTE_SIZE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 9; - attribute C_COMMON_CLK : integer; - attribute C_COMMON_CLK of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_COUNT_18K_BRAM : string; - attribute C_COUNT_18K_BRAM of data_1p5m_blk_mem_gen_v8_4_3 : entity is "1"; - attribute C_COUNT_36K_BRAM : string; - attribute C_COUNT_36K_BRAM of data_1p5m_blk_mem_gen_v8_4_3 : entity is "0"; - attribute C_CTRL_ECC_ALGO : string; - attribute C_CTRL_ECC_ALGO of data_1p5m_blk_mem_gen_v8_4_3 : entity is "NONE"; - attribute C_DEFAULT_DATA : string; - attribute C_DEFAULT_DATA of data_1p5m_blk_mem_gen_v8_4_3 : entity is "0"; - attribute C_DISABLE_WARN_BHV_COLL : integer; - attribute C_DISABLE_WARN_BHV_COLL of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_DISABLE_WARN_BHV_RANGE : integer; - attribute C_DISABLE_WARN_BHV_RANGE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_ELABORATION_DIR : string; - attribute C_ELABORATION_DIR of data_1p5m_blk_mem_gen_v8_4_3 : entity is "./"; - attribute C_ENABLE_32BIT_ADDRESS : integer; - attribute C_ENABLE_32BIT_ADDRESS of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_DEEPSLEEP_PIN : integer; - attribute C_EN_DEEPSLEEP_PIN of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_ECC_PIPE : integer; - attribute C_EN_ECC_PIPE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_RDADDRA_CHG : integer; - attribute C_EN_RDADDRA_CHG of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_RDADDRB_CHG : integer; - attribute C_EN_RDADDRB_CHG of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_SAFETY_CKT : integer; - attribute C_EN_SAFETY_CKT of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_SHUTDOWN_PIN : integer; - attribute C_EN_SHUTDOWN_PIN of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_SLEEP_PIN : integer; - attribute C_EN_SLEEP_PIN of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EST_POWER_SUMMARY : string; - attribute C_EST_POWER_SUMMARY of data_1p5m_blk_mem_gen_v8_4_3 : entity is "Estimated Power for IP : 0.990811 mW"; - attribute C_FAMILY : string; - attribute C_FAMILY of data_1p5m_blk_mem_gen_v8_4_3 : entity is "kintex7"; - attribute C_HAS_AXI_ID : integer; - attribute C_HAS_AXI_ID of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_ENA : integer; - attribute C_HAS_ENA of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_HAS_ENB : integer; - attribute C_HAS_ENB of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_INJECTERR : integer; - attribute C_HAS_INJECTERR of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_MEM_OUTPUT_REGS_A : integer; - attribute C_HAS_MEM_OUTPUT_REGS_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_HAS_MEM_OUTPUT_REGS_B : integer; - attribute C_HAS_MEM_OUTPUT_REGS_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_MUX_OUTPUT_REGS_A : integer; - attribute C_HAS_MUX_OUTPUT_REGS_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_HAS_MUX_OUTPUT_REGS_B : integer; - attribute C_HAS_MUX_OUTPUT_REGS_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_REGCEA : integer; - attribute C_HAS_REGCEA of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_REGCEB : integer; - attribute C_HAS_REGCEB of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_RSTA : integer; - attribute C_HAS_RSTA of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_RSTB : integer; - attribute C_HAS_RSTB of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; - attribute C_HAS_SOFTECC_INPUT_REGS_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; - attribute C_HAS_SOFTECC_OUTPUT_REGS_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_INITA_VAL : string; - attribute C_INITA_VAL of data_1p5m_blk_mem_gen_v8_4_3 : entity is "0"; - attribute C_INITB_VAL : string; - attribute C_INITB_VAL of data_1p5m_blk_mem_gen_v8_4_3 : entity is "0"; - attribute C_INIT_FILE : string; - attribute C_INIT_FILE of data_1p5m_blk_mem_gen_v8_4_3 : entity is "data_1p5m.mem"; - attribute C_INIT_FILE_NAME : string; - attribute C_INIT_FILE_NAME of data_1p5m_blk_mem_gen_v8_4_3 : entity is "data_1p5m.mif"; - attribute C_INTERFACE_TYPE : integer; - attribute C_INTERFACE_TYPE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_LOAD_INIT_FILE : integer; - attribute C_LOAD_INIT_FILE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_MEM_TYPE : integer; - attribute C_MEM_TYPE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 3; - attribute C_MUX_PIPELINE_STAGES : integer; - attribute C_MUX_PIPELINE_STAGES of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_PRIM_TYPE : integer; - attribute C_PRIM_TYPE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_READ_DEPTH_A : integer; - attribute C_READ_DEPTH_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 2048; - attribute C_READ_DEPTH_B : integer; - attribute C_READ_DEPTH_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 2048; - attribute C_READ_LATENCY_A : integer; - attribute C_READ_LATENCY_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_READ_LATENCY_B : integer; - attribute C_READ_LATENCY_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_READ_WIDTH_A : integer; - attribute C_READ_WIDTH_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_READ_WIDTH_B : integer; - attribute C_READ_WIDTH_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_RSTRAM_A : integer; - attribute C_RSTRAM_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_RSTRAM_B : integer; - attribute C_RSTRAM_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_RST_PRIORITY_A : string; - attribute C_RST_PRIORITY_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is "CE"; - attribute C_RST_PRIORITY_B : string; - attribute C_RST_PRIORITY_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is "CE"; - attribute C_SIM_COLLISION_CHECK : string; - attribute C_SIM_COLLISION_CHECK of data_1p5m_blk_mem_gen_v8_4_3 : entity is "ALL"; - attribute C_USE_BRAM_BLOCK : integer; - attribute C_USE_BRAM_BLOCK of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_BYTE_WEA : integer; - attribute C_USE_BYTE_WEA of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_BYTE_WEB : integer; - attribute C_USE_BYTE_WEB of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_DEFAULT_DATA : integer; - attribute C_USE_DEFAULT_DATA of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_ECC : integer; - attribute C_USE_ECC of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_SOFTECC : integer; - attribute C_USE_SOFTECC of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_URAM : integer; - attribute C_USE_URAM of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_WEA_WIDTH : integer; - attribute C_WEA_WIDTH of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_WEB_WIDTH : integer; - attribute C_WEB_WIDTH of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_WRITE_DEPTH_A : integer; - attribute C_WRITE_DEPTH_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 2048; - attribute C_WRITE_DEPTH_B : integer; - attribute C_WRITE_DEPTH_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 2048; - attribute C_WRITE_MODE_A : string; - attribute C_WRITE_MODE_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is "WRITE_FIRST"; - attribute C_WRITE_MODE_B : string; - attribute C_WRITE_MODE_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is "WRITE_FIRST"; - attribute C_WRITE_WIDTH_A : integer; - attribute C_WRITE_WIDTH_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_WRITE_WIDTH_B : integer; - attribute C_WRITE_WIDTH_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of data_1p5m_blk_mem_gen_v8_4_3 : entity is "kintex7"; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of data_1p5m_blk_mem_gen_v8_4_3 : entity is "blk_mem_gen_v8_4_3"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of data_1p5m_blk_mem_gen_v8_4_3 : entity is "yes"; -end data_1p5m_blk_mem_gen_v8_4_3; - -architecture STRUCTURE of data_1p5m_blk_mem_gen_v8_4_3 is - signal \\ : STD_LOGIC; -begin - dbiterr <= \\; - doutb(0) <= \\; - rdaddrecc(10) <= \\; - rdaddrecc(9) <= \\; - rdaddrecc(8) <= \\; - rdaddrecc(7) <= \\; - rdaddrecc(6) <= \\; - rdaddrecc(5) <= \\; - rdaddrecc(4) <= \\; - rdaddrecc(3) <= \\; - rdaddrecc(2) <= \\; - rdaddrecc(1) <= \\; - rdaddrecc(0) <= \\; - rsta_busy <= \\; - rstb_busy <= \\; - s_axi_arready <= \\; - s_axi_awready <= \\; - s_axi_bid(3) <= \\; - s_axi_bid(2) <= \\; - s_axi_bid(1) <= \\; - s_axi_bid(0) <= \\; - s_axi_bresp(1) <= \\; - s_axi_bresp(0) <= \\; - s_axi_bvalid <= \\; - s_axi_dbiterr <= \\; - s_axi_rdaddrecc(10) <= \\; - s_axi_rdaddrecc(9) <= \\; - s_axi_rdaddrecc(8) <= \\; - s_axi_rdaddrecc(7) <= \\; - s_axi_rdaddrecc(6) <= \\; - s_axi_rdaddrecc(5) <= \\; - s_axi_rdaddrecc(4) <= \\; - s_axi_rdaddrecc(3) <= \\; - s_axi_rdaddrecc(2) <= \\; - s_axi_rdaddrecc(1) <= \\; - s_axi_rdaddrecc(0) <= \\; - s_axi_rdata(0) <= \\; - s_axi_rid(3) <= \\; - s_axi_rid(2) <= \\; - s_axi_rid(1) <= \\; - s_axi_rid(0) <= \\; - s_axi_rlast <= \\; - s_axi_rresp(1) <= \\; - s_axi_rresp(0) <= \\; - s_axi_rvalid <= \\; - s_axi_sbiterr <= \\; - s_axi_wready <= \\; - sbiterr <= \\; -GND: unisim.vcomponents.GND - port map ( - G => \\ - ); -inst_blk_mem_gen: entity work.data_1p5m_blk_mem_gen_v8_4_3_synth - port map ( - addra(10 downto 0) => addra(10 downto 0), - clka => clka, - douta(0) => douta(0), - ena => ena - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity data_1p5m is - port ( - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); - douta : out STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of data_1p5m : entity is true; - attribute CHECK_LICENSE_TYPE : string; - attribute CHECK_LICENSE_TYPE of data_1p5m : entity is "data_1p5m,blk_mem_gen_v8_4_3,{}"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of data_1p5m : entity is "yes"; - attribute x_core_info : string; - attribute x_core_info of data_1p5m : entity is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; -end data_1p5m; - -architecture STRUCTURE of data_1p5m is - signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; - signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); - signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); - signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - attribute C_ADDRA_WIDTH : integer; - attribute C_ADDRA_WIDTH of U0 : label is 11; - attribute C_ADDRB_WIDTH : integer; - attribute C_ADDRB_WIDTH of U0 : label is 11; - attribute C_ALGORITHM : integer; - attribute C_ALGORITHM of U0 : label is 1; - attribute C_AXI_ID_WIDTH : integer; - attribute C_AXI_ID_WIDTH of U0 : label is 4; - attribute C_AXI_SLAVE_TYPE : integer; - attribute C_AXI_SLAVE_TYPE of U0 : label is 0; - attribute C_AXI_TYPE : integer; - attribute C_AXI_TYPE of U0 : label is 1; - attribute C_BYTE_SIZE : integer; - attribute C_BYTE_SIZE of U0 : label is 9; - attribute C_COMMON_CLK : integer; - attribute C_COMMON_CLK of U0 : label is 0; - attribute C_COUNT_18K_BRAM : string; - attribute C_COUNT_18K_BRAM of U0 : label is "1"; - attribute C_COUNT_36K_BRAM : string; - attribute C_COUNT_36K_BRAM of U0 : label is "0"; - attribute C_CTRL_ECC_ALGO : string; - attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; - attribute C_DEFAULT_DATA : string; - attribute C_DEFAULT_DATA of U0 : label is "0"; - attribute C_DISABLE_WARN_BHV_COLL : integer; - attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; - attribute C_DISABLE_WARN_BHV_RANGE : integer; - attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; - attribute C_ELABORATION_DIR : string; - attribute C_ELABORATION_DIR of U0 : label is "./"; - attribute C_ENABLE_32BIT_ADDRESS : integer; - attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; - attribute C_EN_DEEPSLEEP_PIN : integer; - attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; - attribute C_EN_ECC_PIPE : integer; - attribute C_EN_ECC_PIPE of U0 : label is 0; - attribute C_EN_RDADDRA_CHG : integer; - attribute C_EN_RDADDRA_CHG of U0 : label is 0; - attribute C_EN_RDADDRB_CHG : integer; - attribute C_EN_RDADDRB_CHG of U0 : label is 0; - attribute C_EN_SAFETY_CKT : integer; - attribute C_EN_SAFETY_CKT of U0 : label is 0; - attribute C_EN_SHUTDOWN_PIN : integer; - attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; - attribute C_EN_SLEEP_PIN : integer; - attribute C_EN_SLEEP_PIN of U0 : label is 0; - attribute C_EST_POWER_SUMMARY : string; - attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 0.990811 mW"; - attribute C_FAMILY : string; - attribute C_FAMILY of U0 : label is "kintex7"; - attribute C_HAS_AXI_ID : integer; - attribute C_HAS_AXI_ID of U0 : label is 0; - attribute C_HAS_ENA : integer; - attribute C_HAS_ENA of U0 : label is 1; - attribute C_HAS_ENB : integer; - attribute C_HAS_ENB of U0 : label is 0; - attribute C_HAS_INJECTERR : integer; - attribute C_HAS_INJECTERR of U0 : label is 0; - attribute C_HAS_MEM_OUTPUT_REGS_A : integer; - attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1; - attribute C_HAS_MEM_OUTPUT_REGS_B : integer; - attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; - attribute C_HAS_MUX_OUTPUT_REGS_A : integer; - attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 1; - attribute C_HAS_MUX_OUTPUT_REGS_B : integer; - attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; - attribute C_HAS_REGCEA : integer; - attribute C_HAS_REGCEA of U0 : label is 0; - attribute C_HAS_REGCEB : integer; - attribute C_HAS_REGCEB of U0 : label is 0; - attribute C_HAS_RSTA : integer; - attribute C_HAS_RSTA of U0 : label is 0; - attribute C_HAS_RSTB : integer; - attribute C_HAS_RSTB of U0 : label is 0; - attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; - attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; - attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; - attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; - attribute C_INITA_VAL : string; - attribute C_INITA_VAL of U0 : label is "0"; - attribute C_INITB_VAL : string; - attribute C_INITB_VAL of U0 : label is "0"; - attribute C_INIT_FILE : string; - attribute C_INIT_FILE of U0 : label is "data_1p5m.mem"; - attribute C_INIT_FILE_NAME : string; - attribute C_INIT_FILE_NAME of U0 : label is "data_1p5m.mif"; - attribute C_INTERFACE_TYPE : integer; - attribute C_INTERFACE_TYPE of U0 : label is 0; - attribute C_LOAD_INIT_FILE : integer; - attribute C_LOAD_INIT_FILE of U0 : label is 1; - attribute C_MEM_TYPE : integer; - attribute C_MEM_TYPE of U0 : label is 3; - attribute C_MUX_PIPELINE_STAGES : integer; - attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; - attribute C_PRIM_TYPE : integer; - attribute C_PRIM_TYPE of U0 : label is 1; - attribute C_READ_DEPTH_A : integer; - attribute C_READ_DEPTH_A of U0 : label is 2048; - attribute C_READ_DEPTH_B : integer; - attribute C_READ_DEPTH_B of U0 : label is 2048; - attribute C_READ_LATENCY_A : integer; - attribute C_READ_LATENCY_A of U0 : label is 1; - attribute C_READ_LATENCY_B : integer; - attribute C_READ_LATENCY_B of U0 : label is 1; - attribute C_READ_WIDTH_A : integer; - attribute C_READ_WIDTH_A of U0 : label is 1; - attribute C_READ_WIDTH_B : integer; - attribute C_READ_WIDTH_B of U0 : label is 1; - attribute C_RSTRAM_A : integer; - attribute C_RSTRAM_A of U0 : label is 0; - attribute C_RSTRAM_B : integer; - attribute C_RSTRAM_B of U0 : label is 0; - attribute C_RST_PRIORITY_A : string; - attribute C_RST_PRIORITY_A of U0 : label is "CE"; - attribute C_RST_PRIORITY_B : string; - attribute C_RST_PRIORITY_B of U0 : label is "CE"; - attribute C_SIM_COLLISION_CHECK : string; - attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; - attribute C_USE_BRAM_BLOCK : integer; - attribute C_USE_BRAM_BLOCK of U0 : label is 0; - attribute C_USE_BYTE_WEA : integer; - attribute C_USE_BYTE_WEA of U0 : label is 0; - attribute C_USE_BYTE_WEB : integer; - attribute C_USE_BYTE_WEB of U0 : label is 0; - attribute C_USE_DEFAULT_DATA : integer; - attribute C_USE_DEFAULT_DATA of U0 : label is 0; - attribute C_USE_ECC : integer; - attribute C_USE_ECC of U0 : label is 0; - attribute C_USE_SOFTECC : integer; - attribute C_USE_SOFTECC of U0 : label is 0; - attribute C_USE_URAM : integer; - attribute C_USE_URAM of U0 : label is 0; - attribute C_WEA_WIDTH : integer; - attribute C_WEA_WIDTH of U0 : label is 1; - attribute C_WEB_WIDTH : integer; - attribute C_WEB_WIDTH of U0 : label is 1; - attribute C_WRITE_DEPTH_A : integer; - attribute C_WRITE_DEPTH_A of U0 : label is 2048; - attribute C_WRITE_DEPTH_B : integer; - attribute C_WRITE_DEPTH_B of U0 : label is 2048; - attribute C_WRITE_MODE_A : string; - attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST"; - attribute C_WRITE_MODE_B : string; - attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; - attribute C_WRITE_WIDTH_A : integer; - attribute C_WRITE_WIDTH_A of U0 : label is 1; - attribute C_WRITE_WIDTH_B : integer; - attribute C_WRITE_WIDTH_B of U0 : label is 1; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of U0 : label is "kintex7"; - attribute downgradeipidentifiedwarnings of U0 : label is "yes"; - attribute x_interface_info : string; - attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; - attribute x_interface_parameter : string; - attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1"; - attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN"; - attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; - attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; -begin -U0: entity work.data_1p5m_blk_mem_gen_v8_4_3 - port map ( - addra(10 downto 0) => addra(10 downto 0), - addrb(10 downto 0) => B"00000000000", - clka => clka, - clkb => '0', - dbiterr => NLW_U0_dbiterr_UNCONNECTED, - deepsleep => '0', - dina(0) => '0', - dinb(0) => '0', - douta(0) => douta(0), - doutb(0) => NLW_U0_doutb_UNCONNECTED(0), - eccpipece => '0', - ena => ena, - enb => '0', - injectdbiterr => '0', - injectsbiterr => '0', - rdaddrecc(10 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(10 downto 0), - regcea => '0', - regceb => '0', - rsta => '0', - rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, - rstb => '0', - rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, - s_aclk => '0', - s_aresetn => '0', - s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", - s_axi_arburst(1 downto 0) => B"00", - s_axi_arid(3 downto 0) => B"0000", - s_axi_arlen(7 downto 0) => B"00000000", - s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, - s_axi_arsize(2 downto 0) => B"000", - s_axi_arvalid => '0', - s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", - s_axi_awburst(1 downto 0) => B"00", - s_axi_awid(3 downto 0) => B"0000", - s_axi_awlen(7 downto 0) => B"00000000", - s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, - s_axi_awsize(2 downto 0) => B"000", - s_axi_awvalid => '0', - s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), - s_axi_bready => '0', - s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), - s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, - s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, - s_axi_injectdbiterr => '0', - s_axi_injectsbiterr => '0', - s_axi_rdaddrecc(10 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(10 downto 0), - s_axi_rdata(0) => NLW_U0_s_axi_rdata_UNCONNECTED(0), - s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), - s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, - s_axi_rready => '0', - s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), - s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, - s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, - s_axi_wdata(0) => '0', - s_axi_wlast => '0', - s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, - s_axi_wstrb(0) => '0', - s_axi_wvalid => '0', - sbiterr => NLW_U0_sbiterr_UNCONNECTED, - shutdown => '0', - sleep => '0', - wea(0) => '0', - web(0) => '0' - ); -end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/data_1p5m_stub.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/data_1p5m_stub.v deleted file mode 100644 index 7ece828a..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/data_1p5m_stub.v +++ /dev/null @@ -1,23 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:34:17 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_stub.v -// Design : data_1p5m -// Purpose : Stub declaration of top-level module interface -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) -module data_1p5m(clka, ena, addra, douta) -/* synthesis syn_black_box black_box_pad_pin="clka,ena,addra[10:0],douta[0:0]" */; - input clka; - input ena; - input [10:0]addra; - output [0:0]douta; -endmodule diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/data_1p5m_stub.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/data_1p5m_stub.vhdl deleted file mode 100644 index 434c04bd..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/data_1p5m_stub.vhdl +++ /dev/null @@ -1,33 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:34:17 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_stub.vhdl --- Design : data_1p5m --- Purpose : Stub declaration of top-level module interface --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity data_1p5m is - Port ( - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); - douta : out STD_LOGIC_VECTOR ( 0 to 0 ) - ); - -end data_1p5m; - -architecture stub of data_1p5m is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clka,ena,addra[10:0],douta[0:0]"; -attribute x_core_info : string; -attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; -begin -end; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/sim/data_1p5m.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/sim/data_1p5m.v deleted file mode 100644 index b47f55d3..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/data_1p5m/sim/data_1p5m.v +++ /dev/null @@ -1,214 +0,0 @@ -// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - - -// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 -// IP Revision: 3 - -`timescale 1ns/1ps - -(* DowngradeIPIdentifiedWarnings = "yes" *) -module data_1p5m ( - clka, - ena, - addra, - douta -); - -(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) -input wire clka; -(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) -input wire ena; -(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) -input wire [10 : 0] addra; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) -(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) -output wire [0 : 0] douta; - - blk_mem_gen_v8_4_3 #( - .C_FAMILY("kintex7"), - .C_XDEVICEFAMILY("kintex7"), - .C_ELABORATION_DIR("./"), - .C_INTERFACE_TYPE(0), - .C_AXI_TYPE(1), - .C_AXI_SLAVE_TYPE(0), - .C_USE_BRAM_BLOCK(0), - .C_ENABLE_32BIT_ADDRESS(0), - .C_CTRL_ECC_ALGO("NONE"), - .C_HAS_AXI_ID(0), - .C_AXI_ID_WIDTH(4), - .C_MEM_TYPE(3), - .C_BYTE_SIZE(9), - .C_ALGORITHM(1), - .C_PRIM_TYPE(1), - .C_LOAD_INIT_FILE(1), - .C_INIT_FILE_NAME("data_1p5m.mif"), - .C_INIT_FILE("data_1p5m.mem"), - .C_USE_DEFAULT_DATA(0), - .C_DEFAULT_DATA("0"), - .C_HAS_RSTA(0), - .C_RST_PRIORITY_A("CE"), - .C_RSTRAM_A(0), - .C_INITA_VAL("0"), - .C_HAS_ENA(1), - .C_HAS_REGCEA(0), - .C_USE_BYTE_WEA(0), - .C_WEA_WIDTH(1), - .C_WRITE_MODE_A("WRITE_FIRST"), - .C_WRITE_WIDTH_A(1), - .C_READ_WIDTH_A(1), - .C_WRITE_DEPTH_A(2048), - .C_READ_DEPTH_A(2048), - .C_ADDRA_WIDTH(11), - .C_HAS_RSTB(0), - .C_RST_PRIORITY_B("CE"), - .C_RSTRAM_B(0), - .C_INITB_VAL("0"), - .C_HAS_ENB(0), - .C_HAS_REGCEB(0), - .C_USE_BYTE_WEB(0), - .C_WEB_WIDTH(1), - .C_WRITE_MODE_B("WRITE_FIRST"), - .C_WRITE_WIDTH_B(1), - .C_READ_WIDTH_B(1), - .C_WRITE_DEPTH_B(2048), - .C_READ_DEPTH_B(2048), - .C_ADDRB_WIDTH(11), - .C_HAS_MEM_OUTPUT_REGS_A(1), - .C_HAS_MEM_OUTPUT_REGS_B(0), - .C_HAS_MUX_OUTPUT_REGS_A(1), - .C_HAS_MUX_OUTPUT_REGS_B(0), - .C_MUX_PIPELINE_STAGES(0), - .C_HAS_SOFTECC_INPUT_REGS_A(0), - .C_HAS_SOFTECC_OUTPUT_REGS_B(0), - .C_USE_SOFTECC(0), - .C_USE_ECC(0), - .C_EN_ECC_PIPE(0), - .C_READ_LATENCY_A(1), - .C_READ_LATENCY_B(1), - .C_HAS_INJECTERR(0), - .C_SIM_COLLISION_CHECK("ALL"), - .C_COMMON_CLK(0), - .C_DISABLE_WARN_BHV_COLL(0), - .C_EN_SLEEP_PIN(0), - .C_USE_URAM(0), - .C_EN_RDADDRA_CHG(0), - .C_EN_RDADDRB_CHG(0), - .C_EN_DEEPSLEEP_PIN(0), - .C_EN_SHUTDOWN_PIN(0), - .C_EN_SAFETY_CKT(0), - .C_DISABLE_WARN_BHV_RANGE(0), - .C_COUNT_36K_BRAM("0"), - .C_COUNT_18K_BRAM("1"), - .C_EST_POWER_SUMMARY("Estimated Power for IP : 0.990811 mW") - ) inst ( - .clka(clka), - .rsta(1'D0), - .ena(ena), - .regcea(1'D0), - .wea(1'B0), - .addra(addra), - .dina(1'B0), - .douta(douta), - .clkb(1'D0), - .rstb(1'D0), - .enb(1'D0), - .regceb(1'D0), - .web(1'B0), - .addrb(11'B0), - .dinb(1'B0), - .doutb(), - .injectsbiterr(1'D0), - .injectdbiterr(1'D0), - .eccpipece(1'D0), - .sbiterr(), - .dbiterr(), - .rdaddrecc(), - .sleep(1'D0), - .deepsleep(1'D0), - .shutdown(1'D0), - .rsta_busy(), - .rstb_busy(), - .s_aclk(1'H0), - .s_aresetn(1'D0), - .s_axi_awid(4'B0), - .s_axi_awaddr(32'B0), - .s_axi_awlen(8'B0), - .s_axi_awsize(3'B0), - .s_axi_awburst(2'B0), - .s_axi_awvalid(1'D0), - .s_axi_awready(), - .s_axi_wdata(1'B0), - .s_axi_wstrb(1'B0), - .s_axi_wlast(1'D0), - .s_axi_wvalid(1'D0), - .s_axi_wready(), - .s_axi_bid(), - .s_axi_bresp(), - .s_axi_bvalid(), - .s_axi_bready(1'D0), - .s_axi_arid(4'B0), - .s_axi_araddr(32'B0), - .s_axi_arlen(8'B0), - .s_axi_arsize(3'B0), - .s_axi_arburst(2'B0), - .s_axi_arvalid(1'D0), - .s_axi_arready(), - .s_axi_rid(), - .s_axi_rdata(), - .s_axi_rresp(), - .s_axi_rlast(), - .s_axi_rvalid(), - .s_axi_rready(1'D0), - .s_axi_injectsbiterr(1'D0), - .s_axi_injectdbiterr(1'D0), - .s_axi_sbiterr(), - .s_axi_dbiterr(), - .s_axi_rdaddrecc() - ); -endmodule diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/sim/vio_manual_ctrl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/sim/vio_manual_ctrl.v index 3acdf5fb..493f196e 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/sim/vio_manual_ctrl.v +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/sim/vio_manual_ctrl.v @@ -58,7 +58,7 @@ probe_out4 input clk; -output reg [2 : 0] probe_out0 = 'h0 ; +output reg [1 : 0] probe_out0 = 'h2 ; output reg [0 : 0] probe_out1 = 'h0 ; output reg [31 : 0] probe_out2 = 'h00000000 ; output reg [1 : 0] probe_out3 = 'h3 ; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.veo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.veo index 4832fe5b..39fbf855 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.veo +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.veo @@ -56,7 +56,7 @@ //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG vio_manual_ctrl your_instance_name ( .clk(clk), // input wire clk - .probe_out0(probe_out0), // output wire [2 : 0] probe_out0 + .probe_out0(probe_out0), // output wire [1 : 0] probe_out0 .probe_out1(probe_out1), // output wire [0 : 0] probe_out1 .probe_out2(probe_out2), // output wire [31 : 0] probe_out2 .probe_out3(probe_out3), // output wire [1 : 0] probe_out3 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.vho b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.vho index 0775b07e..877bb0cb 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.vho +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.vho @@ -55,7 +55,7 @@ COMPONENT vio_manual_ctrl PORT ( clk : IN STD_LOGIC; - probe_out0 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + probe_out0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); probe_out2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); probe_out3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.v index 466415a6..d76c3fc0 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.v +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:34:28 2023 +// Date : Tue Mar 21 22:54:43 2023 // Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) // Command : write_verilog -force -mode funcsim -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v +// D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v // Design : vio_manual_ctrl // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -22,14 +22,14 @@ module vio_manual_ctrl probe_out3, probe_out4); input clk; - output [2:0]probe_out0; + output [1:0]probe_out0; output [0:0]probe_out1; output [31:0]probe_out2; output [1:0]probe_out3; output [3:0]probe_out4; wire clk; - wire [2:0]probe_out0; + wire [1:0]probe_out0; wire [0:0]probe_out1; wire [31:0]probe_out2; wire [1:0]probe_out3; @@ -563,8 +563,8 @@ module vio_manual_ctrl (* C_PROBE_IN98_WIDTH = "1" *) (* C_PROBE_IN99_WIDTH = "1" *) (* C_PROBE_IN9_WIDTH = "1" *) - (* C_PROBE_OUT0_INIT_VAL = "3'b000" *) - (* C_PROBE_OUT0_WIDTH = "3" *) + (* C_PROBE_OUT0_INIT_VAL = "2'b10" *) + (* C_PROBE_OUT0_WIDTH = "2" *) (* C_PROBE_OUT100_INIT_VAL = "1'b0" *) (* C_PROBE_OUT100_WIDTH = "1" *) (* C_PROBE_OUT101_INIT_VAL = "1'b0" *) @@ -1081,525 +1081,525 @@ module vio_manual_ctrl (* C_XSDB_SLAVE_TYPE = "33" *) (* DONT_TOUCH *) (* DowngradeIPIdentifiedWarnings = "yes" *) - (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000101111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000010001001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000010001010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000010001011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000010001100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000010001101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000010001110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000010001111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000010010000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000010010001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000010010010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000110000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000010010011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000010010100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000010010101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000010010110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000010010111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000010011000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000010011001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000010011010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000010011011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000010011100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000110001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000010011101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000010011110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000010011111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000010100000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000010100001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000010100010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000010100011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000010100100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010100101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010100110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000110010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010100111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010101000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010101001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010101010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010101011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010101100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010101101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010101110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010101111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010110000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000110011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010110001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010110010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010110011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010110100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010110101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010110110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010110111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010111000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010111001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010111010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000110100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010111011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010111100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010111101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010111110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010111111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000011000000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000011000001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000011000010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000011000011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000011000100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000110101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000011000101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000011000110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000011000111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000011001000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000011001001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000011001010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000011001011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000011001100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000011001101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000011001110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000110110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000011001111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000011010000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000011010001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000011010010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000011010011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000011010100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000011010101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000011010110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000011010111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000011011000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000110111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000011011001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000011011010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000011011011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000011011100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000011011101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000011011110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000011011111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000011100000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000011100001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000011100010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000111000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000011100011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000011100100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011100101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011100110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011100111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011101000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011101001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011101010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011101011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011101100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000100011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000111001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011101101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011101110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011101111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011110000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011110001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011110010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011110011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011110100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011110101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011110110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000111010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011110111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011111000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011111001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011111010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011111011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011111100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011111101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011111110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011111111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000100000000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000111011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000100000001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000100000010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000100000011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000100000100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000100000101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000100000110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000100000111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000100001000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000100001001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000100001010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000111100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000100001011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000100001100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000100001101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000100001110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000100001111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000100010000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000100010001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000100010010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000100010011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000100010100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000111101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000100010101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000100010110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000100010111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000100011000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000100011001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000100011010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000100011011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000100011100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000100011101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000100011110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000111110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000100011111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000100100000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000100100001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000100100010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000100100011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000100100100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000111111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000001000000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000001000001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000001000010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000100101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000001000011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000001000100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000001000101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000001000110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000001000111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000001001000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000001001001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000001001010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000001001011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000001001100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000101001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000001001101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000001001110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000001001111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000001010000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000001010001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000001010010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000001010011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000001010100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000001010101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000001010110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000101010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000001010111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000001011000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000001011001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000001011010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000001011011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000001011100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000001011101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000001011110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000001011111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000001100000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000101011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000001100001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000001100010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000001100011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000001100100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001100101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001100110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001100111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001101000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001101001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001101010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000101100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001101011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001101100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001101101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001101110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001101111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001110000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001110001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001110010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001110011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001110100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000101101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001110101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001110110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001110111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001111000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001111001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001111010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001111011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001111100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001111101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001111110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000101110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001111111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000010000000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000010000001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000010000010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000010000011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000010000100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000010000101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000010000110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000010000111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000010001000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000101110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000010001000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000010001001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000010001010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000010001011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000010001100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000010001101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000010001110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000010001111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000010010000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000010010001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000101111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000010010010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000010010011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000010010100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000010010101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000010010110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000010010111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000010011000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000010011001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000010011010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000010011011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000110000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000010011100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000010011101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000010011110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000010011111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000010100000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000010100001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000010100010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000010100011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010100100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010100101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000110001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010100110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010100111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010101000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010101001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010101010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010101011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010101100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010101101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010101110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010101111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000110010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010110000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010110001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010110010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010110011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010110100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010110101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010110110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010110111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010111000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010111001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000110011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010111010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010111011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010111100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010111101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010111110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010111111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000011000000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000011000001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000011000010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000011000011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000110100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000011000100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000011000101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000011000110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000011000111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000011001000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000011001001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000011001010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000011001011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000011001100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000011001101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000110101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000011001110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000011001111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000011010000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000011010001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000011010010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000011010011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000011010100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000011010101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000011010110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000011010111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000110110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000011011000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000011011001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000011011010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000011011011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000011011100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000011011101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000011011110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000011011111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000011100000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000011100001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000110111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000011100010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000011100011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011100100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011100101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011100110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011100111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011101000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011101001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011101010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011101011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000100010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000111000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011101100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011101101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011101110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011101111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011110000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011110001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011110010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011110011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011110100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011110101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000111001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011110110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011110111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011111000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011111001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011111010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011111011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011111100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011111101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011111110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011111111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000111010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000100000000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000100000001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000100000010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000100000011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000100000100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000100000101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000100000110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000100000111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000100001000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000100001001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000111011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000100001010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000100001011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000100001100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000100001101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000100001110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000100001111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000100010000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000100010001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000100010010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000100010011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000111100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000100010100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000100010101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000100010110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000100010111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000100011000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000100011001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000100011010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000100011011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000100011100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000100011101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000111101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000100011110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000100011111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000100100000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000100100001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000100100010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000100100011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000111110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000111111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000001000000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000001000001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000100100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000001000010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000001000011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000001000100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000001000101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000001000110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000001000111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000001001000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000001001001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000001001010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000001001011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000101000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000001001100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000001001101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000001001110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000001001111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000001010000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000001010001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000001010010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000001010011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000001010100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000001010101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000101001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000001010110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000001010111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000001011000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000001011001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000001011010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000001011011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000001011100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000001011101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000001011110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000001011111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000101010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000001100000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000001100001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000001100010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000001100011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001100100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001100101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001100110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001100111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001101000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001101001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000101011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001101010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001101011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001101100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001101101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001101110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001101111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001110000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001110001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001110010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001110011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000101100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001110100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001110101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001110110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001110111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001111000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001111001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001111010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001111011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001111100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001111101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000101101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001111110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001111111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000010000000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000010000001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000010000010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000010000011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000010000100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000010000101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000010000110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000010000111" *) (* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *) - (* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000011" *) - (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000101111" *) - (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000010001001" *) - (* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000010001010" *) - (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000010001011" *) - (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000010001100" *) - (* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000010001101" *) - (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000010001110" *) - (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000010001111" *) - (* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000010010000" *) - (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000010010001" *) - (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000010010010" *) - (* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000110000" *) - (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000010010011" *) - (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000010010100" *) - (* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000010010101" *) - (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000010010110" *) - (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000010010111" *) - (* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000010011000" *) - (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000010011001" *) - (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000010011010" *) - (* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000010011011" *) - (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000010011100" *) - (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000110001" *) - (* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000010011101" *) - (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000010011110" *) - (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000010011111" *) - (* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000010100000" *) - (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000010100001" *) - (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000010100010" *) - (* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000010100011" *) - (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000010100100" *) - (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010100101" *) - (* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010100110" *) - (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000110010" *) - (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010100111" *) - (* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010101000" *) - (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010101001" *) - (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010101010" *) - (* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010101011" *) - (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010101100" *) - (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010101101" *) - (* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010101110" *) - (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010101111" *) - (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010110000" *) - (* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000110011" *) - (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010110001" *) - (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010110010" *) - (* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010110011" *) - (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010110100" *) - (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010110101" *) - (* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010110110" *) - (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010110111" *) - (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010111000" *) - (* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010111001" *) - (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010111010" *) - (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000110100" *) - (* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010111011" *) - (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010111100" *) - (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010111101" *) - (* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010111110" *) - (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010111111" *) - (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000011000000" *) - (* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000011000001" *) - (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000011000010" *) - (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000011000011" *) - (* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000011000100" *) - (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000110101" *) - (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000011000101" *) - (* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000011000110" *) - (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000011000111" *) - (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000011001000" *) - (* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000011001001" *) - (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000011001010" *) - (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000011001011" *) - (* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000011001100" *) - (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000011001101" *) - (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000011001110" *) - (* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000110110" *) - (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000011001111" *) - (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000011010000" *) - (* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000011010001" *) - (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000011010010" *) - (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000011010011" *) - (* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000011010100" *) - (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000011010101" *) - (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000011010110" *) - (* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000011010111" *) - (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000011011000" *) - (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000110111" *) - (* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000011011001" *) - (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000011011010" *) - (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000011011011" *) - (* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000011011100" *) - (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000011011101" *) - (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000011011110" *) - (* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000011011111" *) - (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000011100000" *) - (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000011100001" *) - (* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000011100010" *) - (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000111000" *) - (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000011100011" *) - (* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000011100100" *) - (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011100101" *) - (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011100110" *) - (* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011100111" *) - (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011101000" *) - (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011101001" *) - (* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011101010" *) - (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011101011" *) - (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011101100" *) - (* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000100" *) - (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000111001" *) - (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011101101" *) - (* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011101110" *) - (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011101111" *) - (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011110000" *) - (* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011110001" *) - (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011110010" *) - (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011110011" *) - (* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011110100" *) - (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011110101" *) - (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011110110" *) - (* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000111010" *) - (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011110111" *) - (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011111000" *) - (* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011111001" *) - (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011111010" *) - (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011111011" *) - (* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011111100" *) - (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011111101" *) - (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011111110" *) - (* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011111111" *) - (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000100000000" *) - (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000111011" *) - (* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000100000001" *) - (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000100000010" *) - (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000100000011" *) - (* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000100000100" *) - (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000100000101" *) - (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000100000110" *) - (* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000100000111" *) - (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000100001000" *) - (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000100001001" *) - (* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000100001010" *) - (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000111100" *) - (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000100001011" *) - (* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000100001100" *) - (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000100001101" *) - (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000100001110" *) - (* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000100001111" *) - (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000100010000" *) - (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000100010001" *) - (* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000100010010" *) - (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000100010011" *) - (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000100010100" *) - (* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000111101" *) - (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000100010101" *) - (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000100010110" *) - (* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000100010111" *) - (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000100011000" *) - (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000100011001" *) - (* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000100011010" *) - (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000100011011" *) - (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000100011100" *) - (* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000100011101" *) - (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000100011110" *) - (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000111110" *) - (* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000100011111" *) - (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000100100000" *) - (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000100100001" *) - (* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000100100010" *) - (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000100100011" *) - (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000100100100" *) - (* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000111111" *) - (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000001000000" *) - (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000001000001" *) - (* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000001000010" *) - (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000100100" *) - (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000001000011" *) - (* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000001000100" *) - (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000001000101" *) - (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000001000110" *) - (* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000001000111" *) - (* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000001001000" *) - (* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000001001001" *) - (* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000001001010" *) - (* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000001001011" *) - (* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000001001100" *) - (* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000100110" *) - (* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000001001101" *) - (* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000001001110" *) - (* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000001001111" *) - (* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000001010000" *) - (* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000001010001" *) - (* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000001010010" *) - (* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000001010011" *) - (* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000001010100" *) - (* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000001010101" *) - (* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000001010110" *) - (* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000101010" *) - (* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000001010111" *) - (* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000001011000" *) - (* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000001011001" *) - (* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000001011010" *) - (* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000001011011" *) - (* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000001011100" *) - (* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000001011101" *) - (* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000001011110" *) - (* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000001011111" *) - (* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000001100000" *) - (* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000101011" *) - (* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000001100001" *) - (* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000001100010" *) - (* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000001100011" *) - (* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000001100100" *) - (* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001100101" *) - (* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001100110" *) - (* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001100111" *) - (* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001101000" *) - (* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001101001" *) - (* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001101010" *) - (* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000101100" *) - (* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001101011" *) - (* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001101100" *) - (* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001101101" *) - (* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001101110" *) - (* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001101111" *) - (* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001110000" *) - (* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001110001" *) - (* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001110010" *) - (* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001110011" *) - (* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001110100" *) - (* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000101101" *) - (* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001110101" *) - (* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001110110" *) - (* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001110111" *) - (* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001111000" *) - (* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001111001" *) - (* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001111010" *) - (* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001111011" *) - (* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001111100" *) - (* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001111101" *) - (* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001111110" *) - (* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000101110" *) - (* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001111111" *) - (* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000010000000" *) - (* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000010000001" *) - (* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000010000010" *) - (* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000010000011" *) - (* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000010000100" *) - (* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000010000101" *) - (* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000010000110" *) - (* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000010000111" *) - (* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000010001000" *) + (* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000010" *) + (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000101110" *) + (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000010001000" *) + (* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000010001001" *) + (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000010001010" *) + (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000010001011" *) + (* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000010001100" *) + (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000010001101" *) + (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000010001110" *) + (* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000010001111" *) + (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000010010000" *) + (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000010010001" *) + (* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000101111" *) + (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000010010010" *) + (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000010010011" *) + (* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000010010100" *) + (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000010010101" *) + (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000010010110" *) + (* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000010010111" *) + (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000010011000" *) + (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000010011001" *) + (* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000010011010" *) + (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000010011011" *) + (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000110000" *) + (* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000010011100" *) + (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000010011101" *) + (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000010011110" *) + (* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000010011111" *) + (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000010100000" *) + (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000010100001" *) + (* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000010100010" *) + (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000010100011" *) + (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010100100" *) + (* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010100101" *) + (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000110001" *) + (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010100110" *) + (* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010100111" *) + (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010101000" *) + (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010101001" *) + (* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010101010" *) + (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010101011" *) + (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010101100" *) + (* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010101101" *) + (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010101110" *) + (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010101111" *) + (* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000110010" *) + (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010110000" *) + (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010110001" *) + (* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010110010" *) + (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010110011" *) + (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010110100" *) + (* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010110101" *) + (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010110110" *) + (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010110111" *) + (* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010111000" *) + (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010111001" *) + (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000110011" *) + (* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010111010" *) + (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010111011" *) + (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010111100" *) + (* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010111101" *) + (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010111110" *) + (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010111111" *) + (* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000011000000" *) + (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000011000001" *) + (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000011000010" *) + (* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000011000011" *) + (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000110100" *) + (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000011000100" *) + (* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000011000101" *) + (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000011000110" *) + (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000011000111" *) + (* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000011001000" *) + (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000011001001" *) + (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000011001010" *) + (* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000011001011" *) + (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000011001100" *) + (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000011001101" *) + (* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000110101" *) + (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000011001110" *) + (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000011001111" *) + (* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000011010000" *) + (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000011010001" *) + (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000011010010" *) + (* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000011010011" *) + (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000011010100" *) + (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000011010101" *) + (* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000011010110" *) + (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000011010111" *) + (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000110110" *) + (* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000011011000" *) + (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000011011001" *) + (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000011011010" *) + (* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000011011011" *) + (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000011011100" *) + (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000011011101" *) + (* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000011011110" *) + (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000011011111" *) + (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000011100000" *) + (* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000011100001" *) + (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000110111" *) + (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000011100010" *) + (* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000011100011" *) + (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011100100" *) + (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011100101" *) + (* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011100110" *) + (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011100111" *) + (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011101000" *) + (* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011101001" *) + (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011101010" *) + (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011101011" *) + (* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000011" *) + (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000111000" *) + (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011101100" *) + (* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011101101" *) + (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011101110" *) + (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011101111" *) + (* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011110000" *) + (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011110001" *) + (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011110010" *) + (* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011110011" *) + (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011110100" *) + (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011110101" *) + (* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000111001" *) + (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011110110" *) + (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011110111" *) + (* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011111000" *) + (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011111001" *) + (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011111010" *) + (* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011111011" *) + (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011111100" *) + (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011111101" *) + (* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011111110" *) + (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011111111" *) + (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000111010" *) + (* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000100000000" *) + (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000100000001" *) + (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000100000010" *) + (* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000100000011" *) + (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000100000100" *) + (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000100000101" *) + (* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000100000110" *) + (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000100000111" *) + (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000100001000" *) + (* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000100001001" *) + (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000111011" *) + (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000100001010" *) + (* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000100001011" *) + (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000100001100" *) + (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000100001101" *) + (* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000100001110" *) + (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000100001111" *) + (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000100010000" *) + (* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000100010001" *) + (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000100010010" *) + (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000100010011" *) + (* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000111100" *) + (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000100010100" *) + (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000100010101" *) + (* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000100010110" *) + (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000100010111" *) + (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000100011000" *) + (* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000100011001" *) + (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000100011010" *) + (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000100011011" *) + (* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000100011100" *) + (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000100011101" *) + (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000111101" *) + (* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000100011110" *) + (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000100011111" *) + (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000100100000" *) + (* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000100100001" *) + (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000100100010" *) + (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000100100011" *) + (* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000111110" *) + (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000111111" *) + (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000001000000" *) + (* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000001000001" *) + (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000100011" *) + (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000001000010" *) + (* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000001000011" *) + (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000001000100" *) + (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000001000101" *) + (* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000001000110" *) + (* LC_LOW_BIT_POS_PROBE_OUT35 = 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*) + (* LC_PROBE_OUT_INIT_VAL_STRING = "292'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000010" *) + (* LC_PROBE_OUT_LOW_BIT_POS_STRING = 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*) + (* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000001000111110000000000000001" *) (* LC_TOTAL_PROBE_IN_WIDTH = "0" *) - (* LC_TOTAL_PROBE_OUT_WIDTH = "42" *) + (* LC_TOTAL_PROBE_OUT_WIDTH = "41" *) (* syn_noprune = "1" *) vio_manual_ctrl_vio_v3_0_20_vio inst (.clk(clk), @@ -2895,7 +2895,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all \G_PROBE_OUT[0].wr_probe_out_reg[0]_2 , Q, internal_cnt_rst); - output [2:0]probe_out0; + output [1:0]probe_out0; output [0:0]probe_out1; output [31:0]probe_out2; output [1:0]probe_out3; @@ -2931,9 +2931,8 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all wire [15:0]Bus_Data_out_int; (* async_reg = "true" *) wire Committ_1; (* async_reg = "true" *) wire Committ_2; + wire \G_PROBE_OUT[0].PROBE_OUT0_INST_n_2 ; wire \G_PROBE_OUT[0].PROBE_OUT0_INST_n_3 ; - wire \G_PROBE_OUT[0].PROBE_OUT0_INST_n_4 ; - wire \G_PROBE_OUT[0].PROBE_OUT0_INST_n_5 ; wire \G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0 ; wire \G_PROBE_OUT[0].wr_probe_out[0]_i_2_n_0 ; wire \G_PROBE_OUT[0].wr_probe_out[0]_i_6_n_0 ; @@ -2989,7 +2988,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all wire in0; wire internal_cnt_rst; wire out; - wire [2:0]probe_out0; + wire [1:0]probe_out0; wire [0:0]probe_out1; wire [31:0]probe_out2; wire [1:0]probe_out3; @@ -3017,9 +3016,9 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .Q(Committ_2), .R(1'b0)); vio_manual_ctrl_vio_v3_0_20_probe_out_one \G_PROBE_OUT[0].PROBE_OUT0_INST - (.D({\G_PROBE_OUT[0].PROBE_OUT0_INST_n_3 ,\G_PROBE_OUT[0].PROBE_OUT0_INST_n_4 ,\G_PROBE_OUT[0].PROBE_OUT0_INST_n_5 }), + (.D({\G_PROBE_OUT[0].PROBE_OUT0_INST_n_2 ,\G_PROBE_OUT[0].PROBE_OUT0_INST_n_3 }), .E(Committ_2), - .Q(Q[2:0]), + .Q(Q[1:0]), .SR(SR), .clk(clk), .out(out), @@ -3177,7 +3176,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .D(\G_PROBE_OUT[4].wr_probe_out[4]_i_1_n_0 ), .Q(wr_probe_out[4]), .R(\G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair24" *) + (* SOFT_HLUTNM = "soft_lutpair23" *) LUT3 #( .INIT(8'hB8)) \Probe_out_reg_int[0]_i_1 @@ -3193,9 +3192,9 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I2(\addr_p1_reg[2]_0 [1]), .I3(\G_PROBE_OUT[1].PROBE_OUT0_INST_n_1 ), .I4(\addr_p1_reg[2]_0 [0]), - .I5(\G_PROBE_OUT[0].PROBE_OUT0_INST_n_5 ), + .I5(\G_PROBE_OUT[0].PROBE_OUT0_INST_n_3 ), .O(\Probe_out_reg_int[0]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair28" *) + (* SOFT_HLUTNM = "soft_lutpair27" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[10]_i_1 @@ -3203,7 +3202,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[10]), .O(\Probe_out_reg_int[10]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair27" *) + (* SOFT_HLUTNM = "soft_lutpair26" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[11]_i_1 @@ -3211,7 +3210,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[11]), .O(\Probe_out_reg_int[11]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair25" *) + (* SOFT_HLUTNM = "soft_lutpair24" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[12]_i_1 @@ -3219,7 +3218,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[12]), .O(\Probe_out_reg_int[12]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair26" *) + (* SOFT_HLUTNM = "soft_lutpair25" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[13]_i_1 @@ -3227,7 +3226,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[13]), .O(\Probe_out_reg_int[13]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair26" *) + (* SOFT_HLUTNM = "soft_lutpair25" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[14]_i_1 @@ -3235,7 +3234,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[14]), .O(\Probe_out_reg_int[14]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair25" *) + (* SOFT_HLUTNM = "soft_lutpair24" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[15]_i_1 @@ -3243,7 +3242,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[15]), .O(\Probe_out_reg_int[15]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair24" *) + (* SOFT_HLUTNM = "soft_lutpair23" *) LUT3 #( .INIT(8'hB8)) \Probe_out_reg_int[1]_i_1 @@ -3257,18 +3256,17 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all (.I0(\G_PROBE_OUT[3].PROBE_OUT0_INST_n_2 ), .I1(Bus_Data_out_int[1]), .I2(\addr_p1_reg[2]_0 [1]), - .I3(\G_PROBE_OUT[0].PROBE_OUT0_INST_n_4 ), + .I3(\G_PROBE_OUT[0].PROBE_OUT0_INST_n_2 ), .I4(\addr_p1_reg[2]_0 [0]), .O(\Probe_out_reg_int[1]_i_2_n_0 )); - LUT6 #( - .INIT(64'h88888888B8BBB888)) + LUT5 #( + .INIT(32'h88B88888)) \Probe_out_reg_int[2]_i_1 (.I0(\G_PROBE_OUT[4].PROBE_OUT0_INST_n_5 ), .I1(\addr_p1_reg[2]_0 [2]), - .I2(Bus_Data_out_int[2]), - .I3(\addr_p1_reg[2]_0 [1]), - .I4(\G_PROBE_OUT[0].PROBE_OUT0_INST_n_3 ), - .I5(\addr_p1_reg[2]_0 [0]), + .I2(\addr_p1_reg[2]_0 [1]), + .I3(\addr_p1_reg[2]_0 [0]), + .I4(Bus_Data_out_int[2]), .O(probe_out_mem[2])); LUT5 #( .INIT(32'h88B88888)) @@ -3279,7 +3277,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I3(\addr_p1_reg[2]_0 [0]), .I4(Bus_Data_out_int[3]), .O(probe_out_mem[3])); - (* SOFT_HLUTNM = "soft_lutpair30" *) + (* SOFT_HLUTNM = "soft_lutpair29" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[4]_i_1 @@ -3287,7 +3285,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[4]), .O(\Probe_out_reg_int[4]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair30" *) + (* SOFT_HLUTNM = "soft_lutpair29" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[5]_i_1 @@ -3295,7 +3293,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[5]), .O(\Probe_out_reg_int[5]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair29" *) + (* SOFT_HLUTNM = "soft_lutpair28" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[6]_i_1 @@ -3303,7 +3301,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[6]), .O(\Probe_out_reg_int[6]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair29" *) + (* SOFT_HLUTNM = "soft_lutpair28" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[7]_i_1 @@ -3311,7 +3309,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[7]), .O(\Probe_out_reg_int[7]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair28" *) + (* SOFT_HLUTNM = "soft_lutpair27" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[8]_i_1 @@ -3319,7 +3317,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[8]), .O(\Probe_out_reg_int[8]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair27" *) + (* SOFT_HLUTNM = "soft_lutpair26" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[9]_i_1 @@ -3453,25 +3451,24 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one out, E, clk); - output [2:0]probe_out0; - output [2:0]D; + output [1:0]probe_out0; + output [1:0]D; input [0:0]SR; - input [2:0]Q; + input [1:0]Q; input [0:0]wr_probe_out; input out; input [0:0]E; input clk; - wire [2:0]D; + wire [1:0]D; wire [0:0]E; - wire [2:0]Q; + wire [1:0]Q; (* DIRECT_RESET *) wire [0:0]SR; wire clk; wire \data_int[0]_i_1_n_0 ; wire \data_int[1]_i_1_n_0 ; - wire \data_int[2]_i_1_n_0 ; wire out; - (* DONT_TOUCH *) wire [2:0]probe_out0; + (* DONT_TOUCH *) wire [1:0]probe_out0; wire [0:0]wr_probe_out; (* DONT_TOUCH *) @@ -3484,20 +3481,12 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one .R(SR)); (* DONT_TOUCH *) (* KEEP = "yes" *) - FDRE \Probe_out_reg[1] + FDSE \Probe_out_reg[1] (.C(clk), .CE(E), .D(D[1]), .Q(probe_out0[1]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[2] - (.C(clk), - .CE(E), - .D(D[2]), - .Q(probe_out0[2]), - .R(SR)); + .S(SR)); LUT3 #( .INIT(8'hB8)) \data_int[0]_i_1 @@ -3505,7 +3494,6 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one .I1(wr_probe_out), .I2(D[0]), .O(\data_int[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair14" *) LUT3 #( .INIT(8'hB8)) \data_int[1]_i_1 @@ -3513,32 +3501,18 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one .I1(wr_probe_out), .I2(D[1]), .O(\data_int[1]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT3 #( - .INIT(8'hB8)) - \data_int[2]_i_1 - (.I0(Q[2]), - .I1(wr_probe_out), - .I2(D[2]), - .O(\data_int[2]_i_1_n_0 )); FDRE \data_int_reg[0] (.C(out), .CE(1'b1), .D(\data_int[0]_i_1_n_0 ), .Q(D[0]), .R(SR)); - FDRE \data_int_reg[1] + FDSE \data_int_reg[1] (.C(out), .CE(1'b1), .D(\data_int[1]_i_1_n_0 ), .Q(D[1]), - .R(SR)); - FDRE \data_int_reg[2] - (.C(out), - .CE(1'b1), - .D(\data_int[2]_i_1_n_0 ), - .Q(D[2]), - .R(SR)); + .S(SR)); endmodule (* ORIG_REF_NAME = "vio_v3_0_20_probe_out_one" *) @@ -3659,7 +3633,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 wire s_den_o; wire s_dwe_o; - (* SOFT_HLUTNM = "soft_lutpair22" *) + (* SOFT_HLUTNM = "soft_lutpair21" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[0]_i_1 @@ -3667,7 +3641,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [0]), .O(\Bus_Data_out_int[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair17" *) + (* SOFT_HLUTNM = "soft_lutpair16" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[10]_i_1 @@ -3675,7 +3649,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [10]), .O(\Bus_Data_out_int[10]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair17" *) + (* SOFT_HLUTNM = "soft_lutpair16" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[11]_i_1 @@ -3683,7 +3657,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [11]), .O(\Bus_Data_out_int[11]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair16" *) + (* SOFT_HLUTNM = "soft_lutpair15" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[12]_i_1 @@ -3691,7 +3665,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [12]), .O(\Bus_Data_out_int[12]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair16" *) + (* SOFT_HLUTNM = "soft_lutpair15" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[13]_i_1 @@ -3699,7 +3673,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [13]), .O(\Bus_Data_out_int[13]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair15" *) + (* SOFT_HLUTNM = "soft_lutpair14" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[14]_i_1 @@ -3707,7 +3681,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [14]), .O(\Bus_Data_out_int[14]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair15" *) + (* SOFT_HLUTNM = "soft_lutpair14" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[15]_i_1 @@ -3715,7 +3689,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [15]), .O(\Bus_Data_out_int[15]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair22" *) + (* SOFT_HLUTNM = "soft_lutpair21" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[1]_i_1 @@ -3723,7 +3697,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [1]), .O(\Bus_Data_out_int[1]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair21" *) + (* SOFT_HLUTNM = "soft_lutpair20" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[2]_i_1 @@ -3731,7 +3705,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [2]), .O(\Bus_Data_out_int[2]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair21" *) + (* SOFT_HLUTNM = "soft_lutpair20" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[3]_i_1 @@ -3739,7 +3713,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [3]), .O(\Bus_Data_out_int[3]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair20" *) + (* SOFT_HLUTNM = "soft_lutpair19" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[4]_i_1 @@ -3747,7 +3721,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [4]), .O(\Bus_Data_out_int[4]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair20" *) + (* SOFT_HLUTNM = "soft_lutpair19" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[5]_i_1 @@ -3755,7 +3729,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [5]), .O(\Bus_Data_out_int[5]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair19" *) + (* SOFT_HLUTNM = "soft_lutpair18" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[6]_i_1 @@ -3763,7 +3737,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [6]), .O(\Bus_Data_out_int[6]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair19" *) + (* SOFT_HLUTNM = "soft_lutpair18" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[7]_i_1 @@ -3771,7 +3745,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [7]), .O(\Bus_Data_out_int[7]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair18" *) + (* SOFT_HLUTNM = "soft_lutpair17" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[8]_i_1 @@ -3779,7 +3753,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [8]), .O(\Bus_Data_out_int[8]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair18" *) + (* SOFT_HLUTNM = "soft_lutpair17" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[9]_i_1 @@ -4448,7 +4422,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized2 .D(D[1]), .Q(probe_out3[1]), .S(SR)); - (* SOFT_HLUTNM = "soft_lutpair23" *) + (* SOFT_HLUTNM = "soft_lutpair22" *) LUT3 #( .INIT(8'hB8)) \data_int[0]_i_1 @@ -4456,7 +4430,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized2 .I1(wr_probe_out), .I2(D[0]), .O(\data_int[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair23" *) + (* SOFT_HLUTNM = "soft_lutpair22" *) LUT3 #( .INIT(8'hB8)) \data_int[1]_i_1 @@ -4587,7 +4561,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_width wire rd_probe_out_width; wire s_rst_o; - (* SOFT_HLUTNM = "soft_lutpair31" *) + (* SOFT_HLUTNM = "soft_lutpair30" *) LUT5 #( .INIT(32'h0000001A)) \addr_count[0]_i_1 @@ -4597,7 +4571,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_width .I3(s_rst_o), .I4(internal_cnt_rst), .O(\addr_count[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair31" *) + (* SOFT_HLUTNM = "soft_lutpair30" *) LUT5 #( .INIT(32'h0000002C)) \addr_count[1]_i_1 @@ -4619,20 +4593,20 @@ module vio_manual_ctrl_vio_v3_0_20_probe_width .D(\addr_count[1]_i_1_n_0 ), .Q(addr_count[1]), .R(1'b0)); - LUT2 #( - .INIT(4'h6)) - \probe_width_int[0]_i_1 - (.I0(addr_count[0]), - .I1(addr_count[1]), - .O(probe_width_mem[0])); - (* SOFT_HLUTNM = "soft_lutpair32" *) LUT2 #( .INIT(4'h7)) - \probe_width_int[1]_i_1 + \probe_width_int[0]_i_1 (.I0(addr_count[1]), .I1(addr_count[0]), + .O(probe_width_mem[0])); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT2 #( + .INIT(4'h6)) + \probe_width_int[1]_i_1 + (.I0(addr_count[0]), + .I1(addr_count[1]), .O(probe_width_mem[1])); - (* SOFT_HLUTNM = "soft_lutpair32" *) + (* SOFT_HLUTNM = "soft_lutpair31" *) LUT2 #( .INIT(4'h2)) \probe_width_int[8]_i_1 @@ -4751,7 +4725,7 @@ endmodule (* C_PROBE_IN92_WIDTH = "1" *) (* C_PROBE_IN93_WIDTH = "1" *) (* C_PROBE_IN94_WIDTH = "1" *) (* C_PROBE_IN95_WIDTH = "1" *) (* C_PROBE_IN96_WIDTH = "1" *) (* C_PROBE_IN97_WIDTH = "1" *) (* C_PROBE_IN98_WIDTH = "1" *) (* C_PROBE_IN99_WIDTH = "1" *) (* C_PROBE_IN9_WIDTH = "1" *) -(* C_PROBE_OUT0_INIT_VAL = "3'b000" *) (* C_PROBE_OUT0_WIDTH = "3" *) (* C_PROBE_OUT100_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT0_INIT_VAL = "2'b10" *) (* C_PROBE_OUT0_WIDTH = "2" *) (* C_PROBE_OUT100_INIT_VAL = "1'b0" *) (* C_PROBE_OUT100_WIDTH = "1" *) (* C_PROBE_OUT101_INIT_VAL = "1'b0" *) (* C_PROBE_OUT101_WIDTH = "1" *) (* C_PROBE_OUT102_INIT_VAL = "1'b0" *) (* C_PROBE_OUT102_WIDTH = "1" *) (* C_PROBE_OUT103_INIT_VAL = "1'b0" *) (* C_PROBE_OUT103_WIDTH = "1" *) (* C_PROBE_OUT104_INIT_VAL = "1'b0" *) (* C_PROBE_OUT104_WIDTH = "1" *) @@ -4923,180 +4897,180 @@ endmodule (* C_PROBE_OUT98_WIDTH = "1" *) (* C_PROBE_OUT99_INIT_VAL = "1'b0" *) (* C_PROBE_OUT99_WIDTH = "1" *) (* C_PROBE_OUT9_INIT_VAL = "1'b0" *) (* C_PROBE_OUT9_WIDTH = "1" *) (* C_USE_TEST_REG = "1" *) (* C_XDEVICEFAMILY = "kintex7" *) (* C_XLNX_HW_PROBE_INFO = "DEFAULT" *) (* C_XSDB_SLAVE_TYPE = "33" *) -(* DowngradeIPIdentifiedWarnings = "yes" *) (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000010001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000010001010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000010001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000010001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000010001101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000010001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000010001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000010010000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000010010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000010010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000110000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000010010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000010010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000010010101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000010010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000010010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000010011000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000010011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000010011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000010011011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000010011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000010011101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000010011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000010011111" *) (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000010100000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000010100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000010100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000010100011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000010100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010100110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010101000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010101011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010101110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000110011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010110011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010110110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010111001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010111011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010111110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000011000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000011000001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000011000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000011000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000011000100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000011000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000011000110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000011000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000011001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000011001001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000011001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000011001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000011001100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000011001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000011001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000110110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000011001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000011010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000011010001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000011010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000011010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000011010100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000011010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000011010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000011010111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000011011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000011011001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000011011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000011011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000011011100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000011011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000011011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000011011111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000011100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000011100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000011100010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000011100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000011100100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011100111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011101010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000100011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011101110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011110001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011110100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000111010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011111001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011111100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011111111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000100000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000100000001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000100000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000100000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000100000100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000100000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000100000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000100000111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000100001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000100001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000100001010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000100001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000100001100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000100001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000100001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000100001111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000100010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000100010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000100010010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000100010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000100010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000111101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000100010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000100010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000100010111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000100011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000100011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000100011010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000100011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000100011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000100011101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000100011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000100011111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000100100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000100100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000100100010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000100100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000100100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000111111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000001000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000001000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000001000010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000001000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000001000100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000001000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000001000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000001000111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000001001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000001001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000001001010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000001001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000001001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000101001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000001001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000001001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000001001111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000001010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000001010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000001010010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000001010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000001010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000001010101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000001010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000001010111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000001011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000001011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000001011010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000001011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000001011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000001011101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000001011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000001011111" *) (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000001100000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000001100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000001100010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000001100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000001100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001100101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001101000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000101100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001101101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001110000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001110011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001110101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001111000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001111011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001111110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000010000000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000010000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000010000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000010000011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000010000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000010000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000010000110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000010000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000010001000" *) (* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *) -(* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000011" *) (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000101111" *) (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000010001001" *) -(* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000010001010" *) (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000010001011" *) (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000010001100" *) -(* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000010001101" *) (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000010001110" *) (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000010001111" *) -(* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000010010000" *) (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000010010001" *) (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000010010010" *) -(* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000110000" *) (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000010010011" *) (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000010010100" *) -(* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000010010101" *) (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000010010110" *) (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000010010111" *) -(* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000010011000" *) (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000010011001" *) (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000010011010" *) -(* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000010011011" *) (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000010011100" *) (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000110001" *) -(* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000010011101" *) (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000010011110" *) (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000010011111" *) -(* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000010100000" *) (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000010100001" *) (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000010100010" *) -(* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000010100011" *) (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000010100100" *) (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010100101" *) -(* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010100110" *) (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000110010" *) (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010100111" *) -(* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010101000" *) (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010101001" *) (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010101010" *) -(* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010101011" *) (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010101100" *) (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010101101" *) -(* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010101110" *) (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010101111" *) (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010110000" *) -(* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000110011" *) (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010110001" *) (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010110010" *) -(* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010110011" *) (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010110100" *) (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010110101" *) -(* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010110110" *) (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010110111" *) (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010111000" *) -(* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010111001" *) (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010111010" *) (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000110100" *) -(* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010111011" *) (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010111100" *) (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010111101" *) -(* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010111110" *) (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010111111" *) (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000011000000" *) -(* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000011000001" *) (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000011000010" *) (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000011000011" *) -(* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000011000100" *) (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000110101" *) (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000011000101" *) -(* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000011000110" *) (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000011000111" *) (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000011001000" *) -(* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000011001001" *) (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000011001010" *) (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000011001011" *) -(* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000011001100" *) (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000011001101" *) (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000011001110" *) -(* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000110110" *) (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000011001111" *) (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000011010000" *) -(* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000011010001" *) (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000011010010" *) (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000011010011" *) -(* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000011010100" *) (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000011010101" *) (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000011010110" *) -(* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000011010111" *) (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000011011000" *) (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000110111" *) -(* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000011011001" *) (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000011011010" *) (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000011011011" *) -(* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000011011100" *) (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000011011101" *) (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000011011110" *) -(* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000011011111" *) (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000011100000" *) (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000011100001" *) -(* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000011100010" *) (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000111000" *) (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000011100011" *) -(* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000011100100" *) (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011100101" *) (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011100110" *) -(* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011100111" *) (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011101000" *) (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011101001" *) -(* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011101010" *) (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011101011" *) (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011101100" *) -(* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000100" *) (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000111001" *) (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011101101" *) -(* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011101110" *) (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011101111" *) (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011110000" *) -(* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011110001" *) (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011110010" *) (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011110011" *) -(* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011110100" *) (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011110101" *) (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011110110" *) -(* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000111010" *) (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011110111" *) (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011111000" *) -(* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011111001" *) (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011111010" *) (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011111011" *) -(* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011111100" *) (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011111101" *) (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011111110" *) -(* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011111111" *) (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000100000000" *) (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000111011" *) -(* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000100000001" *) (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000100000010" *) (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000100000011" *) -(* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000100000100" *) (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000100000101" *) (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000100000110" *) -(* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000100000111" *) (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000100001000" *) (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000100001001" *) -(* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000100001010" *) (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000111100" *) (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000100001011" *) -(* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000100001100" *) (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000100001101" *) (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000100001110" *) -(* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000100001111" *) (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000100010000" *) (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000100010001" *) -(* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000100010010" *) (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000100010011" *) (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000100010100" *) -(* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000111101" *) (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000100010101" *) (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000100010110" *) -(* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000100010111" *) (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000100011000" *) (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000100011001" *) -(* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000100011010" *) (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000100011011" *) (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000100011100" *) -(* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000100011101" *) (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000100011110" *) (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000111110" *) -(* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000100011111" *) (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000100100000" *) (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000100100001" *) -(* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000100100010" *) (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000100100011" *) (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000100100100" *) -(* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000111111" *) (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000001000000" *) (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000001000001" *) -(* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000001000010" *) (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000100100" *) (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000001000011" *) -(* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000001000100" *) (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000001000101" *) (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000001000110" *) -(* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000001000111" *) (* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000001001000" *) (* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000001001001" *) -(* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000001001010" *) (* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000001001011" *) (* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000001001100" *) -(* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000100110" *) (* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000001001101" *) (* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000001001110" *) -(* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000001001111" *) (* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000001010000" *) (* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000001010001" *) -(* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000001010010" *) (* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000001010011" *) (* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000001010100" *) -(* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000001010101" *) (* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000001010110" *) (* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000101010" *) -(* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000001010111" *) (* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000001011000" *) (* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000001011001" *) -(* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000001011010" *) (* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000001011011" *) (* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000001011100" *) -(* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000001011101" *) (* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000001011110" *) (* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000001011111" *) -(* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000001100000" *) (* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000101011" *) (* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000001100001" *) -(* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000001100010" *) (* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000001100011" *) (* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000001100100" *) -(* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001100101" *) (* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001100110" *) (* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001100111" *) -(* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001101000" *) (* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001101001" *) (* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001101010" *) -(* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000101100" *) (* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001101011" *) (* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001101100" *) -(* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001101101" *) (* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001101110" *) (* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001101111" *) -(* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001110000" *) (* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001110001" *) (* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001110010" *) -(* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001110011" *) (* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001110100" *) (* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000101101" *) -(* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001110101" *) (* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001110110" *) (* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001110111" *) -(* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001111000" *) (* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001111001" *) (* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001111010" *) -(* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001111011" *) (* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001111100" *) (* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001111101" *) -(* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001111110" *) (* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000101110" *) (* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001111111" *) -(* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000010000000" *) (* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000010000001" *) (* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000010000010" *) -(* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000010000011" *) (* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000010000100" *) (* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000010000101" *) -(* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000010000110" *) (* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000010000111" *) (* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000010001000" *) -(* LC_PROBE_IN_WIDTH_STRING = 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*) (* LC_PROBE_OUT_HIGH_BIT_POS_STRING = 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*) (* LC_PROBE_OUT_INIT_VAL_STRING = "293'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000" *) -(* LC_PROBE_OUT_LOW_BIT_POS_STRING = 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*) (* LC_PROBE_OUT_WIDTH_STRING = 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*) (* LC_TOTAL_PROBE_IN_WIDTH = "0" *) -(* LC_TOTAL_PROBE_OUT_WIDTH = "42" *) (* ORIG_REF_NAME = "vio_v3_0_20_vio" *) (* dont_touch = "true" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000010001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000010001001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000010001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000010001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000010001100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000010001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000010001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000010001111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000010010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000010010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000101111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000010010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000010010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000010010100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000010010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000010010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000010010111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000010011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000010011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000010011010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000010011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000010011100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000010011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000010011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000010011111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000010100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000010100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000010100010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000010100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010100101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010100111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010101010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010101101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000110010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010110010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010110101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010111000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010111010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010111101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000011000000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000011000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000011000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000011000011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000011000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000011000101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000011000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000011000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000011001000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000011001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000011001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000011001011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000011001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000011001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000110101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000011001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000011001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000011010000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000011010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000011010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000011010011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000011010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000011010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000011010110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000011010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000011011000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000011011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000011011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000011011011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000011011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000011011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000011011110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000011011111" *) (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000011100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000011100001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000011100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000011100011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011100110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011101001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000100010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011101101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011110000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011110011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000111001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011111000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011111011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011111110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000100000000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000100000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000100000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000100000011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000100000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000100000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000100000110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000100000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000100001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000100001001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000100001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000100001011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000100001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000100001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000100001110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000100001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000100010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000100010001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000100010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000100010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000111100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000100010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000100010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000100010110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000100010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000100011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000100011001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000100011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000100011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000100011100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000100011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000100011110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000100011111" *) (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000100100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000100100001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000100100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000100100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000111110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000001000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000001000001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000001000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000001000011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000001000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000001000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000001000110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000001000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000001001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000001001001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000001001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000001001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000101000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000001001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000001001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000001001110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000001001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000001010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000001010001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000001010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000001010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000001010100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000001010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000001010110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000001010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000001011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000001011001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000001011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000001011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000001011100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000001011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000001011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000001011111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000001100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000001100001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000001100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000001100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001100100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001100111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000101011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001101100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001101111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001110010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001110100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001110111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001111010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001111101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001111111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000010000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000010000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000010000010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000010000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000010000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000010000101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000010000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000010000111" *) (* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *) +(* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000010" *) (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000101110" *) (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000010001000" *) +(* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000010001001" *) (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000010001010" *) (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000010001011" *) +(* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000010001100" *) (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000010001101" *) (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000010001110" *) +(* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000010001111" *) (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000010010000" *) (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000010010001" *) +(* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000101111" *) (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000010010010" *) (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000010010011" *) +(* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000010010100" *) (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000010010101" *) (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000010010110" *) +(* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000010010111" *) (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000010011000" *) (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000010011001" *) +(* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000010011010" *) (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000010011011" *) (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000110000" *) +(* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000010011100" *) (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000010011101" *) (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000010011110" *) +(* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000010011111" *) (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000010100000" *) (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000010100001" *) +(* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000010100010" *) (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000010100011" *) (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010100100" *) +(* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010100101" *) (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000110001" *) (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010100110" *) +(* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010100111" *) (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010101000" *) (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010101001" *) +(* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010101010" *) (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010101011" *) (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010101100" *) +(* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010101101" *) (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010101110" *) (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010101111" *) +(* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000110010" *) (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010110000" *) (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010110001" *) +(* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010110010" *) (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010110011" *) (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010110100" *) +(* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010110101" *) (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010110110" *) (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010110111" *) +(* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010111000" *) (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010111001" *) (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000110011" *) +(* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010111010" *) (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010111011" *) (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010111100" *) +(* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010111101" *) (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010111110" *) (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010111111" *) +(* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000011000000" *) (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000011000001" *) (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000011000010" *) +(* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000011000011" *) (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000110100" *) (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000011000100" *) +(* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000011000101" *) (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000011000110" *) (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000011000111" *) +(* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000011001000" *) (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000011001001" *) (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000011001010" *) +(* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000011001011" *) (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000011001100" *) (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000011001101" *) +(* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000110101" *) (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000011001110" *) (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000011001111" *) +(* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000011010000" *) (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000011010001" *) (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000011010010" *) +(* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000011010011" *) (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000011010100" *) (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000011010101" *) +(* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000011010110" *) (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000011010111" *) (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000110110" *) +(* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000011011000" *) (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000011011001" *) (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000011011010" *) +(* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000011011011" *) (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000011011100" *) (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000011011101" *) +(* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000011011110" *) (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000011011111" *) (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000011100000" *) +(* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000011100001" *) (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000110111" *) (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000011100010" *) +(* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000011100011" *) (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011100100" *) (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011100101" *) +(* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011100110" *) (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011100111" *) (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011101000" *) +(* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011101001" *) (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011101010" *) (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011101011" *) +(* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000011" *) (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000111000" *) (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011101100" *) +(* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011101101" *) (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011101110" *) (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011101111" *) +(* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011110000" *) (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011110001" *) (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011110010" *) +(* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011110011" *) (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011110100" *) (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011110101" *) +(* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000111001" *) (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011110110" *) (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011110111" *) +(* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011111000" *) (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011111001" *) (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011111010" *) +(* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011111011" *) (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011111100" *) (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011111101" *) +(* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011111110" *) (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011111111" *) (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000111010" *) +(* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000100000000" *) (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000100000001" *) (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000100000010" *) +(* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000100000011" *) (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000100000100" *) (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000100000101" *) +(* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000100000110" *) (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000100000111" *) (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000100001000" *) +(* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000100001001" *) (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000111011" *) (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000100001010" *) +(* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000100001011" *) (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000100001100" *) (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000100001101" *) +(* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000100001110" *) (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000100001111" *) (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000100010000" *) +(* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000100010001" *) (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000100010010" *) (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000100010011" *) +(* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000111100" *) (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000100010100" *) (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000100010101" *) +(* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000100010110" *) (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000100010111" *) (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000100011000" *) +(* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000100011001" *) (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000100011010" *) (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000100011011" *) +(* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000100011100" *) (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000100011101" *) (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000111101" *) +(* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000100011110" *) (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000100011111" *) (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000100100000" *) +(* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000100100001" *) (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000100100010" *) (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000100100011" *) +(* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000111110" *) (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000111111" *) (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000001000000" *) +(* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000001000001" *) (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000100011" *) (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000001000010" *) +(* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000001000011" *) (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000001000100" *) (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000001000101" *) +(* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000001000110" *) (* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000001000111" *) (* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000001001000" *) +(* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000001001001" *) (* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000001001010" *) (* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000001001011" *) +(* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000100101" *) (* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000001001100" *) (* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000001001101" *) +(* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000001001110" *) (* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000001001111" *) (* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000001010000" *) +(* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000001010001" *) (* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000001010010" *) (* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000001010011" *) +(* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000001010100" *) (* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000001010101" *) (* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000101001" *) +(* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000001010110" *) (* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000001010111" *) (* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000001011000" *) +(* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000001011001" *) (* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000001011010" *) (* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000001011011" *) +(* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000001011100" *) (* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000001011101" *) (* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000001011110" *) +(* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000001011111" *) (* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000101010" *) (* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000001100000" *) +(* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000001100001" *) (* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000001100010" *) (* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000001100011" *) +(* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001100100" *) (* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001100101" *) (* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001100110" *) +(* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001100111" *) (* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001101000" *) (* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001101001" *) +(* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000101011" *) (* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001101010" *) (* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001101011" *) +(* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001101100" *) (* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001101101" *) (* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001101110" *) +(* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001101111" *) (* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001110000" *) (* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001110001" *) +(* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001110010" *) (* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001110011" *) (* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000101100" *) +(* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001110100" *) (* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001110101" *) (* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001110110" *) +(* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001110111" *) (* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001111000" *) (* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001111001" *) +(* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001111010" *) (* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001111011" *) (* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001111100" *) +(* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001111101" *) (* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000101101" *) (* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001111110" *) +(* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001111111" *) (* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000010000000" *) (* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000010000001" *) +(* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000010000010" *) (* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000010000011" *) (* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000010000100" *) +(* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000010000101" *) (* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000010000110" *) (* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000010000111" *) +(* LC_PROBE_IN_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* LC_PROBE_OUT_HIGH_BIT_POS_STRING = "4096'b0000000100100011000000010010001000000001001000010000000100100000000000010001111100000001000111100000000100011101000000010001110000000001000110110000000100011010000000010001100100000001000110000000000100010111000000010001011000000001000101010000000100010100000000010001001100000001000100100000000100010001000000010001000000000001000011110000000100001110000000010000110100000001000011000000000100001011000000010000101000000001000010010000000100001000000000010000011100000001000001100000000100000101000000010000010000000001000000110000000100000010000000010000000100000001000000000000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100100000000000010001000000000000000100000000000000001" *) (* LC_PROBE_OUT_INIT_VAL_STRING = "292'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000010" *) +(* LC_PROBE_OUT_LOW_BIT_POS_STRING = "4096'b0000000100100011000000010010001000000001001000010000000100100000000000010001111100000001000111100000000100011101000000010001110000000001000110110000000100011010000000010001100100000001000110000000000100010111000000010001011000000001000101010000000100010100000000010001001100000001000100100000000100010001000000010001000000000001000011110000000100001110000000010000110100000001000011000000000100001011000000010000101000000001000010010000000100001000000000010000011100000001000001100000000100000101000000010000010000000001000000110000000100000010000000010000000100000001000000000000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001001010000000000100011000000000000001100000000000000100000000000000000" *) (* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000001000111110000000000000001" *) (* LC_TOTAL_PROBE_IN_WIDTH = "0" *) +(* LC_TOTAL_PROBE_OUT_WIDTH = "41" *) (* ORIG_REF_NAME = "vio_v3_0_20_vio" *) (* dont_touch = "true" *) module vio_manual_ctrl_vio_v3_0_20_vio (clk, probe_in0, @@ -5872,7 +5846,7 @@ module vio_manual_ctrl_vio_v3_0_20_vio input [0:0]probe_in255; (* dont_touch = "true" *) input [36:0]sl_iport0; (* dont_touch = "true" *) output [16:0]sl_oport0; - output [2:0]probe_out0; + output [1:0]probe_out0; output [0:0]probe_out1; output [31:0]probe_out2; output [1:0]probe_out3; @@ -6133,7 +6107,8 @@ module vio_manual_ctrl_vio_v3_0_20_vio wire DECODER_INST_n_5; wire DECODER_INST_n_6; wire DECODER_INST_n_7; - wire PROBE_OUT_ALL_INST_n_42; + wire PROBE_OUT_ALL_INST_n_41; + wire PROBE_OUT_ALL_INST_n_45; wire PROBE_OUT_ALL_INST_n_46; wire PROBE_OUT_ALL_INST_n_47; wire PROBE_OUT_ALL_INST_n_48; @@ -6149,7 +6124,6 @@ module vio_manual_ctrl_vio_v3_0_20_vio wire PROBE_OUT_ALL_INST_n_58; wire PROBE_OUT_ALL_INST_n_59; wire PROBE_OUT_ALL_INST_n_60; - wire PROBE_OUT_ALL_INST_n_61; wire [16:0]bus_addr; (* DONT_TOUCH *) wire bus_clk; wire \bus_data_int_reg_n_0_[0] ; @@ -6178,7 +6152,7 @@ module vio_manual_ctrl_vio_v3_0_20_vio wire committ; wire internal_cnt_rst; wire p_0_in; - wire [2:0]probe_out0; + wire [1:0]probe_out0; wire [0:0]probe_out1; wire [31:0]probe_out2; wire [1:0]probe_out3; @@ -6441,29 +6415,29 @@ module vio_manual_ctrl_vio_v3_0_20_vio assign probe_out98[0] = \ ; assign probe_out99[0] = \ ; vio_manual_ctrl_vio_v3_0_20_decoder DECODER_INST - (.\Bus_data_out_reg[10]_0 (PROBE_OUT_ALL_INST_n_55), - .\Bus_data_out_reg[11]_0 (PROBE_OUT_ALL_INST_n_54), - .\Bus_data_out_reg[12]_0 (PROBE_OUT_ALL_INST_n_53), - .\Bus_data_out_reg[13]_0 (PROBE_OUT_ALL_INST_n_52), - .\Bus_data_out_reg[14]_0 (PROBE_OUT_ALL_INST_n_51), + (.\Bus_data_out_reg[10]_0 (PROBE_OUT_ALL_INST_n_54), + .\Bus_data_out_reg[11]_0 (PROBE_OUT_ALL_INST_n_53), + .\Bus_data_out_reg[12]_0 (PROBE_OUT_ALL_INST_n_52), + .\Bus_data_out_reg[13]_0 (PROBE_OUT_ALL_INST_n_51), + .\Bus_data_out_reg[14]_0 (PROBE_OUT_ALL_INST_n_50), .\Bus_data_out_reg[15]_0 (bus_do), - .\Bus_data_out_reg[15]_1 (PROBE_OUT_ALL_INST_n_50), + .\Bus_data_out_reg[15]_1 (PROBE_OUT_ALL_INST_n_49), .\Bus_data_out_reg[3]_0 ({probe_width_int[8],probe_width_int[1:0]}), - .\Bus_data_out_reg[4]_0 (PROBE_OUT_ALL_INST_n_61), - .\Bus_data_out_reg[5]_0 (PROBE_OUT_ALL_INST_n_60), - .\Bus_data_out_reg[6]_0 (PROBE_OUT_ALL_INST_n_59), - .\Bus_data_out_reg[7]_0 (PROBE_OUT_ALL_INST_n_58), - .\Bus_data_out_reg[8]_0 (PROBE_OUT_ALL_INST_n_57), - .\Bus_data_out_reg[9]_0 (PROBE_OUT_ALL_INST_n_56), + .\Bus_data_out_reg[4]_0 (PROBE_OUT_ALL_INST_n_60), + .\Bus_data_out_reg[5]_0 (PROBE_OUT_ALL_INST_n_59), + .\Bus_data_out_reg[6]_0 (PROBE_OUT_ALL_INST_n_58), + .\Bus_data_out_reg[7]_0 (PROBE_OUT_ALL_INST_n_57), + .\Bus_data_out_reg[8]_0 (PROBE_OUT_ALL_INST_n_56), + .\Bus_data_out_reg[9]_0 (PROBE_OUT_ALL_INST_n_55), .\G_PROBE_OUT[0].wr_probe_out[0]_i_3_0 (DECODER_INST_n_7), .\G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 (DECODER_INST_n_5), - .Q({PROBE_OUT_ALL_INST_n_46,PROBE_OUT_ALL_INST_n_47,PROBE_OUT_ALL_INST_n_48,PROBE_OUT_ALL_INST_n_49}), + .Q({PROBE_OUT_ALL_INST_n_45,PROBE_OUT_ALL_INST_n_46,PROBE_OUT_ALL_INST_n_47,PROBE_OUT_ALL_INST_n_48}), .SR(clear), .in0(committ), .internal_cnt_rst(internal_cnt_rst), .out(bus_clk), .\probe_out_modified_reg[15]_0 ({\bus_data_int_reg_n_0_[15] ,\bus_data_int_reg_n_0_[14] ,\bus_data_int_reg_n_0_[13] ,\bus_data_int_reg_n_0_[12] ,\bus_data_int_reg_n_0_[11] ,\bus_data_int_reg_n_0_[10] ,\bus_data_int_reg_n_0_[9] ,\bus_data_int_reg_n_0_[8] ,\bus_data_int_reg_n_0_[7] ,\bus_data_int_reg_n_0_[6] ,\bus_data_int_reg_n_0_[5] ,\bus_data_int_reg_n_0_[4] ,\bus_data_int_reg_n_0_[3] ,\bus_data_int_reg_n_0_[2] ,p_0_in,\bus_data_int_reg_n_0_[0] }), - .\rd_en_reg[6]_0 (PROBE_OUT_ALL_INST_n_42), + .\rd_en_reg[6]_0 (PROBE_OUT_ALL_INST_n_41), .rd_probe_out_width(rd_probe_out_width), .s_daddr_o(bus_addr), .s_den_o(bus_den), @@ -6478,22 +6452,22 @@ module vio_manual_ctrl_vio_v3_0_20_vio (.\G_PROBE_OUT[0].wr_probe_out_reg[0]_0 (DECODER_INST_n_7), .\G_PROBE_OUT[0].wr_probe_out_reg[0]_1 (DECODER_INST_n_5), .\G_PROBE_OUT[0].wr_probe_out_reg[0]_2 (DECODER_INST_n_6), - .\Probe_out_reg_int_reg[10]_0 (PROBE_OUT_ALL_INST_n_55), - .\Probe_out_reg_int_reg[11]_0 (PROBE_OUT_ALL_INST_n_54), - .\Probe_out_reg_int_reg[12]_0 (PROBE_OUT_ALL_INST_n_53), - .\Probe_out_reg_int_reg[13]_0 (PROBE_OUT_ALL_INST_n_52), - .\Probe_out_reg_int_reg[14]_0 (PROBE_OUT_ALL_INST_n_51), - .\Probe_out_reg_int_reg[15]_0 (PROBE_OUT_ALL_INST_n_50), - .\Probe_out_reg_int_reg[3]_0 ({PROBE_OUT_ALL_INST_n_46,PROBE_OUT_ALL_INST_n_47,PROBE_OUT_ALL_INST_n_48,PROBE_OUT_ALL_INST_n_49}), - .\Probe_out_reg_int_reg[4]_0 (PROBE_OUT_ALL_INST_n_61), - .\Probe_out_reg_int_reg[5]_0 (PROBE_OUT_ALL_INST_n_60), - .\Probe_out_reg_int_reg[6]_0 (PROBE_OUT_ALL_INST_n_59), - .\Probe_out_reg_int_reg[7]_0 (PROBE_OUT_ALL_INST_n_58), - .\Probe_out_reg_int_reg[8]_0 (PROBE_OUT_ALL_INST_n_57), - .\Probe_out_reg_int_reg[9]_0 (PROBE_OUT_ALL_INST_n_56), + .\Probe_out_reg_int_reg[10]_0 (PROBE_OUT_ALL_INST_n_54), + .\Probe_out_reg_int_reg[11]_0 (PROBE_OUT_ALL_INST_n_53), + .\Probe_out_reg_int_reg[12]_0 (PROBE_OUT_ALL_INST_n_52), + .\Probe_out_reg_int_reg[13]_0 (PROBE_OUT_ALL_INST_n_51), + .\Probe_out_reg_int_reg[14]_0 (PROBE_OUT_ALL_INST_n_50), + .\Probe_out_reg_int_reg[15]_0 (PROBE_OUT_ALL_INST_n_49), + .\Probe_out_reg_int_reg[3]_0 ({PROBE_OUT_ALL_INST_n_45,PROBE_OUT_ALL_INST_n_46,PROBE_OUT_ALL_INST_n_47,PROBE_OUT_ALL_INST_n_48}), + .\Probe_out_reg_int_reg[4]_0 (PROBE_OUT_ALL_INST_n_60), + .\Probe_out_reg_int_reg[5]_0 (PROBE_OUT_ALL_INST_n_59), + .\Probe_out_reg_int_reg[6]_0 (PROBE_OUT_ALL_INST_n_58), + .\Probe_out_reg_int_reg[7]_0 (PROBE_OUT_ALL_INST_n_57), + .\Probe_out_reg_int_reg[8]_0 (PROBE_OUT_ALL_INST_n_56), + .\Probe_out_reg_int_reg[9]_0 (PROBE_OUT_ALL_INST_n_55), .Q({\bus_data_int_reg_n_0_[15] ,\bus_data_int_reg_n_0_[14] ,\bus_data_int_reg_n_0_[13] ,\bus_data_int_reg_n_0_[12] ,\bus_data_int_reg_n_0_[11] ,\bus_data_int_reg_n_0_[10] ,\bus_data_int_reg_n_0_[9] ,\bus_data_int_reg_n_0_[8] ,\bus_data_int_reg_n_0_[7] ,\bus_data_int_reg_n_0_[6] ,\bus_data_int_reg_n_0_[5] ,\bus_data_int_reg_n_0_[4] ,\bus_data_int_reg_n_0_[3] ,\bus_data_int_reg_n_0_[2] ,p_0_in,\bus_data_int_reg_n_0_[0] }), .SR(clear), - .\addr_count[1]_i_5 (PROBE_OUT_ALL_INST_n_42), + .\addr_count[1]_i_5 (PROBE_OUT_ALL_INST_n_41), .\addr_p1_reg[2]_0 (xsdb_addr_2_0_p1), .clk(clk), .in0(committ), diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.vhdl index 8626d906..bfccd60b 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.vhdl +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:34:28 2023 +-- Date : Tue Mar 21 22:54:43 2023 -- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl +-- D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl -- Design : vio_manual_ctrl -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -917,10 +917,10 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity vio_manual_ctrl_vio_v3_0_20_probe_out_one is port ( - probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); - D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + D : out STD_LOGIC_VECTOR ( 1 downto 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); wr_probe_out : in STD_LOGIC_VECTOR ( 0 to 0 ); \out\ : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); @@ -931,23 +931,17 @@ entity vio_manual_ctrl_vio_v3_0_20_probe_out_one is end vio_manual_ctrl_vio_v3_0_20_probe_out_one; architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_probe_out_one is - signal \^d\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^d\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \data_int[0]_i_1_n_0\ : STD_LOGIC; signal \data_int[1]_i_1_n_0\ : STD_LOGIC; - signal \data_int[2]_i_1_n_0\ : STD_LOGIC; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of \Probe_out_reg[0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \Probe_out_reg[0]\ : label is "yes"; attribute DONT_TOUCH of \Probe_out_reg[1]\ : label is std.standard.true; attribute KEEP of \Probe_out_reg[1]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[2]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[2]\ : label is "yes"; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \data_int[1]_i_1\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \data_int[2]_i_1\ : label is "soft_lutpair14"; begin - D(2 downto 0) <= \^d\(2 downto 0); + D(1 downto 0) <= \^d\(1 downto 0); \Probe_out_reg[0]\: unisim.vcomponents.FDRE port map ( C => clk, @@ -956,21 +950,13 @@ begin Q => probe_out0(0), R => SR(0) ); -\Probe_out_reg[1]\: unisim.vcomponents.FDRE +\Probe_out_reg[1]\: unisim.vcomponents.FDSE port map ( C => clk, CE => E(0), D => \^d\(1), Q => probe_out0(1), - R => SR(0) - ); -\Probe_out_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => clk, - CE => E(0), - D => \^d\(2), - Q => probe_out0(2), - R => SR(0) + S => SR(0) ); \data_int[0]_i_1\: unisim.vcomponents.LUT3 generic map( @@ -992,16 +978,6 @@ begin I2 => \^d\(1), O => \data_int[1]_i_1_n_0\ ); -\data_int[2]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => Q(2), - I1 => wr_probe_out(0), - I2 => \^d\(2), - O => \data_int[2]_i_1_n_0\ - ); \data_int_reg[0]\: unisim.vcomponents.FDRE port map ( C => \out\, @@ -1010,21 +986,13 @@ begin Q => \^d\(0), R => SR(0) ); -\data_int_reg[1]\: unisim.vcomponents.FDRE +\data_int_reg[1]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => '1', D => \data_int[1]_i_1_n_0\, Q => \^d\(1), - R => SR(0) - ); -\data_int_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => \out\, - CE => '1', - D => \data_int[2]_i_1_n_0\, - Q => \^d\(2), - R => SR(0) + S => SR(0) ); end STRUCTURE; library IEEE; @@ -1132,22 +1100,22 @@ architecture STRUCTURE of \vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameteri signal \mem_probe_out[0]\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal rd_probe_out : STD_LOGIC_VECTOR ( 2 to 2 ); attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \Bus_Data_out_int[0]_i_1\ : label is "soft_lutpair22"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[10]_i_1\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[11]_i_1\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[12]_i_1\ : label is "soft_lutpair16"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[13]_i_1\ : label is "soft_lutpair16"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[14]_i_1\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[15]_i_1\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[1]_i_1\ : label is "soft_lutpair22"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[2]_i_1\ : label is "soft_lutpair21"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[3]_i_1\ : label is "soft_lutpair21"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[4]_i_1\ : label is "soft_lutpair20"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[5]_i_1\ : label is "soft_lutpair20"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[6]_i_1\ : label is "soft_lutpair19"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[7]_i_1\ : label is "soft_lutpair19"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[8]_i_1\ : label is "soft_lutpair18"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[9]_i_1\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[0]_i_1\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[10]_i_1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[11]_i_1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[12]_i_1\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[13]_i_1\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[14]_i_1\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[15]_i_1\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[1]_i_1\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[2]_i_1\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[3]_i_1\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[4]_i_1\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[5]_i_1\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[6]_i_1\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[7]_i_1\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[8]_i_1\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[9]_i_1\ : label is "soft_lutpair17"; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of \Probe_out_reg[0]\ : label is std.standard.true; attribute KEEP : string; @@ -2139,8 +2107,8 @@ architecture STRUCTURE of \vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameteri attribute DONT_TOUCH of \Probe_out_reg[1]\ : label is std.standard.true; attribute KEEP of \Probe_out_reg[1]\ : label is "yes"; attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \data_int[0]_i_1\ : label is "soft_lutpair23"; - attribute SOFT_HLUTNM of \data_int[1]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \data_int[0]_i_1\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \data_int[1]_i_1\ : label is "soft_lutpair22"; begin D(1 downto 0) <= \^d\(1 downto 0); \Probe_out_reg[0]\: unisim.vcomponents.FDSE @@ -2316,10 +2284,10 @@ architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_probe_width is signal \addr_count[1]_i_1_n_0\ : STD_LOGIC; signal probe_width_mem : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \addr_count[0]_i_1\ : label is "soft_lutpair31"; - attribute SOFT_HLUTNM of \addr_count[1]_i_1\ : label is "soft_lutpair31"; - attribute SOFT_HLUTNM of \probe_width_int[1]_i_1\ : label is "soft_lutpair32"; - attribute SOFT_HLUTNM of \probe_width_int[8]_i_1\ : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \addr_count[0]_i_1\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \addr_count[1]_i_1\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \probe_width_int[1]_i_1\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \probe_width_int[8]_i_1\ : label is "soft_lutpair31"; begin \addr_count[0]_i_1\: unisim.vcomponents.LUT5 generic map( @@ -2362,21 +2330,21 @@ begin R => '0' ); \probe_width_int[0]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => addr_count(0), - I1 => addr_count(1), - O => probe_width_mem(0) - ); -\probe_width_int[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => addr_count(1), I1 => addr_count(0), + O => probe_width_mem(0) + ); +\probe_width_int[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => addr_count(0), + I1 => addr_count(1), O => probe_width_mem(1) ); \probe_width_int[8]_i_1\: unisim.vcomponents.LUT2 @@ -5411,7 +5379,7 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity vio_manual_ctrl_vio_v3_0_20_probe_out_all is port ( - probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); @@ -5455,9 +5423,8 @@ architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_probe_out_all is attribute async_reg of Committ_1 : signal is "true"; signal Committ_2 : STD_LOGIC; attribute async_reg of Committ_2 : signal is "true"; + signal \G_PROBE_OUT[0].PROBE_OUT0_INST_n_2\ : STD_LOGIC; signal \G_PROBE_OUT[0].PROBE_OUT0_INST_n_3\ : STD_LOGIC; - signal \G_PROBE_OUT[0].PROBE_OUT0_INST_n_4\ : STD_LOGIC; - signal \G_PROBE_OUT[0].PROBE_OUT0_INST_n_5\ : STD_LOGIC; signal \G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0\ : STD_LOGIC; signal \G_PROBE_OUT[0].wr_probe_out[0]_i_2_n_0\ : STD_LOGIC; signal \G_PROBE_OUT[0].wr_probe_out[0]_i_6_n_0\ : STD_LOGIC; @@ -5500,20 +5467,20 @@ architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_probe_out_all is attribute ASYNC_REG_boolean of Committ_2_reg : label is std.standard.true; attribute KEEP of Committ_2_reg : label is "yes"; attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \Probe_out_reg_int[0]_i_1\ : label is "soft_lutpair24"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[10]_i_1\ : label is "soft_lutpair28"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[11]_i_1\ : label is "soft_lutpair27"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[12]_i_1\ : label is "soft_lutpair25"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[13]_i_1\ : label is "soft_lutpair26"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[14]_i_1\ : label is "soft_lutpair26"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[15]_i_1\ : label is "soft_lutpair25"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[1]_i_1\ : label is "soft_lutpair24"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[4]_i_1\ : label is "soft_lutpair30"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[5]_i_1\ : label is "soft_lutpair30"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[6]_i_1\ : label is "soft_lutpair29"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[7]_i_1\ : label is "soft_lutpair29"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[8]_i_1\ : label is "soft_lutpair28"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[9]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[0]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[10]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[11]_i_1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[12]_i_1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[13]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[14]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[15]_i_1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[1]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[4]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[5]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[6]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[7]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[8]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[9]_i_1\ : label is "soft_lutpair26"; begin \addr_count[1]_i_5\ <= \^addr_count[1]_i_5\; \addr_p1_reg[2]_0\(2 downto 0) <= \^addr_p1_reg[2]_0\(2 downto 0); @@ -5535,15 +5502,14 @@ Committ_2_reg: unisim.vcomponents.FDRE ); \G_PROBE_OUT[0].PROBE_OUT0_INST\: entity work.vio_manual_ctrl_vio_v3_0_20_probe_out_one port map ( - D(2) => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_3\, - D(1) => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_4\, - D(0) => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_5\, + D(1) => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_2\, + D(0) => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_3\, E(0) => Committ_2, - Q(2 downto 0) => Q(2 downto 0), + Q(1 downto 0) => Q(1 downto 0), SR(0) => SR(0), clk => clk, \out\ => \out\, - probe_out0(2 downto 0) => probe_out0(2 downto 0), + probe_out0(1 downto 0) => probe_out0(1 downto 0), wr_probe_out(0) => wr_probe_out(0) ); \G_PROBE_OUT[0].wr_probe_out[0]_i_1\: unisim.vcomponents.LUT4 @@ -5767,7 +5733,7 @@ Committ_2_reg: unisim.vcomponents.FDRE I2 => \^addr_p1_reg[2]_0\(1), I3 => \G_PROBE_OUT[1].PROBE_OUT0_INST_n_1\, I4 => \^addr_p1_reg[2]_0\(0), - I5 => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_5\, + I5 => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_3\, O => \Probe_out_reg_int[0]_i_2_n_0\ ); \Probe_out_reg_int[10]_i_1\: unisim.vcomponents.LUT3 @@ -5848,21 +5814,20 @@ Committ_2_reg: unisim.vcomponents.FDRE I0 => \G_PROBE_OUT[3].PROBE_OUT0_INST_n_2\, I1 => Bus_Data_out_int(1), I2 => \^addr_p1_reg[2]_0\(1), - I3 => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_4\, + I3 => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_2\, I4 => \^addr_p1_reg[2]_0\(0), O => \Probe_out_reg_int[1]_i_2_n_0\ ); -\Probe_out_reg_int[2]_i_1\: unisim.vcomponents.LUT6 +\Probe_out_reg_int[2]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"88888888B8BBB888" + INIT => X"88B88888" ) port map ( I0 => \G_PROBE_OUT[4].PROBE_OUT0_INST_n_5\, I1 => \^addr_p1_reg[2]_0\(2), - I2 => Bus_Data_out_int(2), - I3 => \^addr_p1_reg[2]_0\(1), - I4 => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_3\, - I5 => \^addr_p1_reg[2]_0\(0), + I2 => \^addr_p1_reg[2]_0\(1), + I3 => \^addr_p1_reg[2]_0\(0), + I4 => Bus_Data_out_int(2), O => probe_out_mem(2) ); \Probe_out_reg_int[3]_i_1\: unisim.vcomponents.LUT5 @@ -6355,7 +6320,7 @@ entity vio_manual_ctrl_vio_v3_0_20_vio is probe_in255 : in STD_LOGIC_VECTOR ( 0 to 0 ); sl_iport0 : in STD_LOGIC_VECTOR ( 36 downto 0 ); sl_oport0 : out STD_LOGIC_VECTOR ( 16 downto 0 ); - probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); @@ -7165,9 +7130,9 @@ entity vio_manual_ctrl_vio_v3_0_20_vio is attribute C_PROBE_IN9_WIDTH : integer; attribute C_PROBE_IN9_WIDTH of vio_manual_ctrl_vio_v3_0_20_vio : entity is 1; attribute C_PROBE_OUT0_INIT_VAL : string; - attribute C_PROBE_OUT0_INIT_VAL of vio_manual_ctrl_vio_v3_0_20_vio : entity is "3'b000"; + attribute C_PROBE_OUT0_INIT_VAL of vio_manual_ctrl_vio_v3_0_20_vio : entity is "2'b10"; attribute C_PROBE_OUT0_WIDTH : integer; - attribute C_PROBE_OUT0_WIDTH of vio_manual_ctrl_vio_v3_0_20_vio : entity is 3; + attribute C_PROBE_OUT0_WIDTH of vio_manual_ctrl_vio_v3_0_20_vio : entity is 2; attribute C_PROBE_OUT100_INIT_VAL : string; attribute C_PROBE_OUT100_INIT_VAL of vio_manual_ctrl_vio_v3_0_20_vio : entity is "1'b0"; attribute C_PROBE_OUT100_WIDTH : integer; @@ -8199,1043 +8164,1043 @@ entity vio_manual_ctrl_vio_v3_0_20_vio is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of vio_manual_ctrl_vio_v3_0_20_vio : entity is "yes"; attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT0 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT0 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000000001"; attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT1 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT1 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000000010"; attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT10 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT10 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101110"; attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT100 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT100 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001000"; attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT101 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT101 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001001"; attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT102 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT102 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001010"; attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT103 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT103 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001011"; attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT104 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT104 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001100"; attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT105 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT105 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001101"; attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT106 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT106 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001110"; attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT107 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT107 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001111"; attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT108 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT108 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010000"; attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT109 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT109 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010001"; attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT11 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT11 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101111"; attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT110 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT110 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010010"; attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT111 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT111 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010011"; attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT112 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT112 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010100"; attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT113 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT113 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010101"; attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT114 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT114 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010110"; attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT115 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT115 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010111"; attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT116 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT116 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011000"; attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT117 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT117 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011001"; attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT118 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT118 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011010"; attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT119 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT119 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011011"; attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT12 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT12 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110000"; attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT120 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT120 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011100"; attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT121 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT121 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011101"; attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT122 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT122 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011110"; attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT123 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT123 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011111"; attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT124 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT124 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100000"; attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT125 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT125 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100001"; attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT126 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT126 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100010"; attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT127 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT127 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100011"; attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT128 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT128 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100100"; attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT129 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT129 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100101"; attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT13 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT13 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110001"; attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT130 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT130 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100110"; attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT131 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT131 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100111"; attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT132 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT132 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101000"; attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT133 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT133 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101001"; attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT134 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT134 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101010"; attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT135 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT135 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101011"; attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT136 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT136 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101100"; attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT137 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT137 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101101"; attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT138 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT138 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101110"; attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT139 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT139 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101111"; attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT14 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT14 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110010"; attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT140 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT140 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110000"; attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT141 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT141 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110001"; attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT142 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT142 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110010"; attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT143 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT143 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110011"; attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT144 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT144 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110100"; attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT145 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT145 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110101"; attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT146 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT146 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110110"; attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT147 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT147 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110111"; attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT148 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT148 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111000"; attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT149 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT149 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111001"; attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT15 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT15 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110011"; attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT150 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT150 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111010"; attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT151 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT151 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111011"; attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT152 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT152 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111100"; attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT153 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT153 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111101"; attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT154 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT154 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111110"; attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT155 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT155 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111111"; attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT156 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT156 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000000"; attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT157 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT157 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000001"; attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT158 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT158 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000010"; attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT159 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT159 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000011"; attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT16 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT16 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110100"; attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT160 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT160 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000100"; attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT161 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT161 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000101"; attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT162 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT162 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000110"; attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT163 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT163 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000111"; attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT164 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT164 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001000"; attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT165 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT165 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001001"; attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT166 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT166 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001010"; attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT167 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT167 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001011"; attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT168 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT168 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001100"; attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT169 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT169 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001101"; attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT17 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT17 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110101"; attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT170 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT170 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001110"; attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT171 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT171 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001111"; attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT172 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT172 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010000"; attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT173 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT173 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010001"; attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT174 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT174 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010010"; attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT175 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT175 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010011"; attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT176 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT176 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010100"; attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT177 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT177 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010101"; attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT178 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT178 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010110"; attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT179 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT179 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010111"; attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT18 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT18 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110110"; attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT180 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT180 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011000"; attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT181 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT181 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011001"; attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT182 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT182 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011010"; attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT183 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT183 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011011"; attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT184 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT184 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011100"; attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT185 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT185 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011101"; attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT186 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT186 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011110"; attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT187 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT187 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011111"; attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT188 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT188 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100000"; attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT189 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT189 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100001"; attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT19 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT19 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110111"; attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT190 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT190 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100010"; attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT191 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT191 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100011"; attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT192 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT192 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100100"; attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT193 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT193 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100101"; attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT194 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT194 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100110"; attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT195 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT195 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100111"; attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT196 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT196 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101000"; attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT197 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT197 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101001"; attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT198 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT198 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101010"; attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT199 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT199 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101011"; attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT2 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT2 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000100010"; attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT20 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT20 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111000"; attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT200 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT200 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101100"; attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT201 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT201 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101101"; attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT202 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT202 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101110"; attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT203 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT203 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101111"; attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT204 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT204 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110000"; attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT205 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT205 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110001"; attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT206 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT206 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110010"; attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT207 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT207 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110011"; attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT208 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT208 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110100"; attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT209 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT209 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110101"; attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT21 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT21 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111001"; attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT210 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT210 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110110"; attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT211 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT211 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110111"; attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT212 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT212 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111000"; attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT213 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT213 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111001"; attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT214 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT214 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111010"; attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT215 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT215 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111011"; attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT216 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT216 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111100"; attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT217 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT217 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111101"; attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT218 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT218 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111110"; attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT219 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT219 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111111"; attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT22 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT22 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111010"; attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT220 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT220 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000000"; attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT221 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT221 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000001"; attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT222 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT222 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000010"; attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT223 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT223 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000011"; attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT224 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT224 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000100"; attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT225 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT225 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000101"; attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT226 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT226 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000110"; attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT227 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT227 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000111"; attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT228 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT228 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001000"; attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT229 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT229 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001001"; attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT23 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT23 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111011"; attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT230 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT230 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001010"; attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT231 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT231 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001011"; attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT232 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT232 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001100"; attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT233 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT233 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001101"; attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT234 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT234 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001110"; attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT235 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT235 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001111"; attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT236 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT236 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010000"; attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT237 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT237 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010001"; attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT238 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT238 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010010"; attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT239 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT239 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010011"; attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT24 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT24 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111100"; attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT240 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT240 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010100"; attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT241 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT241 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010101"; attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT242 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT242 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010110"; attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT243 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT243 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010111"; attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT244 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT244 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011000"; attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT245 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT245 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011001"; attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT246 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT246 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011010"; attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT247 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT247 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011011"; attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT248 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT248 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011100"; attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT249 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT249 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011101"; attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT25 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT25 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111101"; attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT250 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT250 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011110"; attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT251 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT251 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011111"; attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT252 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT252 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100000"; attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT253 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT253 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100001"; attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT254 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT254 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100010"; attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT255 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT255 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100011"; attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT26 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT26 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111110"; attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT27 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT27 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111111"; attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT28 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT28 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000000"; attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT29 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT29 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000001"; attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT3 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT3 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000100100"; attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT30 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT30 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000010"; attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT31 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT31 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000011"; attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT32 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT32 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000100"; attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT33 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT33 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000101"; attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT34 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT34 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000110"; attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT35 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT35 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000111"; attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT36 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT36 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001000"; attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT37 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT37 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001001"; attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT38 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT38 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001010"; attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT39 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT39 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001011"; attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT4 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT4 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101000"; attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT40 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT40 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001100"; attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT41 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT41 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001101"; attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT42 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT42 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001110"; attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT43 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT43 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001111"; attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT44 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT44 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010000"; attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT45 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT45 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010001"; attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT46 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT46 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010010"; attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT47 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT47 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010011"; attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT48 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT48 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010100"; attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT49 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT49 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010101"; attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT5 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT5 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101001"; attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT50 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT50 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010110"; attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT51 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT51 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010111"; attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT52 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT52 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011000"; attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT53 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT53 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011001"; attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT54 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT54 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011010"; attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT55 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT55 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011011"; attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT56 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT56 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011100"; attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT57 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT57 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011101"; attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT58 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT58 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011110"; attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT59 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT59 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011111"; attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT6 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT6 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101010"; attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT60 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT60 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100000"; attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT61 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT61 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100001"; attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT62 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT62 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100010"; attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT63 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT63 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100011"; attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT64 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT64 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100100"; attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT65 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT65 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100101"; attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT66 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT66 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100110"; attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT67 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT67 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100111"; attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT68 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT68 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101000"; attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT69 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT69 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101001"; attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT7 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT7 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101011"; attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT70 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT70 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101010"; attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT71 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT71 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101011"; attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT72 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT72 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101100"; attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT73 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT73 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101101"; attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT74 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT74 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101110"; attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT75 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT75 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101111"; attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT76 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT76 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110000"; attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT77 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT77 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110001"; attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT78 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT78 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110010"; attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT79 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT79 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110011"; attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT8 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT8 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101100"; attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT80 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT80 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110100"; attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT81 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT81 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110101"; attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT82 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT82 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110110"; attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT83 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT83 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110111"; attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT84 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT84 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111000"; attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT85 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT85 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111001"; attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT86 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT86 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111010"; attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT87 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT87 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111011"; attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT88 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT88 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111100"; attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT89 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT89 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111101"; attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT9 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT9 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101101"; attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT90 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT90 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111110"; attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT91 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT91 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111111"; attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT92 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT92 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000000"; attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT93 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT93 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000001"; attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT94 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT94 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000010"; attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT95 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT95 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000011"; attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT96 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT96 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000100"; attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT97 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT97 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000101"; attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT98 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT98 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000110"; attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT99 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT99 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000111"; attribute LC_LOW_BIT_POS_PROBE_OUT0 : string; attribute LC_LOW_BIT_POS_PROBE_OUT0 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000000000"; attribute LC_LOW_BIT_POS_PROBE_OUT1 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT1 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT1 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000000010"; attribute LC_LOW_BIT_POS_PROBE_OUT10 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT10 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT10 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101110"; attribute LC_LOW_BIT_POS_PROBE_OUT100 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT100 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT100 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001000"; attribute LC_LOW_BIT_POS_PROBE_OUT101 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT101 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT101 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001001"; attribute LC_LOW_BIT_POS_PROBE_OUT102 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT102 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT102 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001010"; attribute LC_LOW_BIT_POS_PROBE_OUT103 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT103 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT103 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001011"; attribute LC_LOW_BIT_POS_PROBE_OUT104 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT104 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT104 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001100"; attribute LC_LOW_BIT_POS_PROBE_OUT105 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT105 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT105 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001101"; attribute LC_LOW_BIT_POS_PROBE_OUT106 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT106 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT106 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001110"; attribute LC_LOW_BIT_POS_PROBE_OUT107 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT107 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT107 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001111"; attribute LC_LOW_BIT_POS_PROBE_OUT108 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT108 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT108 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010000"; attribute LC_LOW_BIT_POS_PROBE_OUT109 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT109 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT109 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010001"; attribute LC_LOW_BIT_POS_PROBE_OUT11 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT11 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT11 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101111"; attribute LC_LOW_BIT_POS_PROBE_OUT110 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT110 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT110 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010010"; attribute LC_LOW_BIT_POS_PROBE_OUT111 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT111 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT111 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010011"; attribute LC_LOW_BIT_POS_PROBE_OUT112 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT112 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT112 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010100"; attribute LC_LOW_BIT_POS_PROBE_OUT113 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT113 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT113 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010101"; attribute LC_LOW_BIT_POS_PROBE_OUT114 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT114 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT114 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010110"; attribute LC_LOW_BIT_POS_PROBE_OUT115 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT115 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT115 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010111"; attribute LC_LOW_BIT_POS_PROBE_OUT116 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT116 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT116 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011000"; attribute LC_LOW_BIT_POS_PROBE_OUT117 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT117 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT117 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011001"; attribute LC_LOW_BIT_POS_PROBE_OUT118 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT118 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT118 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011010"; attribute LC_LOW_BIT_POS_PROBE_OUT119 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT119 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT119 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011011"; attribute LC_LOW_BIT_POS_PROBE_OUT12 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT12 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT12 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110000"; attribute LC_LOW_BIT_POS_PROBE_OUT120 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT120 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT120 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011100"; attribute LC_LOW_BIT_POS_PROBE_OUT121 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT121 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT121 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011101"; attribute LC_LOW_BIT_POS_PROBE_OUT122 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT122 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT122 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011110"; attribute LC_LOW_BIT_POS_PROBE_OUT123 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT123 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT123 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011111"; attribute LC_LOW_BIT_POS_PROBE_OUT124 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT124 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT124 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100000"; attribute LC_LOW_BIT_POS_PROBE_OUT125 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT125 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT125 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100001"; attribute LC_LOW_BIT_POS_PROBE_OUT126 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT126 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT126 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100010"; attribute LC_LOW_BIT_POS_PROBE_OUT127 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT127 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT127 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100011"; attribute LC_LOW_BIT_POS_PROBE_OUT128 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT128 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100101"; + attribute LC_LOW_BIT_POS_PROBE_OUT128 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100100"; attribute LC_LOW_BIT_POS_PROBE_OUT129 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT129 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT129 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100101"; attribute LC_LOW_BIT_POS_PROBE_OUT13 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT13 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT13 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110001"; attribute LC_LOW_BIT_POS_PROBE_OUT130 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT130 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100111"; + attribute LC_LOW_BIT_POS_PROBE_OUT130 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100110"; attribute LC_LOW_BIT_POS_PROBE_OUT131 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT131 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101000"; + attribute LC_LOW_BIT_POS_PROBE_OUT131 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100111"; attribute LC_LOW_BIT_POS_PROBE_OUT132 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT132 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101001"; + attribute LC_LOW_BIT_POS_PROBE_OUT132 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101000"; attribute LC_LOW_BIT_POS_PROBE_OUT133 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT133 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT133 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101001"; attribute LC_LOW_BIT_POS_PROBE_OUT134 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT134 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT134 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101010"; attribute LC_LOW_BIT_POS_PROBE_OUT135 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT135 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT135 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101011"; attribute LC_LOW_BIT_POS_PROBE_OUT136 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT136 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT136 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101100"; attribute LC_LOW_BIT_POS_PROBE_OUT137 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT137 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT137 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101101"; attribute LC_LOW_BIT_POS_PROBE_OUT138 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT138 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT138 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101110"; attribute LC_LOW_BIT_POS_PROBE_OUT139 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT139 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT139 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101111"; attribute LC_LOW_BIT_POS_PROBE_OUT14 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT14 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT14 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110010"; attribute LC_LOW_BIT_POS_PROBE_OUT140 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT140 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT140 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110000"; attribute LC_LOW_BIT_POS_PROBE_OUT141 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT141 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT141 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110001"; attribute LC_LOW_BIT_POS_PROBE_OUT142 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT142 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT142 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110010"; attribute LC_LOW_BIT_POS_PROBE_OUT143 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT143 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT143 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110011"; attribute LC_LOW_BIT_POS_PROBE_OUT144 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT144 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT144 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110100"; attribute LC_LOW_BIT_POS_PROBE_OUT145 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT145 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT145 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110101"; attribute LC_LOW_BIT_POS_PROBE_OUT146 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT146 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT146 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110110"; attribute LC_LOW_BIT_POS_PROBE_OUT147 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT147 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT147 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110111"; attribute LC_LOW_BIT_POS_PROBE_OUT148 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT148 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT148 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111000"; attribute LC_LOW_BIT_POS_PROBE_OUT149 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT149 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT149 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111001"; attribute LC_LOW_BIT_POS_PROBE_OUT15 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT15 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT15 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110011"; attribute LC_LOW_BIT_POS_PROBE_OUT150 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT150 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT150 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111010"; attribute LC_LOW_BIT_POS_PROBE_OUT151 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT151 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT151 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111011"; attribute LC_LOW_BIT_POS_PROBE_OUT152 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT152 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT152 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111100"; attribute LC_LOW_BIT_POS_PROBE_OUT153 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT153 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT153 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111101"; attribute LC_LOW_BIT_POS_PROBE_OUT154 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT154 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT154 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111110"; attribute LC_LOW_BIT_POS_PROBE_OUT155 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT155 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT155 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111111"; attribute LC_LOW_BIT_POS_PROBE_OUT156 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT156 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT156 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000000"; attribute LC_LOW_BIT_POS_PROBE_OUT157 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT157 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT157 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000001"; attribute LC_LOW_BIT_POS_PROBE_OUT158 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT158 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT158 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000010"; attribute LC_LOW_BIT_POS_PROBE_OUT159 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT159 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT159 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000011"; attribute LC_LOW_BIT_POS_PROBE_OUT16 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT16 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT16 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110100"; attribute LC_LOW_BIT_POS_PROBE_OUT160 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT160 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT160 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000100"; attribute LC_LOW_BIT_POS_PROBE_OUT161 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT161 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT161 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000101"; attribute LC_LOW_BIT_POS_PROBE_OUT162 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT162 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT162 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000110"; attribute LC_LOW_BIT_POS_PROBE_OUT163 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT163 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT163 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000111"; attribute LC_LOW_BIT_POS_PROBE_OUT164 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT164 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT164 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001000"; attribute LC_LOW_BIT_POS_PROBE_OUT165 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT165 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT165 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001001"; attribute LC_LOW_BIT_POS_PROBE_OUT166 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT166 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT166 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001010"; attribute LC_LOW_BIT_POS_PROBE_OUT167 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT167 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT167 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001011"; attribute LC_LOW_BIT_POS_PROBE_OUT168 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT168 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT168 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001100"; attribute LC_LOW_BIT_POS_PROBE_OUT169 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT169 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT169 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001101"; attribute LC_LOW_BIT_POS_PROBE_OUT17 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT17 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT17 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110101"; attribute LC_LOW_BIT_POS_PROBE_OUT170 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT170 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT170 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001110"; attribute LC_LOW_BIT_POS_PROBE_OUT171 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT171 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT171 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001111"; attribute LC_LOW_BIT_POS_PROBE_OUT172 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT172 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT172 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010000"; attribute LC_LOW_BIT_POS_PROBE_OUT173 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT173 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT173 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010001"; attribute LC_LOW_BIT_POS_PROBE_OUT174 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT174 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT174 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010010"; attribute LC_LOW_BIT_POS_PROBE_OUT175 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT175 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT175 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010011"; attribute LC_LOW_BIT_POS_PROBE_OUT176 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT176 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT176 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010100"; attribute LC_LOW_BIT_POS_PROBE_OUT177 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT177 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT177 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010101"; attribute LC_LOW_BIT_POS_PROBE_OUT178 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT178 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT178 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010110"; attribute LC_LOW_BIT_POS_PROBE_OUT179 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT179 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT179 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010111"; attribute LC_LOW_BIT_POS_PROBE_OUT18 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT18 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT18 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110110"; attribute LC_LOW_BIT_POS_PROBE_OUT180 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT180 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT180 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011000"; attribute LC_LOW_BIT_POS_PROBE_OUT181 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT181 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT181 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011001"; attribute LC_LOW_BIT_POS_PROBE_OUT182 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT182 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT182 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011010"; attribute LC_LOW_BIT_POS_PROBE_OUT183 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT183 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT183 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011011"; attribute LC_LOW_BIT_POS_PROBE_OUT184 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT184 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT184 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011100"; attribute LC_LOW_BIT_POS_PROBE_OUT185 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT185 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT185 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011101"; attribute LC_LOW_BIT_POS_PROBE_OUT186 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT186 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT186 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011110"; attribute LC_LOW_BIT_POS_PROBE_OUT187 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT187 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT187 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011111"; attribute LC_LOW_BIT_POS_PROBE_OUT188 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT188 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT188 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100000"; attribute LC_LOW_BIT_POS_PROBE_OUT189 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT189 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT189 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100001"; attribute LC_LOW_BIT_POS_PROBE_OUT19 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT19 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT19 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110111"; attribute LC_LOW_BIT_POS_PROBE_OUT190 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT190 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT190 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100010"; attribute LC_LOW_BIT_POS_PROBE_OUT191 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT191 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT191 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100011"; attribute LC_LOW_BIT_POS_PROBE_OUT192 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT192 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100101"; + attribute LC_LOW_BIT_POS_PROBE_OUT192 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100100"; attribute LC_LOW_BIT_POS_PROBE_OUT193 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT193 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT193 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100101"; attribute LC_LOW_BIT_POS_PROBE_OUT194 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT194 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100111"; + attribute LC_LOW_BIT_POS_PROBE_OUT194 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100110"; attribute LC_LOW_BIT_POS_PROBE_OUT195 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT195 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101000"; + attribute LC_LOW_BIT_POS_PROBE_OUT195 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100111"; attribute LC_LOW_BIT_POS_PROBE_OUT196 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT196 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101001"; + attribute LC_LOW_BIT_POS_PROBE_OUT196 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101000"; attribute LC_LOW_BIT_POS_PROBE_OUT197 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT197 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT197 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101001"; attribute LC_LOW_BIT_POS_PROBE_OUT198 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT198 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT198 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101010"; attribute LC_LOW_BIT_POS_PROBE_OUT199 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT199 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT199 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101011"; attribute LC_LOW_BIT_POS_PROBE_OUT2 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT2 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT2 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000000011"; attribute LC_LOW_BIT_POS_PROBE_OUT20 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT20 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT20 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111000"; attribute LC_LOW_BIT_POS_PROBE_OUT200 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT200 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT200 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101100"; attribute LC_LOW_BIT_POS_PROBE_OUT201 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT201 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT201 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101101"; attribute LC_LOW_BIT_POS_PROBE_OUT202 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT202 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT202 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101110"; attribute LC_LOW_BIT_POS_PROBE_OUT203 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT203 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT203 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101111"; attribute LC_LOW_BIT_POS_PROBE_OUT204 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT204 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT204 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110000"; attribute LC_LOW_BIT_POS_PROBE_OUT205 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT205 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT205 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110001"; attribute LC_LOW_BIT_POS_PROBE_OUT206 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT206 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT206 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110010"; attribute LC_LOW_BIT_POS_PROBE_OUT207 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT207 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT207 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110011"; attribute LC_LOW_BIT_POS_PROBE_OUT208 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT208 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT208 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110100"; attribute LC_LOW_BIT_POS_PROBE_OUT209 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT209 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT209 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110101"; attribute LC_LOW_BIT_POS_PROBE_OUT21 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT21 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT21 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111001"; attribute LC_LOW_BIT_POS_PROBE_OUT210 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT210 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT210 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110110"; attribute LC_LOW_BIT_POS_PROBE_OUT211 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT211 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT211 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110111"; attribute LC_LOW_BIT_POS_PROBE_OUT212 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT212 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT212 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111000"; attribute LC_LOW_BIT_POS_PROBE_OUT213 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT213 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT213 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111001"; attribute LC_LOW_BIT_POS_PROBE_OUT214 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT214 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT214 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111010"; attribute LC_LOW_BIT_POS_PROBE_OUT215 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT215 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT215 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111011"; attribute LC_LOW_BIT_POS_PROBE_OUT216 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT216 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT216 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111100"; attribute LC_LOW_BIT_POS_PROBE_OUT217 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT217 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT217 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111101"; attribute LC_LOW_BIT_POS_PROBE_OUT218 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT218 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT218 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111110"; attribute LC_LOW_BIT_POS_PROBE_OUT219 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT219 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT219 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111111"; attribute LC_LOW_BIT_POS_PROBE_OUT22 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT22 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT22 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111010"; attribute LC_LOW_BIT_POS_PROBE_OUT220 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT220 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT220 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000000"; attribute LC_LOW_BIT_POS_PROBE_OUT221 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT221 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT221 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000001"; attribute LC_LOW_BIT_POS_PROBE_OUT222 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT222 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT222 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000010"; attribute LC_LOW_BIT_POS_PROBE_OUT223 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT223 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT223 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000011"; attribute LC_LOW_BIT_POS_PROBE_OUT224 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT224 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT224 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000100"; attribute LC_LOW_BIT_POS_PROBE_OUT225 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT225 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT225 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000101"; attribute LC_LOW_BIT_POS_PROBE_OUT226 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT226 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT226 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000110"; attribute LC_LOW_BIT_POS_PROBE_OUT227 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT227 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT227 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000111"; attribute LC_LOW_BIT_POS_PROBE_OUT228 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT228 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT228 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001000"; attribute LC_LOW_BIT_POS_PROBE_OUT229 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT229 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT229 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001001"; attribute LC_LOW_BIT_POS_PROBE_OUT23 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT23 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT23 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111011"; attribute LC_LOW_BIT_POS_PROBE_OUT230 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT230 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT230 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001010"; attribute LC_LOW_BIT_POS_PROBE_OUT231 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT231 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT231 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001011"; attribute LC_LOW_BIT_POS_PROBE_OUT232 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT232 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT232 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001100"; attribute LC_LOW_BIT_POS_PROBE_OUT233 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT233 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT233 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001101"; attribute LC_LOW_BIT_POS_PROBE_OUT234 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT234 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT234 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001110"; attribute LC_LOW_BIT_POS_PROBE_OUT235 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT235 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT235 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001111"; attribute LC_LOW_BIT_POS_PROBE_OUT236 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT236 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT236 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010000"; attribute LC_LOW_BIT_POS_PROBE_OUT237 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT237 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT237 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010001"; attribute LC_LOW_BIT_POS_PROBE_OUT238 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT238 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT238 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010010"; attribute LC_LOW_BIT_POS_PROBE_OUT239 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT239 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT239 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010011"; attribute LC_LOW_BIT_POS_PROBE_OUT24 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT24 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT24 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111100"; attribute LC_LOW_BIT_POS_PROBE_OUT240 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT240 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT240 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010100"; attribute LC_LOW_BIT_POS_PROBE_OUT241 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT241 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT241 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010101"; attribute LC_LOW_BIT_POS_PROBE_OUT242 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT242 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT242 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010110"; attribute LC_LOW_BIT_POS_PROBE_OUT243 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT243 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT243 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010111"; attribute LC_LOW_BIT_POS_PROBE_OUT244 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT244 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT244 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011000"; attribute LC_LOW_BIT_POS_PROBE_OUT245 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT245 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT245 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011001"; attribute LC_LOW_BIT_POS_PROBE_OUT246 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT246 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT246 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011010"; attribute LC_LOW_BIT_POS_PROBE_OUT247 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT247 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT247 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011011"; attribute LC_LOW_BIT_POS_PROBE_OUT248 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT248 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT248 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011100"; attribute LC_LOW_BIT_POS_PROBE_OUT249 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT249 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT249 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011101"; attribute LC_LOW_BIT_POS_PROBE_OUT25 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT25 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT25 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111101"; attribute LC_LOW_BIT_POS_PROBE_OUT250 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT250 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT250 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011110"; attribute LC_LOW_BIT_POS_PROBE_OUT251 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT251 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT251 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011111"; attribute LC_LOW_BIT_POS_PROBE_OUT252 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT252 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT252 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100000"; attribute LC_LOW_BIT_POS_PROBE_OUT253 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT253 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT253 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100001"; attribute LC_LOW_BIT_POS_PROBE_OUT254 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT254 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT254 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100010"; attribute LC_LOW_BIT_POS_PROBE_OUT255 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT255 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT255 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100011"; attribute LC_LOW_BIT_POS_PROBE_OUT26 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT26 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT26 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111110"; attribute LC_LOW_BIT_POS_PROBE_OUT27 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT27 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT27 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111111"; attribute LC_LOW_BIT_POS_PROBE_OUT28 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT28 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT28 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000000"; attribute LC_LOW_BIT_POS_PROBE_OUT29 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT29 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT29 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000001"; attribute LC_LOW_BIT_POS_PROBE_OUT3 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT3 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT3 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000100011"; attribute LC_LOW_BIT_POS_PROBE_OUT30 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT30 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT30 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000010"; attribute LC_LOW_BIT_POS_PROBE_OUT31 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT31 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT31 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000011"; attribute LC_LOW_BIT_POS_PROBE_OUT32 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT32 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT32 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000100"; attribute LC_LOW_BIT_POS_PROBE_OUT33 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT33 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT33 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000101"; attribute LC_LOW_BIT_POS_PROBE_OUT34 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT34 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT34 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000110"; attribute LC_LOW_BIT_POS_PROBE_OUT35 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT35 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT35 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000111"; attribute LC_LOW_BIT_POS_PROBE_OUT36 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT36 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT36 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001000"; attribute LC_LOW_BIT_POS_PROBE_OUT37 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT37 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT37 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001001"; attribute LC_LOW_BIT_POS_PROBE_OUT38 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT38 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT38 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001010"; attribute LC_LOW_BIT_POS_PROBE_OUT39 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT39 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT39 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001011"; attribute LC_LOW_BIT_POS_PROBE_OUT4 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT4 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT4 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000100101"; attribute LC_LOW_BIT_POS_PROBE_OUT40 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT40 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT40 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001100"; attribute LC_LOW_BIT_POS_PROBE_OUT41 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT41 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT41 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001101"; attribute LC_LOW_BIT_POS_PROBE_OUT42 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT42 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT42 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001110"; attribute LC_LOW_BIT_POS_PROBE_OUT43 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT43 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT43 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001111"; attribute LC_LOW_BIT_POS_PROBE_OUT44 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT44 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT44 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010000"; attribute LC_LOW_BIT_POS_PROBE_OUT45 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT45 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT45 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010001"; attribute LC_LOW_BIT_POS_PROBE_OUT46 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT46 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT46 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010010"; attribute LC_LOW_BIT_POS_PROBE_OUT47 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT47 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT47 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010011"; attribute LC_LOW_BIT_POS_PROBE_OUT48 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT48 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT48 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010100"; attribute LC_LOW_BIT_POS_PROBE_OUT49 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT49 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT49 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010101"; attribute LC_LOW_BIT_POS_PROBE_OUT5 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT5 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT5 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101001"; attribute LC_LOW_BIT_POS_PROBE_OUT50 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT50 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT50 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010110"; attribute LC_LOW_BIT_POS_PROBE_OUT51 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT51 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT51 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010111"; attribute LC_LOW_BIT_POS_PROBE_OUT52 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT52 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT52 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011000"; attribute LC_LOW_BIT_POS_PROBE_OUT53 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT53 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT53 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011001"; attribute LC_LOW_BIT_POS_PROBE_OUT54 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT54 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT54 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011010"; attribute LC_LOW_BIT_POS_PROBE_OUT55 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT55 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT55 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011011"; attribute LC_LOW_BIT_POS_PROBE_OUT56 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT56 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT56 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011100"; attribute LC_LOW_BIT_POS_PROBE_OUT57 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT57 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT57 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011101"; attribute LC_LOW_BIT_POS_PROBE_OUT58 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT58 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT58 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011110"; attribute LC_LOW_BIT_POS_PROBE_OUT59 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT59 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT59 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011111"; attribute LC_LOW_BIT_POS_PROBE_OUT6 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT6 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT6 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101010"; attribute LC_LOW_BIT_POS_PROBE_OUT60 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT60 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT60 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100000"; attribute LC_LOW_BIT_POS_PROBE_OUT61 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT61 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT61 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100001"; attribute LC_LOW_BIT_POS_PROBE_OUT62 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT62 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT62 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100010"; attribute LC_LOW_BIT_POS_PROBE_OUT63 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT63 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT63 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100011"; attribute LC_LOW_BIT_POS_PROBE_OUT64 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT64 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100101"; + attribute LC_LOW_BIT_POS_PROBE_OUT64 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100100"; attribute LC_LOW_BIT_POS_PROBE_OUT65 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT65 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT65 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100101"; attribute LC_LOW_BIT_POS_PROBE_OUT66 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT66 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100111"; + attribute LC_LOW_BIT_POS_PROBE_OUT66 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100110"; attribute LC_LOW_BIT_POS_PROBE_OUT67 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT67 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101000"; + attribute LC_LOW_BIT_POS_PROBE_OUT67 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100111"; attribute LC_LOW_BIT_POS_PROBE_OUT68 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT68 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101001"; + attribute LC_LOW_BIT_POS_PROBE_OUT68 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101000"; attribute LC_LOW_BIT_POS_PROBE_OUT69 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT69 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT69 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101001"; attribute LC_LOW_BIT_POS_PROBE_OUT7 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT7 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT7 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101011"; attribute LC_LOW_BIT_POS_PROBE_OUT70 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT70 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT70 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101010"; attribute LC_LOW_BIT_POS_PROBE_OUT71 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT71 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT71 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101011"; attribute LC_LOW_BIT_POS_PROBE_OUT72 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT72 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT72 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101100"; attribute LC_LOW_BIT_POS_PROBE_OUT73 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT73 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT73 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101101"; attribute LC_LOW_BIT_POS_PROBE_OUT74 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT74 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT74 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101110"; attribute LC_LOW_BIT_POS_PROBE_OUT75 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT75 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT75 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101111"; attribute LC_LOW_BIT_POS_PROBE_OUT76 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT76 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT76 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110000"; attribute LC_LOW_BIT_POS_PROBE_OUT77 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT77 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT77 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110001"; attribute LC_LOW_BIT_POS_PROBE_OUT78 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT78 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT78 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110010"; attribute LC_LOW_BIT_POS_PROBE_OUT79 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT79 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT79 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110011"; attribute LC_LOW_BIT_POS_PROBE_OUT8 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT8 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT8 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101100"; attribute LC_LOW_BIT_POS_PROBE_OUT80 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT80 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT80 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110100"; attribute LC_LOW_BIT_POS_PROBE_OUT81 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT81 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT81 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110101"; attribute LC_LOW_BIT_POS_PROBE_OUT82 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT82 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT82 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110110"; attribute LC_LOW_BIT_POS_PROBE_OUT83 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT83 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT83 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110111"; attribute LC_LOW_BIT_POS_PROBE_OUT84 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT84 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT84 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111000"; attribute LC_LOW_BIT_POS_PROBE_OUT85 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT85 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT85 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111001"; attribute LC_LOW_BIT_POS_PROBE_OUT86 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT86 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT86 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111010"; attribute LC_LOW_BIT_POS_PROBE_OUT87 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT87 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT87 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111011"; attribute LC_LOW_BIT_POS_PROBE_OUT88 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT88 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT88 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111100"; attribute LC_LOW_BIT_POS_PROBE_OUT89 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT89 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT89 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111101"; attribute LC_LOW_BIT_POS_PROBE_OUT9 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT9 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT9 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101101"; attribute LC_LOW_BIT_POS_PROBE_OUT90 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT90 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT90 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111110"; attribute LC_LOW_BIT_POS_PROBE_OUT91 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT91 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT91 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111111"; attribute LC_LOW_BIT_POS_PROBE_OUT92 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT92 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT92 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000000"; attribute LC_LOW_BIT_POS_PROBE_OUT93 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT93 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT93 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000001"; attribute LC_LOW_BIT_POS_PROBE_OUT94 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT94 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT94 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000010"; attribute LC_LOW_BIT_POS_PROBE_OUT95 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT95 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT95 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000011"; attribute LC_LOW_BIT_POS_PROBE_OUT96 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT96 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT96 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000100"; attribute LC_LOW_BIT_POS_PROBE_OUT97 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT97 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT97 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000101"; attribute LC_LOW_BIT_POS_PROBE_OUT98 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT98 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT98 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000110"; attribute LC_LOW_BIT_POS_PROBE_OUT99 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT99 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT99 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000111"; attribute LC_PROBE_IN_WIDTH_STRING : string; attribute LC_PROBE_IN_WIDTH_STRING of vio_manual_ctrl_vio_v3_0_20_vio : entity is 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attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string; - attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of vio_manual_ctrl_vio_v3_0_20_vio : entity is "4096'b0000000100100100000000010010001100000001001000100000000100100001000000010010000000000001000111110000000100011110000000010001110100000001000111000000000100011011000000010001101000000001000110010000000100011000000000010001011100000001000101100000000100010101000000010001010000000001000100110000000100010010000000010001000100000001000100000000000100001111000000010000111000000001000011010000000100001100000000010000101100000001000010100000000100001001000000010000100000000001000001110000000100000110000000010000010100000001000001000000000100000011000000010000001000000001000000010000000100000000000000001111111100000000111111100000000011111101000000001111110000000000111110110000000011111010000000001111100100000000111110000000000011110111000000001111011000000000111101010000000011110100000000001111001100000000111100100000000011110001000000001111000000000000111011110000000011101110000000001110110100000000111011000000000011101011000000001110101000000000111010010000000011101000000000001110011100000000111001100000000011100101000000001110010000000000111000110000000011100010000000001110000100000000111000000000000011011111000000001101111000000000110111010000000011011100000000001101101100000000110110100000000011011001000000001101100000000000110101110000000011010110000000001101010100000000110101000000000011010011000000001101001000000000110100010000000011010000000000001100111100000000110011100000000011001101000000001100110000000000110010110000000011001010000000001100100100000000110010000000000011000111000000001100011000000000110001010000000011000100000000001100001100000000110000100000000011000001000000001100000000000000101111110000000010111110000000001011110100000000101111000000000010111011000000001011101000000000101110010000000010111000000000001011011100000000101101100000000010110101000000001011010000000000101100110000000010110010000000001011000100000000101100000000000010101111000000001010111000000000101011010000000010101100000000001010101100000000101010100000000010101001000000001010100000000000101001110000000010100110000000001010010100000000101001000000000010100011000000001010001000000000101000010000000010100000000000001001111100000000100111100000000010011101000000001001110000000000100110110000000010011010000000001001100100000000100110000000000010010111000000001001011000000000100101010000000010010100000000001001001100000000100100100000000010010001000000001001000000000000100011110000000010001110000000001000110100000000100011000000000010001011000000001000101000000000100010010000000010001000000000001000011100000000100001100000000010000101000000001000010000000000100000110000000010000010000000001000000100000000100000000000000001111111000000000111111000000000011111010000000001111100000000000111101100000000011110100000000001111001000000000111100000000000011101110000000001110110000000000111010100000000011101000000000001110011000000000111001000000000011100010000000001110000000000000110111100000000011011100000000001101101000000000110110000000000011010110000000001101010000000000110100100000000011010000000000001100111000000000110011000000000011001010000000001100100000000000110001100000000011000100000000001100001000000000110000000000000010111110000000001011110000000000101110100000000010111000000000001011011000000000101101000000000010110010000000001011000000000000101011100000000010101100000000001010101000000000101010000000000010100110000000001010010000000000101000100000000010100000000000001001111000000000100111000000000010011010000000001001100000000000100101100000000010010100000000001001001000000000100100000000000010001110000000001000110000000000100010100000000010001000000000001000011000000000100001000000000010000010000000001000000000000000011111100000000001111100000000000111101000000000011110000000000001110110000000000111010000000000011100100000000001110000000000000110111000000000011011000000000001101010000000000110100000000000011001100000000001100100000000000110001000000000011000000000000001011110000000000101110000000000010110100000000001011000000000000101011000000000010101000000000001010010000000000100101000000000010001100000000000000110000000000000010"; + attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of vio_manual_ctrl_vio_v3_0_20_vio : entity is "4096'b0000000100100011000000010010001000000001001000010000000100100000000000010001111100000001000111100000000100011101000000010001110000000001000110110000000100011010000000010001100100000001000110000000000100010111000000010001011000000001000101010000000100010100000000010001001100000001000100100000000100010001000000010001000000000001000011110000000100001110000000010000110100000001000011000000000100001011000000010000101000000001000010010000000100001000000000010000011100000001000001100000000100000101000000010000010000000001000000110000000100000010000000010000000100000001000000000000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100100000000000010001000000000000000100000000000000001"; attribute LC_PROBE_OUT_INIT_VAL_STRING : string; - attribute LC_PROBE_OUT_INIT_VAL_STRING of vio_manual_ctrl_vio_v3_0_20_vio : entity is "293'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000"; + attribute LC_PROBE_OUT_INIT_VAL_STRING of vio_manual_ctrl_vio_v3_0_20_vio : entity is "292'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000010"; attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string; - attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of vio_manual_ctrl_vio_v3_0_20_vio : entity is "4096'b0000000100100100000000010010001100000001001000100000000100100001000000010010000000000001000111110000000100011110000000010001110100000001000111000000000100011011000000010001101000000001000110010000000100011000000000010001011100000001000101100000000100010101000000010001010000000001000100110000000100010010000000010001000100000001000100000000000100001111000000010000111000000001000011010000000100001100000000010000101100000001000010100000000100001001000000010000100000000001000001110000000100000110000000010000010100000001000001000000000100000011000000010000001000000001000000010000000100000000000000001111111100000000111111100000000011111101000000001111110000000000111110110000000011111010000000001111100100000000111110000000000011110111000000001111011000000000111101010000000011110100000000001111001100000000111100100000000011110001000000001111000000000000111011110000000011101110000000001110110100000000111011000000000011101011000000001110101000000000111010010000000011101000000000001110011100000000111001100000000011100101000000001110010000000000111000110000000011100010000000001110000100000000111000000000000011011111000000001101111000000000110111010000000011011100000000001101101100000000110110100000000011011001000000001101100000000000110101110000000011010110000000001101010100000000110101000000000011010011000000001101001000000000110100010000000011010000000000001100111100000000110011100000000011001101000000001100110000000000110010110000000011001010000000001100100100000000110010000000000011000111000000001100011000000000110001010000000011000100000000001100001100000000110000100000000011000001000000001100000000000000101111110000000010111110000000001011110100000000101111000000000010111011000000001011101000000000101110010000000010111000000000001011011100000000101101100000000010110101000000001011010000000000101100110000000010110010000000001011000100000000101100000000000010101111000000001010111000000000101011010000000010101100000000001010101100000000101010100000000010101001000000001010100000000000101001110000000010100110000000001010010100000000101001000000000010100011000000001010001000000000101000010000000010100000000000001001111100000000100111100000000010011101000000001001110000000000100110110000000010011010000000001001100100000000100110000000000010010111000000001001011000000000100101010000000010010100000000001001001100000000100100100000000010010001000000001001000000000000100011110000000010001110000000001000110100000000100011000000000010001011000000001000101000000000100010010000000010001000000000001000011100000000100001100000000010000101000000001000010000000000100000110000000010000010000000001000000100000000100000000000000001111111000000000111111000000000011111010000000001111100000000000111101100000000011110100000000001111001000000000111100000000000011101110000000001110110000000000111010100000000011101000000000001110011000000000111001000000000011100010000000001110000000000000110111100000000011011100000000001101101000000000110110000000000011010110000000001101010000000000110100100000000011010000000000001100111000000000110011000000000011001010000000001100100000000000110001100000000011000100000000001100001000000000110000000000000010111110000000001011110000000000101110100000000010111000000000001011011000000000101101000000000010110010000000001011000000000000101011100000000010101100000000001010101000000000101010000000000010100110000000001010010000000000101000100000000010100000000000001001111000000000100111000000000010011010000000001001100000000000100101100000000010010100000000001001001000000000100100000000000010001110000000001000110000000000100010100000000010001000000000001000011000000000100001000000000010000010000000001000000000000000011111100000000001111100000000000111101000000000011110000000000001110110000000000111010000000000011100100000000001110000000000000110111000000000011011000000000001101010000000000110100000000000011001100000000001100100000000000110001000000000011000000000000001011110000000000101110000000000010110100000000001011000000000000101011000000000010101000000000001001100000000000100100000000000000010000000000000000110000000000000000"; + attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of vio_manual_ctrl_vio_v3_0_20_vio : entity is "4096'b0000000100100011000000010010001000000001001000010000000100100000000000010001111100000001000111100000000100011101000000010001110000000001000110110000000100011010000000010001100100000001000110000000000100010111000000010001011000000001000101010000000100010100000000010001001100000001000100100000000100010001000000010001000000000001000011110000000100001110000000010000110100000001000011000000000100001011000000010000101000000001000010010000000100001000000000010000011100000001000001100000000100000101000000010000010000000001000000110000000100000010000000010000000100000001000000000000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001001010000000000100011000000000000001100000000000000100000000000000000"; attribute LC_PROBE_OUT_WIDTH_STRING : string; - attribute LC_PROBE_OUT_WIDTH_STRING of vio_manual_ctrl_vio_v3_0_20_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000001000111110000000000000010"; + attribute LC_PROBE_OUT_WIDTH_STRING of vio_manual_ctrl_vio_v3_0_20_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000001000111110000000000000001"; attribute LC_TOTAL_PROBE_IN_WIDTH : integer; attribute LC_TOTAL_PROBE_IN_WIDTH of vio_manual_ctrl_vio_v3_0_20_vio : entity is 0; attribute LC_TOTAL_PROBE_OUT_WIDTH : integer; - attribute LC_TOTAL_PROBE_OUT_WIDTH of vio_manual_ctrl_vio_v3_0_20_vio : entity is 42; + attribute LC_TOTAL_PROBE_OUT_WIDTH of vio_manual_ctrl_vio_v3_0_20_vio : entity is 41; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of vio_manual_ctrl_vio_v3_0_20_vio : entity is "vio_v3_0_20_vio"; attribute dont_touch : string; @@ -9247,7 +9212,8 @@ architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_vio is signal DECODER_INST_n_5 : STD_LOGIC; signal DECODER_INST_n_6 : STD_LOGIC; signal DECODER_INST_n_7 : STD_LOGIC; - signal PROBE_OUT_ALL_INST_n_42 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_41 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_45 : STD_LOGIC; signal PROBE_OUT_ALL_INST_n_46 : STD_LOGIC; signal PROBE_OUT_ALL_INST_n_47 : STD_LOGIC; signal PROBE_OUT_ALL_INST_n_48 : STD_LOGIC; @@ -9263,7 +9229,6 @@ architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_vio is signal PROBE_OUT_ALL_INST_n_58 : STD_LOGIC; signal PROBE_OUT_ALL_INST_n_59 : STD_LOGIC; signal PROBE_OUT_ALL_INST_n_60 : STD_LOGIC; - signal PROBE_OUT_ALL_INST_n_61 : STD_LOGIC; signal bus_addr : STD_LOGIC_VECTOR ( 16 downto 0 ); signal bus_clk : STD_LOGIC; attribute DONT_TOUCH_boolean : boolean; @@ -9567,27 +9532,27 @@ begin probe_out99(0) <= \\; DECODER_INST: entity work.vio_manual_ctrl_vio_v3_0_20_decoder port map ( - \Bus_data_out_reg[10]_0\ => PROBE_OUT_ALL_INST_n_55, - \Bus_data_out_reg[11]_0\ => PROBE_OUT_ALL_INST_n_54, - \Bus_data_out_reg[12]_0\ => PROBE_OUT_ALL_INST_n_53, - \Bus_data_out_reg[13]_0\ => PROBE_OUT_ALL_INST_n_52, - \Bus_data_out_reg[14]_0\ => PROBE_OUT_ALL_INST_n_51, + \Bus_data_out_reg[10]_0\ => PROBE_OUT_ALL_INST_n_54, + \Bus_data_out_reg[11]_0\ => PROBE_OUT_ALL_INST_n_53, + \Bus_data_out_reg[12]_0\ => PROBE_OUT_ALL_INST_n_52, + \Bus_data_out_reg[13]_0\ => PROBE_OUT_ALL_INST_n_51, + \Bus_data_out_reg[14]_0\ => PROBE_OUT_ALL_INST_n_50, \Bus_data_out_reg[15]_0\(15 downto 0) => bus_do(15 downto 0), - \Bus_data_out_reg[15]_1\ => PROBE_OUT_ALL_INST_n_50, + \Bus_data_out_reg[15]_1\ => PROBE_OUT_ALL_INST_n_49, \Bus_data_out_reg[3]_0\(2) => probe_width_int(8), \Bus_data_out_reg[3]_0\(1 downto 0) => probe_width_int(1 downto 0), - \Bus_data_out_reg[4]_0\ => PROBE_OUT_ALL_INST_n_61, - \Bus_data_out_reg[5]_0\ => PROBE_OUT_ALL_INST_n_60, - \Bus_data_out_reg[6]_0\ => PROBE_OUT_ALL_INST_n_59, - \Bus_data_out_reg[7]_0\ => PROBE_OUT_ALL_INST_n_58, - \Bus_data_out_reg[8]_0\ => PROBE_OUT_ALL_INST_n_57, - \Bus_data_out_reg[9]_0\ => PROBE_OUT_ALL_INST_n_56, + \Bus_data_out_reg[4]_0\ => PROBE_OUT_ALL_INST_n_60, + \Bus_data_out_reg[5]_0\ => PROBE_OUT_ALL_INST_n_59, + \Bus_data_out_reg[6]_0\ => PROBE_OUT_ALL_INST_n_58, + \Bus_data_out_reg[7]_0\ => PROBE_OUT_ALL_INST_n_57, + \Bus_data_out_reg[8]_0\ => PROBE_OUT_ALL_INST_n_56, + \Bus_data_out_reg[9]_0\ => PROBE_OUT_ALL_INST_n_55, \G_PROBE_OUT[0].wr_probe_out[0]_i_3_0\ => DECODER_INST_n_7, \G_PROBE_OUT[0].wr_probe_out[0]_i_4_0\ => DECODER_INST_n_5, - Q(3) => PROBE_OUT_ALL_INST_n_46, - Q(2) => PROBE_OUT_ALL_INST_n_47, - Q(1) => PROBE_OUT_ALL_INST_n_48, - Q(0) => PROBE_OUT_ALL_INST_n_49, + Q(3) => PROBE_OUT_ALL_INST_n_45, + Q(2) => PROBE_OUT_ALL_INST_n_46, + Q(1) => PROBE_OUT_ALL_INST_n_47, + Q(0) => PROBE_OUT_ALL_INST_n_48, SR(0) => clear, in0 => committ, internal_cnt_rst => internal_cnt_rst, @@ -9608,7 +9573,7 @@ DECODER_INST: entity work.vio_manual_ctrl_vio_v3_0_20_decoder \probe_out_modified_reg[15]_0\(2) => \bus_data_int_reg_n_0_[2]\, \probe_out_modified_reg[15]_0\(1) => p_0_in, \probe_out_modified_reg[15]_0\(0) => \bus_data_int_reg_n_0_[0]\, - \rd_en_reg[6]_0\ => PROBE_OUT_ALL_INST_n_42, + \rd_en_reg[6]_0\ => PROBE_OUT_ALL_INST_n_41, rd_probe_out_width => rd_probe_out_width, s_daddr_o(16 downto 0) => bus_addr(16 downto 0), s_den_o => bus_den, @@ -9627,22 +9592,22 @@ PROBE_OUT_ALL_INST: entity work.vio_manual_ctrl_vio_v3_0_20_probe_out_all \G_PROBE_OUT[0].wr_probe_out_reg[0]_0\ => DECODER_INST_n_7, \G_PROBE_OUT[0].wr_probe_out_reg[0]_1\ => DECODER_INST_n_5, \G_PROBE_OUT[0].wr_probe_out_reg[0]_2\ => DECODER_INST_n_6, - \Probe_out_reg_int_reg[10]_0\ => PROBE_OUT_ALL_INST_n_55, - \Probe_out_reg_int_reg[11]_0\ => PROBE_OUT_ALL_INST_n_54, - \Probe_out_reg_int_reg[12]_0\ => PROBE_OUT_ALL_INST_n_53, - \Probe_out_reg_int_reg[13]_0\ => PROBE_OUT_ALL_INST_n_52, - \Probe_out_reg_int_reg[14]_0\ => PROBE_OUT_ALL_INST_n_51, - \Probe_out_reg_int_reg[15]_0\ => PROBE_OUT_ALL_INST_n_50, - \Probe_out_reg_int_reg[3]_0\(3) => PROBE_OUT_ALL_INST_n_46, - \Probe_out_reg_int_reg[3]_0\(2) => PROBE_OUT_ALL_INST_n_47, - \Probe_out_reg_int_reg[3]_0\(1) => PROBE_OUT_ALL_INST_n_48, - \Probe_out_reg_int_reg[3]_0\(0) => PROBE_OUT_ALL_INST_n_49, - \Probe_out_reg_int_reg[4]_0\ => PROBE_OUT_ALL_INST_n_61, - \Probe_out_reg_int_reg[5]_0\ => PROBE_OUT_ALL_INST_n_60, - \Probe_out_reg_int_reg[6]_0\ => PROBE_OUT_ALL_INST_n_59, - \Probe_out_reg_int_reg[7]_0\ => PROBE_OUT_ALL_INST_n_58, - \Probe_out_reg_int_reg[8]_0\ => PROBE_OUT_ALL_INST_n_57, - \Probe_out_reg_int_reg[9]_0\ => PROBE_OUT_ALL_INST_n_56, + \Probe_out_reg_int_reg[10]_0\ => PROBE_OUT_ALL_INST_n_54, + \Probe_out_reg_int_reg[11]_0\ => PROBE_OUT_ALL_INST_n_53, + \Probe_out_reg_int_reg[12]_0\ => PROBE_OUT_ALL_INST_n_52, + \Probe_out_reg_int_reg[13]_0\ => PROBE_OUT_ALL_INST_n_51, + \Probe_out_reg_int_reg[14]_0\ => PROBE_OUT_ALL_INST_n_50, + \Probe_out_reg_int_reg[15]_0\ => PROBE_OUT_ALL_INST_n_49, + \Probe_out_reg_int_reg[3]_0\(3) => PROBE_OUT_ALL_INST_n_45, + \Probe_out_reg_int_reg[3]_0\(2) => PROBE_OUT_ALL_INST_n_46, + \Probe_out_reg_int_reg[3]_0\(1) => PROBE_OUT_ALL_INST_n_47, + \Probe_out_reg_int_reg[3]_0\(0) => PROBE_OUT_ALL_INST_n_48, + \Probe_out_reg_int_reg[4]_0\ => PROBE_OUT_ALL_INST_n_60, + \Probe_out_reg_int_reg[5]_0\ => PROBE_OUT_ALL_INST_n_59, + \Probe_out_reg_int_reg[6]_0\ => PROBE_OUT_ALL_INST_n_58, + \Probe_out_reg_int_reg[7]_0\ => PROBE_OUT_ALL_INST_n_57, + \Probe_out_reg_int_reg[8]_0\ => PROBE_OUT_ALL_INST_n_56, + \Probe_out_reg_int_reg[9]_0\ => PROBE_OUT_ALL_INST_n_55, Q(15) => \bus_data_int_reg_n_0_[15]\, Q(14) => \bus_data_int_reg_n_0_[14]\, Q(13) => \bus_data_int_reg_n_0_[13]\, @@ -9660,13 +9625,13 @@ PROBE_OUT_ALL_INST: entity work.vio_manual_ctrl_vio_v3_0_20_probe_out_all Q(1) => p_0_in, Q(0) => \bus_data_int_reg_n_0_[0]\, SR(0) => clear, - \addr_count[1]_i_5\ => PROBE_OUT_ALL_INST_n_42, + \addr_count[1]_i_5\ => PROBE_OUT_ALL_INST_n_41, \addr_p1_reg[2]_0\(2 downto 0) => xsdb_addr_2_0_p1(2 downto 0), clk => clk, in0 => committ, internal_cnt_rst => internal_cnt_rst, \out\ => bus_clk, - probe_out0(2 downto 0) => probe_out0(2 downto 0), + probe_out0(1 downto 0) => probe_out0(1 downto 0), probe_out1(0) => probe_out1(0), probe_out2(31 downto 0) => probe_out2(31 downto 0), probe_out3(1 downto 0) => probe_out3(1 downto 0), @@ -9833,7 +9798,7 @@ use UNISIM.VCOMPONENTS.ALL; entity vio_manual_ctrl is port ( clk : in STD_LOGIC; - probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); @@ -10653,9 +10618,9 @@ architecture STRUCTURE of vio_manual_ctrl is attribute C_PROBE_IN9_WIDTH : integer; attribute C_PROBE_IN9_WIDTH of inst : label is 1; attribute C_PROBE_OUT0_INIT_VAL : string; - attribute C_PROBE_OUT0_INIT_VAL of inst : label is "3'b000"; + attribute C_PROBE_OUT0_INIT_VAL of inst : label is "2'b10"; attribute C_PROBE_OUT0_WIDTH : integer; - attribute C_PROBE_OUT0_WIDTH of inst : label is 3; + attribute C_PROBE_OUT0_WIDTH of inst : label is 2; attribute C_PROBE_OUT100_INIT_VAL : string; attribute C_PROBE_OUT100_INIT_VAL of inst : label is "1'b0"; attribute C_PROBE_OUT100_WIDTH : integer; @@ -11689,1043 +11654,1043 @@ architecture STRUCTURE of vio_manual_ctrl is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000001"; attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000010"; attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000101110"; attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000010001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000010001000"; attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000010001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000010001001"; attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000010001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000010001010"; attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000010001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000010001011"; attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000010001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000010001100"; attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000010001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000010001101"; attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000010001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000010001110"; attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000010010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000010001111"; attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000010010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000010010000"; attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000010010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000010010001"; attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000101111"; attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000010010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000010010010"; attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000010010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000010010011"; attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000010010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000010010100"; attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000010010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000010010101"; attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000010010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000010010110"; attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000010011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000010010111"; attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000010011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000010011000"; attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000010011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000010011001"; attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000010011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000010011010"; attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000010011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000010011011"; attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000110000"; attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000010011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000010011100"; attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000010011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000010011101"; attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000010011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000010011110"; attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000010100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000010011111"; attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000010100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000010100000"; attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000010100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000010100001"; attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000010100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000010100010"; attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000010100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000010100011"; attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010100100"; attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010100110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010100101"; attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000110001"; attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010100111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010100110"; attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010101000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010100111"; attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010101000"; attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010101001"; attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010101010"; attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010101011"; attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010101100"; attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010101101"; attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010101110"; attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010101111"; attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000110010"; attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010110000"; attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010110001"; attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010110010"; attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010110011"; attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010110100"; attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010110101"; attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010110110"; attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010110111"; attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010111000"; attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010111001"; attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000110011"; attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010111010"; attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010111011"; attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010111100"; attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010111101"; attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010111110"; attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000011000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010111111"; attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000011000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000011000000"; attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000011000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000011000001"; attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000011000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000011000010"; attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000011000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000011000011"; attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000110100"; attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000011000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000011000100"; attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000011000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000011000101"; attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000011000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000011000110"; attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000011001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000011000111"; attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000011001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000011001000"; attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000011001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000011001001"; attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000011001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000011001010"; attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000011001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000011001011"; attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000011001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000011001100"; attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000011001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000011001101"; attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000110101"; attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000011001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000011001110"; attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000011010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000011001111"; attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000011010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000011010000"; attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000011010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000011010001"; attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000011010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000011010010"; attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000011010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000011010011"; attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000011010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000011010100"; attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000011010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000011010101"; attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000011010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000011010110"; attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000011011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000011010111"; attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000110110"; attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000011011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000011011000"; attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000011011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000011011001"; attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000011011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000011011010"; attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000011011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000011011011"; attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000011011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000011011100"; attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000011011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000011011101"; attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000011011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000011011110"; attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000011100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000011011111"; attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000011100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000011100000"; attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000011100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000011100001"; attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000110111"; attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000011100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000011100010"; attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000011100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000011100011"; attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011100100"; attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011100110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011100101"; attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011100111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011100110"; attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011101000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011100111"; attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011101000"; attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011101001"; attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011101010"; attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011101011"; attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000100010"; attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000111000"; attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011101100"; attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011101101"; attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011101110"; attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011101111"; attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011110000"; attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011110001"; attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011110010"; attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011110011"; attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011110100"; attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011110101"; attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000111001"; attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011110110"; attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011110111"; attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011111000"; attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011111001"; attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011111010"; attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011111011"; attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011111100"; attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011111101"; attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011111110"; attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000100000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011111111"; attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000111010"; attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000100000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000100000000"; attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000100000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000100000001"; attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000100000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000100000010"; attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000100000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000100000011"; attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000100000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000100000100"; attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000100000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000100000101"; attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000100000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000100000110"; attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000100001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000100000111"; attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000100001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000100001000"; attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000100001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000100001001"; attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000111011"; attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000100001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000100001010"; attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000100001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000100001011"; attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000100001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000100001100"; attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000100001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000100001101"; attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000100001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000100001110"; attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000100010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000100001111"; attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000100010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000100010000"; attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000100010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000100010001"; attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000100010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000100010010"; attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000100010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000100010011"; attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000111100"; attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000100010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000100010100"; attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000100010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000100010101"; attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000100010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000100010110"; attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000100011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000100010111"; attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000100011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000100011000"; attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000100011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000100011001"; attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000100011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000100011010"; attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000100011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000100011011"; attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000100011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000100011100"; attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000100011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000100011101"; attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000111101"; attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000100011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000100011110"; attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000100100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000100011111"; attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000100100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000100100000"; attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000100100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000100100001"; attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000100100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000100100010"; attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000100100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000100100011"; attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000111110"; attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000001000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000111111"; attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000001000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000001000000"; attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000001000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000001000001"; attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000100100"; attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000001000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000001000010"; attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000001000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000001000011"; attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000001000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000001000100"; attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000001000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000001000101"; attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000001000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000001000110"; attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000001001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000001000111"; attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000001001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000001001000"; attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000001001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000001001001"; attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000001001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000001001010"; attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000001001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000001001011"; attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000101000"; attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000001001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000001001100"; attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000001001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000001001101"; attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000001001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000001001110"; attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000001010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000001001111"; attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000001010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000001010000"; attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000001010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000001010001"; attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000001010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000001010010"; attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000001010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000001010011"; attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000001010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000001010100"; attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000001010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000001010101"; attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000101001"; attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000001010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000001010110"; attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000001011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000001010111"; attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000001011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000001011000"; attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000001011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000001011001"; attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000001011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000001011010"; attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000001011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000001011011"; attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000001011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000001011100"; attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000001011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000001011101"; attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000001011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000001011110"; attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000001100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000001011111"; attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000101010"; attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000001100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000001100000"; attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000001100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000001100001"; attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000001100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000001100010"; attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000001100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000001100011"; attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001100100"; attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001100110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001100101"; attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001100111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001100110"; attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001101000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001100111"; attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001101000"; attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001101001"; attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000101011"; attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001101010"; attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001101011"; attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001101100"; attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001101101"; attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001101110"; attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001101111"; attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001110000"; attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001110001"; attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001110010"; attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001110011"; attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000101100"; attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001110100"; attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001110101"; attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001110110"; attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001110111"; attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001111000"; attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001111001"; attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001111010"; attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001111011"; attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001111100"; attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001111101"; attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000101101"; attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001111110"; attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000010000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001111111"; attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000010000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000010000000"; attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000010000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000010000001"; attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000010000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000010000010"; attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000010000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000010000011"; attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000010000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000010000100"; attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000010000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000010000101"; attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000010000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000010000110"; attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000010001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000010000111"; attribute LC_LOW_BIT_POS_PROBE_OUT0 : string; attribute LC_LOW_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000000"; attribute LC_LOW_BIT_POS_PROBE_OUT1 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000010"; attribute LC_LOW_BIT_POS_PROBE_OUT10 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000101110"; attribute LC_LOW_BIT_POS_PROBE_OUT100 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000010001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000010001000"; attribute LC_LOW_BIT_POS_PROBE_OUT101 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000010001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000010001001"; attribute LC_LOW_BIT_POS_PROBE_OUT102 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000010001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000010001010"; attribute LC_LOW_BIT_POS_PROBE_OUT103 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000010001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000010001011"; attribute LC_LOW_BIT_POS_PROBE_OUT104 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000010001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000010001100"; attribute LC_LOW_BIT_POS_PROBE_OUT105 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000010001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000010001101"; attribute LC_LOW_BIT_POS_PROBE_OUT106 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000010001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000010001110"; attribute LC_LOW_BIT_POS_PROBE_OUT107 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000010010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000010001111"; attribute LC_LOW_BIT_POS_PROBE_OUT108 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000010010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000010010000"; attribute LC_LOW_BIT_POS_PROBE_OUT109 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000010010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000010010001"; attribute LC_LOW_BIT_POS_PROBE_OUT11 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000101111"; attribute LC_LOW_BIT_POS_PROBE_OUT110 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000010010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000010010010"; attribute LC_LOW_BIT_POS_PROBE_OUT111 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000010010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000010010011"; attribute LC_LOW_BIT_POS_PROBE_OUT112 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000010010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000010010100"; attribute LC_LOW_BIT_POS_PROBE_OUT113 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000010010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000010010101"; attribute LC_LOW_BIT_POS_PROBE_OUT114 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000010010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000010010110"; attribute LC_LOW_BIT_POS_PROBE_OUT115 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000010011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000010010111"; attribute LC_LOW_BIT_POS_PROBE_OUT116 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000010011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000010011000"; attribute LC_LOW_BIT_POS_PROBE_OUT117 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000010011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000010011001"; attribute LC_LOW_BIT_POS_PROBE_OUT118 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000010011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000010011010"; attribute LC_LOW_BIT_POS_PROBE_OUT119 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000010011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000010011011"; attribute LC_LOW_BIT_POS_PROBE_OUT12 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000110000"; attribute LC_LOW_BIT_POS_PROBE_OUT120 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000010011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000010011100"; attribute LC_LOW_BIT_POS_PROBE_OUT121 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000010011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000010011101"; attribute LC_LOW_BIT_POS_PROBE_OUT122 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000010011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000010011110"; attribute LC_LOW_BIT_POS_PROBE_OUT123 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000010100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000010011111"; attribute LC_LOW_BIT_POS_PROBE_OUT124 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000010100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000010100000"; attribute LC_LOW_BIT_POS_PROBE_OUT125 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000010100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000010100001"; attribute LC_LOW_BIT_POS_PROBE_OUT126 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000010100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000010100010"; attribute LC_LOW_BIT_POS_PROBE_OUT127 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000010100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000010100011"; attribute LC_LOW_BIT_POS_PROBE_OUT128 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010100101"; + attribute LC_LOW_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010100100"; attribute LC_LOW_BIT_POS_PROBE_OUT129 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010100101"; attribute LC_LOW_BIT_POS_PROBE_OUT13 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000110001"; attribute LC_LOW_BIT_POS_PROBE_OUT130 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010100111"; + attribute LC_LOW_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010100110"; attribute LC_LOW_BIT_POS_PROBE_OUT131 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010101000"; + attribute LC_LOW_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010100111"; attribute LC_LOW_BIT_POS_PROBE_OUT132 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010101001"; + attribute LC_LOW_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010101000"; attribute LC_LOW_BIT_POS_PROBE_OUT133 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010101001"; attribute LC_LOW_BIT_POS_PROBE_OUT134 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010101010"; attribute LC_LOW_BIT_POS_PROBE_OUT135 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010101011"; attribute LC_LOW_BIT_POS_PROBE_OUT136 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010101100"; attribute LC_LOW_BIT_POS_PROBE_OUT137 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010101101"; attribute LC_LOW_BIT_POS_PROBE_OUT138 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010101110"; attribute LC_LOW_BIT_POS_PROBE_OUT139 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010101111"; attribute LC_LOW_BIT_POS_PROBE_OUT14 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000110010"; attribute LC_LOW_BIT_POS_PROBE_OUT140 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010110000"; attribute LC_LOW_BIT_POS_PROBE_OUT141 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010110001"; attribute LC_LOW_BIT_POS_PROBE_OUT142 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010110010"; attribute LC_LOW_BIT_POS_PROBE_OUT143 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010110011"; attribute LC_LOW_BIT_POS_PROBE_OUT144 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010110100"; attribute LC_LOW_BIT_POS_PROBE_OUT145 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010110101"; attribute LC_LOW_BIT_POS_PROBE_OUT146 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010110110"; attribute LC_LOW_BIT_POS_PROBE_OUT147 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010110111"; attribute LC_LOW_BIT_POS_PROBE_OUT148 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010111000"; attribute LC_LOW_BIT_POS_PROBE_OUT149 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010111001"; attribute LC_LOW_BIT_POS_PROBE_OUT15 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000110011"; attribute LC_LOW_BIT_POS_PROBE_OUT150 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010111010"; attribute LC_LOW_BIT_POS_PROBE_OUT151 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010111011"; attribute LC_LOW_BIT_POS_PROBE_OUT152 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010111100"; attribute LC_LOW_BIT_POS_PROBE_OUT153 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010111101"; attribute LC_LOW_BIT_POS_PROBE_OUT154 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010111110"; attribute LC_LOW_BIT_POS_PROBE_OUT155 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000011000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010111111"; attribute LC_LOW_BIT_POS_PROBE_OUT156 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000011000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000011000000"; attribute LC_LOW_BIT_POS_PROBE_OUT157 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000011000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000011000001"; attribute LC_LOW_BIT_POS_PROBE_OUT158 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000011000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000011000010"; attribute LC_LOW_BIT_POS_PROBE_OUT159 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000011000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000011000011"; attribute LC_LOW_BIT_POS_PROBE_OUT16 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000110100"; attribute LC_LOW_BIT_POS_PROBE_OUT160 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000011000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000011000100"; attribute LC_LOW_BIT_POS_PROBE_OUT161 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000011000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000011000101"; attribute LC_LOW_BIT_POS_PROBE_OUT162 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000011000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000011000110"; attribute LC_LOW_BIT_POS_PROBE_OUT163 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000011001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000011000111"; attribute LC_LOW_BIT_POS_PROBE_OUT164 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000011001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000011001000"; attribute LC_LOW_BIT_POS_PROBE_OUT165 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000011001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000011001001"; attribute LC_LOW_BIT_POS_PROBE_OUT166 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000011001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000011001010"; attribute LC_LOW_BIT_POS_PROBE_OUT167 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000011001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000011001011"; attribute LC_LOW_BIT_POS_PROBE_OUT168 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000011001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000011001100"; attribute LC_LOW_BIT_POS_PROBE_OUT169 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000011001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000011001101"; attribute LC_LOW_BIT_POS_PROBE_OUT17 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000110101"; attribute LC_LOW_BIT_POS_PROBE_OUT170 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000011001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000011001110"; attribute LC_LOW_BIT_POS_PROBE_OUT171 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000011010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000011001111"; attribute LC_LOW_BIT_POS_PROBE_OUT172 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000011010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000011010000"; attribute LC_LOW_BIT_POS_PROBE_OUT173 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000011010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000011010001"; attribute LC_LOW_BIT_POS_PROBE_OUT174 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000011010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000011010010"; attribute LC_LOW_BIT_POS_PROBE_OUT175 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000011010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000011010011"; attribute LC_LOW_BIT_POS_PROBE_OUT176 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000011010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000011010100"; attribute LC_LOW_BIT_POS_PROBE_OUT177 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000011010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000011010101"; attribute LC_LOW_BIT_POS_PROBE_OUT178 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000011010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000011010110"; attribute LC_LOW_BIT_POS_PROBE_OUT179 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000011011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000011010111"; attribute LC_LOW_BIT_POS_PROBE_OUT18 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000110110"; attribute LC_LOW_BIT_POS_PROBE_OUT180 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000011011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000011011000"; attribute LC_LOW_BIT_POS_PROBE_OUT181 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000011011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000011011001"; attribute LC_LOW_BIT_POS_PROBE_OUT182 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000011011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000011011010"; attribute LC_LOW_BIT_POS_PROBE_OUT183 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000011011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000011011011"; attribute LC_LOW_BIT_POS_PROBE_OUT184 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000011011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000011011100"; attribute LC_LOW_BIT_POS_PROBE_OUT185 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000011011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000011011101"; attribute LC_LOW_BIT_POS_PROBE_OUT186 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000011011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000011011110"; attribute LC_LOW_BIT_POS_PROBE_OUT187 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000011100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000011011111"; attribute LC_LOW_BIT_POS_PROBE_OUT188 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000011100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000011100000"; attribute LC_LOW_BIT_POS_PROBE_OUT189 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000011100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000011100001"; attribute LC_LOW_BIT_POS_PROBE_OUT19 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000110111"; attribute LC_LOW_BIT_POS_PROBE_OUT190 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000011100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000011100010"; attribute LC_LOW_BIT_POS_PROBE_OUT191 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000011100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000011100011"; attribute LC_LOW_BIT_POS_PROBE_OUT192 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011100101"; + attribute LC_LOW_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011100100"; attribute LC_LOW_BIT_POS_PROBE_OUT193 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011100101"; attribute LC_LOW_BIT_POS_PROBE_OUT194 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011100111"; + attribute LC_LOW_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011100110"; attribute LC_LOW_BIT_POS_PROBE_OUT195 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011101000"; + attribute LC_LOW_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011100111"; attribute LC_LOW_BIT_POS_PROBE_OUT196 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011101001"; + attribute LC_LOW_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011101000"; attribute LC_LOW_BIT_POS_PROBE_OUT197 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011101001"; attribute LC_LOW_BIT_POS_PROBE_OUT198 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011101010"; attribute LC_LOW_BIT_POS_PROBE_OUT199 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011101011"; attribute LC_LOW_BIT_POS_PROBE_OUT2 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000011"; attribute LC_LOW_BIT_POS_PROBE_OUT20 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000111000"; attribute LC_LOW_BIT_POS_PROBE_OUT200 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011101100"; attribute LC_LOW_BIT_POS_PROBE_OUT201 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011101101"; attribute LC_LOW_BIT_POS_PROBE_OUT202 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011101110"; attribute LC_LOW_BIT_POS_PROBE_OUT203 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011101111"; attribute LC_LOW_BIT_POS_PROBE_OUT204 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011110000"; attribute LC_LOW_BIT_POS_PROBE_OUT205 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011110001"; attribute LC_LOW_BIT_POS_PROBE_OUT206 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011110010"; attribute LC_LOW_BIT_POS_PROBE_OUT207 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011110011"; attribute LC_LOW_BIT_POS_PROBE_OUT208 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011110100"; attribute LC_LOW_BIT_POS_PROBE_OUT209 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011110101"; attribute LC_LOW_BIT_POS_PROBE_OUT21 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000111001"; attribute LC_LOW_BIT_POS_PROBE_OUT210 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011110110"; attribute LC_LOW_BIT_POS_PROBE_OUT211 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011110111"; attribute LC_LOW_BIT_POS_PROBE_OUT212 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011111000"; attribute LC_LOW_BIT_POS_PROBE_OUT213 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011111001"; attribute LC_LOW_BIT_POS_PROBE_OUT214 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011111010"; attribute LC_LOW_BIT_POS_PROBE_OUT215 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011111011"; attribute LC_LOW_BIT_POS_PROBE_OUT216 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011111100"; attribute LC_LOW_BIT_POS_PROBE_OUT217 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011111101"; attribute LC_LOW_BIT_POS_PROBE_OUT218 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011111110"; attribute LC_LOW_BIT_POS_PROBE_OUT219 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000100000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011111111"; attribute LC_LOW_BIT_POS_PROBE_OUT22 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000111010"; attribute LC_LOW_BIT_POS_PROBE_OUT220 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000100000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000100000000"; attribute LC_LOW_BIT_POS_PROBE_OUT221 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000100000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000100000001"; attribute LC_LOW_BIT_POS_PROBE_OUT222 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000100000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000100000010"; attribute LC_LOW_BIT_POS_PROBE_OUT223 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000100000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000100000011"; attribute LC_LOW_BIT_POS_PROBE_OUT224 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000100000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000100000100"; attribute LC_LOW_BIT_POS_PROBE_OUT225 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000100000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000100000101"; attribute LC_LOW_BIT_POS_PROBE_OUT226 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000100000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000100000110"; attribute LC_LOW_BIT_POS_PROBE_OUT227 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000100001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000100000111"; attribute LC_LOW_BIT_POS_PROBE_OUT228 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000100001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000100001000"; attribute LC_LOW_BIT_POS_PROBE_OUT229 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000100001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000100001001"; attribute LC_LOW_BIT_POS_PROBE_OUT23 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000111011"; attribute LC_LOW_BIT_POS_PROBE_OUT230 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000100001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000100001010"; attribute LC_LOW_BIT_POS_PROBE_OUT231 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000100001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000100001011"; attribute LC_LOW_BIT_POS_PROBE_OUT232 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000100001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000100001100"; attribute LC_LOW_BIT_POS_PROBE_OUT233 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000100001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000100001101"; attribute LC_LOW_BIT_POS_PROBE_OUT234 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000100001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000100001110"; attribute LC_LOW_BIT_POS_PROBE_OUT235 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000100010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000100001111"; attribute LC_LOW_BIT_POS_PROBE_OUT236 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000100010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000100010000"; attribute LC_LOW_BIT_POS_PROBE_OUT237 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000100010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000100010001"; attribute LC_LOW_BIT_POS_PROBE_OUT238 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000100010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000100010010"; attribute LC_LOW_BIT_POS_PROBE_OUT239 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000100010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000100010011"; attribute LC_LOW_BIT_POS_PROBE_OUT24 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000111100"; attribute LC_LOW_BIT_POS_PROBE_OUT240 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000100010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000100010100"; attribute LC_LOW_BIT_POS_PROBE_OUT241 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000100010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000100010101"; attribute LC_LOW_BIT_POS_PROBE_OUT242 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000100010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000100010110"; attribute LC_LOW_BIT_POS_PROBE_OUT243 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000100011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000100010111"; attribute LC_LOW_BIT_POS_PROBE_OUT244 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000100011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000100011000"; attribute LC_LOW_BIT_POS_PROBE_OUT245 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000100011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000100011001"; attribute LC_LOW_BIT_POS_PROBE_OUT246 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000100011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000100011010"; attribute LC_LOW_BIT_POS_PROBE_OUT247 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000100011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000100011011"; attribute LC_LOW_BIT_POS_PROBE_OUT248 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000100011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000100011100"; attribute LC_LOW_BIT_POS_PROBE_OUT249 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000100011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000100011101"; attribute LC_LOW_BIT_POS_PROBE_OUT25 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000111101"; attribute LC_LOW_BIT_POS_PROBE_OUT250 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000100011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000100011110"; attribute LC_LOW_BIT_POS_PROBE_OUT251 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000100100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000100011111"; attribute LC_LOW_BIT_POS_PROBE_OUT252 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000100100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000100100000"; attribute LC_LOW_BIT_POS_PROBE_OUT253 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000100100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000100100001"; attribute LC_LOW_BIT_POS_PROBE_OUT254 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000100100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000100100010"; attribute LC_LOW_BIT_POS_PROBE_OUT255 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000100100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000100100011"; attribute LC_LOW_BIT_POS_PROBE_OUT26 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000111110"; attribute LC_LOW_BIT_POS_PROBE_OUT27 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000001000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000111111"; attribute LC_LOW_BIT_POS_PROBE_OUT28 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000001000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000001000000"; attribute LC_LOW_BIT_POS_PROBE_OUT29 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000001000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000001000001"; attribute LC_LOW_BIT_POS_PROBE_OUT3 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000100011"; attribute LC_LOW_BIT_POS_PROBE_OUT30 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000001000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000001000010"; attribute LC_LOW_BIT_POS_PROBE_OUT31 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000001000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000001000011"; attribute LC_LOW_BIT_POS_PROBE_OUT32 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000001000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000001000100"; attribute LC_LOW_BIT_POS_PROBE_OUT33 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000001000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000001000101"; attribute LC_LOW_BIT_POS_PROBE_OUT34 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000001000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000001000110"; attribute LC_LOW_BIT_POS_PROBE_OUT35 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000001001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000001000111"; attribute LC_LOW_BIT_POS_PROBE_OUT36 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000001001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000001001000"; attribute LC_LOW_BIT_POS_PROBE_OUT37 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000001001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000001001001"; attribute LC_LOW_BIT_POS_PROBE_OUT38 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000001001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000001001010"; attribute LC_LOW_BIT_POS_PROBE_OUT39 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000001001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000001001011"; attribute LC_LOW_BIT_POS_PROBE_OUT4 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000100101"; attribute LC_LOW_BIT_POS_PROBE_OUT40 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000001001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000001001100"; attribute LC_LOW_BIT_POS_PROBE_OUT41 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000001001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000001001101"; attribute LC_LOW_BIT_POS_PROBE_OUT42 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000001001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000001001110"; attribute LC_LOW_BIT_POS_PROBE_OUT43 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000001010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000001001111"; attribute LC_LOW_BIT_POS_PROBE_OUT44 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000001010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000001010000"; attribute LC_LOW_BIT_POS_PROBE_OUT45 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000001010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000001010001"; attribute LC_LOW_BIT_POS_PROBE_OUT46 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000001010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000001010010"; attribute LC_LOW_BIT_POS_PROBE_OUT47 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000001010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000001010011"; attribute LC_LOW_BIT_POS_PROBE_OUT48 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000001010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000001010100"; attribute LC_LOW_BIT_POS_PROBE_OUT49 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000001010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000001010101"; attribute LC_LOW_BIT_POS_PROBE_OUT5 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000101001"; attribute LC_LOW_BIT_POS_PROBE_OUT50 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000001010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000001010110"; attribute LC_LOW_BIT_POS_PROBE_OUT51 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000001011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000001010111"; attribute LC_LOW_BIT_POS_PROBE_OUT52 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000001011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000001011000"; attribute LC_LOW_BIT_POS_PROBE_OUT53 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000001011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000001011001"; attribute LC_LOW_BIT_POS_PROBE_OUT54 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000001011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000001011010"; attribute LC_LOW_BIT_POS_PROBE_OUT55 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000001011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000001011011"; attribute LC_LOW_BIT_POS_PROBE_OUT56 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000001011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000001011100"; attribute LC_LOW_BIT_POS_PROBE_OUT57 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000001011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000001011101"; attribute LC_LOW_BIT_POS_PROBE_OUT58 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000001011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000001011110"; attribute LC_LOW_BIT_POS_PROBE_OUT59 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000001100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000001011111"; attribute LC_LOW_BIT_POS_PROBE_OUT6 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000101010"; attribute LC_LOW_BIT_POS_PROBE_OUT60 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000001100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000001100000"; attribute LC_LOW_BIT_POS_PROBE_OUT61 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000001100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000001100001"; attribute LC_LOW_BIT_POS_PROBE_OUT62 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000001100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000001100010"; attribute LC_LOW_BIT_POS_PROBE_OUT63 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000001100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000001100011"; attribute LC_LOW_BIT_POS_PROBE_OUT64 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001100101"; + attribute LC_LOW_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001100100"; attribute LC_LOW_BIT_POS_PROBE_OUT65 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001100101"; attribute LC_LOW_BIT_POS_PROBE_OUT66 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001100111"; + attribute LC_LOW_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001100110"; attribute LC_LOW_BIT_POS_PROBE_OUT67 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001101000"; + attribute LC_LOW_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001100111"; attribute LC_LOW_BIT_POS_PROBE_OUT68 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001101001"; + attribute LC_LOW_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001101000"; attribute LC_LOW_BIT_POS_PROBE_OUT69 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001101001"; attribute LC_LOW_BIT_POS_PROBE_OUT7 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000101011"; attribute LC_LOW_BIT_POS_PROBE_OUT70 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001101010"; attribute LC_LOW_BIT_POS_PROBE_OUT71 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001101011"; attribute LC_LOW_BIT_POS_PROBE_OUT72 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001101100"; attribute LC_LOW_BIT_POS_PROBE_OUT73 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001101101"; attribute LC_LOW_BIT_POS_PROBE_OUT74 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001101110"; attribute LC_LOW_BIT_POS_PROBE_OUT75 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001101111"; attribute LC_LOW_BIT_POS_PROBE_OUT76 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001110000"; attribute LC_LOW_BIT_POS_PROBE_OUT77 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001110001"; attribute LC_LOW_BIT_POS_PROBE_OUT78 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001110010"; attribute LC_LOW_BIT_POS_PROBE_OUT79 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001110011"; attribute LC_LOW_BIT_POS_PROBE_OUT8 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000101100"; attribute LC_LOW_BIT_POS_PROBE_OUT80 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001110100"; attribute LC_LOW_BIT_POS_PROBE_OUT81 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001110101"; attribute LC_LOW_BIT_POS_PROBE_OUT82 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001110110"; attribute LC_LOW_BIT_POS_PROBE_OUT83 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001110111"; attribute LC_LOW_BIT_POS_PROBE_OUT84 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001111000"; attribute LC_LOW_BIT_POS_PROBE_OUT85 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001111001"; attribute LC_LOW_BIT_POS_PROBE_OUT86 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001111010"; attribute LC_LOW_BIT_POS_PROBE_OUT87 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001111011"; attribute LC_LOW_BIT_POS_PROBE_OUT88 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001111100"; attribute LC_LOW_BIT_POS_PROBE_OUT89 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001111101"; attribute LC_LOW_BIT_POS_PROBE_OUT9 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000101101"; attribute LC_LOW_BIT_POS_PROBE_OUT90 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001111110"; attribute LC_LOW_BIT_POS_PROBE_OUT91 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000010000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001111111"; attribute LC_LOW_BIT_POS_PROBE_OUT92 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000010000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000010000000"; attribute LC_LOW_BIT_POS_PROBE_OUT93 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000010000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000010000001"; attribute LC_LOW_BIT_POS_PROBE_OUT94 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000010000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000010000010"; attribute LC_LOW_BIT_POS_PROBE_OUT95 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000010000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000010000011"; attribute LC_LOW_BIT_POS_PROBE_OUT96 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000010000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000010000100"; attribute LC_LOW_BIT_POS_PROBE_OUT97 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000010000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000010000101"; attribute LC_LOW_BIT_POS_PROBE_OUT98 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000010000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000010000110"; attribute LC_LOW_BIT_POS_PROBE_OUT99 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000010001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000010000111"; attribute LC_PROBE_IN_WIDTH_STRING : string; attribute LC_PROBE_IN_WIDTH_STRING of inst : label is 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attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string; - attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of inst : label is 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+ attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of inst : label is 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attribute LC_PROBE_OUT_INIT_VAL_STRING : string; - attribute LC_PROBE_OUT_INIT_VAL_STRING of inst : label is "293'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000"; + attribute LC_PROBE_OUT_INIT_VAL_STRING of inst : label is "292'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000010"; attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string; - attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of inst : label is 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+ attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of inst : label is 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attribute LC_PROBE_OUT_WIDTH_STRING : string; - attribute LC_PROBE_OUT_WIDTH_STRING of inst : label is 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+ attribute LC_PROBE_OUT_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000001000111110000000000000001"; attribute LC_TOTAL_PROBE_IN_WIDTH : integer; attribute LC_TOTAL_PROBE_IN_WIDTH of inst : label is 0; attribute LC_TOTAL_PROBE_OUT_WIDTH : integer; - attribute LC_TOTAL_PROBE_OUT_WIDTH of inst : label is 42; + attribute LC_TOTAL_PROBE_OUT_WIDTH of inst : label is 41; attribute syn_noprune : string; attribute syn_noprune of inst : label is "1"; begin @@ -12988,7 +12953,7 @@ inst: entity work.vio_manual_ctrl_vio_v3_0_20_vio probe_in97(0) => '0', probe_in98(0) => '0', probe_in99(0) => '0', - probe_out0(2 downto 0) => probe_out0(2 downto 0), + probe_out0(1 downto 0) => probe_out0(1 downto 0), probe_out1(0) => probe_out1(0), probe_out10(0) => NLW_inst_probe_out10_UNCONNECTED(0), probe_out100(0) => NLW_inst_probe_out100_UNCONNECTED(0), diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.v index 89b68089..753fedff 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.v +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:34:28 2023 +// Date : Tue Mar 21 22:54:43 2023 // Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) // Command : write_verilog -force -mode synth_stub -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v +// D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v // Design : vio_manual_ctrl // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 @@ -16,9 +16,9 @@ (* X_CORE_INFO = "vio,Vivado 2019.1.3" *) module vio_manual_ctrl(clk, probe_out0, probe_out1, probe_out2, probe_out3, probe_out4) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */; +/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */; input clk; - output [2:0]probe_out0; + output [1:0]probe_out0; output [0:0]probe_out1; output [31:0]probe_out2; output [1:0]probe_out3; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.vhdl index 762f1d28..31ef8c8c 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.vhdl +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:34:28 2023 +-- Date : Tue Mar 21 22:54:43 2023 -- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode synth_stub --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl +-- D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl -- Design : vio_manual_ctrl -- Purpose : Stub declaration of top-level module interface -- Device : xc7k410tffg900-2 @@ -15,7 +15,7 @@ use IEEE.STD_LOGIC_1164.ALL; entity vio_manual_ctrl is Port ( clk : in STD_LOGIC; - probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); @@ -28,7 +28,7 @@ architecture stub of vio_manual_ctrl is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; begin diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/README.txt deleted file mode 100644 index f3d66c82..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/README.txt +++ /dev/null @@ -1,83 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required -# to simulate the design for a simulator, the directory structure -# and the generated exported files. -# -################################################################################ - -1. Simulate Design - -To simulate design, cd to the simulator directory and execute the script. - -For example:- - -% cd questa -% ./top.sh - -The export simulation flow requires the Xilinx pre-compiled simulation library -components for the target simulator. These components are referred using the -'-lib_map_path' switch. If this switch is specified, then the export simulation -will automatically set this library path in the generated script and update, -copy the simulator setup file(s) in the exported directory. - -If '-lib_map_path' is not specified, then the pre-compiled simulation library -information will not be included in the exported scripts and that may cause -simulation errors when running this script. Alternatively, you can provide the -library information using this switch while executing the generated script. - -For example:- - -% ./top.sh -lib_map_path /design/questa/clibs - -Please refer to the generated script header 'Prerequisite' section for more details. - -2. Directory Structure - -By default, if the -directory switch is not specified, export_simulation will -create the following directory structure:- - -/export_sim/ - -For example, if the current working directory is /tmp/test, export_simulation -will create the following directory path:- - -/tmp/test/export_sim/questa - -If -directory switch is specified, export_simulation will create a simulator -sub-directory under the specified directory path. - -For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' -command will create the following directory:- - -/tmp/test/my_test_area/func_sim/questa - -By default, if -simulator is not specified, export_simulation will create a -simulator sub-directory for each simulator and export the files for each simulator -in this sub-directory respectively. - -IMPORTANT: Please note that the simulation library path must be specified manually -in the generated script for the respective simulator. Please refer to the generated -script header 'Prerequisite' section for more details. - -3. Exported script and files - -Export simulation will create the driver shell script, setup files and copy the -design sources in the output directory path. - -By default, when the -script_name switch is not specified, export_simulation will -create the following script name:- - -.sh (Unix) -When exporting the files for an IP using the -of_objects switch, export_simulation -will create the following script name:- - -.sh (Unix) -Export simulation will create the setup files for the target simulator specified -with the -simulator switch. - -For example, if the target simulator is "ies", export_simulation will create the -'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' -file. - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/COSLUT_10_16bit.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/COSLUT_10_16bit.mif deleted file mode 100644 index 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-000000000000000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/COSLUT_10_16bit.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/COSLUT_10_16bit.sh deleted file mode 100644 index fdacf154..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/COSLUT_10_16bit.sh +++ /dev/null @@ -1,154 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : COSLUT_10_16bit.sh -# Simulator : Aldec Active-HDL Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:35:15 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: COSLUT_10_16bit.sh [-help] -# usage: COSLUT_10_16bit.sh [-lib_map_path] -# usage: COSLUT_10_16bit.sh [-noclean_files] -# usage: COSLUT_10_16bit.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'COSLUT_10_16bit.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "COSLUT_10_16bit.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - runvsimsa -l simulate.log -do "do {simulate.do}" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./COSLUT_10_16bit.sh -help\" for more information)\n" - exit 1 - fi - map_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - map_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Map library.cfg file -map_setup_file() -{ - file="library.cfg" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then - lib_map_path="$1" - else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - vmap -link $lib_map_path - fi - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./COSLUT_10_16bit.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: COSLUT_10_16bit.sh [-help]\n\ -Usage: COSLUT_10_16bit.sh [-lib_map_path]\n\ -Usage: COSLUT_10_16bit.sh [-reset_run]\n\ -Usage: COSLUT_10_16bit.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/COSLUT_10_16bit.udo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/COSLUT_10_16bit.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/README.txt deleted file mode 100644 index c007b0f1..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:35:15 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./COSLUT_10_16bit.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './COSLUT_10_16bit.sh' script. - -./COSLUT_10_16bit.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./COSLUT_10_16bit.sh -noclean_files - -For more information on the script, please type './COSLUT_10_16bit.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/compile.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/compile.do deleted file mode 100644 index fb8165a0..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/compile.do +++ /dev/null @@ -1,27 +0,0 @@ -vlib work -vlib activehdl - -vlib activehdl/xil_defaultlib -vlib activehdl/xpm -vlib activehdl/blk_mem_gen_v8_4_3 - -vmap xil_defaultlib activehdl/xil_defaultlib -vmap xpm activehdl/xpm -vmap blk_mem_gen_v8_4_3 activehdl/blk_mem_gen_v8_4_3 - -vlog -work xil_defaultlib -sv2k12 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -93 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work blk_mem_gen_v8_4_3 -v2k5 \ -"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ - -vlog -work xil_defaultlib -v2k5 \ -"../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/cos_8192_18bit.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/cos_8192_18bit.coe deleted file mode 100644 index 1568f12a..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/cos_8192_18bit.coe +++ /dev/null @@ -1,8194 +0,0 @@ -memory_initialization_radix=10; -memory_initialization_vector= -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131070 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-1659 -1634 -1609 -1584 -1558 -1533 -1508 -1483 -1458 -1433 -1408 -1382 -1357 -1332 -1307 -1282 -1257 -1232 -1206 -1181 -1156 -1131 -1106 -1081 -1056 -1031 -1005 -980 -955 -930 -905 -880 -855 -829 -804 -779 -754 -729 -704 -679 -654 -628 -603 -578 -553 -528 -503 -478 -452 -427 -402 -377 -352 -327 -302 -276 -251 -226 -201 -176 -151 -126 -101 -75 -50 -25 -0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/file_info.txt deleted file mode 100644 index a5ce948f..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, -COSLUT_10_16bit.v,verilog,xil_defaultlib,../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/simulate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/simulate.do deleted file mode 100644 index 2d1b6265..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/simulate.do +++ /dev/null @@ -1,17 +0,0 @@ -onbreak {quit -force} -onerror {quit -force} - -asim -t 1ps +access +r +m+COSLUT_10_16bit -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.COSLUT_10_16bit xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure - -do {COSLUT_10_16bit.udo} - -run -all - -endsim - -quit -force diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/wave.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/activehdl/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/COSLUT_10_16bit.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/COSLUT_10_16bit.mif deleted file mode 100644 index af6c440d..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/COSLUT_10_16bit.mif +++ /dev/null @@ -1,8192 +0,0 @@ -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 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-000000001110001001 -000000001101110000 -000000001101010111 -000000001100111101 -000000001100100100 -000000001100001011 -000000001011110010 -000000001011011001 -000000001011000000 -000000001010100111 -000000001010001110 -000000001001110100 -000000001001011011 -000000001001000010 -000000001000101001 -000000001000010000 -000000000111110111 -000000000111011110 -000000000111000100 -000000000110101011 -000000000110010010 -000000000101111001 -000000000101100000 -000000000101000111 -000000000100101110 -000000000100010100 -000000000011111011 -000000000011100010 -000000000011001001 -000000000010110000 -000000000010010111 -000000000001111110 -000000000001100101 -000000000001001011 -000000000000110010 -000000000000011001 -000000000000000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/COSLUT_10_16bit.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/COSLUT_10_16bit.sh deleted file mode 100644 index c5969cd8..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/COSLUT_10_16bit.sh +++ /dev/null @@ -1,175 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : COSLUT_10_16bit.sh -# Simulator : Cadence Incisive Enterprise Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:35:15 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: COSLUT_10_16bit.sh [-help] -# usage: COSLUT_10_16bit.sh [-lib_map_path] -# usage: COSLUT_10_16bit.sh [-noclean_files] -# usage: COSLUT_10_16bit.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'COSLUT_10_16bit.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Set the compiled library directory -ref_lib_dir="." - -# Command line options -irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" - -# Design libraries -design_libs=(xil_defaultlib xpm blk_mem_gen_v8_4_3) - -# Simulation root library directory -sim_lib_dir="ies_lib" - -# Script info -echo -e "COSLUT_10_16bit.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - execute -} - -# RUN_STEP: -execute() -{ - irun $irun_opts \ - -reflib "$ref_lib_dir/unisim:unisim" \ - -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ - -reflib "$ref_lib_dir/secureip:secureip" \ - -reflib "$ref_lib_dir/unimacro:unimacro" \ - -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.COSLUT_10_16bit \ - -f run.f \ - -top glbl \ - glbl.v -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./COSLUT_10_16bit.sh -help\" for more information)\n" - exit 1 - else - ref_lib_dir=$2 - fi - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./COSLUT_10_16bit.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: COSLUT_10_16bit.sh [-help]\n\ -Usage: COSLUT_10_16bit.sh [-lib_map_path]\n\ -Usage: COSLUT_10_16bit.sh [-reset_run]\n\ -Usage: COSLUT_10_16bit.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/README.txt deleted file mode 100644 index bfa3fc14..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/README.txt +++ /dev/null @@ -1,48 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:35:15 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./COSLUT_10_16bit.sh - -This command will launch the 'execute' function for the single-step flow. This -function is called from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './COSLUT_10_16bit.sh' script. - -./COSLUT_10_16bit.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./COSLUT_10_16bit.sh -noclean_files - -For more information on the script, please type './COSLUT_10_16bit.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/cos_8192_18bit.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/cos_8192_18bit.coe deleted file mode 100644 index 1568f12a..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/cos_8192_18bit.coe +++ /dev/null @@ -1,8194 +0,0 @@ -memory_initialization_radix=10; -memory_initialization_vector= -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131069 -131069 -131069 -131069 -131069 -131069 -131069 -131069 -131068 -131068 -131068 -131068 -131068 -131068 -131067 -131067 -131067 -131067 -131067 -131066 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-930 -905 -880 -855 -829 -804 -779 -754 -729 -704 -679 -654 -628 -603 -578 -553 -528 -503 -478 -452 -427 -402 -377 -352 -327 -302 -276 -251 -226 -201 -176 -151 -126 -101 -75 -50 -25 -0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/file_info.txt deleted file mode 100644 index a5ce948f..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, -COSLUT_10_16bit.v,verilog,xil_defaultlib,../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/run.f b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/run.f deleted file mode 100644 index 12f6547e..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/ies/run.f +++ /dev/null @@ -1,17 +0,0 @@ --makelib ies_lib/xil_defaultlib -sv \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ --endlib --makelib ies_lib/xpm \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ --endlib --makelib ies_lib/blk_mem_gen_v8_4_3 \ - "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ --endlib --makelib ies_lib/xil_defaultlib \ - "../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v" \ --endlib --makelib ies_lib/xil_defaultlib \ - glbl.v --endlib - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/COSLUT_10_16bit.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/COSLUT_10_16bit.mif deleted file mode 100644 index af6c440d..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/COSLUT_10_16bit.mif +++ /dev/null @@ -1,8192 +0,0 @@ -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111101 -011111111111111101 -011111111111111101 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-000000000101000111 -000000000100101110 -000000000100010100 -000000000011111011 -000000000011100010 -000000000011001001 -000000000010110000 -000000000010010111 -000000000001111110 -000000000001100101 -000000000001001011 -000000000000110010 -000000000000011001 -000000000000000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/COSLUT_10_16bit.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/COSLUT_10_16bit.sh deleted file mode 100644 index 65bfc458..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/COSLUT_10_16bit.sh +++ /dev/null @@ -1,167 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : COSLUT_10_16bit.sh -# Simulator : Mentor Graphics ModelSim Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:35:15 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: COSLUT_10_16bit.sh [-help] -# usage: COSLUT_10_16bit.sh [-lib_map_path] -# usage: COSLUT_10_16bit.sh [-noclean_files] -# usage: COSLUT_10_16bit.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'COSLUT_10_16bit.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "COSLUT_10_16bit.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - vsim -64 -c -do "do {simulate.do}" -l simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./COSLUT_10_16bit.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Copy modelsim.ini file -copy_setup_file() -{ - file="modelsim.ini" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - else - lib_map_path="C:/Mentor/CompLib/2019.1.3" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - cp $src_file . - fi -} - -# Create design library directory -create_lib_dir() -{ - lib_dir="modelsim_lib" - if [[ -e $lib_dir ]]; then - rm -rf $lib_dir - fi - - mkdir $lib_dir - -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./COSLUT_10_16bit.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: COSLUT_10_16bit.sh [-help]\n\ -Usage: COSLUT_10_16bit.sh [-lib_map_path]\n\ -Usage: COSLUT_10_16bit.sh [-reset_run]\n\ -Usage: COSLUT_10_16bit.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/COSLUT_10_16bit.udo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/COSLUT_10_16bit.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/README.txt deleted file mode 100644 index c007b0f1..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:35:15 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./COSLUT_10_16bit.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './COSLUT_10_16bit.sh' script. - -./COSLUT_10_16bit.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./COSLUT_10_16bit.sh -noclean_files - -For more information on the script, please type './COSLUT_10_16bit.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/compile.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/compile.do deleted file mode 100644 index aea10ac9..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/compile.do +++ /dev/null @@ -1,14 +0,0 @@ -vlib modelsim_lib/work -vlib modelsim_lib/msim - -vlib modelsim_lib/msim/xil_defaultlib - -vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib - -vlog -work xil_defaultlib -64 -incr \ -"../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v" \ - - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/cos_8192_18bit.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/cos_8192_18bit.coe deleted file mode 100644 index 1568f12a..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/cos_8192_18bit.coe +++ /dev/null @@ -1,8194 +0,0 @@ -memory_initialization_radix=10; -memory_initialization_vector= -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131069 -131069 -131069 -131069 -131069 -131069 -131069 -131069 -131068 -131068 -131068 -131068 -131068 -131068 -131067 -131067 -131067 -131067 -131067 -131066 -131066 -131066 -131066 -131065 -131065 -131065 -131065 -131064 -131064 -131064 -131064 -131063 -131063 -131063 -131063 -131062 -131062 -131062 -131061 -131061 -131061 -131061 -131060 -131060 -131060 -131059 -131059 -131059 -131058 -131058 -131057 -131057 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a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/file_info.txt deleted file mode 100644 index 28a0c037..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/file_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -COSLUT_10_16bit.v,verilog,xil_defaultlib,../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/modelsim.ini b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/modelsim.ini deleted file mode 100644 index 04a43f2c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/modelsim.ini +++ /dev/null @@ -1,2590 +0,0 @@ -; vsim modelsim.ini file -[Version] -INIVersion = "2020.4" - -; Copyright 1991-2020 Mentor Graphics Corporation -; -; All Rights Reserved. -; -; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF -; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. -; - -[Library] -others = $MODEL_TECH/../modelsim.ini -; -; VITAL concerns: -; -; The library ieee contains (among other packages) the packages of the -; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use -; the physical library ieee (recommended), or use the physical library -; vital2000, but not both. The design can use logical library ieee and/or -; vital2000 as long as each of these maps to the same physical library, either -; ieee or vital2000. -; -; A design using the 1995 version of the VITAL packages, whether or not -; it also uses the 2000 version of the VITAL packages, must have logical library -; name ieee mapped to physical library vital1995. (A design cannot use library -; vital1995 directly because some packages in this library use logical name ieee -; when referring to the other packages in the library.) The design source -; should use logical name ieee when referring to any packages there except the -; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical -; name vital2000 (mapped to physical library vital2000) to refer to those -; packages. -; ieee = $MODEL_TECH/../vital1995 -; -; For compatiblity with previous releases, logical library name vital2000 maps -; to library vital2000 (a different library than library ieee, containing the -; same packages). -; A design should not reference VITAL from both the ieee library and the -; vital2000 library because the vital packages are effectively different. -; A design that references both the ieee and vital2000 libraries must have -; both logical names ieee and vital2000 mapped to the same library, either of -; these: -; $MODEL_TECH/../ieee -; $MODEL_TECH/../vital2000 -; - -; added mapping for ADMS - -;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release -;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release -;mvc_lib = $MODEL_TECH/../mvc_lib - -; Automatically perform logical->physical mapping for physical libraries that -; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). -; The tail of the filesystem path name is chosen as the logical library name. -; For example, in the command "vopt -L ./path/to/lib1 -o opttop top", -; vopt automatically performs the mapping "lib1 -> ./path/to/lib1". -; See the User Manual for more details. -; -; AutoLibMapping = 0 - -secureip = C:/Mentor/CompLib/2019.1.3/secureip -unisim = C:/Mentor/CompLib/2019.1.3/unisim -unimacro = C:/Mentor/CompLib/2019.1.3/unimacro -unifast = C:/Mentor/CompLib/2019.1.3/unifast -unisims_ver = C:/Mentor/CompLib/2019.1.3/unisims_ver -unimacro_ver = C:/Mentor/CompLib/2019.1.3/unimacro_ver -unifast_ver = C:/Mentor/CompLib/2019.1.3/unifast_ver -simprims_ver = C:/Mentor/CompLib/2019.1.3/simprims_ver -xpm = C:/Mentor/CompLib/2019.1.3/xpm -xilinx_vip = C:/Mentor/CompLib/2019.1.3/xilinx_vip -advanced_io_wizard_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/advanced_io_wizard_phy_v1_0_0 -advanced_io_wizard_v1_0_0 = C:/Mentor/CompLib/2019.1.3/advanced_io_wizard_v1_0_0 -ahblite_axi_bridge_v3_0_14 = C:/Mentor/CompLib/2019.1.3/ahblite_axi_bridge_v3_0_14 -ai_noc = C:/Mentor/CompLib/2019.1.3/ai_noc -ai_pl_trig = C:/Mentor/CompLib/2019.1.3/ai_pl_trig -ai_pl = C:/Mentor/CompLib/2019.1.3/ai_pl -audio_clock_recovery_v1_0 = C:/Mentor/CompLib/2019.1.3/audio_clock_recovery_v1_0 -audio_tpg_v1_0_0 = C:/Mentor/CompLib/2019.1.3/audio_tpg_v1_0_0 -av_pat_gen_v1_0_0 = C:/Mentor/CompLib/2019.1.3/av_pat_gen_v1_0_0 -axis_infrastructure_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axis_infrastructure_v1_1_0 -axis_protocol_checker_v2_0_3 = C:/Mentor/CompLib/2019.1.3/axis_protocol_checker_v2_0_3 -axi_ahblite_bridge_v3_0_16 = C:/Mentor/CompLib/2019.1.3/axi_ahblite_bridge_v3_0_16 -axi_amm_bridge_v1_0_9 = C:/Mentor/CompLib/2019.1.3/axi_amm_bridge_v1_0_9 -axi_bram_ctrl_v4_1_1 = C:/Mentor/CompLib/2019.1.3/axi_bram_ctrl_v4_1_1 -axi_chip2chip_v5_0_6 = C:/Mentor/CompLib/2019.1.3/axi_chip2chip_v5_0_6 -axi_dbg_hub = C:/Mentor/CompLib/2019.1.3/axi_dbg_hub -axi_infrastructure_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axi_infrastructure_v1_1_0 -axi_jtag_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_jtag_v1_0_0 -axi_lite_ipif_v3_0_4 = C:/Mentor/CompLib/2019.1.3/axi_lite_ipif_v3_0_4 -axi_pcie3_v3_0_9 = C:/Mentor/CompLib/2019.1.3/axi_pcie3_v3_0_9 -axi_perf_mon_v5_0_21 = C:/Mentor/CompLib/2019.1.3/axi_perf_mon_v5_0_21 -axi_pmon_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_pmon_v1_0_0 -blk_mem_gen_v8_3_6 = C:/Mentor/CompLib/2019.1.3/blk_mem_gen_v8_3_6 -blk_mem_gen_v8_4_3 = C:/Mentor/CompLib/2019.1.3/blk_mem_gen_v8_4_3 -bsip_v1_1_0 = C:/Mentor/CompLib/2019.1.3/bsip_v1_1_0 -bs_mux_v1_0_0 = C:/Mentor/CompLib/2019.1.3/bs_mux_v1_0_0 -clk_gen_sim_v1_0_0 = C:/Mentor/CompLib/2019.1.3/clk_gen_sim_v1_0_0 -clk_vip_v1_0_2 = C:/Mentor/CompLib/2019.1.3/clk_vip_v1_0_2 -cmac_usplus_v2_4_5 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_4_5 -cmac_usplus_v2_5_3 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_5_3 -cmac_usplus_v2_6_2 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_6_2 -cmac_v2_3_5 = C:/Mentor/CompLib/2019.1.3/cmac_v2_3_5 -cmac_v2_4_1 = C:/Mentor/CompLib/2019.1.3/cmac_v2_4_1 -cmac_v2_5_1 = C:/Mentor/CompLib/2019.1.3/cmac_v2_5_1 -compact_gt_v1_0_5 = C:/Mentor/CompLib/2019.1.3/compact_gt_v1_0_5 -ddr4_pl_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/ddr4_pl_phy_v1_0_0 -ddr4_pl_v1_0_2 = C:/Mentor/CompLib/2019.1.3/ddr4_pl_v1_0_2 -dist_mem_gen_v8_0_13 = C:/Mentor/CompLib/2019.1.3/dist_mem_gen_v8_0_13 -ecc_v2_0_13 = C:/Mentor/CompLib/2019.1.3/ecc_v2_0_13 -emb_fifo_gen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/emb_fifo_gen_v1_0_1 -emb_mem_gen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/emb_mem_gen_v1_0_1 -emc_common_v3_0_5 = C:/Mentor/CompLib/2019.1.3/emc_common_v3_0_5 -ethernet_1_10_25g_v2_0_5 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_0_5 -ethernet_1_10_25g_v2_1_4 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_1_4 -ethernet_1_10_25g_v2_2_3 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_2_3 -ethernet_1_10_25g_v2_3_3 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_3_3 -fifo_generator_v13_0_6 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_0_6 -fifo_generator_v13_1_4 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_1_4 -fifo_generator_v13_2_4 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_2_4 -fit_timer_v2_0_10 = C:/Mentor/CompLib/2019.1.3/fit_timer_v2_0_10 -generic_baseblocks_v2_1_0 = C:/Mentor/CompLib/2019.1.3/generic_baseblocks_v2_1_0 -gigantic_mux = C:/Mentor/CompLib/2019.1.3/gigantic_mux -gig_ethernet_pcs_pma_v16_1_6 = C:/Mentor/CompLib/2019.1.3/gig_ethernet_pcs_pma_v16_1_6 -gmii_to_rgmii_v4_0_7 = C:/Mentor/CompLib/2019.1.3/gmii_to_rgmii_v4_0_7 -gtwizard_ultrascale_v1_5_4 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_5_4 -gtwizard_ultrascale_v1_6_11 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_6_11 -gtwizard_ultrascale_v1_7_6 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_7_6 -hbm_v1_0_4 = C:/Mentor/CompLib/2019.1.3/hbm_v1_0_4 -hdcp22_cipher_dp_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdcp22_cipher_dp_v1_0_0 -hdcp22_cipher_v1_0_3 = C:/Mentor/CompLib/2019.1.3/hdcp22_cipher_v1_0_3 -hdcp22_rng_v1_0_1 = C:/Mentor/CompLib/2019.1.3/hdcp22_rng_v1_0_1 -hdcp_keymngmt_blk_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdcp_keymngmt_blk_v1_0_0 -hdcp_v1_0_3 = C:/Mentor/CompLib/2019.1.3/hdcp_v1_0_3 -hdmi_gt_controller_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdmi_gt_controller_v1_0_0 -high_speed_selectio_wiz_v3_2_3 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_2_3 -high_speed_selectio_wiz_v3_3_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_3_1 -high_speed_selectio_wiz_v3_4_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_4_1 -high_speed_selectio_wiz_v3_5_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_5_1 -i2s_receiver_v1_0_3 = C:/Mentor/CompLib/2019.1.3/i2s_receiver_v1_0_3 -i2s_transmitter_v1_0_3 = C:/Mentor/CompLib/2019.1.3/i2s_transmitter_v1_0_3 -ibert_lib_v1_0_6 = C:/Mentor/CompLib/2019.1.3/ibert_lib_v1_0_6 -ieee802d3_clause74_fec_v1_0_4 = C:/Mentor/CompLib/2019.1.3/ieee802d3_clause74_fec_v1_0_4 -interlaken_v2_4_3 = C:/Mentor/CompLib/2019.1.3/interlaken_v2_4_3 -in_system_ibert_v1_0_9 = C:/Mentor/CompLib/2019.1.3/in_system_ibert_v1_0_9 -iomodule_v3_1_4 = C:/Mentor/CompLib/2019.1.3/iomodule_v3_1_4 -jesd204c_v4_1_1 = C:/Mentor/CompLib/2019.1.3/jesd204c_v4_1_1 -jesd204_v7_2_6 = C:/Mentor/CompLib/2019.1.3/jesd204_v7_2_6 -jtag_axi = C:/Mentor/CompLib/2019.1.3/jtag_axi -lib_cdc_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_cdc_v1_0_2 -lib_pkg_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_pkg_v1_0_2 -lmb_bram_if_cntlr_v4_0_16 = C:/Mentor/CompLib/2019.1.3/lmb_bram_if_cntlr_v4_0_16 -lmb_v10_v3_0_9 = C:/Mentor/CompLib/2019.1.3/lmb_v10_v3_0_9 -ltlib_v1_0_0 = C:/Mentor/CompLib/2019.1.3/ltlib_v1_0_0 -lut_buffer_v1_0_0 = C:/Mentor/CompLib/2019.1.3/lut_buffer_v1_0_0 -lut_buffer_v2_0_0 = C:/Mentor/CompLib/2019.1.3/lut_buffer_v2_0_0 -l_ethernet_v2_3_5 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_3_5 -l_ethernet_v2_4_3 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_4_3 -l_ethernet_v2_5_2 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_5_2 -mammoth_transcode_v1_0_0 = C:/Mentor/CompLib/2019.1.3/mammoth_transcode_v1_0_0 -microblaze_v10_0_7 = C:/Mentor/CompLib/2019.1.3/microblaze_v10_0_7 -microblaze_v11_0_1 = C:/Mentor/CompLib/2019.1.3/microblaze_v11_0_1 -microblaze_v9_5_4 = C:/Mentor/CompLib/2019.1.3/microblaze_v9_5_4 -mii_to_rmii_v2_0_21 = C:/Mentor/CompLib/2019.1.3/mii_to_rmii_v2_0_21 -mipi_csi2_rx_ctrl_v1_0_8 = C:/Mentor/CompLib/2019.1.3/mipi_csi2_rx_ctrl_v1_0_8 -mipi_csi2_tx_ctrl_v1_0_4 = C:/Mentor/CompLib/2019.1.3/mipi_csi2_tx_ctrl_v1_0_4 -mipi_dphy_v4_1_4 = C:/Mentor/CompLib/2019.1.3/mipi_dphy_v4_1_4 -mipi_dsi_tx_ctrl_v1_0_7 = C:/Mentor/CompLib/2019.1.3/mipi_dsi_tx_ctrl_v1_0_7 -mrmac_v1_0_0 = C:/Mentor/CompLib/2019.1.3/mrmac_v1_0_0 -multi_channel_25g_rs_fec_v1_0_5 = C:/Mentor/CompLib/2019.1.3/multi_channel_25g_rs_fec_v1_0_5 -mutex_v2_1_10 = C:/Mentor/CompLib/2019.1.3/mutex_v2_1_10 -axi_tg_lib = C:/Mentor/CompLib/2019.1.3/axi_tg_lib -noc_na_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_na_v1_0_0 -noc_nidb_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nidb_v1_0_0 -noc_nmu_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nmu_v1_0_0 -noc_nps_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nps_v1_0_0 -nvmeha_v1_0_0 = C:/Mentor/CompLib/2019.1.3/nvmeha_v1_0_0 -oddr_v1_0_0 = C:/Mentor/CompLib/2019.1.3/oddr_v1_0_0 -pci32_v5_0_12 = C:/Mentor/CompLib/2019.1.3/pci32_v5_0_12 -pci64_v5_0_11 = C:/Mentor/CompLib/2019.1.3/pci64_v5_0_11 -pcie_jtag_v1_0_0 = C:/Mentor/CompLib/2019.1.3/pcie_jtag_v1_0_0 -pc_cfr_v6_0_8 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_0_8 -pc_cfr_v6_1_4 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_1_4 -pc_cfr_v6_2_2 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_2_2 -pc_cfr_v6_3_0 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_3_0 -picxo = C:/Mentor/CompLib/2019.1.3/picxo -qdma_v3_0_2 = C:/Mentor/CompLib/2019.1.3/qdma_v3_0_2 -rama_v1_1_2_lib = C:/Mentor/CompLib/2019.1.3/rama_v1_1_2_lib -rld3_pl_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/rld3_pl_phy_v1_0_0 -rld3_pl_v1_0_1 = C:/Mentor/CompLib/2019.1.3/rld3_pl_v1_0_1 -roe_framer_v2_0_1 = C:/Mentor/CompLib/2019.1.3/roe_framer_v2_0_1 -rst_vip_v1_0_3 = C:/Mentor/CompLib/2019.1.3/rst_vip_v1_0_3 -smartconnect_v1_0 = C:/Mentor/CompLib/2019.1.3/smartconnect_v1_0 -sd_fec_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sd_fec_v1_0_2 -sem_ultra_v3_1_11 = C:/Mentor/CompLib/2019.1.3/sem_ultra_v3_1_11 -sem_v4_1_12 = C:/Mentor/CompLib/2019.1.3/sem_v4_1_12 -shell_utils_msp432_bsl_crc_gen_v1_0_0 = C:/Mentor/CompLib/2019.1.3/shell_utils_msp432_bsl_crc_gen_v1_0_0 -sim_clk_gen_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sim_clk_gen_v1_0_2 -sim_rst_gen_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sim_rst_gen_v1_0_2 -sim_trig_top_v1_0 = C:/Mentor/CompLib/2019.1.3/sim_trig_top_v1_0 -stm_v1_0 = C:/Mentor/CompLib/2019.1.3/stm_v1_0 -stm_v1_0_0 = C:/Mentor/CompLib/2019.1.3/stm_v1_0_0 -system_cache_v4_0_6 = C:/Mentor/CompLib/2019.1.3/system_cache_v4_0_6 -ta_dma_v1_0_3 = C:/Mentor/CompLib/2019.1.3/ta_dma_v1_0_3 -tcc_decoder_3gpplte_v3_0_6 = C:/Mentor/CompLib/2019.1.3/tcc_decoder_3gpplte_v3_0_6 -ten_gig_eth_mac_v15_1_7 = C:/Mentor/CompLib/2019.1.3/ten_gig_eth_mac_v15_1_7 -ten_gig_eth_pcs_pma_v6_0_15 = C:/Mentor/CompLib/2019.1.3/ten_gig_eth_pcs_pma_v6_0_15 -timer_sync_1588_v1_2_4 = C:/Mentor/CompLib/2019.1.3/timer_sync_1588_v1_2_4 -tmr_inject_v1_0_3 = C:/Mentor/CompLib/2019.1.3/tmr_inject_v1_0_3 -tmr_manager_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tmr_manager_v1_0_4 -tmr_voter_v1_0_2 = C:/Mentor/CompLib/2019.1.3/tmr_voter_v1_0_2 -tsn_endpoint_ethernet_mac_block_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tsn_endpoint_ethernet_mac_block_v1_0_4 -uhdsdi_gt_v1_0_3 = C:/Mentor/CompLib/2019.1.3/uhdsdi_gt_v1_0_3 -uhdsdi_gt_v2_0_0 = C:/Mentor/CompLib/2019.1.3/uhdsdi_gt_v2_0_0 -usxgmii_v1_0_5 = C:/Mentor/CompLib/2019.1.3/usxgmii_v1_0_5 -usxgmii_v1_1_0 = C:/Mentor/CompLib/2019.1.3/usxgmii_v1_1_0 -util_idelay_ctrl_v1_0_1 = C:/Mentor/CompLib/2019.1.3/util_idelay_ctrl_v1_0_1 -util_reduced_logic_v2_0_4 = C:/Mentor/CompLib/2019.1.3/util_reduced_logic_v2_0_4 -util_vector_logic_v2_0_1 = C:/Mentor/CompLib/2019.1.3/util_vector_logic_v2_0_1 -ba317 = C:/Mentor/CompLib/2019.1.3/ba317 -vfb_v1_0_13 = C:/Mentor/CompLib/2019.1.3/vfb_v1_0_13 -video_frame_crc_v1_0_1 = C:/Mentor/CompLib/2019.1.3/video_frame_crc_v1_0_1 -vid_edid_v1_0_0 = C:/Mentor/CompLib/2019.1.3/vid_edid_v1_0_0 -vid_phy_controller_v2_1_5 = C:/Mentor/CompLib/2019.1.3/vid_phy_controller_v2_1_5 -vid_phy_controller_v2_2_3 = C:/Mentor/CompLib/2019.1.3/vid_phy_controller_v2_2_3 -v_axi4s_remap_v1_0_11 = C:/Mentor/CompLib/2019.1.3/v_axi4s_remap_v1_0_11 -v_csc_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_csc_v1_0_13 -v_deinterlacer_v4_0_12 = C:/Mentor/CompLib/2019.1.3/v_deinterlacer_v4_0_12 -v_deinterlacer_v5_0_13 = C:/Mentor/CompLib/2019.1.3/v_deinterlacer_v5_0_13 -v_demosaic_v1_0_5 = C:/Mentor/CompLib/2019.1.3/v_demosaic_v1_0_5 -v_frmbuf_rd_v2_1_2 = C:/Mentor/CompLib/2019.1.3/v_frmbuf_rd_v2_1_2 -v_frmbuf_wr_v2_1_2 = C:/Mentor/CompLib/2019.1.3/v_frmbuf_wr_v2_1_2 -v_gamma_lut_v1_0_5 = C:/Mentor/CompLib/2019.1.3/v_gamma_lut_v1_0_5 -v_hcresampler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_hcresampler_v1_0_13 -v_hdmi_rx_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_rx_v2_0_0 -v_hdmi_rx_v3_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_rx_v3_0_0 -v_hdmi_tx_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_tx_v2_0_0 -v_hdmi_tx_v3_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_tx_v3_0_0 -v_hscaler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_hscaler_v1_0_13 -v_letterbox_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_letterbox_v1_0_13 -v_mix_v3_0_3 = C:/Mentor/CompLib/2019.1.3/v_mix_v3_0_3 -v_mix_v4_0_0 = C:/Mentor/CompLib/2019.1.3/v_mix_v4_0_0 -v_multi_scaler_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_multi_scaler_v1_0_1 -v_scenechange_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_scenechange_v1_0_1 -v_sdi_rx_vid_bridge_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_sdi_rx_vid_bridge_v2_0_0 -v_smpte_sdi_v3_0_8 = C:/Mentor/CompLib/2019.1.3/v_smpte_sdi_v3_0_8 -v_smpte_uhdsdi_rx_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_rx_v1_0_0 -v_smpte_uhdsdi_tx_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_tx_v1_0_0 -v_smpte_uhdsdi_v1_0_7 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_v1_0_7 -v_tpg_v7_0_13 = C:/Mentor/CompLib/2019.1.3/v_tpg_v7_0_13 -v_tpg_v8_0_1 = C:/Mentor/CompLib/2019.1.3/v_tpg_v8_0_1 -v_uhdsdi_audio_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v1_0_0 -v_uhdsdi_audio_v1_1_0 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v1_1_0 -v_uhdsdi_audio_v2_0_1 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v2_0_1 -v_uhdsdi_vidgen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_vidgen_v1_0_1 -v_vcresampler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_vcresampler_v1_0_13 -v_vid_in_axi4s_v4_0_9 = C:/Mentor/CompLib/2019.1.3/v_vid_in_axi4s_v4_0_9 -v_vscaler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_vscaler_v1_0_13 -xaui_v12_3_6 = C:/Mentor/CompLib/2019.1.3/xaui_v12_3_6 -xbip_dsp48_wrapper_v3_0_4 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_wrapper_v3_0_4 -xbip_utils_v3_0_10 = C:/Mentor/CompLib/2019.1.3/xbip_utils_v3_0_10 -xdma_v4_1_3 = C:/Mentor/CompLib/2019.1.3/xdma_v4_1_3 -xhmc_v1_0_9 = C:/Mentor/CompLib/2019.1.3/xhmc_v1_0_9 -xlconcat_v2_1_3 = C:/Mentor/CompLib/2019.1.3/xlconcat_v2_1_3 -xlconstant_v1_1_6 = C:/Mentor/CompLib/2019.1.3/xlconstant_v1_1_6 -xlslice_v1_0_2 = C:/Mentor/CompLib/2019.1.3/xlslice_v1_0_2 -xsdbm_v2_0_0 = C:/Mentor/CompLib/2019.1.3/xsdbm_v2_0_0 -xsdbm_v3_0_0 = C:/Mentor/CompLib/2019.1.3/xsdbm_v3_0_0 -xxv_ethernet_v2_4_5 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v2_4_5 -xxv_ethernet_v2_5_3 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v2_5_3 -xxv_ethernet_v3_0_3 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v3_0_3 -zynq_ultra_ps_e_v3_2_3 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_v3_2_3 -zynq_ultra_ps_e_v3_3_0 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_v3_3_0 -lib_srl_fifo_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_srl_fifo_v1_0_2 -lib_fifo_v1_0_13 = C:/Mentor/CompLib/2019.1.3/lib_fifo_v1_0_13 -axi_datamover_v5_1_21 = C:/Mentor/CompLib/2019.1.3/axi_datamover_v5_1_21 -amm_axi_bridge_v1_0_5 = C:/Mentor/CompLib/2019.1.3/amm_axi_bridge_v1_0_5 -axis_interconnect_v1_1_17 = C:/Mentor/CompLib/2019.1.3/axis_interconnect_v1_1_17 -ats_switch_v1_0_2 = C:/Mentor/CompLib/2019.1.3/ats_switch_v1_0_2 -audio_formatter_v1_0_1 = C:/Mentor/CompLib/2019.1.3/audio_formatter_v1_0_1 -axi4stream_vip_v1_1_5 = C:/Mentor/CompLib/2019.1.3/axi4stream_vip_v1_1_5 -v_tc_v6_1_13 = C:/Mentor/CompLib/2019.1.3/v_tc_v6_1_13 -v_axi4s_vid_out_v4_0_10 = C:/Mentor/CompLib/2019.1.3/v_axi4s_vid_out_v4_0_10 -axi4svideo_bridge_v1_0_10 = C:/Mentor/CompLib/2019.1.3/axi4svideo_bridge_v1_0_10 -axis_accelerator_adapter_v2_1_15 = C:/Mentor/CompLib/2019.1.3/axis_accelerator_adapter_v2_1_15 -axis_broadcaster_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axis_broadcaster_v1_1_18 -axis_clock_converter_v1_1_20 = C:/Mentor/CompLib/2019.1.3/axis_clock_converter_v1_1_20 -axis_combiner_v1_1_17 = C:/Mentor/CompLib/2019.1.3/axis_combiner_v1_1_17 -axis_data_fifo_v1_1_20 = C:/Mentor/CompLib/2019.1.3/axis_data_fifo_v1_1_20 -axis_data_fifo_v2_0_1 = C:/Mentor/CompLib/2019.1.3/axis_data_fifo_v2_0_1 -axis_register_slice_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_register_slice_v1_1_19 -axis_dwidth_converter_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axis_dwidth_converter_v1_1_18 -axis_subset_converter_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_subset_converter_v1_1_19 -axis_switch_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_switch_v1_1_19 -axis_vio_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axis_vio_v1_0_0 -axi_apb_bridge_v3_0_15 = C:/Mentor/CompLib/2019.1.3/axi_apb_bridge_v3_0_15 -axi_bram_ctrl_v4_0_14 = C:/Mentor/CompLib/2019.1.3/axi_bram_ctrl_v4_0_14 -axi_sg_v4_1_12 = C:/Mentor/CompLib/2019.1.3/axi_sg_v4_1_12 -axi_cdma_v4_1_19 = C:/Mentor/CompLib/2019.1.3/axi_cdma_v4_1_19 -axi_clock_converter_v2_1_18 = C:/Mentor/CompLib/2019.1.3/axi_clock_converter_v2_1_18 -axi_data_fifo_v2_1_18 = C:/Mentor/CompLib/2019.1.3/axi_data_fifo_v2_1_18 -axi_register_slice_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_register_slice_v2_1_19 -axi_crossbar_v2_1_20 = C:/Mentor/CompLib/2019.1.3/axi_crossbar_v2_1_20 -axi_dma_v7_1_20 = C:/Mentor/CompLib/2019.1.3/axi_dma_v7_1_20 -axi_protocol_converter_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_protocol_converter_v2_1_19 -axi_dwidth_converter_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_dwidth_converter_v2_1_19 -axi_emc_v3_0_19 = C:/Mentor/CompLib/2019.1.3/axi_emc_v3_0_19 -axi_epc_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_epc_v2_0_22 -lib_bmg_v1_0_12 = C:/Mentor/CompLib/2019.1.3/lib_bmg_v1_0_12 -axi_ethernetlite_v3_0_17 = C:/Mentor/CompLib/2019.1.3/axi_ethernetlite_v3_0_17 -axi_ethernet_buffer_v2_0_20 = C:/Mentor/CompLib/2019.1.3/axi_ethernet_buffer_v2_0_20 -axi_fifo_mm_s_v4_1_16 = C:/Mentor/CompLib/2019.1.3/axi_fifo_mm_s_v4_1_16 -axi_fifo_mm_s_v4_2_1 = C:/Mentor/CompLib/2019.1.3/axi_fifo_mm_s_v4_2_1 -axi_firewall_v1_0_7 = C:/Mentor/CompLib/2019.1.3/axi_firewall_v1_0_7 -interrupt_control_v3_1_4 = C:/Mentor/CompLib/2019.1.3/interrupt_control_v3_1_4 -axi_gpio_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_gpio_v2_0_21 -axi_hwicap_v3_0_23 = C:/Mentor/CompLib/2019.1.3/axi_hwicap_v3_0_23 -axi_iic_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_iic_v2_0_22 -axi_intc_v4_1_13 = C:/Mentor/CompLib/2019.1.3/axi_intc_v4_1_13 -axi_interconnect_v1_7_16 = C:/Mentor/CompLib/2019.1.3/axi_interconnect_v1_7_16 -axi_master_burst_v2_0_7 = C:/Mentor/CompLib/2019.1.3/axi_master_burst_v2_0_7 -axi_msg_v1_0_5 = C:/Mentor/CompLib/2019.1.3/axi_msg_v1_0_5 -axi_mcdma_v1_0_5 = C:/Mentor/CompLib/2019.1.3/axi_mcdma_v1_0_5 -axi_mcdma_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axi_mcdma_v1_1_0 -axi_memory_init_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_memory_init_v1_0_0 -axi_mm2s_mapper_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axi_mm2s_mapper_v1_1_18 -axi_mmu_v2_1_17 = C:/Mentor/CompLib/2019.1.3/axi_mmu_v2_1_17 -axi_pcie_v2_9_1 = C:/Mentor/CompLib/2019.1.3/axi_pcie_v2_9_1 -axi_protocol_checker_v2_0_5 = C:/Mentor/CompLib/2019.1.3/axi_protocol_checker_v2_0_5 -axi_quad_spi_v3_2_18 = C:/Mentor/CompLib/2019.1.3/axi_quad_spi_v3_2_18 -axi_sideband_util_v1_0_3 = C:/Mentor/CompLib/2019.1.3/axi_sideband_util_v1_0_3 -axi_tft_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_tft_v2_0_22 -axi_timebase_wdt_v3_0_11 = C:/Mentor/CompLib/2019.1.3/axi_timebase_wdt_v3_0_11 -axi_timer_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_timer_v2_0_21 -axi_traffic_gen_v2_0_20 = C:/Mentor/CompLib/2019.1.3/axi_traffic_gen_v2_0_20 -axi_traffic_gen_v3_0_5 = C:/Mentor/CompLib/2019.1.3/axi_traffic_gen_v3_0_5 -axi_uart16550_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_uart16550_v2_0_21 -axi_uartlite_v2_0_23 = C:/Mentor/CompLib/2019.1.3/axi_uartlite_v2_0_23 -axi_usb2_device_v5_0_20 = C:/Mentor/CompLib/2019.1.3/axi_usb2_device_v5_0_20 -axi_utils_v2_0_6 = C:/Mentor/CompLib/2019.1.3/axi_utils_v2_0_6 -axi_vdma_v6_3_7 = C:/Mentor/CompLib/2019.1.3/axi_vdma_v6_3_7 -xbip_pipe_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_pipe_v3_0_6 -xbip_dsp48_addsub_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_addsub_v3_0_6 -xbip_addsub_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_addsub_v3_0_6 -c_reg_fd_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_reg_fd_v12_0_6 -c_addsub_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_addsub_v12_0_13 -axi_vfifo_ctrl_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_vfifo_ctrl_v2_0_21 -axi_vip_v1_1_5 = C:/Mentor/CompLib/2019.1.3/axi_vip_v1_1_5 -bs_switch_v1_0_0 = C:/Mentor/CompLib/2019.1.3/bs_switch_v1_0_0 -canfd_v2_0_1 = C:/Mentor/CompLib/2019.1.3/canfd_v2_0_1 -can_v5_0_22 = C:/Mentor/CompLib/2019.1.3/can_v5_0_22 -cic_compiler_v4_0_14 = C:/Mentor/CompLib/2019.1.3/cic_compiler_v4_0_14 -xbip_bram18k_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_bram18k_v3_0_6 -mult_gen_v12_0_15 = C:/Mentor/CompLib/2019.1.3/mult_gen_v12_0_15 -cmpy_v6_0_17 = C:/Mentor/CompLib/2019.1.3/cmpy_v6_0_17 -c_mux_bit_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_mux_bit_v12_0_6 -c_shift_ram_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_shift_ram_v12_0_13 -c_mux_bus_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_mux_bus_v12_0_6 -c_gate_bit_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_gate_bit_v12_0_6 -xbip_counter_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_counter_v3_0_6 -c_counter_binary_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_counter_binary_v12_0_13 -c_compare_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_compare_v12_0_6 -convolution_v9_0_14 = C:/Mentor/CompLib/2019.1.3/convolution_v9_0_14 -cordic_v6_0_15 = C:/Mentor/CompLib/2019.1.3/cordic_v6_0_15 -cpri_v8_10_3 = C:/Mentor/CompLib/2019.1.3/cpri_v8_10_3 -xbip_dsp48_acc_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_acc_v3_0_6 -xbip_accum_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_accum_v3_0_6 -c_accum_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_accum_v12_0_13 -xbip_dsp48_multadd_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_multadd_v3_0_6 -dds_compiler_v6_0_18 = C:/Mentor/CompLib/2019.1.3/dds_compiler_v6_0_18 -dft_v4_0_16 = C:/Mentor/CompLib/2019.1.3/dft_v4_0_16 -dft_v4_1_1 = C:/Mentor/CompLib/2019.1.3/dft_v4_1_1 -displayport_v7_0_11 = C:/Mentor/CompLib/2019.1.3/displayport_v7_0_11 -displayport_v8_1_1 = C:/Mentor/CompLib/2019.1.3/displayport_v8_1_1 -displayport_v9_0_1 = C:/Mentor/CompLib/2019.1.3/displayport_v9_0_1 -xbip_dsp48_mult_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_mult_v3_0_6 -floating_point_v7_0_16 = C:/Mentor/CompLib/2019.1.3/floating_point_v7_0_16 -div_gen_v5_1_15 = C:/Mentor/CompLib/2019.1.3/div_gen_v5_1_15 -dp_videoaxi4s_bridge_v1_0_0 = C:/Mentor/CompLib/2019.1.3/dp_videoaxi4s_bridge_v1_0_0 -dsp_macro_v1_0_0 = C:/Mentor/CompLib/2019.1.3/dsp_macro_v1_0_0 -fir_compiler_v5_2_6 = C:/Mentor/CompLib/2019.1.3/fir_compiler_v5_2_6 -duc_ddc_compiler_v3_0_15 = C:/Mentor/CompLib/2019.1.3/duc_ddc_compiler_v3_0_15 -ernic_v1_0_1 = C:/Mentor/CompLib/2019.1.3/ernic_v1_0_1 -etrnic_v1_0_3 = C:/Mentor/CompLib/2019.1.3/etrnic_v1_0_3 -etrnic_v1_1_2 = C:/Mentor/CompLib/2019.1.3/etrnic_v1_1_2 -fc32_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/fc32_rs_fec_v1_0_11 -fec_5g_common_v1_0_1 = C:/Mentor/CompLib/2019.1.3/fec_5g_common_v1_0_1 -fec_5g_common_v1_1_1 = C:/Mentor/CompLib/2019.1.3/fec_5g_common_v1_1_1 -fir_compiler_v7_2_12 = C:/Mentor/CompLib/2019.1.3/fir_compiler_v7_2_12 -flexo_100g_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/flexo_100g_rs_fec_v1_0_11 -floating_point_v7_1_8 = C:/Mentor/CompLib/2019.1.3/floating_point_v7_1_8 -g709_rs_encoder_v2_2_6 = C:/Mentor/CompLib/2019.1.3/g709_rs_encoder_v2_2_6 -rs_toolbox_v9_0_7 = C:/Mentor/CompLib/2019.1.3/rs_toolbox_v9_0_7 -g709_rs_decoder_v2_2_8 = C:/Mentor/CompLib/2019.1.3/g709_rs_decoder_v2_2_8 -g709_fec_v2_3_5 = C:/Mentor/CompLib/2019.1.3/g709_fec_v2_3_5 -g709_fec_v2_4_1 = C:/Mentor/CompLib/2019.1.3/g709_fec_v2_4_1 -g975_efec_i4_v1_0_17 = C:/Mentor/CompLib/2019.1.3/g975_efec_i4_v1_0_17 -g975_efec_i7_v2_0_18 = C:/Mentor/CompLib/2019.1.3/g975_efec_i7_v2_0_18 -ieee802d3_200g_rs_fec_v1_0_7 = C:/Mentor/CompLib/2019.1.3/ieee802d3_200g_rs_fec_v1_0_7 -ieee802d3_25g_rs_fec_v1_0_13 = C:/Mentor/CompLib/2019.1.3/ieee802d3_25g_rs_fec_v1_0_13 -ieee802d3_400g_rs_fec_v1_0_7 = C:/Mentor/CompLib/2019.1.3/ieee802d3_400g_rs_fec_v1_0_7 -ieee802d3_50g_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/ieee802d3_50g_rs_fec_v1_0_11 -ieee802d3_50g_rs_fec_v2_0_1 = C:/Mentor/CompLib/2019.1.3/ieee802d3_50g_rs_fec_v2_0_1 -ieee802d3_rs_fec_v1_0_15 = C:/Mentor/CompLib/2019.1.3/ieee802d3_rs_fec_v1_0_15 -ieee802d3_rs_fec_v2_0_5 = C:/Mentor/CompLib/2019.1.3/ieee802d3_rs_fec_v2_0_5 -ldpc_v2_0_3 = C:/Mentor/CompLib/2019.1.3/ldpc_v2_0_3 -lte_3gpp_channel_estimator_v2_0_16 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_channel_estimator_v2_0_16 -lte_3gpp_mimo_decoder_v3_0_15 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_mimo_decoder_v3_0_15 -lte_3gpp_mimo_encoder_v4_0_14 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_mimo_encoder_v4_0_14 -tcc_encoder_3gpplte_v4_0_15 = C:/Mentor/CompLib/2019.1.3/tcc_encoder_3gpplte_v4_0_15 -lte_dl_channel_encoder_v3_0_15 = C:/Mentor/CompLib/2019.1.3/lte_dl_channel_encoder_v3_0_15 -lte_dl_channel_encoder_v4_0_0 = C:/Mentor/CompLib/2019.1.3/lte_dl_channel_encoder_v4_0_0 -xfft_v7_2_9 = C:/Mentor/CompLib/2019.1.3/xfft_v7_2_9 -lte_fft_v2_0_18 = C:/Mentor/CompLib/2019.1.3/lte_fft_v2_0_18 -xfft_v9_1_2 = C:/Mentor/CompLib/2019.1.3/xfft_v9_1_2 -lte_fft_v2_1_0 = C:/Mentor/CompLib/2019.1.3/lte_fft_v2_1_0 -xbip_dsp48_multacc_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_multacc_v3_0_6 -lte_pucch_receiver_v2_0_16 = C:/Mentor/CompLib/2019.1.3/lte_pucch_receiver_v2_0_16 -xbip_multadd_v3_0_14 = C:/Mentor/CompLib/2019.1.3/xbip_multadd_v3_0_14 -lte_rach_detector_v3_1_5 = C:/Mentor/CompLib/2019.1.3/lte_rach_detector_v3_1_5 -lte_ul_channel_decoder_v4_0_16 = C:/Mentor/CompLib/2019.1.3/lte_ul_channel_decoder_v4_0_16 -mailbox_v2_1_11 = C:/Mentor/CompLib/2019.1.3/mailbox_v2_1_11 -mdm_v3_2_16 = C:/Mentor/CompLib/2019.1.3/mdm_v3_2_16 -iomodule_v3_0 = C:/Mentor/CompLib/2019.1.3/iomodule_v3_0 -lmb_bram_if_cntlr_v4_0 = C:/Mentor/CompLib/2019.1.3/lmb_bram_if_cntlr_v4_0 -lmb_v10_v3_0 = C:/Mentor/CompLib/2019.1.3/lmb_v10_v3_0 -axi_lite_ipif_v3_0 = C:/Mentor/CompLib/2019.1.3/axi_lite_ipif_v3_0 -mdm_v3_2 = C:/Mentor/CompLib/2019.1.3/mdm_v3_2 -microblaze_mcs_v2_3_6 = C:/Mentor/CompLib/2019.1.3/microblaze_mcs_v2_3_6 -noc_mc_ddr4_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_mc_ddr4_phy_v1_0_0 -perf_axi_tg_v1_0_8 = C:/Mentor/CompLib/2019.1.3/perf_axi_tg_v1_0_8 -polar_v1_0_3 = C:/Mentor/CompLib/2019.1.3/polar_v1_0_3 -prc_v1_3_2 = C:/Mentor/CompLib/2019.1.3/prc_v1_3_2 -processing_system7_vip_v1_0_7 = C:/Mentor/CompLib/2019.1.3/processing_system7_vip_v1_0_7 -proc_sys_reset_v5_0_13 = C:/Mentor/CompLib/2019.1.3/proc_sys_reset_v5_0_13 -pr_axi_shutdown_manager_v1_0_1 = C:/Mentor/CompLib/2019.1.3/pr_axi_shutdown_manager_v1_0_1 -pr_bitstream_monitor_v1_0_1 = C:/Mentor/CompLib/2019.1.3/pr_bitstream_monitor_v1_0_1 -pr_decoupler_v1_0_7 = C:/Mentor/CompLib/2019.1.3/pr_decoupler_v1_0_7 -quadsgmii_v3_4_6 = C:/Mentor/CompLib/2019.1.3/quadsgmii_v3_4_6 -rs_decoder_v9_0_16 = C:/Mentor/CompLib/2019.1.3/rs_decoder_v9_0_16 -rs_encoder_v9_0_15 = C:/Mentor/CompLib/2019.1.3/rs_encoder_v9_0_15 -rxaui_v4_4_6 = C:/Mentor/CompLib/2019.1.3/rxaui_v4_4_6 -sd_fec_v1_1_3 = C:/Mentor/CompLib/2019.1.3/sd_fec_v1_1_3 -sid_v8_0_14 = C:/Mentor/CompLib/2019.1.3/sid_v8_0_14 -soft_ecc_proxy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/soft_ecc_proxy_v1_0_0 -spdif_v2_0_21 = C:/Mentor/CompLib/2019.1.3/spdif_v2_0_21 -srio_gen2_v4_1_6 = C:/Mentor/CompLib/2019.1.3/srio_gen2_v4_1_6 -switch_core_top_v1_0_7 = C:/Mentor/CompLib/2019.1.3/switch_core_top_v1_0_7 -sync_ip = C:/Mentor/CompLib/2019.1.3/sync_ip -tcc_decoder_3gppmm_v2_0_18 = C:/Mentor/CompLib/2019.1.3/tcc_decoder_3gppmm_v2_0_18 -tcc_encoder_3gpp_v5_0_15 = C:/Mentor/CompLib/2019.1.3/tcc_encoder_3gpp_v5_0_15 -tmr_comparator_v1_0_2 = C:/Mentor/CompLib/2019.1.3/tmr_comparator_v1_0_2 -tmr_sem_v1_0_9 = C:/Mentor/CompLib/2019.1.3/tmr_sem_v1_0_9 -tri_mode_ethernet_mac_v9_0_14 = C:/Mentor/CompLib/2019.1.3/tri_mode_ethernet_mac_v9_0_14 -tsn_temac_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tsn_temac_v1_0_4 -videoaxi4s_bridge_v1_0_5 = C:/Mentor/CompLib/2019.1.3/videoaxi4s_bridge_v1_0_5 -viterbi_v9_1_11 = C:/Mentor/CompLib/2019.1.3/viterbi_v9_1_11 -v_ccm_v6_0_15 = C:/Mentor/CompLib/2019.1.3/v_ccm_v6_0_15 -v_cfa_v7_0_14 = C:/Mentor/CompLib/2019.1.3/v_cfa_v7_0_14 -v_cresample_v4_0_14 = C:/Mentor/CompLib/2019.1.3/v_cresample_v4_0_14 -v_dual_splitter_v1_0_9 = C:/Mentor/CompLib/2019.1.3/v_dual_splitter_v1_0_9 -v_enhance_v8_0_15 = C:/Mentor/CompLib/2019.1.3/v_enhance_v8_0_15 -v_gamma_v7_0_15 = C:/Mentor/CompLib/2019.1.3/v_gamma_v7_0_15 -v_osd_v6_0_16 = C:/Mentor/CompLib/2019.1.3/v_osd_v6_0_16 -v_rgb2ycrcb_v7_1_13 = C:/Mentor/CompLib/2019.1.3/v_rgb2ycrcb_v7_1_13 -v_vid_sdi_tx_bridge_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_vid_sdi_tx_bridge_v2_0_0 -v_ycrcb2rgb_v7_1_13 = C:/Mentor/CompLib/2019.1.3/v_ycrcb2rgb_v7_1_13 -xbip_dsp48_macro_v3_0_17 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_macro_v3_0_17 -xfft_v9_0_17 = C:/Mentor/CompLib/2019.1.3/xfft_v9_0_17 -xsdbs_v1_0_2 = C:/Mentor/CompLib/2019.1.3/xsdbs_v1_0_2 -zynq_ultra_ps_e_vip_v1_0_5 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_vip_v1_0_5 -[DefineOptionset] -; Define optionset entries for the various compilers, vmake, and vsim. -; These option sets can be used with the "-optionset " syntax. -; i.e. -; vlog -optionset COMPILEDEBUG top.sv -; vsim -optionset UVMDEBUG my_top -; -; Following are some useful examples. - -; define a vsim optionset for uvm debugging -UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop - -; define a vopt optionset for debugging -VOPTDEBUG = +acc -debugdb - -[encryption] -; For vencrypt and vhencrypt. - -; Controls whether to encrypt whole files by ignoring all protect directives -; (except "viewport" and "interface_viewport") that are present in the input. -; The default is 0, use embedded protect directives to control the encryption. -; Set this to 1 to encrypt whole files by ignoring embedded protect directives. -; wholefile = 0 - -; Sets the data_method to use for the symmetric session key. -; The session key is a symmetric key that is randomly generated for each -; protected region (envelope) and is the heart of all encryption. This is used -; to set the length of the session key to generate and use when encrypting the -; HDL text. Supported values are aes128, aes192, and aes256. -; data_method = aes128 - -; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption -; "recipe" comprising an optional common block, at least one tool block (which -; contains the key public key), and the text to be encrypted. The common block -; and any of the tool blocks may contain rights in the form of the "control" -; directive. The text to be encrypted is specified either by setting -; "wholefile" to 1 or by embedding protect "begin" and "end" directives in -; the input HDL files. - -; Common recipe specification file. This file is optional. Its presence will -; require at least one "toolblock" to be specified. -; Directives such as "author" "author_info" and "data_method", -; as well as the common block license specification, go in this file. -; common = - -; Tool block specification recipe(s). Public key file with optional tool block -; file name. May be multiply-defined; at least one tool block is required if -; a recipe is being specified. -; Key file is a file name with no extension (.deprecated or .active will be -; supplied by the encryption tool). -; Rights file name is optional. -; toolblock = [,]{:[,]} - -; Location of directory containing recipe files. -; The default location is in the product installation directory. -; keyring = $MODEL_TECH/../keyring - -; Enable encryption statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list] -; Add '-' to disable specific statistics. Default is [cmd,msg]. -Stats = cmd,msg - -[vcom] -; VHDL93 variable selects language version as the default. -; Default is VHDL-2002. -; Value of 0 or 1987 for VHDL-1987. -; Value of 1 or 1993 for VHDL-1993. -; Default or value of 2 or 2002 for VHDL-2002. -; Value of 3 or 2008 for VHDL-2008 -; Value of 4 or ams99 for VHDL-AMS-1999 -; Value of 5 or ams07 for VHDL-AMS-2007 -VHDL93 = 2002 - -; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. -; ignoreStandardRealVector = 1 - -; Show source line containing error. Default is off. -; Show_source = 1 - -; Turn off unbound-component warnings. Default is on. -; Show_Warning1 = 0 - -; Turn off process-without-a-wait-statement warnings. Default is on. -; Show_Warning2 = 0 - -; Turn off null-range warnings. Default is on. -; Show_Warning3 = 0 - -; Turn off no-space-in-time-literal warnings. Default is on. -; Show_Warning4 = 0 - -; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. -; Show_Warning5 = 0 - -; Turn off optimization for IEEE std_logic_1164 package. Default is on. -; Optimize_1164 = 0 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Turn on resolving of ambiguous function overloading in favor of the -; "explicit" function declaration (not the one automatically created by -; the compiler for each type declaration). Default is off. -; The .ini file has Explicit enabled so that std_logic_signed/unsigned -; will match the behavior of synthesis tools. -Explicit = 1 - -; Turn off acceleration of the VITAL packages. Default is to accelerate. -; NoVital = 1 - -; Turn off VITAL compliance checking. Default is checking on. -; NoVitalCheck = 1 - -; Ignore VITAL compliance checking errors. Default is to not ignore. -; IgnoreVitalErrors = 1 - -; Turn off VITAL compliance checking warnings. Default is to show warnings. -; Show_VitalChecksWarnings = 0 - -; Turn off PSL assertion warning messages. Default is to show warnings. -; Show_PslChecksWarnings = 0 - -; Enable parsing of embedded PSL assertions. Default is enabled. -; EmbeddedPsl = 0 - -; Keep silent about case statement static warnings. -; Default is to give a warning. -; NoCaseStaticError = 1 - -; Keep silent about warnings caused by aggregates that are not locally static. -; Default is to give a warning. -; NoOthersStaticError = 1 - -; Treat as errors: -; case statement static warnings -; warnings caused by aggregates that are not locally static -; Overrides NoCaseStaticError, NoOthersStaticError settings. -; PedanticErrors = 1 - -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn off "Loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on some limited synthesis rule compliance checking. Checks only: -; -- signals used (read) by a process must be in the sensitivity list -; CheckSynthesis = 1 - -; Activate optimizations on expressions that do not involve signals, -; waits, or function/procedure/task invocations. Default is off. -; ScalarOpts = 1 - -; Turns on lint-style checking. -; Show_Lint = 1 - -; Require the user to specify a configuration for all bindings, -; and do not generate a compile time default binding for the -; component. This will result in an elaboration error of -; 'component not bound' if the user fails to do so. Avoids the rare -; issue of a false dependency upon the unused default binding. -; RequireConfigForAllDefaultBinding = 1 - -; Perform default binding at compile time. -; Default is to do default binding at load time. -; BindAtCompile = 1; - -; Inhibit range checking on subscripts of arrays. Range checking on -; scalars defined with subtypes is inhibited by default. -; NoIndexCheck = 1 - -; Inhibit range checks on all (implicit and explicit) assignments to -; scalar objects defined with subtypes. -; NoRangeCheck = 1 - -; Set the prefix to be honored for synthesis/coverage pragma recognition. -; Default is "". -; AddPragmaPrefix = "" - -; Ignore synthesis and coverage pragmas with this prefix. -; Default is "". -; IgnorePragmaPrefix = "" - -; Turn on code coverage in VHDL design units. Default is off. -; Coverage = sbceft - -; Turn off code coverage in VHDL subprograms. Default is on. -; CoverSub = 0 - -; Automatically exclude VHDL case statement OTHERS choice branches. -; This includes OTHERS choices in selected signal assigment statements. -; Default is to not exclude. -; CoverExcludeDefault = 1 - -; Control compiler and VOPT optimizations that are allowed when -; code coverage is on. Refer to the comment for this in the [vlog] area. -; CoverOpt = 3 - -; Turn on or off clkOpt optimization for code coverage. Default is on. -; CoverClkOpt = 1 - -; Turn on or off clkOpt optimization builtins for code coverage. Default is on. -; CoverClkOptBuiltins = 0 - -; Inform code coverage optimizations to respect VHDL 'H' and 'L' -; values on signals in conditions and expressions, and to not automatically -; convert them to '1' and '0'. Default is to not convert. -; CoverRespectHandL = 0 - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable or disable Focused Expression Coverage analysis for conditions and -; expressions. Focused Expression Coverage data is provided by default when -; expression and/or condition coverage is active. -; CoverFEC = 0 - -; Enable or disable UDP Coverage analysis for conditions and expressions. -; UDP Coverage data is disabled by default when expression and/or condition -; coverage is active. -; CoverUDP = 1 - -; Enable or disable Rapid Expression Coverage mode for conditions and expressions. -; Disabling this would convert non-masking conditions in FEC tables to matching -; input patterns. -; CoverREC = 1 - -; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions -; for expression/condition coverage. -; NOTE: Enabling this may have a negative impact on simulation performance. -; CoverExpandReductionPrefix = 0 - -; Enable or disable short circuit evaluation of conditions and expressions when -; condition or expression coverage is active. Short circuit evaluation is enabled -; by default. -; CoverShortCircuit = 0 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Use this directory for compiler temporary files instead of "work/_temp" -; CompilerTempDir = /tmp - -; Set this to cause the compilers to force data to be committed to disk -; when the files are closed. -; SyncCompilerFiles = 1 - -; Add VHDL-AMS declarations to package STANDARD -; Default is not to add -; AmsStandard = 1 - -; Range and length checking will be performed on array indices and discrete -; ranges, and when violations are found within subprograms, errors will be -; reported. Default is to issue warnings for violations, because subprograms -; may not be invoked. -; NoDeferSubpgmCheck = 0 - -; Turn ON detection of FSMs having single bit current state variable. -; FsmSingle = 1 - -; Turn off reset state transitions in FSM. -; FsmResetTrans = 0 - -; Turn ON detection of FSM Implicit Transitions. -; FsmImplicitTrans = 1 - -; Controls whether or not to show immediate assertions with constant expressions -; in GUI/report/UCDB etc. By default, immediate assertions with constant -; expressions are shown in GUI/report/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Controls how VHDL basic identifiers are stored with the design unit. -; Does not make the language case-sensitive, affects only how declarations -; declared with basic identifiers have their names stored and printed -; (in the GUI, examine, etc.). -; Default is to preserve the case as originally depicted in the VHDL source. -; Value of 0 indicates to change all basic identifiers to lower case. -; PreserveCase = 0 - -; For Configuration Declarations, controls the effect that USE clauses have -; on visibility inside the configuration items being configured. If 1 -; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, -; extend the visibility of objects made visible through USE clauses into nested -; component configurations. -; OldVHDLConfigurationVisibility = 0 - -; Allows VHDL configuration declarations to be in a different library from -; the corresponding configured entity. Default is to not allow this for -; stricter LRM-compliance. -; SeparateConfigLibrary = 1; - -; Determine how mode OUT subprogram parameters of type array and record are treated. -; If 0 (the default), then only VHDL 2008 will do this initialization. -; If 1, always initialize the mode OUT parameter to its default value. -; If 2, do not initialize the mode OUT out parameter. -; Note that prior to release 10.1, all language versions did not initialize mode -; OUT array and record type parameters, unless overridden here via this mechanism. -; In release 10.1 and later, only files compiled with VHDL 2008 will cause this -; initialization, unless overridden here. -; InitOutCompositeParam = 0 - -; Generate symbols debugging database in only some special cases to save on -; the number of files in the library. For other design-units, this database is -; generated on-demand in vsim. -; Default is to to generate debugging database for all design-units. -; SmartDbgSym = 1 - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -; Describe compilation options according to matching file patterns. -; File pattern * matches all printing characters other than '/'. -; File pattern **/x matches all paths containing file/directory x. -; File pattern x/** matches all paths beginning at directory x. -; FileOptMap = (**/*.vhd => -2008); - -; Describe library targets of compilation according to matching file patterns. -; LibMap = (**/*.vhd => work); - -[vlog] -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn off "Loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on Verilog hazard checking (order-dependent accessing of global vars). -; Default is off. -; Hazard = 1 - -; Turn on converting regular Verilog identifiers to uppercase. Allows case -; insensitivity for module names. Default is no conversion. -; UpCase = 1 - -; Activate optimizations on expressions that do not involve signals, -; waits, or function/procedure/task invocations. Default is off. -; ScalarOpts = 1 - -; Turns on lint-style checking. -; Show_Lint = 1 - -; Show source line containing error. Default is off. -; Show_source = 1 - -; Turn on bad option warning. Default is off. -; Show_BadOptionWarning = 1 - -; Revert back to IEEE 1364-1995 syntax, default is 0 (off). -; vlog95compat = 1 - -; Turn off PSL warning messages. Default is to show warnings. -; Show_PslChecksWarnings = 0 - -; Enable parsing of embedded PSL assertions. Default is enabled. -; EmbeddedPsl = 0 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Set the threshold for automatically identifying sparse Verilog memories. -; A memory with total size in bytes equal to or more than the sparse memory -; threshold gets marked as sparse automatically, unless specified otherwise -; in source code or by the +nosparse commandline option of vlog or vopt. -; The default is 1M. (i.e. memories with total size equal -; to or greater than 1Mb are marked as sparse) -; SparseMemThreshold = 1048576 - -; Set the prefix to be honored for synthesis and coverage pragma recognition. -; Default is "". -; AddPragmaPrefix = "" - -; Ignore synthesis and coverage pragmas with this prefix. -; Default is "". -; IgnorePragmaPrefix = "" - -; Set the option to treat all files specified in a vlog invocation as a -; single compilation unit. The default value is set to 0 which will treat -; each file as a separate compilation unit as specified in the P1800 draft standard. -; MultiFileCompilationUnit = 1 - -; Turn on code coverage in Verilog design units. Default is off. -; Coverage = sbceft - -; Automatically exclude Verilog case statement default branches. -; Default is to not automatically exclude defaults. -; CoverExcludeDefault = 1 - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Enable Multi Bit Expression Coverage in a Design, If design has expression with -; multi bit operands, this option enables its Expression Coverage. -; The default value is 0. -; CoverFecMultiBit = 1 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable or disable Focused Expression Coverage analysis for conditions and -; expressions. Focused Expression Coverage data is provided by default when -; expression and/or condition coverage is active. -; CoverFEC = 0 - -; Enable or disable UDP Coverage analysis for conditions and expressions. -; UDP Coverage data is disabled by default when expression and/or condition -; coverage is active. -; CoverUDP = 1 - -; Enable or disable Rapid Expression Coverage mode for conditions and expressions. -; Disabling this would convert non-masking conditions in FEC tables to matching -; input patterns. -; CoverREC = 1 - -; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions -; for expression/condition coverage. -; NOTE: Enabling this may have a negative impact on simulation performance. -; CoverExpandReductionPrefix = 0 - -; Enable or disable short circuit evaluation of conditions and expressions when -; condition or expression coverage is active. Short circuit evaluation is enabled -; by default. -; CoverShortCircuit = 0 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Turn on code coverage in VLOG `celldefine modules, modules containing -; specify blocks, and modules included using vlog -v and -y. Default is off. -; CoverCells = 1 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Control compiler and VOPT optimizations that are allowed when -; code coverage is on. This is a number from 0 to 5, with the following -; meanings (the default is 3): -; 5 -- All allowable optimizations are on. -; 4 -- Turn off removing unreferenced code. -; 3 -- Turn off process, always block and if statement merging. -; 2 -- Turn off expression optimization, converting primitives -; to continuous assignments, VHDL subprogram inlining. -; and VHDL clkOpt (converting FF's to builtins). -; 1 -- Turn off continuous assignment optimizations and clock suppression. -; 0 -- Turn off Verilog module inlining and VHDL arch inlining. -; HOWEVER, if fsm coverage is turned on, optimizations will be forced to -; level 3, with also turning off converting primitives to continuous assigns. -; CoverOpt = 3 - -; Specify the override for the default value of "cross_num_print_missing" -; option for the Cross in Covergroups. If not specified then LRM default -; value of 0 (zero) is used. This is a compile time option. -; SVCrossNumPrintMissingDefault = 0 - -; Setting following to 1 would cause creation of variables which -; would represent the value of Coverpoint expressions. This is used -; in conjunction with "SVCoverpointExprVariablePrefix" option -; in the modelsim.ini -; EnableSVCoverpointExprVariable = 0 - -; Specify the override for the prefix used in forming the variable names -; which represent the Coverpoint expressions. This is used in conjunction with -; "EnableSVCoverpointExprVariable" option of the modelsim.ini -; The default prefix is "expr". -; The variable name is -; variable name => _ -; SVCoverpointExprVariablePrefix = expr - -; Override for the default value of the SystemVerilog covergroup, -; coverpoint, and cross option.goal (defined to be 100 in the LRM). -; NOTE: It does not override specific assignments in SystemVerilog -; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" -; in the [vsim] section can override this value. -; SVCovergroupGoalDefault = 100 - -; Override for the default value of the SystemVerilog covergroup, -; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) -; NOTE: It does not override specific assignments in SystemVerilog -; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" -; in the [vsim] section can override this value. -; SVCovergroupTypeGoalDefault = 100 - -; Specify the override for the default value of "strobe" option for the -; Covergroup Type. This is a compile time option which forces "strobe" to -; a user specified default value and supersedes SystemVerilog specified -; default value of '0'(zero). NOTE: This can be overriden by a runtime -; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. -; SVCovergroupStrobeDefault = 0 - -; Specify the override for the default value of "per_instance" option for the -; Covergroup variables. This is a compile time option which forces "per_instance" -; to a user specified default value and supersedes SystemVerilog specified -; default value of '0'(zero). -; SVCovergroupPerInstanceDefault = 0 - -; Specify the override for the default value of "get_inst_coverage" option for the -; Covergroup variables. This is a compile time option which forces -; "get_inst_coverage" to a user specified default value and supersedes -; SystemVerilog specified default value of '0'(zero). -; SVCovergroupGetInstCoverageDefault = 0 - -; -; A space separated list of resource libraries that contain precompiled -; packages. The behavior is identical to using the "-L" switch. -; -; LibrarySearchPath = [ ...] -LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact - -; The behavior is identical to the "-mixedansiports" switch. Default is off. -; MixedAnsiPorts = 1 - -; Enable SystemVerilog 3.1a $typeof() function. Default is off. -; EnableTypeOf = 1 - -; Only allow lower case pragmas. Default is disabled. -; AcceptLowerCasePragmaOnly = 1 - -; Set the maximum depth permitted for a recursive include file nesting. -; IncludeRecursionDepthMax = 5 - -; Turn ON detection of FSMs having single bit current state variable. -; FsmSingle = 1 - -; Turn off reset state transitions in FSM. -; FsmResetTrans = 0 - -; Turn off detections of FSMs having x-assignment. -; FsmXAssign = 0 - -; Turn ON detection of FSM Implicit Transitions. -; FsmImplicitTrans = 1 - -; List of file suffixes which will be read as SystemVerilog. White space -; in extensions can be specified with a back-slash: "\ ". Back-slashes -; can be specified with two consecutive back-slashes: "\\"; -; SvFileSuffixes = sv svp svh - -; This setting is the same as the vlog -sv command line switch. -; Enables SystemVerilog features and keywords when true (1). -; When false (0), the rules of IEEE Std 1364-2005 are followed and -; SystemVerilog keywords are ignored. -; Svlog = 0 - -; Prints attribute placed upon SV packages during package import -; when true (1). The attribute will be ignored when this -; entry is false (0). The attribute name is "mti_design_element_load_message". -; The value of this attribute is a string literal. -; Default is true (1). -; PrintSVPackageLoadingAttribute = 1 - -; Do not show immediate assertions with constant expressions in -; GUI/reports/UCDB etc. By default immediate assertions with constant -; expressions are shown in GUI/reports/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Controls if untyped parameters that are initialized with values greater -; than 2147483647 are mapped to generics of type INTEGER or ignored. -; If mapped to VHDL Integers, values greater than 2147483647 -; are mapped to negative values. -; Default is to map these parameter to generic of type INTEGER -; ForceUnsignedToVHDLInteger = 1 - -; Enable AMS wreal (wired real) extensions. Default is 0. -; WrealType = 1 - -; Controls SystemVerilog Language Extensions. These options enable -; some non-LRM compliant behavior. -; SvExtensions = [+|-][,[+|-]*] - -; Generate symbols debugging database in only some special cases to save on -; the number of files in the library. For other design-units, this database is -; generated on-demand in vsim. -; Default is to to generate debugging database for all design-units. -; SmartDbgSym = 1 - -; Controls how $unit library entries are named. Valid options are: -; "file" (generate name based on the first file on the command line) -; "du" (generate name based on first design unit following an item -; found in $unit scope) -; CUAutoName = file - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -[sccom] -; Enable use of SCV include files and library. Default is off. -; UseScv = 1 - -; Add C++ compiler options to the sccom command line by using this variable. -; CppOptions = -g - -; Use custom C++ compiler located at this path rather than the default path. -; The path should point directly at a compiler executable. -; CppPath = /usr/bin/g++ - -; Specify the compiler version from the list of support GNU compilers. -; examples 4.7.4, 5.3.0, 7.4.0 -; CppInstall = 7.4.0 - -; Enable verbose messages from sccom. Default is off. -; SccomVerbose = 1 - -; sccom logfile. Default is no logfile. -; SccomLogfile = sccom.log - -; Enable use of SC_MS include files and library. Default is off. -; UseScMs = 1 - -; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. -; Sc22Mode = 1 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -; Enable use of UVMC library. Default is off. -; UseUvmc = 1 - -[vopt] -; Turn on code coverage in vopt. Default is off. -; Coverage = sbceft - -; enable or disable param saving in UCDB. -; CoverageSaveParam = 0 - -; Control compiler optimizations that are allowed when -; code coverage is on. Refer to the comment for this in the [vlog] area. -; CoverOpt = 3 - -; Controls set of CoverConstructs that are being considered for Coverage -; Collection. -; Some of Valid options are: default,set1,set2 -; Covermode = default - -; Controls set of HDL cover constructs that would be considered(or not considered) -; for Coverage Collection. (Default corresponds to covermode default). -; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". -; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Enable Multi Bit Expression Coverage in a Design, If design has expression with -; multi bit operands, this option enables its Expression Coverage. -; The default value is 0. -; CoverFecMultiBit = 1 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Do not show immediate assertions with constant expressions in -; GUI/reports/UCDB etc. By default immediate assertions with constant -; expressions are shown in GUI/reports/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Set the maximum number of iterations permitted for a generate loop. -; Restricting this permits the implementation to recognize infinite -; generate loops. -; GenerateLoopIterationMax = 100000 - -; Set the maximum depth permitted for a recursive generate instantiation. -; Restricting this permits the implementation to recognize infinite -; recursions. -; GenerateRecursionDepthMax = 200 - -; Set the number of processes created during the code generation phase. -; By default a heuristic is used to set this value. This may be set to 0 -; to disable this feature completely. -; ParallelJobs = 0 - -; Controls SystemVerilog Language Extensions. These options enable -; some non-LRM compliant behavior. -; SvExtensions = [+|-][,[+|-]*] - -; Load the specified shared objects with the RTLD_GLOBAL flag. -; This gives global visibility to all symbols in the shared objects, -; meaning that subsequently loaded shared objects can bind to symbols -; in the global shared objects. The list of shared objects should -; be whitespace delimited. This option is not supported on the -; Windows or AIX platforms. -; GlobalSharedObjectList = example1.so example2.so example3.so - -; Disable SystemVerilog elaboration system task messages -; IgnoreSVAInfo = 1 -; IgnoreSVAWarning = 1 -; IgnoreSVAError = 1 -; IgnoreSVAFatal = 1 - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -[vsim] -; vopt flow -; Set to turn on automatic optimization of a design. -; Default is on -VoptFlow = 1 - -; Simulator resolution -; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. -Resolution = fs - -; Disable certain code coverage exclusions automatically. -; Assertions and FSM are exluded from the code coverage by default -; Set AutoExclusionsDisable = fsm to enable code coverage for fsm -; Set AutoExclusionsDisable = assertions to enable code coverage for assertions -; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions -; Or specify comma or space separated list -;AutoExclusionsDisable = fsm,assertions - -; User time unit for run commands -; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the -; unit specified for Resolution. For example, if Resolution is 100ps, -; then UserTimeUnit defaults to ps. -; Should generally be set to default. -UserTimeUnit = default - -; Default run length -RunLength = 100 - -; Maximum iterations that can be run without advancing simulation time -IterationLimit = 10000000 - -; Specify libraries to be searched for precompiled modules -; LibrarySearchPath = [ ...] - -; Set XPROP assertion fail limit. Default is 5. -; Any positive integer, -1 for infinity. -; XpropAssertionLimit = 5 - -; Control PSL and Verilog Assume directives during simulation -; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts -; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts -; SimulateAssumeDirectives = 1 - -; Control the simulation of PSL and SVA -; These switches can be overridden by the vsim command line switches: -; -psl, -nopsl, -sva, -nosva. -; Set SimulatePSL = 0 to disable PSL simulation -; Set SimulatePSL = 1 to enable PSL simulation (default) -; SimulatePSL = 1 -; Set SimulateSVA = 0 to disable SVA simulation -; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) -; SimulateSVA = 1 - -; Control SVA and VHDL immediate assertion directives during simulation -; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts -; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts -; SimulateImmedAsserts = 1 - -; License feature mappings for Verilog and VHDL -; qhsimvh Single language VHDL license -; qhsimvl Single language Verilog license -; msimhdlsim Language neutral license for either Verilog or VHDL -; msimhdlmix Second language only, language neutral license for either -; Verilog or VHDL -; -; Directives to license manager can be set either as single value or as -; space separated multi-values: -; vhdl Immediately checkout and hold a VHDL license (i.e., one of -; qhsimvh, msimhdlsim, or msimhdlmix) -; vlog Immediately checkout and hold a Verilog license (i.e., one of -; qhsimvl, msimhdlsim, or msimhdlmix) -; plus Immediately checkout and hold a VHDL license and a Verilog license -; noqueue Do not wait in the license queue when a license is not available -; viewsim Try for viewer license but accept simulator license(s) instead -; of queuing for viewer license (PE ONLY) -; noviewer Disable checkout of msimviewer license feature (PE ONLY) -; noslvhdl Disable checkout of qhsimvh license feature -; noslvlog Disable checkout of qhsimvl license feature -; nomix Disable checkout of msimhdlmix license feature -; nolnl Disable checkout of msimhdlsim license feature -; mixedonly Disable checkout of qhsimvh and qhsimvl license features -; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features -; -; Examples (remove ";" comment character to activate licensing directives): -; Single directive: -; License = plus -; Multi-directive (Note: space delimited directives): -; License = noqueue plus - -; Severity level of a VHDL assertion message or of a SystemVerilog severity system task -; which will cause a running simulation to stop. -; VHDL assertions and SystemVerilog severity system task that occur with the -; given severity or higher will cause a running simulation to stop. -; This value is ignored during elaboration. -; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal -BreakOnAssertion = 3 - -; Severity level of a tool message which will cause a running simulation to -; stop. This value is ignored during elaboration. Default is to not break. -; 0 = Note 1 = Warning 2 = Error 3 = Fatal -;BreakOnMessage = 2 - -; The class debug feature enables more visibility and tracking of class instances -; during simulation. By default this feature is disabled (0). To enable this -; feature set ClassDebug to 1. -; ClassDebug = 1 - -; Message Format conversion specifications: -; %S - Severity Level of message/assertion -; %R - Text of message -; %T - Time of message -; %D - Delta value (iteration number) of Time -; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected -; %i - Instance/Region/Signal pathname with Process name (if available) -; %I - shorthand for one of these: -; " %K: %i" -; " %K: %i File: %F" (when path is not Process or Signal) -; except that the %i in this case does not report the Process name -; %O - Process name -; %P - Instance/Region path without leaf process -; %F - File name -; %L - Line number; if assertion message, then line number of assertion or, if -; assertion is in a subprogram, line from which the call is made -; %u - Design unit name in form library.primary -; %U - Design unit name in form library.primary(secondary) -; %% - The '%' character itself -; -; If specific format for Severity Level is defined, use that format. -; Else, for a message that occurs during elaboration: -; -- Failure/Fatal message in VHDL region that is not a Process, and in -; certain non-VHDL regions, uses MessageFormatBreakLine; -; -- Failure/Fatal message otherwise uses MessageFormatBreak; -; -- Note/Warning/Error message uses MessageFormat. -; Else, for a message that occurs during runtime and triggers a breakpoint because -; of the BreakOnAssertion setting: -; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; -; -- otherwise uses MessageFormatBreak. -; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. -; -; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" -; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" -; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" -; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" - -; Error File - alternate file for storing error messages -; ErrorFile = error.log - -; Simulation Breakpoint messages -; This flag controls the display of function names when reporting the location -; where the simulator stops because of a breakpoint or fatal error. -; Example with function name: # Break in Process ctr at counter.vhd line 44 -; Example without function name: # Break at counter.vhd line 44 -; Default value is 1. -ShowFunctions = 1 - -; Default radix for all windows and commands. -; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned -; Flags may be one of: enumnumeric, showbase, wreal -DefaultRadix = hexadecimal -DefaultRadixFlags = showbase -; Set to 1 for make the signal_force VHDL and Verilog functions use the -; default radix when processing the force value. Prior to 10.2 signal_force -; used the default radix, now it always uses symbolic unless value explicitly indicates base -;SignalForceFunctionUseDefaultRadix = 0 - -; VSIM Startup command -; Startup = do startup.do - -; VSIM Shutdown file -; Filename to save u/i formats and configurations. -; ShutdownFile = restart.do -; To explicitly disable auto save: -; ShutdownFile = --disable-auto-save - -; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. -; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. -; BatchMode = 1 - -; File for saving command transcript when -batch option used -; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero -; default is unset so command transcript only goes to stdout for better performance -; BatchTranscriptFile = transcript - -; File for saving command transcript, this option is ignored when -batch option is used -TranscriptFile = transcript - -; Transcript file long line wrapping mode(s) -; mode == 0 :: no wrapping, line recorded as is -; mode == 1 :: wrap at first whitespace after WSColumn -; or at Column. -; mode == 2 :: wrap as above, but add continuation -; character ('\') at end of each wrapped line -; -; WrapMode = 0 -; WrapColumn = 30000 -; WrapWSColumn = 27000 - -; File for saving command history -; CommandHistory = cmdhist.log - -; Specify whether paths in simulator commands should be described -; in VHDL or Verilog format. -; For VHDL, PathSeparator = / -; For Verilog, PathSeparator = . -; Must not be the same character as DatasetSeparator. -PathSeparator = / - -; Specify the dataset separator for fully rooted contexts. -; The default is ':'. For example: sim:/top -; Must not be the same character as PathSeparator. -DatasetSeparator = : - -; Specify a unique path separator for the Signal Spy set of functions. -; The default will be to use the PathSeparator variable. -; Must not be the same character as DatasetSeparator. -; SignalSpyPathSeparator = / - -; Used to control parsing of HDL identifiers input to the tool. -; This includes CLI commands, vsim/vopt/vlog/vcom options, -; string arguments to FLI/VPI/DPI calls, etc. -; If set to 1, accept either Verilog escaped Id syntax or -; VHDL extended id syntax, regardless of source language. -; If set to 0, the syntax of the source language must be used. -; Each identifier in a hierarchical name may need different syntax, -; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or -; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" -; GenerousIdentifierParsing = 1 - -; Disable VHDL assertion messages -; IgnoreNote = 1 -; IgnoreWarning = 1 -; IgnoreError = 1 -; IgnoreFailure = 1 - -; Disable SystemVerilog assertion messages -; IgnoreSVAInfo = 1 -; IgnoreSVAWarning = 1 -; IgnoreSVAError = 1 -; IgnoreSVAFatal = 1 - -; Do not print any additional information from Severity System tasks. -; Only the message provided by the user is printed along with severity -; information. -; SVAPrintOnlyUserMessage = 1; - -; Default force kind. May be freeze, drive, deposit, or default -; or in other terms, fixed, wired, or charged. -; A value of "default" will use the signal kind to determine the -; force kind, drive for resolved signals, freeze for unresolved signals -; DefaultForceKind = freeze - -; Control the iteration of events when a VHDL signal is forced to a value -; This flag can be set to honour the signal update event in next iteration, -; the default is to update and propagate in the same iteration. -; ForceSigNextIter = 1 - -; Enable simulation statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; If zero, open files when elaborated; otherwise, open files on -; first read or write. Default is 0. -; DelayFileOpen = 1 - -; Control VHDL files opened for write. -; 0 = Buffered, 1 = Unbuffered -UnbufferedOutput = 0 - -; Control the number of VHDL files open concurrently. -; This number should always be less than the current ulimit -; setting for max file descriptors. -; 0 = unlimited -ConcurrentFileLimit = 40 - -; If nonzero, close files as soon as there is either an explicit call to -; file_close, or when the file variable's scope is closed. When zero, a -; file opened in append mode is not closed in case it is immediately -; reopened in append mode; otherwise, the file will be closed at the -; point it is reopened. -; AppendClose = 1 - -; Control the number of hierarchical regions displayed as -; part of a signal name shown in the Wave window. -; A value of zero tells VSIM to display the full name. -; The default is 0. -; WaveSignalNameWidth = 0 - -; Turn off warnings when changing VHDL constants and generics -; Default is 1 to generate warning messages -; WarnConstantChange = 0 - -; Turn off warnings from accelerated versions of the std_logic_arith, -; std_logic_unsigned, and std_logic_signed packages. -; StdArithNoWarnings = 1 - -; Turn off warnings from accelerated versions of the IEEE numeric_std -; and numeric_bit packages. -; NumericStdNoWarnings = 1 - -; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names -; in the design hierarchy. -; This style is controlled by the value of the GenerateFormat -; value described next. Default is to use new-style names, which -; comprise the generate statement label, '(', the value of the generate -; parameter, and a closing ')'. -; Set this to 1 to use old-style names. -; OldVhdlForGenNames = 1 - -; Control the format of the old-style VHDL FOR generate statement region -; name for each iteration. Do not quote the value. -; The format string here must contain the conversion codes %s and %d, -; in that order, and no other conversion codes. The %s represents -; the generate statement label; the %d represents the generate parameter value -; at a particular iteration (this is the position number if the generate parameter -; is of an enumeration type). Embedded whitespace is allowed (but discouraged); -; leading and trailing whitespace is ignored. -; Application of the format must result in a unique region name over all -; loop iterations for a particular immediately enclosing scope so that name -; lookup can function properly. The default is %s__%d. -; GenerateFormat = %s__%d - -; Enable more efficient logging of VHDL Variables. -; Logging VHDL variables without this enabled, while possible, is very -; inefficient. Enabling this will provide a more efficient logging methodology -; at the expense of more memory usage. By default this feature is disabled (0). -; To enabled this feature, set this variable to 1. -; VhdlVariableLogging = 1 - -; Enable logging of VHDL access type variables and their designated objects. -; This setting will allow both variables of an access type ("access variables") -; and their designated objects ("access objects") to be logged. Logging a -; variable of an access type will automatically also cause the designated -; object(s) of that variable to be logged as the simulation progresses. -; Further, enabling this allows access objects to be logged by name. By default -; this feature is disabled (0). To enable this feature, set this variable to 1. -; Enabling this will automatically enable the VhdlVariableLogging feature also. -; AccessObjDebug = 1 - -; Make each VHDL package in a PDU has its own separate copy of the package instead -; of sharing the package between PDUs. The default is to share packages. -; To ensure that each PDU has its own set of packages, set this variable to 1. -; VhdlSeparatePduPackage = 1 - -; Specify whether checkpoint files should be compressed. -; The default is 1 (compressed). -; CheckpointCompressMode = 0 - -; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. -; Use custom gcc compiler located at this path rather than the default path. -; The path should point directly at a compiler executable. -; DpiCppPath = /bin/gcc -; -; Specify the compiler version from the list of support GNU compilers. -; examples 4.7.4, 5.3.0, 7.4.0 -; DpiCppInstall = 7.4.0 - -; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. -; The term "out-of-the-blue" refers to SystemVerilog export function calls -; made from C functions that don't have the proper context setup -; (as is the case when running under "DPI-C" import functions). -; When this is enabled, one can call a DPI export function -; (but not task) from any C code. -; the setting of this variable can be one of the following values: -; 0 : dpioutoftheblue call is disabled (default) -; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. -; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. -; DpiOutOfTheBlue = 1 - -; Specify whether continuous assignments are run before other normal priority -; processes scheduled in the same iteration. This event ordering minimizes race -; differences between optimized and non-optimized designs, and is the default -; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set -; ImmediateContinuousAssign to 0. -; The default is 1 (enabled). -; ImmediateContinuousAssign = 0 - -; List of dynamically loaded objects for Verilog PLI applications -; Veriuser = veriuser.sl - -; Which default VPI object model should the tool conform to? -; The 1364 modes are Verilog-only, for backwards compatibility with older -; libraries, and SystemVerilog objects are not available in these modes. -; -; In the absence of a user-specified default, the tool default is the -; latest available LRM behavior. -; Options for PliCompatDefault are: -; VPI_COMPATIBILITY_VERSION_1364v1995 -; VPI_COMPATIBILITY_VERSION_1364v2001 -; VPI_COMPATIBILITY_VERSION_1364v2005 -; VPI_COMPATIBILITY_VERSION_1800v2005 -; VPI_COMPATIBILITY_VERSION_1800v2008 -; -; Synonyms for each string are also recognized: -; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) -; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) -; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) -; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) -; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) - - -; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 - -; Specify whether the Verilog system task $fopen or vpi_mcd_open() -; will create directories that do not exist when opening the file -; in "a" or "w" mode. -; The default is 0 (do not create non-existent directories) -; CreateDirForFileAccess = 1 - -; Specify default options for the restart command. Options can be one -; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions -; DefaultRestartOptions = -force - - -; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. -; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. -; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". -; The list of options must be delimited by commas, without spaces or tabs. -; -; Some examples -; To turn on all available UVM-aware debug features: -; UVMControl = all -; To turn on the struct window, mesage logging, and transaction logging: -; UVMControl = struct,msglog,trlog -; To turn on all options except certe: -; UVMControl = all,-certe -; To completely disable all UVM-aware debug functionality: -; UVMControl = disable - -; Specify the WildcardFilter setting. -; A space separated list of object types to be excluded when performing -; wildcard matches with log, wave, etc commands. The default value for this variable is: -; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" -; See "Using the WildcardFilter Preference Variable" in the documentation for -; details on how to use this variable and for descriptions of the filter types. -WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile - -; Specify the WildcardSizeThreshold setting. -; This integer setting specifies the size at which objects will be excluded when -; performing wildcard matches with log, wave, etc commands. Objects of size equal -; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard -; matches. The size is a simple calculation of number of bits or items in the object. -; The default value is 8k (8192). Setting this value to 0 will disable the checking -; of object size against this threshold and allow all objects of any size to be logged. -WildcardSizeThreshold = 8192 - -; Specify whether warning messages are output when objects are filtered out due to the -; WildcardSizeThreshold. The default is 0 (no messages generated). -WildcardSizeThresholdVerbose = 0 - -; Turn on (1) or off (0) WLF file compression. -; The default is 1 (compress WLF file). -; WLFCompress = 0 - -; Specify whether to save all design hierarchy (1) in the WLF file -; or only regions containing logged signals (0). -; The default is 0 (save only regions with logged signals). -; WLFSaveAllRegions = 1 - -; WLF file time limit. Limit WLF file by time, as closely as possible, -; to the specified amount of simulation time. When the limit is exceeded -; the earliest times get truncated from the file. -; If both time and size limits are specified the most restrictive is used. -; UserTimeUnits are used if time units are not specified. -; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} -; WLFTimeLimit = 0 - -; WLF file size limit. Limit WLF file size, as closely as possible, -; to the specified number of megabytes. If both time and size limits -; are specified then the most restrictive is used. -; The default is 0 (no limit). -; WLFSizeLimit = 1000 - -; Specify whether or not a WLF file should be deleted when the -; simulation ends. A value of 1 will cause the WLF file to be deleted. -; The default is 0 (do not delete WLF file when simulation ends). -; WLFDeleteOnQuit = 1 - -; Specify whether or not a WLF file should be optimized during -; simulation. If set to 0, the WLF file will not be optimized. -; The default is 1, optimize the WLF file. -; WLFOptimize = 0 - -; Specify the name of the WLF file. -; The default is vsim.wlf -; WLFFilename = vsim.wlf - -; Specify whether to lock the WLF file. -; Locking the file prevents other invocations of ModelSim/Questa tools from -; inadvertently overwriting the WLF file. -; The default is 1, lock the WLF file. -; WLFFileLock = 0 - -; Specify the update interval for the WLF file in live simulation. -; The interval is given in seconds. -; The value is the smallest interval between WLF file updates. The WLF file -; will be flushed (updated) after (at least) the interval has elapsed, ensuring -; that the data is correct when viewed from a separate viewer. -; A value of 0 means that no updating will occur. -; The default value is 10 seconds. -; WLFUpdateInterval = 10 - -; Specify the WLF cache size limit for WLF files. -; The value is given in megabytes. A value of 0 turns off the cache. -; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). -; On Windows, the default value is 1000 (megabytes) to help to avoid filling -; process memory. -; WLFSimCacheSize allows a different cache size to be set for a live simulation -; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize -; is not set, it defaults to the WLFCacheSize value. -; WLFCacheSize = 2000 -; WLFSimCacheSize = 500 - -; Specify the WLF file event collapse mode. -; 0 = Preserve all events and event order. (same as -wlfnocollapse) -; 1 = Only record values of logged objects at the end of a simulator iteration. -; (same as -wlfcollapsedelta) -; 2 = Only record values of logged objects at the end of a simulator time step. -; (same as -wlfcollapsetime) -; The default is 1. -; WLFCollapseMode = 0 - -; Specify whether WLF file logging can use threads on multi-processor machines. -; If 0, no threads will be used; if 1, threads will be used if the system has -; more than one processor. -; WLFUseThreads = 1 - -; Specify the size of objects that will trigger "large object" messages -; at log/wave/list time. The size calculation of the object is the same as that -; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. -; Setting LargeObjectSize to 0 will disable these messages. -; LargeObjectSize = 500000 - -; Specify the depth of stack frames returned by $stacktrace([level]). -; This depth will be picked up when the optional 'level' argument -; is not specified or its value is not a positive integer. -; StackTraceDepth = 100 - -; Turn on/off undebuggable SystemC type warnings. Default is on. -; ShowUndebuggableScTypeWarning = 0 - -; Turn on/off unassociated SystemC name warnings. Default is off. -; ShowUnassociatedScNameWarning = 1 - -; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. -; ScShowIeeeDeprecationWarnings = 1 - -; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. -; For SystemC-2.3.2 the valid values are 0,1 and 2 -; 0 = SC_SIGNAL_WRITE_CHECK_DISABLE_ -; 1 = SC_SIGNAL_WRITE_CHECK_DEFAULT_ -; 2 = SC_SIGNAL_WRITE_CHECK_CONFLICT_ -; For SystemC-2.2 the valid values are 0 and 1 -; 0 = DISABLE -; 1 = ENABLE -; ScEnableScSignalWriteCheck = 1 - -; Set SystemC default time unit. -; Set to fs, ps, ns, us, ms, or sec with optional -; prefix of 1, 10, or 100. The default is 1 ns. -; The ScTimeUnit value is honored if it is coarser than Resolution. -; If ScTimeUnit is finer than Resolution, it is set to the value -; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, -; then the default time unit will be 1 ns. However if Resolution -; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. -ScTimeUnit = ns - -; Set SystemC sc_main stack size. The stack size is set as an integer -; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or -; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends -; on the amount of data on the sc_main() stack and the memory required -; to succesfully execute the longest function call chain of sc_main(). -ScMainStackSize = 10 Mb - -; Set SystemC thread stack size. The stack size is set as an integer -; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or -; Gb(Giga-byte). The stack size for sc_thread depends -; on the amount of data on the sc_thread stack and the memory required -; to succesfully execute the thread. -; ScStackSize = 1 Mb - -; Turn on/off execution of remainder of sc_main upon quitting the current -; simulation session. If the cumulative length of sc_main() in terms of -; simulation time units is less than the length of the current simulation -; run upon quit or restart, sc_main() will be in the middle of execution. -; This switch gives the option to execute the remainder of sc_main upon -; quitting simulation. The drawback of not running sc_main till the end -; is memory leaks for objects created by sc_main. If on, the remainder of -; sc_main will be executed ignoring all delays. This may cause the simulator -; to crash if the code in sc_main is dependent on some simulation state. -; Default is on. -ScMainFinishOnQuit = 1 - -; Enable calling of the DPI export taks/functions from the -; SystemC start_of_simulation() callback. -; The default is off. -; EnableDpiSosCb = 1 - - -; Set the SCV relationship name that will be used to identify phase -; relations. If the name given to a transactor relation matches this -; name, the transactions involved will be treated as phase transactions -ScvPhaseRelationName = mti_phase - -; Customize the vsim kernel shutdown behavior at the end of the simulation. -; Some common causes of the end of simulation are $finish (implicit or explicit), -; sc_stop(), tf_dofinish(), and assertion failures. -; This should be set to "ask", "exit", or "stop". The default is "ask". -; "ask" -- In batch mode, the vsim kernel will abruptly exit. -; In GUI mode, a dialog box will pop up and ask for user confirmation -; whether or not to quit the simulation. -; "stop" -- Cause the simulation to stay loaded in memory. This can make some -; post-simulation tasks easier. -; "exit" -- The simulation will abruptly exit without asking for any confirmation. -; "final" -- Run SystemVerilog final blocks then behave as "stop". -; Note: This variable can be overridden with the vsim "-onfinish" command line switch. -OnFinish = ask - -; Print pending deferred assertion messages. -; Deferred assertion messages may be scheduled after the $finish in the same -; time step. Deferred assertions scheduled to print after the $finish are -; printed before exiting with severity level NOTE since it's not known whether -; the assertion is still valid due to being printed in the active region -; instead of the reactive region where they are normally printed. -; OnFinishPendingAssert = 1; - -; Print "simstats" result. Default is 0. -; 0 == do not print simstats -; 1 == print at end of simulation -; 2 == print at end of each run command and end of simulation -; PrintSimStats = 1 - -; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages -; AssertFile = assert.log - -; Enable assertion counts. Default is off. -; AssertionCounts = 1 - -; Run simulator in assertion debug mode. Default is off. -; AssertionDebug = 1 - -; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. -; AssertionEnable = 0 - -; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. -; Any positive integer, -1 for infinity. -; AssertionLimit = 1 - -; Turn on/off concurrent assertion pass log. Default is off. -; Assertion pass logging is only enabled when assertion is browseable -; and assertion debug is enabled. -; AssertionPassLog = 1 - -; Turn on/off PSL concurrent assertion fail log. Default is on. -; The flag does not affect SVA -; AssertionFailLog = 0 - -; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. -; AssertionFailLocalVarLog = 0 - -; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. -; 0 = Continue 1 = Break 2 = Exit -; AssertionFailAction = 1 - -; Enable the active thread monitor in the waveform display when assertion debug is enabled. -; AssertionActiveThreadMonitor = 1 - -; Control how many waveform rows will be used for displaying the active threads. Default is 5. -; AssertionActiveThreadMonitorLimit = 5 - -; Assertion thread limit after which assertion would be killed/switched off. -; The default is -1 (unlimited). If the number of threads for an assertion go -; beyond this limit, the assertion would be either switched off or killed. This -; limit applies to only assert directives. -;AssertionThreadLimit = -1 - -; Action to be taken once the assertion thread limit is reached. Default -; is kill. It can have a value of off or kill. In case of kill, all the existing -; threads are terminated and no new attempts are started. In case of off, the -; existing attempts keep on evaluating but no new attempts are started. This -; variable applies to only assert directives. -;AssertionThreadLimitAction = kill - -; Cover thread limit after which cover would be killed/switched off. -; The default is -1 (unlimited). If the number of threads for a cover go -; beyond this limit, the cover would be either switched off or killed. This -; limit applies to only cover directives. -;CoverThreadLimit = -1 - -; Action to be taken once the cover thread limit is reached. Default -; is kill. It can have a value of off or kill. In case of kill, all the existing -; threads are terminated and no new attempts are started. In case of off, the -; existing attempts keep on evaluating but no new attempts are started. This -; variable applies to only cover directives. -;CoverThreadLimitAction = kill - - -; By default immediate assertions do not participate in Assertion Coverage calculations -; unless they are executed. This switch causes all immediate assertions in the design -; to participate in Assertion Coverage calculations, whether attempted or not. -; UnattemptedImmediateAssertions = 0 - -; By default immediate covers participate in Coverage calculations -; whether they are attempted or not. This switch causes all unattempted -; immediate covers in the design to stop participating in Coverage -; calculations. -; UnattemptedImmediateCovers = 0 - -; By default pass action block is not executed for assertions on vacuous -; success. The following variable is provided to enable execution of -; pass action block on vacuous success. The following variable is only effective -; if the user does not disable pass action block execution by using either -; system tasks or CLI. Also there is a performance penalty for enabling -; the following variable. -;AssertionEnableVacuousPassActionBlock = 1 - -; As per strict 1850-2005 PSL LRM, an always property can either pass -; or fail. However, by default, Questa reports multiple passes and -; multiple fails on top always/never property (always/never operator -; is the top operator under Verification Directive). The reason -; being that Questa reports passes and fails on per attempt of the -; top always/never property. Use the following flag to instruct -; Questa to strictly follow LRM. With this flag, all assert/never -; directives will start an attempt once at start of simulation. -; The attempt can either fail, match or match vacuously. -; For e.g. if always is the top operator under assert, the always will -; keep on checking the property at every clock. If the property under -; always fails, the directive will be considered failed and no more -; checking will be done for that directive. A top always property, -; if it does not fail, will show a pass at end of simulation. -; The default value is '0' (i.e. zero is off). For example: -; PslOneAttempt = 1 - -; Specify the number of clock ticks to represent infinite clock ticks. -; This affects eventually!, until! and until_!. If at End of Simulation -; (EOS) an active strong-property has not clocked this number of -; clock ticks then neither pass or fail (vacuous match) is returned -; else respective fail/pass is returned. The default value is '0' (zero) -; which effectively does not check for clock tick condition. For example: -; PslInfinityThreshold = 5000 - -; Control how many thread start times will be preserved for ATV viewing for a given assertion -; instance. Default is -1 (ALL). -; ATVStartTimeKeepCount = -1 - -; Turn on/off code coverage -; CodeCoverage = 0 - -; This option applies to condition and expression coverage UDP tables. It -; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. -; If this option is used and a match occurs in more than one row in the UDP table, -; none of the counts for all matching rows is incremented. By default, counts are -; incremented for all matching rows. -; CoverCountAll = 1 - -; Turn off automatic inclusion of VHDL integers in toggle coverage. Default -; is to include them. -; ToggleNoIntegers = 1 - -; Set the maximum number of values that are collected for toggle coverage of -; VHDL integers. Default is 100; -; ToggleMaxIntValues = 100 - -; Set the maximum number of values that are collected for toggle coverage of -; Verilog real. Default is 100; -; ToggleMaxRealValues = 100 - -; Turn on automatic inclusion of Verilog integers in toggle coverage, except -; for enumeration types. Default is to include them. -; ToggleVlogIntegers = 0 - -; Turn on automatic inclusion of Verilog real type in toggle coverage, except -; for shortreal types. Default is to not include them. -; ToggleVlogReal = 1 - -; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays -; and VHDL arrays-of-arrays in toggle coverage. -; Default is to not include them. -; ToggleFixedSizeArray = 1 - -; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, -; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. -; This leads to a longer simulation time with bigger arrays covered with toggle coverage. -; Default is 1024. -; ToggleMaxFixedSizeArray = 1024 - -; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized -; one-dimensional packed vectors for toggle coverage. Default is 0. -; TogglePackedAsVec = 0 - -; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for -; toggle coverage. Default is 0. -; ToggleVlogEnumBits = 0 - -; Turn off automatic inclusion of VHDL records in toggle coverage. -; Default is to include them. -; ToggleVHDLRecords = 0 - -; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. -; For unlimited width, set to 0. -; ToggleWidthLimit = 128 - -; Limit the counts that are tracked for toggle coverage. When all edges for a bit have -; reached this count, further activity on the bit is ignored. Default is 1. -; For unlimited counts, set to 0. -; ToggleCountLimit = 1 - -; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. -; Following is the toggle coverage calculation criteria based on extended toggle mode: -; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). -; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. -; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. -; ExtendedToggleMode = 3 - -; Enable toggle statistics collection only for ports. Default is 0. -; TogglePortsOnly = 1 - -; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has -; reached this count, further tracking of the input patterns linked to it is ignored. -; Default is 1. For unlimited counts, set to 0. -; NOTE: Changing this value from its default value may affect simulation performance. -; FecCountLimit = 1 - -; Limit the counts that are tracked for UDP Coverage. When a bin has -; reached this count, further tracking of the input patterns linked to it is ignored. -; Default is 1. For unlimited counts, set to 0. -; NOTE: Changing this value from its default value may affect simulation performance. -; UdpCountLimit = 1 - -; Control toggle coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either -; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; ToggleDeglitchPeriod = 10.0ps - -; Turn on/off all PSL/SVA cover directive enables. Default is on. -; CoverEnable = 0 - -; Turn on/off PSL/SVA cover log. Default is off "0". -; CoverLog = 1 - -; Set "at_least" value for all PSL/SVA cover directives. Default is 1. -; CoverAtLeast = 2 - -; Set "limit" value for all PSL/SVA cover directives. Default is -1. -; Any positive integer, -1 for infinity. -; CoverLimit = 1 - -; Specify the coverage database filename. -; Default is "" (i.e. database is NOT automatically saved on close). -; UCDBFilename = vsim.ucdb - -; Specify the maximum limit for the number of Cross (bin) products reported -; in XML and UCDB report against a Cross. A warning is issued if the limit -; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this -; setting. -; MaxReportRhsSVCrossProducts = 1000 - -; Specify the override for the "auto_bin_max" option for the Covergroups. -; If not specified then value from Covergroup "option" is used. -; SVCoverpointAutoBinMax = 64 - -; Specify the override for the value of "cross_num_print_missing" -; option for the Cross in Covergroups. If not specified then value -; specified in the "option.cross_num_print_missing" is used. This -; is a runtime option. NOTE: This overrides any "cross_num_print_missing" -; value specified by user in source file and any SVCrossNumPrintMissingDefault -; specified in modelsim.ini. -; SVCrossNumPrintMissing = 0 - -; Specify whether to use the value of "cross_num_print_missing" -; option in report and GUI for the Cross in Covergroups. If not specified then -; cross_num_print_missing is ignored for creating reports and displaying -; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". -; UseSVCrossNumPrintMissing = 0 - -; Specify the threshold of Coverpoint wildcard bin value range size, above which -; a warning will be triggered. The default is 4K -- 12 wildcard bits. -; SVCoverpointWildCardBinValueSizeWarn = 4096 - -; Specify the override for the value of "strobe" option for the -; Covergroup Type. If not specified then value in "type_option.strobe" -; will be used. This is runtime option which forces "strobe" to -; user specified value and supersedes user specified values in the -; SystemVerilog Code. NOTE: This also overrides the compile time -; default value override specified using "SVCovergroupStrobeDefault" -; SVCovergroupStrobe = 0 - -; Override for explicit assignments in source code to "option.goal" of -; SystemVerilog covergroup, coverpoint, and cross. It also overrides the -; default value of "option.goal" (defined to be 100 in the SystemVerilog -; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". -; SVCovergroupGoal = 100 - -; Override for explicit assignments in source code to "type_option.goal" of -; SystemVerilog covergroup, coverpoint, and cross. It also overrides the -; default value of "type_option.goal" (defined to be 100 in the SystemVerilog -; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". -; SVCovergroupTypeGoal = 100 - -; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() -; builtin functions, and report. This setting changes the default values of -; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 -; behavior if explicit assignments are not made on option.get_inst_coverage and -; type_option.merge_instances by the user. There are two vsim command line -; options, -cvg63 and -nocvg63 to override this setting from vsim command line. -; The default value of this variable from release 6.6 onwards is 0. This default -; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. -; SVCovergroup63Compatibility = 0 - -; Enforce the default behavior of covergroup get_coverage() builtin function, GUI -; and report. This variable sets the default value of type_option.merge_instances. -; There are two vsim command line options, -cvgmergeinstances and -; -nocvgmergeinstances to override this setting from vsim command line. -; The default value of this variable, -1 (don't care), allows the tool to determine -; the effective value, based on factors related to capacity and optimization. -; The type_option.merge_instances appears in the GUI and coverage reports as either -; auto(1) or auto(0), depending on whether the effective value was determined to -; be a 1 or a 0. -; SVCovergroupMergeInstancesDefault = -1 - -; Enable or disable generation of more detailed information about the sampling -; of covergroup, cross, and coverpoints. It provides the details of the number -; of times the covergroup instance and type were sampled, as well as details -; about why covergroup, cross and coverpoint were not covered. A non-zero value -; is to enable this feature. 0 is to disable this feature. Default is 0 -; SVCovergroupSampleInfo = 0 - -; Specify the maximum number of Coverpoint bins in whole design for -; all Covergroups. -; MaxSVCoverpointBinsDesign = 2147483648 - -; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins -; MaxSVCoverpointBinsInst = 1048576 - -; Specify the maximum number of Cross bins in whole design for -; all Covergroups. -; MaxSVCrossBinsDesign = 2147483648 - -; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins -; MaxSVCrossBinsInst = 67108864 - -; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. -; By default, this variable is set 0, in which case option.no_collect setting will take effect. -; If this variable is set to 1, all zero-weight coverage items will not be saved. -; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting -; of this variable. -; CvgZWNoCollect = 1 - -; Specify a space delimited list of double quoted TCL style -; regular expressions which will be matched against the text of all messages. -; If any regular expression is found to be contained within any message, the -; status for that message will not be propagated to the UCDB TESTSTATUS. -; If no match is detected, then the status will be propagated to the -; UCDB TESTSTATUS. More than one such regular expression text is allowed, -; and each message text is compared for each regular expression in the list. -; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" - -; Set weight for all PSL/SVA cover directives. Default is 1. -; CoverWeight = 2 - -; Check vsim plusargs. Default is 0 (off). -; 0 = Don't check plusargs -; 1 = Warning on unrecognized plusarg -; 2 = Error and exit on unrecognized plusarg -; CheckPlusargs = 1 - -; Load the specified shared objects with the RTLD_GLOBAL flag. -; This gives global visibility to all symbols in the shared objects, -; meaning that subsequently loaded shared objects can bind to symbols -; in the global shared objects. The list of shared objects should -; be whitespace delimited. This option is not supported on the -; Windows or AIX platforms. -; GlobalSharedObjectList = example1.so example2.so example3.so - -; Generate the stub definitions for the undefined symbols in the shared libraries being -; loaded in the simulation. When this flow is turned on, the undefined symbols will not -; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. -; The valid arguments are: on, off, verbose. -; on : turn on the automatic generation of stub definitions. -; off: turn off the flow. The undefined symbols will trigger an immediate load failure. -; verbose: Turn on the flow and report the undefined symbols for each shared library. -; NOTE: This variable can be overriden with vsim switch "-undefsyms". -; The default is on. -; -; UndefSyms = off - -; Enable the support for checkpointing foreign C/C++ libraries. -; The valid arguments are: 0, 1, 2 -; 0: off (default) -; 1: on (manually save/restore user shared library data) -; 2: auto (automatically save/restore user shared library data) -; This option is not supported on the Windows platforms. -; -; AllowCheckpointCpp = 2 - -; Initial seed for the random number generator of the root thread (SystemVerilog). -; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. -; The default value is 0. -; Sv_Seed = 0 - -; Specify the solver "engine" that vsim will select for constrained random -; generation. -; Valid values are: -; "auto" - automatically select the best engine for the current -; constraint scenario -; "bdd" - evaluate all constraint scenarios using the BDD solver engine -; "act" - evaluate all constraint scenarios using the ACT solver engine -; While the BDD solver engine is generally efficient with constraint scenarios -; involving bitwise logical relationships, the ACT solver engine can exhibit -; superior performance with constraint scenarios involving large numbers of -; random variables related via arithmetic operators (+, *, etc). -; NOTE: This variable can be overridden with the vsim "-solveengine" command -; line switch. -; The default value is "auto". -; SolveEngine = auto - -; Specifies the maximum size that a dynamic array may be resized to by the -; solver. If the solver attempts to resize a dynamic array to a size greater -; than the specified limit, the solver will abort with an error. -; The default value is 10000. A value of 0 indicates no limit. -; SolveArrayResizeMax = 10000 - -; Specify error message severity when randomize() and randomize(null) failures -; are detected. -; -; Integer value up to two digits are allowed with each digit having the following legal values: -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; -; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents -; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit) -; represents the setting for randomize(null) calls. -; -; 2) When a single digit value is used, the setting is applied to both normal randomize() call -; and randomize(null) call. -; -; Example: Fatal error for randomize() failures and NO error for randomize(null) failures -; -solvefailseverity=40 -; -; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is -; enabled, a constraint contradiction report will be displayed for randomize() calls that -; have a message severity >= warning (i.e. constraint contradiction reports will not be -; generated for randomize() calls having a "no error" severity level) -; -; NOTE: This variable can be overridden with the vsim "-solvefailseverity" command -; line switch. -; -; The default is 1 (warning). -; SolveFailSeverity = 1 - -; Error message severity for suppressible errors that are detected in a -; solve/before constraint. -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" -; command line switch. -; The default is 3 (failure). -; SolveBeforeErrorSeverity = 3 - -; Error message severity for suppressible errors that are related to -; solve engine capacity limits -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" -; command line switch. -; The default is 3 (failure). -; SolveEngineErrorSeverity = 3 - -; Enable/disable constraint conflicts on randomize() failure -; Valid values: -; 0 - disable solvefaildebug -; 1 - basic debug (no performance penalty) -; 2 - enhanced debug (runtime performance penalty) -; -; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is -; enabled, a constraint contradiction report will be displayed for randomize() calls that -; have a message severity >= warning (i.e. constraint contradiction reports will not be -; generated for randomize() calls having a "no error" severity level) -; -; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command -; line switch. -; -; The default is 1 (basic debug). -; SolveFailDebug = 1 - -; Upon encountering a randomize() failure, generate a simplified testcase that -; will reproduce the failure. Optionally output the testcase to a file. -; Testcases for 'no-solution' failures will only be produced if SolveFailDebug -; is enabled (see above). -; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" -; command line switch. -; The default is OFF (do not generate a testcase). To enable testcase -; generation, uncomment this variable. To redirect testcase generation to a -; file, specify the name of the output file. -; SolveFailTestcase = - -; Specify solver timeout threshold (in seconds). randomize() will fail if the -; CPU time required to evaluate any randset exceeds the specified timeout. -; The default value is 500. A value of 0 will disable timeout failures. -; SolveTimeout = 500 - -; Specify the alternative behavior during solver replay. Must be used when combined with -solvereplay switch. -; SolveReplayOpt=[+|-][,[+|-]]*" -' Valid settings: -; validate : toggle the checking of value changes of non-random variables involved in randomize(). (default is off)" -; SolveReplayOpt=validate - -; Specify the maximum size of the solution graph generated by the BDD solver. -; This value can be used to force the BDD solver to abort the evaluation of a -; complex constraint scenario that cannot be evaluated with finite memory. -; This value is specified in 1000s of nodes. -; The default value is 10000. A value of 0 indicates no limit. -; SolveGraphMaxSize = 10000 - -; Specify the maximum number of evaluations that may be performed on the -; solution graph by the BDD solver. This value can be used to force the BDD -; solver to abort the evaluation of a complex constraint scenario that cannot -; be evaluated in finite time. This value is specified in 10000s of evaluations. -; The default value is 10000. A value of 0 indicates no limit. -; SolveGraphMaxEval = 10000 - -; Specify random sequence compatiblity with a prior release. This -; option is used to get the same random sequences during simulation as -; as a prior release. Only prior releases with the same major version -; as the current release are allowed. -; NOTE: Only those random sequence changes due to solver optimizations are -; reverted by this variable. Random sequence changes due to solver bugfixes -; cannot be un-done. -; NOTE: This variable can be overridden with the vsim "-solverev" command -; line switch. -; Default value set to "" (no compatibility). -; SolveRev = - -; Environment variable expansion of command line arguments has been depricated -; in favor shell level expansion. Universal environment variable expansion -; inside -f files is support and continued support for MGC Location Maps provide -; alternative methods for handling flexible pathnames. -; The following line may be uncommented and the value set to 1 to re-enable this -; deprecated behavior. The default value is 0. -; DeprecatedEnvironmentVariableExpansion = 0 - -; Specify the memory threshold for the System Verilog garbage collector. -; The value is the number of megabytes of class objects that must accumulate -; before the garbage collector is run. -; The GCThreshold setting is used when class debug mode is disabled to allow -; less frequent garbage collection and better simulation performance. -; The GCThresholdClassDebug setting is used when class debug mode is enabled -; to allow for more frequent garbage collection. -; GCThreshold = 100 -; GCThresholdClassDebug = 5 - -; Turn on/off collapsing of bus ports in VCD dumpports output -DumpportsCollapse = 1 - -; Location of Multi-Level Verification Component (MVC) installation. -; The default location is the product installation directory. -MvcHome = $QUESTA_MVC_HOME - -; Location of InFact installation. The default is $MODEL_TECH/../../infact -; -; InFactHome = $MODEL_TECH/../../infact - -; Initialize SystemVerilog enums using the base type's default value -; instead of the leftmost value. -; EnumBaseInit = 1 - -; Suppress file type registration. -; SuppressFileTypeReg = 1 - -; Enable/disable non-LRM compliant SystemVerilog language extensions. -; Valid extensions are: -; altdpiheader - Alternative style function signature generated in DPI header", -; cfce - generate an error if $cast fails as a function -; cfmt - C like formatting for specifiers with '#' prefix ('%#x', '%#h') -; dfsp - sets default format specifier as %p, if no format specifier is given for unpacked array in $display and related systasks -; expdfmt - enable format string extensions for $display/$sformatf -; extscan - support values greater than 32 bit for string builtin methods (atohex, atobin, atooct, atoi) -; fmtcap - prints capital hex digits with %X/%H in display calls -; iddp - ignore DPI disable protocol check -; lfmt - zero-pad data if '0' prefixes width in format specifier (e.g. "%04h") -; noexptc - ignore DPI export type name overloading check -; realrand - support randomize() with real variables and constraints (Default) -; SvExtensions = [+|-][,[+|-]*] - -; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions. -; Valid extensions are: -; arraymode - consider rand_mode of unpacked array field independently from its elements -; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles (Default) -; funcback - enable function backtracking (ACT only) -; genmodseedfix - enable LRM-compliant seeding of module/interface instances under for-generate blocks (Default) -; nodist - interpret 'dist' constraint as 'inside' (ACT only) -; noorder - ignore solve/before ordering constraints (ACT only) -; pathseed - enable unique seeding of module instances based on hierarchical path name -; prerandfirst - execute all pre_randomize() functions before evaluating any constraints -; promotedist - promote priority of 'dist' constraint if LHS has no solve/before -; purecheck - suppress pre_randomize() and post_randomize() calls for randomize(null) -; randindex - allow random index in constraint (Default) -; randstruct - consider all fields of unpacked structs as 'rand' -; skew - skew randomize results (ACT only) -; strictstab - strict random stability -; SvRandExtensions = [+|-][,[+|-]*] - -; Controls the formatting of '%p' and '%P' conversion specification, used in $display -; and similar system tasks. -; 1. SVPrettyPrintFlags=I use spaces(S) or tabs(T) per indentation level. -; The 'I' flag when present causes relevant data types to be expanded and indented into -; a more readable format. -; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). -; 2. SVPrettyPrintFlags=L limits the output to lines. -; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). -; 3. SVPrettyPrintFlags=C limits the output to characters. -; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). -; 4. SVPrettyPrintFlags=F limits the output to of relevant datatypes -; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). -; 5. SVPrettyPrintFlags=E limits the output to of relevant datatypes -; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). -; 6. SVPrettyPrintFlags=D suppresses the output of sub-elements below . -; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). -; 7. SVPrettyPrintFlags=R shows the output of specifier %p as per the specifed radix. -; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)). -; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format. -; 8. Items 1-7 above can be combined as a comma separated list. -; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb) -; SVPrettyPrintFlags=I4S - -[lmc] -; The simulator's interface to Logic Modeling's SmartModel SWIFT software -libsm = $MODEL_TECH/libsm.sl -; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) -; libsm = $MODEL_TECH/libsm.dll -; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) -; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl -; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) -; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o -; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) -; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so -; Logic Modeling's SmartModel SWIFT software (Windows NT) -; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll -; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) -; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so -; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) -; libswift = $LMC_HOME/lib/linux.lib/libswift.so - -; The simulator's interface to Logic Modeling's hardware modeler SFI software -libhm = $MODEL_TECH/libhm.sl -; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) -; libhm = $MODEL_TECH/libhm.dll -; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) -; libsfi = /lib/hp700/libsfi.sl -; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) -; libsfi = /lib/rs6000/libsfi.a -; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) -; libsfi = /lib/sun4.solaris/libsfi.so -; Logic Modeling's hardware modeler SFI software (Windows NT) -; libsfi = /lib/pcnt/lm_sfi.dll -; Logic Modeling's hardware modeler SFI software (Linux) -; libsfi = /lib/linux/libsfi.so - -[msg_system] -; Change a message severity or suppress a message. -; The format is: = [,...] -; suppress can be used to achieve +nowarn functionality -; The format is: suppress = ,,[,,...] -; Examples: -suppress = 8780 ;an explanation can be had by running: verror 8780 -; note = 3009 -; warning = 3033 -; error = 3010,3016 -; fatal = 3016,3033 -; suppress = 3009,3016,3601 -; suppress = 3009,CNNODP,3601,TFMPC -; suppress = 8683,8684 -; The command verror can be used to get the complete -; description of a message. - -; Control transcripting of Verilog display system task messages and -; PLI/FLI print function call messages. The system tasks include -; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They -; also include the analogous file I/O tasks that write to STDOUT -; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, -; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default -; is to have messages appear only in the transcript. The other -; settings are to send messages to the wlf file only (messages that -; are recorded in the wlf file can be viewed in the MsgViewer) or -; to both the transcript and the wlf file. The valid values are -; tran {transcript only (default)} -; wlf {wlf file only} -; both {transcript and wlf file} -; displaymsgmode = tran - -; Control transcripting of elaboration/runtime messages not -; addressed by the displaymsgmode setting. The default is to -; have messages appear only in the transcript. The other settings -; are to send messages to the wlf file only (messages that are -; recorded in the wlf file can be viewed in the MsgViewer) or to both -; the transcript and the wlf file. The valid values are -; tran {transcript only (default)} -; wlf {wlf file only} -; both {transcript and wlf file} -; msgmode = tran - -; Controls number of displays of a particluar message -; default value is 5 -; MsgLimitCount = 5 - -[utils] -; Default Library Type (while creating a library with "vlib") -; 0 - legacy library using subdirectories for design units -; 2 - flat library -; DefaultLibType = 2 - -; Flat Library Page Size (while creating a library with "vlib") -; Set the size in bytes for flat library file pages. Libraries containing -; very large files may benefit from a larger value. -; FlatLibPageSize = 8192 - -; Flat Library Page Cleanup Percentage (while creating a library with "vlib") -; Set the percentage of total pages deleted before library cleanup can occur. -; This setting is applied together with FlatLibPageDeleteThreshold. -; FlatLibPageDeletePercentage = 50 - -; Flat Library Page Cleanup Threshold (while creating a library with "vlib") -; Set the number of pages deleted before library cleanup can occur. -; This setting is applied together with FlatLibPageDeletePercentage. -; FlatLibPageDeleteThreshold = 1000 - - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/simulate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/simulate.do deleted file mode 100644 index d9a90b96..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/simulate.do +++ /dev/null @@ -1,16 +0,0 @@ -onbreak {quit -f} -onerror {quit -f} - -vsim -voptargs="+acc" -t 1ps -L blk_mem_gen_v8_4_3 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.COSLUT_10_16bit xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure -view signals - -do {COSLUT_10_16bit.udo} - -run -all - -quit -force diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/wave.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/modelsim/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/COSLUT_10_16bit.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/COSLUT_10_16bit.mif deleted file mode 100644 index af6c440d..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/COSLUT_10_16bit.mif +++ /dev/null @@ -1,8192 +0,0 @@ -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111101 -011111111111111101 -011111111111111101 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-000000000101000111 -000000000100101110 -000000000100010100 -000000000011111011 -000000000011100010 -000000000011001001 -000000000010110000 -000000000010010111 -000000000001111110 -000000000001100101 -000000000001001011 -000000000000110010 -000000000000011001 -000000000000000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/COSLUT_10_16bit.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/COSLUT_10_16bit.sh deleted file mode 100644 index 07c9eeae..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/COSLUT_10_16bit.sh +++ /dev/null @@ -1,175 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : COSLUT_10_16bit.sh -# Simulator : Mentor Graphics Questa Advanced Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:35:15 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: COSLUT_10_16bit.sh [-help] -# usage: COSLUT_10_16bit.sh [-lib_map_path] -# usage: COSLUT_10_16bit.sh [-noclean_files] -# usage: COSLUT_10_16bit.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'COSLUT_10_16bit.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "COSLUT_10_16bit.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -elaborate() -{ - source elaborate.do 2>&1 | tee -a elaborate.log -} - -# RUN_STEP: -simulate() -{ - vsim -64 -c -do "do {simulate.do}" -l simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./COSLUT_10_16bit.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Copy modelsim.ini file -copy_setup_file() -{ - file="modelsim.ini" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then - lib_map_path="$1" - else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - cp $src_file . - fi -} - -# Create design library directory -create_lib_dir() -{ - lib_dir="questa_lib" - if [[ -e $lib_dir ]]; then - rm -rf $lib_dir - fi - - mkdir $lib_dir - -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./COSLUT_10_16bit.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: COSLUT_10_16bit.sh [-help]\n\ -Usage: COSLUT_10_16bit.sh [-lib_map_path]\n\ -Usage: COSLUT_10_16bit.sh [-reset_run]\n\ -Usage: COSLUT_10_16bit.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/COSLUT_10_16bit.udo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/COSLUT_10_16bit.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/README.txt deleted file mode 100644 index c007b0f1..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:35:15 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./COSLUT_10_16bit.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './COSLUT_10_16bit.sh' script. - -./COSLUT_10_16bit.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./COSLUT_10_16bit.sh -noclean_files - -For more information on the script, please type './COSLUT_10_16bit.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/compile.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/compile.do deleted file mode 100644 index 46d5193a..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/compile.do +++ /dev/null @@ -1,27 +0,0 @@ -vlib questa_lib/work -vlib questa_lib/msim - -vlib questa_lib/msim/xil_defaultlib -vlib questa_lib/msim/xpm -vlib questa_lib/msim/blk_mem_gen_v8_4_3 - -vmap xil_defaultlib questa_lib/msim/xil_defaultlib -vmap xpm questa_lib/msim/xpm -vmap blk_mem_gen_v8_4_3 questa_lib/msim/blk_mem_gen_v8_4_3 - -vlog -work xil_defaultlib -64 -sv \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -64 -93 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work blk_mem_gen_v8_4_3 -64 \ -"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ - -vlog -work xil_defaultlib -64 \ -"../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/cos_8192_18bit.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/cos_8192_18bit.coe deleted file mode 100644 index 1568f12a..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/cos_8192_18bit.coe +++ /dev/null @@ -1,8194 +0,0 @@ -memory_initialization_radix=10; -memory_initialization_vector= -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 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-1961 -1935 -1910 -1885 -1860 -1835 -1810 -1785 -1759 -1734 -1709 -1684 -1659 -1634 -1609 -1584 -1558 -1533 -1508 -1483 -1458 -1433 -1408 -1382 -1357 -1332 -1307 -1282 -1257 -1232 -1206 -1181 -1156 -1131 -1106 -1081 -1056 -1031 -1005 -980 -955 -930 -905 -880 -855 -829 -804 -779 -754 -729 -704 -679 -654 -628 -603 -578 -553 -528 -503 -478 -452 -427 -402 -377 -352 -327 -302 -276 -251 -226 -201 -176 -151 -126 -101 -75 -50 -25 -0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/elaborate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/elaborate.do deleted file mode 100644 index d356746e..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/elaborate.do +++ /dev/null @@ -1 +0,0 @@ -vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.COSLUT_10_16bit xil_defaultlib.glbl -o COSLUT_10_16bit_opt diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/file_info.txt deleted file mode 100644 index a5ce948f..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, -COSLUT_10_16bit.v,verilog,xil_defaultlib,../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/simulate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/simulate.do deleted file mode 100644 index 4255df17..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/simulate.do +++ /dev/null @@ -1,16 +0,0 @@ -onbreak {quit -f} -onerror {quit -f} - -vsim -t 1ps -lib xil_defaultlib COSLUT_10_16bit_opt - -do {wave.do} - -view wave -view structure -view signals - -do {COSLUT_10_16bit.udo} - -run -all - -quit -force diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/wave.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/questa/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/COSLUT_10_16bit.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/COSLUT_10_16bit.mif deleted file mode 100644 index af6c440d..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/COSLUT_10_16bit.mif +++ /dev/null @@ -1,8192 +0,0 @@ -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111101 -011111111111111101 -011111111111111101 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-000000000101000111 -000000000100101110 -000000000100010100 -000000000011111011 -000000000011100010 -000000000011001001 -000000000010110000 -000000000010010111 -000000000001111110 -000000000001100101 -000000000001001011 -000000000000110010 -000000000000011001 -000000000000000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/COSLUT_10_16bit.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/COSLUT_10_16bit.sh deleted file mode 100644 index 5f4132e0..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/COSLUT_10_16bit.sh +++ /dev/null @@ -1,154 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : COSLUT_10_16bit.sh -# Simulator : Aldec Riviera-PRO Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:35:15 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: COSLUT_10_16bit.sh [-help] -# usage: COSLUT_10_16bit.sh [-lib_map_path] -# usage: COSLUT_10_16bit.sh [-noclean_files] -# usage: COSLUT_10_16bit.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'COSLUT_10_16bit.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "COSLUT_10_16bit.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - runvsimsa -l simulate.log -do "do {simulate.do}" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./COSLUT_10_16bit.sh -help\" for more information)\n" - exit 1 - fi - map_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - map_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Map library.cfg file -map_setup_file() -{ - file="library.cfg" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then - lib_map_path="$1" - else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - vmap -link $lib_map_path - fi - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./COSLUT_10_16bit.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: COSLUT_10_16bit.sh [-help]\n\ -Usage: COSLUT_10_16bit.sh [-lib_map_path]\n\ -Usage: COSLUT_10_16bit.sh [-reset_run]\n\ -Usage: COSLUT_10_16bit.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/COSLUT_10_16bit.udo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/COSLUT_10_16bit.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/README.txt deleted file mode 100644 index c007b0f1..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:35:15 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./COSLUT_10_16bit.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './COSLUT_10_16bit.sh' script. - -./COSLUT_10_16bit.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./COSLUT_10_16bit.sh -noclean_files - -For more information on the script, please type './COSLUT_10_16bit.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/compile.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/compile.do deleted file mode 100644 index 94b6ff95..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/compile.do +++ /dev/null @@ -1,27 +0,0 @@ -vlib work -vlib riviera - -vlib riviera/xil_defaultlib -vlib riviera/xpm -vlib riviera/blk_mem_gen_v8_4_3 - -vmap xil_defaultlib riviera/xil_defaultlib -vmap xpm riviera/xpm -vmap blk_mem_gen_v8_4_3 riviera/blk_mem_gen_v8_4_3 - -vlog -work xil_defaultlib -sv2k12 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -93 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work blk_mem_gen_v8_4_3 -v2k5 \ -"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ - -vlog -work xil_defaultlib -v2k5 \ -"../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/cos_8192_18bit.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/cos_8192_18bit.coe deleted file mode 100644 index 1568f12a..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/cos_8192_18bit.coe +++ /dev/null @@ -1,8194 +0,0 @@ -memory_initialization_radix=10; -memory_initialization_vector= -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131070 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-1634 -1609 -1584 -1558 -1533 -1508 -1483 -1458 -1433 -1408 -1382 -1357 -1332 -1307 -1282 -1257 -1232 -1206 -1181 -1156 -1131 -1106 -1081 -1056 -1031 -1005 -980 -955 -930 -905 -880 -855 -829 -804 -779 -754 -729 -704 -679 -654 -628 -603 -578 -553 -528 -503 -478 -452 -427 -402 -377 -352 -327 -302 -276 -251 -226 -201 -176 -151 -126 -101 -75 -50 -25 -0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/file_info.txt deleted file mode 100644 index a5ce948f..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, -COSLUT_10_16bit.v,verilog,xil_defaultlib,../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/simulate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/simulate.do deleted file mode 100644 index 2d1b6265..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/simulate.do +++ /dev/null @@ -1,17 +0,0 @@ -onbreak {quit -force} -onerror {quit -force} - -asim -t 1ps +access +r +m+COSLUT_10_16bit -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.COSLUT_10_16bit xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure - -do {COSLUT_10_16bit.udo} - -run -all - -endsim - -quit -force diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/wave.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/riviera/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/vcs/COSLUT_10_16bit.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/vcs/COSLUT_10_16bit.mif deleted file mode 100644 index af6c440d..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/vcs/COSLUT_10_16bit.mif +++ /dev/null @@ -1,8192 +0,0 @@ -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 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09b04a61..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/vcs/COSLUT_10_16bit.sh +++ /dev/null @@ -1,233 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : COSLUT_10_16bit.sh -# Simulator : Synopsys Verilog Compiler Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:35:15 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: COSLUT_10_16bit.sh [-help] -# usage: COSLUT_10_16bit.sh [-lib_map_path] -# usage: COSLUT_10_16bit.sh [-noclean_files] -# usage: COSLUT_10_16bit.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'COSLUT_10_16bit.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Command line options -vlogan_opts="-full64" -vhdlan_opts="-full64" -vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" -vcs_sim_opts="-ucli -licqueue -l simulate.log" - -# Design libraries -design_libs=(xil_defaultlib xpm blk_mem_gen_v8_4_3) - -# Simulation root library directory -sim_lib_dir="vcs_lib" - -# Script info -echo -e "COSLUT_10_16bit.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - vlogan -work xil_defaultlib $vlogan_opts -sverilog \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - 2>&1 | tee -a vlogan.log - - vhdlan -work xpm $vhdlan_opts \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - 2>&1 | tee -a vhdlan.log - - vlogan -work blk_mem_gen_v8_4_3 $vlogan_opts +v2k \ - "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ - 2>&1 | tee -a vlogan.log - - vlogan -work xil_defaultlib $vlogan_opts +v2k \ - "$ref_dir/../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v" \ - 2>&1 | tee -a vlogan.log - - - vlogan -work xil_defaultlib $vlogan_opts +v2k \ - glbl.v \ - 2>&1 | tee -a vlogan.log - -} - -# RUN_STEP: -elaborate() -{ - vcs $vcs_elab_opts xil_defaultlib.COSLUT_10_16bit xil_defaultlib.glbl -o COSLUT_10_16bit_simv -} - -# RUN_STEP: -simulate() -{ - ./COSLUT_10_16bit_simv $vcs_sim_opts -do simulate.do -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./COSLUT_10_16bit.sh -help\" for more information)\n" - exit 1 - fi - create_lib_mappings $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - create_lib_mappings $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Define design library mappings -create_lib_mappings() -{ - file="synopsys_sim.setup" - if [[ -e $file ]]; then - if [[ ($1 == "") ]]; then - return - else - rm -rf $file - fi - fi - - touch $file - - lib_map_path="" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - mapping="$lib:$sim_lib_dir/$lib" - echo $mapping >> $file - done - - if [[ ($lib_map_path != "") ]]; then - incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" - echo $incl_ref >> $file - fi -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(ucli.key COSLUT_10_16bit_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc COSLUT_10_16bit_simv.daidir) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./COSLUT_10_16bit.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: COSLUT_10_16bit.sh [-help]\n\ -Usage: COSLUT_10_16bit.sh [-lib_map_path]\n\ -Usage: COSLUT_10_16bit.sh [-reset_run]\n\ -Usage: COSLUT_10_16bit.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/vcs/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/vcs/README.txt deleted file mode 100644 index c007b0f1..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/vcs/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:35:15 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./COSLUT_10_16bit.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './COSLUT_10_16bit.sh' script. - -./COSLUT_10_16bit.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./COSLUT_10_16bit.sh -noclean_files - -For more information on the script, please type './COSLUT_10_16bit.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/vcs/cos_8192_18bit.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/vcs/cos_8192_18bit.coe deleted file mode 100644 index 1568f12a..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/vcs/cos_8192_18bit.coe +++ /dev/null @@ -1,8194 +0,0 @@ -memory_initialization_radix=10; -memory_initialization_vector= -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131069 -131069 -131069 -131069 -131069 -131069 -131069 -131069 -131068 -131068 -131068 -131068 -131068 -131068 -131067 -131067 -131067 -131067 -131067 -131066 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-930 -905 -880 -855 -829 -804 -779 -754 -729 -704 -679 -654 -628 -603 -578 -553 -528 -503 -478 -452 -427 -402 -377 -352 -327 -302 -276 -251 -226 -201 -176 -151 -126 -101 -75 -50 -25 -0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/vcs/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/vcs/file_info.txt deleted file mode 100644 index a5ce948f..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/vcs/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, -COSLUT_10_16bit.v,verilog,xil_defaultlib,../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/vcs/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/vcs/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/vcs/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/vcs/simulate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/vcs/simulate.do deleted file mode 100644 index 58afc787..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/vcs/simulate.do +++ /dev/null @@ -1,2 +0,0 @@ -run -quit diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xcelium/COSLUT_10_16bit.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xcelium/COSLUT_10_16bit.mif deleted file mode 100644 index af6c440d..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xcelium/COSLUT_10_16bit.mif +++ /dev/null @@ -1,8192 +0,0 @@ -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 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a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xcelium/COSLUT_10_16bit.sh +++ /dev/null @@ -1,175 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : COSLUT_10_16bit.sh -# Simulator : Cadence Xcelium Parallel Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:35:15 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: COSLUT_10_16bit.sh [-help] -# usage: COSLUT_10_16bit.sh [-lib_map_path] -# usage: COSLUT_10_16bit.sh [-noclean_files] -# usage: COSLUT_10_16bit.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'COSLUT_10_16bit.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Set the compiled library directory -ref_lib_dir="." - -# Command line options -xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" - -# Design libraries -design_libs=(xil_defaultlib xpm blk_mem_gen_v8_4_3) - -# Simulation root library directory -sim_lib_dir="xcelium_lib" - -# Script info -echo -e "COSLUT_10_16bit.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - execute -} - -# RUN_STEP: -execute() -{ - xrun $xrun_opts \ - -reflib "$ref_lib_dir/unisim:unisim" \ - -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ - -reflib "$ref_lib_dir/secureip:secureip" \ - -reflib "$ref_lib_dir/unimacro:unimacro" \ - -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.COSLUT_10_16bit \ - -f run.f \ - -top glbl \ - glbl.v -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./COSLUT_10_16bit.sh -help\" for more information)\n" - exit 1 - else - ref_lib_dir=$2 - fi - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./COSLUT_10_16bit.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: COSLUT_10_16bit.sh [-help]\n\ -Usage: COSLUT_10_16bit.sh [-lib_map_path]\n\ -Usage: COSLUT_10_16bit.sh [-reset_run]\n\ -Usage: COSLUT_10_16bit.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xcelium/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xcelium/README.txt deleted file mode 100644 index bfa3fc14..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xcelium/README.txt +++ /dev/null @@ -1,48 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:35:15 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./COSLUT_10_16bit.sh - -This command will launch the 'execute' function for the single-step flow. This -function is called from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './COSLUT_10_16bit.sh' script. - -./COSLUT_10_16bit.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./COSLUT_10_16bit.sh -noclean_files - -For more information on the script, please type './COSLUT_10_16bit.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xcelium/cos_8192_18bit.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xcelium/cos_8192_18bit.coe deleted file mode 100644 index 1568f12a..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xcelium/cos_8192_18bit.coe +++ /dev/null @@ -1,8194 +0,0 @@ -memory_initialization_radix=10; -memory_initialization_vector= -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131069 -131069 -131069 -131069 -131069 -131069 -131069 -131069 -131068 -131068 -131068 -131068 -131068 -131068 -131067 -131067 -131067 -131067 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-1031 -1005 -980 -955 -930 -905 -880 -855 -829 -804 -779 -754 -729 -704 -679 -654 -628 -603 -578 -553 -528 -503 -478 -452 -427 -402 -377 -352 -327 -302 -276 -251 -226 -201 -176 -151 -126 -101 -75 -50 -25 -0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xcelium/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xcelium/file_info.txt deleted file mode 100644 index a5ce948f..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xcelium/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, -COSLUT_10_16bit.v,verilog,xil_defaultlib,../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xcelium/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xcelium/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xcelium/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xcelium/run.f b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xcelium/run.f deleted file mode 100644 index 7b7f3ab5..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xcelium/run.f +++ /dev/null @@ -1,17 +0,0 @@ --makelib xcelium_lib/xil_defaultlib -sv \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ --endlib --makelib xcelium_lib/xpm \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ --endlib --makelib xcelium_lib/blk_mem_gen_v8_4_3 \ - "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ --endlib --makelib xcelium_lib/xil_defaultlib \ - "../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v" \ --endlib --makelib xcelium_lib/xil_defaultlib \ - glbl.v --endlib - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/COSLUT_10_16bit.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/COSLUT_10_16bit.mif deleted file mode 100644 index af6c440d..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/COSLUT_10_16bit.mif +++ /dev/null @@ -1,8192 +0,0 @@ -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111111 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111110 -011111111111111101 -011111111111111101 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-000000000101100000 -000000000101000111 -000000000100101110 -000000000100010100 -000000000011111011 -000000000011100010 -000000000011001001 -000000000010110000 -000000000010010111 -000000000001111110 -000000000001100101 -000000000001001011 -000000000000110010 -000000000000011001 -000000000000000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/COSLUT_10_16bit.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/COSLUT_10_16bit.sh deleted file mode 100644 index db93e3d8..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/COSLUT_10_16bit.sh +++ /dev/null @@ -1,212 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : COSLUT_10_16bit.sh -# Simulator : Xilinx Vivado Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:35:15 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: COSLUT_10_16bit.sh [-help] -# usage: COSLUT_10_16bit.sh [-lib_map_path] -# usage: COSLUT_10_16bit.sh [-noclean_files] -# usage: COSLUT_10_16bit.sh [-reset_run] -# -#********************************************************************************************************* - -# Command line options -xv_boost_lib_path=C:/Xilinx/Vivado/2019.1/tps/boost_1_64_0 -xvlog_opts="--relax" - - -# Script info -echo -e "COSLUT_10_16bit.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log - -} - -# RUN_STEP: -elaborate() -{ - xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_3 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot COSLUT_10_16bit xil_defaultlib.COSLUT_10_16bit xil_defaultlib.glbl -log elaborate.log -} - -# RUN_STEP: -simulate() -{ - xsim COSLUT_10_16bit -key {Behavioral:sim_1:Functional:COSLUT_10_16bit} -tclbatch cmd.tcl -log simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./COSLUT_10_16bit.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Copy xsim.ini file -copy_setup_file() -{ - file="xsim.ini" - lib_map_path="C:/Xilinx/Vivado/2019.1/data/xsim" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - cp $src_file . - fi - - # Map local design libraries to xsim.ini - map_local_libs - - fi -} - -# Map local design libraries -map_local_libs() -{ - updated_mappings=() - local_mappings=() - - # Local design libraries - local_libs=() - - if [[ 0 == ${#local_libs[@]} ]]; then - return - fi - - file="xsim.ini" - file_backup="xsim.ini.bak" - - if [[ -e $file ]]; then - rm -f $file_backup - # Create a backup copy of the xsim.ini file - cp $file $file_backup - # Read libraries from backup file and search in local library collection - while read -r line - do - IN=$line - # Split mapping entry with '=' delimiter to fetch library name and mapping - read lib_name mapping <<<$(IFS="="; echo $IN) - # If local library found, then construct the local mapping and add to local mapping collection - if `echo ${local_libs[@]} | grep -wq $lib_name` ; then - line="$lib_name=xsim.dir/$lib_name" - local_mappings+=("$lib_name") - fi - # Add to updated library mapping collection - updated_mappings+=("$line") - done < "$file_backup" - # Append local libraries not found originally from xsim.ini - for (( i=0; i<${#local_libs[*]}; i++ )); do - lib_name="${local_libs[i]}" - if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then - line="$lib_name=xsim.dir/$lib_name" - updated_mappings+=("$line") - fi - done - # Write updated mappings in xsim.ini - rm -f $file - for (( i=0; i<${#updated_mappings[*]}; i++ )); do - lib_name="${updated_mappings[i]}" - echo $lib_name >> $file - done - else - for (( i=0; i<${#local_libs[*]}; i++ )); do - lib_name="${local_libs[i]}" - mapping="$lib_name=xsim.dir/$lib_name" - echo $mapping >> $file - done - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb COSLUT_10_16bit.wdb xsim.dir) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./COSLUT_10_16bit.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: COSLUT_10_16bit.sh [-help]\n\ -Usage: COSLUT_10_16bit.sh [-lib_map_path]\n\ -Usage: COSLUT_10_16bit.sh [-reset_run]\n\ -Usage: COSLUT_10_16bit.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/README.txt deleted file mode 100644 index c007b0f1..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:35:15 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./COSLUT_10_16bit.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './COSLUT_10_16bit.sh' script. - -./COSLUT_10_16bit.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./COSLUT_10_16bit.sh -noclean_files - -For more information on the script, please type './COSLUT_10_16bit.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/cmd.tcl b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/cmd.tcl deleted file mode 100644 index eef7a0f0..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/cmd.tcl +++ /dev/null @@ -1,12 +0,0 @@ -set curr_wave [current_wave_config] -if { [string length $curr_wave] == 0 } { - if { [llength [get_objects]] > 0} { - add_wave / - set_property needs_save false [current_wave_config] - } else { - send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." - } -} - -run -all -quit diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/cos_8192_18bit.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/cos_8192_18bit.coe deleted file mode 100644 index 1568f12a..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/cos_8192_18bit.coe +++ /dev/null @@ -1,8194 +0,0 @@ -memory_initialization_radix=10; -memory_initialization_vector= -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131071 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131070 -131069 -131069 -131069 -131069 -131069 -131069 -131069 -131069 -131068 -131068 -131068 -131068 -131068 -131068 -131067 -131067 -131067 -131067 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-1031 -1005 -980 -955 -930 -905 -880 -855 -829 -804 -779 -754 -729 -704 -679 -654 -628 -603 -578 -553 -528 -503 -478 -452 -427 -402 -377 -352 -327 -302 -276 -251 -226 -201 -176 -151 -126 -101 -75 -50 -25 -0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/elab.opt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/elab.opt deleted file mode 100644 index d17271f4..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/elab.opt +++ /dev/null @@ -1 +0,0 @@ ---relax --debug typical --mt auto -L blk_mem_gen_v8_4_3 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot COSLUT_10_16bit xil_defaultlib.COSLUT_10_16bit xil_defaultlib.glbl -log elaborate.log diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/file_info.txt deleted file mode 100644 index 28a0c037..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/file_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -COSLUT_10_16bit.v,verilog,xil_defaultlib,../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/vlog.prj b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/vlog.prj deleted file mode 100644 index d4f183cd..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/vlog.prj +++ /dev/null @@ -1,6 +0,0 @@ -verilog xil_defaultlib \ -"../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v" \ - -verilog xil_defaultlib "glbl.v" - -nosort diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/xsim.ini b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/xsim.ini deleted file mode 100644 index 6cb07f57..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/COSLUT_10_16bit/xsim/xsim.ini +++ /dev/null @@ -1,430 +0,0 @@ -std=$RDI_DATADIR/xsim/vhdl/std -ieee=$RDI_DATADIR/xsim/vhdl/ieee -ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed -vl=$RDI_DATADIR/xsim/vhdl/vl -synopsys=$RDI_DATADIR/xsim/vhdl/synopsys -secureip=$RDI_DATADIR/xsim/verilog/secureip -unisim=$RDI_DATADIR/xsim/vhdl/unisim -unimacro=$RDI_DATADIR/xsim/vhdl/unimacro -unifast=$RDI_DATADIR/xsim/vhdl/unifast -unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver -unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver -unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver -simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver -system_cache_v4_0_6=$RDI_DATADIR/xsim/ip/system_cache_v4_0_6 -bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0 -g709_rs_decoder_v2_2_8=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_8 -xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0 -mipi_dphy_v4_1_4=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_1_4 -iomodule_v3_1_4=$RDI_DATADIR/xsim/ip/iomodule_v3_1_4 -ieee802d3_50g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_11 -common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0 -lte_fft_v2_1_0=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_0 -ieee802d3_50g_rs_fec_v2_0_1=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_1 -convolution_v9_0_14=$RDI_DATADIR/xsim/ip/convolution_v9_0_14 -gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4 -v_cfa_v7_0_14=$RDI_DATADIR/xsim/ip/v_cfa_v7_0_14 -axi4svideo_bridge_v1_0_10=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_10 -pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11 -v_vscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_13 -xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6 -gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux -ethernet_1_10_25g_v2_2_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_2_3 -zynq_ultra_ps_e_v3_3_0=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_0 -v_cresample_v4_0_14=$RDI_DATADIR/xsim/ip/v_cresample_v4_0_14 -v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9 -v_scenechange_v1_0_1=$RDI_DATADIR/xsim/ip/v_scenechange_v1_0_1 -hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0 -ahblite_axi_bridge_v3_0_14=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_14 -tri_mode_ethernet_mac_v9_0_14=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_14 -blk_mem_gen_v8_4_3=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_3 -noc_mc_ddr4_phy_v1_0_0=$RDI_DATADIR/xsim/ip/noc_mc_ddr4_phy_v1_0_0 -axi_data_fifo_v2_1_18=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_18 -axi_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_5 -ethernet_1_10_25g_v2_0_5=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_0_5 -compact_gt_v1_0_5=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_5 -axi_gpio_v2_0_21=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_21 -qdma_v3_0_2=$RDI_DATADIR/xsim/ip/qdma_v3_0_2 -viterbi_v9_1_11=$RDI_DATADIR/xsim/ip/viterbi_v9_1_11 -sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2 -ba317=$RDI_DATADIR/xsim/ip/ba317 -xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4 -fifo_generator_v13_2_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_4 -axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14 -vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0 -axi_emc_v3_0_19=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_19 -cmac_v2_5_1=$RDI_DATADIR/xsim/ip/cmac_v2_5_1 -floating_point_v7_1_8=$RDI_DATADIR/xsim/ip/floating_point_v7_1_8 -xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6 -vid_phy_controller_v2_2_3=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_3 -common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1 -axi_firewall_v1_0_7=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_7 -util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1 -axis_accelerator_adapter_v2_1_15=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_15 -tmr_comparator_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_2 -sd_fec_v1_0_2=$RDI_DATADIR/xsim/ip/sd_fec_v1_0_2 -tmr_manager_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_4 -tsn_temac_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_4 -usxgmii_v1_0_5=$RDI_DATADIR/xsim/ip/usxgmii_v1_0_5 -lte_dl_channel_encoder_v4_0_0=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v4_0_0 -ai_noc=$RDI_DATADIR/xsim/ip/ai_noc -lte_3gpp_mimo_decoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_15 -v_uhdsdi_audio_v1_0_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_0_0 -axi4stream_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_5 -cmac_usplus_v2_4_5=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_4_5 -etrnic_v1_1_2=$RDI_DATADIR/xsim/ip/etrnic_v1_1_2 -floating_point_v7_0_16=$RDI_DATADIR/xsim/ip/floating_point_v7_0_16 -axi_dma_v7_1_20=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_20 -jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi -axi_traffic_gen_v3_0_5=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_5 -emb_mem_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_1 -axi_amm_bridge_v1_0_9=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_9 -axi_datamover_v5_1_21=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_21 -v_axi4s_vid_out_v4_0_10=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_10 -jesd204_v7_2_6=$RDI_DATADIR/xsim/ip/jesd204_v7_2_6 -v_letterbox_v1_0_13=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_13 -interlaken_v2_4_3=$RDI_DATADIR/xsim/ip/interlaken_v2_4_3 -uhdsdi_gt_v2_0_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_0 -axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7 -rst_vip_v1_0_3=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_3 -audio_formatter_v1_0_1=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_1 -lte_3gpp_channel_estimator_v2_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_16 -v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13 -g709_fec_v2_3_5=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_5 -xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6 -axi_chip2chip_v5_0_6=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_6 -fc32_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_11 -v_mix_v3_0_3=$RDI_DATADIR/xsim/ip/v_mix_v3_0_3 -multi_channel_25g_rs_fec_v1_0_5=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_5 -in_system_ibert_v1_0_9=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_9 -ethernet_1_10_25g_v2_1_4=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_1_4 -axis_broadcaster_v1_1_18=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_18 -axis_combiner_v1_1_17=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_17 -axi_apb_bridge_v3_0_15=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_15 -displayport_v9_0_1=$RDI_DATADIR/xsim/ip/displayport_v9_0_1 -clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2 -hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1 -axi_register_slice_v2_1_19=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_19 -vid_phy_controller_v2_1_5=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_5 -picxo=$RDI_DATADIR/xsim/ip/picxo -usxgmii_v1_1_0=$RDI_DATADIR/xsim/ip/usxgmii_v1_1_0 -v_vcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_13 -bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0 -prc_v1_3_2=$RDI_DATADIR/xsim/ip/prc_v1_3_2 -axi_usb2_device_v5_0_20=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_20 -lte_3gpp_mimo_encoder_v4_0_14=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_14 -l_ethernet_v2_5_2=$RDI_DATADIR/xsim/ip/l_ethernet_v2_5_2 -xdma_v4_1_3=$RDI_DATADIR/xsim/ip/xdma_v4_1_3 -axis_vio_v1_0_0=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_0 -c_counter_binary_v12_0_13=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_13 -noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0 -xbip_dsp48_macro_v3_0_17=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_17 -c_accum_v12_0_13=$RDI_DATADIR/xsim/ip/c_accum_v12_0_13 -xbip_multadd_v3_0_14=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_14 -axi_uartlite_v2_0_23=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_23 -noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0 -axi_intc_v4_1_13=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_13 -i2s_transmitter_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_3 -pc_cfr_v6_0_8=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_8 -mutex_v2_1_10=$RDI_DATADIR/xsim/ip/mutex_v2_1_10 -c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6 -sid_v8_0_14=$RDI_DATADIR/xsim/ip/sid_v8_0_14 -fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6 -quadsgmii_v3_4_6=$RDI_DATADIR/xsim/ip/quadsgmii_v3_4_6 -microblaze_v11_0_1=$RDI_DATADIR/xsim/ip/microblaze_v11_0_1 -lib_bmg_v1_0_12=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_12 -dds_compiler_v6_0_18=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_18 -me_pl_v1_0=$RDI_DATADIR/xsim/ip/me_pl_v1_0 -gtwizard_ultrascale_v1_7_6=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_6 -axis_clock_converter_v1_1_20=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_20 -nvmeha_v1_0_0=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_0 -tmr_inject_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_3 -axi_mcdma_v1_1_0=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_0 -axi_hwicap_v3_0_23=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_23 -v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0 -v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0 -canfd_v2_0_1=$RDI_DATADIR/xsim/ip/canfd_v2_0_1 -gig_ethernet_pcs_pma_v16_1_6=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_6 -lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2 -ieee802d3_rs_fec_v2_0_5=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_5 -ibert_lib_v1_0_6=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_6 -high_speed_selectio_wiz_v3_4_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_1 -xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6 -fec_5g_common_v1_0_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_1 -tmr_voter_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_2 -hdmi_gt_controller_v1_0_0=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_0 -axi_traffic_gen_v2_0_20=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_20 -flexo_100g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_11 -v_smpte_uhdsdi_v1_0_7=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_7 -xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6 -fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10 -ieee802d3_rs_fec_v1_0_15=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_15 -axis_subset_converter_v1_1_19=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_19 -noc_nmu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_v1_0_0 -duc_ddc_compiler_v3_0_15=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_15 -dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13 -mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0 -ieee802d3_200g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_7 -sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1 -mrmac_v1_0_0=$RDI_DATADIR/xsim/ip/mrmac_v1_0_0 -sem_ultra_v3_1_11=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_11 -v_tpg_v8_0_1=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_1 -axi_tft_v2_0_22=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_22 -ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13 -switch_core_top_v1_0_7=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_7 -rama_v1_1_2_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_2_lib -v_hcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_13 -emb_fifo_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_1 -hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3 -axis_data_fifo_v2_0_1=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_1 -hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0 -rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1 -displayport_v8_1_1=$RDI_DATADIR/xsim/ip/displayport_v8_1_1 -axi_mmu_v2_1_17=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_17 -proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13 -pc_cfr_v6_3_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_3_0 -v_osd_v6_0_16=$RDI_DATADIR/xsim/ip/v_osd_v6_0_16 -pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12 -xfft_v9_0_17=$RDI_DATADIR/xsim/ip/xfft_v9_0_17 -axi_cdma_v4_1_19=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_19 -audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0 -lib_fifo_v1_0_13=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_13 -v_enhance_v8_0_15=$RDI_DATADIR/xsim/ip/v_enhance_v8_0_15 -axi_clock_converter_v2_1_18=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_18 -xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0 -emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5 -axi_mm2s_mapper_v1_1_18=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_18 -xfft_v7_2_9=$RDI_DATADIR/xsim/ip/xfft_v7_2_9 -pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0 -v_smpte_sdi_v3_0_8=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_8 -fir_compiler_v7_2_12=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_12 -div_gen_v5_1_15=$RDI_DATADIR/xsim/ip/div_gen_v5_1_15 -mdm_v3_2_16=$RDI_DATADIR/xsim/ip/mdm_v3_2_16 -v_axi4s_remap_v1_0_11=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_11 -xxv_ethernet_v2_5_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_5_3 -xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2 -ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig -remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4 -pr_axi_shutdown_manager_v1_0_1=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_1 -axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0 -smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0 -axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib -axi_dwidth_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_19 -xlconstant_v1_1_6=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_6 -tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6 -mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2 -v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1 -axi_fifo_mm_s_v4_2_1=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_1 -util_idelay_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_1 -rs_toolbox_v9_0_7=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_7 -v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0 -dsp_macro_v1_0_0=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_0 -pc_cfr_v6_2_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_2 -axi_timer_v2_0_21=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_21 -high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1 -axi_sideband_util_v1_0_3=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_3 -sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2 -gmii_to_rgmii_v4_0_7=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_0_7 -xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2 -high_speed_selectio_wiz_v3_5_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_5_1 -axi_msg_v1_0_5=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_5 -axi_ahblite_bridge_v3_0_16=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_16 -v_rgb2ycrcb_v7_1_13=$RDI_DATADIR/xsim/ip/v_rgb2ycrcb_v7_1_13 -v_mix_v4_0_0=$RDI_DATADIR/xsim/ip/v_mix_v4_0_0 -axi_ethernetlite_v3_0_17=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_17 -axi_uart16550_v2_0_21=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_21 -axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0 -vfb_v1_0_13=$RDI_DATADIR/xsim/ip/vfb_v1_0_13 -advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0 -ats_switch_v1_0_2=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_2 -interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4 -axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub -cpri_v8_10_3=$RDI_DATADIR/xsim/ip/cpri_v8_10_3 -c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6 -v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0 -stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0 -rld3_pl_v1_0_1=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_1 -ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0 -lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0 -axi_epc_v2_0_22=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_22 -g709_rs_encoder_v2_2_6=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_6 -blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6 -tmr_sem_v1_0_9=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_9 -fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6 -axi_vdma_v6_3_7=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_7 -axis_data_fifo_v1_1_20=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_20 -xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip -axi_ethernet_buffer_v2_0_20=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_20 -rs_encoder_v9_0_15=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_15 -axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0 -ta_dma_v1_0_3=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_3 -tcc_encoder_3gpp_v5_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_15 -axi_perf_mon_v5_0_21=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_21 -noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0 -sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1 -lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2 -v_csc_v1_0_13=$RDI_DATADIR/xsim/ip/v_csc_v1_0_13 -shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0 -lte_fft_v2_0_18=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_18 -gtwizard_ultrascale_v1_6_11=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_11 -amm_axi_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_5 -mii_to_rmii_v2_0_21=$RDI_DATADIR/xsim/ip/mii_to_rmii_v2_0_21 -videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5 -audio_clock_recovery_v1_0=$RDI_DATADIR/xsim/ip/audio_clock_recovery_v1_0 -cmac_v2_4_1=$RDI_DATADIR/xsim/ip/cmac_v2_4_1 -i2s_receiver_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_3 -v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0 -v_demosaic_v1_0_5=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_5 -remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4 -microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4 -hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3 -etrnic_v1_0_3=$RDI_DATADIR/xsim/ip/etrnic_v1_0_3 -xfft_v9_1_2=$RDI_DATADIR/xsim/ip/xfft_v9_1_2 -ddr4_pl_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_2 -xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6 -cmac_usplus_v2_5_3=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_5_3 -jesd204c_v4_1_1=$RDI_DATADIR/xsim/ip/jesd204c_v4_1_1 -debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1 -axis_protocol_checker_v2_0_3=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_3 -v_frmbuf_wr_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_2 -v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9 -mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4 -lte_dl_channel_encoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_15 -axi_protocol_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_19 -xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0 -clk_gen_sim_v1_0_0=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_0 -axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0 -microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7 -cmpy_v6_0_17=$RDI_DATADIR/xsim/ip/cmpy_v6_0_17 -cmac_v2_3_5=$RDI_DATADIR/xsim/ip/cmac_v2_3_5 -ieee802d3_400g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_7 -xxv_ethernet_v2_4_5=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_4_5 -axi_timebase_wdt_v3_0_11=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_11 -tcc_decoder_3gppmm_v2_0_18=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_18 -v_deinterlacer_v5_0_13=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_13 -dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16 -axi_fifo_mm_s_v4_1_16=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_16 -processing_system7_vip_v1_0_7=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_7 -g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18 -rs_decoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_16 -c_shift_ram_v12_0_13=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_13 -displayport_v7_0_11=$RDI_DATADIR/xsim/ip/displayport_v7_0_11 -v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0 -v_deinterlacer_v4_0_12=$RDI_DATADIR/xsim/ip/v_deinterlacer_v4_0_12 -sem_v4_1_12=$RDI_DATADIR/xsim/ip/sem_v4_1_12 -xaui_v12_3_6=$RDI_DATADIR/xsim/ip/xaui_v12_3_6 -ten_gig_eth_mac_v15_1_7=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_7 -oddr_v1_0_0=$RDI_DATADIR/xsim/ip/oddr_v1_0_0 -c_addsub_v12_0_13=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_13 -v_ccm_v6_0_15=$RDI_DATADIR/xsim/ip/v_ccm_v6_0_15 -zynq_ultra_ps_e_vip_v1_0_5=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_5 -cic_compiler_v4_0_14=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_14 -c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6 -axi_memory_init_v1_0_0=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_0 -pr_decoupler_v1_0_7=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_7 -timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4 -lte_pucch_receiver_v2_0_16=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_16 -zynq_ultra_ps_e_v3_2_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_3 -v_gamma_lut_v1_0_5=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_5 -bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0 -pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0 -tcc_encoder_3gpplte_v4_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_15 -polar_v1_0_3=$RDI_DATADIR/xsim/ip/polar_v1_0_3 -rxaui_v4_4_6=$RDI_DATADIR/xsim/ip/rxaui_v4_4_6 -xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6 -v_gamma_v7_0_15=$RDI_DATADIR/xsim/ip/v_gamma_v7_0_15 -ernic_v1_0_1=$RDI_DATADIR/xsim/ip/ernic_v1_0_1 -high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3 -mailbox_v2_1_11=$RDI_DATADIR/xsim/ip/mailbox_v2_1_11 -video_frame_crc_v1_0_1=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_1 -axi_sg_v4_1_12=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_12 -ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0 -lmb_bram_if_cntlr_v4_0_16=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_16 -l_ethernet_v2_4_3=$RDI_DATADIR/xsim/ip/l_ethernet_v2_4_3 -dft_v4_1_1=$RDI_DATADIR/xsim/ip/dft_v4_1_1 -rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0 -axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6 -v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0 -stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0 -lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0 -uhdsdi_gt_v1_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_3 -pc_cfr_v6_1_4=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_4 -lmb_v10_v3_0_9=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_9 -axis_interconnect_v1_1_17=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_17 -cordic_v6_0_15=$RDI_DATADIR/xsim/ip/cordic_v6_0_15 -axis_register_slice_v1_1_19=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_19 -axis_switch_v1_1_19=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_19 -axi_interconnect_v1_7_16=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_16 -mult_gen_v12_0_15=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_15 -spdif_v2_0_21=$RDI_DATADIR/xsim/ip/spdif_v2_0_21 -v_hscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_13 -ethernet_1_10_25g_v2_3_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_3_3 -xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6 -axi_quad_spi_v3_2_18=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_18 -axi_bram_ctrl_v4_1_1=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_1 -axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4 -axi_protocol_checker_v2_0_5=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_5 -axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0 -mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7 -ieee802d3_25g_rs_fec_v1_0_13=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_13 -aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0 -xtlm=$RDI_DATADIR/xsim/ip/xtlm -iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0 -ieee802d3_clause74_fec_v1_0_4=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_4 -xlconcat_v2_1_3=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_3 -perf_axi_tg_v1_0_8=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_8 -axi_crossbar_v2_1_20=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_20 -tsn_endpoint_ethernet_mac_block_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_4 -v_ycrcb2rgb_v7_1_13=$RDI_DATADIR/xsim/ip/v_ycrcb2rgb_v7_1_13 -xhmc_v1_0_9=$RDI_DATADIR/xsim/ip/xhmc_v1_0_9 -dp_videoaxi4s_bridge_v1_0_0=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_0 -lte_ul_channel_decoder_v4_0_16=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_16 -soft_ecc_proxy_v1_0_0=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_0 -pr_bitstream_monitor_v1_0_1=$RDI_DATADIR/xsim/ip/pr_bitstream_monitor_v1_0_1 -sync_ip=$RDI_DATADIR/xsim/ip/sync_ip -v_frmbuf_rd_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_1_2 -c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6 -cmac_usplus_v2_6_2=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_6_2 -axi_mcdma_v1_0_5=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_5 -c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6 -g709_fec_v2_4_1=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_1 -lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0 -ai_pl=$RDI_DATADIR/xsim/ip/ai_pl -fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4 -v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0 -l_ethernet_v2_3_5=$RDI_DATADIR/xsim/ip/l_ethernet_v2_3_5 -microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6 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-axi_pcie3_v3_0_9=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_9 -axi_vfifo_ctrl_v2_0_21=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_21 -xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/README.txt deleted file mode 100644 index f3d66c82..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/README.txt +++ /dev/null @@ -1,83 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required -# to simulate the design for a simulator, the directory structure -# and the generated exported files. -# -################################################################################ - -1. Simulate Design - -To simulate design, cd to the simulator directory and execute the script. - -For example:- - -% cd questa -% ./top.sh - -The export simulation flow requires the Xilinx pre-compiled simulation library -components for the target simulator. These components are referred using the -'-lib_map_path' switch. If this switch is specified, then the export simulation -will automatically set this library path in the generated script and update, -copy the simulator setup file(s) in the exported directory. - -If '-lib_map_path' is not specified, then the pre-compiled simulation library -information will not be included in the exported scripts and that may cause -simulation errors when running this script. Alternatively, you can provide the -library information using this switch while executing the generated script. - -For example:- - -% ./top.sh -lib_map_path /design/questa/clibs - -Please refer to the generated script header 'Prerequisite' section for more details. - -2. Directory Structure - -By default, if the -directory switch is not specified, export_simulation will -create the following directory structure:- - -/export_sim/ - -For example, if the current working directory is /tmp/test, export_simulation -will create the following directory path:- - -/tmp/test/export_sim/questa - -If -directory switch is specified, export_simulation will create a simulator -sub-directory under the specified directory path. - -For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' -command will create the following directory:- - -/tmp/test/my_test_area/func_sim/questa - -By default, if -simulator is not specified, export_simulation will create a -simulator sub-directory for each simulator and export the files for each simulator -in this sub-directory respectively. - -IMPORTANT: Please note that the simulation library path must be specified manually -in the generated script for the respective simulator. Please refer to the generated -script header 'Prerequisite' section for more details. - -3. Exported script and files - -Export simulation will create the driver shell script, setup files and copy the -design sources in the output directory path. - -By default, when the -script_name switch is not specified, export_simulation will -create the following script name:- - -.sh (Unix) -When exporting the files for an IP using the -of_objects switch, export_simulation -will create the following script name:- - -.sh (Unix) -Export simulation will create the setup files for the target simulator specified -with the -simulator switch. - -For example, if the target simulator is "ies", export_simulation will create the -'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' -file. - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/GaussFir_12m.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/GaussFir_12m.coe deleted file mode 100644 index c70ab501..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/GaussFir_12m.coe +++ /dev/null @@ -1,20 +0,0 @@ -Radix=10; -Coefficient_Width=16; -CoefData= -3 -19 -97 -366 -1052 -2321 -3999 -5485 -6082 -5485 -3999 -2321 -1052 -366 -97 -19 -3 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/GaussFir_12m.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/GaussFir_12m.mif deleted file mode 100644 index 7033a867..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/GaussFir_12m.mif +++ /dev/null @@ -1,20 +0,0 @@ -00000003 0 0 0 0 0 0 -00000013 0 0 0 0 1 0 -00000061 0 0 0 0 2 0 -0000016e 0 0 0 0 3 0 -0000041c 0 1 0 0 4 0 -00000911 0 1 0 0 5 0 -00000f9f 0 1 0 0 6 0 -0000156d 0 1 0 0 7 0 -000017c2 0 2 0 0 8 0 -0000156d 0 2 0 0 9 0 -00000f9f 0 2 0 0 10 0 -00000911 0 2 0 0 11 0 -0000041c 0 3 0 0 12 0 -0000016e 0 3 0 0 13 0 -00000061 0 3 0 0 14 0 -00000013 0 3 0 0 15 0 -00000003 0 4 0 0 16 0 -00000000 0 4 0 0 17 0 -00000000 0 4 0 0 18 0 -00000000 0 4 0 0 19 0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/GaussFir_12m.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/GaussFir_12m.sh deleted file mode 100644 index 1bcb3827..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/GaussFir_12m.sh +++ /dev/null @@ -1,154 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : GaussFir_12m.sh -# Simulator : Aldec Active-HDL Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:36:27 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: GaussFir_12m.sh [-help] -# usage: GaussFir_12m.sh [-lib_map_path] -# usage: GaussFir_12m.sh [-noclean_files] -# usage: GaussFir_12m.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'GaussFir_12m.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "GaussFir_12m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - runvsimsa -l simulate.log -do "do {simulate.do}" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./GaussFir_12m.sh -help\" for more information)\n" - exit 1 - fi - map_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - map_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Map library.cfg file -map_setup_file() -{ - file="library.cfg" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then - lib_map_path="$1" - else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - vmap -link $lib_map_path - fi - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./GaussFir_12m.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: GaussFir_12m.sh [-help]\n\ -Usage: GaussFir_12m.sh [-lib_map_path]\n\ -Usage: GaussFir_12m.sh [-reset_run]\n\ -Usage: GaussFir_12m.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/GaussFir_12m.udo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/GaussFir_12m.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/README.txt deleted file mode 100644 index e937a880..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:36:27 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./GaussFir_12m.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './GaussFir_12m.sh' script. - -./GaussFir_12m.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./GaussFir_12m.sh -noclean_files - -For more information on the script, please type './GaussFir_12m.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/compile.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/compile.do deleted file mode 100644 index 8b9646aa..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/compile.do +++ /dev/null @@ -1,37 +0,0 @@ -vlib work -vlib activehdl - -vlib activehdl/xil_defaultlib -vlib activehdl/xpm -vlib activehdl/xbip_utils_v3_0_10 -vlib activehdl/axi_utils_v2_0_6 -vlib activehdl/fir_compiler_v7_2_12 - -vmap xil_defaultlib activehdl/xil_defaultlib -vmap xpm activehdl/xpm -vmap xbip_utils_v3_0_10 activehdl/xbip_utils_v3_0_10 -vmap axi_utils_v2_0_6 activehdl/axi_utils_v2_0_6 -vmap fir_compiler_v7_2_12 activehdl/fir_compiler_v7_2_12 - -vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/GaussFir_12m/cmodel" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -93 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vcom -work xbip_utils_v3_0_10 -93 \ -"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ - -vcom -work axi_utils_v2_0_6 -93 \ -"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ - -vcom -work fir_compiler_v7_2_12 -93 \ -"../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ - -vcom -work xil_defaultlib -93 \ -"../../../ip/GaussFir_12m/sim/GaussFir_12m.vhd" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/file_info.txt deleted file mode 100644 index febe2aeb..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/file_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/GaussFir_12m/cmodel" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/GaussFir_12m/cmodel" -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -GaussFir_12m.vhd,vhdl,xil_defaultlib,../../../ip/GaussFir_12m/sim/GaussFir_12m.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/simulate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/simulate.do deleted file mode 100644 index d7ffdd4f..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/simulate.do +++ /dev/null @@ -1,17 +0,0 @@ -onbreak {quit -force} -onerror {quit -force} - -asim -t 1ps +access +r +m+GaussFir_12m -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.GaussFir_12m xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure - -do {GaussFir_12m.udo} - -run -all - -endsim - -quit -force diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/wave.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/activehdl/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/GaussFir_12m.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/GaussFir_12m.coe deleted file mode 100644 index c70ab501..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/GaussFir_12m.coe +++ /dev/null @@ -1,20 +0,0 @@ -Radix=10; -Coefficient_Width=16; -CoefData= -3 -19 -97 -366 -1052 -2321 -3999 -5485 -6082 -5485 -3999 -2321 -1052 -366 -97 -19 -3 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/GaussFir_12m.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/GaussFir_12m.mif deleted file mode 100644 index 7033a867..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/GaussFir_12m.mif +++ /dev/null @@ -1,20 +0,0 @@ -00000003 0 0 0 0 0 0 -00000013 0 0 0 0 1 0 -00000061 0 0 0 0 2 0 -0000016e 0 0 0 0 3 0 -0000041c 0 1 0 0 4 0 -00000911 0 1 0 0 5 0 -00000f9f 0 1 0 0 6 0 -0000156d 0 1 0 0 7 0 -000017c2 0 2 0 0 8 0 -0000156d 0 2 0 0 9 0 -00000f9f 0 2 0 0 10 0 -00000911 0 2 0 0 11 0 -0000041c 0 3 0 0 12 0 -0000016e 0 3 0 0 13 0 -00000061 0 3 0 0 14 0 -00000013 0 3 0 0 15 0 -00000003 0 4 0 0 16 0 -00000000 0 4 0 0 17 0 -00000000 0 4 0 0 18 0 -00000000 0 4 0 0 19 0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/GaussFir_12m.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/GaussFir_12m.sh deleted file mode 100644 index d346192b..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/GaussFir_12m.sh +++ /dev/null @@ -1,176 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : GaussFir_12m.sh -# Simulator : Cadence Incisive Enterprise Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:36:27 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: GaussFir_12m.sh [-help] -# usage: GaussFir_12m.sh [-lib_map_path] -# usage: GaussFir_12m.sh [-noclean_files] -# usage: GaussFir_12m.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'GaussFir_12m.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Set the compiled library directory -ref_lib_dir="." - -# Command line options -irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" - -# Design libraries -design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 fir_compiler_v7_2_12) - -# Simulation root library directory -sim_lib_dir="ies_lib" - -# Script info -echo -e "GaussFir_12m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - execute -} - -# RUN_STEP: -execute() -{ - irun $irun_opts \ - -reflib "$ref_lib_dir/unisim:unisim" \ - -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ - -reflib "$ref_lib_dir/secureip:secureip" \ - -reflib "$ref_lib_dir/unimacro:unimacro" \ - -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.GaussFir_12m \ - -f run.f \ - -top glbl \ - glbl.v \ - +incdir+"../../../ip/GaussFir_12m/cmodel" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./GaussFir_12m.sh -help\" for more information)\n" - exit 1 - else - ref_lib_dir=$2 - fi - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./GaussFir_12m.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: GaussFir_12m.sh [-help]\n\ -Usage: GaussFir_12m.sh [-lib_map_path]\n\ -Usage: GaussFir_12m.sh [-reset_run]\n\ -Usage: GaussFir_12m.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/README.txt deleted file mode 100644 index b56b3160..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/README.txt +++ /dev/null @@ -1,48 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:36:27 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./GaussFir_12m.sh - -This command will launch the 'execute' function for the single-step flow. This -function is called from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './GaussFir_12m.sh' script. - -./GaussFir_12m.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./GaussFir_12m.sh -noclean_files - -For more information on the script, please type './GaussFir_12m.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/file_info.txt deleted file mode 100644 index febe2aeb..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/file_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/GaussFir_12m/cmodel" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/GaussFir_12m/cmodel" -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -GaussFir_12m.vhd,vhdl,xil_defaultlib,../../../ip/GaussFir_12m/sim/GaussFir_12m.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/run.f b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/run.f deleted file mode 100644 index 9e386d52..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/ies/run.f +++ /dev/null @@ -1,23 +0,0 @@ --makelib ies_lib/xil_defaultlib -sv \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ --endlib --makelib ies_lib/xpm \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ --endlib --makelib ies_lib/xbip_utils_v3_0_10 \ - "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ --endlib --makelib ies_lib/axi_utils_v2_0_6 \ - "../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ --endlib --makelib ies_lib/fir_compiler_v7_2_12 \ - "../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ --endlib --makelib ies_lib/xil_defaultlib \ - "../../../ip/GaussFir_12m/sim/GaussFir_12m.vhd" \ --endlib --makelib ies_lib/xil_defaultlib \ - glbl.v --endlib - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/GaussFir_12m.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/GaussFir_12m.coe deleted file mode 100644 index c70ab501..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/GaussFir_12m.coe +++ /dev/null @@ -1,20 +0,0 @@ -Radix=10; -Coefficient_Width=16; -CoefData= -3 -19 -97 -366 -1052 -2321 -3999 -5485 -6082 -5485 -3999 -2321 -1052 -366 -97 -19 -3 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/GaussFir_12m.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/GaussFir_12m.mif deleted file mode 100644 index 7033a867..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/GaussFir_12m.mif +++ /dev/null @@ -1,20 +0,0 @@ -00000003 0 0 0 0 0 0 -00000013 0 0 0 0 1 0 -00000061 0 0 0 0 2 0 -0000016e 0 0 0 0 3 0 -0000041c 0 1 0 0 4 0 -00000911 0 1 0 0 5 0 -00000f9f 0 1 0 0 6 0 -0000156d 0 1 0 0 7 0 -000017c2 0 2 0 0 8 0 -0000156d 0 2 0 0 9 0 -00000f9f 0 2 0 0 10 0 -00000911 0 2 0 0 11 0 -0000041c 0 3 0 0 12 0 -0000016e 0 3 0 0 13 0 -00000061 0 3 0 0 14 0 -00000013 0 3 0 0 15 0 -00000003 0 4 0 0 16 0 -00000000 0 4 0 0 17 0 -00000000 0 4 0 0 18 0 -00000000 0 4 0 0 19 0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/GaussFir_12m.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/GaussFir_12m.sh deleted file mode 100644 index c372025d..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/GaussFir_12m.sh +++ /dev/null @@ -1,167 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : GaussFir_12m.sh -# Simulator : Mentor Graphics ModelSim Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:36:27 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: GaussFir_12m.sh [-help] -# usage: GaussFir_12m.sh [-lib_map_path] -# usage: GaussFir_12m.sh [-noclean_files] -# usage: GaussFir_12m.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'GaussFir_12m.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "GaussFir_12m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - vsim -64 -c -do "do {simulate.do}" -l simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./GaussFir_12m.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Copy modelsim.ini file -copy_setup_file() -{ - file="modelsim.ini" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - else - lib_map_path="C:/Mentor/CompLib/2019.1.3" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - cp $src_file . - fi -} - -# Create design library directory -create_lib_dir() -{ - lib_dir="modelsim_lib" - if [[ -e $lib_dir ]]; then - rm -rf $lib_dir - fi - - mkdir $lib_dir - -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./GaussFir_12m.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: GaussFir_12m.sh [-help]\n\ -Usage: GaussFir_12m.sh [-lib_map_path]\n\ -Usage: GaussFir_12m.sh [-reset_run]\n\ -Usage: GaussFir_12m.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/GaussFir_12m.udo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/GaussFir_12m.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/README.txt deleted file mode 100644 index e937a880..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:36:27 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./GaussFir_12m.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './GaussFir_12m.sh' script. - -./GaussFir_12m.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./GaussFir_12m.sh -noclean_files - -For more information on the script, please type './GaussFir_12m.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/compile.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/compile.do deleted file mode 100644 index 9f06bd11..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/compile.do +++ /dev/null @@ -1,14 +0,0 @@ -vlib modelsim_lib/work -vlib modelsim_lib/msim - -vlib modelsim_lib/msim/xil_defaultlib - -vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib - -vcom -work xil_defaultlib -64 -93 \ -"../../../ip/GaussFir_12m/sim/GaussFir_12m.vhd" \ - - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/file_info.txt deleted file mode 100644 index 7d7a858c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/file_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -GaussFir_12m.vhd,vhdl,xil_defaultlib,../../../ip/GaussFir_12m/sim/GaussFir_12m.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/modelsim.ini b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/modelsim.ini deleted file mode 100644 index 04a43f2c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/modelsim.ini +++ /dev/null @@ -1,2590 +0,0 @@ -; vsim modelsim.ini file -[Version] -INIVersion = "2020.4" - -; Copyright 1991-2020 Mentor Graphics Corporation -; -; All Rights Reserved. -; -; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF -; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. -; - -[Library] -others = $MODEL_TECH/../modelsim.ini -; -; VITAL concerns: -; -; The library ieee contains (among other packages) the packages of the -; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use -; the physical library ieee (recommended), or use the physical library -; vital2000, but not both. The design can use logical library ieee and/or -; vital2000 as long as each of these maps to the same physical library, either -; ieee or vital2000. -; -; A design using the 1995 version of the VITAL packages, whether or not -; it also uses the 2000 version of the VITAL packages, must have logical library -; name ieee mapped to physical library vital1995. (A design cannot use library -; vital1995 directly because some packages in this library use logical name ieee -; when referring to the other packages in the library.) The design source -; should use logical name ieee when referring to any packages there except the -; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical -; name vital2000 (mapped to physical library vital2000) to refer to those -; packages. -; ieee = $MODEL_TECH/../vital1995 -; -; For compatiblity with previous releases, logical library name vital2000 maps -; to library vital2000 (a different library than library ieee, containing the -; same packages). -; A design should not reference VITAL from both the ieee library and the -; vital2000 library because the vital packages are effectively different. -; A design that references both the ieee and vital2000 libraries must have -; both logical names ieee and vital2000 mapped to the same library, either of -; these: -; $MODEL_TECH/../ieee -; $MODEL_TECH/../vital2000 -; - -; added mapping for ADMS - -;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release -;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release -;mvc_lib = $MODEL_TECH/../mvc_lib - -; Automatically perform logical->physical mapping for physical libraries that -; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). -; The tail of the filesystem path name is chosen as the logical library name. -; For example, in the command "vopt -L ./path/to/lib1 -o opttop top", -; vopt automatically performs the mapping "lib1 -> ./path/to/lib1". -; See the User Manual for more details. -; -; AutoLibMapping = 0 - -secureip = C:/Mentor/CompLib/2019.1.3/secureip -unisim = C:/Mentor/CompLib/2019.1.3/unisim -unimacro = C:/Mentor/CompLib/2019.1.3/unimacro -unifast = C:/Mentor/CompLib/2019.1.3/unifast -unisims_ver = C:/Mentor/CompLib/2019.1.3/unisims_ver -unimacro_ver = C:/Mentor/CompLib/2019.1.3/unimacro_ver -unifast_ver = C:/Mentor/CompLib/2019.1.3/unifast_ver -simprims_ver = C:/Mentor/CompLib/2019.1.3/simprims_ver -xpm = C:/Mentor/CompLib/2019.1.3/xpm -xilinx_vip = C:/Mentor/CompLib/2019.1.3/xilinx_vip -advanced_io_wizard_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/advanced_io_wizard_phy_v1_0_0 -advanced_io_wizard_v1_0_0 = C:/Mentor/CompLib/2019.1.3/advanced_io_wizard_v1_0_0 -ahblite_axi_bridge_v3_0_14 = C:/Mentor/CompLib/2019.1.3/ahblite_axi_bridge_v3_0_14 -ai_noc = C:/Mentor/CompLib/2019.1.3/ai_noc -ai_pl_trig = C:/Mentor/CompLib/2019.1.3/ai_pl_trig -ai_pl = C:/Mentor/CompLib/2019.1.3/ai_pl -audio_clock_recovery_v1_0 = C:/Mentor/CompLib/2019.1.3/audio_clock_recovery_v1_0 -audio_tpg_v1_0_0 = C:/Mentor/CompLib/2019.1.3/audio_tpg_v1_0_0 -av_pat_gen_v1_0_0 = C:/Mentor/CompLib/2019.1.3/av_pat_gen_v1_0_0 -axis_infrastructure_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axis_infrastructure_v1_1_0 -axis_protocol_checker_v2_0_3 = C:/Mentor/CompLib/2019.1.3/axis_protocol_checker_v2_0_3 -axi_ahblite_bridge_v3_0_16 = C:/Mentor/CompLib/2019.1.3/axi_ahblite_bridge_v3_0_16 -axi_amm_bridge_v1_0_9 = C:/Mentor/CompLib/2019.1.3/axi_amm_bridge_v1_0_9 -axi_bram_ctrl_v4_1_1 = C:/Mentor/CompLib/2019.1.3/axi_bram_ctrl_v4_1_1 -axi_chip2chip_v5_0_6 = C:/Mentor/CompLib/2019.1.3/axi_chip2chip_v5_0_6 -axi_dbg_hub = C:/Mentor/CompLib/2019.1.3/axi_dbg_hub -axi_infrastructure_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axi_infrastructure_v1_1_0 -axi_jtag_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_jtag_v1_0_0 -axi_lite_ipif_v3_0_4 = C:/Mentor/CompLib/2019.1.3/axi_lite_ipif_v3_0_4 -axi_pcie3_v3_0_9 = C:/Mentor/CompLib/2019.1.3/axi_pcie3_v3_0_9 -axi_perf_mon_v5_0_21 = C:/Mentor/CompLib/2019.1.3/axi_perf_mon_v5_0_21 -axi_pmon_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_pmon_v1_0_0 -blk_mem_gen_v8_3_6 = C:/Mentor/CompLib/2019.1.3/blk_mem_gen_v8_3_6 -blk_mem_gen_v8_4_3 = C:/Mentor/CompLib/2019.1.3/blk_mem_gen_v8_4_3 -bsip_v1_1_0 = C:/Mentor/CompLib/2019.1.3/bsip_v1_1_0 -bs_mux_v1_0_0 = C:/Mentor/CompLib/2019.1.3/bs_mux_v1_0_0 -clk_gen_sim_v1_0_0 = C:/Mentor/CompLib/2019.1.3/clk_gen_sim_v1_0_0 -clk_vip_v1_0_2 = C:/Mentor/CompLib/2019.1.3/clk_vip_v1_0_2 -cmac_usplus_v2_4_5 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_4_5 -cmac_usplus_v2_5_3 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_5_3 -cmac_usplus_v2_6_2 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_6_2 -cmac_v2_3_5 = C:/Mentor/CompLib/2019.1.3/cmac_v2_3_5 -cmac_v2_4_1 = C:/Mentor/CompLib/2019.1.3/cmac_v2_4_1 -cmac_v2_5_1 = C:/Mentor/CompLib/2019.1.3/cmac_v2_5_1 -compact_gt_v1_0_5 = C:/Mentor/CompLib/2019.1.3/compact_gt_v1_0_5 -ddr4_pl_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/ddr4_pl_phy_v1_0_0 -ddr4_pl_v1_0_2 = C:/Mentor/CompLib/2019.1.3/ddr4_pl_v1_0_2 -dist_mem_gen_v8_0_13 = C:/Mentor/CompLib/2019.1.3/dist_mem_gen_v8_0_13 -ecc_v2_0_13 = C:/Mentor/CompLib/2019.1.3/ecc_v2_0_13 -emb_fifo_gen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/emb_fifo_gen_v1_0_1 -emb_mem_gen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/emb_mem_gen_v1_0_1 -emc_common_v3_0_5 = C:/Mentor/CompLib/2019.1.3/emc_common_v3_0_5 -ethernet_1_10_25g_v2_0_5 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_0_5 -ethernet_1_10_25g_v2_1_4 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_1_4 -ethernet_1_10_25g_v2_2_3 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_2_3 -ethernet_1_10_25g_v2_3_3 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_3_3 -fifo_generator_v13_0_6 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_0_6 -fifo_generator_v13_1_4 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_1_4 -fifo_generator_v13_2_4 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_2_4 -fit_timer_v2_0_10 = C:/Mentor/CompLib/2019.1.3/fit_timer_v2_0_10 -generic_baseblocks_v2_1_0 = C:/Mentor/CompLib/2019.1.3/generic_baseblocks_v2_1_0 -gigantic_mux = C:/Mentor/CompLib/2019.1.3/gigantic_mux -gig_ethernet_pcs_pma_v16_1_6 = C:/Mentor/CompLib/2019.1.3/gig_ethernet_pcs_pma_v16_1_6 -gmii_to_rgmii_v4_0_7 = C:/Mentor/CompLib/2019.1.3/gmii_to_rgmii_v4_0_7 -gtwizard_ultrascale_v1_5_4 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_5_4 -gtwizard_ultrascale_v1_6_11 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_6_11 -gtwizard_ultrascale_v1_7_6 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_7_6 -hbm_v1_0_4 = C:/Mentor/CompLib/2019.1.3/hbm_v1_0_4 -hdcp22_cipher_dp_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdcp22_cipher_dp_v1_0_0 -hdcp22_cipher_v1_0_3 = C:/Mentor/CompLib/2019.1.3/hdcp22_cipher_v1_0_3 -hdcp22_rng_v1_0_1 = C:/Mentor/CompLib/2019.1.3/hdcp22_rng_v1_0_1 -hdcp_keymngmt_blk_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdcp_keymngmt_blk_v1_0_0 -hdcp_v1_0_3 = C:/Mentor/CompLib/2019.1.3/hdcp_v1_0_3 -hdmi_gt_controller_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdmi_gt_controller_v1_0_0 -high_speed_selectio_wiz_v3_2_3 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_2_3 -high_speed_selectio_wiz_v3_3_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_3_1 -high_speed_selectio_wiz_v3_4_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_4_1 -high_speed_selectio_wiz_v3_5_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_5_1 -i2s_receiver_v1_0_3 = C:/Mentor/CompLib/2019.1.3/i2s_receiver_v1_0_3 -i2s_transmitter_v1_0_3 = C:/Mentor/CompLib/2019.1.3/i2s_transmitter_v1_0_3 -ibert_lib_v1_0_6 = C:/Mentor/CompLib/2019.1.3/ibert_lib_v1_0_6 -ieee802d3_clause74_fec_v1_0_4 = C:/Mentor/CompLib/2019.1.3/ieee802d3_clause74_fec_v1_0_4 -interlaken_v2_4_3 = C:/Mentor/CompLib/2019.1.3/interlaken_v2_4_3 -in_system_ibert_v1_0_9 = C:/Mentor/CompLib/2019.1.3/in_system_ibert_v1_0_9 -iomodule_v3_1_4 = C:/Mentor/CompLib/2019.1.3/iomodule_v3_1_4 -jesd204c_v4_1_1 = C:/Mentor/CompLib/2019.1.3/jesd204c_v4_1_1 -jesd204_v7_2_6 = C:/Mentor/CompLib/2019.1.3/jesd204_v7_2_6 -jtag_axi = C:/Mentor/CompLib/2019.1.3/jtag_axi -lib_cdc_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_cdc_v1_0_2 -lib_pkg_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_pkg_v1_0_2 -lmb_bram_if_cntlr_v4_0_16 = C:/Mentor/CompLib/2019.1.3/lmb_bram_if_cntlr_v4_0_16 -lmb_v10_v3_0_9 = C:/Mentor/CompLib/2019.1.3/lmb_v10_v3_0_9 -ltlib_v1_0_0 = C:/Mentor/CompLib/2019.1.3/ltlib_v1_0_0 -lut_buffer_v1_0_0 = C:/Mentor/CompLib/2019.1.3/lut_buffer_v1_0_0 -lut_buffer_v2_0_0 = C:/Mentor/CompLib/2019.1.3/lut_buffer_v2_0_0 -l_ethernet_v2_3_5 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_3_5 -l_ethernet_v2_4_3 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_4_3 -l_ethernet_v2_5_2 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_5_2 -mammoth_transcode_v1_0_0 = C:/Mentor/CompLib/2019.1.3/mammoth_transcode_v1_0_0 -microblaze_v10_0_7 = C:/Mentor/CompLib/2019.1.3/microblaze_v10_0_7 -microblaze_v11_0_1 = C:/Mentor/CompLib/2019.1.3/microblaze_v11_0_1 -microblaze_v9_5_4 = C:/Mentor/CompLib/2019.1.3/microblaze_v9_5_4 -mii_to_rmii_v2_0_21 = C:/Mentor/CompLib/2019.1.3/mii_to_rmii_v2_0_21 -mipi_csi2_rx_ctrl_v1_0_8 = C:/Mentor/CompLib/2019.1.3/mipi_csi2_rx_ctrl_v1_0_8 -mipi_csi2_tx_ctrl_v1_0_4 = C:/Mentor/CompLib/2019.1.3/mipi_csi2_tx_ctrl_v1_0_4 -mipi_dphy_v4_1_4 = C:/Mentor/CompLib/2019.1.3/mipi_dphy_v4_1_4 -mipi_dsi_tx_ctrl_v1_0_7 = C:/Mentor/CompLib/2019.1.3/mipi_dsi_tx_ctrl_v1_0_7 -mrmac_v1_0_0 = C:/Mentor/CompLib/2019.1.3/mrmac_v1_0_0 -multi_channel_25g_rs_fec_v1_0_5 = C:/Mentor/CompLib/2019.1.3/multi_channel_25g_rs_fec_v1_0_5 -mutex_v2_1_10 = C:/Mentor/CompLib/2019.1.3/mutex_v2_1_10 -axi_tg_lib = C:/Mentor/CompLib/2019.1.3/axi_tg_lib -noc_na_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_na_v1_0_0 -noc_nidb_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nidb_v1_0_0 -noc_nmu_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nmu_v1_0_0 -noc_nps_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nps_v1_0_0 -nvmeha_v1_0_0 = C:/Mentor/CompLib/2019.1.3/nvmeha_v1_0_0 -oddr_v1_0_0 = C:/Mentor/CompLib/2019.1.3/oddr_v1_0_0 -pci32_v5_0_12 = C:/Mentor/CompLib/2019.1.3/pci32_v5_0_12 -pci64_v5_0_11 = C:/Mentor/CompLib/2019.1.3/pci64_v5_0_11 -pcie_jtag_v1_0_0 = C:/Mentor/CompLib/2019.1.3/pcie_jtag_v1_0_0 -pc_cfr_v6_0_8 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_0_8 -pc_cfr_v6_1_4 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_1_4 -pc_cfr_v6_2_2 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_2_2 -pc_cfr_v6_3_0 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_3_0 -picxo = C:/Mentor/CompLib/2019.1.3/picxo -qdma_v3_0_2 = C:/Mentor/CompLib/2019.1.3/qdma_v3_0_2 -rama_v1_1_2_lib = C:/Mentor/CompLib/2019.1.3/rama_v1_1_2_lib -rld3_pl_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/rld3_pl_phy_v1_0_0 -rld3_pl_v1_0_1 = C:/Mentor/CompLib/2019.1.3/rld3_pl_v1_0_1 -roe_framer_v2_0_1 = C:/Mentor/CompLib/2019.1.3/roe_framer_v2_0_1 -rst_vip_v1_0_3 = C:/Mentor/CompLib/2019.1.3/rst_vip_v1_0_3 -smartconnect_v1_0 = C:/Mentor/CompLib/2019.1.3/smartconnect_v1_0 -sd_fec_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sd_fec_v1_0_2 -sem_ultra_v3_1_11 = C:/Mentor/CompLib/2019.1.3/sem_ultra_v3_1_11 -sem_v4_1_12 = C:/Mentor/CompLib/2019.1.3/sem_v4_1_12 -shell_utils_msp432_bsl_crc_gen_v1_0_0 = C:/Mentor/CompLib/2019.1.3/shell_utils_msp432_bsl_crc_gen_v1_0_0 -sim_clk_gen_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sim_clk_gen_v1_0_2 -sim_rst_gen_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sim_rst_gen_v1_0_2 -sim_trig_top_v1_0 = C:/Mentor/CompLib/2019.1.3/sim_trig_top_v1_0 -stm_v1_0 = C:/Mentor/CompLib/2019.1.3/stm_v1_0 -stm_v1_0_0 = C:/Mentor/CompLib/2019.1.3/stm_v1_0_0 -system_cache_v4_0_6 = C:/Mentor/CompLib/2019.1.3/system_cache_v4_0_6 -ta_dma_v1_0_3 = C:/Mentor/CompLib/2019.1.3/ta_dma_v1_0_3 -tcc_decoder_3gpplte_v3_0_6 = C:/Mentor/CompLib/2019.1.3/tcc_decoder_3gpplte_v3_0_6 -ten_gig_eth_mac_v15_1_7 = C:/Mentor/CompLib/2019.1.3/ten_gig_eth_mac_v15_1_7 -ten_gig_eth_pcs_pma_v6_0_15 = C:/Mentor/CompLib/2019.1.3/ten_gig_eth_pcs_pma_v6_0_15 -timer_sync_1588_v1_2_4 = C:/Mentor/CompLib/2019.1.3/timer_sync_1588_v1_2_4 -tmr_inject_v1_0_3 = C:/Mentor/CompLib/2019.1.3/tmr_inject_v1_0_3 -tmr_manager_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tmr_manager_v1_0_4 -tmr_voter_v1_0_2 = C:/Mentor/CompLib/2019.1.3/tmr_voter_v1_0_2 -tsn_endpoint_ethernet_mac_block_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tsn_endpoint_ethernet_mac_block_v1_0_4 -uhdsdi_gt_v1_0_3 = C:/Mentor/CompLib/2019.1.3/uhdsdi_gt_v1_0_3 -uhdsdi_gt_v2_0_0 = C:/Mentor/CompLib/2019.1.3/uhdsdi_gt_v2_0_0 -usxgmii_v1_0_5 = C:/Mentor/CompLib/2019.1.3/usxgmii_v1_0_5 -usxgmii_v1_1_0 = C:/Mentor/CompLib/2019.1.3/usxgmii_v1_1_0 -util_idelay_ctrl_v1_0_1 = C:/Mentor/CompLib/2019.1.3/util_idelay_ctrl_v1_0_1 -util_reduced_logic_v2_0_4 = C:/Mentor/CompLib/2019.1.3/util_reduced_logic_v2_0_4 -util_vector_logic_v2_0_1 = C:/Mentor/CompLib/2019.1.3/util_vector_logic_v2_0_1 -ba317 = C:/Mentor/CompLib/2019.1.3/ba317 -vfb_v1_0_13 = C:/Mentor/CompLib/2019.1.3/vfb_v1_0_13 -video_frame_crc_v1_0_1 = C:/Mentor/CompLib/2019.1.3/video_frame_crc_v1_0_1 -vid_edid_v1_0_0 = C:/Mentor/CompLib/2019.1.3/vid_edid_v1_0_0 -vid_phy_controller_v2_1_5 = C:/Mentor/CompLib/2019.1.3/vid_phy_controller_v2_1_5 -vid_phy_controller_v2_2_3 = C:/Mentor/CompLib/2019.1.3/vid_phy_controller_v2_2_3 -v_axi4s_remap_v1_0_11 = C:/Mentor/CompLib/2019.1.3/v_axi4s_remap_v1_0_11 -v_csc_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_csc_v1_0_13 -v_deinterlacer_v4_0_12 = C:/Mentor/CompLib/2019.1.3/v_deinterlacer_v4_0_12 -v_deinterlacer_v5_0_13 = C:/Mentor/CompLib/2019.1.3/v_deinterlacer_v5_0_13 -v_demosaic_v1_0_5 = C:/Mentor/CompLib/2019.1.3/v_demosaic_v1_0_5 -v_frmbuf_rd_v2_1_2 = C:/Mentor/CompLib/2019.1.3/v_frmbuf_rd_v2_1_2 -v_frmbuf_wr_v2_1_2 = C:/Mentor/CompLib/2019.1.3/v_frmbuf_wr_v2_1_2 -v_gamma_lut_v1_0_5 = C:/Mentor/CompLib/2019.1.3/v_gamma_lut_v1_0_5 -v_hcresampler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_hcresampler_v1_0_13 -v_hdmi_rx_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_rx_v2_0_0 -v_hdmi_rx_v3_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_rx_v3_0_0 -v_hdmi_tx_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_tx_v2_0_0 -v_hdmi_tx_v3_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_tx_v3_0_0 -v_hscaler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_hscaler_v1_0_13 -v_letterbox_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_letterbox_v1_0_13 -v_mix_v3_0_3 = C:/Mentor/CompLib/2019.1.3/v_mix_v3_0_3 -v_mix_v4_0_0 = C:/Mentor/CompLib/2019.1.3/v_mix_v4_0_0 -v_multi_scaler_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_multi_scaler_v1_0_1 -v_scenechange_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_scenechange_v1_0_1 -v_sdi_rx_vid_bridge_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_sdi_rx_vid_bridge_v2_0_0 -v_smpte_sdi_v3_0_8 = C:/Mentor/CompLib/2019.1.3/v_smpte_sdi_v3_0_8 -v_smpte_uhdsdi_rx_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_rx_v1_0_0 -v_smpte_uhdsdi_tx_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_tx_v1_0_0 -v_smpte_uhdsdi_v1_0_7 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_v1_0_7 -v_tpg_v7_0_13 = C:/Mentor/CompLib/2019.1.3/v_tpg_v7_0_13 -v_tpg_v8_0_1 = C:/Mentor/CompLib/2019.1.3/v_tpg_v8_0_1 -v_uhdsdi_audio_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v1_0_0 -v_uhdsdi_audio_v1_1_0 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v1_1_0 -v_uhdsdi_audio_v2_0_1 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v2_0_1 -v_uhdsdi_vidgen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_vidgen_v1_0_1 -v_vcresampler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_vcresampler_v1_0_13 -v_vid_in_axi4s_v4_0_9 = C:/Mentor/CompLib/2019.1.3/v_vid_in_axi4s_v4_0_9 -v_vscaler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_vscaler_v1_0_13 -xaui_v12_3_6 = C:/Mentor/CompLib/2019.1.3/xaui_v12_3_6 -xbip_dsp48_wrapper_v3_0_4 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_wrapper_v3_0_4 -xbip_utils_v3_0_10 = C:/Mentor/CompLib/2019.1.3/xbip_utils_v3_0_10 -xdma_v4_1_3 = C:/Mentor/CompLib/2019.1.3/xdma_v4_1_3 -xhmc_v1_0_9 = C:/Mentor/CompLib/2019.1.3/xhmc_v1_0_9 -xlconcat_v2_1_3 = C:/Mentor/CompLib/2019.1.3/xlconcat_v2_1_3 -xlconstant_v1_1_6 = C:/Mentor/CompLib/2019.1.3/xlconstant_v1_1_6 -xlslice_v1_0_2 = C:/Mentor/CompLib/2019.1.3/xlslice_v1_0_2 -xsdbm_v2_0_0 = C:/Mentor/CompLib/2019.1.3/xsdbm_v2_0_0 -xsdbm_v3_0_0 = C:/Mentor/CompLib/2019.1.3/xsdbm_v3_0_0 -xxv_ethernet_v2_4_5 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v2_4_5 -xxv_ethernet_v2_5_3 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v2_5_3 -xxv_ethernet_v3_0_3 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v3_0_3 -zynq_ultra_ps_e_v3_2_3 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_v3_2_3 -zynq_ultra_ps_e_v3_3_0 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_v3_3_0 -lib_srl_fifo_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_srl_fifo_v1_0_2 -lib_fifo_v1_0_13 = C:/Mentor/CompLib/2019.1.3/lib_fifo_v1_0_13 -axi_datamover_v5_1_21 = C:/Mentor/CompLib/2019.1.3/axi_datamover_v5_1_21 -amm_axi_bridge_v1_0_5 = C:/Mentor/CompLib/2019.1.3/amm_axi_bridge_v1_0_5 -axis_interconnect_v1_1_17 = C:/Mentor/CompLib/2019.1.3/axis_interconnect_v1_1_17 -ats_switch_v1_0_2 = C:/Mentor/CompLib/2019.1.3/ats_switch_v1_0_2 -audio_formatter_v1_0_1 = C:/Mentor/CompLib/2019.1.3/audio_formatter_v1_0_1 -axi4stream_vip_v1_1_5 = C:/Mentor/CompLib/2019.1.3/axi4stream_vip_v1_1_5 -v_tc_v6_1_13 = C:/Mentor/CompLib/2019.1.3/v_tc_v6_1_13 -v_axi4s_vid_out_v4_0_10 = C:/Mentor/CompLib/2019.1.3/v_axi4s_vid_out_v4_0_10 -axi4svideo_bridge_v1_0_10 = C:/Mentor/CompLib/2019.1.3/axi4svideo_bridge_v1_0_10 -axis_accelerator_adapter_v2_1_15 = C:/Mentor/CompLib/2019.1.3/axis_accelerator_adapter_v2_1_15 -axis_broadcaster_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axis_broadcaster_v1_1_18 -axis_clock_converter_v1_1_20 = C:/Mentor/CompLib/2019.1.3/axis_clock_converter_v1_1_20 -axis_combiner_v1_1_17 = C:/Mentor/CompLib/2019.1.3/axis_combiner_v1_1_17 -axis_data_fifo_v1_1_20 = C:/Mentor/CompLib/2019.1.3/axis_data_fifo_v1_1_20 -axis_data_fifo_v2_0_1 = C:/Mentor/CompLib/2019.1.3/axis_data_fifo_v2_0_1 -axis_register_slice_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_register_slice_v1_1_19 -axis_dwidth_converter_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axis_dwidth_converter_v1_1_18 -axis_subset_converter_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_subset_converter_v1_1_19 -axis_switch_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_switch_v1_1_19 -axis_vio_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axis_vio_v1_0_0 -axi_apb_bridge_v3_0_15 = C:/Mentor/CompLib/2019.1.3/axi_apb_bridge_v3_0_15 -axi_bram_ctrl_v4_0_14 = C:/Mentor/CompLib/2019.1.3/axi_bram_ctrl_v4_0_14 -axi_sg_v4_1_12 = C:/Mentor/CompLib/2019.1.3/axi_sg_v4_1_12 -axi_cdma_v4_1_19 = C:/Mentor/CompLib/2019.1.3/axi_cdma_v4_1_19 -axi_clock_converter_v2_1_18 = C:/Mentor/CompLib/2019.1.3/axi_clock_converter_v2_1_18 -axi_data_fifo_v2_1_18 = C:/Mentor/CompLib/2019.1.3/axi_data_fifo_v2_1_18 -axi_register_slice_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_register_slice_v2_1_19 -axi_crossbar_v2_1_20 = C:/Mentor/CompLib/2019.1.3/axi_crossbar_v2_1_20 -axi_dma_v7_1_20 = C:/Mentor/CompLib/2019.1.3/axi_dma_v7_1_20 -axi_protocol_converter_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_protocol_converter_v2_1_19 -axi_dwidth_converter_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_dwidth_converter_v2_1_19 -axi_emc_v3_0_19 = C:/Mentor/CompLib/2019.1.3/axi_emc_v3_0_19 -axi_epc_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_epc_v2_0_22 -lib_bmg_v1_0_12 = C:/Mentor/CompLib/2019.1.3/lib_bmg_v1_0_12 -axi_ethernetlite_v3_0_17 = C:/Mentor/CompLib/2019.1.3/axi_ethernetlite_v3_0_17 -axi_ethernet_buffer_v2_0_20 = C:/Mentor/CompLib/2019.1.3/axi_ethernet_buffer_v2_0_20 -axi_fifo_mm_s_v4_1_16 = C:/Mentor/CompLib/2019.1.3/axi_fifo_mm_s_v4_1_16 -axi_fifo_mm_s_v4_2_1 = C:/Mentor/CompLib/2019.1.3/axi_fifo_mm_s_v4_2_1 -axi_firewall_v1_0_7 = C:/Mentor/CompLib/2019.1.3/axi_firewall_v1_0_7 -interrupt_control_v3_1_4 = C:/Mentor/CompLib/2019.1.3/interrupt_control_v3_1_4 -axi_gpio_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_gpio_v2_0_21 -axi_hwicap_v3_0_23 = C:/Mentor/CompLib/2019.1.3/axi_hwicap_v3_0_23 -axi_iic_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_iic_v2_0_22 -axi_intc_v4_1_13 = C:/Mentor/CompLib/2019.1.3/axi_intc_v4_1_13 -axi_interconnect_v1_7_16 = C:/Mentor/CompLib/2019.1.3/axi_interconnect_v1_7_16 -axi_master_burst_v2_0_7 = C:/Mentor/CompLib/2019.1.3/axi_master_burst_v2_0_7 -axi_msg_v1_0_5 = C:/Mentor/CompLib/2019.1.3/axi_msg_v1_0_5 -axi_mcdma_v1_0_5 = C:/Mentor/CompLib/2019.1.3/axi_mcdma_v1_0_5 -axi_mcdma_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axi_mcdma_v1_1_0 -axi_memory_init_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_memory_init_v1_0_0 -axi_mm2s_mapper_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axi_mm2s_mapper_v1_1_18 -axi_mmu_v2_1_17 = C:/Mentor/CompLib/2019.1.3/axi_mmu_v2_1_17 -axi_pcie_v2_9_1 = C:/Mentor/CompLib/2019.1.3/axi_pcie_v2_9_1 -axi_protocol_checker_v2_0_5 = C:/Mentor/CompLib/2019.1.3/axi_protocol_checker_v2_0_5 -axi_quad_spi_v3_2_18 = C:/Mentor/CompLib/2019.1.3/axi_quad_spi_v3_2_18 -axi_sideband_util_v1_0_3 = C:/Mentor/CompLib/2019.1.3/axi_sideband_util_v1_0_3 -axi_tft_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_tft_v2_0_22 -axi_timebase_wdt_v3_0_11 = C:/Mentor/CompLib/2019.1.3/axi_timebase_wdt_v3_0_11 -axi_timer_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_timer_v2_0_21 -axi_traffic_gen_v2_0_20 = C:/Mentor/CompLib/2019.1.3/axi_traffic_gen_v2_0_20 -axi_traffic_gen_v3_0_5 = C:/Mentor/CompLib/2019.1.3/axi_traffic_gen_v3_0_5 -axi_uart16550_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_uart16550_v2_0_21 -axi_uartlite_v2_0_23 = C:/Mentor/CompLib/2019.1.3/axi_uartlite_v2_0_23 -axi_usb2_device_v5_0_20 = C:/Mentor/CompLib/2019.1.3/axi_usb2_device_v5_0_20 -axi_utils_v2_0_6 = C:/Mentor/CompLib/2019.1.3/axi_utils_v2_0_6 -axi_vdma_v6_3_7 = C:/Mentor/CompLib/2019.1.3/axi_vdma_v6_3_7 -xbip_pipe_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_pipe_v3_0_6 -xbip_dsp48_addsub_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_addsub_v3_0_6 -xbip_addsub_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_addsub_v3_0_6 -c_reg_fd_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_reg_fd_v12_0_6 -c_addsub_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_addsub_v12_0_13 -axi_vfifo_ctrl_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_vfifo_ctrl_v2_0_21 -axi_vip_v1_1_5 = C:/Mentor/CompLib/2019.1.3/axi_vip_v1_1_5 -bs_switch_v1_0_0 = C:/Mentor/CompLib/2019.1.3/bs_switch_v1_0_0 -canfd_v2_0_1 = C:/Mentor/CompLib/2019.1.3/canfd_v2_0_1 -can_v5_0_22 = C:/Mentor/CompLib/2019.1.3/can_v5_0_22 -cic_compiler_v4_0_14 = C:/Mentor/CompLib/2019.1.3/cic_compiler_v4_0_14 -xbip_bram18k_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_bram18k_v3_0_6 -mult_gen_v12_0_15 = C:/Mentor/CompLib/2019.1.3/mult_gen_v12_0_15 -cmpy_v6_0_17 = C:/Mentor/CompLib/2019.1.3/cmpy_v6_0_17 -c_mux_bit_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_mux_bit_v12_0_6 -c_shift_ram_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_shift_ram_v12_0_13 -c_mux_bus_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_mux_bus_v12_0_6 -c_gate_bit_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_gate_bit_v12_0_6 -xbip_counter_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_counter_v3_0_6 -c_counter_binary_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_counter_binary_v12_0_13 -c_compare_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_compare_v12_0_6 -convolution_v9_0_14 = C:/Mentor/CompLib/2019.1.3/convolution_v9_0_14 -cordic_v6_0_15 = C:/Mentor/CompLib/2019.1.3/cordic_v6_0_15 -cpri_v8_10_3 = C:/Mentor/CompLib/2019.1.3/cpri_v8_10_3 -xbip_dsp48_acc_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_acc_v3_0_6 -xbip_accum_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_accum_v3_0_6 -c_accum_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_accum_v12_0_13 -xbip_dsp48_multadd_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_multadd_v3_0_6 -dds_compiler_v6_0_18 = C:/Mentor/CompLib/2019.1.3/dds_compiler_v6_0_18 -dft_v4_0_16 = C:/Mentor/CompLib/2019.1.3/dft_v4_0_16 -dft_v4_1_1 = C:/Mentor/CompLib/2019.1.3/dft_v4_1_1 -displayport_v7_0_11 = C:/Mentor/CompLib/2019.1.3/displayport_v7_0_11 -displayport_v8_1_1 = C:/Mentor/CompLib/2019.1.3/displayport_v8_1_1 -displayport_v9_0_1 = C:/Mentor/CompLib/2019.1.3/displayport_v9_0_1 -xbip_dsp48_mult_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_mult_v3_0_6 -floating_point_v7_0_16 = C:/Mentor/CompLib/2019.1.3/floating_point_v7_0_16 -div_gen_v5_1_15 = C:/Mentor/CompLib/2019.1.3/div_gen_v5_1_15 -dp_videoaxi4s_bridge_v1_0_0 = C:/Mentor/CompLib/2019.1.3/dp_videoaxi4s_bridge_v1_0_0 -dsp_macro_v1_0_0 = C:/Mentor/CompLib/2019.1.3/dsp_macro_v1_0_0 -fir_compiler_v5_2_6 = C:/Mentor/CompLib/2019.1.3/fir_compiler_v5_2_6 -duc_ddc_compiler_v3_0_15 = C:/Mentor/CompLib/2019.1.3/duc_ddc_compiler_v3_0_15 -ernic_v1_0_1 = C:/Mentor/CompLib/2019.1.3/ernic_v1_0_1 -etrnic_v1_0_3 = C:/Mentor/CompLib/2019.1.3/etrnic_v1_0_3 -etrnic_v1_1_2 = C:/Mentor/CompLib/2019.1.3/etrnic_v1_1_2 -fc32_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/fc32_rs_fec_v1_0_11 -fec_5g_common_v1_0_1 = C:/Mentor/CompLib/2019.1.3/fec_5g_common_v1_0_1 -fec_5g_common_v1_1_1 = C:/Mentor/CompLib/2019.1.3/fec_5g_common_v1_1_1 -fir_compiler_v7_2_12 = C:/Mentor/CompLib/2019.1.3/fir_compiler_v7_2_12 -flexo_100g_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/flexo_100g_rs_fec_v1_0_11 -floating_point_v7_1_8 = C:/Mentor/CompLib/2019.1.3/floating_point_v7_1_8 -g709_rs_encoder_v2_2_6 = C:/Mentor/CompLib/2019.1.3/g709_rs_encoder_v2_2_6 -rs_toolbox_v9_0_7 = C:/Mentor/CompLib/2019.1.3/rs_toolbox_v9_0_7 -g709_rs_decoder_v2_2_8 = C:/Mentor/CompLib/2019.1.3/g709_rs_decoder_v2_2_8 -g709_fec_v2_3_5 = C:/Mentor/CompLib/2019.1.3/g709_fec_v2_3_5 -g709_fec_v2_4_1 = C:/Mentor/CompLib/2019.1.3/g709_fec_v2_4_1 -g975_efec_i4_v1_0_17 = C:/Mentor/CompLib/2019.1.3/g975_efec_i4_v1_0_17 -g975_efec_i7_v2_0_18 = C:/Mentor/CompLib/2019.1.3/g975_efec_i7_v2_0_18 -ieee802d3_200g_rs_fec_v1_0_7 = C:/Mentor/CompLib/2019.1.3/ieee802d3_200g_rs_fec_v1_0_7 -ieee802d3_25g_rs_fec_v1_0_13 = C:/Mentor/CompLib/2019.1.3/ieee802d3_25g_rs_fec_v1_0_13 -ieee802d3_400g_rs_fec_v1_0_7 = C:/Mentor/CompLib/2019.1.3/ieee802d3_400g_rs_fec_v1_0_7 -ieee802d3_50g_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/ieee802d3_50g_rs_fec_v1_0_11 -ieee802d3_50g_rs_fec_v2_0_1 = C:/Mentor/CompLib/2019.1.3/ieee802d3_50g_rs_fec_v2_0_1 -ieee802d3_rs_fec_v1_0_15 = C:/Mentor/CompLib/2019.1.3/ieee802d3_rs_fec_v1_0_15 -ieee802d3_rs_fec_v2_0_5 = C:/Mentor/CompLib/2019.1.3/ieee802d3_rs_fec_v2_0_5 -ldpc_v2_0_3 = C:/Mentor/CompLib/2019.1.3/ldpc_v2_0_3 -lte_3gpp_channel_estimator_v2_0_16 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_channel_estimator_v2_0_16 -lte_3gpp_mimo_decoder_v3_0_15 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_mimo_decoder_v3_0_15 -lte_3gpp_mimo_encoder_v4_0_14 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_mimo_encoder_v4_0_14 -tcc_encoder_3gpplte_v4_0_15 = C:/Mentor/CompLib/2019.1.3/tcc_encoder_3gpplte_v4_0_15 -lte_dl_channel_encoder_v3_0_15 = C:/Mentor/CompLib/2019.1.3/lte_dl_channel_encoder_v3_0_15 -lte_dl_channel_encoder_v4_0_0 = C:/Mentor/CompLib/2019.1.3/lte_dl_channel_encoder_v4_0_0 -xfft_v7_2_9 = C:/Mentor/CompLib/2019.1.3/xfft_v7_2_9 -lte_fft_v2_0_18 = C:/Mentor/CompLib/2019.1.3/lte_fft_v2_0_18 -xfft_v9_1_2 = C:/Mentor/CompLib/2019.1.3/xfft_v9_1_2 -lte_fft_v2_1_0 = C:/Mentor/CompLib/2019.1.3/lte_fft_v2_1_0 -xbip_dsp48_multacc_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_multacc_v3_0_6 -lte_pucch_receiver_v2_0_16 = C:/Mentor/CompLib/2019.1.3/lte_pucch_receiver_v2_0_16 -xbip_multadd_v3_0_14 = C:/Mentor/CompLib/2019.1.3/xbip_multadd_v3_0_14 -lte_rach_detector_v3_1_5 = C:/Mentor/CompLib/2019.1.3/lte_rach_detector_v3_1_5 -lte_ul_channel_decoder_v4_0_16 = C:/Mentor/CompLib/2019.1.3/lte_ul_channel_decoder_v4_0_16 -mailbox_v2_1_11 = C:/Mentor/CompLib/2019.1.3/mailbox_v2_1_11 -mdm_v3_2_16 = C:/Mentor/CompLib/2019.1.3/mdm_v3_2_16 -iomodule_v3_0 = C:/Mentor/CompLib/2019.1.3/iomodule_v3_0 -lmb_bram_if_cntlr_v4_0 = C:/Mentor/CompLib/2019.1.3/lmb_bram_if_cntlr_v4_0 -lmb_v10_v3_0 = C:/Mentor/CompLib/2019.1.3/lmb_v10_v3_0 -axi_lite_ipif_v3_0 = C:/Mentor/CompLib/2019.1.3/axi_lite_ipif_v3_0 -mdm_v3_2 = C:/Mentor/CompLib/2019.1.3/mdm_v3_2 -microblaze_mcs_v2_3_6 = C:/Mentor/CompLib/2019.1.3/microblaze_mcs_v2_3_6 -noc_mc_ddr4_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_mc_ddr4_phy_v1_0_0 -perf_axi_tg_v1_0_8 = C:/Mentor/CompLib/2019.1.3/perf_axi_tg_v1_0_8 -polar_v1_0_3 = C:/Mentor/CompLib/2019.1.3/polar_v1_0_3 -prc_v1_3_2 = C:/Mentor/CompLib/2019.1.3/prc_v1_3_2 -processing_system7_vip_v1_0_7 = C:/Mentor/CompLib/2019.1.3/processing_system7_vip_v1_0_7 -proc_sys_reset_v5_0_13 = C:/Mentor/CompLib/2019.1.3/proc_sys_reset_v5_0_13 -pr_axi_shutdown_manager_v1_0_1 = C:/Mentor/CompLib/2019.1.3/pr_axi_shutdown_manager_v1_0_1 -pr_bitstream_monitor_v1_0_1 = C:/Mentor/CompLib/2019.1.3/pr_bitstream_monitor_v1_0_1 -pr_decoupler_v1_0_7 = C:/Mentor/CompLib/2019.1.3/pr_decoupler_v1_0_7 -quadsgmii_v3_4_6 = C:/Mentor/CompLib/2019.1.3/quadsgmii_v3_4_6 -rs_decoder_v9_0_16 = C:/Mentor/CompLib/2019.1.3/rs_decoder_v9_0_16 -rs_encoder_v9_0_15 = C:/Mentor/CompLib/2019.1.3/rs_encoder_v9_0_15 -rxaui_v4_4_6 = C:/Mentor/CompLib/2019.1.3/rxaui_v4_4_6 -sd_fec_v1_1_3 = C:/Mentor/CompLib/2019.1.3/sd_fec_v1_1_3 -sid_v8_0_14 = C:/Mentor/CompLib/2019.1.3/sid_v8_0_14 -soft_ecc_proxy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/soft_ecc_proxy_v1_0_0 -spdif_v2_0_21 = C:/Mentor/CompLib/2019.1.3/spdif_v2_0_21 -srio_gen2_v4_1_6 = C:/Mentor/CompLib/2019.1.3/srio_gen2_v4_1_6 -switch_core_top_v1_0_7 = C:/Mentor/CompLib/2019.1.3/switch_core_top_v1_0_7 -sync_ip = C:/Mentor/CompLib/2019.1.3/sync_ip -tcc_decoder_3gppmm_v2_0_18 = C:/Mentor/CompLib/2019.1.3/tcc_decoder_3gppmm_v2_0_18 -tcc_encoder_3gpp_v5_0_15 = C:/Mentor/CompLib/2019.1.3/tcc_encoder_3gpp_v5_0_15 -tmr_comparator_v1_0_2 = C:/Mentor/CompLib/2019.1.3/tmr_comparator_v1_0_2 -tmr_sem_v1_0_9 = C:/Mentor/CompLib/2019.1.3/tmr_sem_v1_0_9 -tri_mode_ethernet_mac_v9_0_14 = C:/Mentor/CompLib/2019.1.3/tri_mode_ethernet_mac_v9_0_14 -tsn_temac_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tsn_temac_v1_0_4 -videoaxi4s_bridge_v1_0_5 = C:/Mentor/CompLib/2019.1.3/videoaxi4s_bridge_v1_0_5 -viterbi_v9_1_11 = C:/Mentor/CompLib/2019.1.3/viterbi_v9_1_11 -v_ccm_v6_0_15 = C:/Mentor/CompLib/2019.1.3/v_ccm_v6_0_15 -v_cfa_v7_0_14 = C:/Mentor/CompLib/2019.1.3/v_cfa_v7_0_14 -v_cresample_v4_0_14 = C:/Mentor/CompLib/2019.1.3/v_cresample_v4_0_14 -v_dual_splitter_v1_0_9 = C:/Mentor/CompLib/2019.1.3/v_dual_splitter_v1_0_9 -v_enhance_v8_0_15 = C:/Mentor/CompLib/2019.1.3/v_enhance_v8_0_15 -v_gamma_v7_0_15 = C:/Mentor/CompLib/2019.1.3/v_gamma_v7_0_15 -v_osd_v6_0_16 = C:/Mentor/CompLib/2019.1.3/v_osd_v6_0_16 -v_rgb2ycrcb_v7_1_13 = C:/Mentor/CompLib/2019.1.3/v_rgb2ycrcb_v7_1_13 -v_vid_sdi_tx_bridge_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_vid_sdi_tx_bridge_v2_0_0 -v_ycrcb2rgb_v7_1_13 = C:/Mentor/CompLib/2019.1.3/v_ycrcb2rgb_v7_1_13 -xbip_dsp48_macro_v3_0_17 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_macro_v3_0_17 -xfft_v9_0_17 = C:/Mentor/CompLib/2019.1.3/xfft_v9_0_17 -xsdbs_v1_0_2 = C:/Mentor/CompLib/2019.1.3/xsdbs_v1_0_2 -zynq_ultra_ps_e_vip_v1_0_5 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_vip_v1_0_5 -[DefineOptionset] -; Define optionset entries for the various compilers, vmake, and vsim. -; These option sets can be used with the "-optionset " syntax. -; i.e. -; vlog -optionset COMPILEDEBUG top.sv -; vsim -optionset UVMDEBUG my_top -; -; Following are some useful examples. - -; define a vsim optionset for uvm debugging -UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop - -; define a vopt optionset for debugging -VOPTDEBUG = +acc -debugdb - -[encryption] -; For vencrypt and vhencrypt. - -; Controls whether to encrypt whole files by ignoring all protect directives -; (except "viewport" and "interface_viewport") that are present in the input. -; The default is 0, use embedded protect directives to control the encryption. -; Set this to 1 to encrypt whole files by ignoring embedded protect directives. -; wholefile = 0 - -; Sets the data_method to use for the symmetric session key. -; The session key is a symmetric key that is randomly generated for each -; protected region (envelope) and is the heart of all encryption. This is used -; to set the length of the session key to generate and use when encrypting the -; HDL text. Supported values are aes128, aes192, and aes256. -; data_method = aes128 - -; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption -; "recipe" comprising an optional common block, at least one tool block (which -; contains the key public key), and the text to be encrypted. The common block -; and any of the tool blocks may contain rights in the form of the "control" -; directive. The text to be encrypted is specified either by setting -; "wholefile" to 1 or by embedding protect "begin" and "end" directives in -; the input HDL files. - -; Common recipe specification file. This file is optional. Its presence will -; require at least one "toolblock" to be specified. -; Directives such as "author" "author_info" and "data_method", -; as well as the common block license specification, go in this file. -; common = - -; Tool block specification recipe(s). Public key file with optional tool block -; file name. May be multiply-defined; at least one tool block is required if -; a recipe is being specified. -; Key file is a file name with no extension (.deprecated or .active will be -; supplied by the encryption tool). -; Rights file name is optional. -; toolblock = [,]{:[,]} - -; Location of directory containing recipe files. -; The default location is in the product installation directory. -; keyring = $MODEL_TECH/../keyring - -; Enable encryption statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list] -; Add '-' to disable specific statistics. Default is [cmd,msg]. -Stats = cmd,msg - -[vcom] -; VHDL93 variable selects language version as the default. -; Default is VHDL-2002. -; Value of 0 or 1987 for VHDL-1987. -; Value of 1 or 1993 for VHDL-1993. -; Default or value of 2 or 2002 for VHDL-2002. -; Value of 3 or 2008 for VHDL-2008 -; Value of 4 or ams99 for VHDL-AMS-1999 -; Value of 5 or ams07 for VHDL-AMS-2007 -VHDL93 = 2002 - -; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. -; ignoreStandardRealVector = 1 - -; Show source line containing error. Default is off. -; Show_source = 1 - -; Turn off unbound-component warnings. Default is on. -; Show_Warning1 = 0 - -; Turn off process-without-a-wait-statement warnings. Default is on. -; Show_Warning2 = 0 - -; Turn off null-range warnings. Default is on. -; Show_Warning3 = 0 - -; Turn off no-space-in-time-literal warnings. Default is on. -; Show_Warning4 = 0 - -; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. -; Show_Warning5 = 0 - -; Turn off optimization for IEEE std_logic_1164 package. Default is on. -; Optimize_1164 = 0 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Turn on resolving of ambiguous function overloading in favor of the -; "explicit" function declaration (not the one automatically created by -; the compiler for each type declaration). Default is off. -; The .ini file has Explicit enabled so that std_logic_signed/unsigned -; will match the behavior of synthesis tools. -Explicit = 1 - -; Turn off acceleration of the VITAL packages. Default is to accelerate. -; NoVital = 1 - -; Turn off VITAL compliance checking. Default is checking on. -; NoVitalCheck = 1 - -; Ignore VITAL compliance checking errors. Default is to not ignore. -; IgnoreVitalErrors = 1 - -; Turn off VITAL compliance checking warnings. Default is to show warnings. -; Show_VitalChecksWarnings = 0 - -; Turn off PSL assertion warning messages. Default is to show warnings. -; Show_PslChecksWarnings = 0 - -; Enable parsing of embedded PSL assertions. Default is enabled. -; EmbeddedPsl = 0 - -; Keep silent about case statement static warnings. -; Default is to give a warning. -; NoCaseStaticError = 1 - -; Keep silent about warnings caused by aggregates that are not locally static. -; Default is to give a warning. -; NoOthersStaticError = 1 - -; Treat as errors: -; case statement static warnings -; warnings caused by aggregates that are not locally static -; Overrides NoCaseStaticError, NoOthersStaticError settings. -; PedanticErrors = 1 - -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn off "Loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on some limited synthesis rule compliance checking. Checks only: -; -- signals used (read) by a process must be in the sensitivity list -; CheckSynthesis = 1 - -; Activate optimizations on expressions that do not involve signals, -; waits, or function/procedure/task invocations. Default is off. -; ScalarOpts = 1 - -; Turns on lint-style checking. -; Show_Lint = 1 - -; Require the user to specify a configuration for all bindings, -; and do not generate a compile time default binding for the -; component. This will result in an elaboration error of -; 'component not bound' if the user fails to do so. Avoids the rare -; issue of a false dependency upon the unused default binding. -; RequireConfigForAllDefaultBinding = 1 - -; Perform default binding at compile time. -; Default is to do default binding at load time. -; BindAtCompile = 1; - -; Inhibit range checking on subscripts of arrays. Range checking on -; scalars defined with subtypes is inhibited by default. -; NoIndexCheck = 1 - -; Inhibit range checks on all (implicit and explicit) assignments to -; scalar objects defined with subtypes. -; NoRangeCheck = 1 - -; Set the prefix to be honored for synthesis/coverage pragma recognition. -; Default is "". -; AddPragmaPrefix = "" - -; Ignore synthesis and coverage pragmas with this prefix. -; Default is "". -; IgnorePragmaPrefix = "" - -; Turn on code coverage in VHDL design units. Default is off. -; Coverage = sbceft - -; Turn off code coverage in VHDL subprograms. Default is on. -; CoverSub = 0 - -; Automatically exclude VHDL case statement OTHERS choice branches. -; This includes OTHERS choices in selected signal assigment statements. -; Default is to not exclude. -; CoverExcludeDefault = 1 - -; Control compiler and VOPT optimizations that are allowed when -; code coverage is on. Refer to the comment for this in the [vlog] area. -; CoverOpt = 3 - -; Turn on or off clkOpt optimization for code coverage. Default is on. -; CoverClkOpt = 1 - -; Turn on or off clkOpt optimization builtins for code coverage. Default is on. -; CoverClkOptBuiltins = 0 - -; Inform code coverage optimizations to respect VHDL 'H' and 'L' -; values on signals in conditions and expressions, and to not automatically -; convert them to '1' and '0'. Default is to not convert. -; CoverRespectHandL = 0 - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable or disable Focused Expression Coverage analysis for conditions and -; expressions. Focused Expression Coverage data is provided by default when -; expression and/or condition coverage is active. -; CoverFEC = 0 - -; Enable or disable UDP Coverage analysis for conditions and expressions. -; UDP Coverage data is disabled by default when expression and/or condition -; coverage is active. -; CoverUDP = 1 - -; Enable or disable Rapid Expression Coverage mode for conditions and expressions. -; Disabling this would convert non-masking conditions in FEC tables to matching -; input patterns. -; CoverREC = 1 - -; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions -; for expression/condition coverage. -; NOTE: Enabling this may have a negative impact on simulation performance. -; CoverExpandReductionPrefix = 0 - -; Enable or disable short circuit evaluation of conditions and expressions when -; condition or expression coverage is active. Short circuit evaluation is enabled -; by default. -; CoverShortCircuit = 0 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Use this directory for compiler temporary files instead of "work/_temp" -; CompilerTempDir = /tmp - -; Set this to cause the compilers to force data to be committed to disk -; when the files are closed. -; SyncCompilerFiles = 1 - -; Add VHDL-AMS declarations to package STANDARD -; Default is not to add -; AmsStandard = 1 - -; Range and length checking will be performed on array indices and discrete -; ranges, and when violations are found within subprograms, errors will be -; reported. Default is to issue warnings for violations, because subprograms -; may not be invoked. -; NoDeferSubpgmCheck = 0 - -; Turn ON detection of FSMs having single bit current state variable. -; FsmSingle = 1 - -; Turn off reset state transitions in FSM. -; FsmResetTrans = 0 - -; Turn ON detection of FSM Implicit Transitions. -; FsmImplicitTrans = 1 - -; Controls whether or not to show immediate assertions with constant expressions -; in GUI/report/UCDB etc. By default, immediate assertions with constant -; expressions are shown in GUI/report/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Controls how VHDL basic identifiers are stored with the design unit. -; Does not make the language case-sensitive, affects only how declarations -; declared with basic identifiers have their names stored and printed -; (in the GUI, examine, etc.). -; Default is to preserve the case as originally depicted in the VHDL source. -; Value of 0 indicates to change all basic identifiers to lower case. -; PreserveCase = 0 - -; For Configuration Declarations, controls the effect that USE clauses have -; on visibility inside the configuration items being configured. If 1 -; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, -; extend the visibility of objects made visible through USE clauses into nested -; component configurations. -; OldVHDLConfigurationVisibility = 0 - -; Allows VHDL configuration declarations to be in a different library from -; the corresponding configured entity. Default is to not allow this for -; stricter LRM-compliance. -; SeparateConfigLibrary = 1; - -; Determine how mode OUT subprogram parameters of type array and record are treated. -; If 0 (the default), then only VHDL 2008 will do this initialization. -; If 1, always initialize the mode OUT parameter to its default value. -; If 2, do not initialize the mode OUT out parameter. -; Note that prior to release 10.1, all language versions did not initialize mode -; OUT array and record type parameters, unless overridden here via this mechanism. -; In release 10.1 and later, only files compiled with VHDL 2008 will cause this -; initialization, unless overridden here. -; InitOutCompositeParam = 0 - -; Generate symbols debugging database in only some special cases to save on -; the number of files in the library. For other design-units, this database is -; generated on-demand in vsim. -; Default is to to generate debugging database for all design-units. -; SmartDbgSym = 1 - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -; Describe compilation options according to matching file patterns. -; File pattern * matches all printing characters other than '/'. -; File pattern **/x matches all paths containing file/directory x. -; File pattern x/** matches all paths beginning at directory x. -; FileOptMap = (**/*.vhd => -2008); - -; Describe library targets of compilation according to matching file patterns. -; LibMap = (**/*.vhd => work); - -[vlog] -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn off "Loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on Verilog hazard checking (order-dependent accessing of global vars). -; Default is off. -; Hazard = 1 - -; Turn on converting regular Verilog identifiers to uppercase. Allows case -; insensitivity for module names. Default is no conversion. -; UpCase = 1 - -; Activate optimizations on expressions that do not involve signals, -; waits, or function/procedure/task invocations. Default is off. -; ScalarOpts = 1 - -; Turns on lint-style checking. -; Show_Lint = 1 - -; Show source line containing error. Default is off. -; Show_source = 1 - -; Turn on bad option warning. Default is off. -; Show_BadOptionWarning = 1 - -; Revert back to IEEE 1364-1995 syntax, default is 0 (off). -; vlog95compat = 1 - -; Turn off PSL warning messages. Default is to show warnings. -; Show_PslChecksWarnings = 0 - -; Enable parsing of embedded PSL assertions. Default is enabled. -; EmbeddedPsl = 0 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Set the threshold for automatically identifying sparse Verilog memories. -; A memory with total size in bytes equal to or more than the sparse memory -; threshold gets marked as sparse automatically, unless specified otherwise -; in source code or by the +nosparse commandline option of vlog or vopt. -; The default is 1M. (i.e. memories with total size equal -; to or greater than 1Mb are marked as sparse) -; SparseMemThreshold = 1048576 - -; Set the prefix to be honored for synthesis and coverage pragma recognition. -; Default is "". -; AddPragmaPrefix = "" - -; Ignore synthesis and coverage pragmas with this prefix. -; Default is "". -; IgnorePragmaPrefix = "" - -; Set the option to treat all files specified in a vlog invocation as a -; single compilation unit. The default value is set to 0 which will treat -; each file as a separate compilation unit as specified in the P1800 draft standard. -; MultiFileCompilationUnit = 1 - -; Turn on code coverage in Verilog design units. Default is off. -; Coverage = sbceft - -; Automatically exclude Verilog case statement default branches. -; Default is to not automatically exclude defaults. -; CoverExcludeDefault = 1 - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Enable Multi Bit Expression Coverage in a Design, If design has expression with -; multi bit operands, this option enables its Expression Coverage. -; The default value is 0. -; CoverFecMultiBit = 1 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable or disable Focused Expression Coverage analysis for conditions and -; expressions. Focused Expression Coverage data is provided by default when -; expression and/or condition coverage is active. -; CoverFEC = 0 - -; Enable or disable UDP Coverage analysis for conditions and expressions. -; UDP Coverage data is disabled by default when expression and/or condition -; coverage is active. -; CoverUDP = 1 - -; Enable or disable Rapid Expression Coverage mode for conditions and expressions. -; Disabling this would convert non-masking conditions in FEC tables to matching -; input patterns. -; CoverREC = 1 - -; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions -; for expression/condition coverage. -; NOTE: Enabling this may have a negative impact on simulation performance. -; CoverExpandReductionPrefix = 0 - -; Enable or disable short circuit evaluation of conditions and expressions when -; condition or expression coverage is active. Short circuit evaluation is enabled -; by default. -; CoverShortCircuit = 0 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Turn on code coverage in VLOG `celldefine modules, modules containing -; specify blocks, and modules included using vlog -v and -y. Default is off. -; CoverCells = 1 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Control compiler and VOPT optimizations that are allowed when -; code coverage is on. This is a number from 0 to 5, with the following -; meanings (the default is 3): -; 5 -- All allowable optimizations are on. -; 4 -- Turn off removing unreferenced code. -; 3 -- Turn off process, always block and if statement merging. -; 2 -- Turn off expression optimization, converting primitives -; to continuous assignments, VHDL subprogram inlining. -; and VHDL clkOpt (converting FF's to builtins). -; 1 -- Turn off continuous assignment optimizations and clock suppression. -; 0 -- Turn off Verilog module inlining and VHDL arch inlining. -; HOWEVER, if fsm coverage is turned on, optimizations will be forced to -; level 3, with also turning off converting primitives to continuous assigns. -; CoverOpt = 3 - -; Specify the override for the default value of "cross_num_print_missing" -; option for the Cross in Covergroups. If not specified then LRM default -; value of 0 (zero) is used. This is a compile time option. -; SVCrossNumPrintMissingDefault = 0 - -; Setting following to 1 would cause creation of variables which -; would represent the value of Coverpoint expressions. This is used -; in conjunction with "SVCoverpointExprVariablePrefix" option -; in the modelsim.ini -; EnableSVCoverpointExprVariable = 0 - -; Specify the override for the prefix used in forming the variable names -; which represent the Coverpoint expressions. This is used in conjunction with -; "EnableSVCoverpointExprVariable" option of the modelsim.ini -; The default prefix is "expr". -; The variable name is -; variable name => _ -; SVCoverpointExprVariablePrefix = expr - -; Override for the default value of the SystemVerilog covergroup, -; coverpoint, and cross option.goal (defined to be 100 in the LRM). -; NOTE: It does not override specific assignments in SystemVerilog -; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" -; in the [vsim] section can override this value. -; SVCovergroupGoalDefault = 100 - -; Override for the default value of the SystemVerilog covergroup, -; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) -; NOTE: It does not override specific assignments in SystemVerilog -; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" -; in the [vsim] section can override this value. -; SVCovergroupTypeGoalDefault = 100 - -; Specify the override for the default value of "strobe" option for the -; Covergroup Type. This is a compile time option which forces "strobe" to -; a user specified default value and supersedes SystemVerilog specified -; default value of '0'(zero). NOTE: This can be overriden by a runtime -; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. -; SVCovergroupStrobeDefault = 0 - -; Specify the override for the default value of "per_instance" option for the -; Covergroup variables. This is a compile time option which forces "per_instance" -; to a user specified default value and supersedes SystemVerilog specified -; default value of '0'(zero). -; SVCovergroupPerInstanceDefault = 0 - -; Specify the override for the default value of "get_inst_coverage" option for the -; Covergroup variables. This is a compile time option which forces -; "get_inst_coverage" to a user specified default value and supersedes -; SystemVerilog specified default value of '0'(zero). -; SVCovergroupGetInstCoverageDefault = 0 - -; -; A space separated list of resource libraries that contain precompiled -; packages. The behavior is identical to using the "-L" switch. -; -; LibrarySearchPath = [ ...] -LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact - -; The behavior is identical to the "-mixedansiports" switch. Default is off. -; MixedAnsiPorts = 1 - -; Enable SystemVerilog 3.1a $typeof() function. Default is off. -; EnableTypeOf = 1 - -; Only allow lower case pragmas. Default is disabled. -; AcceptLowerCasePragmaOnly = 1 - -; Set the maximum depth permitted for a recursive include file nesting. -; IncludeRecursionDepthMax = 5 - -; Turn ON detection of FSMs having single bit current state variable. -; FsmSingle = 1 - -; Turn off reset state transitions in FSM. -; FsmResetTrans = 0 - -; Turn off detections of FSMs having x-assignment. -; FsmXAssign = 0 - -; Turn ON detection of FSM Implicit Transitions. -; FsmImplicitTrans = 1 - -; List of file suffixes which will be read as SystemVerilog. White space -; in extensions can be specified with a back-slash: "\ ". Back-slashes -; can be specified with two consecutive back-slashes: "\\"; -; SvFileSuffixes = sv svp svh - -; This setting is the same as the vlog -sv command line switch. -; Enables SystemVerilog features and keywords when true (1). -; When false (0), the rules of IEEE Std 1364-2005 are followed and -; SystemVerilog keywords are ignored. -; Svlog = 0 - -; Prints attribute placed upon SV packages during package import -; when true (1). The attribute will be ignored when this -; entry is false (0). The attribute name is "mti_design_element_load_message". -; The value of this attribute is a string literal. -; Default is true (1). -; PrintSVPackageLoadingAttribute = 1 - -; Do not show immediate assertions with constant expressions in -; GUI/reports/UCDB etc. By default immediate assertions with constant -; expressions are shown in GUI/reports/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Controls if untyped parameters that are initialized with values greater -; than 2147483647 are mapped to generics of type INTEGER or ignored. -; If mapped to VHDL Integers, values greater than 2147483647 -; are mapped to negative values. -; Default is to map these parameter to generic of type INTEGER -; ForceUnsignedToVHDLInteger = 1 - -; Enable AMS wreal (wired real) extensions. Default is 0. -; WrealType = 1 - -; Controls SystemVerilog Language Extensions. These options enable -; some non-LRM compliant behavior. -; SvExtensions = [+|-][,[+|-]*] - -; Generate symbols debugging database in only some special cases to save on -; the number of files in the library. For other design-units, this database is -; generated on-demand in vsim. -; Default is to to generate debugging database for all design-units. -; SmartDbgSym = 1 - -; Controls how $unit library entries are named. Valid options are: -; "file" (generate name based on the first file on the command line) -; "du" (generate name based on first design unit following an item -; found in $unit scope) -; CUAutoName = file - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -[sccom] -; Enable use of SCV include files and library. Default is off. -; UseScv = 1 - -; Add C++ compiler options to the sccom command line by using this variable. -; CppOptions = -g - -; Use custom C++ compiler located at this path rather than the default path. -; The path should point directly at a compiler executable. -; CppPath = /usr/bin/g++ - -; Specify the compiler version from the list of support GNU compilers. -; examples 4.7.4, 5.3.0, 7.4.0 -; CppInstall = 7.4.0 - -; Enable verbose messages from sccom. Default is off. -; SccomVerbose = 1 - -; sccom logfile. Default is no logfile. -; SccomLogfile = sccom.log - -; Enable use of SC_MS include files and library. Default is off. -; UseScMs = 1 - -; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. -; Sc22Mode = 1 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -; Enable use of UVMC library. Default is off. -; UseUvmc = 1 - -[vopt] -; Turn on code coverage in vopt. Default is off. -; Coverage = sbceft - -; enable or disable param saving in UCDB. -; CoverageSaveParam = 0 - -; Control compiler optimizations that are allowed when -; code coverage is on. Refer to the comment for this in the [vlog] area. -; CoverOpt = 3 - -; Controls set of CoverConstructs that are being considered for Coverage -; Collection. -; Some of Valid options are: default,set1,set2 -; Covermode = default - -; Controls set of HDL cover constructs that would be considered(or not considered) -; for Coverage Collection. (Default corresponds to covermode default). -; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". -; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Enable Multi Bit Expression Coverage in a Design, If design has expression with -; multi bit operands, this option enables its Expression Coverage. -; The default value is 0. -; CoverFecMultiBit = 1 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Do not show immediate assertions with constant expressions in -; GUI/reports/UCDB etc. By default immediate assertions with constant -; expressions are shown in GUI/reports/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Set the maximum number of iterations permitted for a generate loop. -; Restricting this permits the implementation to recognize infinite -; generate loops. -; GenerateLoopIterationMax = 100000 - -; Set the maximum depth permitted for a recursive generate instantiation. -; Restricting this permits the implementation to recognize infinite -; recursions. -; GenerateRecursionDepthMax = 200 - -; Set the number of processes created during the code generation phase. -; By default a heuristic is used to set this value. This may be set to 0 -; to disable this feature completely. -; ParallelJobs = 0 - -; Controls SystemVerilog Language Extensions. These options enable -; some non-LRM compliant behavior. -; SvExtensions = [+|-][,[+|-]*] - -; Load the specified shared objects with the RTLD_GLOBAL flag. -; This gives global visibility to all symbols in the shared objects, -; meaning that subsequently loaded shared objects can bind to symbols -; in the global shared objects. The list of shared objects should -; be whitespace delimited. This option is not supported on the -; Windows or AIX platforms. -; GlobalSharedObjectList = example1.so example2.so example3.so - -; Disable SystemVerilog elaboration system task messages -; IgnoreSVAInfo = 1 -; IgnoreSVAWarning = 1 -; IgnoreSVAError = 1 -; IgnoreSVAFatal = 1 - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -[vsim] -; vopt flow -; Set to turn on automatic optimization of a design. -; Default is on -VoptFlow = 1 - -; Simulator resolution -; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. -Resolution = fs - -; Disable certain code coverage exclusions automatically. -; Assertions and FSM are exluded from the code coverage by default -; Set AutoExclusionsDisable = fsm to enable code coverage for fsm -; Set AutoExclusionsDisable = assertions to enable code coverage for assertions -; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions -; Or specify comma or space separated list -;AutoExclusionsDisable = fsm,assertions - -; User time unit for run commands -; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the -; unit specified for Resolution. For example, if Resolution is 100ps, -; then UserTimeUnit defaults to ps. -; Should generally be set to default. -UserTimeUnit = default - -; Default run length -RunLength = 100 - -; Maximum iterations that can be run without advancing simulation time -IterationLimit = 10000000 - -; Specify libraries to be searched for precompiled modules -; LibrarySearchPath = [ ...] - -; Set XPROP assertion fail limit. Default is 5. -; Any positive integer, -1 for infinity. -; XpropAssertionLimit = 5 - -; Control PSL and Verilog Assume directives during simulation -; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts -; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts -; SimulateAssumeDirectives = 1 - -; Control the simulation of PSL and SVA -; These switches can be overridden by the vsim command line switches: -; -psl, -nopsl, -sva, -nosva. -; Set SimulatePSL = 0 to disable PSL simulation -; Set SimulatePSL = 1 to enable PSL simulation (default) -; SimulatePSL = 1 -; Set SimulateSVA = 0 to disable SVA simulation -; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) -; SimulateSVA = 1 - -; Control SVA and VHDL immediate assertion directives during simulation -; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts -; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts -; SimulateImmedAsserts = 1 - -; License feature mappings for Verilog and VHDL -; qhsimvh Single language VHDL license -; qhsimvl Single language Verilog license -; msimhdlsim Language neutral license for either Verilog or VHDL -; msimhdlmix Second language only, language neutral license for either -; Verilog or VHDL -; -; Directives to license manager can be set either as single value or as -; space separated multi-values: -; vhdl Immediately checkout and hold a VHDL license (i.e., one of -; qhsimvh, msimhdlsim, or msimhdlmix) -; vlog Immediately checkout and hold a Verilog license (i.e., one of -; qhsimvl, msimhdlsim, or msimhdlmix) -; plus Immediately checkout and hold a VHDL license and a Verilog license -; noqueue Do not wait in the license queue when a license is not available -; viewsim Try for viewer license but accept simulator license(s) instead -; of queuing for viewer license (PE ONLY) -; noviewer Disable checkout of msimviewer license feature (PE ONLY) -; noslvhdl Disable checkout of qhsimvh license feature -; noslvlog Disable checkout of qhsimvl license feature -; nomix Disable checkout of msimhdlmix license feature -; nolnl Disable checkout of msimhdlsim license feature -; mixedonly Disable checkout of qhsimvh and qhsimvl license features -; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features -; -; Examples (remove ";" comment character to activate licensing directives): -; Single directive: -; License = plus -; Multi-directive (Note: space delimited directives): -; License = noqueue plus - -; Severity level of a VHDL assertion message or of a SystemVerilog severity system task -; which will cause a running simulation to stop. -; VHDL assertions and SystemVerilog severity system task that occur with the -; given severity or higher will cause a running simulation to stop. -; This value is ignored during elaboration. -; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal -BreakOnAssertion = 3 - -; Severity level of a tool message which will cause a running simulation to -; stop. This value is ignored during elaboration. Default is to not break. -; 0 = Note 1 = Warning 2 = Error 3 = Fatal -;BreakOnMessage = 2 - -; The class debug feature enables more visibility and tracking of class instances -; during simulation. By default this feature is disabled (0). To enable this -; feature set ClassDebug to 1. -; ClassDebug = 1 - -; Message Format conversion specifications: -; %S - Severity Level of message/assertion -; %R - Text of message -; %T - Time of message -; %D - Delta value (iteration number) of Time -; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected -; %i - Instance/Region/Signal pathname with Process name (if available) -; %I - shorthand for one of these: -; " %K: %i" -; " %K: %i File: %F" (when path is not Process or Signal) -; except that the %i in this case does not report the Process name -; %O - Process name -; %P - Instance/Region path without leaf process -; %F - File name -; %L - Line number; if assertion message, then line number of assertion or, if -; assertion is in a subprogram, line from which the call is made -; %u - Design unit name in form library.primary -; %U - Design unit name in form library.primary(secondary) -; %% - The '%' character itself -; -; If specific format for Severity Level is defined, use that format. -; Else, for a message that occurs during elaboration: -; -- Failure/Fatal message in VHDL region that is not a Process, and in -; certain non-VHDL regions, uses MessageFormatBreakLine; -; -- Failure/Fatal message otherwise uses MessageFormatBreak; -; -- Note/Warning/Error message uses MessageFormat. -; Else, for a message that occurs during runtime and triggers a breakpoint because -; of the BreakOnAssertion setting: -; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; -; -- otherwise uses MessageFormatBreak. -; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. -; -; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" -; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" -; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" -; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" - -; Error File - alternate file for storing error messages -; ErrorFile = error.log - -; Simulation Breakpoint messages -; This flag controls the display of function names when reporting the location -; where the simulator stops because of a breakpoint or fatal error. -; Example with function name: # Break in Process ctr at counter.vhd line 44 -; Example without function name: # Break at counter.vhd line 44 -; Default value is 1. -ShowFunctions = 1 - -; Default radix for all windows and commands. -; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned -; Flags may be one of: enumnumeric, showbase, wreal -DefaultRadix = hexadecimal -DefaultRadixFlags = showbase -; Set to 1 for make the signal_force VHDL and Verilog functions use the -; default radix when processing the force value. Prior to 10.2 signal_force -; used the default radix, now it always uses symbolic unless value explicitly indicates base -;SignalForceFunctionUseDefaultRadix = 0 - -; VSIM Startup command -; Startup = do startup.do - -; VSIM Shutdown file -; Filename to save u/i formats and configurations. -; ShutdownFile = restart.do -; To explicitly disable auto save: -; ShutdownFile = --disable-auto-save - -; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. -; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. -; BatchMode = 1 - -; File for saving command transcript when -batch option used -; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero -; default is unset so command transcript only goes to stdout for better performance -; BatchTranscriptFile = transcript - -; File for saving command transcript, this option is ignored when -batch option is used -TranscriptFile = transcript - -; Transcript file long line wrapping mode(s) -; mode == 0 :: no wrapping, line recorded as is -; mode == 1 :: wrap at first whitespace after WSColumn -; or at Column. -; mode == 2 :: wrap as above, but add continuation -; character ('\') at end of each wrapped line -; -; WrapMode = 0 -; WrapColumn = 30000 -; WrapWSColumn = 27000 - -; File for saving command history -; CommandHistory = cmdhist.log - -; Specify whether paths in simulator commands should be described -; in VHDL or Verilog format. -; For VHDL, PathSeparator = / -; For Verilog, PathSeparator = . -; Must not be the same character as DatasetSeparator. -PathSeparator = / - -; Specify the dataset separator for fully rooted contexts. -; The default is ':'. For example: sim:/top -; Must not be the same character as PathSeparator. -DatasetSeparator = : - -; Specify a unique path separator for the Signal Spy set of functions. -; The default will be to use the PathSeparator variable. -; Must not be the same character as DatasetSeparator. -; SignalSpyPathSeparator = / - -; Used to control parsing of HDL identifiers input to the tool. -; This includes CLI commands, vsim/vopt/vlog/vcom options, -; string arguments to FLI/VPI/DPI calls, etc. -; If set to 1, accept either Verilog escaped Id syntax or -; VHDL extended id syntax, regardless of source language. -; If set to 0, the syntax of the source language must be used. -; Each identifier in a hierarchical name may need different syntax, -; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or -; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" -; GenerousIdentifierParsing = 1 - -; Disable VHDL assertion messages -; IgnoreNote = 1 -; IgnoreWarning = 1 -; IgnoreError = 1 -; IgnoreFailure = 1 - -; Disable SystemVerilog assertion messages -; IgnoreSVAInfo = 1 -; IgnoreSVAWarning = 1 -; IgnoreSVAError = 1 -; IgnoreSVAFatal = 1 - -; Do not print any additional information from Severity System tasks. -; Only the message provided by the user is printed along with severity -; information. -; SVAPrintOnlyUserMessage = 1; - -; Default force kind. May be freeze, drive, deposit, or default -; or in other terms, fixed, wired, or charged. -; A value of "default" will use the signal kind to determine the -; force kind, drive for resolved signals, freeze for unresolved signals -; DefaultForceKind = freeze - -; Control the iteration of events when a VHDL signal is forced to a value -; This flag can be set to honour the signal update event in next iteration, -; the default is to update and propagate in the same iteration. -; ForceSigNextIter = 1 - -; Enable simulation statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; If zero, open files when elaborated; otherwise, open files on -; first read or write. Default is 0. -; DelayFileOpen = 1 - -; Control VHDL files opened for write. -; 0 = Buffered, 1 = Unbuffered -UnbufferedOutput = 0 - -; Control the number of VHDL files open concurrently. -; This number should always be less than the current ulimit -; setting for max file descriptors. -; 0 = unlimited -ConcurrentFileLimit = 40 - -; If nonzero, close files as soon as there is either an explicit call to -; file_close, or when the file variable's scope is closed. When zero, a -; file opened in append mode is not closed in case it is immediately -; reopened in append mode; otherwise, the file will be closed at the -; point it is reopened. -; AppendClose = 1 - -; Control the number of hierarchical regions displayed as -; part of a signal name shown in the Wave window. -; A value of zero tells VSIM to display the full name. -; The default is 0. -; WaveSignalNameWidth = 0 - -; Turn off warnings when changing VHDL constants and generics -; Default is 1 to generate warning messages -; WarnConstantChange = 0 - -; Turn off warnings from accelerated versions of the std_logic_arith, -; std_logic_unsigned, and std_logic_signed packages. -; StdArithNoWarnings = 1 - -; Turn off warnings from accelerated versions of the IEEE numeric_std -; and numeric_bit packages. -; NumericStdNoWarnings = 1 - -; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names -; in the design hierarchy. -; This style is controlled by the value of the GenerateFormat -; value described next. Default is to use new-style names, which -; comprise the generate statement label, '(', the value of the generate -; parameter, and a closing ')'. -; Set this to 1 to use old-style names. -; OldVhdlForGenNames = 1 - -; Control the format of the old-style VHDL FOR generate statement region -; name for each iteration. Do not quote the value. -; The format string here must contain the conversion codes %s and %d, -; in that order, and no other conversion codes. The %s represents -; the generate statement label; the %d represents the generate parameter value -; at a particular iteration (this is the position number if the generate parameter -; is of an enumeration type). Embedded whitespace is allowed (but discouraged); -; leading and trailing whitespace is ignored. -; Application of the format must result in a unique region name over all -; loop iterations for a particular immediately enclosing scope so that name -; lookup can function properly. The default is %s__%d. -; GenerateFormat = %s__%d - -; Enable more efficient logging of VHDL Variables. -; Logging VHDL variables without this enabled, while possible, is very -; inefficient. Enabling this will provide a more efficient logging methodology -; at the expense of more memory usage. By default this feature is disabled (0). -; To enabled this feature, set this variable to 1. -; VhdlVariableLogging = 1 - -; Enable logging of VHDL access type variables and their designated objects. -; This setting will allow both variables of an access type ("access variables") -; and their designated objects ("access objects") to be logged. Logging a -; variable of an access type will automatically also cause the designated -; object(s) of that variable to be logged as the simulation progresses. -; Further, enabling this allows access objects to be logged by name. By default -; this feature is disabled (0). To enable this feature, set this variable to 1. -; Enabling this will automatically enable the VhdlVariableLogging feature also. -; AccessObjDebug = 1 - -; Make each VHDL package in a PDU has its own separate copy of the package instead -; of sharing the package between PDUs. The default is to share packages. -; To ensure that each PDU has its own set of packages, set this variable to 1. -; VhdlSeparatePduPackage = 1 - -; Specify whether checkpoint files should be compressed. -; The default is 1 (compressed). -; CheckpointCompressMode = 0 - -; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. -; Use custom gcc compiler located at this path rather than the default path. -; The path should point directly at a compiler executable. -; DpiCppPath = /bin/gcc -; -; Specify the compiler version from the list of support GNU compilers. -; examples 4.7.4, 5.3.0, 7.4.0 -; DpiCppInstall = 7.4.0 - -; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. -; The term "out-of-the-blue" refers to SystemVerilog export function calls -; made from C functions that don't have the proper context setup -; (as is the case when running under "DPI-C" import functions). -; When this is enabled, one can call a DPI export function -; (but not task) from any C code. -; the setting of this variable can be one of the following values: -; 0 : dpioutoftheblue call is disabled (default) -; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. -; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. -; DpiOutOfTheBlue = 1 - -; Specify whether continuous assignments are run before other normal priority -; processes scheduled in the same iteration. This event ordering minimizes race -; differences between optimized and non-optimized designs, and is the default -; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set -; ImmediateContinuousAssign to 0. -; The default is 1 (enabled). -; ImmediateContinuousAssign = 0 - -; List of dynamically loaded objects for Verilog PLI applications -; Veriuser = veriuser.sl - -; Which default VPI object model should the tool conform to? -; The 1364 modes are Verilog-only, for backwards compatibility with older -; libraries, and SystemVerilog objects are not available in these modes. -; -; In the absence of a user-specified default, the tool default is the -; latest available LRM behavior. -; Options for PliCompatDefault are: -; VPI_COMPATIBILITY_VERSION_1364v1995 -; VPI_COMPATIBILITY_VERSION_1364v2001 -; VPI_COMPATIBILITY_VERSION_1364v2005 -; VPI_COMPATIBILITY_VERSION_1800v2005 -; VPI_COMPATIBILITY_VERSION_1800v2008 -; -; Synonyms for each string are also recognized: -; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) -; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) -; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) -; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) -; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) - - -; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 - -; Specify whether the Verilog system task $fopen or vpi_mcd_open() -; will create directories that do not exist when opening the file -; in "a" or "w" mode. -; The default is 0 (do not create non-existent directories) -; CreateDirForFileAccess = 1 - -; Specify default options for the restart command. Options can be one -; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions -; DefaultRestartOptions = -force - - -; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. -; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. -; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". -; The list of options must be delimited by commas, without spaces or tabs. -; -; Some examples -; To turn on all available UVM-aware debug features: -; UVMControl = all -; To turn on the struct window, mesage logging, and transaction logging: -; UVMControl = struct,msglog,trlog -; To turn on all options except certe: -; UVMControl = all,-certe -; To completely disable all UVM-aware debug functionality: -; UVMControl = disable - -; Specify the WildcardFilter setting. -; A space separated list of object types to be excluded when performing -; wildcard matches with log, wave, etc commands. The default value for this variable is: -; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" -; See "Using the WildcardFilter Preference Variable" in the documentation for -; details on how to use this variable and for descriptions of the filter types. -WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile - -; Specify the WildcardSizeThreshold setting. -; This integer setting specifies the size at which objects will be excluded when -; performing wildcard matches with log, wave, etc commands. Objects of size equal -; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard -; matches. The size is a simple calculation of number of bits or items in the object. -; The default value is 8k (8192). Setting this value to 0 will disable the checking -; of object size against this threshold and allow all objects of any size to be logged. -WildcardSizeThreshold = 8192 - -; Specify whether warning messages are output when objects are filtered out due to the -; WildcardSizeThreshold. The default is 0 (no messages generated). -WildcardSizeThresholdVerbose = 0 - -; Turn on (1) or off (0) WLF file compression. -; The default is 1 (compress WLF file). -; WLFCompress = 0 - -; Specify whether to save all design hierarchy (1) in the WLF file -; or only regions containing logged signals (0). -; The default is 0 (save only regions with logged signals). -; WLFSaveAllRegions = 1 - -; WLF file time limit. Limit WLF file by time, as closely as possible, -; to the specified amount of simulation time. When the limit is exceeded -; the earliest times get truncated from the file. -; If both time and size limits are specified the most restrictive is used. -; UserTimeUnits are used if time units are not specified. -; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} -; WLFTimeLimit = 0 - -; WLF file size limit. Limit WLF file size, as closely as possible, -; to the specified number of megabytes. If both time and size limits -; are specified then the most restrictive is used. -; The default is 0 (no limit). -; WLFSizeLimit = 1000 - -; Specify whether or not a WLF file should be deleted when the -; simulation ends. A value of 1 will cause the WLF file to be deleted. -; The default is 0 (do not delete WLF file when simulation ends). -; WLFDeleteOnQuit = 1 - -; Specify whether or not a WLF file should be optimized during -; simulation. If set to 0, the WLF file will not be optimized. -; The default is 1, optimize the WLF file. -; WLFOptimize = 0 - -; Specify the name of the WLF file. -; The default is vsim.wlf -; WLFFilename = vsim.wlf - -; Specify whether to lock the WLF file. -; Locking the file prevents other invocations of ModelSim/Questa tools from -; inadvertently overwriting the WLF file. -; The default is 1, lock the WLF file. -; WLFFileLock = 0 - -; Specify the update interval for the WLF file in live simulation. -; The interval is given in seconds. -; The value is the smallest interval between WLF file updates. The WLF file -; will be flushed (updated) after (at least) the interval has elapsed, ensuring -; that the data is correct when viewed from a separate viewer. -; A value of 0 means that no updating will occur. -; The default value is 10 seconds. -; WLFUpdateInterval = 10 - -; Specify the WLF cache size limit for WLF files. -; The value is given in megabytes. A value of 0 turns off the cache. -; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). -; On Windows, the default value is 1000 (megabytes) to help to avoid filling -; process memory. -; WLFSimCacheSize allows a different cache size to be set for a live simulation -; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize -; is not set, it defaults to the WLFCacheSize value. -; WLFCacheSize = 2000 -; WLFSimCacheSize = 500 - -; Specify the WLF file event collapse mode. -; 0 = Preserve all events and event order. (same as -wlfnocollapse) -; 1 = Only record values of logged objects at the end of a simulator iteration. -; (same as -wlfcollapsedelta) -; 2 = Only record values of logged objects at the end of a simulator time step. -; (same as -wlfcollapsetime) -; The default is 1. -; WLFCollapseMode = 0 - -; Specify whether WLF file logging can use threads on multi-processor machines. -; If 0, no threads will be used; if 1, threads will be used if the system has -; more than one processor. -; WLFUseThreads = 1 - -; Specify the size of objects that will trigger "large object" messages -; at log/wave/list time. The size calculation of the object is the same as that -; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. -; Setting LargeObjectSize to 0 will disable these messages. -; LargeObjectSize = 500000 - -; Specify the depth of stack frames returned by $stacktrace([level]). -; This depth will be picked up when the optional 'level' argument -; is not specified or its value is not a positive integer. -; StackTraceDepth = 100 - -; Turn on/off undebuggable SystemC type warnings. Default is on. -; ShowUndebuggableScTypeWarning = 0 - -; Turn on/off unassociated SystemC name warnings. Default is off. -; ShowUnassociatedScNameWarning = 1 - -; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. -; ScShowIeeeDeprecationWarnings = 1 - -; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. -; For SystemC-2.3.2 the valid values are 0,1 and 2 -; 0 = SC_SIGNAL_WRITE_CHECK_DISABLE_ -; 1 = SC_SIGNAL_WRITE_CHECK_DEFAULT_ -; 2 = SC_SIGNAL_WRITE_CHECK_CONFLICT_ -; For SystemC-2.2 the valid values are 0 and 1 -; 0 = DISABLE -; 1 = ENABLE -; ScEnableScSignalWriteCheck = 1 - -; Set SystemC default time unit. -; Set to fs, ps, ns, us, ms, or sec with optional -; prefix of 1, 10, or 100. The default is 1 ns. -; The ScTimeUnit value is honored if it is coarser than Resolution. -; If ScTimeUnit is finer than Resolution, it is set to the value -; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, -; then the default time unit will be 1 ns. However if Resolution -; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. -ScTimeUnit = ns - -; Set SystemC sc_main stack size. The stack size is set as an integer -; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or -; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends -; on the amount of data on the sc_main() stack and the memory required -; to succesfully execute the longest function call chain of sc_main(). -ScMainStackSize = 10 Mb - -; Set SystemC thread stack size. The stack size is set as an integer -; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or -; Gb(Giga-byte). The stack size for sc_thread depends -; on the amount of data on the sc_thread stack and the memory required -; to succesfully execute the thread. -; ScStackSize = 1 Mb - -; Turn on/off execution of remainder of sc_main upon quitting the current -; simulation session. If the cumulative length of sc_main() in terms of -; simulation time units is less than the length of the current simulation -; run upon quit or restart, sc_main() will be in the middle of execution. -; This switch gives the option to execute the remainder of sc_main upon -; quitting simulation. The drawback of not running sc_main till the end -; is memory leaks for objects created by sc_main. If on, the remainder of -; sc_main will be executed ignoring all delays. This may cause the simulator -; to crash if the code in sc_main is dependent on some simulation state. -; Default is on. -ScMainFinishOnQuit = 1 - -; Enable calling of the DPI export taks/functions from the -; SystemC start_of_simulation() callback. -; The default is off. -; EnableDpiSosCb = 1 - - -; Set the SCV relationship name that will be used to identify phase -; relations. If the name given to a transactor relation matches this -; name, the transactions involved will be treated as phase transactions -ScvPhaseRelationName = mti_phase - -; Customize the vsim kernel shutdown behavior at the end of the simulation. -; Some common causes of the end of simulation are $finish (implicit or explicit), -; sc_stop(), tf_dofinish(), and assertion failures. -; This should be set to "ask", "exit", or "stop". The default is "ask". -; "ask" -- In batch mode, the vsim kernel will abruptly exit. -; In GUI mode, a dialog box will pop up and ask for user confirmation -; whether or not to quit the simulation. -; "stop" -- Cause the simulation to stay loaded in memory. This can make some -; post-simulation tasks easier. -; "exit" -- The simulation will abruptly exit without asking for any confirmation. -; "final" -- Run SystemVerilog final blocks then behave as "stop". -; Note: This variable can be overridden with the vsim "-onfinish" command line switch. -OnFinish = ask - -; Print pending deferred assertion messages. -; Deferred assertion messages may be scheduled after the $finish in the same -; time step. Deferred assertions scheduled to print after the $finish are -; printed before exiting with severity level NOTE since it's not known whether -; the assertion is still valid due to being printed in the active region -; instead of the reactive region where they are normally printed. -; OnFinishPendingAssert = 1; - -; Print "simstats" result. Default is 0. -; 0 == do not print simstats -; 1 == print at end of simulation -; 2 == print at end of each run command and end of simulation -; PrintSimStats = 1 - -; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages -; AssertFile = assert.log - -; Enable assertion counts. Default is off. -; AssertionCounts = 1 - -; Run simulator in assertion debug mode. Default is off. -; AssertionDebug = 1 - -; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. -; AssertionEnable = 0 - -; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. -; Any positive integer, -1 for infinity. -; AssertionLimit = 1 - -; Turn on/off concurrent assertion pass log. Default is off. -; Assertion pass logging is only enabled when assertion is browseable -; and assertion debug is enabled. -; AssertionPassLog = 1 - -; Turn on/off PSL concurrent assertion fail log. Default is on. -; The flag does not affect SVA -; AssertionFailLog = 0 - -; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. -; AssertionFailLocalVarLog = 0 - -; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. -; 0 = Continue 1 = Break 2 = Exit -; AssertionFailAction = 1 - -; Enable the active thread monitor in the waveform display when assertion debug is enabled. -; AssertionActiveThreadMonitor = 1 - -; Control how many waveform rows will be used for displaying the active threads. Default is 5. -; AssertionActiveThreadMonitorLimit = 5 - -; Assertion thread limit after which assertion would be killed/switched off. -; The default is -1 (unlimited). If the number of threads for an assertion go -; beyond this limit, the assertion would be either switched off or killed. This -; limit applies to only assert directives. -;AssertionThreadLimit = -1 - -; Action to be taken once the assertion thread limit is reached. Default -; is kill. It can have a value of off or kill. In case of kill, all the existing -; threads are terminated and no new attempts are started. In case of off, the -; existing attempts keep on evaluating but no new attempts are started. This -; variable applies to only assert directives. -;AssertionThreadLimitAction = kill - -; Cover thread limit after which cover would be killed/switched off. -; The default is -1 (unlimited). If the number of threads for a cover go -; beyond this limit, the cover would be either switched off or killed. This -; limit applies to only cover directives. -;CoverThreadLimit = -1 - -; Action to be taken once the cover thread limit is reached. Default -; is kill. It can have a value of off or kill. In case of kill, all the existing -; threads are terminated and no new attempts are started. In case of off, the -; existing attempts keep on evaluating but no new attempts are started. This -; variable applies to only cover directives. -;CoverThreadLimitAction = kill - - -; By default immediate assertions do not participate in Assertion Coverage calculations -; unless they are executed. This switch causes all immediate assertions in the design -; to participate in Assertion Coverage calculations, whether attempted or not. -; UnattemptedImmediateAssertions = 0 - -; By default immediate covers participate in Coverage calculations -; whether they are attempted or not. This switch causes all unattempted -; immediate covers in the design to stop participating in Coverage -; calculations. -; UnattemptedImmediateCovers = 0 - -; By default pass action block is not executed for assertions on vacuous -; success. The following variable is provided to enable execution of -; pass action block on vacuous success. The following variable is only effective -; if the user does not disable pass action block execution by using either -; system tasks or CLI. Also there is a performance penalty for enabling -; the following variable. -;AssertionEnableVacuousPassActionBlock = 1 - -; As per strict 1850-2005 PSL LRM, an always property can either pass -; or fail. However, by default, Questa reports multiple passes and -; multiple fails on top always/never property (always/never operator -; is the top operator under Verification Directive). The reason -; being that Questa reports passes and fails on per attempt of the -; top always/never property. Use the following flag to instruct -; Questa to strictly follow LRM. With this flag, all assert/never -; directives will start an attempt once at start of simulation. -; The attempt can either fail, match or match vacuously. -; For e.g. if always is the top operator under assert, the always will -; keep on checking the property at every clock. If the property under -; always fails, the directive will be considered failed and no more -; checking will be done for that directive. A top always property, -; if it does not fail, will show a pass at end of simulation. -; The default value is '0' (i.e. zero is off). For example: -; PslOneAttempt = 1 - -; Specify the number of clock ticks to represent infinite clock ticks. -; This affects eventually!, until! and until_!. If at End of Simulation -; (EOS) an active strong-property has not clocked this number of -; clock ticks then neither pass or fail (vacuous match) is returned -; else respective fail/pass is returned. The default value is '0' (zero) -; which effectively does not check for clock tick condition. For example: -; PslInfinityThreshold = 5000 - -; Control how many thread start times will be preserved for ATV viewing for a given assertion -; instance. Default is -1 (ALL). -; ATVStartTimeKeepCount = -1 - -; Turn on/off code coverage -; CodeCoverage = 0 - -; This option applies to condition and expression coverage UDP tables. It -; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. -; If this option is used and a match occurs in more than one row in the UDP table, -; none of the counts for all matching rows is incremented. By default, counts are -; incremented for all matching rows. -; CoverCountAll = 1 - -; Turn off automatic inclusion of VHDL integers in toggle coverage. Default -; is to include them. -; ToggleNoIntegers = 1 - -; Set the maximum number of values that are collected for toggle coverage of -; VHDL integers. Default is 100; -; ToggleMaxIntValues = 100 - -; Set the maximum number of values that are collected for toggle coverage of -; Verilog real. Default is 100; -; ToggleMaxRealValues = 100 - -; Turn on automatic inclusion of Verilog integers in toggle coverage, except -; for enumeration types. Default is to include them. -; ToggleVlogIntegers = 0 - -; Turn on automatic inclusion of Verilog real type in toggle coverage, except -; for shortreal types. Default is to not include them. -; ToggleVlogReal = 1 - -; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays -; and VHDL arrays-of-arrays in toggle coverage. -; Default is to not include them. -; ToggleFixedSizeArray = 1 - -; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, -; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. -; This leads to a longer simulation time with bigger arrays covered with toggle coverage. -; Default is 1024. -; ToggleMaxFixedSizeArray = 1024 - -; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized -; one-dimensional packed vectors for toggle coverage. Default is 0. -; TogglePackedAsVec = 0 - -; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for -; toggle coverage. Default is 0. -; ToggleVlogEnumBits = 0 - -; Turn off automatic inclusion of VHDL records in toggle coverage. -; Default is to include them. -; ToggleVHDLRecords = 0 - -; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. -; For unlimited width, set to 0. -; ToggleWidthLimit = 128 - -; Limit the counts that are tracked for toggle coverage. When all edges for a bit have -; reached this count, further activity on the bit is ignored. Default is 1. -; For unlimited counts, set to 0. -; ToggleCountLimit = 1 - -; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. -; Following is the toggle coverage calculation criteria based on extended toggle mode: -; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). -; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. -; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. -; ExtendedToggleMode = 3 - -; Enable toggle statistics collection only for ports. Default is 0. -; TogglePortsOnly = 1 - -; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has -; reached this count, further tracking of the input patterns linked to it is ignored. -; Default is 1. For unlimited counts, set to 0. -; NOTE: Changing this value from its default value may affect simulation performance. -; FecCountLimit = 1 - -; Limit the counts that are tracked for UDP Coverage. When a bin has -; reached this count, further tracking of the input patterns linked to it is ignored. -; Default is 1. For unlimited counts, set to 0. -; NOTE: Changing this value from its default value may affect simulation performance. -; UdpCountLimit = 1 - -; Control toggle coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either -; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; ToggleDeglitchPeriod = 10.0ps - -; Turn on/off all PSL/SVA cover directive enables. Default is on. -; CoverEnable = 0 - -; Turn on/off PSL/SVA cover log. Default is off "0". -; CoverLog = 1 - -; Set "at_least" value for all PSL/SVA cover directives. Default is 1. -; CoverAtLeast = 2 - -; Set "limit" value for all PSL/SVA cover directives. Default is -1. -; Any positive integer, -1 for infinity. -; CoverLimit = 1 - -; Specify the coverage database filename. -; Default is "" (i.e. database is NOT automatically saved on close). -; UCDBFilename = vsim.ucdb - -; Specify the maximum limit for the number of Cross (bin) products reported -; in XML and UCDB report against a Cross. A warning is issued if the limit -; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this -; setting. -; MaxReportRhsSVCrossProducts = 1000 - -; Specify the override for the "auto_bin_max" option for the Covergroups. -; If not specified then value from Covergroup "option" is used. -; SVCoverpointAutoBinMax = 64 - -; Specify the override for the value of "cross_num_print_missing" -; option for the Cross in Covergroups. If not specified then value -; specified in the "option.cross_num_print_missing" is used. This -; is a runtime option. NOTE: This overrides any "cross_num_print_missing" -; value specified by user in source file and any SVCrossNumPrintMissingDefault -; specified in modelsim.ini. -; SVCrossNumPrintMissing = 0 - -; Specify whether to use the value of "cross_num_print_missing" -; option in report and GUI for the Cross in Covergroups. If not specified then -; cross_num_print_missing is ignored for creating reports and displaying -; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". -; UseSVCrossNumPrintMissing = 0 - -; Specify the threshold of Coverpoint wildcard bin value range size, above which -; a warning will be triggered. The default is 4K -- 12 wildcard bits. -; SVCoverpointWildCardBinValueSizeWarn = 4096 - -; Specify the override for the value of "strobe" option for the -; Covergroup Type. If not specified then value in "type_option.strobe" -; will be used. This is runtime option which forces "strobe" to -; user specified value and supersedes user specified values in the -; SystemVerilog Code. NOTE: This also overrides the compile time -; default value override specified using "SVCovergroupStrobeDefault" -; SVCovergroupStrobe = 0 - -; Override for explicit assignments in source code to "option.goal" of -; SystemVerilog covergroup, coverpoint, and cross. It also overrides the -; default value of "option.goal" (defined to be 100 in the SystemVerilog -; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". -; SVCovergroupGoal = 100 - -; Override for explicit assignments in source code to "type_option.goal" of -; SystemVerilog covergroup, coverpoint, and cross. It also overrides the -; default value of "type_option.goal" (defined to be 100 in the SystemVerilog -; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". -; SVCovergroupTypeGoal = 100 - -; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() -; builtin functions, and report. This setting changes the default values of -; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 -; behavior if explicit assignments are not made on option.get_inst_coverage and -; type_option.merge_instances by the user. There are two vsim command line -; options, -cvg63 and -nocvg63 to override this setting from vsim command line. -; The default value of this variable from release 6.6 onwards is 0. This default -; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. -; SVCovergroup63Compatibility = 0 - -; Enforce the default behavior of covergroup get_coverage() builtin function, GUI -; and report. This variable sets the default value of type_option.merge_instances. -; There are two vsim command line options, -cvgmergeinstances and -; -nocvgmergeinstances to override this setting from vsim command line. -; The default value of this variable, -1 (don't care), allows the tool to determine -; the effective value, based on factors related to capacity and optimization. -; The type_option.merge_instances appears in the GUI and coverage reports as either -; auto(1) or auto(0), depending on whether the effective value was determined to -; be a 1 or a 0. -; SVCovergroupMergeInstancesDefault = -1 - -; Enable or disable generation of more detailed information about the sampling -; of covergroup, cross, and coverpoints. It provides the details of the number -; of times the covergroup instance and type were sampled, as well as details -; about why covergroup, cross and coverpoint were not covered. A non-zero value -; is to enable this feature. 0 is to disable this feature. Default is 0 -; SVCovergroupSampleInfo = 0 - -; Specify the maximum number of Coverpoint bins in whole design for -; all Covergroups. -; MaxSVCoverpointBinsDesign = 2147483648 - -; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins -; MaxSVCoverpointBinsInst = 1048576 - -; Specify the maximum number of Cross bins in whole design for -; all Covergroups. -; MaxSVCrossBinsDesign = 2147483648 - -; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins -; MaxSVCrossBinsInst = 67108864 - -; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. -; By default, this variable is set 0, in which case option.no_collect setting will take effect. -; If this variable is set to 1, all zero-weight coverage items will not be saved. -; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting -; of this variable. -; CvgZWNoCollect = 1 - -; Specify a space delimited list of double quoted TCL style -; regular expressions which will be matched against the text of all messages. -; If any regular expression is found to be contained within any message, the -; status for that message will not be propagated to the UCDB TESTSTATUS. -; If no match is detected, then the status will be propagated to the -; UCDB TESTSTATUS. More than one such regular expression text is allowed, -; and each message text is compared for each regular expression in the list. -; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" - -; Set weight for all PSL/SVA cover directives. Default is 1. -; CoverWeight = 2 - -; Check vsim plusargs. Default is 0 (off). -; 0 = Don't check plusargs -; 1 = Warning on unrecognized plusarg -; 2 = Error and exit on unrecognized plusarg -; CheckPlusargs = 1 - -; Load the specified shared objects with the RTLD_GLOBAL flag. -; This gives global visibility to all symbols in the shared objects, -; meaning that subsequently loaded shared objects can bind to symbols -; in the global shared objects. The list of shared objects should -; be whitespace delimited. This option is not supported on the -; Windows or AIX platforms. -; GlobalSharedObjectList = example1.so example2.so example3.so - -; Generate the stub definitions for the undefined symbols in the shared libraries being -; loaded in the simulation. When this flow is turned on, the undefined symbols will not -; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. -; The valid arguments are: on, off, verbose. -; on : turn on the automatic generation of stub definitions. -; off: turn off the flow. The undefined symbols will trigger an immediate load failure. -; verbose: Turn on the flow and report the undefined symbols for each shared library. -; NOTE: This variable can be overriden with vsim switch "-undefsyms". -; The default is on. -; -; UndefSyms = off - -; Enable the support for checkpointing foreign C/C++ libraries. -; The valid arguments are: 0, 1, 2 -; 0: off (default) -; 1: on (manually save/restore user shared library data) -; 2: auto (automatically save/restore user shared library data) -; This option is not supported on the Windows platforms. -; -; AllowCheckpointCpp = 2 - -; Initial seed for the random number generator of the root thread (SystemVerilog). -; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. -; The default value is 0. -; Sv_Seed = 0 - -; Specify the solver "engine" that vsim will select for constrained random -; generation. -; Valid values are: -; "auto" - automatically select the best engine for the current -; constraint scenario -; "bdd" - evaluate all constraint scenarios using the BDD solver engine -; "act" - evaluate all constraint scenarios using the ACT solver engine -; While the BDD solver engine is generally efficient with constraint scenarios -; involving bitwise logical relationships, the ACT solver engine can exhibit -; superior performance with constraint scenarios involving large numbers of -; random variables related via arithmetic operators (+, *, etc). -; NOTE: This variable can be overridden with the vsim "-solveengine" command -; line switch. -; The default value is "auto". -; SolveEngine = auto - -; Specifies the maximum size that a dynamic array may be resized to by the -; solver. If the solver attempts to resize a dynamic array to a size greater -; than the specified limit, the solver will abort with an error. -; The default value is 10000. A value of 0 indicates no limit. -; SolveArrayResizeMax = 10000 - -; Specify error message severity when randomize() and randomize(null) failures -; are detected. -; -; Integer value up to two digits are allowed with each digit having the following legal values: -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; -; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents -; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit) -; represents the setting for randomize(null) calls. -; -; 2) When a single digit value is used, the setting is applied to both normal randomize() call -; and randomize(null) call. -; -; Example: Fatal error for randomize() failures and NO error for randomize(null) failures -; -solvefailseverity=40 -; -; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is -; enabled, a constraint contradiction report will be displayed for randomize() calls that -; have a message severity >= warning (i.e. constraint contradiction reports will not be -; generated for randomize() calls having a "no error" severity level) -; -; NOTE: This variable can be overridden with the vsim "-solvefailseverity" command -; line switch. -; -; The default is 1 (warning). -; SolveFailSeverity = 1 - -; Error message severity for suppressible errors that are detected in a -; solve/before constraint. -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" -; command line switch. -; The default is 3 (failure). -; SolveBeforeErrorSeverity = 3 - -; Error message severity for suppressible errors that are related to -; solve engine capacity limits -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" -; command line switch. -; The default is 3 (failure). -; SolveEngineErrorSeverity = 3 - -; Enable/disable constraint conflicts on randomize() failure -; Valid values: -; 0 - disable solvefaildebug -; 1 - basic debug (no performance penalty) -; 2 - enhanced debug (runtime performance penalty) -; -; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is -; enabled, a constraint contradiction report will be displayed for randomize() calls that -; have a message severity >= warning (i.e. constraint contradiction reports will not be -; generated for randomize() calls having a "no error" severity level) -; -; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command -; line switch. -; -; The default is 1 (basic debug). -; SolveFailDebug = 1 - -; Upon encountering a randomize() failure, generate a simplified testcase that -; will reproduce the failure. Optionally output the testcase to a file. -; Testcases for 'no-solution' failures will only be produced if SolveFailDebug -; is enabled (see above). -; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" -; command line switch. -; The default is OFF (do not generate a testcase). To enable testcase -; generation, uncomment this variable. To redirect testcase generation to a -; file, specify the name of the output file. -; SolveFailTestcase = - -; Specify solver timeout threshold (in seconds). randomize() will fail if the -; CPU time required to evaluate any randset exceeds the specified timeout. -; The default value is 500. A value of 0 will disable timeout failures. -; SolveTimeout = 500 - -; Specify the alternative behavior during solver replay. Must be used when combined with -solvereplay switch. -; SolveReplayOpt=[+|-][,[+|-]]*" -' Valid settings: -; validate : toggle the checking of value changes of non-random variables involved in randomize(). (default is off)" -; SolveReplayOpt=validate - -; Specify the maximum size of the solution graph generated by the BDD solver. -; This value can be used to force the BDD solver to abort the evaluation of a -; complex constraint scenario that cannot be evaluated with finite memory. -; This value is specified in 1000s of nodes. -; The default value is 10000. A value of 0 indicates no limit. -; SolveGraphMaxSize = 10000 - -; Specify the maximum number of evaluations that may be performed on the -; solution graph by the BDD solver. This value can be used to force the BDD -; solver to abort the evaluation of a complex constraint scenario that cannot -; be evaluated in finite time. This value is specified in 10000s of evaluations. -; The default value is 10000. A value of 0 indicates no limit. -; SolveGraphMaxEval = 10000 - -; Specify random sequence compatiblity with a prior release. This -; option is used to get the same random sequences during simulation as -; as a prior release. Only prior releases with the same major version -; as the current release are allowed. -; NOTE: Only those random sequence changes due to solver optimizations are -; reverted by this variable. Random sequence changes due to solver bugfixes -; cannot be un-done. -; NOTE: This variable can be overridden with the vsim "-solverev" command -; line switch. -; Default value set to "" (no compatibility). -; SolveRev = - -; Environment variable expansion of command line arguments has been depricated -; in favor shell level expansion. Universal environment variable expansion -; inside -f files is support and continued support for MGC Location Maps provide -; alternative methods for handling flexible pathnames. -; The following line may be uncommented and the value set to 1 to re-enable this -; deprecated behavior. The default value is 0. -; DeprecatedEnvironmentVariableExpansion = 0 - -; Specify the memory threshold for the System Verilog garbage collector. -; The value is the number of megabytes of class objects that must accumulate -; before the garbage collector is run. -; The GCThreshold setting is used when class debug mode is disabled to allow -; less frequent garbage collection and better simulation performance. -; The GCThresholdClassDebug setting is used when class debug mode is enabled -; to allow for more frequent garbage collection. -; GCThreshold = 100 -; GCThresholdClassDebug = 5 - -; Turn on/off collapsing of bus ports in VCD dumpports output -DumpportsCollapse = 1 - -; Location of Multi-Level Verification Component (MVC) installation. -; The default location is the product installation directory. -MvcHome = $QUESTA_MVC_HOME - -; Location of InFact installation. The default is $MODEL_TECH/../../infact -; -; InFactHome = $MODEL_TECH/../../infact - -; Initialize SystemVerilog enums using the base type's default value -; instead of the leftmost value. -; EnumBaseInit = 1 - -; Suppress file type registration. -; SuppressFileTypeReg = 1 - -; Enable/disable non-LRM compliant SystemVerilog language extensions. -; Valid extensions are: -; altdpiheader - Alternative style function signature generated in DPI header", -; cfce - generate an error if $cast fails as a function -; cfmt - C like formatting for specifiers with '#' prefix ('%#x', '%#h') -; dfsp - sets default format specifier as %p, if no format specifier is given for unpacked array in $display and related systasks -; expdfmt - enable format string extensions for $display/$sformatf -; extscan - support values greater than 32 bit for string builtin methods (atohex, atobin, atooct, atoi) -; fmtcap - prints capital hex digits with %X/%H in display calls -; iddp - ignore DPI disable protocol check -; lfmt - zero-pad data if '0' prefixes width in format specifier (e.g. "%04h") -; noexptc - ignore DPI export type name overloading check -; realrand - support randomize() with real variables and constraints (Default) -; SvExtensions = [+|-][,[+|-]*] - -; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions. -; Valid extensions are: -; arraymode - consider rand_mode of unpacked array field independently from its elements -; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles (Default) -; funcback - enable function backtracking (ACT only) -; genmodseedfix - enable LRM-compliant seeding of module/interface instances under for-generate blocks (Default) -; nodist - interpret 'dist' constraint as 'inside' (ACT only) -; noorder - ignore solve/before ordering constraints (ACT only) -; pathseed - enable unique seeding of module instances based on hierarchical path name -; prerandfirst - execute all pre_randomize() functions before evaluating any constraints -; promotedist - promote priority of 'dist' constraint if LHS has no solve/before -; purecheck - suppress pre_randomize() and post_randomize() calls for randomize(null) -; randindex - allow random index in constraint (Default) -; randstruct - consider all fields of unpacked structs as 'rand' -; skew - skew randomize results (ACT only) -; strictstab - strict random stability -; SvRandExtensions = [+|-][,[+|-]*] - -; Controls the formatting of '%p' and '%P' conversion specification, used in $display -; and similar system tasks. -; 1. SVPrettyPrintFlags=I use spaces(S) or tabs(T) per indentation level. -; The 'I' flag when present causes relevant data types to be expanded and indented into -; a more readable format. -; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). -; 2. SVPrettyPrintFlags=L limits the output to lines. -; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). -; 3. SVPrettyPrintFlags=C limits the output to characters. -; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). -; 4. SVPrettyPrintFlags=F limits the output to of relevant datatypes -; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). -; 5. SVPrettyPrintFlags=E limits the output to of relevant datatypes -; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). -; 6. SVPrettyPrintFlags=D suppresses the output of sub-elements below . -; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). -; 7. SVPrettyPrintFlags=R shows the output of specifier %p as per the specifed radix. -; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)). -; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format. -; 8. Items 1-7 above can be combined as a comma separated list. -; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb) -; SVPrettyPrintFlags=I4S - -[lmc] -; The simulator's interface to Logic Modeling's SmartModel SWIFT software -libsm = $MODEL_TECH/libsm.sl -; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) -; libsm = $MODEL_TECH/libsm.dll -; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) -; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl -; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) -; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o -; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) -; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so -; Logic Modeling's SmartModel SWIFT software (Windows NT) -; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll -; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) -; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so -; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) -; libswift = $LMC_HOME/lib/linux.lib/libswift.so - -; The simulator's interface to Logic Modeling's hardware modeler SFI software -libhm = $MODEL_TECH/libhm.sl -; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) -; libhm = $MODEL_TECH/libhm.dll -; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) -; libsfi = /lib/hp700/libsfi.sl -; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) -; libsfi = /lib/rs6000/libsfi.a -; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) -; libsfi = /lib/sun4.solaris/libsfi.so -; Logic Modeling's hardware modeler SFI software (Windows NT) -; libsfi = /lib/pcnt/lm_sfi.dll -; Logic Modeling's hardware modeler SFI software (Linux) -; libsfi = /lib/linux/libsfi.so - -[msg_system] -; Change a message severity or suppress a message. -; The format is: = [,...] -; suppress can be used to achieve +nowarn functionality -; The format is: suppress = ,,[,,...] -; Examples: -suppress = 8780 ;an explanation can be had by running: verror 8780 -; note = 3009 -; warning = 3033 -; error = 3010,3016 -; fatal = 3016,3033 -; suppress = 3009,3016,3601 -; suppress = 3009,CNNODP,3601,TFMPC -; suppress = 8683,8684 -; The command verror can be used to get the complete -; description of a message. - -; Control transcripting of Verilog display system task messages and -; PLI/FLI print function call messages. The system tasks include -; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They -; also include the analogous file I/O tasks that write to STDOUT -; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, -; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default -; is to have messages appear only in the transcript. The other -; settings are to send messages to the wlf file only (messages that -; are recorded in the wlf file can be viewed in the MsgViewer) or -; to both the transcript and the wlf file. The valid values are -; tran {transcript only (default)} -; wlf {wlf file only} -; both {transcript and wlf file} -; displaymsgmode = tran - -; Control transcripting of elaboration/runtime messages not -; addressed by the displaymsgmode setting. The default is to -; have messages appear only in the transcript. The other settings -; are to send messages to the wlf file only (messages that are -; recorded in the wlf file can be viewed in the MsgViewer) or to both -; the transcript and the wlf file. The valid values are -; tran {transcript only (default)} -; wlf {wlf file only} -; both {transcript and wlf file} -; msgmode = tran - -; Controls number of displays of a particluar message -; default value is 5 -; MsgLimitCount = 5 - -[utils] -; Default Library Type (while creating a library with "vlib") -; 0 - legacy library using subdirectories for design units -; 2 - flat library -; DefaultLibType = 2 - -; Flat Library Page Size (while creating a library with "vlib") -; Set the size in bytes for flat library file pages. Libraries containing -; very large files may benefit from a larger value. -; FlatLibPageSize = 8192 - -; Flat Library Page Cleanup Percentage (while creating a library with "vlib") -; Set the percentage of total pages deleted before library cleanup can occur. -; This setting is applied together with FlatLibPageDeleteThreshold. -; FlatLibPageDeletePercentage = 50 - -; Flat Library Page Cleanup Threshold (while creating a library with "vlib") -; Set the number of pages deleted before library cleanup can occur. -; This setting is applied together with FlatLibPageDeletePercentage. -; FlatLibPageDeleteThreshold = 1000 - - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/simulate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/simulate.do deleted file mode 100644 index 1afd7fb0..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/simulate.do +++ /dev/null @@ -1,16 +0,0 @@ -onbreak {quit -f} -onerror {quit -f} - -vsim -voptargs="+acc" -t 1ps -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.GaussFir_12m xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure -view signals - -do {GaussFir_12m.udo} - -run -all - -quit -force diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/wave.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/modelsim/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/GaussFir_12m.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/GaussFir_12m.coe deleted file mode 100644 index c70ab501..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/GaussFir_12m.coe +++ /dev/null @@ -1,20 +0,0 @@ -Radix=10; -Coefficient_Width=16; -CoefData= -3 -19 -97 -366 -1052 -2321 -3999 -5485 -6082 -5485 -3999 -2321 -1052 -366 -97 -19 -3 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/GaussFir_12m.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/GaussFir_12m.mif deleted file mode 100644 index 7033a867..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/GaussFir_12m.mif +++ /dev/null @@ -1,20 +0,0 @@ -00000003 0 0 0 0 0 0 -00000013 0 0 0 0 1 0 -00000061 0 0 0 0 2 0 -0000016e 0 0 0 0 3 0 -0000041c 0 1 0 0 4 0 -00000911 0 1 0 0 5 0 -00000f9f 0 1 0 0 6 0 -0000156d 0 1 0 0 7 0 -000017c2 0 2 0 0 8 0 -0000156d 0 2 0 0 9 0 -00000f9f 0 2 0 0 10 0 -00000911 0 2 0 0 11 0 -0000041c 0 3 0 0 12 0 -0000016e 0 3 0 0 13 0 -00000061 0 3 0 0 14 0 -00000013 0 3 0 0 15 0 -00000003 0 4 0 0 16 0 -00000000 0 4 0 0 17 0 -00000000 0 4 0 0 18 0 -00000000 0 4 0 0 19 0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/GaussFir_12m.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/GaussFir_12m.sh deleted file mode 100644 index 4982fbd1..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/GaussFir_12m.sh +++ /dev/null @@ -1,175 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : GaussFir_12m.sh -# Simulator : Mentor Graphics Questa Advanced Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:36:27 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: GaussFir_12m.sh [-help] -# usage: GaussFir_12m.sh [-lib_map_path] -# usage: GaussFir_12m.sh [-noclean_files] -# usage: GaussFir_12m.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'GaussFir_12m.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "GaussFir_12m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -elaborate() -{ - source elaborate.do 2>&1 | tee -a elaborate.log -} - -# RUN_STEP: -simulate() -{ - vsim -64 -c -do "do {simulate.do}" -l simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./GaussFir_12m.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Copy modelsim.ini file -copy_setup_file() -{ - file="modelsim.ini" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then - lib_map_path="$1" - else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - cp $src_file . - fi -} - -# Create design library directory -create_lib_dir() -{ - lib_dir="questa_lib" - if [[ -e $lib_dir ]]; then - rm -rf $lib_dir - fi - - mkdir $lib_dir - -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./GaussFir_12m.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: GaussFir_12m.sh [-help]\n\ -Usage: GaussFir_12m.sh [-lib_map_path]\n\ -Usage: GaussFir_12m.sh [-reset_run]\n\ -Usage: GaussFir_12m.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/GaussFir_12m.udo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/GaussFir_12m.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/README.txt deleted file mode 100644 index e937a880..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:36:27 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./GaussFir_12m.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './GaussFir_12m.sh' script. - -./GaussFir_12m.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./GaussFir_12m.sh -noclean_files - -For more information on the script, please type './GaussFir_12m.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/compile.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/compile.do deleted file mode 100644 index 0fd54656..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/compile.do +++ /dev/null @@ -1,37 +0,0 @@ -vlib questa_lib/work -vlib questa_lib/msim - -vlib questa_lib/msim/xil_defaultlib -vlib questa_lib/msim/xpm -vlib questa_lib/msim/xbip_utils_v3_0_10 -vlib questa_lib/msim/axi_utils_v2_0_6 -vlib questa_lib/msim/fir_compiler_v7_2_12 - -vmap xil_defaultlib questa_lib/msim/xil_defaultlib -vmap xpm questa_lib/msim/xpm -vmap xbip_utils_v3_0_10 questa_lib/msim/xbip_utils_v3_0_10 -vmap axi_utils_v2_0_6 questa_lib/msim/axi_utils_v2_0_6 -vmap fir_compiler_v7_2_12 questa_lib/msim/fir_compiler_v7_2_12 - -vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/GaussFir_12m/cmodel" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -64 -93 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vcom -work xbip_utils_v3_0_10 -64 -93 \ -"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ - -vcom -work axi_utils_v2_0_6 -64 -93 \ -"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ - -vcom -work fir_compiler_v7_2_12 -64 -93 \ -"../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ - -vcom -work xil_defaultlib -64 -93 \ -"../../../ip/GaussFir_12m/sim/GaussFir_12m.vhd" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/elaborate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/elaborate.do deleted file mode 100644 index 9e49e4fe..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/elaborate.do +++ /dev/null @@ -1 +0,0 @@ -vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.GaussFir_12m xil_defaultlib.glbl -o GaussFir_12m_opt diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/file_info.txt deleted file mode 100644 index febe2aeb..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/file_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/GaussFir_12m/cmodel" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/GaussFir_12m/cmodel" -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -GaussFir_12m.vhd,vhdl,xil_defaultlib,../../../ip/GaussFir_12m/sim/GaussFir_12m.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/simulate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/simulate.do deleted file mode 100644 index 67dd6f5f..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/simulate.do +++ /dev/null @@ -1,16 +0,0 @@ -onbreak {quit -f} -onerror {quit -f} - -vsim -t 1ps -lib xil_defaultlib GaussFir_12m_opt - -do {wave.do} - -view wave -view structure -view signals - -do {GaussFir_12m.udo} - -run -all - -quit -force diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/wave.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/questa/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/GaussFir_12m.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/GaussFir_12m.coe deleted file mode 100644 index c70ab501..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/GaussFir_12m.coe +++ /dev/null @@ -1,20 +0,0 @@ -Radix=10; -Coefficient_Width=16; -CoefData= -3 -19 -97 -366 -1052 -2321 -3999 -5485 -6082 -5485 -3999 -2321 -1052 -366 -97 -19 -3 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/GaussFir_12m.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/GaussFir_12m.mif deleted file mode 100644 index 7033a867..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/GaussFir_12m.mif +++ /dev/null @@ -1,20 +0,0 @@ -00000003 0 0 0 0 0 0 -00000013 0 0 0 0 1 0 -00000061 0 0 0 0 2 0 -0000016e 0 0 0 0 3 0 -0000041c 0 1 0 0 4 0 -00000911 0 1 0 0 5 0 -00000f9f 0 1 0 0 6 0 -0000156d 0 1 0 0 7 0 -000017c2 0 2 0 0 8 0 -0000156d 0 2 0 0 9 0 -00000f9f 0 2 0 0 10 0 -00000911 0 2 0 0 11 0 -0000041c 0 3 0 0 12 0 -0000016e 0 3 0 0 13 0 -00000061 0 3 0 0 14 0 -00000013 0 3 0 0 15 0 -00000003 0 4 0 0 16 0 -00000000 0 4 0 0 17 0 -00000000 0 4 0 0 18 0 -00000000 0 4 0 0 19 0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/GaussFir_12m.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/GaussFir_12m.sh deleted file mode 100644 index c53d77ac..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/GaussFir_12m.sh +++ /dev/null @@ -1,154 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : GaussFir_12m.sh -# Simulator : Aldec Riviera-PRO Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:36:27 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: GaussFir_12m.sh [-help] -# usage: GaussFir_12m.sh [-lib_map_path] -# usage: GaussFir_12m.sh [-noclean_files] -# usage: GaussFir_12m.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'GaussFir_12m.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "GaussFir_12m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - runvsimsa -l simulate.log -do "do {simulate.do}" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./GaussFir_12m.sh -help\" for more information)\n" - exit 1 - fi - map_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - map_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Map library.cfg file -map_setup_file() -{ - file="library.cfg" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then - lib_map_path="$1" - else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - vmap -link $lib_map_path - fi - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./GaussFir_12m.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: GaussFir_12m.sh [-help]\n\ -Usage: GaussFir_12m.sh [-lib_map_path]\n\ -Usage: GaussFir_12m.sh [-reset_run]\n\ -Usage: GaussFir_12m.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/GaussFir_12m.udo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/GaussFir_12m.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/README.txt deleted file mode 100644 index e937a880..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:36:27 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./GaussFir_12m.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './GaussFir_12m.sh' script. - -./GaussFir_12m.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./GaussFir_12m.sh -noclean_files - -For more information on the script, please type './GaussFir_12m.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/compile.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/compile.do deleted file mode 100644 index 20f83f24..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/compile.do +++ /dev/null @@ -1,37 +0,0 @@ -vlib work -vlib riviera - -vlib riviera/xil_defaultlib -vlib riviera/xpm -vlib riviera/xbip_utils_v3_0_10 -vlib riviera/axi_utils_v2_0_6 -vlib riviera/fir_compiler_v7_2_12 - -vmap xil_defaultlib riviera/xil_defaultlib -vmap xpm riviera/xpm -vmap xbip_utils_v3_0_10 riviera/xbip_utils_v3_0_10 -vmap axi_utils_v2_0_6 riviera/axi_utils_v2_0_6 -vmap fir_compiler_v7_2_12 riviera/fir_compiler_v7_2_12 - -vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/GaussFir_12m/cmodel" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -93 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vcom -work xbip_utils_v3_0_10 -93 \ -"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ - -vcom -work axi_utils_v2_0_6 -93 \ -"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ - -vcom -work fir_compiler_v7_2_12 -93 \ -"../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ - -vcom -work xil_defaultlib -93 \ -"../../../ip/GaussFir_12m/sim/GaussFir_12m.vhd" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/file_info.txt deleted file mode 100644 index febe2aeb..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/file_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/GaussFir_12m/cmodel" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/GaussFir_12m/cmodel" -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -GaussFir_12m.vhd,vhdl,xil_defaultlib,../../../ip/GaussFir_12m/sim/GaussFir_12m.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/simulate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/simulate.do deleted file mode 100644 index d7ffdd4f..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/simulate.do +++ /dev/null @@ -1,17 +0,0 @@ -onbreak {quit -force} -onerror {quit -force} - -asim -t 1ps +access +r +m+GaussFir_12m -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.GaussFir_12m xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure - -do {GaussFir_12m.udo} - -run -all - -endsim - -quit -force diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/wave.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/riviera/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/GaussFir_12m.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/GaussFir_12m.coe deleted file mode 100644 index c70ab501..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/GaussFir_12m.coe +++ /dev/null @@ -1,20 +0,0 @@ -Radix=10; -Coefficient_Width=16; -CoefData= -3 -19 -97 -366 -1052 -2321 -3999 -5485 -6082 -5485 -3999 -2321 -1052 -366 -97 -19 -3 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/GaussFir_12m.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/GaussFir_12m.mif deleted file mode 100644 index 7033a867..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/GaussFir_12m.mif +++ /dev/null @@ -1,20 +0,0 @@ -00000003 0 0 0 0 0 0 -00000013 0 0 0 0 1 0 -00000061 0 0 0 0 2 0 -0000016e 0 0 0 0 3 0 -0000041c 0 1 0 0 4 0 -00000911 0 1 0 0 5 0 -00000f9f 0 1 0 0 6 0 -0000156d 0 1 0 0 7 0 -000017c2 0 2 0 0 8 0 -0000156d 0 2 0 0 9 0 -00000f9f 0 2 0 0 10 0 -00000911 0 2 0 0 11 0 -0000041c 0 3 0 0 12 0 -0000016e 0 3 0 0 13 0 -00000061 0 3 0 0 14 0 -00000013 0 3 0 0 15 0 -00000003 0 4 0 0 16 0 -00000000 0 4 0 0 17 0 -00000000 0 4 0 0 18 0 -00000000 0 4 0 0 19 0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/GaussFir_12m.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/GaussFir_12m.sh deleted file mode 100644 index c7b9a8de..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/GaussFir_12m.sh +++ /dev/null @@ -1,241 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : GaussFir_12m.sh -# Simulator : Synopsys Verilog Compiler Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:36:27 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: GaussFir_12m.sh [-help] -# usage: GaussFir_12m.sh [-lib_map_path] -# usage: GaussFir_12m.sh [-noclean_files] -# usage: GaussFir_12m.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'GaussFir_12m.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Command line options -vlogan_opts="-full64" -vhdlan_opts="-full64" -vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" -vcs_sim_opts="-ucli -licqueue -l simulate.log" - -# Design libraries -design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 fir_compiler_v7_2_12) - -# Simulation root library directory -sim_lib_dir="vcs_lib" - -# Script info -echo -e "GaussFir_12m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ip/GaussFir_12m/cmodel" \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - 2>&1 | tee -a vlogan.log - - vhdlan -work xpm $vhdlan_opts \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - 2>&1 | tee -a vhdlan.log - - vhdlan -work xbip_utils_v3_0_10 $vhdlan_opts \ - "$ref_dir/../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ - 2>&1 | tee -a vhdlan.log - - vhdlan -work axi_utils_v2_0_6 $vhdlan_opts \ - "$ref_dir/../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ - 2>&1 | tee -a vhdlan.log - - vhdlan -work fir_compiler_v7_2_12 $vhdlan_opts \ - "$ref_dir/../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ - 2>&1 | tee -a vhdlan.log - - vhdlan -work xil_defaultlib $vhdlan_opts \ - "$ref_dir/../../../ip/GaussFir_12m/sim/GaussFir_12m.vhd" \ - 2>&1 | tee -a vhdlan.log - - - vlogan -work xil_defaultlib $vlogan_opts +v2k \ - glbl.v \ - 2>&1 | tee -a vlogan.log - -} - -# RUN_STEP: -elaborate() -{ - vcs $vcs_elab_opts xil_defaultlib.GaussFir_12m xil_defaultlib.glbl -o GaussFir_12m_simv -} - -# RUN_STEP: -simulate() -{ - ./GaussFir_12m_simv $vcs_sim_opts -do simulate.do -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./GaussFir_12m.sh -help\" for more information)\n" - exit 1 - fi - create_lib_mappings $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - create_lib_mappings $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Define design library mappings -create_lib_mappings() -{ - file="synopsys_sim.setup" - if [[ -e $file ]]; then - if [[ ($1 == "") ]]; then - return - else - rm -rf $file - fi - fi - - touch $file - - lib_map_path="" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - mapping="$lib:$sim_lib_dir/$lib" - echo $mapping >> $file - done - - if [[ ($lib_map_path != "") ]]; then - incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" - echo $incl_ref >> $file - fi -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(ucli.key GaussFir_12m_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc GaussFir_12m_simv.daidir) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./GaussFir_12m.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: GaussFir_12m.sh [-help]\n\ -Usage: GaussFir_12m.sh [-lib_map_path]\n\ -Usage: GaussFir_12m.sh [-reset_run]\n\ -Usage: GaussFir_12m.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/README.txt deleted file mode 100644 index e937a880..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:36:27 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./GaussFir_12m.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './GaussFir_12m.sh' script. - -./GaussFir_12m.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./GaussFir_12m.sh -noclean_files - -For more information on the script, please type './GaussFir_12m.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/file_info.txt deleted file mode 100644 index febe2aeb..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/file_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/GaussFir_12m/cmodel" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/GaussFir_12m/cmodel" -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -GaussFir_12m.vhd,vhdl,xil_defaultlib,../../../ip/GaussFir_12m/sim/GaussFir_12m.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/simulate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/simulate.do deleted file mode 100644 index 58afc787..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/vcs/simulate.do +++ /dev/null @@ -1,2 +0,0 @@ -run -quit diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/GaussFir_12m.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/GaussFir_12m.coe deleted file mode 100644 index c70ab501..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/GaussFir_12m.coe +++ /dev/null @@ -1,20 +0,0 @@ -Radix=10; -Coefficient_Width=16; -CoefData= -3 -19 -97 -366 -1052 -2321 -3999 -5485 -6082 -5485 -3999 -2321 -1052 -366 -97 -19 -3 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/GaussFir_12m.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/GaussFir_12m.mif deleted file mode 100644 index 7033a867..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/GaussFir_12m.mif +++ /dev/null @@ -1,20 +0,0 @@ -00000003 0 0 0 0 0 0 -00000013 0 0 0 0 1 0 -00000061 0 0 0 0 2 0 -0000016e 0 0 0 0 3 0 -0000041c 0 1 0 0 4 0 -00000911 0 1 0 0 5 0 -00000f9f 0 1 0 0 6 0 -0000156d 0 1 0 0 7 0 -000017c2 0 2 0 0 8 0 -0000156d 0 2 0 0 9 0 -00000f9f 0 2 0 0 10 0 -00000911 0 2 0 0 11 0 -0000041c 0 3 0 0 12 0 -0000016e 0 3 0 0 13 0 -00000061 0 3 0 0 14 0 -00000013 0 3 0 0 15 0 -00000003 0 4 0 0 16 0 -00000000 0 4 0 0 17 0 -00000000 0 4 0 0 18 0 -00000000 0 4 0 0 19 0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/GaussFir_12m.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/GaussFir_12m.sh deleted file mode 100644 index a957b61c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/GaussFir_12m.sh +++ /dev/null @@ -1,176 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : GaussFir_12m.sh -# Simulator : Cadence Xcelium Parallel Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:36:27 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: GaussFir_12m.sh [-help] -# usage: GaussFir_12m.sh [-lib_map_path] -# usage: GaussFir_12m.sh [-noclean_files] -# usage: GaussFir_12m.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'GaussFir_12m.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Set the compiled library directory -ref_lib_dir="." - -# Command line options -xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" - -# Design libraries -design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 fir_compiler_v7_2_12) - -# Simulation root library directory -sim_lib_dir="xcelium_lib" - -# Script info -echo -e "GaussFir_12m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - execute -} - -# RUN_STEP: -execute() -{ - xrun $xrun_opts \ - -reflib "$ref_lib_dir/unisim:unisim" \ - -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ - -reflib "$ref_lib_dir/secureip:secureip" \ - -reflib "$ref_lib_dir/unimacro:unimacro" \ - -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.GaussFir_12m \ - -f run.f \ - -top glbl \ - glbl.v \ - +incdir+"../../../ip/GaussFir_12m/cmodel" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./GaussFir_12m.sh -help\" for more information)\n" - exit 1 - else - ref_lib_dir=$2 - fi - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./GaussFir_12m.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: GaussFir_12m.sh [-help]\n\ -Usage: GaussFir_12m.sh [-lib_map_path]\n\ -Usage: GaussFir_12m.sh [-reset_run]\n\ -Usage: GaussFir_12m.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/README.txt deleted file mode 100644 index b56b3160..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/README.txt +++ /dev/null @@ -1,48 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:36:27 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./GaussFir_12m.sh - -This command will launch the 'execute' function for the single-step flow. This -function is called from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './GaussFir_12m.sh' script. - -./GaussFir_12m.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./GaussFir_12m.sh -noclean_files - -For more information on the script, please type './GaussFir_12m.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/file_info.txt deleted file mode 100644 index febe2aeb..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/file_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/GaussFir_12m/cmodel" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/GaussFir_12m/cmodel" -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -GaussFir_12m.vhd,vhdl,xil_defaultlib,../../../ip/GaussFir_12m/sim/GaussFir_12m.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/run.f b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/run.f deleted file mode 100644 index 8fa18876..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xcelium/run.f +++ /dev/null @@ -1,23 +0,0 @@ --makelib xcelium_lib/xil_defaultlib -sv \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ --endlib --makelib xcelium_lib/xpm \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ --endlib --makelib xcelium_lib/xbip_utils_v3_0_10 \ - "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ --endlib --makelib xcelium_lib/axi_utils_v2_0_6 \ - "../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ --endlib --makelib xcelium_lib/fir_compiler_v7_2_12 \ - "../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ --endlib --makelib xcelium_lib/xil_defaultlib \ - "../../../ip/GaussFir_12m/sim/GaussFir_12m.vhd" \ --endlib --makelib xcelium_lib/xil_defaultlib \ - glbl.v --endlib - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/GaussFir_12m.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/GaussFir_12m.coe deleted file mode 100644 index c70ab501..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/GaussFir_12m.coe +++ /dev/null @@ -1,20 +0,0 @@ -Radix=10; -Coefficient_Width=16; -CoefData= -3 -19 -97 -366 -1052 -2321 -3999 -5485 -6082 -5485 -3999 -2321 -1052 -366 -97 -19 -3 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/GaussFir_12m.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/GaussFir_12m.mif deleted file mode 100644 index 7033a867..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/GaussFir_12m.mif +++ /dev/null @@ -1,20 +0,0 @@ -00000003 0 0 0 0 0 0 -00000013 0 0 0 0 1 0 -00000061 0 0 0 0 2 0 -0000016e 0 0 0 0 3 0 -0000041c 0 1 0 0 4 0 -00000911 0 1 0 0 5 0 -00000f9f 0 1 0 0 6 0 -0000156d 0 1 0 0 7 0 -000017c2 0 2 0 0 8 0 -0000156d 0 2 0 0 9 0 -00000f9f 0 2 0 0 10 0 -00000911 0 2 0 0 11 0 -0000041c 0 3 0 0 12 0 -0000016e 0 3 0 0 13 0 -00000061 0 3 0 0 14 0 -00000013 0 3 0 0 15 0 -00000003 0 4 0 0 16 0 -00000000 0 4 0 0 17 0 -00000000 0 4 0 0 18 0 -00000000 0 4 0 0 19 0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/GaussFir_12m.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/GaussFir_12m.sh deleted file mode 100644 index e8c92c77..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/GaussFir_12m.sh +++ /dev/null @@ -1,214 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : GaussFir_12m.sh -# Simulator : Xilinx Vivado Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:36:27 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: GaussFir_12m.sh [-help] -# usage: GaussFir_12m.sh [-lib_map_path] -# usage: GaussFir_12m.sh [-noclean_files] -# usage: GaussFir_12m.sh [-reset_run] -# -#********************************************************************************************************* - -# Command line options -xv_boost_lib_path=C:/Xilinx/Vivado/2019.1/tps/boost_1_64_0 -xvlog_opts="--relax" -xvhdl_opts="--relax" - - -# Script info -echo -e "GaussFir_12m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log - xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log - -} - -# RUN_STEP: -elaborate() -{ - xelab --relax --debug typical --mt auto -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot GaussFir_12m xil_defaultlib.GaussFir_12m xil_defaultlib.glbl -log elaborate.log -} - -# RUN_STEP: -simulate() -{ - xsim GaussFir_12m -key {Behavioral:sim_1:Functional:GaussFir_12m} -tclbatch cmd.tcl -log simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./GaussFir_12m.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Copy xsim.ini file -copy_setup_file() -{ - file="xsim.ini" - lib_map_path="C:/Xilinx/Vivado/2019.1/data/xsim" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - cp $src_file . - fi - - # Map local design libraries to xsim.ini - map_local_libs - - fi -} - -# Map local design libraries -map_local_libs() -{ - updated_mappings=() - local_mappings=() - - # Local design libraries - local_libs=() - - if [[ 0 == ${#local_libs[@]} ]]; then - return - fi - - file="xsim.ini" - file_backup="xsim.ini.bak" - - if [[ -e $file ]]; then - rm -f $file_backup - # Create a backup copy of the xsim.ini file - cp $file $file_backup - # Read libraries from backup file and search in local library collection - while read -r line - do - IN=$line - # Split mapping entry with '=' delimiter to fetch library name and mapping - read lib_name mapping <<<$(IFS="="; echo $IN) - # If local library found, then construct the local mapping and add to local mapping collection - if `echo ${local_libs[@]} | grep -wq $lib_name` ; then - line="$lib_name=xsim.dir/$lib_name" - local_mappings+=("$lib_name") - fi - # Add to updated library mapping collection - updated_mappings+=("$line") - done < "$file_backup" - # Append local libraries not found originally from xsim.ini - for (( i=0; i<${#local_libs[*]}; i++ )); do - lib_name="${local_libs[i]}" - if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then - line="$lib_name=xsim.dir/$lib_name" - updated_mappings+=("$line") - fi - done - # Write updated mappings in xsim.ini - rm -f $file - for (( i=0; i<${#updated_mappings[*]}; i++ )); do - lib_name="${updated_mappings[i]}" - echo $lib_name >> $file - done - else - for (( i=0; i<${#local_libs[*]}; i++ )); do - lib_name="${local_libs[i]}" - mapping="$lib_name=xsim.dir/$lib_name" - echo $mapping >> $file - done - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb GaussFir_12m.wdb xsim.dir) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./GaussFir_12m.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: GaussFir_12m.sh [-help]\n\ -Usage: GaussFir_12m.sh [-lib_map_path]\n\ -Usage: GaussFir_12m.sh [-reset_run]\n\ -Usage: GaussFir_12m.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/README.txt deleted file mode 100644 index e937a880..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:36:27 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./GaussFir_12m.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './GaussFir_12m.sh' script. - -./GaussFir_12m.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./GaussFir_12m.sh -noclean_files - -For more information on the script, please type './GaussFir_12m.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/cmd.tcl b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/cmd.tcl deleted file mode 100644 index eef7a0f0..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/cmd.tcl +++ /dev/null @@ -1,12 +0,0 @@ -set curr_wave [current_wave_config] -if { [string length $curr_wave] == 0 } { - if { [llength [get_objects]] > 0} { - add_wave / - set_property needs_save false [current_wave_config] - } else { - send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." - } -} - -run -all -quit diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/elab.opt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/elab.opt deleted file mode 100644 index 08756545..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/elab.opt +++ /dev/null @@ -1 +0,0 @@ ---relax --debug typical --mt auto -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot GaussFir_12m xil_defaultlib.GaussFir_12m xil_defaultlib.glbl -log elaborate.log diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/file_info.txt deleted file mode 100644 index 7d7a858c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/file_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -GaussFir_12m.vhd,vhdl,xil_defaultlib,../../../ip/GaussFir_12m/sim/GaussFir_12m.vhd,incdir="../../../ip/GaussFir_12m/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/vhdl.prj b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/vhdl.prj deleted file mode 100644 index 1dd93329..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/vhdl.prj +++ /dev/null @@ -1,4 +0,0 @@ -vhdl xil_defaultlib \ -"../../../ip/GaussFir_12m/sim/GaussFir_12m.vhd" \ - -nosort diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/vlog.prj b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/vlog.prj deleted file mode 100644 index 35119d5b..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/vlog.prj +++ /dev/null @@ -1,4 +0,0 @@ - -verilog xil_defaultlib "glbl.v" - -nosort diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/xsim.ini b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/xsim.ini deleted file mode 100644 index 6cb07f57..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_12m/xsim/xsim.ini +++ /dev/null @@ -1,430 +0,0 @@ -std=$RDI_DATADIR/xsim/vhdl/std -ieee=$RDI_DATADIR/xsim/vhdl/ieee -ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed -vl=$RDI_DATADIR/xsim/vhdl/vl -synopsys=$RDI_DATADIR/xsim/vhdl/synopsys -secureip=$RDI_DATADIR/xsim/verilog/secureip -unisim=$RDI_DATADIR/xsim/vhdl/unisim -unimacro=$RDI_DATADIR/xsim/vhdl/unimacro -unifast=$RDI_DATADIR/xsim/vhdl/unifast -unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver -unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver -unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver -simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver -system_cache_v4_0_6=$RDI_DATADIR/xsim/ip/system_cache_v4_0_6 -bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0 -g709_rs_decoder_v2_2_8=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_8 -xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0 -mipi_dphy_v4_1_4=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_1_4 -iomodule_v3_1_4=$RDI_DATADIR/xsim/ip/iomodule_v3_1_4 -ieee802d3_50g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_11 -common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0 -lte_fft_v2_1_0=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_0 -ieee802d3_50g_rs_fec_v2_0_1=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_1 -convolution_v9_0_14=$RDI_DATADIR/xsim/ip/convolution_v9_0_14 -gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4 -v_cfa_v7_0_14=$RDI_DATADIR/xsim/ip/v_cfa_v7_0_14 -axi4svideo_bridge_v1_0_10=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_10 -pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11 -v_vscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_13 -xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6 -gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux -ethernet_1_10_25g_v2_2_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_2_3 -zynq_ultra_ps_e_v3_3_0=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_0 -v_cresample_v4_0_14=$RDI_DATADIR/xsim/ip/v_cresample_v4_0_14 -v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9 -v_scenechange_v1_0_1=$RDI_DATADIR/xsim/ip/v_scenechange_v1_0_1 -hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0 -ahblite_axi_bridge_v3_0_14=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_14 -tri_mode_ethernet_mac_v9_0_14=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_14 -blk_mem_gen_v8_4_3=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_3 -noc_mc_ddr4_phy_v1_0_0=$RDI_DATADIR/xsim/ip/noc_mc_ddr4_phy_v1_0_0 -axi_data_fifo_v2_1_18=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_18 -axi_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_5 -ethernet_1_10_25g_v2_0_5=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_0_5 -compact_gt_v1_0_5=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_5 -axi_gpio_v2_0_21=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_21 -qdma_v3_0_2=$RDI_DATADIR/xsim/ip/qdma_v3_0_2 -viterbi_v9_1_11=$RDI_DATADIR/xsim/ip/viterbi_v9_1_11 -sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2 -ba317=$RDI_DATADIR/xsim/ip/ba317 -xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4 -fifo_generator_v13_2_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_4 -axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14 -vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0 -axi_emc_v3_0_19=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_19 -cmac_v2_5_1=$RDI_DATADIR/xsim/ip/cmac_v2_5_1 -floating_point_v7_1_8=$RDI_DATADIR/xsim/ip/floating_point_v7_1_8 -xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6 -vid_phy_controller_v2_2_3=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_3 -common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1 -axi_firewall_v1_0_7=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_7 -util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1 -axis_accelerator_adapter_v2_1_15=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_15 -tmr_comparator_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_2 -sd_fec_v1_0_2=$RDI_DATADIR/xsim/ip/sd_fec_v1_0_2 -tmr_manager_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_4 -tsn_temac_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_4 -usxgmii_v1_0_5=$RDI_DATADIR/xsim/ip/usxgmii_v1_0_5 -lte_dl_channel_encoder_v4_0_0=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v4_0_0 -ai_noc=$RDI_DATADIR/xsim/ip/ai_noc -lte_3gpp_mimo_decoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_15 -v_uhdsdi_audio_v1_0_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_0_0 -axi4stream_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_5 -cmac_usplus_v2_4_5=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_4_5 -etrnic_v1_1_2=$RDI_DATADIR/xsim/ip/etrnic_v1_1_2 -floating_point_v7_0_16=$RDI_DATADIR/xsim/ip/floating_point_v7_0_16 -axi_dma_v7_1_20=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_20 -jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi -axi_traffic_gen_v3_0_5=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_5 -emb_mem_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_1 -axi_amm_bridge_v1_0_9=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_9 -axi_datamover_v5_1_21=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_21 -v_axi4s_vid_out_v4_0_10=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_10 -jesd204_v7_2_6=$RDI_DATADIR/xsim/ip/jesd204_v7_2_6 -v_letterbox_v1_0_13=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_13 -interlaken_v2_4_3=$RDI_DATADIR/xsim/ip/interlaken_v2_4_3 -uhdsdi_gt_v2_0_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_0 -axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7 -rst_vip_v1_0_3=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_3 -audio_formatter_v1_0_1=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_1 -lte_3gpp_channel_estimator_v2_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_16 -v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13 -g709_fec_v2_3_5=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_5 -xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6 -axi_chip2chip_v5_0_6=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_6 -fc32_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_11 -v_mix_v3_0_3=$RDI_DATADIR/xsim/ip/v_mix_v3_0_3 -multi_channel_25g_rs_fec_v1_0_5=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_5 -in_system_ibert_v1_0_9=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_9 -ethernet_1_10_25g_v2_1_4=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_1_4 -axis_broadcaster_v1_1_18=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_18 -axis_combiner_v1_1_17=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_17 -axi_apb_bridge_v3_0_15=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_15 -displayport_v9_0_1=$RDI_DATADIR/xsim/ip/displayport_v9_0_1 -clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2 -hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1 -axi_register_slice_v2_1_19=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_19 -vid_phy_controller_v2_1_5=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_5 -picxo=$RDI_DATADIR/xsim/ip/picxo -usxgmii_v1_1_0=$RDI_DATADIR/xsim/ip/usxgmii_v1_1_0 -v_vcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_13 -bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0 -prc_v1_3_2=$RDI_DATADIR/xsim/ip/prc_v1_3_2 -axi_usb2_device_v5_0_20=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_20 -lte_3gpp_mimo_encoder_v4_0_14=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_14 -l_ethernet_v2_5_2=$RDI_DATADIR/xsim/ip/l_ethernet_v2_5_2 -xdma_v4_1_3=$RDI_DATADIR/xsim/ip/xdma_v4_1_3 -axis_vio_v1_0_0=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_0 -c_counter_binary_v12_0_13=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_13 -noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0 -xbip_dsp48_macro_v3_0_17=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_17 -c_accum_v12_0_13=$RDI_DATADIR/xsim/ip/c_accum_v12_0_13 -xbip_multadd_v3_0_14=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_14 -axi_uartlite_v2_0_23=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_23 -noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0 -axi_intc_v4_1_13=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_13 -i2s_transmitter_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_3 -pc_cfr_v6_0_8=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_8 -mutex_v2_1_10=$RDI_DATADIR/xsim/ip/mutex_v2_1_10 -c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6 -sid_v8_0_14=$RDI_DATADIR/xsim/ip/sid_v8_0_14 -fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6 -quadsgmii_v3_4_6=$RDI_DATADIR/xsim/ip/quadsgmii_v3_4_6 -microblaze_v11_0_1=$RDI_DATADIR/xsim/ip/microblaze_v11_0_1 -lib_bmg_v1_0_12=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_12 -dds_compiler_v6_0_18=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_18 -me_pl_v1_0=$RDI_DATADIR/xsim/ip/me_pl_v1_0 -gtwizard_ultrascale_v1_7_6=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_6 -axis_clock_converter_v1_1_20=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_20 -nvmeha_v1_0_0=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_0 -tmr_inject_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_3 -axi_mcdma_v1_1_0=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_0 -axi_hwicap_v3_0_23=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_23 -v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0 -v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0 -canfd_v2_0_1=$RDI_DATADIR/xsim/ip/canfd_v2_0_1 -gig_ethernet_pcs_pma_v16_1_6=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_6 -lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2 -ieee802d3_rs_fec_v2_0_5=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_5 -ibert_lib_v1_0_6=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_6 -high_speed_selectio_wiz_v3_4_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_1 -xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6 -fec_5g_common_v1_0_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_1 -tmr_voter_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_2 -hdmi_gt_controller_v1_0_0=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_0 -axi_traffic_gen_v2_0_20=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_20 -flexo_100g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_11 -v_smpte_uhdsdi_v1_0_7=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_7 -xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6 -fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10 -ieee802d3_rs_fec_v1_0_15=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_15 -axis_subset_converter_v1_1_19=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_19 -noc_nmu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_v1_0_0 -duc_ddc_compiler_v3_0_15=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_15 -dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13 -mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0 -ieee802d3_200g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_7 -sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1 -mrmac_v1_0_0=$RDI_DATADIR/xsim/ip/mrmac_v1_0_0 -sem_ultra_v3_1_11=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_11 -v_tpg_v8_0_1=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_1 -axi_tft_v2_0_22=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_22 -ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13 -switch_core_top_v1_0_7=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_7 -rama_v1_1_2_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_2_lib -v_hcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_13 -emb_fifo_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_1 -hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3 -axis_data_fifo_v2_0_1=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_1 -hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0 -rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1 -displayport_v8_1_1=$RDI_DATADIR/xsim/ip/displayport_v8_1_1 -axi_mmu_v2_1_17=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_17 -proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13 -pc_cfr_v6_3_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_3_0 -v_osd_v6_0_16=$RDI_DATADIR/xsim/ip/v_osd_v6_0_16 -pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12 -xfft_v9_0_17=$RDI_DATADIR/xsim/ip/xfft_v9_0_17 -axi_cdma_v4_1_19=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_19 -audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0 -lib_fifo_v1_0_13=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_13 -v_enhance_v8_0_15=$RDI_DATADIR/xsim/ip/v_enhance_v8_0_15 -axi_clock_converter_v2_1_18=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_18 -xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0 -emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5 -axi_mm2s_mapper_v1_1_18=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_18 -xfft_v7_2_9=$RDI_DATADIR/xsim/ip/xfft_v7_2_9 -pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0 -v_smpte_sdi_v3_0_8=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_8 -fir_compiler_v7_2_12=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_12 -div_gen_v5_1_15=$RDI_DATADIR/xsim/ip/div_gen_v5_1_15 -mdm_v3_2_16=$RDI_DATADIR/xsim/ip/mdm_v3_2_16 -v_axi4s_remap_v1_0_11=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_11 -xxv_ethernet_v2_5_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_5_3 -xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2 -ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig -remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4 -pr_axi_shutdown_manager_v1_0_1=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_1 -axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0 -smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0 -axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib -axi_dwidth_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_19 -xlconstant_v1_1_6=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_6 -tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6 -mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2 -v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1 -axi_fifo_mm_s_v4_2_1=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_1 -util_idelay_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_1 -rs_toolbox_v9_0_7=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_7 -v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0 -dsp_macro_v1_0_0=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_0 -pc_cfr_v6_2_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_2 -axi_timer_v2_0_21=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_21 -high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1 -axi_sideband_util_v1_0_3=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_3 -sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2 -gmii_to_rgmii_v4_0_7=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_0_7 -xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2 -high_speed_selectio_wiz_v3_5_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_5_1 -axi_msg_v1_0_5=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_5 -axi_ahblite_bridge_v3_0_16=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_16 -v_rgb2ycrcb_v7_1_13=$RDI_DATADIR/xsim/ip/v_rgb2ycrcb_v7_1_13 -v_mix_v4_0_0=$RDI_DATADIR/xsim/ip/v_mix_v4_0_0 -axi_ethernetlite_v3_0_17=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_17 -axi_uart16550_v2_0_21=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_21 -axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0 -vfb_v1_0_13=$RDI_DATADIR/xsim/ip/vfb_v1_0_13 -advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0 -ats_switch_v1_0_2=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_2 -interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4 -axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub -cpri_v8_10_3=$RDI_DATADIR/xsim/ip/cpri_v8_10_3 -c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6 -v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0 -stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0 -rld3_pl_v1_0_1=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_1 -ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0 -lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0 -axi_epc_v2_0_22=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_22 -g709_rs_encoder_v2_2_6=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_6 -blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6 -tmr_sem_v1_0_9=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_9 -fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6 -axi_vdma_v6_3_7=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_7 -axis_data_fifo_v1_1_20=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_20 -xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip -axi_ethernet_buffer_v2_0_20=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_20 -rs_encoder_v9_0_15=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_15 -axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0 -ta_dma_v1_0_3=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_3 -tcc_encoder_3gpp_v5_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_15 -axi_perf_mon_v5_0_21=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_21 -noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0 -sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1 -lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2 -v_csc_v1_0_13=$RDI_DATADIR/xsim/ip/v_csc_v1_0_13 -shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0 -lte_fft_v2_0_18=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_18 -gtwizard_ultrascale_v1_6_11=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_11 -amm_axi_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_5 -mii_to_rmii_v2_0_21=$RDI_DATADIR/xsim/ip/mii_to_rmii_v2_0_21 -videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5 -audio_clock_recovery_v1_0=$RDI_DATADIR/xsim/ip/audio_clock_recovery_v1_0 -cmac_v2_4_1=$RDI_DATADIR/xsim/ip/cmac_v2_4_1 -i2s_receiver_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_3 -v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0 -v_demosaic_v1_0_5=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_5 -remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4 -microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4 -hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3 -etrnic_v1_0_3=$RDI_DATADIR/xsim/ip/etrnic_v1_0_3 -xfft_v9_1_2=$RDI_DATADIR/xsim/ip/xfft_v9_1_2 -ddr4_pl_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_2 -xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6 -cmac_usplus_v2_5_3=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_5_3 -jesd204c_v4_1_1=$RDI_DATADIR/xsim/ip/jesd204c_v4_1_1 -debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1 -axis_protocol_checker_v2_0_3=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_3 -v_frmbuf_wr_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_2 -v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9 -mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4 -lte_dl_channel_encoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_15 -axi_protocol_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_19 -xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0 -clk_gen_sim_v1_0_0=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_0 -axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0 -microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7 -cmpy_v6_0_17=$RDI_DATADIR/xsim/ip/cmpy_v6_0_17 -cmac_v2_3_5=$RDI_DATADIR/xsim/ip/cmac_v2_3_5 -ieee802d3_400g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_7 -xxv_ethernet_v2_4_5=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_4_5 -axi_timebase_wdt_v3_0_11=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_11 -tcc_decoder_3gppmm_v2_0_18=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_18 -v_deinterlacer_v5_0_13=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_13 -dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16 -axi_fifo_mm_s_v4_1_16=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_16 -processing_system7_vip_v1_0_7=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_7 -g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18 -rs_decoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_16 -c_shift_ram_v12_0_13=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_13 -displayport_v7_0_11=$RDI_DATADIR/xsim/ip/displayport_v7_0_11 -v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0 -v_deinterlacer_v4_0_12=$RDI_DATADIR/xsim/ip/v_deinterlacer_v4_0_12 -sem_v4_1_12=$RDI_DATADIR/xsim/ip/sem_v4_1_12 -xaui_v12_3_6=$RDI_DATADIR/xsim/ip/xaui_v12_3_6 -ten_gig_eth_mac_v15_1_7=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_7 -oddr_v1_0_0=$RDI_DATADIR/xsim/ip/oddr_v1_0_0 -c_addsub_v12_0_13=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_13 -v_ccm_v6_0_15=$RDI_DATADIR/xsim/ip/v_ccm_v6_0_15 -zynq_ultra_ps_e_vip_v1_0_5=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_5 -cic_compiler_v4_0_14=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_14 -c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6 -axi_memory_init_v1_0_0=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_0 -pr_decoupler_v1_0_7=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_7 -timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4 -lte_pucch_receiver_v2_0_16=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_16 -zynq_ultra_ps_e_v3_2_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_3 -v_gamma_lut_v1_0_5=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_5 -bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0 -pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0 -tcc_encoder_3gpplte_v4_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_15 -polar_v1_0_3=$RDI_DATADIR/xsim/ip/polar_v1_0_3 -rxaui_v4_4_6=$RDI_DATADIR/xsim/ip/rxaui_v4_4_6 -xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6 -v_gamma_v7_0_15=$RDI_DATADIR/xsim/ip/v_gamma_v7_0_15 -ernic_v1_0_1=$RDI_DATADIR/xsim/ip/ernic_v1_0_1 -high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3 -mailbox_v2_1_11=$RDI_DATADIR/xsim/ip/mailbox_v2_1_11 -video_frame_crc_v1_0_1=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_1 -axi_sg_v4_1_12=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_12 -ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0 -lmb_bram_if_cntlr_v4_0_16=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_16 -l_ethernet_v2_4_3=$RDI_DATADIR/xsim/ip/l_ethernet_v2_4_3 -dft_v4_1_1=$RDI_DATADIR/xsim/ip/dft_v4_1_1 -rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0 -axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6 -v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0 -stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0 -lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0 -uhdsdi_gt_v1_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_3 -pc_cfr_v6_1_4=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_4 -lmb_v10_v3_0_9=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_9 -axis_interconnect_v1_1_17=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_17 -cordic_v6_0_15=$RDI_DATADIR/xsim/ip/cordic_v6_0_15 -axis_register_slice_v1_1_19=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_19 -axis_switch_v1_1_19=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_19 -axi_interconnect_v1_7_16=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_16 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-c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6 -g709_fec_v2_4_1=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_1 -lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0 -ai_pl=$RDI_DATADIR/xsim/ip/ai_pl -fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4 -v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0 -l_ethernet_v2_3_5=$RDI_DATADIR/xsim/ip/l_ethernet_v2_3_5 -microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6 -v_uhdsdi_audio_v2_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_1 -ldpc_v2_0_3=$RDI_DATADIR/xsim/ip/ldpc_v2_0_3 -xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6 -xpm=$RDI_DATADIR/xsim/ip/xpm -srio_gen2_v4_1_6=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_6 -g975_efec_i4_v1_0_17=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_17 -noc_na_v1_0_0=$RDI_DATADIR/xsim/ip/noc_na_v1_0_0 -roe_framer_v2_0_1=$RDI_DATADIR/xsim/ip/roe_framer_v2_0_1 -xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10 -generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0 -ten_gig_eth_pcs_pma_v6_0_15=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_15 -can_v5_0_22=$RDI_DATADIR/xsim/ip/can_v5_0_22 -av_pat_gen_v1_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_0 -fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1 -lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0 -axis_dwidth_converter_v1_1_18=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_18 -lte_rach_detector_v3_1_5=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_5 -xxv_ethernet_v3_0_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v3_0_3 -axi_iic_v2_0_22=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_22 -axi_pcie_v2_9_1=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_1 -util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4 -sim_trig_top_v1_0=$RDI_DATADIR/xsim/ip/sim_trig_top_v1_0 -v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0 -v_tpg_v7_0_13=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_13 -sd_fec_v1_1_3=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_3 -xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6 -lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2 -v_multi_scaler_v1_0_1=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_0_1 -axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0 -advanced_io_wizard_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_0 -mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8 -axi_pcie3_v3_0_9=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_9 -axi_vfifo_ctrl_v2_0_21=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_21 -xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/README.txt deleted file mode 100644 index f3d66c82..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/README.txt +++ /dev/null @@ -1,83 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required -# to simulate the design for a simulator, the directory structure -# and the generated exported files. -# -################################################################################ - -1. Simulate Design - -To simulate design, cd to the simulator directory and execute the script. - -For example:- - -% cd questa -% ./top.sh - -The export simulation flow requires the Xilinx pre-compiled simulation library -components for the target simulator. These components are referred using the -'-lib_map_path' switch. If this switch is specified, then the export simulation -will automatically set this library path in the generated script and update, -copy the simulator setup file(s) in the exported directory. - -If '-lib_map_path' is not specified, then the pre-compiled simulation library -information will not be included in the exported scripts and that may cause -simulation errors when running this script. Alternatively, you can provide the -library information using this switch while executing the generated script. - -For example:- - -% ./top.sh -lib_map_path /design/questa/clibs - -Please refer to the generated script header 'Prerequisite' section for more details. - -2. Directory Structure - -By default, if the -directory switch is not specified, export_simulation will -create the following directory structure:- - -/export_sim/ - -For example, if the current working directory is /tmp/test, export_simulation -will create the following directory path:- - -/tmp/test/export_sim/questa - -If -directory switch is specified, export_simulation will create a simulator -sub-directory under the specified directory path. - -For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' -command will create the following directory:- - -/tmp/test/my_test_area/func_sim/questa - -By default, if -simulator is not specified, export_simulation will create a -simulator sub-directory for each simulator and export the files for each simulator -in this sub-directory respectively. - -IMPORTANT: Please note that the simulation library path must be specified manually -in the generated script for the respective simulator. Please refer to the generated -script header 'Prerequisite' section for more details. - -3. Exported script and files - -Export simulation will create the driver shell script, setup files and copy the -design sources in the output directory path. - -By default, when the -script_name switch is not specified, export_simulation will -create the following script name:- - -.sh (Unix) -When exporting the files for an IP using the -of_objects switch, export_simulation -will create the following script name:- - -.sh (Unix) -Export simulation will create the setup files for the target simulator specified -with the -simulator switch. - -For example, if the target simulator is "ies", export_simulation will create the -'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' -file. - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/GaussFir_1mp5.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/GaussFir_1mp5.mif deleted file mode 100644 index 647b490c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/GaussFir_1mp5.mif +++ /dev/null @@ -1,160 +0,0 @@ -00000000 0 0 0 0 0 0 -00000000 0 0 0 0 1 0 -00000001 0 0 0 0 2 0 -00000001 0 0 0 0 3 0 -00000001 0 0 0 0 4 0 -00000001 0 0 0 0 5 0 -00000002 0 0 0 0 6 0 -00000002 0 0 0 0 7 0 -00000002 0 0 0 0 8 0 -00000003 0 0 0 0 9 0 -00000004 0 0 0 0 10 0 -00000005 0 0 0 0 11 0 -00000006 0 0 0 0 12 0 -00000007 0 0 0 0 13 0 -00000008 0 0 0 0 14 0 -0000000a 0 0 0 0 15 0 -0000000c 0 0 0 0 16 0 -0000000e 0 0 0 0 17 0 -00000011 0 0 0 0 18 0 -00000015 0 0 0 0 19 0 -00000018 0 0 0 0 20 0 -0000001d 0 0 0 0 21 0 -00000022 0 0 0 0 22 0 -00000027 0 0 0 0 23 0 -0000002e 0 0 0 0 24 0 -00000035 0 0 0 0 25 0 -0000003d 0 0 0 0 26 0 -00000046 0 0 0 0 27 0 -00000050 0 0 0 0 28 0 -0000005b 0 0 0 0 29 0 -00000068 0 0 0 0 30 0 -00000075 0 0 0 0 31 0 -00000084 0 1 0 0 32 0 -00000093 0 1 0 0 33 0 -000000a4 0 1 0 0 34 0 -000000b6 0 1 0 0 35 0 -000000ca 0 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3 0 0 122 0 -00000001 0 3 0 0 123 0 -00000001 0 3 0 0 124 0 -00000001 0 3 0 0 125 0 -00000001 0 3 0 0 126 0 -00000000 0 3 0 0 127 0 -00000000 0 4 0 0 128 0 -00000000 0 4 0 0 129 0 -00000000 0 4 0 0 130 0 -00000000 0 4 0 0 131 0 -00000000 0 4 0 0 132 0 -00000000 0 4 0 0 133 0 -00000000 0 4 0 0 134 0 -00000000 0 4 0 0 135 0 -00000000 0 4 0 0 136 0 -00000000 0 4 0 0 137 0 -00000000 0 4 0 0 138 0 -00000000 0 4 0 0 139 0 -00000000 0 4 0 0 140 0 -00000000 0 4 0 0 141 0 -00000000 0 4 0 0 142 0 -00000000 0 4 0 0 143 0 -00000000 0 4 0 0 144 0 -00000000 0 4 0 0 145 0 -00000000 0 4 0 0 146 0 -00000000 0 4 0 0 147 0 -00000000 0 4 0 0 148 0 -00000000 0 4 0 0 149 0 -00000000 0 4 0 0 150 0 -00000000 0 4 0 0 151 0 -00000000 0 4 0 0 152 0 -00000000 0 4 0 0 153 0 -00000000 0 4 0 0 154 0 -00000000 0 4 0 0 155 0 -00000000 0 4 0 0 156 0 -00000000 0 4 0 0 157 0 -00000000 0 4 0 0 158 0 -00000000 0 4 0 0 159 0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/GaussFir_1mp5.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/GaussFir_1mp5.sh deleted file mode 100644 index 31c281d9..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/GaussFir_1mp5.sh +++ /dev/null @@ -1,154 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : GaussFir_1mp5.sh -# Simulator : Aldec Active-HDL Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:36:16 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: GaussFir_1mp5.sh [-help] -# usage: GaussFir_1mp5.sh [-lib_map_path] -# usage: GaussFir_1mp5.sh [-noclean_files] -# usage: GaussFir_1mp5.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'GaussFir_1mp5.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "GaussFir_1mp5.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - runvsimsa -l simulate.log -do "do {simulate.do}" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./GaussFir_1mp5.sh -help\" for more information)\n" - exit 1 - fi - map_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - map_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Map library.cfg file -map_setup_file() -{ - file="library.cfg" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then - lib_map_path="$1" - else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - vmap -link $lib_map_path - fi - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./GaussFir_1mp5.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: GaussFir_1mp5.sh [-help]\n\ -Usage: GaussFir_1mp5.sh [-lib_map_path]\n\ -Usage: GaussFir_1mp5.sh [-reset_run]\n\ -Usage: GaussFir_1mp5.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/GaussFir_1mp5.udo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/GaussFir_1mp5.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/Gaussfir_1p5m.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/Gaussfir_1p5m.coe deleted file mode 100644 index 9fa4e7e5..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/Gaussfir_1p5m.coe +++ /dev/null @@ -1,132 +0,0 @@ -Radix=10; -Coefficient_Width=16; -CoefData= -0 -0 -1 -1 -1 -1 -2 -2 -2 -3 -4 -5 -6 -7 -8 -10 -12 -14 -17 -21 -24 -29 -34 -39 -46 -53 -61 -70 -80 -91 -104 -117 -132 -147 -164 -182 -202 -222 -244 -267 -290 -315 -340 -366 -392 -419 -446 -473 -500 -526 -552 -577 -602 -625 -647 -667 -686 -702 -717 -730 -741 -749 -755 -759 -760 -759 -755 -749 -741 -730 -717 -702 -686 -667 -647 -625 -602 -577 -552 -526 -500 -473 -446 -419 -392 -366 -340 -315 -290 -267 -244 -222 -202 -182 -164 -147 -132 -117 -104 -91 -80 -70 -61 -53 -46 -39 -34 -29 -24 -21 -17 -14 -12 -10 -8 -7 -6 -5 -4 -3 -2 -2 -2 -1 -1 -1 -1 -0 -0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/README.txt deleted file mode 100644 index 775767b0..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:36:16 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./GaussFir_1mp5.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './GaussFir_1mp5.sh' script. - -./GaussFir_1mp5.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./GaussFir_1mp5.sh -noclean_files - -For more information on the script, please type './GaussFir_1mp5.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/compile.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/compile.do deleted file mode 100644 index 0e143fce..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/compile.do +++ /dev/null @@ -1,37 +0,0 @@ -vlib work -vlib activehdl - -vlib activehdl/xil_defaultlib -vlib activehdl/xpm -vlib activehdl/xbip_utils_v3_0_10 -vlib activehdl/axi_utils_v2_0_6 -vlib activehdl/fir_compiler_v7_2_12 - -vmap xil_defaultlib activehdl/xil_defaultlib -vmap xpm activehdl/xpm -vmap xbip_utils_v3_0_10 activehdl/xbip_utils_v3_0_10 -vmap axi_utils_v2_0_6 activehdl/axi_utils_v2_0_6 -vmap fir_compiler_v7_2_12 activehdl/fir_compiler_v7_2_12 - -vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/GaussFir_1mp5/cmodel" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -93 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vcom -work xbip_utils_v3_0_10 -93 \ -"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ - -vcom -work axi_utils_v2_0_6 -93 \ -"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ - -vcom -work fir_compiler_v7_2_12 -93 \ -"../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ - -vcom -work xil_defaultlib -93 \ -"../../../ip/GaussFir_1mp5/sim/GaussFir_1mp5.vhd" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/file_info.txt deleted file mode 100644 index 800f64df..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/file_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/GaussFir_1mp5/cmodel" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/GaussFir_1mp5/cmodel" -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -GaussFir_1mp5.vhd,vhdl,xil_defaultlib,../../../ip/GaussFir_1mp5/sim/GaussFir_1mp5.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/simulate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/simulate.do deleted file mode 100644 index 909b3769..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/simulate.do +++ /dev/null @@ -1,17 +0,0 @@ -onbreak {quit -force} -onerror {quit -force} - -asim -t 1ps +access +r +m+GaussFir_1mp5 -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.GaussFir_1mp5 xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure - -do {GaussFir_1mp5.udo} - -run -all - -endsim - -quit -force diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/wave.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/activehdl/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/GaussFir_1mp5.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/GaussFir_1mp5.mif deleted file mode 100644 index 647b490c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/GaussFir_1mp5.mif +++ /dev/null @@ -1,160 +0,0 @@ -00000000 0 0 0 0 0 0 -00000000 0 0 0 0 1 0 -00000001 0 0 0 0 2 0 -00000001 0 0 0 0 3 0 -00000001 0 0 0 0 4 0 -00000001 0 0 0 0 5 0 -00000002 0 0 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4 0 0 135 0 -00000000 0 4 0 0 136 0 -00000000 0 4 0 0 137 0 -00000000 0 4 0 0 138 0 -00000000 0 4 0 0 139 0 -00000000 0 4 0 0 140 0 -00000000 0 4 0 0 141 0 -00000000 0 4 0 0 142 0 -00000000 0 4 0 0 143 0 -00000000 0 4 0 0 144 0 -00000000 0 4 0 0 145 0 -00000000 0 4 0 0 146 0 -00000000 0 4 0 0 147 0 -00000000 0 4 0 0 148 0 -00000000 0 4 0 0 149 0 -00000000 0 4 0 0 150 0 -00000000 0 4 0 0 151 0 -00000000 0 4 0 0 152 0 -00000000 0 4 0 0 153 0 -00000000 0 4 0 0 154 0 -00000000 0 4 0 0 155 0 -00000000 0 4 0 0 156 0 -00000000 0 4 0 0 157 0 -00000000 0 4 0 0 158 0 -00000000 0 4 0 0 159 0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/GaussFir_1mp5.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/GaussFir_1mp5.sh deleted file mode 100644 index 9d45ce0f..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/GaussFir_1mp5.sh +++ /dev/null @@ -1,176 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : GaussFir_1mp5.sh -# Simulator : Cadence Incisive Enterprise Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:36:16 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: GaussFir_1mp5.sh [-help] -# usage: GaussFir_1mp5.sh [-lib_map_path] -# usage: GaussFir_1mp5.sh [-noclean_files] -# usage: GaussFir_1mp5.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'GaussFir_1mp5.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Set the compiled library directory -ref_lib_dir="." - -# Command line options -irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" - -# Design libraries -design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 fir_compiler_v7_2_12) - -# Simulation root library directory -sim_lib_dir="ies_lib" - -# Script info -echo -e "GaussFir_1mp5.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - execute -} - -# RUN_STEP: -execute() -{ - irun $irun_opts \ - -reflib "$ref_lib_dir/unisim:unisim" \ - -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ - -reflib "$ref_lib_dir/secureip:secureip" \ - -reflib "$ref_lib_dir/unimacro:unimacro" \ - -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.GaussFir_1mp5 \ - -f run.f \ - -top glbl \ - glbl.v \ - +incdir+"../../../ip/GaussFir_1mp5/cmodel" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./GaussFir_1mp5.sh -help\" for more information)\n" - exit 1 - else - ref_lib_dir=$2 - fi - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./GaussFir_1mp5.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: GaussFir_1mp5.sh [-help]\n\ -Usage: GaussFir_1mp5.sh [-lib_map_path]\n\ -Usage: GaussFir_1mp5.sh [-reset_run]\n\ -Usage: GaussFir_1mp5.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/Gaussfir_1p5m.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/Gaussfir_1p5m.coe deleted file mode 100644 index 9fa4e7e5..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/Gaussfir_1p5m.coe +++ /dev/null @@ -1,132 +0,0 @@ -Radix=10; -Coefficient_Width=16; -CoefData= -0 -0 -1 -1 -1 -1 -2 -2 -2 -3 -4 -5 -6 -7 -8 -10 -12 -14 -17 -21 -24 -29 -34 -39 -46 -53 -61 -70 -80 -91 -104 -117 -132 -147 -164 -182 -202 -222 -244 -267 -290 -315 -340 -366 -392 -419 -446 -473 -500 -526 -552 -577 -602 -625 -647 -667 -686 -702 -717 -730 -741 -749 -755 -759 -760 -759 -755 -749 -741 -730 -717 -702 -686 -667 -647 -625 -602 -577 -552 -526 -500 -473 -446 -419 -392 -366 -340 -315 -290 -267 -244 -222 -202 -182 -164 -147 -132 -117 -104 -91 -80 -70 -61 -53 -46 -39 -34 -29 -24 -21 -17 -14 -12 -10 -8 -7 -6 -5 -4 -3 -2 -2 -2 -1 -1 -1 -1 -0 -0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/README.txt deleted file mode 100644 index c1c0d5df..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/README.txt +++ /dev/null @@ -1,48 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:36:16 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./GaussFir_1mp5.sh - -This command will launch the 'execute' function for the single-step flow. This -function is called from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './GaussFir_1mp5.sh' script. - -./GaussFir_1mp5.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./GaussFir_1mp5.sh -noclean_files - -For more information on the script, please type './GaussFir_1mp5.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/file_info.txt deleted file mode 100644 index 800f64df..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/file_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/GaussFir_1mp5/cmodel" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/GaussFir_1mp5/cmodel" -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -GaussFir_1mp5.vhd,vhdl,xil_defaultlib,../../../ip/GaussFir_1mp5/sim/GaussFir_1mp5.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/run.f b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/run.f deleted file mode 100644 index c45564c6..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/ies/run.f +++ /dev/null @@ -1,23 +0,0 @@ --makelib ies_lib/xil_defaultlib -sv \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ --endlib --makelib ies_lib/xpm \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ --endlib --makelib ies_lib/xbip_utils_v3_0_10 \ - "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ --endlib --makelib ies_lib/axi_utils_v2_0_6 \ - "../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ --endlib --makelib ies_lib/fir_compiler_v7_2_12 \ - "../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ --endlib --makelib ies_lib/xil_defaultlib \ - "../../../ip/GaussFir_1mp5/sim/GaussFir_1mp5.vhd" \ --endlib --makelib ies_lib/xil_defaultlib \ - glbl.v --endlib - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/GaussFir_1mp5.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/GaussFir_1mp5.mif deleted file mode 100644 index 647b490c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/GaussFir_1mp5.mif +++ /dev/null @@ -1,160 +0,0 @@ -00000000 0 0 0 0 0 0 -00000000 0 0 0 0 1 0 -00000001 0 0 0 0 2 0 -00000001 0 0 0 0 3 0 -00000001 0 0 0 0 4 0 -00000001 0 0 0 0 5 0 -00000002 0 0 0 0 6 0 -00000002 0 0 0 0 7 0 -00000002 0 0 0 0 8 0 -00000003 0 0 0 0 9 0 -00000004 0 0 0 0 10 0 -00000005 0 0 0 0 11 0 -00000006 0 0 0 0 12 0 -00000007 0 0 0 0 13 0 -00000008 0 0 0 0 14 0 -0000000a 0 0 0 0 15 0 -0000000c 0 0 0 0 16 0 -0000000e 0 0 0 0 17 0 -00000011 0 0 0 0 18 0 -00000015 0 0 0 0 19 0 -00000018 0 0 0 0 20 0 -0000001d 0 0 0 0 21 0 -00000022 0 0 0 0 22 0 -00000027 0 0 0 0 23 0 -0000002e 0 0 0 0 24 0 -00000035 0 0 0 0 25 0 -0000003d 0 0 0 0 26 0 -00000046 0 0 0 0 27 0 -00000050 0 0 0 0 28 0 -0000005b 0 0 0 0 29 0 -00000068 0 0 0 0 30 0 -00000075 0 0 0 0 31 0 -00000084 0 1 0 0 32 0 -00000093 0 1 0 0 33 0 -000000a4 0 1 0 0 34 0 -000000b6 0 1 0 0 35 0 -000000ca 0 1 0 0 36 0 -000000de 0 1 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3 0 0 123 0 -00000001 0 3 0 0 124 0 -00000001 0 3 0 0 125 0 -00000001 0 3 0 0 126 0 -00000000 0 3 0 0 127 0 -00000000 0 4 0 0 128 0 -00000000 0 4 0 0 129 0 -00000000 0 4 0 0 130 0 -00000000 0 4 0 0 131 0 -00000000 0 4 0 0 132 0 -00000000 0 4 0 0 133 0 -00000000 0 4 0 0 134 0 -00000000 0 4 0 0 135 0 -00000000 0 4 0 0 136 0 -00000000 0 4 0 0 137 0 -00000000 0 4 0 0 138 0 -00000000 0 4 0 0 139 0 -00000000 0 4 0 0 140 0 -00000000 0 4 0 0 141 0 -00000000 0 4 0 0 142 0 -00000000 0 4 0 0 143 0 -00000000 0 4 0 0 144 0 -00000000 0 4 0 0 145 0 -00000000 0 4 0 0 146 0 -00000000 0 4 0 0 147 0 -00000000 0 4 0 0 148 0 -00000000 0 4 0 0 149 0 -00000000 0 4 0 0 150 0 -00000000 0 4 0 0 151 0 -00000000 0 4 0 0 152 0 -00000000 0 4 0 0 153 0 -00000000 0 4 0 0 154 0 -00000000 0 4 0 0 155 0 -00000000 0 4 0 0 156 0 -00000000 0 4 0 0 157 0 -00000000 0 4 0 0 158 0 -00000000 0 4 0 0 159 0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/GaussFir_1mp5.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/GaussFir_1mp5.sh deleted file mode 100644 index 47de49c6..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/GaussFir_1mp5.sh +++ /dev/null @@ -1,167 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : GaussFir_1mp5.sh -# Simulator : Mentor Graphics ModelSim Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:36:16 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: GaussFir_1mp5.sh [-help] -# usage: GaussFir_1mp5.sh [-lib_map_path] -# usage: GaussFir_1mp5.sh [-noclean_files] -# usage: GaussFir_1mp5.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'GaussFir_1mp5.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "GaussFir_1mp5.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - vsim -64 -c -do "do {simulate.do}" -l simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./GaussFir_1mp5.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Copy modelsim.ini file -copy_setup_file() -{ - file="modelsim.ini" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - else - lib_map_path="C:/Mentor/CompLib/2019.1.3" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - cp $src_file . - fi -} - -# Create design library directory -create_lib_dir() -{ - lib_dir="modelsim_lib" - if [[ -e $lib_dir ]]; then - rm -rf $lib_dir - fi - - mkdir $lib_dir - -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./GaussFir_1mp5.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: GaussFir_1mp5.sh [-help]\n\ -Usage: GaussFir_1mp5.sh [-lib_map_path]\n\ -Usage: GaussFir_1mp5.sh [-reset_run]\n\ -Usage: GaussFir_1mp5.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/GaussFir_1mp5.udo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/GaussFir_1mp5.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/Gaussfir_1p5m.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/Gaussfir_1p5m.coe deleted file mode 100644 index 9fa4e7e5..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/Gaussfir_1p5m.coe +++ /dev/null @@ -1,132 +0,0 @@ -Radix=10; -Coefficient_Width=16; -CoefData= -0 -0 -1 -1 -1 -1 -2 -2 -2 -3 -4 -5 -6 -7 -8 -10 -12 -14 -17 -21 -24 -29 -34 -39 -46 -53 -61 -70 -80 -91 -104 -117 -132 -147 -164 -182 -202 -222 -244 -267 -290 -315 -340 -366 -392 -419 -446 -473 -500 -526 -552 -577 -602 -625 -647 -667 -686 -702 -717 -730 -741 -749 -755 -759 -760 -759 -755 -749 -741 -730 -717 -702 -686 -667 -647 -625 -602 -577 -552 -526 -500 -473 -446 -419 -392 -366 -340 -315 -290 -267 -244 -222 -202 -182 -164 -147 -132 -117 -104 -91 -80 -70 -61 -53 -46 -39 -34 -29 -24 -21 -17 -14 -12 -10 -8 -7 -6 -5 -4 -3 -2 -2 -2 -1 -1 -1 -1 -0 -0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/README.txt deleted file mode 100644 index 775767b0..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:36:16 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./GaussFir_1mp5.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './GaussFir_1mp5.sh' script. - -./GaussFir_1mp5.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./GaussFir_1mp5.sh -noclean_files - -For more information on the script, please type './GaussFir_1mp5.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/compile.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/compile.do deleted file mode 100644 index c585f50d..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/compile.do +++ /dev/null @@ -1,14 +0,0 @@ -vlib modelsim_lib/work -vlib modelsim_lib/msim - -vlib modelsim_lib/msim/xil_defaultlib - -vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib - -vcom -work xil_defaultlib -64 -93 \ -"../../../ip/GaussFir_1mp5/sim/GaussFir_1mp5.vhd" \ - - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/file_info.txt deleted file mode 100644 index 6c768509..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/file_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -GaussFir_1mp5.vhd,vhdl,xil_defaultlib,../../../ip/GaussFir_1mp5/sim/GaussFir_1mp5.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/modelsim.ini b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/modelsim.ini deleted file mode 100644 index 04a43f2c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/modelsim.ini +++ /dev/null @@ -1,2590 +0,0 @@ -; vsim modelsim.ini file -[Version] -INIVersion = "2020.4" - -; Copyright 1991-2020 Mentor Graphics Corporation -; -; All Rights Reserved. -; -; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF -; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. -; - -[Library] -others = $MODEL_TECH/../modelsim.ini -; -; VITAL concerns: -; -; The library ieee contains (among other packages) the packages of the -; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use -; the physical library ieee (recommended), or use the physical library -; vital2000, but not both. The design can use logical library ieee and/or -; vital2000 as long as each of these maps to the same physical library, either -; ieee or vital2000. -; -; A design using the 1995 version of the VITAL packages, whether or not -; it also uses the 2000 version of the VITAL packages, must have logical library -; name ieee mapped to physical library vital1995. (A design cannot use library -; vital1995 directly because some packages in this library use logical name ieee -; when referring to the other packages in the library.) The design source -; should use logical name ieee when referring to any packages there except the -; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical -; name vital2000 (mapped to physical library vital2000) to refer to those -; packages. -; ieee = $MODEL_TECH/../vital1995 -; -; For compatiblity with previous releases, logical library name vital2000 maps -; to library vital2000 (a different library than library ieee, containing the -; same packages). -; A design should not reference VITAL from both the ieee library and the -; vital2000 library because the vital packages are effectively different. -; A design that references both the ieee and vital2000 libraries must have -; both logical names ieee and vital2000 mapped to the same library, either of -; these: -; $MODEL_TECH/../ieee -; $MODEL_TECH/../vital2000 -; - -; added mapping for ADMS - -;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release -;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release -;mvc_lib = $MODEL_TECH/../mvc_lib - -; Automatically perform logical->physical mapping for physical libraries that -; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). -; The tail of the filesystem path name is chosen as the logical library name. -; For example, in the command "vopt -L ./path/to/lib1 -o opttop top", -; vopt automatically performs the mapping "lib1 -> ./path/to/lib1". -; See the User Manual for more details. -; -; AutoLibMapping = 0 - -secureip = C:/Mentor/CompLib/2019.1.3/secureip -unisim = C:/Mentor/CompLib/2019.1.3/unisim -unimacro = C:/Mentor/CompLib/2019.1.3/unimacro -unifast = C:/Mentor/CompLib/2019.1.3/unifast -unisims_ver = C:/Mentor/CompLib/2019.1.3/unisims_ver -unimacro_ver = C:/Mentor/CompLib/2019.1.3/unimacro_ver -unifast_ver = C:/Mentor/CompLib/2019.1.3/unifast_ver -simprims_ver = C:/Mentor/CompLib/2019.1.3/simprims_ver -xpm = C:/Mentor/CompLib/2019.1.3/xpm -xilinx_vip = C:/Mentor/CompLib/2019.1.3/xilinx_vip -advanced_io_wizard_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/advanced_io_wizard_phy_v1_0_0 -advanced_io_wizard_v1_0_0 = C:/Mentor/CompLib/2019.1.3/advanced_io_wizard_v1_0_0 -ahblite_axi_bridge_v3_0_14 = C:/Mentor/CompLib/2019.1.3/ahblite_axi_bridge_v3_0_14 -ai_noc = C:/Mentor/CompLib/2019.1.3/ai_noc -ai_pl_trig = C:/Mentor/CompLib/2019.1.3/ai_pl_trig -ai_pl = C:/Mentor/CompLib/2019.1.3/ai_pl -audio_clock_recovery_v1_0 = C:/Mentor/CompLib/2019.1.3/audio_clock_recovery_v1_0 -audio_tpg_v1_0_0 = C:/Mentor/CompLib/2019.1.3/audio_tpg_v1_0_0 -av_pat_gen_v1_0_0 = C:/Mentor/CompLib/2019.1.3/av_pat_gen_v1_0_0 -axis_infrastructure_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axis_infrastructure_v1_1_0 -axis_protocol_checker_v2_0_3 = C:/Mentor/CompLib/2019.1.3/axis_protocol_checker_v2_0_3 -axi_ahblite_bridge_v3_0_16 = C:/Mentor/CompLib/2019.1.3/axi_ahblite_bridge_v3_0_16 -axi_amm_bridge_v1_0_9 = C:/Mentor/CompLib/2019.1.3/axi_amm_bridge_v1_0_9 -axi_bram_ctrl_v4_1_1 = C:/Mentor/CompLib/2019.1.3/axi_bram_ctrl_v4_1_1 -axi_chip2chip_v5_0_6 = C:/Mentor/CompLib/2019.1.3/axi_chip2chip_v5_0_6 -axi_dbg_hub = C:/Mentor/CompLib/2019.1.3/axi_dbg_hub -axi_infrastructure_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axi_infrastructure_v1_1_0 -axi_jtag_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_jtag_v1_0_0 -axi_lite_ipif_v3_0_4 = C:/Mentor/CompLib/2019.1.3/axi_lite_ipif_v3_0_4 -axi_pcie3_v3_0_9 = C:/Mentor/CompLib/2019.1.3/axi_pcie3_v3_0_9 -axi_perf_mon_v5_0_21 = C:/Mentor/CompLib/2019.1.3/axi_perf_mon_v5_0_21 -axi_pmon_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_pmon_v1_0_0 -blk_mem_gen_v8_3_6 = C:/Mentor/CompLib/2019.1.3/blk_mem_gen_v8_3_6 -blk_mem_gen_v8_4_3 = C:/Mentor/CompLib/2019.1.3/blk_mem_gen_v8_4_3 -bsip_v1_1_0 = C:/Mentor/CompLib/2019.1.3/bsip_v1_1_0 -bs_mux_v1_0_0 = C:/Mentor/CompLib/2019.1.3/bs_mux_v1_0_0 -clk_gen_sim_v1_0_0 = C:/Mentor/CompLib/2019.1.3/clk_gen_sim_v1_0_0 -clk_vip_v1_0_2 = C:/Mentor/CompLib/2019.1.3/clk_vip_v1_0_2 -cmac_usplus_v2_4_5 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_4_5 -cmac_usplus_v2_5_3 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_5_3 -cmac_usplus_v2_6_2 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_6_2 -cmac_v2_3_5 = C:/Mentor/CompLib/2019.1.3/cmac_v2_3_5 -cmac_v2_4_1 = C:/Mentor/CompLib/2019.1.3/cmac_v2_4_1 -cmac_v2_5_1 = C:/Mentor/CompLib/2019.1.3/cmac_v2_5_1 -compact_gt_v1_0_5 = C:/Mentor/CompLib/2019.1.3/compact_gt_v1_0_5 -ddr4_pl_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/ddr4_pl_phy_v1_0_0 -ddr4_pl_v1_0_2 = C:/Mentor/CompLib/2019.1.3/ddr4_pl_v1_0_2 -dist_mem_gen_v8_0_13 = C:/Mentor/CompLib/2019.1.3/dist_mem_gen_v8_0_13 -ecc_v2_0_13 = C:/Mentor/CompLib/2019.1.3/ecc_v2_0_13 -emb_fifo_gen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/emb_fifo_gen_v1_0_1 -emb_mem_gen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/emb_mem_gen_v1_0_1 -emc_common_v3_0_5 = C:/Mentor/CompLib/2019.1.3/emc_common_v3_0_5 -ethernet_1_10_25g_v2_0_5 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_0_5 -ethernet_1_10_25g_v2_1_4 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_1_4 -ethernet_1_10_25g_v2_2_3 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_2_3 -ethernet_1_10_25g_v2_3_3 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_3_3 -fifo_generator_v13_0_6 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_0_6 -fifo_generator_v13_1_4 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_1_4 -fifo_generator_v13_2_4 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_2_4 -fit_timer_v2_0_10 = C:/Mentor/CompLib/2019.1.3/fit_timer_v2_0_10 -generic_baseblocks_v2_1_0 = C:/Mentor/CompLib/2019.1.3/generic_baseblocks_v2_1_0 -gigantic_mux = C:/Mentor/CompLib/2019.1.3/gigantic_mux -gig_ethernet_pcs_pma_v16_1_6 = C:/Mentor/CompLib/2019.1.3/gig_ethernet_pcs_pma_v16_1_6 -gmii_to_rgmii_v4_0_7 = C:/Mentor/CompLib/2019.1.3/gmii_to_rgmii_v4_0_7 -gtwizard_ultrascale_v1_5_4 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_5_4 -gtwizard_ultrascale_v1_6_11 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_6_11 -gtwizard_ultrascale_v1_7_6 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_7_6 -hbm_v1_0_4 = C:/Mentor/CompLib/2019.1.3/hbm_v1_0_4 -hdcp22_cipher_dp_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdcp22_cipher_dp_v1_0_0 -hdcp22_cipher_v1_0_3 = C:/Mentor/CompLib/2019.1.3/hdcp22_cipher_v1_0_3 -hdcp22_rng_v1_0_1 = C:/Mentor/CompLib/2019.1.3/hdcp22_rng_v1_0_1 -hdcp_keymngmt_blk_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdcp_keymngmt_blk_v1_0_0 -hdcp_v1_0_3 = C:/Mentor/CompLib/2019.1.3/hdcp_v1_0_3 -hdmi_gt_controller_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdmi_gt_controller_v1_0_0 -high_speed_selectio_wiz_v3_2_3 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_2_3 -high_speed_selectio_wiz_v3_3_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_3_1 -high_speed_selectio_wiz_v3_4_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_4_1 -high_speed_selectio_wiz_v3_5_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_5_1 -i2s_receiver_v1_0_3 = C:/Mentor/CompLib/2019.1.3/i2s_receiver_v1_0_3 -i2s_transmitter_v1_0_3 = C:/Mentor/CompLib/2019.1.3/i2s_transmitter_v1_0_3 -ibert_lib_v1_0_6 = C:/Mentor/CompLib/2019.1.3/ibert_lib_v1_0_6 -ieee802d3_clause74_fec_v1_0_4 = C:/Mentor/CompLib/2019.1.3/ieee802d3_clause74_fec_v1_0_4 -interlaken_v2_4_3 = C:/Mentor/CompLib/2019.1.3/interlaken_v2_4_3 -in_system_ibert_v1_0_9 = C:/Mentor/CompLib/2019.1.3/in_system_ibert_v1_0_9 -iomodule_v3_1_4 = C:/Mentor/CompLib/2019.1.3/iomodule_v3_1_4 -jesd204c_v4_1_1 = C:/Mentor/CompLib/2019.1.3/jesd204c_v4_1_1 -jesd204_v7_2_6 = C:/Mentor/CompLib/2019.1.3/jesd204_v7_2_6 -jtag_axi = C:/Mentor/CompLib/2019.1.3/jtag_axi -lib_cdc_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_cdc_v1_0_2 -lib_pkg_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_pkg_v1_0_2 -lmb_bram_if_cntlr_v4_0_16 = C:/Mentor/CompLib/2019.1.3/lmb_bram_if_cntlr_v4_0_16 -lmb_v10_v3_0_9 = C:/Mentor/CompLib/2019.1.3/lmb_v10_v3_0_9 -ltlib_v1_0_0 = C:/Mentor/CompLib/2019.1.3/ltlib_v1_0_0 -lut_buffer_v1_0_0 = C:/Mentor/CompLib/2019.1.3/lut_buffer_v1_0_0 -lut_buffer_v2_0_0 = C:/Mentor/CompLib/2019.1.3/lut_buffer_v2_0_0 -l_ethernet_v2_3_5 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_3_5 -l_ethernet_v2_4_3 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_4_3 -l_ethernet_v2_5_2 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_5_2 -mammoth_transcode_v1_0_0 = C:/Mentor/CompLib/2019.1.3/mammoth_transcode_v1_0_0 -microblaze_v10_0_7 = C:/Mentor/CompLib/2019.1.3/microblaze_v10_0_7 -microblaze_v11_0_1 = C:/Mentor/CompLib/2019.1.3/microblaze_v11_0_1 -microblaze_v9_5_4 = C:/Mentor/CompLib/2019.1.3/microblaze_v9_5_4 -mii_to_rmii_v2_0_21 = C:/Mentor/CompLib/2019.1.3/mii_to_rmii_v2_0_21 -mipi_csi2_rx_ctrl_v1_0_8 = C:/Mentor/CompLib/2019.1.3/mipi_csi2_rx_ctrl_v1_0_8 -mipi_csi2_tx_ctrl_v1_0_4 = C:/Mentor/CompLib/2019.1.3/mipi_csi2_tx_ctrl_v1_0_4 -mipi_dphy_v4_1_4 = C:/Mentor/CompLib/2019.1.3/mipi_dphy_v4_1_4 -mipi_dsi_tx_ctrl_v1_0_7 = C:/Mentor/CompLib/2019.1.3/mipi_dsi_tx_ctrl_v1_0_7 -mrmac_v1_0_0 = C:/Mentor/CompLib/2019.1.3/mrmac_v1_0_0 -multi_channel_25g_rs_fec_v1_0_5 = C:/Mentor/CompLib/2019.1.3/multi_channel_25g_rs_fec_v1_0_5 -mutex_v2_1_10 = C:/Mentor/CompLib/2019.1.3/mutex_v2_1_10 -axi_tg_lib = C:/Mentor/CompLib/2019.1.3/axi_tg_lib -noc_na_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_na_v1_0_0 -noc_nidb_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nidb_v1_0_0 -noc_nmu_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nmu_v1_0_0 -noc_nps_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nps_v1_0_0 -nvmeha_v1_0_0 = C:/Mentor/CompLib/2019.1.3/nvmeha_v1_0_0 -oddr_v1_0_0 = C:/Mentor/CompLib/2019.1.3/oddr_v1_0_0 -pci32_v5_0_12 = C:/Mentor/CompLib/2019.1.3/pci32_v5_0_12 -pci64_v5_0_11 = C:/Mentor/CompLib/2019.1.3/pci64_v5_0_11 -pcie_jtag_v1_0_0 = C:/Mentor/CompLib/2019.1.3/pcie_jtag_v1_0_0 -pc_cfr_v6_0_8 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_0_8 -pc_cfr_v6_1_4 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_1_4 -pc_cfr_v6_2_2 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_2_2 -pc_cfr_v6_3_0 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_3_0 -picxo = C:/Mentor/CompLib/2019.1.3/picxo -qdma_v3_0_2 = C:/Mentor/CompLib/2019.1.3/qdma_v3_0_2 -rama_v1_1_2_lib = C:/Mentor/CompLib/2019.1.3/rama_v1_1_2_lib -rld3_pl_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/rld3_pl_phy_v1_0_0 -rld3_pl_v1_0_1 = C:/Mentor/CompLib/2019.1.3/rld3_pl_v1_0_1 -roe_framer_v2_0_1 = C:/Mentor/CompLib/2019.1.3/roe_framer_v2_0_1 -rst_vip_v1_0_3 = C:/Mentor/CompLib/2019.1.3/rst_vip_v1_0_3 -smartconnect_v1_0 = C:/Mentor/CompLib/2019.1.3/smartconnect_v1_0 -sd_fec_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sd_fec_v1_0_2 -sem_ultra_v3_1_11 = C:/Mentor/CompLib/2019.1.3/sem_ultra_v3_1_11 -sem_v4_1_12 = C:/Mentor/CompLib/2019.1.3/sem_v4_1_12 -shell_utils_msp432_bsl_crc_gen_v1_0_0 = C:/Mentor/CompLib/2019.1.3/shell_utils_msp432_bsl_crc_gen_v1_0_0 -sim_clk_gen_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sim_clk_gen_v1_0_2 -sim_rst_gen_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sim_rst_gen_v1_0_2 -sim_trig_top_v1_0 = C:/Mentor/CompLib/2019.1.3/sim_trig_top_v1_0 -stm_v1_0 = C:/Mentor/CompLib/2019.1.3/stm_v1_0 -stm_v1_0_0 = C:/Mentor/CompLib/2019.1.3/stm_v1_0_0 -system_cache_v4_0_6 = C:/Mentor/CompLib/2019.1.3/system_cache_v4_0_6 -ta_dma_v1_0_3 = C:/Mentor/CompLib/2019.1.3/ta_dma_v1_0_3 -tcc_decoder_3gpplte_v3_0_6 = C:/Mentor/CompLib/2019.1.3/tcc_decoder_3gpplte_v3_0_6 -ten_gig_eth_mac_v15_1_7 = C:/Mentor/CompLib/2019.1.3/ten_gig_eth_mac_v15_1_7 -ten_gig_eth_pcs_pma_v6_0_15 = C:/Mentor/CompLib/2019.1.3/ten_gig_eth_pcs_pma_v6_0_15 -timer_sync_1588_v1_2_4 = C:/Mentor/CompLib/2019.1.3/timer_sync_1588_v1_2_4 -tmr_inject_v1_0_3 = C:/Mentor/CompLib/2019.1.3/tmr_inject_v1_0_3 -tmr_manager_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tmr_manager_v1_0_4 -tmr_voter_v1_0_2 = C:/Mentor/CompLib/2019.1.3/tmr_voter_v1_0_2 -tsn_endpoint_ethernet_mac_block_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tsn_endpoint_ethernet_mac_block_v1_0_4 -uhdsdi_gt_v1_0_3 = C:/Mentor/CompLib/2019.1.3/uhdsdi_gt_v1_0_3 -uhdsdi_gt_v2_0_0 = C:/Mentor/CompLib/2019.1.3/uhdsdi_gt_v2_0_0 -usxgmii_v1_0_5 = C:/Mentor/CompLib/2019.1.3/usxgmii_v1_0_5 -usxgmii_v1_1_0 = C:/Mentor/CompLib/2019.1.3/usxgmii_v1_1_0 -util_idelay_ctrl_v1_0_1 = C:/Mentor/CompLib/2019.1.3/util_idelay_ctrl_v1_0_1 -util_reduced_logic_v2_0_4 = C:/Mentor/CompLib/2019.1.3/util_reduced_logic_v2_0_4 -util_vector_logic_v2_0_1 = C:/Mentor/CompLib/2019.1.3/util_vector_logic_v2_0_1 -ba317 = C:/Mentor/CompLib/2019.1.3/ba317 -vfb_v1_0_13 = C:/Mentor/CompLib/2019.1.3/vfb_v1_0_13 -video_frame_crc_v1_0_1 = C:/Mentor/CompLib/2019.1.3/video_frame_crc_v1_0_1 -vid_edid_v1_0_0 = C:/Mentor/CompLib/2019.1.3/vid_edid_v1_0_0 -vid_phy_controller_v2_1_5 = C:/Mentor/CompLib/2019.1.3/vid_phy_controller_v2_1_5 -vid_phy_controller_v2_2_3 = C:/Mentor/CompLib/2019.1.3/vid_phy_controller_v2_2_3 -v_axi4s_remap_v1_0_11 = C:/Mentor/CompLib/2019.1.3/v_axi4s_remap_v1_0_11 -v_csc_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_csc_v1_0_13 -v_deinterlacer_v4_0_12 = C:/Mentor/CompLib/2019.1.3/v_deinterlacer_v4_0_12 -v_deinterlacer_v5_0_13 = C:/Mentor/CompLib/2019.1.3/v_deinterlacer_v5_0_13 -v_demosaic_v1_0_5 = C:/Mentor/CompLib/2019.1.3/v_demosaic_v1_0_5 -v_frmbuf_rd_v2_1_2 = C:/Mentor/CompLib/2019.1.3/v_frmbuf_rd_v2_1_2 -v_frmbuf_wr_v2_1_2 = C:/Mentor/CompLib/2019.1.3/v_frmbuf_wr_v2_1_2 -v_gamma_lut_v1_0_5 = C:/Mentor/CompLib/2019.1.3/v_gamma_lut_v1_0_5 -v_hcresampler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_hcresampler_v1_0_13 -v_hdmi_rx_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_rx_v2_0_0 -v_hdmi_rx_v3_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_rx_v3_0_0 -v_hdmi_tx_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_tx_v2_0_0 -v_hdmi_tx_v3_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_tx_v3_0_0 -v_hscaler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_hscaler_v1_0_13 -v_letterbox_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_letterbox_v1_0_13 -v_mix_v3_0_3 = C:/Mentor/CompLib/2019.1.3/v_mix_v3_0_3 -v_mix_v4_0_0 = C:/Mentor/CompLib/2019.1.3/v_mix_v4_0_0 -v_multi_scaler_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_multi_scaler_v1_0_1 -v_scenechange_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_scenechange_v1_0_1 -v_sdi_rx_vid_bridge_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_sdi_rx_vid_bridge_v2_0_0 -v_smpte_sdi_v3_0_8 = C:/Mentor/CompLib/2019.1.3/v_smpte_sdi_v3_0_8 -v_smpte_uhdsdi_rx_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_rx_v1_0_0 -v_smpte_uhdsdi_tx_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_tx_v1_0_0 -v_smpte_uhdsdi_v1_0_7 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_v1_0_7 -v_tpg_v7_0_13 = C:/Mentor/CompLib/2019.1.3/v_tpg_v7_0_13 -v_tpg_v8_0_1 = C:/Mentor/CompLib/2019.1.3/v_tpg_v8_0_1 -v_uhdsdi_audio_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v1_0_0 -v_uhdsdi_audio_v1_1_0 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v1_1_0 -v_uhdsdi_audio_v2_0_1 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v2_0_1 -v_uhdsdi_vidgen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_vidgen_v1_0_1 -v_vcresampler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_vcresampler_v1_0_13 -v_vid_in_axi4s_v4_0_9 = C:/Mentor/CompLib/2019.1.3/v_vid_in_axi4s_v4_0_9 -v_vscaler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_vscaler_v1_0_13 -xaui_v12_3_6 = C:/Mentor/CompLib/2019.1.3/xaui_v12_3_6 -xbip_dsp48_wrapper_v3_0_4 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_wrapper_v3_0_4 -xbip_utils_v3_0_10 = C:/Mentor/CompLib/2019.1.3/xbip_utils_v3_0_10 -xdma_v4_1_3 = C:/Mentor/CompLib/2019.1.3/xdma_v4_1_3 -xhmc_v1_0_9 = C:/Mentor/CompLib/2019.1.3/xhmc_v1_0_9 -xlconcat_v2_1_3 = C:/Mentor/CompLib/2019.1.3/xlconcat_v2_1_3 -xlconstant_v1_1_6 = C:/Mentor/CompLib/2019.1.3/xlconstant_v1_1_6 -xlslice_v1_0_2 = C:/Mentor/CompLib/2019.1.3/xlslice_v1_0_2 -xsdbm_v2_0_0 = C:/Mentor/CompLib/2019.1.3/xsdbm_v2_0_0 -xsdbm_v3_0_0 = C:/Mentor/CompLib/2019.1.3/xsdbm_v3_0_0 -xxv_ethernet_v2_4_5 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v2_4_5 -xxv_ethernet_v2_5_3 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v2_5_3 -xxv_ethernet_v3_0_3 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v3_0_3 -zynq_ultra_ps_e_v3_2_3 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_v3_2_3 -zynq_ultra_ps_e_v3_3_0 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_v3_3_0 -lib_srl_fifo_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_srl_fifo_v1_0_2 -lib_fifo_v1_0_13 = C:/Mentor/CompLib/2019.1.3/lib_fifo_v1_0_13 -axi_datamover_v5_1_21 = C:/Mentor/CompLib/2019.1.3/axi_datamover_v5_1_21 -amm_axi_bridge_v1_0_5 = C:/Mentor/CompLib/2019.1.3/amm_axi_bridge_v1_0_5 -axis_interconnect_v1_1_17 = C:/Mentor/CompLib/2019.1.3/axis_interconnect_v1_1_17 -ats_switch_v1_0_2 = C:/Mentor/CompLib/2019.1.3/ats_switch_v1_0_2 -audio_formatter_v1_0_1 = C:/Mentor/CompLib/2019.1.3/audio_formatter_v1_0_1 -axi4stream_vip_v1_1_5 = C:/Mentor/CompLib/2019.1.3/axi4stream_vip_v1_1_5 -v_tc_v6_1_13 = C:/Mentor/CompLib/2019.1.3/v_tc_v6_1_13 -v_axi4s_vid_out_v4_0_10 = C:/Mentor/CompLib/2019.1.3/v_axi4s_vid_out_v4_0_10 -axi4svideo_bridge_v1_0_10 = C:/Mentor/CompLib/2019.1.3/axi4svideo_bridge_v1_0_10 -axis_accelerator_adapter_v2_1_15 = C:/Mentor/CompLib/2019.1.3/axis_accelerator_adapter_v2_1_15 -axis_broadcaster_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axis_broadcaster_v1_1_18 -axis_clock_converter_v1_1_20 = C:/Mentor/CompLib/2019.1.3/axis_clock_converter_v1_1_20 -axis_combiner_v1_1_17 = C:/Mentor/CompLib/2019.1.3/axis_combiner_v1_1_17 -axis_data_fifo_v1_1_20 = C:/Mentor/CompLib/2019.1.3/axis_data_fifo_v1_1_20 -axis_data_fifo_v2_0_1 = C:/Mentor/CompLib/2019.1.3/axis_data_fifo_v2_0_1 -axis_register_slice_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_register_slice_v1_1_19 -axis_dwidth_converter_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axis_dwidth_converter_v1_1_18 -axis_subset_converter_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_subset_converter_v1_1_19 -axis_switch_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_switch_v1_1_19 -axis_vio_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axis_vio_v1_0_0 -axi_apb_bridge_v3_0_15 = C:/Mentor/CompLib/2019.1.3/axi_apb_bridge_v3_0_15 -axi_bram_ctrl_v4_0_14 = C:/Mentor/CompLib/2019.1.3/axi_bram_ctrl_v4_0_14 -axi_sg_v4_1_12 = C:/Mentor/CompLib/2019.1.3/axi_sg_v4_1_12 -axi_cdma_v4_1_19 = C:/Mentor/CompLib/2019.1.3/axi_cdma_v4_1_19 -axi_clock_converter_v2_1_18 = C:/Mentor/CompLib/2019.1.3/axi_clock_converter_v2_1_18 -axi_data_fifo_v2_1_18 = C:/Mentor/CompLib/2019.1.3/axi_data_fifo_v2_1_18 -axi_register_slice_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_register_slice_v2_1_19 -axi_crossbar_v2_1_20 = C:/Mentor/CompLib/2019.1.3/axi_crossbar_v2_1_20 -axi_dma_v7_1_20 = C:/Mentor/CompLib/2019.1.3/axi_dma_v7_1_20 -axi_protocol_converter_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_protocol_converter_v2_1_19 -axi_dwidth_converter_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_dwidth_converter_v2_1_19 -axi_emc_v3_0_19 = C:/Mentor/CompLib/2019.1.3/axi_emc_v3_0_19 -axi_epc_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_epc_v2_0_22 -lib_bmg_v1_0_12 = C:/Mentor/CompLib/2019.1.3/lib_bmg_v1_0_12 -axi_ethernetlite_v3_0_17 = C:/Mentor/CompLib/2019.1.3/axi_ethernetlite_v3_0_17 -axi_ethernet_buffer_v2_0_20 = C:/Mentor/CompLib/2019.1.3/axi_ethernet_buffer_v2_0_20 -axi_fifo_mm_s_v4_1_16 = C:/Mentor/CompLib/2019.1.3/axi_fifo_mm_s_v4_1_16 -axi_fifo_mm_s_v4_2_1 = C:/Mentor/CompLib/2019.1.3/axi_fifo_mm_s_v4_2_1 -axi_firewall_v1_0_7 = C:/Mentor/CompLib/2019.1.3/axi_firewall_v1_0_7 -interrupt_control_v3_1_4 = C:/Mentor/CompLib/2019.1.3/interrupt_control_v3_1_4 -axi_gpio_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_gpio_v2_0_21 -axi_hwicap_v3_0_23 = C:/Mentor/CompLib/2019.1.3/axi_hwicap_v3_0_23 -axi_iic_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_iic_v2_0_22 -axi_intc_v4_1_13 = C:/Mentor/CompLib/2019.1.3/axi_intc_v4_1_13 -axi_interconnect_v1_7_16 = C:/Mentor/CompLib/2019.1.3/axi_interconnect_v1_7_16 -axi_master_burst_v2_0_7 = C:/Mentor/CompLib/2019.1.3/axi_master_burst_v2_0_7 -axi_msg_v1_0_5 = C:/Mentor/CompLib/2019.1.3/axi_msg_v1_0_5 -axi_mcdma_v1_0_5 = C:/Mentor/CompLib/2019.1.3/axi_mcdma_v1_0_5 -axi_mcdma_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axi_mcdma_v1_1_0 -axi_memory_init_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_memory_init_v1_0_0 -axi_mm2s_mapper_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axi_mm2s_mapper_v1_1_18 -axi_mmu_v2_1_17 = C:/Mentor/CompLib/2019.1.3/axi_mmu_v2_1_17 -axi_pcie_v2_9_1 = C:/Mentor/CompLib/2019.1.3/axi_pcie_v2_9_1 -axi_protocol_checker_v2_0_5 = C:/Mentor/CompLib/2019.1.3/axi_protocol_checker_v2_0_5 -axi_quad_spi_v3_2_18 = C:/Mentor/CompLib/2019.1.3/axi_quad_spi_v3_2_18 -axi_sideband_util_v1_0_3 = C:/Mentor/CompLib/2019.1.3/axi_sideband_util_v1_0_3 -axi_tft_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_tft_v2_0_22 -axi_timebase_wdt_v3_0_11 = C:/Mentor/CompLib/2019.1.3/axi_timebase_wdt_v3_0_11 -axi_timer_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_timer_v2_0_21 -axi_traffic_gen_v2_0_20 = C:/Mentor/CompLib/2019.1.3/axi_traffic_gen_v2_0_20 -axi_traffic_gen_v3_0_5 = C:/Mentor/CompLib/2019.1.3/axi_traffic_gen_v3_0_5 -axi_uart16550_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_uart16550_v2_0_21 -axi_uartlite_v2_0_23 = C:/Mentor/CompLib/2019.1.3/axi_uartlite_v2_0_23 -axi_usb2_device_v5_0_20 = C:/Mentor/CompLib/2019.1.3/axi_usb2_device_v5_0_20 -axi_utils_v2_0_6 = C:/Mentor/CompLib/2019.1.3/axi_utils_v2_0_6 -axi_vdma_v6_3_7 = C:/Mentor/CompLib/2019.1.3/axi_vdma_v6_3_7 -xbip_pipe_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_pipe_v3_0_6 -xbip_dsp48_addsub_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_addsub_v3_0_6 -xbip_addsub_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_addsub_v3_0_6 -c_reg_fd_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_reg_fd_v12_0_6 -c_addsub_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_addsub_v12_0_13 -axi_vfifo_ctrl_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_vfifo_ctrl_v2_0_21 -axi_vip_v1_1_5 = C:/Mentor/CompLib/2019.1.3/axi_vip_v1_1_5 -bs_switch_v1_0_0 = C:/Mentor/CompLib/2019.1.3/bs_switch_v1_0_0 -canfd_v2_0_1 = C:/Mentor/CompLib/2019.1.3/canfd_v2_0_1 -can_v5_0_22 = C:/Mentor/CompLib/2019.1.3/can_v5_0_22 -cic_compiler_v4_0_14 = C:/Mentor/CompLib/2019.1.3/cic_compiler_v4_0_14 -xbip_bram18k_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_bram18k_v3_0_6 -mult_gen_v12_0_15 = C:/Mentor/CompLib/2019.1.3/mult_gen_v12_0_15 -cmpy_v6_0_17 = C:/Mentor/CompLib/2019.1.3/cmpy_v6_0_17 -c_mux_bit_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_mux_bit_v12_0_6 -c_shift_ram_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_shift_ram_v12_0_13 -c_mux_bus_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_mux_bus_v12_0_6 -c_gate_bit_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_gate_bit_v12_0_6 -xbip_counter_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_counter_v3_0_6 -c_counter_binary_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_counter_binary_v12_0_13 -c_compare_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_compare_v12_0_6 -convolution_v9_0_14 = C:/Mentor/CompLib/2019.1.3/convolution_v9_0_14 -cordic_v6_0_15 = C:/Mentor/CompLib/2019.1.3/cordic_v6_0_15 -cpri_v8_10_3 = C:/Mentor/CompLib/2019.1.3/cpri_v8_10_3 -xbip_dsp48_acc_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_acc_v3_0_6 -xbip_accum_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_accum_v3_0_6 -c_accum_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_accum_v12_0_13 -xbip_dsp48_multadd_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_multadd_v3_0_6 -dds_compiler_v6_0_18 = C:/Mentor/CompLib/2019.1.3/dds_compiler_v6_0_18 -dft_v4_0_16 = C:/Mentor/CompLib/2019.1.3/dft_v4_0_16 -dft_v4_1_1 = C:/Mentor/CompLib/2019.1.3/dft_v4_1_1 -displayport_v7_0_11 = C:/Mentor/CompLib/2019.1.3/displayport_v7_0_11 -displayport_v8_1_1 = C:/Mentor/CompLib/2019.1.3/displayport_v8_1_1 -displayport_v9_0_1 = C:/Mentor/CompLib/2019.1.3/displayport_v9_0_1 -xbip_dsp48_mult_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_mult_v3_0_6 -floating_point_v7_0_16 = C:/Mentor/CompLib/2019.1.3/floating_point_v7_0_16 -div_gen_v5_1_15 = C:/Mentor/CompLib/2019.1.3/div_gen_v5_1_15 -dp_videoaxi4s_bridge_v1_0_0 = C:/Mentor/CompLib/2019.1.3/dp_videoaxi4s_bridge_v1_0_0 -dsp_macro_v1_0_0 = C:/Mentor/CompLib/2019.1.3/dsp_macro_v1_0_0 -fir_compiler_v5_2_6 = C:/Mentor/CompLib/2019.1.3/fir_compiler_v5_2_6 -duc_ddc_compiler_v3_0_15 = C:/Mentor/CompLib/2019.1.3/duc_ddc_compiler_v3_0_15 -ernic_v1_0_1 = C:/Mentor/CompLib/2019.1.3/ernic_v1_0_1 -etrnic_v1_0_3 = C:/Mentor/CompLib/2019.1.3/etrnic_v1_0_3 -etrnic_v1_1_2 = C:/Mentor/CompLib/2019.1.3/etrnic_v1_1_2 -fc32_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/fc32_rs_fec_v1_0_11 -fec_5g_common_v1_0_1 = C:/Mentor/CompLib/2019.1.3/fec_5g_common_v1_0_1 -fec_5g_common_v1_1_1 = C:/Mentor/CompLib/2019.1.3/fec_5g_common_v1_1_1 -fir_compiler_v7_2_12 = C:/Mentor/CompLib/2019.1.3/fir_compiler_v7_2_12 -flexo_100g_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/flexo_100g_rs_fec_v1_0_11 -floating_point_v7_1_8 = C:/Mentor/CompLib/2019.1.3/floating_point_v7_1_8 -g709_rs_encoder_v2_2_6 = C:/Mentor/CompLib/2019.1.3/g709_rs_encoder_v2_2_6 -rs_toolbox_v9_0_7 = C:/Mentor/CompLib/2019.1.3/rs_toolbox_v9_0_7 -g709_rs_decoder_v2_2_8 = C:/Mentor/CompLib/2019.1.3/g709_rs_decoder_v2_2_8 -g709_fec_v2_3_5 = C:/Mentor/CompLib/2019.1.3/g709_fec_v2_3_5 -g709_fec_v2_4_1 = C:/Mentor/CompLib/2019.1.3/g709_fec_v2_4_1 -g975_efec_i4_v1_0_17 = C:/Mentor/CompLib/2019.1.3/g975_efec_i4_v1_0_17 -g975_efec_i7_v2_0_18 = C:/Mentor/CompLib/2019.1.3/g975_efec_i7_v2_0_18 -ieee802d3_200g_rs_fec_v1_0_7 = C:/Mentor/CompLib/2019.1.3/ieee802d3_200g_rs_fec_v1_0_7 -ieee802d3_25g_rs_fec_v1_0_13 = C:/Mentor/CompLib/2019.1.3/ieee802d3_25g_rs_fec_v1_0_13 -ieee802d3_400g_rs_fec_v1_0_7 = C:/Mentor/CompLib/2019.1.3/ieee802d3_400g_rs_fec_v1_0_7 -ieee802d3_50g_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/ieee802d3_50g_rs_fec_v1_0_11 -ieee802d3_50g_rs_fec_v2_0_1 = C:/Mentor/CompLib/2019.1.3/ieee802d3_50g_rs_fec_v2_0_1 -ieee802d3_rs_fec_v1_0_15 = C:/Mentor/CompLib/2019.1.3/ieee802d3_rs_fec_v1_0_15 -ieee802d3_rs_fec_v2_0_5 = C:/Mentor/CompLib/2019.1.3/ieee802d3_rs_fec_v2_0_5 -ldpc_v2_0_3 = C:/Mentor/CompLib/2019.1.3/ldpc_v2_0_3 -lte_3gpp_channel_estimator_v2_0_16 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_channel_estimator_v2_0_16 -lte_3gpp_mimo_decoder_v3_0_15 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_mimo_decoder_v3_0_15 -lte_3gpp_mimo_encoder_v4_0_14 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_mimo_encoder_v4_0_14 -tcc_encoder_3gpplte_v4_0_15 = C:/Mentor/CompLib/2019.1.3/tcc_encoder_3gpplte_v4_0_15 -lte_dl_channel_encoder_v3_0_15 = C:/Mentor/CompLib/2019.1.3/lte_dl_channel_encoder_v3_0_15 -lte_dl_channel_encoder_v4_0_0 = C:/Mentor/CompLib/2019.1.3/lte_dl_channel_encoder_v4_0_0 -xfft_v7_2_9 = C:/Mentor/CompLib/2019.1.3/xfft_v7_2_9 -lte_fft_v2_0_18 = C:/Mentor/CompLib/2019.1.3/lte_fft_v2_0_18 -xfft_v9_1_2 = C:/Mentor/CompLib/2019.1.3/xfft_v9_1_2 -lte_fft_v2_1_0 = C:/Mentor/CompLib/2019.1.3/lte_fft_v2_1_0 -xbip_dsp48_multacc_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_multacc_v3_0_6 -lte_pucch_receiver_v2_0_16 = C:/Mentor/CompLib/2019.1.3/lte_pucch_receiver_v2_0_16 -xbip_multadd_v3_0_14 = C:/Mentor/CompLib/2019.1.3/xbip_multadd_v3_0_14 -lte_rach_detector_v3_1_5 = C:/Mentor/CompLib/2019.1.3/lte_rach_detector_v3_1_5 -lte_ul_channel_decoder_v4_0_16 = C:/Mentor/CompLib/2019.1.3/lte_ul_channel_decoder_v4_0_16 -mailbox_v2_1_11 = C:/Mentor/CompLib/2019.1.3/mailbox_v2_1_11 -mdm_v3_2_16 = C:/Mentor/CompLib/2019.1.3/mdm_v3_2_16 -iomodule_v3_0 = C:/Mentor/CompLib/2019.1.3/iomodule_v3_0 -lmb_bram_if_cntlr_v4_0 = C:/Mentor/CompLib/2019.1.3/lmb_bram_if_cntlr_v4_0 -lmb_v10_v3_0 = C:/Mentor/CompLib/2019.1.3/lmb_v10_v3_0 -axi_lite_ipif_v3_0 = C:/Mentor/CompLib/2019.1.3/axi_lite_ipif_v3_0 -mdm_v3_2 = C:/Mentor/CompLib/2019.1.3/mdm_v3_2 -microblaze_mcs_v2_3_6 = C:/Mentor/CompLib/2019.1.3/microblaze_mcs_v2_3_6 -noc_mc_ddr4_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_mc_ddr4_phy_v1_0_0 -perf_axi_tg_v1_0_8 = C:/Mentor/CompLib/2019.1.3/perf_axi_tg_v1_0_8 -polar_v1_0_3 = C:/Mentor/CompLib/2019.1.3/polar_v1_0_3 -prc_v1_3_2 = C:/Mentor/CompLib/2019.1.3/prc_v1_3_2 -processing_system7_vip_v1_0_7 = C:/Mentor/CompLib/2019.1.3/processing_system7_vip_v1_0_7 -proc_sys_reset_v5_0_13 = C:/Mentor/CompLib/2019.1.3/proc_sys_reset_v5_0_13 -pr_axi_shutdown_manager_v1_0_1 = C:/Mentor/CompLib/2019.1.3/pr_axi_shutdown_manager_v1_0_1 -pr_bitstream_monitor_v1_0_1 = C:/Mentor/CompLib/2019.1.3/pr_bitstream_monitor_v1_0_1 -pr_decoupler_v1_0_7 = C:/Mentor/CompLib/2019.1.3/pr_decoupler_v1_0_7 -quadsgmii_v3_4_6 = C:/Mentor/CompLib/2019.1.3/quadsgmii_v3_4_6 -rs_decoder_v9_0_16 = C:/Mentor/CompLib/2019.1.3/rs_decoder_v9_0_16 -rs_encoder_v9_0_15 = C:/Mentor/CompLib/2019.1.3/rs_encoder_v9_0_15 -rxaui_v4_4_6 = C:/Mentor/CompLib/2019.1.3/rxaui_v4_4_6 -sd_fec_v1_1_3 = C:/Mentor/CompLib/2019.1.3/sd_fec_v1_1_3 -sid_v8_0_14 = C:/Mentor/CompLib/2019.1.3/sid_v8_0_14 -soft_ecc_proxy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/soft_ecc_proxy_v1_0_0 -spdif_v2_0_21 = C:/Mentor/CompLib/2019.1.3/spdif_v2_0_21 -srio_gen2_v4_1_6 = C:/Mentor/CompLib/2019.1.3/srio_gen2_v4_1_6 -switch_core_top_v1_0_7 = C:/Mentor/CompLib/2019.1.3/switch_core_top_v1_0_7 -sync_ip = C:/Mentor/CompLib/2019.1.3/sync_ip -tcc_decoder_3gppmm_v2_0_18 = C:/Mentor/CompLib/2019.1.3/tcc_decoder_3gppmm_v2_0_18 -tcc_encoder_3gpp_v5_0_15 = C:/Mentor/CompLib/2019.1.3/tcc_encoder_3gpp_v5_0_15 -tmr_comparator_v1_0_2 = C:/Mentor/CompLib/2019.1.3/tmr_comparator_v1_0_2 -tmr_sem_v1_0_9 = C:/Mentor/CompLib/2019.1.3/tmr_sem_v1_0_9 -tri_mode_ethernet_mac_v9_0_14 = C:/Mentor/CompLib/2019.1.3/tri_mode_ethernet_mac_v9_0_14 -tsn_temac_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tsn_temac_v1_0_4 -videoaxi4s_bridge_v1_0_5 = C:/Mentor/CompLib/2019.1.3/videoaxi4s_bridge_v1_0_5 -viterbi_v9_1_11 = C:/Mentor/CompLib/2019.1.3/viterbi_v9_1_11 -v_ccm_v6_0_15 = C:/Mentor/CompLib/2019.1.3/v_ccm_v6_0_15 -v_cfa_v7_0_14 = C:/Mentor/CompLib/2019.1.3/v_cfa_v7_0_14 -v_cresample_v4_0_14 = C:/Mentor/CompLib/2019.1.3/v_cresample_v4_0_14 -v_dual_splitter_v1_0_9 = C:/Mentor/CompLib/2019.1.3/v_dual_splitter_v1_0_9 -v_enhance_v8_0_15 = C:/Mentor/CompLib/2019.1.3/v_enhance_v8_0_15 -v_gamma_v7_0_15 = C:/Mentor/CompLib/2019.1.3/v_gamma_v7_0_15 -v_osd_v6_0_16 = C:/Mentor/CompLib/2019.1.3/v_osd_v6_0_16 -v_rgb2ycrcb_v7_1_13 = C:/Mentor/CompLib/2019.1.3/v_rgb2ycrcb_v7_1_13 -v_vid_sdi_tx_bridge_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_vid_sdi_tx_bridge_v2_0_0 -v_ycrcb2rgb_v7_1_13 = C:/Mentor/CompLib/2019.1.3/v_ycrcb2rgb_v7_1_13 -xbip_dsp48_macro_v3_0_17 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_macro_v3_0_17 -xfft_v9_0_17 = C:/Mentor/CompLib/2019.1.3/xfft_v9_0_17 -xsdbs_v1_0_2 = C:/Mentor/CompLib/2019.1.3/xsdbs_v1_0_2 -zynq_ultra_ps_e_vip_v1_0_5 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_vip_v1_0_5 -[DefineOptionset] -; Define optionset entries for the various compilers, vmake, and vsim. -; These option sets can be used with the "-optionset " syntax. -; i.e. -; vlog -optionset COMPILEDEBUG top.sv -; vsim -optionset UVMDEBUG my_top -; -; Following are some useful examples. - -; define a vsim optionset for uvm debugging -UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop - -; define a vopt optionset for debugging -VOPTDEBUG = +acc -debugdb - -[encryption] -; For vencrypt and vhencrypt. - -; Controls whether to encrypt whole files by ignoring all protect directives -; (except "viewport" and "interface_viewport") that are present in the input. -; The default is 0, use embedded protect directives to control the encryption. -; Set this to 1 to encrypt whole files by ignoring embedded protect directives. -; wholefile = 0 - -; Sets the data_method to use for the symmetric session key. -; The session key is a symmetric key that is randomly generated for each -; protected region (envelope) and is the heart of all encryption. This is used -; to set the length of the session key to generate and use when encrypting the -; HDL text. Supported values are aes128, aes192, and aes256. -; data_method = aes128 - -; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption -; "recipe" comprising an optional common block, at least one tool block (which -; contains the key public key), and the text to be encrypted. The common block -; and any of the tool blocks may contain rights in the form of the "control" -; directive. The text to be encrypted is specified either by setting -; "wholefile" to 1 or by embedding protect "begin" and "end" directives in -; the input HDL files. - -; Common recipe specification file. This file is optional. Its presence will -; require at least one "toolblock" to be specified. -; Directives such as "author" "author_info" and "data_method", -; as well as the common block license specification, go in this file. -; common = - -; Tool block specification recipe(s). Public key file with optional tool block -; file name. May be multiply-defined; at least one tool block is required if -; a recipe is being specified. -; Key file is a file name with no extension (.deprecated or .active will be -; supplied by the encryption tool). -; Rights file name is optional. -; toolblock = [,]{:[,]} - -; Location of directory containing recipe files. -; The default location is in the product installation directory. -; keyring = $MODEL_TECH/../keyring - -; Enable encryption statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list] -; Add '-' to disable specific statistics. Default is [cmd,msg]. -Stats = cmd,msg - -[vcom] -; VHDL93 variable selects language version as the default. -; Default is VHDL-2002. -; Value of 0 or 1987 for VHDL-1987. -; Value of 1 or 1993 for VHDL-1993. -; Default or value of 2 or 2002 for VHDL-2002. -; Value of 3 or 2008 for VHDL-2008 -; Value of 4 or ams99 for VHDL-AMS-1999 -; Value of 5 or ams07 for VHDL-AMS-2007 -VHDL93 = 2002 - -; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. -; ignoreStandardRealVector = 1 - -; Show source line containing error. Default is off. -; Show_source = 1 - -; Turn off unbound-component warnings. Default is on. -; Show_Warning1 = 0 - -; Turn off process-without-a-wait-statement warnings. Default is on. -; Show_Warning2 = 0 - -; Turn off null-range warnings. Default is on. -; Show_Warning3 = 0 - -; Turn off no-space-in-time-literal warnings. Default is on. -; Show_Warning4 = 0 - -; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. -; Show_Warning5 = 0 - -; Turn off optimization for IEEE std_logic_1164 package. Default is on. -; Optimize_1164 = 0 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Turn on resolving of ambiguous function overloading in favor of the -; "explicit" function declaration (not the one automatically created by -; the compiler for each type declaration). Default is off. -; The .ini file has Explicit enabled so that std_logic_signed/unsigned -; will match the behavior of synthesis tools. -Explicit = 1 - -; Turn off acceleration of the VITAL packages. Default is to accelerate. -; NoVital = 1 - -; Turn off VITAL compliance checking. Default is checking on. -; NoVitalCheck = 1 - -; Ignore VITAL compliance checking errors. Default is to not ignore. -; IgnoreVitalErrors = 1 - -; Turn off VITAL compliance checking warnings. Default is to show warnings. -; Show_VitalChecksWarnings = 0 - -; Turn off PSL assertion warning messages. Default is to show warnings. -; Show_PslChecksWarnings = 0 - -; Enable parsing of embedded PSL assertions. Default is enabled. -; EmbeddedPsl = 0 - -; Keep silent about case statement static warnings. -; Default is to give a warning. -; NoCaseStaticError = 1 - -; Keep silent about warnings caused by aggregates that are not locally static. -; Default is to give a warning. -; NoOthersStaticError = 1 - -; Treat as errors: -; case statement static warnings -; warnings caused by aggregates that are not locally static -; Overrides NoCaseStaticError, NoOthersStaticError settings. -; PedanticErrors = 1 - -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn off "Loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on some limited synthesis rule compliance checking. Checks only: -; -- signals used (read) by a process must be in the sensitivity list -; CheckSynthesis = 1 - -; Activate optimizations on expressions that do not involve signals, -; waits, or function/procedure/task invocations. Default is off. -; ScalarOpts = 1 - -; Turns on lint-style checking. -; Show_Lint = 1 - -; Require the user to specify a configuration for all bindings, -; and do not generate a compile time default binding for the -; component. This will result in an elaboration error of -; 'component not bound' if the user fails to do so. Avoids the rare -; issue of a false dependency upon the unused default binding. -; RequireConfigForAllDefaultBinding = 1 - -; Perform default binding at compile time. -; Default is to do default binding at load time. -; BindAtCompile = 1; - -; Inhibit range checking on subscripts of arrays. Range checking on -; scalars defined with subtypes is inhibited by default. -; NoIndexCheck = 1 - -; Inhibit range checks on all (implicit and explicit) assignments to -; scalar objects defined with subtypes. -; NoRangeCheck = 1 - -; Set the prefix to be honored for synthesis/coverage pragma recognition. -; Default is "". -; AddPragmaPrefix = "" - -; Ignore synthesis and coverage pragmas with this prefix. -; Default is "". -; IgnorePragmaPrefix = "" - -; Turn on code coverage in VHDL design units. Default is off. -; Coverage = sbceft - -; Turn off code coverage in VHDL subprograms. Default is on. -; CoverSub = 0 - -; Automatically exclude VHDL case statement OTHERS choice branches. -; This includes OTHERS choices in selected signal assigment statements. -; Default is to not exclude. -; CoverExcludeDefault = 1 - -; Control compiler and VOPT optimizations that are allowed when -; code coverage is on. Refer to the comment for this in the [vlog] area. -; CoverOpt = 3 - -; Turn on or off clkOpt optimization for code coverage. Default is on. -; CoverClkOpt = 1 - -; Turn on or off clkOpt optimization builtins for code coverage. Default is on. -; CoverClkOptBuiltins = 0 - -; Inform code coverage optimizations to respect VHDL 'H' and 'L' -; values on signals in conditions and expressions, and to not automatically -; convert them to '1' and '0'. Default is to not convert. -; CoverRespectHandL = 0 - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable or disable Focused Expression Coverage analysis for conditions and -; expressions. Focused Expression Coverage data is provided by default when -; expression and/or condition coverage is active. -; CoverFEC = 0 - -; Enable or disable UDP Coverage analysis for conditions and expressions. -; UDP Coverage data is disabled by default when expression and/or condition -; coverage is active. -; CoverUDP = 1 - -; Enable or disable Rapid Expression Coverage mode for conditions and expressions. -; Disabling this would convert non-masking conditions in FEC tables to matching -; input patterns. -; CoverREC = 1 - -; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions -; for expression/condition coverage. -; NOTE: Enabling this may have a negative impact on simulation performance. -; CoverExpandReductionPrefix = 0 - -; Enable or disable short circuit evaluation of conditions and expressions when -; condition or expression coverage is active. Short circuit evaluation is enabled -; by default. -; CoverShortCircuit = 0 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Use this directory for compiler temporary files instead of "work/_temp" -; CompilerTempDir = /tmp - -; Set this to cause the compilers to force data to be committed to disk -; when the files are closed. -; SyncCompilerFiles = 1 - -; Add VHDL-AMS declarations to package STANDARD -; Default is not to add -; AmsStandard = 1 - -; Range and length checking will be performed on array indices and discrete -; ranges, and when violations are found within subprograms, errors will be -; reported. Default is to issue warnings for violations, because subprograms -; may not be invoked. -; NoDeferSubpgmCheck = 0 - -; Turn ON detection of FSMs having single bit current state variable. -; FsmSingle = 1 - -; Turn off reset state transitions in FSM. -; FsmResetTrans = 0 - -; Turn ON detection of FSM Implicit Transitions. -; FsmImplicitTrans = 1 - -; Controls whether or not to show immediate assertions with constant expressions -; in GUI/report/UCDB etc. By default, immediate assertions with constant -; expressions are shown in GUI/report/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Controls how VHDL basic identifiers are stored with the design unit. -; Does not make the language case-sensitive, affects only how declarations -; declared with basic identifiers have their names stored and printed -; (in the GUI, examine, etc.). -; Default is to preserve the case as originally depicted in the VHDL source. -; Value of 0 indicates to change all basic identifiers to lower case. -; PreserveCase = 0 - -; For Configuration Declarations, controls the effect that USE clauses have -; on visibility inside the configuration items being configured. If 1 -; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, -; extend the visibility of objects made visible through USE clauses into nested -; component configurations. -; OldVHDLConfigurationVisibility = 0 - -; Allows VHDL configuration declarations to be in a different library from -; the corresponding configured entity. Default is to not allow this for -; stricter LRM-compliance. -; SeparateConfigLibrary = 1; - -; Determine how mode OUT subprogram parameters of type array and record are treated. -; If 0 (the default), then only VHDL 2008 will do this initialization. -; If 1, always initialize the mode OUT parameter to its default value. -; If 2, do not initialize the mode OUT out parameter. -; Note that prior to release 10.1, all language versions did not initialize mode -; OUT array and record type parameters, unless overridden here via this mechanism. -; In release 10.1 and later, only files compiled with VHDL 2008 will cause this -; initialization, unless overridden here. -; InitOutCompositeParam = 0 - -; Generate symbols debugging database in only some special cases to save on -; the number of files in the library. For other design-units, this database is -; generated on-demand in vsim. -; Default is to to generate debugging database for all design-units. -; SmartDbgSym = 1 - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -; Describe compilation options according to matching file patterns. -; File pattern * matches all printing characters other than '/'. -; File pattern **/x matches all paths containing file/directory x. -; File pattern x/** matches all paths beginning at directory x. -; FileOptMap = (**/*.vhd => -2008); - -; Describe library targets of compilation according to matching file patterns. -; LibMap = (**/*.vhd => work); - -[vlog] -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn off "Loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on Verilog hazard checking (order-dependent accessing of global vars). -; Default is off. -; Hazard = 1 - -; Turn on converting regular Verilog identifiers to uppercase. Allows case -; insensitivity for module names. Default is no conversion. -; UpCase = 1 - -; Activate optimizations on expressions that do not involve signals, -; waits, or function/procedure/task invocations. Default is off. -; ScalarOpts = 1 - -; Turns on lint-style checking. -; Show_Lint = 1 - -; Show source line containing error. Default is off. -; Show_source = 1 - -; Turn on bad option warning. Default is off. -; Show_BadOptionWarning = 1 - -; Revert back to IEEE 1364-1995 syntax, default is 0 (off). -; vlog95compat = 1 - -; Turn off PSL warning messages. Default is to show warnings. -; Show_PslChecksWarnings = 0 - -; Enable parsing of embedded PSL assertions. Default is enabled. -; EmbeddedPsl = 0 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Set the threshold for automatically identifying sparse Verilog memories. -; A memory with total size in bytes equal to or more than the sparse memory -; threshold gets marked as sparse automatically, unless specified otherwise -; in source code or by the +nosparse commandline option of vlog or vopt. -; The default is 1M. (i.e. memories with total size equal -; to or greater than 1Mb are marked as sparse) -; SparseMemThreshold = 1048576 - -; Set the prefix to be honored for synthesis and coverage pragma recognition. -; Default is "". -; AddPragmaPrefix = "" - -; Ignore synthesis and coverage pragmas with this prefix. -; Default is "". -; IgnorePragmaPrefix = "" - -; Set the option to treat all files specified in a vlog invocation as a -; single compilation unit. The default value is set to 0 which will treat -; each file as a separate compilation unit as specified in the P1800 draft standard. -; MultiFileCompilationUnit = 1 - -; Turn on code coverage in Verilog design units. Default is off. -; Coverage = sbceft - -; Automatically exclude Verilog case statement default branches. -; Default is to not automatically exclude defaults. -; CoverExcludeDefault = 1 - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Enable Multi Bit Expression Coverage in a Design, If design has expression with -; multi bit operands, this option enables its Expression Coverage. -; The default value is 0. -; CoverFecMultiBit = 1 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable or disable Focused Expression Coverage analysis for conditions and -; expressions. Focused Expression Coverage data is provided by default when -; expression and/or condition coverage is active. -; CoverFEC = 0 - -; Enable or disable UDP Coverage analysis for conditions and expressions. -; UDP Coverage data is disabled by default when expression and/or condition -; coverage is active. -; CoverUDP = 1 - -; Enable or disable Rapid Expression Coverage mode for conditions and expressions. -; Disabling this would convert non-masking conditions in FEC tables to matching -; input patterns. -; CoverREC = 1 - -; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions -; for expression/condition coverage. -; NOTE: Enabling this may have a negative impact on simulation performance. -; CoverExpandReductionPrefix = 0 - -; Enable or disable short circuit evaluation of conditions and expressions when -; condition or expression coverage is active. Short circuit evaluation is enabled -; by default. -; CoverShortCircuit = 0 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Turn on code coverage in VLOG `celldefine modules, modules containing -; specify blocks, and modules included using vlog -v and -y. Default is off. -; CoverCells = 1 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Control compiler and VOPT optimizations that are allowed when -; code coverage is on. This is a number from 0 to 5, with the following -; meanings (the default is 3): -; 5 -- All allowable optimizations are on. -; 4 -- Turn off removing unreferenced code. -; 3 -- Turn off process, always block and if statement merging. -; 2 -- Turn off expression optimization, converting primitives -; to continuous assignments, VHDL subprogram inlining. -; and VHDL clkOpt (converting FF's to builtins). -; 1 -- Turn off continuous assignment optimizations and clock suppression. -; 0 -- Turn off Verilog module inlining and VHDL arch inlining. -; HOWEVER, if fsm coverage is turned on, optimizations will be forced to -; level 3, with also turning off converting primitives to continuous assigns. -; CoverOpt = 3 - -; Specify the override for the default value of "cross_num_print_missing" -; option for the Cross in Covergroups. If not specified then LRM default -; value of 0 (zero) is used. This is a compile time option. -; SVCrossNumPrintMissingDefault = 0 - -; Setting following to 1 would cause creation of variables which -; would represent the value of Coverpoint expressions. This is used -; in conjunction with "SVCoverpointExprVariablePrefix" option -; in the modelsim.ini -; EnableSVCoverpointExprVariable = 0 - -; Specify the override for the prefix used in forming the variable names -; which represent the Coverpoint expressions. This is used in conjunction with -; "EnableSVCoverpointExprVariable" option of the modelsim.ini -; The default prefix is "expr". -; The variable name is -; variable name => _ -; SVCoverpointExprVariablePrefix = expr - -; Override for the default value of the SystemVerilog covergroup, -; coverpoint, and cross option.goal (defined to be 100 in the LRM). -; NOTE: It does not override specific assignments in SystemVerilog -; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" -; in the [vsim] section can override this value. -; SVCovergroupGoalDefault = 100 - -; Override for the default value of the SystemVerilog covergroup, -; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) -; NOTE: It does not override specific assignments in SystemVerilog -; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" -; in the [vsim] section can override this value. -; SVCovergroupTypeGoalDefault = 100 - -; Specify the override for the default value of "strobe" option for the -; Covergroup Type. This is a compile time option which forces "strobe" to -; a user specified default value and supersedes SystemVerilog specified -; default value of '0'(zero). NOTE: This can be overriden by a runtime -; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. -; SVCovergroupStrobeDefault = 0 - -; Specify the override for the default value of "per_instance" option for the -; Covergroup variables. This is a compile time option which forces "per_instance" -; to a user specified default value and supersedes SystemVerilog specified -; default value of '0'(zero). -; SVCovergroupPerInstanceDefault = 0 - -; Specify the override for the default value of "get_inst_coverage" option for the -; Covergroup variables. This is a compile time option which forces -; "get_inst_coverage" to a user specified default value and supersedes -; SystemVerilog specified default value of '0'(zero). -; SVCovergroupGetInstCoverageDefault = 0 - -; -; A space separated list of resource libraries that contain precompiled -; packages. The behavior is identical to using the "-L" switch. -; -; LibrarySearchPath = [ ...] -LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact - -; The behavior is identical to the "-mixedansiports" switch. Default is off. -; MixedAnsiPorts = 1 - -; Enable SystemVerilog 3.1a $typeof() function. Default is off. -; EnableTypeOf = 1 - -; Only allow lower case pragmas. Default is disabled. -; AcceptLowerCasePragmaOnly = 1 - -; Set the maximum depth permitted for a recursive include file nesting. -; IncludeRecursionDepthMax = 5 - -; Turn ON detection of FSMs having single bit current state variable. -; FsmSingle = 1 - -; Turn off reset state transitions in FSM. -; FsmResetTrans = 0 - -; Turn off detections of FSMs having x-assignment. -; FsmXAssign = 0 - -; Turn ON detection of FSM Implicit Transitions. -; FsmImplicitTrans = 1 - -; List of file suffixes which will be read as SystemVerilog. White space -; in extensions can be specified with a back-slash: "\ ". Back-slashes -; can be specified with two consecutive back-slashes: "\\"; -; SvFileSuffixes = sv svp svh - -; This setting is the same as the vlog -sv command line switch. -; Enables SystemVerilog features and keywords when true (1). -; When false (0), the rules of IEEE Std 1364-2005 are followed and -; SystemVerilog keywords are ignored. -; Svlog = 0 - -; Prints attribute placed upon SV packages during package import -; when true (1). The attribute will be ignored when this -; entry is false (0). The attribute name is "mti_design_element_load_message". -; The value of this attribute is a string literal. -; Default is true (1). -; PrintSVPackageLoadingAttribute = 1 - -; Do not show immediate assertions with constant expressions in -; GUI/reports/UCDB etc. By default immediate assertions with constant -; expressions are shown in GUI/reports/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Controls if untyped parameters that are initialized with values greater -; than 2147483647 are mapped to generics of type INTEGER or ignored. -; If mapped to VHDL Integers, values greater than 2147483647 -; are mapped to negative values. -; Default is to map these parameter to generic of type INTEGER -; ForceUnsignedToVHDLInteger = 1 - -; Enable AMS wreal (wired real) extensions. Default is 0. -; WrealType = 1 - -; Controls SystemVerilog Language Extensions. These options enable -; some non-LRM compliant behavior. -; SvExtensions = [+|-][,[+|-]*] - -; Generate symbols debugging database in only some special cases to save on -; the number of files in the library. For other design-units, this database is -; generated on-demand in vsim. -; Default is to to generate debugging database for all design-units. -; SmartDbgSym = 1 - -; Controls how $unit library entries are named. Valid options are: -; "file" (generate name based on the first file on the command line) -; "du" (generate name based on first design unit following an item -; found in $unit scope) -; CUAutoName = file - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -[sccom] -; Enable use of SCV include files and library. Default is off. -; UseScv = 1 - -; Add C++ compiler options to the sccom command line by using this variable. -; CppOptions = -g - -; Use custom C++ compiler located at this path rather than the default path. -; The path should point directly at a compiler executable. -; CppPath = /usr/bin/g++ - -; Specify the compiler version from the list of support GNU compilers. -; examples 4.7.4, 5.3.0, 7.4.0 -; CppInstall = 7.4.0 - -; Enable verbose messages from sccom. Default is off. -; SccomVerbose = 1 - -; sccom logfile. Default is no logfile. -; SccomLogfile = sccom.log - -; Enable use of SC_MS include files and library. Default is off. -; UseScMs = 1 - -; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. -; Sc22Mode = 1 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -; Enable use of UVMC library. Default is off. -; UseUvmc = 1 - -[vopt] -; Turn on code coverage in vopt. Default is off. -; Coverage = sbceft - -; enable or disable param saving in UCDB. -; CoverageSaveParam = 0 - -; Control compiler optimizations that are allowed when -; code coverage is on. Refer to the comment for this in the [vlog] area. -; CoverOpt = 3 - -; Controls set of CoverConstructs that are being considered for Coverage -; Collection. -; Some of Valid options are: default,set1,set2 -; Covermode = default - -; Controls set of HDL cover constructs that would be considered(or not considered) -; for Coverage Collection. (Default corresponds to covermode default). -; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". -; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Enable Multi Bit Expression Coverage in a Design, If design has expression with -; multi bit operands, this option enables its Expression Coverage. -; The default value is 0. -; CoverFecMultiBit = 1 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Do not show immediate assertions with constant expressions in -; GUI/reports/UCDB etc. By default immediate assertions with constant -; expressions are shown in GUI/reports/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Set the maximum number of iterations permitted for a generate loop. -; Restricting this permits the implementation to recognize infinite -; generate loops. -; GenerateLoopIterationMax = 100000 - -; Set the maximum depth permitted for a recursive generate instantiation. -; Restricting this permits the implementation to recognize infinite -; recursions. -; GenerateRecursionDepthMax = 200 - -; Set the number of processes created during the code generation phase. -; By default a heuristic is used to set this value. This may be set to 0 -; to disable this feature completely. -; ParallelJobs = 0 - -; Controls SystemVerilog Language Extensions. These options enable -; some non-LRM compliant behavior. -; SvExtensions = [+|-][,[+|-]*] - -; Load the specified shared objects with the RTLD_GLOBAL flag. -; This gives global visibility to all symbols in the shared objects, -; meaning that subsequently loaded shared objects can bind to symbols -; in the global shared objects. The list of shared objects should -; be whitespace delimited. This option is not supported on the -; Windows or AIX platforms. -; GlobalSharedObjectList = example1.so example2.so example3.so - -; Disable SystemVerilog elaboration system task messages -; IgnoreSVAInfo = 1 -; IgnoreSVAWarning = 1 -; IgnoreSVAError = 1 -; IgnoreSVAFatal = 1 - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -[vsim] -; vopt flow -; Set to turn on automatic optimization of a design. -; Default is on -VoptFlow = 1 - -; Simulator resolution -; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. -Resolution = fs - -; Disable certain code coverage exclusions automatically. -; Assertions and FSM are exluded from the code coverage by default -; Set AutoExclusionsDisable = fsm to enable code coverage for fsm -; Set AutoExclusionsDisable = assertions to enable code coverage for assertions -; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions -; Or specify comma or space separated list -;AutoExclusionsDisable = fsm,assertions - -; User time unit for run commands -; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the -; unit specified for Resolution. For example, if Resolution is 100ps, -; then UserTimeUnit defaults to ps. -; Should generally be set to default. -UserTimeUnit = default - -; Default run length -RunLength = 100 - -; Maximum iterations that can be run without advancing simulation time -IterationLimit = 10000000 - -; Specify libraries to be searched for precompiled modules -; LibrarySearchPath = [ ...] - -; Set XPROP assertion fail limit. Default is 5. -; Any positive integer, -1 for infinity. -; XpropAssertionLimit = 5 - -; Control PSL and Verilog Assume directives during simulation -; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts -; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts -; SimulateAssumeDirectives = 1 - -; Control the simulation of PSL and SVA -; These switches can be overridden by the vsim command line switches: -; -psl, -nopsl, -sva, -nosva. -; Set SimulatePSL = 0 to disable PSL simulation -; Set SimulatePSL = 1 to enable PSL simulation (default) -; SimulatePSL = 1 -; Set SimulateSVA = 0 to disable SVA simulation -; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) -; SimulateSVA = 1 - -; Control SVA and VHDL immediate assertion directives during simulation -; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts -; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts -; SimulateImmedAsserts = 1 - -; License feature mappings for Verilog and VHDL -; qhsimvh Single language VHDL license -; qhsimvl Single language Verilog license -; msimhdlsim Language neutral license for either Verilog or VHDL -; msimhdlmix Second language only, language neutral license for either -; Verilog or VHDL -; -; Directives to license manager can be set either as single value or as -; space separated multi-values: -; vhdl Immediately checkout and hold a VHDL license (i.e., one of -; qhsimvh, msimhdlsim, or msimhdlmix) -; vlog Immediately checkout and hold a Verilog license (i.e., one of -; qhsimvl, msimhdlsim, or msimhdlmix) -; plus Immediately checkout and hold a VHDL license and a Verilog license -; noqueue Do not wait in the license queue when a license is not available -; viewsim Try for viewer license but accept simulator license(s) instead -; of queuing for viewer license (PE ONLY) -; noviewer Disable checkout of msimviewer license feature (PE ONLY) -; noslvhdl Disable checkout of qhsimvh license feature -; noslvlog Disable checkout of qhsimvl license feature -; nomix Disable checkout of msimhdlmix license feature -; nolnl Disable checkout of msimhdlsim license feature -; mixedonly Disable checkout of qhsimvh and qhsimvl license features -; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features -; -; Examples (remove ";" comment character to activate licensing directives): -; Single directive: -; License = plus -; Multi-directive (Note: space delimited directives): -; License = noqueue plus - -; Severity level of a VHDL assertion message or of a SystemVerilog severity system task -; which will cause a running simulation to stop. -; VHDL assertions and SystemVerilog severity system task that occur with the -; given severity or higher will cause a running simulation to stop. -; This value is ignored during elaboration. -; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal -BreakOnAssertion = 3 - -; Severity level of a tool message which will cause a running simulation to -; stop. This value is ignored during elaboration. Default is to not break. -; 0 = Note 1 = Warning 2 = Error 3 = Fatal -;BreakOnMessage = 2 - -; The class debug feature enables more visibility and tracking of class instances -; during simulation. By default this feature is disabled (0). To enable this -; feature set ClassDebug to 1. -; ClassDebug = 1 - -; Message Format conversion specifications: -; %S - Severity Level of message/assertion -; %R - Text of message -; %T - Time of message -; %D - Delta value (iteration number) of Time -; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected -; %i - Instance/Region/Signal pathname with Process name (if available) -; %I - shorthand for one of these: -; " %K: %i" -; " %K: %i File: %F" (when path is not Process or Signal) -; except that the %i in this case does not report the Process name -; %O - Process name -; %P - Instance/Region path without leaf process -; %F - File name -; %L - Line number; if assertion message, then line number of assertion or, if -; assertion is in a subprogram, line from which the call is made -; %u - Design unit name in form library.primary -; %U - Design unit name in form library.primary(secondary) -; %% - The '%' character itself -; -; If specific format for Severity Level is defined, use that format. -; Else, for a message that occurs during elaboration: -; -- Failure/Fatal message in VHDL region that is not a Process, and in -; certain non-VHDL regions, uses MessageFormatBreakLine; -; -- Failure/Fatal message otherwise uses MessageFormatBreak; -; -- Note/Warning/Error message uses MessageFormat. -; Else, for a message that occurs during runtime and triggers a breakpoint because -; of the BreakOnAssertion setting: -; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; -; -- otherwise uses MessageFormatBreak. -; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. -; -; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" -; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" -; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" -; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" - -; Error File - alternate file for storing error messages -; ErrorFile = error.log - -; Simulation Breakpoint messages -; This flag controls the display of function names when reporting the location -; where the simulator stops because of a breakpoint or fatal error. -; Example with function name: # Break in Process ctr at counter.vhd line 44 -; Example without function name: # Break at counter.vhd line 44 -; Default value is 1. -ShowFunctions = 1 - -; Default radix for all windows and commands. -; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned -; Flags may be one of: enumnumeric, showbase, wreal -DefaultRadix = hexadecimal -DefaultRadixFlags = showbase -; Set to 1 for make the signal_force VHDL and Verilog functions use the -; default radix when processing the force value. Prior to 10.2 signal_force -; used the default radix, now it always uses symbolic unless value explicitly indicates base -;SignalForceFunctionUseDefaultRadix = 0 - -; VSIM Startup command -; Startup = do startup.do - -; VSIM Shutdown file -; Filename to save u/i formats and configurations. -; ShutdownFile = restart.do -; To explicitly disable auto save: -; ShutdownFile = --disable-auto-save - -; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. -; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. -; BatchMode = 1 - -; File for saving command transcript when -batch option used -; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero -; default is unset so command transcript only goes to stdout for better performance -; BatchTranscriptFile = transcript - -; File for saving command transcript, this option is ignored when -batch option is used -TranscriptFile = transcript - -; Transcript file long line wrapping mode(s) -; mode == 0 :: no wrapping, line recorded as is -; mode == 1 :: wrap at first whitespace after WSColumn -; or at Column. -; mode == 2 :: wrap as above, but add continuation -; character ('\') at end of each wrapped line -; -; WrapMode = 0 -; WrapColumn = 30000 -; WrapWSColumn = 27000 - -; File for saving command history -; CommandHistory = cmdhist.log - -; Specify whether paths in simulator commands should be described -; in VHDL or Verilog format. -; For VHDL, PathSeparator = / -; For Verilog, PathSeparator = . -; Must not be the same character as DatasetSeparator. -PathSeparator = / - -; Specify the dataset separator for fully rooted contexts. -; The default is ':'. For example: sim:/top -; Must not be the same character as PathSeparator. -DatasetSeparator = : - -; Specify a unique path separator for the Signal Spy set of functions. -; The default will be to use the PathSeparator variable. -; Must not be the same character as DatasetSeparator. -; SignalSpyPathSeparator = / - -; Used to control parsing of HDL identifiers input to the tool. -; This includes CLI commands, vsim/vopt/vlog/vcom options, -; string arguments to FLI/VPI/DPI calls, etc. -; If set to 1, accept either Verilog escaped Id syntax or -; VHDL extended id syntax, regardless of source language. -; If set to 0, the syntax of the source language must be used. -; Each identifier in a hierarchical name may need different syntax, -; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or -; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" -; GenerousIdentifierParsing = 1 - -; Disable VHDL assertion messages -; IgnoreNote = 1 -; IgnoreWarning = 1 -; IgnoreError = 1 -; IgnoreFailure = 1 - -; Disable SystemVerilog assertion messages -; IgnoreSVAInfo = 1 -; IgnoreSVAWarning = 1 -; IgnoreSVAError = 1 -; IgnoreSVAFatal = 1 - -; Do not print any additional information from Severity System tasks. -; Only the message provided by the user is printed along with severity -; information. -; SVAPrintOnlyUserMessage = 1; - -; Default force kind. May be freeze, drive, deposit, or default -; or in other terms, fixed, wired, or charged. -; A value of "default" will use the signal kind to determine the -; force kind, drive for resolved signals, freeze for unresolved signals -; DefaultForceKind = freeze - -; Control the iteration of events when a VHDL signal is forced to a value -; This flag can be set to honour the signal update event in next iteration, -; the default is to update and propagate in the same iteration. -; ForceSigNextIter = 1 - -; Enable simulation statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; If zero, open files when elaborated; otherwise, open files on -; first read or write. Default is 0. -; DelayFileOpen = 1 - -; Control VHDL files opened for write. -; 0 = Buffered, 1 = Unbuffered -UnbufferedOutput = 0 - -; Control the number of VHDL files open concurrently. -; This number should always be less than the current ulimit -; setting for max file descriptors. -; 0 = unlimited -ConcurrentFileLimit = 40 - -; If nonzero, close files as soon as there is either an explicit call to -; file_close, or when the file variable's scope is closed. When zero, a -; file opened in append mode is not closed in case it is immediately -; reopened in append mode; otherwise, the file will be closed at the -; point it is reopened. -; AppendClose = 1 - -; Control the number of hierarchical regions displayed as -; part of a signal name shown in the Wave window. -; A value of zero tells VSIM to display the full name. -; The default is 0. -; WaveSignalNameWidth = 0 - -; Turn off warnings when changing VHDL constants and generics -; Default is 1 to generate warning messages -; WarnConstantChange = 0 - -; Turn off warnings from accelerated versions of the std_logic_arith, -; std_logic_unsigned, and std_logic_signed packages. -; StdArithNoWarnings = 1 - -; Turn off warnings from accelerated versions of the IEEE numeric_std -; and numeric_bit packages. -; NumericStdNoWarnings = 1 - -; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names -; in the design hierarchy. -; This style is controlled by the value of the GenerateFormat -; value described next. Default is to use new-style names, which -; comprise the generate statement label, '(', the value of the generate -; parameter, and a closing ')'. -; Set this to 1 to use old-style names. -; OldVhdlForGenNames = 1 - -; Control the format of the old-style VHDL FOR generate statement region -; name for each iteration. Do not quote the value. -; The format string here must contain the conversion codes %s and %d, -; in that order, and no other conversion codes. The %s represents -; the generate statement label; the %d represents the generate parameter value -; at a particular iteration (this is the position number if the generate parameter -; is of an enumeration type). Embedded whitespace is allowed (but discouraged); -; leading and trailing whitespace is ignored. -; Application of the format must result in a unique region name over all -; loop iterations for a particular immediately enclosing scope so that name -; lookup can function properly. The default is %s__%d. -; GenerateFormat = %s__%d - -; Enable more efficient logging of VHDL Variables. -; Logging VHDL variables without this enabled, while possible, is very -; inefficient. Enabling this will provide a more efficient logging methodology -; at the expense of more memory usage. By default this feature is disabled (0). -; To enabled this feature, set this variable to 1. -; VhdlVariableLogging = 1 - -; Enable logging of VHDL access type variables and their designated objects. -; This setting will allow both variables of an access type ("access variables") -; and their designated objects ("access objects") to be logged. Logging a -; variable of an access type will automatically also cause the designated -; object(s) of that variable to be logged as the simulation progresses. -; Further, enabling this allows access objects to be logged by name. By default -; this feature is disabled (0). To enable this feature, set this variable to 1. -; Enabling this will automatically enable the VhdlVariableLogging feature also. -; AccessObjDebug = 1 - -; Make each VHDL package in a PDU has its own separate copy of the package instead -; of sharing the package between PDUs. The default is to share packages. -; To ensure that each PDU has its own set of packages, set this variable to 1. -; VhdlSeparatePduPackage = 1 - -; Specify whether checkpoint files should be compressed. -; The default is 1 (compressed). -; CheckpointCompressMode = 0 - -; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. -; Use custom gcc compiler located at this path rather than the default path. -; The path should point directly at a compiler executable. -; DpiCppPath = /bin/gcc -; -; Specify the compiler version from the list of support GNU compilers. -; examples 4.7.4, 5.3.0, 7.4.0 -; DpiCppInstall = 7.4.0 - -; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. -; The term "out-of-the-blue" refers to SystemVerilog export function calls -; made from C functions that don't have the proper context setup -; (as is the case when running under "DPI-C" import functions). -; When this is enabled, one can call a DPI export function -; (but not task) from any C code. -; the setting of this variable can be one of the following values: -; 0 : dpioutoftheblue call is disabled (default) -; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. -; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. -; DpiOutOfTheBlue = 1 - -; Specify whether continuous assignments are run before other normal priority -; processes scheduled in the same iteration. This event ordering minimizes race -; differences between optimized and non-optimized designs, and is the default -; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set -; ImmediateContinuousAssign to 0. -; The default is 1 (enabled). -; ImmediateContinuousAssign = 0 - -; List of dynamically loaded objects for Verilog PLI applications -; Veriuser = veriuser.sl - -; Which default VPI object model should the tool conform to? -; The 1364 modes are Verilog-only, for backwards compatibility with older -; libraries, and SystemVerilog objects are not available in these modes. -; -; In the absence of a user-specified default, the tool default is the -; latest available LRM behavior. -; Options for PliCompatDefault are: -; VPI_COMPATIBILITY_VERSION_1364v1995 -; VPI_COMPATIBILITY_VERSION_1364v2001 -; VPI_COMPATIBILITY_VERSION_1364v2005 -; VPI_COMPATIBILITY_VERSION_1800v2005 -; VPI_COMPATIBILITY_VERSION_1800v2008 -; -; Synonyms for each string are also recognized: -; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) -; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) -; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) -; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) -; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) - - -; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 - -; Specify whether the Verilog system task $fopen or vpi_mcd_open() -; will create directories that do not exist when opening the file -; in "a" or "w" mode. -; The default is 0 (do not create non-existent directories) -; CreateDirForFileAccess = 1 - -; Specify default options for the restart command. Options can be one -; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions -; DefaultRestartOptions = -force - - -; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. -; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. -; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". -; The list of options must be delimited by commas, without spaces or tabs. -; -; Some examples -; To turn on all available UVM-aware debug features: -; UVMControl = all -; To turn on the struct window, mesage logging, and transaction logging: -; UVMControl = struct,msglog,trlog -; To turn on all options except certe: -; UVMControl = all,-certe -; To completely disable all UVM-aware debug functionality: -; UVMControl = disable - -; Specify the WildcardFilter setting. -; A space separated list of object types to be excluded when performing -; wildcard matches with log, wave, etc commands. The default value for this variable is: -; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" -; See "Using the WildcardFilter Preference Variable" in the documentation for -; details on how to use this variable and for descriptions of the filter types. -WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile - -; Specify the WildcardSizeThreshold setting. -; This integer setting specifies the size at which objects will be excluded when -; performing wildcard matches with log, wave, etc commands. Objects of size equal -; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard -; matches. The size is a simple calculation of number of bits or items in the object. -; The default value is 8k (8192). Setting this value to 0 will disable the checking -; of object size against this threshold and allow all objects of any size to be logged. -WildcardSizeThreshold = 8192 - -; Specify whether warning messages are output when objects are filtered out due to the -; WildcardSizeThreshold. The default is 0 (no messages generated). -WildcardSizeThresholdVerbose = 0 - -; Turn on (1) or off (0) WLF file compression. -; The default is 1 (compress WLF file). -; WLFCompress = 0 - -; Specify whether to save all design hierarchy (1) in the WLF file -; or only regions containing logged signals (0). -; The default is 0 (save only regions with logged signals). -; WLFSaveAllRegions = 1 - -; WLF file time limit. Limit WLF file by time, as closely as possible, -; to the specified amount of simulation time. When the limit is exceeded -; the earliest times get truncated from the file. -; If both time and size limits are specified the most restrictive is used. -; UserTimeUnits are used if time units are not specified. -; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} -; WLFTimeLimit = 0 - -; WLF file size limit. Limit WLF file size, as closely as possible, -; to the specified number of megabytes. If both time and size limits -; are specified then the most restrictive is used. -; The default is 0 (no limit). -; WLFSizeLimit = 1000 - -; Specify whether or not a WLF file should be deleted when the -; simulation ends. A value of 1 will cause the WLF file to be deleted. -; The default is 0 (do not delete WLF file when simulation ends). -; WLFDeleteOnQuit = 1 - -; Specify whether or not a WLF file should be optimized during -; simulation. If set to 0, the WLF file will not be optimized. -; The default is 1, optimize the WLF file. -; WLFOptimize = 0 - -; Specify the name of the WLF file. -; The default is vsim.wlf -; WLFFilename = vsim.wlf - -; Specify whether to lock the WLF file. -; Locking the file prevents other invocations of ModelSim/Questa tools from -; inadvertently overwriting the WLF file. -; The default is 1, lock the WLF file. -; WLFFileLock = 0 - -; Specify the update interval for the WLF file in live simulation. -; The interval is given in seconds. -; The value is the smallest interval between WLF file updates. The WLF file -; will be flushed (updated) after (at least) the interval has elapsed, ensuring -; that the data is correct when viewed from a separate viewer. -; A value of 0 means that no updating will occur. -; The default value is 10 seconds. -; WLFUpdateInterval = 10 - -; Specify the WLF cache size limit for WLF files. -; The value is given in megabytes. A value of 0 turns off the cache. -; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). -; On Windows, the default value is 1000 (megabytes) to help to avoid filling -; process memory. -; WLFSimCacheSize allows a different cache size to be set for a live simulation -; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize -; is not set, it defaults to the WLFCacheSize value. -; WLFCacheSize = 2000 -; WLFSimCacheSize = 500 - -; Specify the WLF file event collapse mode. -; 0 = Preserve all events and event order. (same as -wlfnocollapse) -; 1 = Only record values of logged objects at the end of a simulator iteration. -; (same as -wlfcollapsedelta) -; 2 = Only record values of logged objects at the end of a simulator time step. -; (same as -wlfcollapsetime) -; The default is 1. -; WLFCollapseMode = 0 - -; Specify whether WLF file logging can use threads on multi-processor machines. -; If 0, no threads will be used; if 1, threads will be used if the system has -; more than one processor. -; WLFUseThreads = 1 - -; Specify the size of objects that will trigger "large object" messages -; at log/wave/list time. The size calculation of the object is the same as that -; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. -; Setting LargeObjectSize to 0 will disable these messages. -; LargeObjectSize = 500000 - -; Specify the depth of stack frames returned by $stacktrace([level]). -; This depth will be picked up when the optional 'level' argument -; is not specified or its value is not a positive integer. -; StackTraceDepth = 100 - -; Turn on/off undebuggable SystemC type warnings. Default is on. -; ShowUndebuggableScTypeWarning = 0 - -; Turn on/off unassociated SystemC name warnings. Default is off. -; ShowUnassociatedScNameWarning = 1 - -; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. -; ScShowIeeeDeprecationWarnings = 1 - -; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. -; For SystemC-2.3.2 the valid values are 0,1 and 2 -; 0 = SC_SIGNAL_WRITE_CHECK_DISABLE_ -; 1 = SC_SIGNAL_WRITE_CHECK_DEFAULT_ -; 2 = SC_SIGNAL_WRITE_CHECK_CONFLICT_ -; For SystemC-2.2 the valid values are 0 and 1 -; 0 = DISABLE -; 1 = ENABLE -; ScEnableScSignalWriteCheck = 1 - -; Set SystemC default time unit. -; Set to fs, ps, ns, us, ms, or sec with optional -; prefix of 1, 10, or 100. The default is 1 ns. -; The ScTimeUnit value is honored if it is coarser than Resolution. -; If ScTimeUnit is finer than Resolution, it is set to the value -; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, -; then the default time unit will be 1 ns. However if Resolution -; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. -ScTimeUnit = ns - -; Set SystemC sc_main stack size. The stack size is set as an integer -; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or -; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends -; on the amount of data on the sc_main() stack and the memory required -; to succesfully execute the longest function call chain of sc_main(). -ScMainStackSize = 10 Mb - -; Set SystemC thread stack size. The stack size is set as an integer -; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or -; Gb(Giga-byte). The stack size for sc_thread depends -; on the amount of data on the sc_thread stack and the memory required -; to succesfully execute the thread. -; ScStackSize = 1 Mb - -; Turn on/off execution of remainder of sc_main upon quitting the current -; simulation session. If the cumulative length of sc_main() in terms of -; simulation time units is less than the length of the current simulation -; run upon quit or restart, sc_main() will be in the middle of execution. -; This switch gives the option to execute the remainder of sc_main upon -; quitting simulation. The drawback of not running sc_main till the end -; is memory leaks for objects created by sc_main. If on, the remainder of -; sc_main will be executed ignoring all delays. This may cause the simulator -; to crash if the code in sc_main is dependent on some simulation state. -; Default is on. -ScMainFinishOnQuit = 1 - -; Enable calling of the DPI export taks/functions from the -; SystemC start_of_simulation() callback. -; The default is off. -; EnableDpiSosCb = 1 - - -; Set the SCV relationship name that will be used to identify phase -; relations. If the name given to a transactor relation matches this -; name, the transactions involved will be treated as phase transactions -ScvPhaseRelationName = mti_phase - -; Customize the vsim kernel shutdown behavior at the end of the simulation. -; Some common causes of the end of simulation are $finish (implicit or explicit), -; sc_stop(), tf_dofinish(), and assertion failures. -; This should be set to "ask", "exit", or "stop". The default is "ask". -; "ask" -- In batch mode, the vsim kernel will abruptly exit. -; In GUI mode, a dialog box will pop up and ask for user confirmation -; whether or not to quit the simulation. -; "stop" -- Cause the simulation to stay loaded in memory. This can make some -; post-simulation tasks easier. -; "exit" -- The simulation will abruptly exit without asking for any confirmation. -; "final" -- Run SystemVerilog final blocks then behave as "stop". -; Note: This variable can be overridden with the vsim "-onfinish" command line switch. -OnFinish = ask - -; Print pending deferred assertion messages. -; Deferred assertion messages may be scheduled after the $finish in the same -; time step. Deferred assertions scheduled to print after the $finish are -; printed before exiting with severity level NOTE since it's not known whether -; the assertion is still valid due to being printed in the active region -; instead of the reactive region where they are normally printed. -; OnFinishPendingAssert = 1; - -; Print "simstats" result. Default is 0. -; 0 == do not print simstats -; 1 == print at end of simulation -; 2 == print at end of each run command and end of simulation -; PrintSimStats = 1 - -; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages -; AssertFile = assert.log - -; Enable assertion counts. Default is off. -; AssertionCounts = 1 - -; Run simulator in assertion debug mode. Default is off. -; AssertionDebug = 1 - -; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. -; AssertionEnable = 0 - -; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. -; Any positive integer, -1 for infinity. -; AssertionLimit = 1 - -; Turn on/off concurrent assertion pass log. Default is off. -; Assertion pass logging is only enabled when assertion is browseable -; and assertion debug is enabled. -; AssertionPassLog = 1 - -; Turn on/off PSL concurrent assertion fail log. Default is on. -; The flag does not affect SVA -; AssertionFailLog = 0 - -; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. -; AssertionFailLocalVarLog = 0 - -; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. -; 0 = Continue 1 = Break 2 = Exit -; AssertionFailAction = 1 - -; Enable the active thread monitor in the waveform display when assertion debug is enabled. -; AssertionActiveThreadMonitor = 1 - -; Control how many waveform rows will be used for displaying the active threads. Default is 5. -; AssertionActiveThreadMonitorLimit = 5 - -; Assertion thread limit after which assertion would be killed/switched off. -; The default is -1 (unlimited). If the number of threads for an assertion go -; beyond this limit, the assertion would be either switched off or killed. This -; limit applies to only assert directives. -;AssertionThreadLimit = -1 - -; Action to be taken once the assertion thread limit is reached. Default -; is kill. It can have a value of off or kill. In case of kill, all the existing -; threads are terminated and no new attempts are started. In case of off, the -; existing attempts keep on evaluating but no new attempts are started. This -; variable applies to only assert directives. -;AssertionThreadLimitAction = kill - -; Cover thread limit after which cover would be killed/switched off. -; The default is -1 (unlimited). If the number of threads for a cover go -; beyond this limit, the cover would be either switched off or killed. This -; limit applies to only cover directives. -;CoverThreadLimit = -1 - -; Action to be taken once the cover thread limit is reached. Default -; is kill. It can have a value of off or kill. In case of kill, all the existing -; threads are terminated and no new attempts are started. In case of off, the -; existing attempts keep on evaluating but no new attempts are started. This -; variable applies to only cover directives. -;CoverThreadLimitAction = kill - - -; By default immediate assertions do not participate in Assertion Coverage calculations -; unless they are executed. This switch causes all immediate assertions in the design -; to participate in Assertion Coverage calculations, whether attempted or not. -; UnattemptedImmediateAssertions = 0 - -; By default immediate covers participate in Coverage calculations -; whether they are attempted or not. This switch causes all unattempted -; immediate covers in the design to stop participating in Coverage -; calculations. -; UnattemptedImmediateCovers = 0 - -; By default pass action block is not executed for assertions on vacuous -; success. The following variable is provided to enable execution of -; pass action block on vacuous success. The following variable is only effective -; if the user does not disable pass action block execution by using either -; system tasks or CLI. Also there is a performance penalty for enabling -; the following variable. -;AssertionEnableVacuousPassActionBlock = 1 - -; As per strict 1850-2005 PSL LRM, an always property can either pass -; or fail. However, by default, Questa reports multiple passes and -; multiple fails on top always/never property (always/never operator -; is the top operator under Verification Directive). The reason -; being that Questa reports passes and fails on per attempt of the -; top always/never property. Use the following flag to instruct -; Questa to strictly follow LRM. With this flag, all assert/never -; directives will start an attempt once at start of simulation. -; The attempt can either fail, match or match vacuously. -; For e.g. if always is the top operator under assert, the always will -; keep on checking the property at every clock. If the property under -; always fails, the directive will be considered failed and no more -; checking will be done for that directive. A top always property, -; if it does not fail, will show a pass at end of simulation. -; The default value is '0' (i.e. zero is off). For example: -; PslOneAttempt = 1 - -; Specify the number of clock ticks to represent infinite clock ticks. -; This affects eventually!, until! and until_!. If at End of Simulation -; (EOS) an active strong-property has not clocked this number of -; clock ticks then neither pass or fail (vacuous match) is returned -; else respective fail/pass is returned. The default value is '0' (zero) -; which effectively does not check for clock tick condition. For example: -; PslInfinityThreshold = 5000 - -; Control how many thread start times will be preserved for ATV viewing for a given assertion -; instance. Default is -1 (ALL). -; ATVStartTimeKeepCount = -1 - -; Turn on/off code coverage -; CodeCoverage = 0 - -; This option applies to condition and expression coverage UDP tables. It -; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. -; If this option is used and a match occurs in more than one row in the UDP table, -; none of the counts for all matching rows is incremented. By default, counts are -; incremented for all matching rows. -; CoverCountAll = 1 - -; Turn off automatic inclusion of VHDL integers in toggle coverage. Default -; is to include them. -; ToggleNoIntegers = 1 - -; Set the maximum number of values that are collected for toggle coverage of -; VHDL integers. Default is 100; -; ToggleMaxIntValues = 100 - -; Set the maximum number of values that are collected for toggle coverage of -; Verilog real. Default is 100; -; ToggleMaxRealValues = 100 - -; Turn on automatic inclusion of Verilog integers in toggle coverage, except -; for enumeration types. Default is to include them. -; ToggleVlogIntegers = 0 - -; Turn on automatic inclusion of Verilog real type in toggle coverage, except -; for shortreal types. Default is to not include them. -; ToggleVlogReal = 1 - -; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays -; and VHDL arrays-of-arrays in toggle coverage. -; Default is to not include them. -; ToggleFixedSizeArray = 1 - -; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, -; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. -; This leads to a longer simulation time with bigger arrays covered with toggle coverage. -; Default is 1024. -; ToggleMaxFixedSizeArray = 1024 - -; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized -; one-dimensional packed vectors for toggle coverage. Default is 0. -; TogglePackedAsVec = 0 - -; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for -; toggle coverage. Default is 0. -; ToggleVlogEnumBits = 0 - -; Turn off automatic inclusion of VHDL records in toggle coverage. -; Default is to include them. -; ToggleVHDLRecords = 0 - -; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. -; For unlimited width, set to 0. -; ToggleWidthLimit = 128 - -; Limit the counts that are tracked for toggle coverage. When all edges for a bit have -; reached this count, further activity on the bit is ignored. Default is 1. -; For unlimited counts, set to 0. -; ToggleCountLimit = 1 - -; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. -; Following is the toggle coverage calculation criteria based on extended toggle mode: -; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). -; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. -; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. -; ExtendedToggleMode = 3 - -; Enable toggle statistics collection only for ports. Default is 0. -; TogglePortsOnly = 1 - -; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has -; reached this count, further tracking of the input patterns linked to it is ignored. -; Default is 1. For unlimited counts, set to 0. -; NOTE: Changing this value from its default value may affect simulation performance. -; FecCountLimit = 1 - -; Limit the counts that are tracked for UDP Coverage. When a bin has -; reached this count, further tracking of the input patterns linked to it is ignored. -; Default is 1. For unlimited counts, set to 0. -; NOTE: Changing this value from its default value may affect simulation performance. -; UdpCountLimit = 1 - -; Control toggle coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either -; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; ToggleDeglitchPeriod = 10.0ps - -; Turn on/off all PSL/SVA cover directive enables. Default is on. -; CoverEnable = 0 - -; Turn on/off PSL/SVA cover log. Default is off "0". -; CoverLog = 1 - -; Set "at_least" value for all PSL/SVA cover directives. Default is 1. -; CoverAtLeast = 2 - -; Set "limit" value for all PSL/SVA cover directives. Default is -1. -; Any positive integer, -1 for infinity. -; CoverLimit = 1 - -; Specify the coverage database filename. -; Default is "" (i.e. database is NOT automatically saved on close). -; UCDBFilename = vsim.ucdb - -; Specify the maximum limit for the number of Cross (bin) products reported -; in XML and UCDB report against a Cross. A warning is issued if the limit -; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this -; setting. -; MaxReportRhsSVCrossProducts = 1000 - -; Specify the override for the "auto_bin_max" option for the Covergroups. -; If not specified then value from Covergroup "option" is used. -; SVCoverpointAutoBinMax = 64 - -; Specify the override for the value of "cross_num_print_missing" -; option for the Cross in Covergroups. If not specified then value -; specified in the "option.cross_num_print_missing" is used. This -; is a runtime option. NOTE: This overrides any "cross_num_print_missing" -; value specified by user in source file and any SVCrossNumPrintMissingDefault -; specified in modelsim.ini. -; SVCrossNumPrintMissing = 0 - -; Specify whether to use the value of "cross_num_print_missing" -; option in report and GUI for the Cross in Covergroups. If not specified then -; cross_num_print_missing is ignored for creating reports and displaying -; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". -; UseSVCrossNumPrintMissing = 0 - -; Specify the threshold of Coverpoint wildcard bin value range size, above which -; a warning will be triggered. The default is 4K -- 12 wildcard bits. -; SVCoverpointWildCardBinValueSizeWarn = 4096 - -; Specify the override for the value of "strobe" option for the -; Covergroup Type. If not specified then value in "type_option.strobe" -; will be used. This is runtime option which forces "strobe" to -; user specified value and supersedes user specified values in the -; SystemVerilog Code. NOTE: This also overrides the compile time -; default value override specified using "SVCovergroupStrobeDefault" -; SVCovergroupStrobe = 0 - -; Override for explicit assignments in source code to "option.goal" of -; SystemVerilog covergroup, coverpoint, and cross. It also overrides the -; default value of "option.goal" (defined to be 100 in the SystemVerilog -; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". -; SVCovergroupGoal = 100 - -; Override for explicit assignments in source code to "type_option.goal" of -; SystemVerilog covergroup, coverpoint, and cross. It also overrides the -; default value of "type_option.goal" (defined to be 100 in the SystemVerilog -; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". -; SVCovergroupTypeGoal = 100 - -; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() -; builtin functions, and report. This setting changes the default values of -; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 -; behavior if explicit assignments are not made on option.get_inst_coverage and -; type_option.merge_instances by the user. There are two vsim command line -; options, -cvg63 and -nocvg63 to override this setting from vsim command line. -; The default value of this variable from release 6.6 onwards is 0. This default -; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. -; SVCovergroup63Compatibility = 0 - -; Enforce the default behavior of covergroup get_coverage() builtin function, GUI -; and report. This variable sets the default value of type_option.merge_instances. -; There are two vsim command line options, -cvgmergeinstances and -; -nocvgmergeinstances to override this setting from vsim command line. -; The default value of this variable, -1 (don't care), allows the tool to determine -; the effective value, based on factors related to capacity and optimization. -; The type_option.merge_instances appears in the GUI and coverage reports as either -; auto(1) or auto(0), depending on whether the effective value was determined to -; be a 1 or a 0. -; SVCovergroupMergeInstancesDefault = -1 - -; Enable or disable generation of more detailed information about the sampling -; of covergroup, cross, and coverpoints. It provides the details of the number -; of times the covergroup instance and type were sampled, as well as details -; about why covergroup, cross and coverpoint were not covered. A non-zero value -; is to enable this feature. 0 is to disable this feature. Default is 0 -; SVCovergroupSampleInfo = 0 - -; Specify the maximum number of Coverpoint bins in whole design for -; all Covergroups. -; MaxSVCoverpointBinsDesign = 2147483648 - -; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins -; MaxSVCoverpointBinsInst = 1048576 - -; Specify the maximum number of Cross bins in whole design for -; all Covergroups. -; MaxSVCrossBinsDesign = 2147483648 - -; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins -; MaxSVCrossBinsInst = 67108864 - -; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. -; By default, this variable is set 0, in which case option.no_collect setting will take effect. -; If this variable is set to 1, all zero-weight coverage items will not be saved. -; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting -; of this variable. -; CvgZWNoCollect = 1 - -; Specify a space delimited list of double quoted TCL style -; regular expressions which will be matched against the text of all messages. -; If any regular expression is found to be contained within any message, the -; status for that message will not be propagated to the UCDB TESTSTATUS. -; If no match is detected, then the status will be propagated to the -; UCDB TESTSTATUS. More than one such regular expression text is allowed, -; and each message text is compared for each regular expression in the list. -; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" - -; Set weight for all PSL/SVA cover directives. Default is 1. -; CoverWeight = 2 - -; Check vsim plusargs. Default is 0 (off). -; 0 = Don't check plusargs -; 1 = Warning on unrecognized plusarg -; 2 = Error and exit on unrecognized plusarg -; CheckPlusargs = 1 - -; Load the specified shared objects with the RTLD_GLOBAL flag. -; This gives global visibility to all symbols in the shared objects, -; meaning that subsequently loaded shared objects can bind to symbols -; in the global shared objects. The list of shared objects should -; be whitespace delimited. This option is not supported on the -; Windows or AIX platforms. -; GlobalSharedObjectList = example1.so example2.so example3.so - -; Generate the stub definitions for the undefined symbols in the shared libraries being -; loaded in the simulation. When this flow is turned on, the undefined symbols will not -; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. -; The valid arguments are: on, off, verbose. -; on : turn on the automatic generation of stub definitions. -; off: turn off the flow. The undefined symbols will trigger an immediate load failure. -; verbose: Turn on the flow and report the undefined symbols for each shared library. -; NOTE: This variable can be overriden with vsim switch "-undefsyms". -; The default is on. -; -; UndefSyms = off - -; Enable the support for checkpointing foreign C/C++ libraries. -; The valid arguments are: 0, 1, 2 -; 0: off (default) -; 1: on (manually save/restore user shared library data) -; 2: auto (automatically save/restore user shared library data) -; This option is not supported on the Windows platforms. -; -; AllowCheckpointCpp = 2 - -; Initial seed for the random number generator of the root thread (SystemVerilog). -; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. -; The default value is 0. -; Sv_Seed = 0 - -; Specify the solver "engine" that vsim will select for constrained random -; generation. -; Valid values are: -; "auto" - automatically select the best engine for the current -; constraint scenario -; "bdd" - evaluate all constraint scenarios using the BDD solver engine -; "act" - evaluate all constraint scenarios using the ACT solver engine -; While the BDD solver engine is generally efficient with constraint scenarios -; involving bitwise logical relationships, the ACT solver engine can exhibit -; superior performance with constraint scenarios involving large numbers of -; random variables related via arithmetic operators (+, *, etc). -; NOTE: This variable can be overridden with the vsim "-solveengine" command -; line switch. -; The default value is "auto". -; SolveEngine = auto - -; Specifies the maximum size that a dynamic array may be resized to by the -; solver. If the solver attempts to resize a dynamic array to a size greater -; than the specified limit, the solver will abort with an error. -; The default value is 10000. A value of 0 indicates no limit. -; SolveArrayResizeMax = 10000 - -; Specify error message severity when randomize() and randomize(null) failures -; are detected. -; -; Integer value up to two digits are allowed with each digit having the following legal values: -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; -; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents -; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit) -; represents the setting for randomize(null) calls. -; -; 2) When a single digit value is used, the setting is applied to both normal randomize() call -; and randomize(null) call. -; -; Example: Fatal error for randomize() failures and NO error for randomize(null) failures -; -solvefailseverity=40 -; -; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is -; enabled, a constraint contradiction report will be displayed for randomize() calls that -; have a message severity >= warning (i.e. constraint contradiction reports will not be -; generated for randomize() calls having a "no error" severity level) -; -; NOTE: This variable can be overridden with the vsim "-solvefailseverity" command -; line switch. -; -; The default is 1 (warning). -; SolveFailSeverity = 1 - -; Error message severity for suppressible errors that are detected in a -; solve/before constraint. -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" -; command line switch. -; The default is 3 (failure). -; SolveBeforeErrorSeverity = 3 - -; Error message severity for suppressible errors that are related to -; solve engine capacity limits -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" -; command line switch. -; The default is 3 (failure). -; SolveEngineErrorSeverity = 3 - -; Enable/disable constraint conflicts on randomize() failure -; Valid values: -; 0 - disable solvefaildebug -; 1 - basic debug (no performance penalty) -; 2 - enhanced debug (runtime performance penalty) -; -; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is -; enabled, a constraint contradiction report will be displayed for randomize() calls that -; have a message severity >= warning (i.e. constraint contradiction reports will not be -; generated for randomize() calls having a "no error" severity level) -; -; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command -; line switch. -; -; The default is 1 (basic debug). -; SolveFailDebug = 1 - -; Upon encountering a randomize() failure, generate a simplified testcase that -; will reproduce the failure. Optionally output the testcase to a file. -; Testcases for 'no-solution' failures will only be produced if SolveFailDebug -; is enabled (see above). -; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" -; command line switch. -; The default is OFF (do not generate a testcase). To enable testcase -; generation, uncomment this variable. To redirect testcase generation to a -; file, specify the name of the output file. -; SolveFailTestcase = - -; Specify solver timeout threshold (in seconds). randomize() will fail if the -; CPU time required to evaluate any randset exceeds the specified timeout. -; The default value is 500. A value of 0 will disable timeout failures. -; SolveTimeout = 500 - -; Specify the alternative behavior during solver replay. Must be used when combined with -solvereplay switch. -; SolveReplayOpt=[+|-][,[+|-]]*" -' Valid settings: -; validate : toggle the checking of value changes of non-random variables involved in randomize(). (default is off)" -; SolveReplayOpt=validate - -; Specify the maximum size of the solution graph generated by the BDD solver. -; This value can be used to force the BDD solver to abort the evaluation of a -; complex constraint scenario that cannot be evaluated with finite memory. -; This value is specified in 1000s of nodes. -; The default value is 10000. A value of 0 indicates no limit. -; SolveGraphMaxSize = 10000 - -; Specify the maximum number of evaluations that may be performed on the -; solution graph by the BDD solver. This value can be used to force the BDD -; solver to abort the evaluation of a complex constraint scenario that cannot -; be evaluated in finite time. This value is specified in 10000s of evaluations. -; The default value is 10000. A value of 0 indicates no limit. -; SolveGraphMaxEval = 10000 - -; Specify random sequence compatiblity with a prior release. This -; option is used to get the same random sequences during simulation as -; as a prior release. Only prior releases with the same major version -; as the current release are allowed. -; NOTE: Only those random sequence changes due to solver optimizations are -; reverted by this variable. Random sequence changes due to solver bugfixes -; cannot be un-done. -; NOTE: This variable can be overridden with the vsim "-solverev" command -; line switch. -; Default value set to "" (no compatibility). -; SolveRev = - -; Environment variable expansion of command line arguments has been depricated -; in favor shell level expansion. Universal environment variable expansion -; inside -f files is support and continued support for MGC Location Maps provide -; alternative methods for handling flexible pathnames. -; The following line may be uncommented and the value set to 1 to re-enable this -; deprecated behavior. The default value is 0. -; DeprecatedEnvironmentVariableExpansion = 0 - -; Specify the memory threshold for the System Verilog garbage collector. -; The value is the number of megabytes of class objects that must accumulate -; before the garbage collector is run. -; The GCThreshold setting is used when class debug mode is disabled to allow -; less frequent garbage collection and better simulation performance. -; The GCThresholdClassDebug setting is used when class debug mode is enabled -; to allow for more frequent garbage collection. -; GCThreshold = 100 -; GCThresholdClassDebug = 5 - -; Turn on/off collapsing of bus ports in VCD dumpports output -DumpportsCollapse = 1 - -; Location of Multi-Level Verification Component (MVC) installation. -; The default location is the product installation directory. -MvcHome = $QUESTA_MVC_HOME - -; Location of InFact installation. The default is $MODEL_TECH/../../infact -; -; InFactHome = $MODEL_TECH/../../infact - -; Initialize SystemVerilog enums using the base type's default value -; instead of the leftmost value. -; EnumBaseInit = 1 - -; Suppress file type registration. -; SuppressFileTypeReg = 1 - -; Enable/disable non-LRM compliant SystemVerilog language extensions. -; Valid extensions are: -; altdpiheader - Alternative style function signature generated in DPI header", -; cfce - generate an error if $cast fails as a function -; cfmt - C like formatting for specifiers with '#' prefix ('%#x', '%#h') -; dfsp - sets default format specifier as %p, if no format specifier is given for unpacked array in $display and related systasks -; expdfmt - enable format string extensions for $display/$sformatf -; extscan - support values greater than 32 bit for string builtin methods (atohex, atobin, atooct, atoi) -; fmtcap - prints capital hex digits with %X/%H in display calls -; iddp - ignore DPI disable protocol check -; lfmt - zero-pad data if '0' prefixes width in format specifier (e.g. "%04h") -; noexptc - ignore DPI export type name overloading check -; realrand - support randomize() with real variables and constraints (Default) -; SvExtensions = [+|-][,[+|-]*] - -; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions. -; Valid extensions are: -; arraymode - consider rand_mode of unpacked array field independently from its elements -; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles (Default) -; funcback - enable function backtracking (ACT only) -; genmodseedfix - enable LRM-compliant seeding of module/interface instances under for-generate blocks (Default) -; nodist - interpret 'dist' constraint as 'inside' (ACT only) -; noorder - ignore solve/before ordering constraints (ACT only) -; pathseed - enable unique seeding of module instances based on hierarchical path name -; prerandfirst - execute all pre_randomize() functions before evaluating any constraints -; promotedist - promote priority of 'dist' constraint if LHS has no solve/before -; purecheck - suppress pre_randomize() and post_randomize() calls for randomize(null) -; randindex - allow random index in constraint (Default) -; randstruct - consider all fields of unpacked structs as 'rand' -; skew - skew randomize results (ACT only) -; strictstab - strict random stability -; SvRandExtensions = [+|-][,[+|-]*] - -; Controls the formatting of '%p' and '%P' conversion specification, used in $display -; and similar system tasks. -; 1. SVPrettyPrintFlags=I use spaces(S) or tabs(T) per indentation level. -; The 'I' flag when present causes relevant data types to be expanded and indented into -; a more readable format. -; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). -; 2. SVPrettyPrintFlags=L limits the output to lines. -; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). -; 3. SVPrettyPrintFlags=C limits the output to characters. -; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). -; 4. SVPrettyPrintFlags=F limits the output to of relevant datatypes -; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). -; 5. SVPrettyPrintFlags=E limits the output to of relevant datatypes -; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). -; 6. SVPrettyPrintFlags=D suppresses the output of sub-elements below . -; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). -; 7. SVPrettyPrintFlags=R shows the output of specifier %p as per the specifed radix. -; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)). -; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format. -; 8. Items 1-7 above can be combined as a comma separated list. -; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb) -; SVPrettyPrintFlags=I4S - -[lmc] -; The simulator's interface to Logic Modeling's SmartModel SWIFT software -libsm = $MODEL_TECH/libsm.sl -; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) -; libsm = $MODEL_TECH/libsm.dll -; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) -; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl -; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) -; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o -; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) -; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so -; Logic Modeling's SmartModel SWIFT software (Windows NT) -; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll -; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) -; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so -; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) -; libswift = $LMC_HOME/lib/linux.lib/libswift.so - -; The simulator's interface to Logic Modeling's hardware modeler SFI software -libhm = $MODEL_TECH/libhm.sl -; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) -; libhm = $MODEL_TECH/libhm.dll -; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) -; libsfi = /lib/hp700/libsfi.sl -; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) -; libsfi = /lib/rs6000/libsfi.a -; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) -; libsfi = /lib/sun4.solaris/libsfi.so -; Logic Modeling's hardware modeler SFI software (Windows NT) -; libsfi = /lib/pcnt/lm_sfi.dll -; Logic Modeling's hardware modeler SFI software (Linux) -; libsfi = /lib/linux/libsfi.so - -[msg_system] -; Change a message severity or suppress a message. -; The format is: = [,...] -; suppress can be used to achieve +nowarn functionality -; The format is: suppress = ,,[,,...] -; Examples: -suppress = 8780 ;an explanation can be had by running: verror 8780 -; note = 3009 -; warning = 3033 -; error = 3010,3016 -; fatal = 3016,3033 -; suppress = 3009,3016,3601 -; suppress = 3009,CNNODP,3601,TFMPC -; suppress = 8683,8684 -; The command verror can be used to get the complete -; description of a message. - -; Control transcripting of Verilog display system task messages and -; PLI/FLI print function call messages. The system tasks include -; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They -; also include the analogous file I/O tasks that write to STDOUT -; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, -; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default -; is to have messages appear only in the transcript. The other -; settings are to send messages to the wlf file only (messages that -; are recorded in the wlf file can be viewed in the MsgViewer) or -; to both the transcript and the wlf file. The valid values are -; tran {transcript only (default)} -; wlf {wlf file only} -; both {transcript and wlf file} -; displaymsgmode = tran - -; Control transcripting of elaboration/runtime messages not -; addressed by the displaymsgmode setting. The default is to -; have messages appear only in the transcript. The other settings -; are to send messages to the wlf file only (messages that are -; recorded in the wlf file can be viewed in the MsgViewer) or to both -; the transcript and the wlf file. The valid values are -; tran {transcript only (default)} -; wlf {wlf file only} -; both {transcript and wlf file} -; msgmode = tran - -; Controls number of displays of a particluar message -; default value is 5 -; MsgLimitCount = 5 - -[utils] -; Default Library Type (while creating a library with "vlib") -; 0 - legacy library using subdirectories for design units -; 2 - flat library -; DefaultLibType = 2 - -; Flat Library Page Size (while creating a library with "vlib") -; Set the size in bytes for flat library file pages. Libraries containing -; very large files may benefit from a larger value. -; FlatLibPageSize = 8192 - -; Flat Library Page Cleanup Percentage (while creating a library with "vlib") -; Set the percentage of total pages deleted before library cleanup can occur. -; This setting is applied together with FlatLibPageDeleteThreshold. -; FlatLibPageDeletePercentage = 50 - -; Flat Library Page Cleanup Threshold (while creating a library with "vlib") -; Set the number of pages deleted before library cleanup can occur. -; This setting is applied together with FlatLibPageDeletePercentage. -; FlatLibPageDeleteThreshold = 1000 - - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/simulate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/simulate.do deleted file mode 100644 index fab79968..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/simulate.do +++ /dev/null @@ -1,16 +0,0 @@ -onbreak {quit -f} -onerror {quit -f} - -vsim -voptargs="+acc" -t 1ps -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.GaussFir_1mp5 xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure -view signals - -do {GaussFir_1mp5.udo} - -run -all - -quit -force diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/wave.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/modelsim/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/GaussFir_1mp5.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/GaussFir_1mp5.mif deleted file mode 100644 index 647b490c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/GaussFir_1mp5.mif +++ /dev/null @@ -1,160 +0,0 @@ -00000000 0 0 0 0 0 0 -00000000 0 0 0 0 1 0 -00000001 0 0 0 0 2 0 -00000001 0 0 0 0 3 0 -00000001 0 0 0 0 4 0 -00000001 0 0 0 0 5 0 -00000002 0 0 0 0 6 0 -00000002 0 0 0 0 7 0 -00000002 0 0 0 0 8 0 -00000003 0 0 0 0 9 0 -00000004 0 0 0 0 10 0 -00000005 0 0 0 0 11 0 -00000006 0 0 0 0 12 0 -00000007 0 0 0 0 13 0 -00000008 0 0 0 0 14 0 -0000000a 0 0 0 0 15 0 -0000000c 0 0 0 0 16 0 -0000000e 0 0 0 0 17 0 -00000011 0 0 0 0 18 0 -00000015 0 0 0 0 19 0 -00000018 0 0 0 0 20 0 -0000001d 0 0 0 0 21 0 -00000022 0 0 0 0 22 0 -00000027 0 0 0 0 23 0 -0000002e 0 0 0 0 24 0 -00000035 0 0 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-0000000c 0 3 0 0 112 0 -0000000a 0 3 0 0 113 0 -00000008 0 3 0 0 114 0 -00000007 0 3 0 0 115 0 -00000006 0 3 0 0 116 0 -00000005 0 3 0 0 117 0 -00000004 0 3 0 0 118 0 -00000003 0 3 0 0 119 0 -00000002 0 3 0 0 120 0 -00000002 0 3 0 0 121 0 -00000002 0 3 0 0 122 0 -00000001 0 3 0 0 123 0 -00000001 0 3 0 0 124 0 -00000001 0 3 0 0 125 0 -00000001 0 3 0 0 126 0 -00000000 0 3 0 0 127 0 -00000000 0 4 0 0 128 0 -00000000 0 4 0 0 129 0 -00000000 0 4 0 0 130 0 -00000000 0 4 0 0 131 0 -00000000 0 4 0 0 132 0 -00000000 0 4 0 0 133 0 -00000000 0 4 0 0 134 0 -00000000 0 4 0 0 135 0 -00000000 0 4 0 0 136 0 -00000000 0 4 0 0 137 0 -00000000 0 4 0 0 138 0 -00000000 0 4 0 0 139 0 -00000000 0 4 0 0 140 0 -00000000 0 4 0 0 141 0 -00000000 0 4 0 0 142 0 -00000000 0 4 0 0 143 0 -00000000 0 4 0 0 144 0 -00000000 0 4 0 0 145 0 -00000000 0 4 0 0 146 0 -00000000 0 4 0 0 147 0 -00000000 0 4 0 0 148 0 -00000000 0 4 0 0 149 0 -00000000 0 4 0 0 150 0 -00000000 0 4 0 0 151 0 -00000000 0 4 0 0 152 0 -00000000 0 4 0 0 153 0 -00000000 0 4 0 0 154 0 -00000000 0 4 0 0 155 0 -00000000 0 4 0 0 156 0 -00000000 0 4 0 0 157 0 -00000000 0 4 0 0 158 0 -00000000 0 4 0 0 159 0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/GaussFir_1mp5.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/GaussFir_1mp5.sh deleted file mode 100644 index 69813e36..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/GaussFir_1mp5.sh +++ /dev/null @@ -1,175 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : GaussFir_1mp5.sh -# Simulator : Mentor Graphics Questa Advanced Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:36:16 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: GaussFir_1mp5.sh [-help] -# usage: GaussFir_1mp5.sh [-lib_map_path] -# usage: GaussFir_1mp5.sh [-noclean_files] -# usage: GaussFir_1mp5.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'GaussFir_1mp5.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "GaussFir_1mp5.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -elaborate() -{ - source elaborate.do 2>&1 | tee -a elaborate.log -} - -# RUN_STEP: -simulate() -{ - vsim -64 -c -do "do {simulate.do}" -l simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./GaussFir_1mp5.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Copy modelsim.ini file -copy_setup_file() -{ - file="modelsim.ini" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then - lib_map_path="$1" - else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - cp $src_file . - fi -} - -# Create design library directory -create_lib_dir() -{ - lib_dir="questa_lib" - if [[ -e $lib_dir ]]; then - rm -rf $lib_dir - fi - - mkdir $lib_dir - -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./GaussFir_1mp5.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: GaussFir_1mp5.sh [-help]\n\ -Usage: GaussFir_1mp5.sh [-lib_map_path]\n\ -Usage: GaussFir_1mp5.sh [-reset_run]\n\ -Usage: GaussFir_1mp5.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/GaussFir_1mp5.udo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/GaussFir_1mp5.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/Gaussfir_1p5m.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/Gaussfir_1p5m.coe deleted file mode 100644 index 9fa4e7e5..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/Gaussfir_1p5m.coe +++ /dev/null @@ -1,132 +0,0 @@ -Radix=10; -Coefficient_Width=16; -CoefData= -0 -0 -1 -1 -1 -1 -2 -2 -2 -3 -4 -5 -6 -7 -8 -10 -12 -14 -17 -21 -24 -29 -34 -39 -46 -53 -61 -70 -80 -91 -104 -117 -132 -147 -164 -182 -202 -222 -244 -267 -290 -315 -340 -366 -392 -419 -446 -473 -500 -526 -552 -577 -602 -625 -647 -667 -686 -702 -717 -730 -741 -749 -755 -759 -760 -759 -755 -749 -741 -730 -717 -702 -686 -667 -647 -625 -602 -577 -552 -526 -500 -473 -446 -419 -392 -366 -340 -315 -290 -267 -244 -222 -202 -182 -164 -147 -132 -117 -104 -91 -80 -70 -61 -53 -46 -39 -34 -29 -24 -21 -17 -14 -12 -10 -8 -7 -6 -5 -4 -3 -2 -2 -2 -1 -1 -1 -1 -0 -0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/README.txt deleted file mode 100644 index 775767b0..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:36:16 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./GaussFir_1mp5.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './GaussFir_1mp5.sh' script. - -./GaussFir_1mp5.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./GaussFir_1mp5.sh -noclean_files - -For more information on the script, please type './GaussFir_1mp5.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/compile.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/compile.do deleted file mode 100644 index 1d065524..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/compile.do +++ /dev/null @@ -1,37 +0,0 @@ -vlib questa_lib/work -vlib questa_lib/msim - -vlib questa_lib/msim/xil_defaultlib -vlib questa_lib/msim/xpm -vlib questa_lib/msim/xbip_utils_v3_0_10 -vlib questa_lib/msim/axi_utils_v2_0_6 -vlib questa_lib/msim/fir_compiler_v7_2_12 - -vmap xil_defaultlib questa_lib/msim/xil_defaultlib -vmap xpm questa_lib/msim/xpm -vmap xbip_utils_v3_0_10 questa_lib/msim/xbip_utils_v3_0_10 -vmap axi_utils_v2_0_6 questa_lib/msim/axi_utils_v2_0_6 -vmap fir_compiler_v7_2_12 questa_lib/msim/fir_compiler_v7_2_12 - -vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/GaussFir_1mp5/cmodel" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -64 -93 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vcom -work xbip_utils_v3_0_10 -64 -93 \ -"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ - -vcom -work axi_utils_v2_0_6 -64 -93 \ -"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ - -vcom -work fir_compiler_v7_2_12 -64 -93 \ -"../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ - -vcom -work xil_defaultlib -64 -93 \ -"../../../ip/GaussFir_1mp5/sim/GaussFir_1mp5.vhd" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/elaborate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/elaborate.do deleted file mode 100644 index b996cb75..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/elaborate.do +++ /dev/null @@ -1 +0,0 @@ -vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.GaussFir_1mp5 xil_defaultlib.glbl -o GaussFir_1mp5_opt diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/file_info.txt deleted file mode 100644 index 800f64df..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/file_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/GaussFir_1mp5/cmodel" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/GaussFir_1mp5/cmodel" -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -GaussFir_1mp5.vhd,vhdl,xil_defaultlib,../../../ip/GaussFir_1mp5/sim/GaussFir_1mp5.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/simulate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/simulate.do deleted file mode 100644 index e176e371..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/simulate.do +++ /dev/null @@ -1,16 +0,0 @@ -onbreak {quit -f} -onerror {quit -f} - -vsim -t 1ps -lib xil_defaultlib GaussFir_1mp5_opt - -do {wave.do} - -view wave -view structure -view signals - -do {GaussFir_1mp5.udo} - -run -all - -quit -force diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/wave.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/questa/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/GaussFir_1mp5.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/GaussFir_1mp5.mif deleted file mode 100644 index 647b490c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/GaussFir_1mp5.mif +++ /dev/null @@ -1,160 +0,0 @@ -00000000 0 0 0 0 0 0 -00000000 0 0 0 0 1 0 -00000001 0 0 0 0 2 0 -00000001 0 0 0 0 3 0 -00000001 0 0 0 0 4 0 -00000001 0 0 0 0 5 0 -00000002 0 0 0 0 6 0 -00000002 0 0 0 0 7 0 -00000002 0 0 0 0 8 0 -00000003 0 0 0 0 9 0 -00000004 0 0 0 0 10 0 -00000005 0 0 0 0 11 0 -00000006 0 0 0 0 12 0 -00000007 0 0 0 0 13 0 -00000008 0 0 0 0 14 0 -0000000a 0 0 0 0 15 0 -0000000c 0 0 0 0 16 0 -0000000e 0 0 0 0 17 0 -00000011 0 0 0 0 18 0 -00000015 0 0 0 0 19 0 -00000018 0 0 0 0 20 0 -0000001d 0 0 0 0 21 0 -00000022 0 0 0 0 22 0 -00000027 0 0 0 0 23 0 -0000002e 0 0 0 0 24 0 -00000035 0 0 0 0 25 0 -0000003d 0 0 0 0 26 0 -00000046 0 0 0 0 27 0 -00000050 0 0 0 0 28 0 -0000005b 0 0 0 0 29 0 -00000068 0 0 0 0 30 0 -00000075 0 0 0 0 31 0 -00000084 0 1 0 0 32 0 -00000093 0 1 0 0 33 0 -000000a4 0 1 0 0 34 0 -000000b6 0 1 0 0 35 0 -000000ca 0 1 0 0 36 0 -000000de 0 1 0 0 37 0 -000000f4 0 1 0 0 38 0 -0000010b 0 1 0 0 39 0 -00000122 0 1 0 0 40 0 -0000013b 0 1 0 0 41 0 -00000154 0 1 0 0 42 0 -0000016e 0 1 0 0 43 0 -00000188 0 1 0 0 44 0 -000001a3 0 1 0 0 45 0 -000001be 0 1 0 0 46 0 -000001d9 0 1 0 0 47 0 -000001f4 0 1 0 0 48 0 -0000020e 0 1 0 0 49 0 -00000228 0 1 0 0 50 0 -00000241 0 1 0 0 51 0 -0000025a 0 1 0 0 52 0 -00000271 0 1 0 0 53 0 -00000287 0 1 0 0 54 0 -0000029b 0 1 0 0 55 0 -000002ae 0 1 0 0 56 0 -000002be 0 1 0 0 57 0 -000002cd 0 1 0 0 58 0 -000002da 0 1 0 0 59 0 -000002e5 0 1 0 0 60 0 -000002ed 0 1 0 0 61 0 -000002f3 0 1 0 0 62 0 -000002f7 0 1 0 0 63 0 -000002f8 0 2 0 0 64 0 -000002f7 0 2 0 0 65 0 -000002f3 0 2 0 0 66 0 -000002ed 0 2 0 0 67 0 -000002e5 0 2 0 0 68 0 -000002da 0 2 0 0 69 0 -000002cd 0 2 0 0 70 0 -000002be 0 2 0 0 71 0 -000002ae 0 2 0 0 72 0 -0000029b 0 2 0 0 73 0 -00000287 0 2 0 0 74 0 -00000271 0 2 0 0 75 0 -0000025a 0 2 0 0 76 0 -00000241 0 2 0 0 77 0 -00000228 0 2 0 0 78 0 -0000020e 0 2 0 0 79 0 -000001f4 0 2 0 0 80 0 -000001d9 0 2 0 0 81 0 -000001be 0 2 0 0 82 0 -000001a3 0 2 0 0 83 0 -00000188 0 2 0 0 84 0 -0000016e 0 2 0 0 85 0 -00000154 0 2 0 0 86 0 -0000013b 0 2 0 0 87 0 -00000122 0 2 0 0 88 0 -0000010b 0 2 0 0 89 0 -000000f4 0 2 0 0 90 0 -000000de 0 2 0 0 91 0 -000000ca 0 2 0 0 92 0 -000000b6 0 2 0 0 93 0 -000000a4 0 2 0 0 94 0 -00000093 0 2 0 0 95 0 -00000084 0 3 0 0 96 0 -00000075 0 3 0 0 97 0 -00000068 0 3 0 0 98 0 -0000005b 0 3 0 0 99 0 -00000050 0 3 0 0 100 0 -00000046 0 3 0 0 101 0 -0000003d 0 3 0 0 102 0 -00000035 0 3 0 0 103 0 -0000002e 0 3 0 0 104 0 -00000027 0 3 0 0 105 0 -00000022 0 3 0 0 106 0 -0000001d 0 3 0 0 107 0 -00000018 0 3 0 0 108 0 -00000015 0 3 0 0 109 0 -00000011 0 3 0 0 110 0 -0000000e 0 3 0 0 111 0 -0000000c 0 3 0 0 112 0 -0000000a 0 3 0 0 113 0 -00000008 0 3 0 0 114 0 -00000007 0 3 0 0 115 0 -00000006 0 3 0 0 116 0 -00000005 0 3 0 0 117 0 -00000004 0 3 0 0 118 0 -00000003 0 3 0 0 119 0 -00000002 0 3 0 0 120 0 -00000002 0 3 0 0 121 0 -00000002 0 3 0 0 122 0 -00000001 0 3 0 0 123 0 -00000001 0 3 0 0 124 0 -00000001 0 3 0 0 125 0 -00000001 0 3 0 0 126 0 -00000000 0 3 0 0 127 0 -00000000 0 4 0 0 128 0 -00000000 0 4 0 0 129 0 -00000000 0 4 0 0 130 0 -00000000 0 4 0 0 131 0 -00000000 0 4 0 0 132 0 -00000000 0 4 0 0 133 0 -00000000 0 4 0 0 134 0 -00000000 0 4 0 0 135 0 -00000000 0 4 0 0 136 0 -00000000 0 4 0 0 137 0 -00000000 0 4 0 0 138 0 -00000000 0 4 0 0 139 0 -00000000 0 4 0 0 140 0 -00000000 0 4 0 0 141 0 -00000000 0 4 0 0 142 0 -00000000 0 4 0 0 143 0 -00000000 0 4 0 0 144 0 -00000000 0 4 0 0 145 0 -00000000 0 4 0 0 146 0 -00000000 0 4 0 0 147 0 -00000000 0 4 0 0 148 0 -00000000 0 4 0 0 149 0 -00000000 0 4 0 0 150 0 -00000000 0 4 0 0 151 0 -00000000 0 4 0 0 152 0 -00000000 0 4 0 0 153 0 -00000000 0 4 0 0 154 0 -00000000 0 4 0 0 155 0 -00000000 0 4 0 0 156 0 -00000000 0 4 0 0 157 0 -00000000 0 4 0 0 158 0 -00000000 0 4 0 0 159 0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/GaussFir_1mp5.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/GaussFir_1mp5.sh deleted file mode 100644 index 2226f19c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/GaussFir_1mp5.sh +++ /dev/null @@ -1,154 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : GaussFir_1mp5.sh -# Simulator : Aldec Riviera-PRO Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:36:16 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: GaussFir_1mp5.sh [-help] -# usage: GaussFir_1mp5.sh [-lib_map_path] -# usage: GaussFir_1mp5.sh [-noclean_files] -# usage: GaussFir_1mp5.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'GaussFir_1mp5.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "GaussFir_1mp5.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - runvsimsa -l simulate.log -do "do {simulate.do}" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./GaussFir_1mp5.sh -help\" for more information)\n" - exit 1 - fi - map_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - map_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Map library.cfg file -map_setup_file() -{ - file="library.cfg" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then - lib_map_path="$1" - else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - vmap -link $lib_map_path - fi - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./GaussFir_1mp5.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: GaussFir_1mp5.sh [-help]\n\ -Usage: GaussFir_1mp5.sh [-lib_map_path]\n\ -Usage: GaussFir_1mp5.sh [-reset_run]\n\ -Usage: GaussFir_1mp5.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/GaussFir_1mp5.udo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/GaussFir_1mp5.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/Gaussfir_1p5m.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/Gaussfir_1p5m.coe deleted file mode 100644 index 9fa4e7e5..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/Gaussfir_1p5m.coe +++ /dev/null @@ -1,132 +0,0 @@ -Radix=10; -Coefficient_Width=16; -CoefData= -0 -0 -1 -1 -1 -1 -2 -2 -2 -3 -4 -5 -6 -7 -8 -10 -12 -14 -17 -21 -24 -29 -34 -39 -46 -53 -61 -70 -80 -91 -104 -117 -132 -147 -164 -182 -202 -222 -244 -267 -290 -315 -340 -366 -392 -419 -446 -473 -500 -526 -552 -577 -602 -625 -647 -667 -686 -702 -717 -730 -741 -749 -755 -759 -760 -759 -755 -749 -741 -730 -717 -702 -686 -667 -647 -625 -602 -577 -552 -526 -500 -473 -446 -419 -392 -366 -340 -315 -290 -267 -244 -222 -202 -182 -164 -147 -132 -117 -104 -91 -80 -70 -61 -53 -46 -39 -34 -29 -24 -21 -17 -14 -12 -10 -8 -7 -6 -5 -4 -3 -2 -2 -2 -1 -1 -1 -1 -0 -0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/README.txt deleted file mode 100644 index 775767b0..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:36:16 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./GaussFir_1mp5.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './GaussFir_1mp5.sh' script. - -./GaussFir_1mp5.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./GaussFir_1mp5.sh -noclean_files - -For more information on the script, please type './GaussFir_1mp5.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/compile.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/compile.do deleted file mode 100644 index e0133975..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/compile.do +++ /dev/null @@ -1,37 +0,0 @@ -vlib work -vlib riviera - -vlib riviera/xil_defaultlib -vlib riviera/xpm -vlib riviera/xbip_utils_v3_0_10 -vlib riviera/axi_utils_v2_0_6 -vlib riviera/fir_compiler_v7_2_12 - -vmap xil_defaultlib riviera/xil_defaultlib -vmap xpm riviera/xpm -vmap xbip_utils_v3_0_10 riviera/xbip_utils_v3_0_10 -vmap axi_utils_v2_0_6 riviera/axi_utils_v2_0_6 -vmap fir_compiler_v7_2_12 riviera/fir_compiler_v7_2_12 - -vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/GaussFir_1mp5/cmodel" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -93 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vcom -work xbip_utils_v3_0_10 -93 \ -"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ - -vcom -work axi_utils_v2_0_6 -93 \ -"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ - -vcom -work fir_compiler_v7_2_12 -93 \ -"../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ - -vcom -work xil_defaultlib -93 \ -"../../../ip/GaussFir_1mp5/sim/GaussFir_1mp5.vhd" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/file_info.txt deleted file mode 100644 index 800f64df..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/file_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/GaussFir_1mp5/cmodel" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/GaussFir_1mp5/cmodel" -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -GaussFir_1mp5.vhd,vhdl,xil_defaultlib,../../../ip/GaussFir_1mp5/sim/GaussFir_1mp5.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/simulate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/simulate.do deleted file mode 100644 index 909b3769..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/simulate.do +++ /dev/null @@ -1,17 +0,0 @@ -onbreak {quit -force} -onerror {quit -force} - -asim -t 1ps +access +r +m+GaussFir_1mp5 -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.GaussFir_1mp5 xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure - -do {GaussFir_1mp5.udo} - -run -all - -endsim - -quit -force diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/wave.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/riviera/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/GaussFir_1mp5.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/GaussFir_1mp5.mif deleted file mode 100644 index 647b490c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/GaussFir_1mp5.mif +++ /dev/null @@ -1,160 +0,0 @@ -00000000 0 0 0 0 0 0 -00000000 0 0 0 0 1 0 -00000001 0 0 0 0 2 0 -00000001 0 0 0 0 3 0 -00000001 0 0 0 0 4 0 -00000001 0 0 0 0 5 0 -00000002 0 0 0 0 6 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0 -00000000 0 4 0 0 136 0 -00000000 0 4 0 0 137 0 -00000000 0 4 0 0 138 0 -00000000 0 4 0 0 139 0 -00000000 0 4 0 0 140 0 -00000000 0 4 0 0 141 0 -00000000 0 4 0 0 142 0 -00000000 0 4 0 0 143 0 -00000000 0 4 0 0 144 0 -00000000 0 4 0 0 145 0 -00000000 0 4 0 0 146 0 -00000000 0 4 0 0 147 0 -00000000 0 4 0 0 148 0 -00000000 0 4 0 0 149 0 -00000000 0 4 0 0 150 0 -00000000 0 4 0 0 151 0 -00000000 0 4 0 0 152 0 -00000000 0 4 0 0 153 0 -00000000 0 4 0 0 154 0 -00000000 0 4 0 0 155 0 -00000000 0 4 0 0 156 0 -00000000 0 4 0 0 157 0 -00000000 0 4 0 0 158 0 -00000000 0 4 0 0 159 0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/GaussFir_1mp5.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/GaussFir_1mp5.sh deleted file mode 100644 index 9937d0ee..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/GaussFir_1mp5.sh +++ /dev/null @@ -1,241 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : GaussFir_1mp5.sh -# Simulator : Synopsys Verilog Compiler Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:36:16 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: GaussFir_1mp5.sh [-help] -# usage: GaussFir_1mp5.sh [-lib_map_path] -# usage: GaussFir_1mp5.sh [-noclean_files] -# usage: GaussFir_1mp5.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'GaussFir_1mp5.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Command line options -vlogan_opts="-full64" -vhdlan_opts="-full64" -vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" -vcs_sim_opts="-ucli -licqueue -l simulate.log" - -# Design libraries -design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 fir_compiler_v7_2_12) - -# Simulation root library directory -sim_lib_dir="vcs_lib" - -# Script info -echo -e "GaussFir_1mp5.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ip/GaussFir_1mp5/cmodel" \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - 2>&1 | tee -a vlogan.log - - vhdlan -work xpm $vhdlan_opts \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - 2>&1 | tee -a vhdlan.log - - vhdlan -work xbip_utils_v3_0_10 $vhdlan_opts \ - "$ref_dir/../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ - 2>&1 | tee -a vhdlan.log - - vhdlan -work axi_utils_v2_0_6 $vhdlan_opts \ - "$ref_dir/../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ - 2>&1 | tee -a vhdlan.log - - vhdlan -work fir_compiler_v7_2_12 $vhdlan_opts \ - "$ref_dir/../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ - 2>&1 | tee -a vhdlan.log - - vhdlan -work xil_defaultlib $vhdlan_opts \ - "$ref_dir/../../../ip/GaussFir_1mp5/sim/GaussFir_1mp5.vhd" \ - 2>&1 | tee -a vhdlan.log - - - vlogan -work xil_defaultlib $vlogan_opts +v2k \ - glbl.v \ - 2>&1 | tee -a vlogan.log - -} - -# RUN_STEP: -elaborate() -{ - vcs $vcs_elab_opts xil_defaultlib.GaussFir_1mp5 xil_defaultlib.glbl -o GaussFir_1mp5_simv -} - -# RUN_STEP: -simulate() -{ - ./GaussFir_1mp5_simv $vcs_sim_opts -do simulate.do -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./GaussFir_1mp5.sh -help\" for more information)\n" - exit 1 - fi - create_lib_mappings $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - create_lib_mappings $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Define design library mappings -create_lib_mappings() -{ - file="synopsys_sim.setup" - if [[ -e $file ]]; then - if [[ ($1 == "") ]]; then - return - else - rm -rf $file - fi - fi - - touch $file - - lib_map_path="" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - mapping="$lib:$sim_lib_dir/$lib" - echo $mapping >> $file - done - - if [[ ($lib_map_path != "") ]]; then - incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" - echo $incl_ref >> $file - fi -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(ucli.key GaussFir_1mp5_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc GaussFir_1mp5_simv.daidir) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./GaussFir_1mp5.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: GaussFir_1mp5.sh [-help]\n\ -Usage: GaussFir_1mp5.sh [-lib_map_path]\n\ -Usage: GaussFir_1mp5.sh [-reset_run]\n\ -Usage: GaussFir_1mp5.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/Gaussfir_1p5m.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/Gaussfir_1p5m.coe deleted file mode 100644 index 9fa4e7e5..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/Gaussfir_1p5m.coe +++ /dev/null @@ -1,132 +0,0 @@ -Radix=10; -Coefficient_Width=16; -CoefData= -0 -0 -1 -1 -1 -1 -2 -2 -2 -3 -4 -5 -6 -7 -8 -10 -12 -14 -17 -21 -24 -29 -34 -39 -46 -53 -61 -70 -80 -91 -104 -117 -132 -147 -164 -182 -202 -222 -244 -267 -290 -315 -340 -366 -392 -419 -446 -473 -500 -526 -552 -577 -602 -625 -647 -667 -686 -702 -717 -730 -741 -749 -755 -759 -760 -759 -755 -749 -741 -730 -717 -702 -686 -667 -647 -625 -602 -577 -552 -526 -500 -473 -446 -419 -392 -366 -340 -315 -290 -267 -244 -222 -202 -182 -164 -147 -132 -117 -104 -91 -80 -70 -61 -53 -46 -39 -34 -29 -24 -21 -17 -14 -12 -10 -8 -7 -6 -5 -4 -3 -2 -2 -2 -1 -1 -1 -1 -0 -0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/README.txt deleted file mode 100644 index 775767b0..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:36:16 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./GaussFir_1mp5.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './GaussFir_1mp5.sh' script. - -./GaussFir_1mp5.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./GaussFir_1mp5.sh -noclean_files - -For more information on the script, please type './GaussFir_1mp5.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/file_info.txt deleted file mode 100644 index 800f64df..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/file_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/GaussFir_1mp5/cmodel" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/GaussFir_1mp5/cmodel" -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -GaussFir_1mp5.vhd,vhdl,xil_defaultlib,../../../ip/GaussFir_1mp5/sim/GaussFir_1mp5.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/simulate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/simulate.do deleted file mode 100644 index 58afc787..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/vcs/simulate.do +++ /dev/null @@ -1,2 +0,0 @@ -run -quit diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/GaussFir_1mp5.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/GaussFir_1mp5.mif deleted file mode 100644 index 647b490c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/GaussFir_1mp5.mif +++ /dev/null @@ -1,160 +0,0 @@ -00000000 0 0 0 0 0 0 -00000000 0 0 0 0 1 0 -00000001 0 0 0 0 2 0 -00000001 0 0 0 0 3 0 -00000001 0 0 0 0 4 0 -00000001 0 0 0 0 5 0 -00000002 0 0 0 0 6 0 -00000002 0 0 0 0 7 0 -00000002 0 0 0 0 8 0 -00000003 0 0 0 0 9 0 -00000004 0 0 0 0 10 0 -00000005 0 0 0 0 11 0 -00000006 0 0 0 0 12 0 -00000007 0 0 0 0 13 0 -00000008 0 0 0 0 14 0 -0000000a 0 0 0 0 15 0 -0000000c 0 0 0 0 16 0 -0000000e 0 0 0 0 17 0 -00000011 0 0 0 0 18 0 -00000015 0 0 0 0 19 0 -00000018 0 0 0 0 20 0 -0000001d 0 0 0 0 21 0 -00000022 0 0 0 0 22 0 -00000027 0 0 0 0 23 0 -0000002e 0 0 0 0 24 0 -00000035 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0 0 153 0 -00000000 0 4 0 0 154 0 -00000000 0 4 0 0 155 0 -00000000 0 4 0 0 156 0 -00000000 0 4 0 0 157 0 -00000000 0 4 0 0 158 0 -00000000 0 4 0 0 159 0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/GaussFir_1mp5.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/GaussFir_1mp5.sh deleted file mode 100644 index 2921cfdd..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/GaussFir_1mp5.sh +++ /dev/null @@ -1,176 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : GaussFir_1mp5.sh -# Simulator : Cadence Xcelium Parallel Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:36:16 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: GaussFir_1mp5.sh [-help] -# usage: GaussFir_1mp5.sh [-lib_map_path] -# usage: GaussFir_1mp5.sh [-noclean_files] -# usage: GaussFir_1mp5.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'GaussFir_1mp5.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Set the compiled library directory -ref_lib_dir="." - -# Command line options -xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" - -# Design libraries -design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 fir_compiler_v7_2_12) - -# Simulation root library directory -sim_lib_dir="xcelium_lib" - -# Script info -echo -e "GaussFir_1mp5.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - execute -} - -# RUN_STEP: -execute() -{ - xrun $xrun_opts \ - -reflib "$ref_lib_dir/unisim:unisim" \ - -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ - -reflib "$ref_lib_dir/secureip:secureip" \ - -reflib "$ref_lib_dir/unimacro:unimacro" \ - -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.GaussFir_1mp5 \ - -f run.f \ - -top glbl \ - glbl.v \ - +incdir+"../../../ip/GaussFir_1mp5/cmodel" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./GaussFir_1mp5.sh -help\" for more information)\n" - exit 1 - else - ref_lib_dir=$2 - fi - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./GaussFir_1mp5.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: GaussFir_1mp5.sh [-help]\n\ -Usage: GaussFir_1mp5.sh [-lib_map_path]\n\ -Usage: GaussFir_1mp5.sh [-reset_run]\n\ -Usage: GaussFir_1mp5.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/Gaussfir_1p5m.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/Gaussfir_1p5m.coe deleted file mode 100644 index 9fa4e7e5..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/Gaussfir_1p5m.coe +++ /dev/null @@ -1,132 +0,0 @@ -Radix=10; -Coefficient_Width=16; -CoefData= -0 -0 -1 -1 -1 -1 -2 -2 -2 -3 -4 -5 -6 -7 -8 -10 -12 -14 -17 -21 -24 -29 -34 -39 -46 -53 -61 -70 -80 -91 -104 -117 -132 -147 -164 -182 -202 -222 -244 -267 -290 -315 -340 -366 -392 -419 -446 -473 -500 -526 -552 -577 -602 -625 -647 -667 -686 -702 -717 -730 -741 -749 -755 -759 -760 -759 -755 -749 -741 -730 -717 -702 -686 -667 -647 -625 -602 -577 -552 -526 -500 -473 -446 -419 -392 -366 -340 -315 -290 -267 -244 -222 -202 -182 -164 -147 -132 -117 -104 -91 -80 -70 -61 -53 -46 -39 -34 -29 -24 -21 -17 -14 -12 -10 -8 -7 -6 -5 -4 -3 -2 -2 -2 -1 -1 -1 -1 -0 -0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/README.txt deleted file mode 100644 index c1c0d5df..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/README.txt +++ /dev/null @@ -1,48 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:36:16 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./GaussFir_1mp5.sh - -This command will launch the 'execute' function for the single-step flow. This -function is called from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './GaussFir_1mp5.sh' script. - -./GaussFir_1mp5.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./GaussFir_1mp5.sh -noclean_files - -For more information on the script, please type './GaussFir_1mp5.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/file_info.txt deleted file mode 100644 index 800f64df..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/file_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/GaussFir_1mp5/cmodel" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/GaussFir_1mp5/cmodel" -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -GaussFir_1mp5.vhd,vhdl,xil_defaultlib,../../../ip/GaussFir_1mp5/sim/GaussFir_1mp5.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/run.f b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/run.f deleted file mode 100644 index 5478458f..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xcelium/run.f +++ /dev/null @@ -1,23 +0,0 @@ --makelib xcelium_lib/xil_defaultlib -sv \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ --endlib --makelib xcelium_lib/xpm \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ --endlib --makelib xcelium_lib/xbip_utils_v3_0_10 \ - "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ --endlib --makelib xcelium_lib/axi_utils_v2_0_6 \ - "../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ --endlib --makelib xcelium_lib/fir_compiler_v7_2_12 \ - "../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ --endlib --makelib xcelium_lib/xil_defaultlib \ - "../../../ip/GaussFir_1mp5/sim/GaussFir_1mp5.vhd" \ --endlib --makelib xcelium_lib/xil_defaultlib \ - glbl.v --endlib - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/GaussFir_1mp5.mif b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/GaussFir_1mp5.mif deleted file mode 100644 index 647b490c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/GaussFir_1mp5.mif +++ /dev/null @@ -1,160 +0,0 @@ -00000000 0 0 0 0 0 0 -00000000 0 0 0 0 1 0 -00000001 0 0 0 0 2 0 -00000001 0 0 0 0 3 0 -00000001 0 0 0 0 4 0 -00000001 0 0 0 0 5 0 -00000002 0 0 0 0 6 0 -00000002 0 0 0 0 7 0 -00000002 0 0 0 0 8 0 -00000003 0 0 0 0 9 0 -00000004 0 0 0 0 10 0 -00000005 0 0 0 0 11 0 -00000006 0 0 0 0 12 0 -00000007 0 0 0 0 13 0 -00000008 0 0 0 0 14 0 -0000000a 0 0 0 0 15 0 -0000000c 0 0 0 0 16 0 -0000000e 0 0 0 0 17 0 -00000011 0 0 0 0 18 0 -00000015 0 0 0 0 19 0 -00000018 0 0 0 0 20 0 -0000001d 0 0 0 0 21 0 -00000022 0 0 0 0 22 0 -00000027 0 0 0 0 23 0 -0000002e 0 0 0 0 24 0 -00000035 0 0 0 0 25 0 -0000003d 0 0 0 0 26 0 -00000046 0 0 0 0 27 0 -00000050 0 0 0 0 28 0 -0000005b 0 0 0 0 29 0 -00000068 0 0 0 0 30 0 -00000075 0 0 0 0 31 0 -00000084 0 1 0 0 32 0 -00000093 0 1 0 0 33 0 -000000a4 0 1 0 0 34 0 -000000b6 0 1 0 0 35 0 -000000ca 0 1 0 0 36 0 -000000de 0 1 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3 0 0 123 0 -00000001 0 3 0 0 124 0 -00000001 0 3 0 0 125 0 -00000001 0 3 0 0 126 0 -00000000 0 3 0 0 127 0 -00000000 0 4 0 0 128 0 -00000000 0 4 0 0 129 0 -00000000 0 4 0 0 130 0 -00000000 0 4 0 0 131 0 -00000000 0 4 0 0 132 0 -00000000 0 4 0 0 133 0 -00000000 0 4 0 0 134 0 -00000000 0 4 0 0 135 0 -00000000 0 4 0 0 136 0 -00000000 0 4 0 0 137 0 -00000000 0 4 0 0 138 0 -00000000 0 4 0 0 139 0 -00000000 0 4 0 0 140 0 -00000000 0 4 0 0 141 0 -00000000 0 4 0 0 142 0 -00000000 0 4 0 0 143 0 -00000000 0 4 0 0 144 0 -00000000 0 4 0 0 145 0 -00000000 0 4 0 0 146 0 -00000000 0 4 0 0 147 0 -00000000 0 4 0 0 148 0 -00000000 0 4 0 0 149 0 -00000000 0 4 0 0 150 0 -00000000 0 4 0 0 151 0 -00000000 0 4 0 0 152 0 -00000000 0 4 0 0 153 0 -00000000 0 4 0 0 154 0 -00000000 0 4 0 0 155 0 -00000000 0 4 0 0 156 0 -00000000 0 4 0 0 157 0 -00000000 0 4 0 0 158 0 -00000000 0 4 0 0 159 0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/GaussFir_1mp5.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/GaussFir_1mp5.sh deleted file mode 100644 index 81ce35a5..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/GaussFir_1mp5.sh +++ /dev/null @@ -1,214 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : GaussFir_1mp5.sh -# Simulator : Xilinx Vivado Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:36:16 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: GaussFir_1mp5.sh [-help] -# usage: GaussFir_1mp5.sh [-lib_map_path] -# usage: GaussFir_1mp5.sh [-noclean_files] -# usage: GaussFir_1mp5.sh [-reset_run] -# -#********************************************************************************************************* - -# Command line options -xv_boost_lib_path=C:/Xilinx/Vivado/2019.1/tps/boost_1_64_0 -xvlog_opts="--relax" -xvhdl_opts="--relax" - - -# Script info -echo -e "GaussFir_1mp5.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log - xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log - -} - -# RUN_STEP: -elaborate() -{ - xelab --relax --debug typical --mt auto -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot GaussFir_1mp5 xil_defaultlib.GaussFir_1mp5 xil_defaultlib.glbl -log elaborate.log -} - -# RUN_STEP: -simulate() -{ - xsim GaussFir_1mp5 -key {Behavioral:sim_1:Functional:GaussFir_1mp5} -tclbatch cmd.tcl -log simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./GaussFir_1mp5.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Copy xsim.ini file -copy_setup_file() -{ - file="xsim.ini" - lib_map_path="C:/Xilinx/Vivado/2019.1/data/xsim" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - cp $src_file . - fi - - # Map local design libraries to xsim.ini - map_local_libs - - fi -} - -# Map local design libraries -map_local_libs() -{ - updated_mappings=() - local_mappings=() - - # Local design libraries - local_libs=() - - if [[ 0 == ${#local_libs[@]} ]]; then - return - fi - - file="xsim.ini" - file_backup="xsim.ini.bak" - - if [[ -e $file ]]; then - rm -f $file_backup - # Create a backup copy of the xsim.ini file - cp $file $file_backup - # Read libraries from backup file and search in local library collection - while read -r line - do - IN=$line - # Split mapping entry with '=' delimiter to fetch library name and mapping - read lib_name mapping <<<$(IFS="="; echo $IN) - # If local library found, then construct the local mapping and add to local mapping collection - if `echo ${local_libs[@]} | grep -wq $lib_name` ; then - line="$lib_name=xsim.dir/$lib_name" - local_mappings+=("$lib_name") - fi - # Add to updated library mapping collection - updated_mappings+=("$line") - done < "$file_backup" - # Append local libraries not found originally from xsim.ini - for (( i=0; i<${#local_libs[*]}; i++ )); do - lib_name="${local_libs[i]}" - if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then - line="$lib_name=xsim.dir/$lib_name" - updated_mappings+=("$line") - fi - done - # Write updated mappings in xsim.ini - rm -f $file - for (( i=0; i<${#updated_mappings[*]}; i++ )); do - lib_name="${updated_mappings[i]}" - echo $lib_name >> $file - done - else - for (( i=0; i<${#local_libs[*]}; i++ )); do - lib_name="${local_libs[i]}" - mapping="$lib_name=xsim.dir/$lib_name" - echo $mapping >> $file - done - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb GaussFir_1mp5.wdb xsim.dir) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./GaussFir_1mp5.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: GaussFir_1mp5.sh [-help]\n\ -Usage: GaussFir_1mp5.sh [-lib_map_path]\n\ -Usage: GaussFir_1mp5.sh [-reset_run]\n\ -Usage: GaussFir_1mp5.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/Gaussfir_1p5m.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/Gaussfir_1p5m.coe deleted file mode 100644 index 9fa4e7e5..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/Gaussfir_1p5m.coe +++ /dev/null @@ -1,132 +0,0 @@ -Radix=10; -Coefficient_Width=16; -CoefData= -0 -0 -1 -1 -1 -1 -2 -2 -2 -3 -4 -5 -6 -7 -8 -10 -12 -14 -17 -21 -24 -29 -34 -39 -46 -53 -61 -70 -80 -91 -104 -117 -132 -147 -164 -182 -202 -222 -244 -267 -290 -315 -340 -366 -392 -419 -446 -473 -500 -526 -552 -577 -602 -625 -647 -667 -686 -702 -717 -730 -741 -749 -755 -759 -760 -759 -755 -749 -741 -730 -717 -702 -686 -667 -647 -625 -602 -577 -552 -526 -500 -473 -446 -419 -392 -366 -340 -315 -290 -267 -244 -222 -202 -182 -164 -147 -132 -117 -104 -91 -80 -70 -61 -53 -46 -39 -34 -29 -24 -21 -17 -14 -12 -10 -8 -7 -6 -5 -4 -3 -2 -2 -2 -1 -1 -1 -1 -0 -0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/README.txt deleted file mode 100644 index 775767b0..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:36:16 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./GaussFir_1mp5.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './GaussFir_1mp5.sh' script. - -./GaussFir_1mp5.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./GaussFir_1mp5.sh -noclean_files - -For more information on the script, please type './GaussFir_1mp5.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/cmd.tcl b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/cmd.tcl deleted file mode 100644 index eef7a0f0..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/cmd.tcl +++ /dev/null @@ -1,12 +0,0 @@ -set curr_wave [current_wave_config] -if { [string length $curr_wave] == 0 } { - if { [llength [get_objects]] > 0} { - add_wave / - set_property needs_save false [current_wave_config] - } else { - send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." - } -} - -run -all -quit diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/elab.opt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/elab.opt deleted file mode 100644 index 1e9644ea..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/elab.opt +++ /dev/null @@ -1 +0,0 @@ ---relax --debug typical --mt auto -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot GaussFir_1mp5 xil_defaultlib.GaussFir_1mp5 xil_defaultlib.glbl -log elaborate.log diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/file_info.txt deleted file mode 100644 index 6c768509..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/file_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -GaussFir_1mp5.vhd,vhdl,xil_defaultlib,../../../ip/GaussFir_1mp5/sim/GaussFir_1mp5.vhd,incdir="../../../ip/GaussFir_1mp5/cmodel" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/vhdl.prj b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/vhdl.prj deleted file mode 100644 index 49091f0b..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/vhdl.prj +++ /dev/null @@ -1,4 +0,0 @@ -vhdl xil_defaultlib \ -"../../../ip/GaussFir_1mp5/sim/GaussFir_1mp5.vhd" \ - -nosort diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/vlog.prj b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/vlog.prj deleted file mode 100644 index 35119d5b..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/vlog.prj +++ /dev/null @@ -1,4 +0,0 @@ - -verilog xil_defaultlib "glbl.v" - -nosort diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/xsim.ini b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/xsim.ini deleted file mode 100644 index 6cb07f57..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/GaussFir_1mp5/xsim/xsim.ini +++ /dev/null @@ -1,430 +0,0 @@ -std=$RDI_DATADIR/xsim/vhdl/std -ieee=$RDI_DATADIR/xsim/vhdl/ieee -ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed -vl=$RDI_DATADIR/xsim/vhdl/vl -synopsys=$RDI_DATADIR/xsim/vhdl/synopsys -secureip=$RDI_DATADIR/xsim/verilog/secureip -unisim=$RDI_DATADIR/xsim/vhdl/unisim -unimacro=$RDI_DATADIR/xsim/vhdl/unimacro -unifast=$RDI_DATADIR/xsim/vhdl/unifast -unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver -unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver -unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver -simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver -system_cache_v4_0_6=$RDI_DATADIR/xsim/ip/system_cache_v4_0_6 -bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0 -g709_rs_decoder_v2_2_8=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_8 -xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0 -mipi_dphy_v4_1_4=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_1_4 -iomodule_v3_1_4=$RDI_DATADIR/xsim/ip/iomodule_v3_1_4 -ieee802d3_50g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_11 -common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0 -lte_fft_v2_1_0=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_0 -ieee802d3_50g_rs_fec_v2_0_1=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_1 -convolution_v9_0_14=$RDI_DATADIR/xsim/ip/convolution_v9_0_14 -gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4 -v_cfa_v7_0_14=$RDI_DATADIR/xsim/ip/v_cfa_v7_0_14 -axi4svideo_bridge_v1_0_10=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_10 -pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11 -v_vscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_13 -xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6 -gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux -ethernet_1_10_25g_v2_2_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_2_3 -zynq_ultra_ps_e_v3_3_0=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_0 -v_cresample_v4_0_14=$RDI_DATADIR/xsim/ip/v_cresample_v4_0_14 -v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9 -v_scenechange_v1_0_1=$RDI_DATADIR/xsim/ip/v_scenechange_v1_0_1 -hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0 -ahblite_axi_bridge_v3_0_14=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_14 -tri_mode_ethernet_mac_v9_0_14=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_14 -blk_mem_gen_v8_4_3=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_3 -noc_mc_ddr4_phy_v1_0_0=$RDI_DATADIR/xsim/ip/noc_mc_ddr4_phy_v1_0_0 -axi_data_fifo_v2_1_18=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_18 -axi_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_5 -ethernet_1_10_25g_v2_0_5=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_0_5 -compact_gt_v1_0_5=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_5 -axi_gpio_v2_0_21=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_21 -qdma_v3_0_2=$RDI_DATADIR/xsim/ip/qdma_v3_0_2 -viterbi_v9_1_11=$RDI_DATADIR/xsim/ip/viterbi_v9_1_11 -sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2 -ba317=$RDI_DATADIR/xsim/ip/ba317 -xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4 -fifo_generator_v13_2_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_4 -axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14 -vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0 -axi_emc_v3_0_19=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_19 -cmac_v2_5_1=$RDI_DATADIR/xsim/ip/cmac_v2_5_1 -floating_point_v7_1_8=$RDI_DATADIR/xsim/ip/floating_point_v7_1_8 -xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6 -vid_phy_controller_v2_2_3=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_3 -common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1 -axi_firewall_v1_0_7=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_7 -util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1 -axis_accelerator_adapter_v2_1_15=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_15 -tmr_comparator_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_2 -sd_fec_v1_0_2=$RDI_DATADIR/xsim/ip/sd_fec_v1_0_2 -tmr_manager_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_4 -tsn_temac_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_4 -usxgmii_v1_0_5=$RDI_DATADIR/xsim/ip/usxgmii_v1_0_5 -lte_dl_channel_encoder_v4_0_0=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v4_0_0 -ai_noc=$RDI_DATADIR/xsim/ip/ai_noc -lte_3gpp_mimo_decoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_15 -v_uhdsdi_audio_v1_0_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_0_0 -axi4stream_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_5 -cmac_usplus_v2_4_5=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_4_5 -etrnic_v1_1_2=$RDI_DATADIR/xsim/ip/etrnic_v1_1_2 -floating_point_v7_0_16=$RDI_DATADIR/xsim/ip/floating_point_v7_0_16 -axi_dma_v7_1_20=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_20 -jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi -axi_traffic_gen_v3_0_5=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_5 -emb_mem_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_1 -axi_amm_bridge_v1_0_9=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_9 -axi_datamover_v5_1_21=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_21 -v_axi4s_vid_out_v4_0_10=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_10 -jesd204_v7_2_6=$RDI_DATADIR/xsim/ip/jesd204_v7_2_6 -v_letterbox_v1_0_13=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_13 -interlaken_v2_4_3=$RDI_DATADIR/xsim/ip/interlaken_v2_4_3 -uhdsdi_gt_v2_0_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_0 -axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7 -rst_vip_v1_0_3=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_3 -audio_formatter_v1_0_1=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_1 -lte_3gpp_channel_estimator_v2_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_16 -v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13 -g709_fec_v2_3_5=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_5 -xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6 -axi_chip2chip_v5_0_6=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_6 -fc32_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_11 -v_mix_v3_0_3=$RDI_DATADIR/xsim/ip/v_mix_v3_0_3 -multi_channel_25g_rs_fec_v1_0_5=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_5 -in_system_ibert_v1_0_9=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_9 -ethernet_1_10_25g_v2_1_4=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_1_4 -axis_broadcaster_v1_1_18=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_18 -axis_combiner_v1_1_17=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_17 -axi_apb_bridge_v3_0_15=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_15 -displayport_v9_0_1=$RDI_DATADIR/xsim/ip/displayport_v9_0_1 -clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2 -hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1 -axi_register_slice_v2_1_19=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_19 -vid_phy_controller_v2_1_5=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_5 -picxo=$RDI_DATADIR/xsim/ip/picxo -usxgmii_v1_1_0=$RDI_DATADIR/xsim/ip/usxgmii_v1_1_0 -v_vcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_13 -bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0 -prc_v1_3_2=$RDI_DATADIR/xsim/ip/prc_v1_3_2 -axi_usb2_device_v5_0_20=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_20 -lte_3gpp_mimo_encoder_v4_0_14=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_14 -l_ethernet_v2_5_2=$RDI_DATADIR/xsim/ip/l_ethernet_v2_5_2 -xdma_v4_1_3=$RDI_DATADIR/xsim/ip/xdma_v4_1_3 -axis_vio_v1_0_0=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_0 -c_counter_binary_v12_0_13=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_13 -noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0 -xbip_dsp48_macro_v3_0_17=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_17 -c_accum_v12_0_13=$RDI_DATADIR/xsim/ip/c_accum_v12_0_13 -xbip_multadd_v3_0_14=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_14 -axi_uartlite_v2_0_23=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_23 -noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0 -axi_intc_v4_1_13=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_13 -i2s_transmitter_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_3 -pc_cfr_v6_0_8=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_8 -mutex_v2_1_10=$RDI_DATADIR/xsim/ip/mutex_v2_1_10 -c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6 -sid_v8_0_14=$RDI_DATADIR/xsim/ip/sid_v8_0_14 -fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6 -quadsgmii_v3_4_6=$RDI_DATADIR/xsim/ip/quadsgmii_v3_4_6 -microblaze_v11_0_1=$RDI_DATADIR/xsim/ip/microblaze_v11_0_1 -lib_bmg_v1_0_12=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_12 -dds_compiler_v6_0_18=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_18 -me_pl_v1_0=$RDI_DATADIR/xsim/ip/me_pl_v1_0 -gtwizard_ultrascale_v1_7_6=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_6 -axis_clock_converter_v1_1_20=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_20 -nvmeha_v1_0_0=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_0 -tmr_inject_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_3 -axi_mcdma_v1_1_0=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_0 -axi_hwicap_v3_0_23=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_23 -v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0 -v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0 -canfd_v2_0_1=$RDI_DATADIR/xsim/ip/canfd_v2_0_1 -gig_ethernet_pcs_pma_v16_1_6=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_6 -lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2 -ieee802d3_rs_fec_v2_0_5=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_5 -ibert_lib_v1_0_6=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_6 -high_speed_selectio_wiz_v3_4_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_1 -xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6 -fec_5g_common_v1_0_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_1 -tmr_voter_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_2 -hdmi_gt_controller_v1_0_0=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_0 -axi_traffic_gen_v2_0_20=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_20 -flexo_100g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_11 -v_smpte_uhdsdi_v1_0_7=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_7 -xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6 -fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10 -ieee802d3_rs_fec_v1_0_15=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_15 -axis_subset_converter_v1_1_19=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_19 -noc_nmu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_v1_0_0 -duc_ddc_compiler_v3_0_15=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_15 -dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13 -mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0 -ieee802d3_200g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_7 -sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1 -mrmac_v1_0_0=$RDI_DATADIR/xsim/ip/mrmac_v1_0_0 -sem_ultra_v3_1_11=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_11 -v_tpg_v8_0_1=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_1 -axi_tft_v2_0_22=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_22 -ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13 -switch_core_top_v1_0_7=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_7 -rama_v1_1_2_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_2_lib -v_hcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_13 -emb_fifo_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_1 -hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3 -axis_data_fifo_v2_0_1=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_1 -hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0 -rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1 -displayport_v8_1_1=$RDI_DATADIR/xsim/ip/displayport_v8_1_1 -axi_mmu_v2_1_17=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_17 -proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13 -pc_cfr_v6_3_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_3_0 -v_osd_v6_0_16=$RDI_DATADIR/xsim/ip/v_osd_v6_0_16 -pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12 -xfft_v9_0_17=$RDI_DATADIR/xsim/ip/xfft_v9_0_17 -axi_cdma_v4_1_19=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_19 -audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0 -lib_fifo_v1_0_13=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_13 -v_enhance_v8_0_15=$RDI_DATADIR/xsim/ip/v_enhance_v8_0_15 -axi_clock_converter_v2_1_18=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_18 -xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0 -emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5 -axi_mm2s_mapper_v1_1_18=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_18 -xfft_v7_2_9=$RDI_DATADIR/xsim/ip/xfft_v7_2_9 -pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0 -v_smpte_sdi_v3_0_8=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_8 -fir_compiler_v7_2_12=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_12 -div_gen_v5_1_15=$RDI_DATADIR/xsim/ip/div_gen_v5_1_15 -mdm_v3_2_16=$RDI_DATADIR/xsim/ip/mdm_v3_2_16 -v_axi4s_remap_v1_0_11=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_11 -xxv_ethernet_v2_5_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_5_3 -xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2 -ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig -remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4 -pr_axi_shutdown_manager_v1_0_1=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_1 -axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0 -smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0 -axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib -axi_dwidth_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_19 -xlconstant_v1_1_6=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_6 -tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6 -mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2 -v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1 -axi_fifo_mm_s_v4_2_1=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_1 -util_idelay_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_1 -rs_toolbox_v9_0_7=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_7 -v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0 -dsp_macro_v1_0_0=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_0 -pc_cfr_v6_2_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_2 -axi_timer_v2_0_21=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_21 -high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1 -axi_sideband_util_v1_0_3=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_3 -sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2 -gmii_to_rgmii_v4_0_7=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_0_7 -xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2 -high_speed_selectio_wiz_v3_5_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_5_1 -axi_msg_v1_0_5=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_5 -axi_ahblite_bridge_v3_0_16=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_16 -v_rgb2ycrcb_v7_1_13=$RDI_DATADIR/xsim/ip/v_rgb2ycrcb_v7_1_13 -v_mix_v4_0_0=$RDI_DATADIR/xsim/ip/v_mix_v4_0_0 -axi_ethernetlite_v3_0_17=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_17 -axi_uart16550_v2_0_21=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_21 -axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0 -vfb_v1_0_13=$RDI_DATADIR/xsim/ip/vfb_v1_0_13 -advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0 -ats_switch_v1_0_2=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_2 -interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4 -axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub -cpri_v8_10_3=$RDI_DATADIR/xsim/ip/cpri_v8_10_3 -c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6 -v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0 -stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0 -rld3_pl_v1_0_1=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_1 -ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0 -lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0 -axi_epc_v2_0_22=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_22 -g709_rs_encoder_v2_2_6=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_6 -blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6 -tmr_sem_v1_0_9=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_9 -fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6 -axi_vdma_v6_3_7=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_7 -axis_data_fifo_v1_1_20=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_20 -xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip -axi_ethernet_buffer_v2_0_20=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_20 -rs_encoder_v9_0_15=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_15 -axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0 -ta_dma_v1_0_3=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_3 -tcc_encoder_3gpp_v5_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_15 -axi_perf_mon_v5_0_21=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_21 -noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0 -sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1 -lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2 -v_csc_v1_0_13=$RDI_DATADIR/xsim/ip/v_csc_v1_0_13 -shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0 -lte_fft_v2_0_18=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_18 -gtwizard_ultrascale_v1_6_11=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_11 -amm_axi_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_5 -mii_to_rmii_v2_0_21=$RDI_DATADIR/xsim/ip/mii_to_rmii_v2_0_21 -videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5 -audio_clock_recovery_v1_0=$RDI_DATADIR/xsim/ip/audio_clock_recovery_v1_0 -cmac_v2_4_1=$RDI_DATADIR/xsim/ip/cmac_v2_4_1 -i2s_receiver_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_3 -v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0 -v_demosaic_v1_0_5=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_5 -remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4 -microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4 -hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3 -etrnic_v1_0_3=$RDI_DATADIR/xsim/ip/etrnic_v1_0_3 -xfft_v9_1_2=$RDI_DATADIR/xsim/ip/xfft_v9_1_2 -ddr4_pl_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_2 -xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6 -cmac_usplus_v2_5_3=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_5_3 -jesd204c_v4_1_1=$RDI_DATADIR/xsim/ip/jesd204c_v4_1_1 -debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1 -axis_protocol_checker_v2_0_3=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_3 -v_frmbuf_wr_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_2 -v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9 -mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4 -lte_dl_channel_encoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_15 -axi_protocol_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_19 -xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0 -clk_gen_sim_v1_0_0=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_0 -axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0 -microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7 -cmpy_v6_0_17=$RDI_DATADIR/xsim/ip/cmpy_v6_0_17 -cmac_v2_3_5=$RDI_DATADIR/xsim/ip/cmac_v2_3_5 -ieee802d3_400g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_7 -xxv_ethernet_v2_4_5=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_4_5 -axi_timebase_wdt_v3_0_11=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_11 -tcc_decoder_3gppmm_v2_0_18=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_18 -v_deinterlacer_v5_0_13=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_13 -dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16 -axi_fifo_mm_s_v4_1_16=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_16 -processing_system7_vip_v1_0_7=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_7 -g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18 -rs_decoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_16 -c_shift_ram_v12_0_13=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_13 -displayport_v7_0_11=$RDI_DATADIR/xsim/ip/displayport_v7_0_11 -v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0 -v_deinterlacer_v4_0_12=$RDI_DATADIR/xsim/ip/v_deinterlacer_v4_0_12 -sem_v4_1_12=$RDI_DATADIR/xsim/ip/sem_v4_1_12 -xaui_v12_3_6=$RDI_DATADIR/xsim/ip/xaui_v12_3_6 -ten_gig_eth_mac_v15_1_7=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_7 -oddr_v1_0_0=$RDI_DATADIR/xsim/ip/oddr_v1_0_0 -c_addsub_v12_0_13=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_13 -v_ccm_v6_0_15=$RDI_DATADIR/xsim/ip/v_ccm_v6_0_15 -zynq_ultra_ps_e_vip_v1_0_5=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_5 -cic_compiler_v4_0_14=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_14 -c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6 -axi_memory_init_v1_0_0=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_0 -pr_decoupler_v1_0_7=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_7 -timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4 -lte_pucch_receiver_v2_0_16=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_16 -zynq_ultra_ps_e_v3_2_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_3 -v_gamma_lut_v1_0_5=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_5 -bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0 -pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0 -tcc_encoder_3gpplte_v4_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_15 -polar_v1_0_3=$RDI_DATADIR/xsim/ip/polar_v1_0_3 -rxaui_v4_4_6=$RDI_DATADIR/xsim/ip/rxaui_v4_4_6 -xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6 -v_gamma_v7_0_15=$RDI_DATADIR/xsim/ip/v_gamma_v7_0_15 -ernic_v1_0_1=$RDI_DATADIR/xsim/ip/ernic_v1_0_1 -high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3 -mailbox_v2_1_11=$RDI_DATADIR/xsim/ip/mailbox_v2_1_11 -video_frame_crc_v1_0_1=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_1 -axi_sg_v4_1_12=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_12 -ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0 -lmb_bram_if_cntlr_v4_0_16=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_16 -l_ethernet_v2_4_3=$RDI_DATADIR/xsim/ip/l_ethernet_v2_4_3 -dft_v4_1_1=$RDI_DATADIR/xsim/ip/dft_v4_1_1 -rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0 -axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6 -v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0 -stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0 -lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0 -uhdsdi_gt_v1_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_3 -pc_cfr_v6_1_4=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_4 -lmb_v10_v3_0_9=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_9 -axis_interconnect_v1_1_17=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_17 -cordic_v6_0_15=$RDI_DATADIR/xsim/ip/cordic_v6_0_15 -axis_register_slice_v1_1_19=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_19 -axis_switch_v1_1_19=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_19 -axi_interconnect_v1_7_16=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_16 -mult_gen_v12_0_15=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_15 -spdif_v2_0_21=$RDI_DATADIR/xsim/ip/spdif_v2_0_21 -v_hscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_13 -ethernet_1_10_25g_v2_3_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_3_3 -xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6 -axi_quad_spi_v3_2_18=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_18 -axi_bram_ctrl_v4_1_1=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_1 -axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4 -axi_protocol_checker_v2_0_5=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_5 -axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0 -mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7 -ieee802d3_25g_rs_fec_v1_0_13=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_13 -aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0 -xtlm=$RDI_DATADIR/xsim/ip/xtlm -iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0 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-axi_mcdma_v1_0_5=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_5 -c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6 -g709_fec_v2_4_1=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_1 -lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0 -ai_pl=$RDI_DATADIR/xsim/ip/ai_pl -fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4 -v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0 -l_ethernet_v2_3_5=$RDI_DATADIR/xsim/ip/l_ethernet_v2_3_5 -microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6 -v_uhdsdi_audio_v2_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_1 -ldpc_v2_0_3=$RDI_DATADIR/xsim/ip/ldpc_v2_0_3 -xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6 -xpm=$RDI_DATADIR/xsim/ip/xpm -srio_gen2_v4_1_6=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_6 -g975_efec_i4_v1_0_17=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_17 -noc_na_v1_0_0=$RDI_DATADIR/xsim/ip/noc_na_v1_0_0 -roe_framer_v2_0_1=$RDI_DATADIR/xsim/ip/roe_framer_v2_0_1 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a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/README.txt +++ /dev/null @@ -1,83 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required -# to simulate the design for a simulator, the directory structure -# and the generated exported files. -# -################################################################################ - -1. Simulate Design - -To simulate design, cd to the simulator directory and execute the script. - -For example:- - -% cd questa -% ./top.sh - -The export simulation flow requires the Xilinx pre-compiled simulation library -components for the target simulator. These components are referred using the -'-lib_map_path' switch. If this switch is specified, then the export simulation -will automatically set this library path in the generated script and update, -copy the simulator setup file(s) in the exported directory. - -If '-lib_map_path' is not specified, then the pre-compiled simulation library -information will not be included in the exported scripts and that may cause -simulation errors when running this script. Alternatively, you can provide the -library information using this switch while executing the generated script. - -For example:- - -% ./top.sh -lib_map_path /design/questa/clibs - -Please refer to the generated script header 'Prerequisite' section for more details. - -2. Directory Structure - -By default, if the -directory switch is not specified, export_simulation will -create the following directory structure:- - -/export_sim/ - -For example, if the current working directory is /tmp/test, export_simulation -will create the following directory path:- - -/tmp/test/export_sim/questa - -If -directory switch is specified, export_simulation will create a simulator -sub-directory under the specified directory path. - -For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' -command will create the following directory:- - -/tmp/test/my_test_area/func_sim/questa - -By default, if -simulator is not specified, export_simulation will create a -simulator sub-directory for each simulator and export the files for each simulator -in this sub-directory respectively. - -IMPORTANT: Please note that the simulation library path must be specified manually -in the generated script for the respective simulator. Please refer to the generated -script header 'Prerequisite' section for more details. - -3. Exported script and files - -Export simulation will create the driver shell script, setup files and copy the -design sources in the output directory path. - -By default, when the -script_name switch is not specified, export_simulation will -create the following script name:- - -.sh (Unix) -When exporting the files for an IP using the -of_objects switch, export_simulation -will create the following script name:- - -.sh (Unix) -Export simulation will create the setup files for the target simulator specified -with the -simulator switch. - -For example, if the target simulator is "ies", export_simulation will create the -'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' -file. - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/README.txt deleted file mode 100644 index d3e5c3fa..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:35:28 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./data_1p5m.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './data_1p5m.sh' script. - -./data_1p5m.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./data_1p5m.sh -noclean_files - -For more information on the script, please type './data_1p5m.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/compile.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/compile.do deleted file mode 100644 index 5f99ef2f..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/compile.do +++ /dev/null @@ -1,27 +0,0 @@ -vlib work -vlib activehdl - -vlib activehdl/xil_defaultlib -vlib activehdl/xpm -vlib activehdl/blk_mem_gen_v8_4_3 - -vmap xil_defaultlib activehdl/xil_defaultlib -vmap xpm activehdl/xpm -vmap blk_mem_gen_v8_4_3 activehdl/blk_mem_gen_v8_4_3 - -vlog -work xil_defaultlib -sv2k12 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -93 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work blk_mem_gen_v8_4_3 -v2k5 \ -"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ - -vlog -work xil_defaultlib -v2k5 \ -"../../../ip/data_1p5m/sim/data_1p5m.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/data_1m5.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/data_1m5.coe deleted file mode 100644 index 3dd9526c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/data_1m5.coe +++ /dev/null @@ -1,2051 +0,0 @@ -memory_initialization_radix = 2; -memory_initialization_vector = -1 -0 -1 -0 -1 -0 -1 -1 -0 -1 -1 -1 -0 -1 -1 -0 -1 -1 -1 -0 -0 -1 -1 -0 -1 -1 -1 -1 -0 -0 -1 -1 -1 -1 -0 -0 -1 -0 -0 -1 -0 -1 -1 -1 -0 -1 -0 -0 -1 -1 -0 -1 -0 -0 -1 -1 -0 -0 -0 -1 -0 -1 -0 -0 -1 -0 -1 -1 -0 -0 -0 -1 -1 -0 -0 -0 -0 -1 -1 -0 -1 -0 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-#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : data_1p5m.sh -# Simulator : Aldec Active-HDL Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:35:28 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: data_1p5m.sh [-help] -# usage: data_1p5m.sh [-lib_map_path] -# usage: data_1p5m.sh [-noclean_files] -# usage: data_1p5m.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'data_1p5m.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "data_1p5m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - runvsimsa -l simulate.log -do "do {simulate.do}" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./data_1p5m.sh -help\" for more information)\n" - exit 1 - fi - map_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - map_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Map library.cfg file -map_setup_file() -{ - file="library.cfg" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then - lib_map_path="$1" - else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - vmap -link $lib_map_path - fi - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./data_1p5m.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: data_1p5m.sh [-help]\n\ -Usage: data_1p5m.sh [-lib_map_path]\n\ -Usage: data_1p5m.sh [-reset_run]\n\ -Usage: data_1p5m.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/data_1p5m.udo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/data_1p5m.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/file_info.txt deleted file mode 100644 index 8f539960..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, -data_1p5m.v,verilog,xil_defaultlib,../../../ip/data_1p5m/sim/data_1p5m.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/simulate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/simulate.do deleted file mode 100644 index 0b05c93d..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/simulate.do +++ /dev/null @@ -1,17 +0,0 @@ -onbreak {quit -force} -onerror {quit -force} - -asim -t 1ps +access +r +m+data_1p5m -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.data_1p5m xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure - -do {data_1p5m.udo} - -run -all - -endsim - -quit -force diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/wave.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/activehdl/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/ies/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/ies/README.txt deleted file mode 100644 index 3e1510d2..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/ies/README.txt +++ /dev/null @@ -1,48 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:35:28 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./data_1p5m.sh - -This command will launch the 'execute' function for the single-step flow. This -function is called from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './data_1p5m.sh' script. - -./data_1p5m.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./data_1p5m.sh -noclean_files - -For more information on the script, please type './data_1p5m.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/ies/data_1m5.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/ies/data_1m5.coe deleted file mode 100644 index 3dd9526c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/ies/data_1m5.coe +++ /dev/null @@ -1,2051 +0,0 @@ -memory_initialization_radix = 2; -memory_initialization_vector = -1 -0 -1 -0 -1 -0 -1 -1 -0 -1 -1 -1 -0 -1 -1 -0 -1 -1 -1 -0 -0 -1 -1 -0 -1 -1 -1 -1 -0 -0 -1 -1 -1 -1 -0 -0 -1 -0 -0 -1 -0 -1 -1 -1 -0 -1 -0 -0 -1 -1 -0 -1 -0 -0 -1 -1 -0 -0 -0 -1 -0 -1 -0 -0 -1 -0 -1 -1 -0 -0 -0 -1 -1 -0 -0 -0 -0 -1 -1 -0 -1 -0 -1 -1 -1 -0 -0 -1 -1 -0 -1 -0 -0 -0 -1 -0 -1 -0 -0 -1 -1 -0 -0 -0 -0 -1 -0 -0 -0 -0 -1 -1 -1 -0 -0 -0 -1 -0 -0 -1 -0 -1 -0 -1 -1 -0 -0 -1 -0 -0 -1 -1 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elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:35:28 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: data_1p5m.sh [-help] -# usage: data_1p5m.sh [-lib_map_path] -# usage: data_1p5m.sh [-noclean_files] -# usage: data_1p5m.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'data_1p5m.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Set the compiled library directory -ref_lib_dir="." - -# Command line options -irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" - -# Design libraries -design_libs=(xil_defaultlib xpm blk_mem_gen_v8_4_3) - -# Simulation root library directory -sim_lib_dir="ies_lib" - -# Script info -echo -e "data_1p5m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - execute -} - -# RUN_STEP: -execute() -{ - irun $irun_opts \ - -reflib "$ref_lib_dir/unisim:unisim" \ - -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ - -reflib "$ref_lib_dir/secureip:secureip" \ - -reflib "$ref_lib_dir/unimacro:unimacro" \ - -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.data_1p5m \ - -f run.f \ - -top glbl \ - glbl.v -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./data_1p5m.sh -help\" for more information)\n" - exit 1 - else - ref_lib_dir=$2 - fi - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./data_1p5m.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: data_1p5m.sh [-help]\n\ -Usage: data_1p5m.sh [-lib_map_path]\n\ -Usage: data_1p5m.sh [-reset_run]\n\ -Usage: data_1p5m.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/ies/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/ies/file_info.txt deleted file mode 100644 index 8f539960..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/ies/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, -data_1p5m.v,verilog,xil_defaultlib,../../../ip/data_1p5m/sim/data_1p5m.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/ies/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/ies/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/ies/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/ies/run.f b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/ies/run.f deleted file mode 100644 index 9e731398..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/ies/run.f +++ /dev/null @@ -1,17 +0,0 @@ --makelib ies_lib/xil_defaultlib -sv \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ --endlib --makelib ies_lib/xpm \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ --endlib --makelib ies_lib/blk_mem_gen_v8_4_3 \ - "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ --endlib --makelib ies_lib/xil_defaultlib \ - "../../../ip/data_1p5m/sim/data_1p5m.v" \ --endlib --makelib ies_lib/xil_defaultlib \ - glbl.v --endlib - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/README.txt deleted file mode 100644 index d3e5c3fa..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:35:28 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./data_1p5m.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './data_1p5m.sh' script. - -./data_1p5m.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./data_1p5m.sh -noclean_files - -For more information on the script, please type './data_1p5m.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/compile.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/compile.do deleted file mode 100644 index ada8e2f9..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/compile.do +++ /dev/null @@ -1,14 +0,0 @@ -vlib modelsim_lib/work -vlib modelsim_lib/msim - -vlib modelsim_lib/msim/xil_defaultlib - -vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib - -vlog -work xil_defaultlib -64 -incr \ -"../../../ip/data_1p5m/sim/data_1p5m.v" \ - - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/data_1m5.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/data_1m5.coe deleted file mode 100644 index 3dd9526c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/data_1m5.coe +++ /dev/null @@ -1,2051 +0,0 @@ -memory_initialization_radix = 2; -memory_initialization_vector = -1 -0 -1 -0 -1 -0 -1 -1 -0 -1 -1 -1 -0 -1 -1 -0 -1 -1 -1 -0 -0 -1 -1 -0 -1 -1 -1 -1 -0 -0 -1 -1 -1 -1 -0 -0 -1 -0 -0 -1 -0 -1 -1 -1 -0 -1 -0 -0 -1 -1 -0 -1 -0 -0 -1 -1 -0 -0 -0 -1 -0 -1 -0 -0 -1 -0 -1 -1 -0 -0 -0 -1 -1 -0 -0 -0 -0 -1 -1 -0 -1 -0 -1 -1 -1 -0 -0 -1 -1 -0 -1 -0 -0 -0 -1 -0 -1 -0 -0 -1 -1 -0 -0 -0 -0 -1 -0 -0 -0 -0 -1 -1 -1 -0 -0 -0 -1 -0 -0 -1 -0 -1 -0 -1 -1 -0 -0 -1 -0 -0 -1 -1 -1 -0 -1 -0 -1 -0 -0 -1 -1 -0 -0 -0 -1 -1 -0 -1 -0 -1 -0 -0 -0 -0 -1 -1 -1 -1 -1 -0 -1 -1 -0 -0 -0 -1 -1 -0 -1 -0 -0 -1 -0 -1 -0 -1 -1 -1 -1 -1 -0 -1 -1 -0 -0 -0 -1 -0 -1 -1 -1 -1 -1 -1 -1 -0 -0 -0 -0 -1 -1 -1 -0 -0 -1 -0 -0 -0 -0 -1 -1 -0 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-1 -1 -1 -0 -0 -1 -1 -0 -0 -0 -1 -1 -0 -0 -1 -1 -0 -1 -0 -1 -0 -1 -0 -0 -0 -0 -1 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/data_1p5m.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/data_1p5m.sh deleted file mode 100644 index 83db1796..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/data_1p5m.sh +++ /dev/null @@ -1,167 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : data_1p5m.sh -# Simulator : Mentor Graphics ModelSim Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:35:28 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: data_1p5m.sh [-help] -# usage: data_1p5m.sh [-lib_map_path] -# usage: data_1p5m.sh [-noclean_files] -# usage: data_1p5m.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'data_1p5m.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "data_1p5m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - vsim -64 -c -do "do {simulate.do}" -l simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./data_1p5m.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Copy modelsim.ini file -copy_setup_file() -{ - file="modelsim.ini" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - else - lib_map_path="C:/Mentor/CompLib/2019.1.3" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - cp $src_file . - fi -} - -# Create design library directory -create_lib_dir() -{ - lib_dir="modelsim_lib" - if [[ -e $lib_dir ]]; then - rm -rf $lib_dir - fi - - mkdir $lib_dir - -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./data_1p5m.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: data_1p5m.sh [-help]\n\ -Usage: data_1p5m.sh [-lib_map_path]\n\ -Usage: data_1p5m.sh [-reset_run]\n\ -Usage: data_1p5m.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/data_1p5m.udo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/data_1p5m.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/file_info.txt deleted file mode 100644 index 05d525e8..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/file_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -data_1p5m.v,verilog,xil_defaultlib,../../../ip/data_1p5m/sim/data_1p5m.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/modelsim.ini b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/modelsim.ini deleted file mode 100644 index 04a43f2c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/modelsim.ini +++ /dev/null @@ -1,2590 +0,0 @@ -; vsim modelsim.ini file -[Version] -INIVersion = "2020.4" - -; Copyright 1991-2020 Mentor Graphics Corporation -; -; All Rights Reserved. -; -; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF -; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. -; - -[Library] -others = $MODEL_TECH/../modelsim.ini -; -; VITAL concerns: -; -; The library ieee contains (among other packages) the packages of the -; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use -; the physical library ieee (recommended), or use the physical library -; vital2000, but not both. The design can use logical library ieee and/or -; vital2000 as long as each of these maps to the same physical library, either -; ieee or vital2000. -; -; A design using the 1995 version of the VITAL packages, whether or not -; it also uses the 2000 version of the VITAL packages, must have logical library -; name ieee mapped to physical library vital1995. (A design cannot use library -; vital1995 directly because some packages in this library use logical name ieee -; when referring to the other packages in the library.) The design source -; should use logical name ieee when referring to any packages there except the -; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical -; name vital2000 (mapped to physical library vital2000) to refer to those -; packages. -; ieee = $MODEL_TECH/../vital1995 -; -; For compatiblity with previous releases, logical library name vital2000 maps -; to library vital2000 (a different library than library ieee, containing the -; same packages). -; A design should not reference VITAL from both the ieee library and the -; vital2000 library because the vital packages are effectively different. -; A design that references both the ieee and vital2000 libraries must have -; both logical names ieee and vital2000 mapped to the same library, either of -; these: -; $MODEL_TECH/../ieee -; $MODEL_TECH/../vital2000 -; - -; added mapping for ADMS - -;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release -;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release -;mvc_lib = $MODEL_TECH/../mvc_lib - -; Automatically perform logical->physical mapping for physical libraries that -; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). -; The tail of the filesystem path name is chosen as the logical library name. -; For example, in the command "vopt -L ./path/to/lib1 -o opttop top", -; vopt automatically performs the mapping "lib1 -> ./path/to/lib1". -; See the User Manual for more details. -; -; AutoLibMapping = 0 - -secureip = C:/Mentor/CompLib/2019.1.3/secureip -unisim = C:/Mentor/CompLib/2019.1.3/unisim -unimacro = C:/Mentor/CompLib/2019.1.3/unimacro -unifast = C:/Mentor/CompLib/2019.1.3/unifast -unisims_ver = C:/Mentor/CompLib/2019.1.3/unisims_ver -unimacro_ver = C:/Mentor/CompLib/2019.1.3/unimacro_ver -unifast_ver = C:/Mentor/CompLib/2019.1.3/unifast_ver -simprims_ver = C:/Mentor/CompLib/2019.1.3/simprims_ver -xpm = C:/Mentor/CompLib/2019.1.3/xpm -xilinx_vip = C:/Mentor/CompLib/2019.1.3/xilinx_vip -advanced_io_wizard_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/advanced_io_wizard_phy_v1_0_0 -advanced_io_wizard_v1_0_0 = C:/Mentor/CompLib/2019.1.3/advanced_io_wizard_v1_0_0 -ahblite_axi_bridge_v3_0_14 = C:/Mentor/CompLib/2019.1.3/ahblite_axi_bridge_v3_0_14 -ai_noc = C:/Mentor/CompLib/2019.1.3/ai_noc -ai_pl_trig = C:/Mentor/CompLib/2019.1.3/ai_pl_trig -ai_pl = C:/Mentor/CompLib/2019.1.3/ai_pl -audio_clock_recovery_v1_0 = C:/Mentor/CompLib/2019.1.3/audio_clock_recovery_v1_0 -audio_tpg_v1_0_0 = C:/Mentor/CompLib/2019.1.3/audio_tpg_v1_0_0 -av_pat_gen_v1_0_0 = C:/Mentor/CompLib/2019.1.3/av_pat_gen_v1_0_0 -axis_infrastructure_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axis_infrastructure_v1_1_0 -axis_protocol_checker_v2_0_3 = C:/Mentor/CompLib/2019.1.3/axis_protocol_checker_v2_0_3 -axi_ahblite_bridge_v3_0_16 = C:/Mentor/CompLib/2019.1.3/axi_ahblite_bridge_v3_0_16 -axi_amm_bridge_v1_0_9 = C:/Mentor/CompLib/2019.1.3/axi_amm_bridge_v1_0_9 -axi_bram_ctrl_v4_1_1 = C:/Mentor/CompLib/2019.1.3/axi_bram_ctrl_v4_1_1 -axi_chip2chip_v5_0_6 = C:/Mentor/CompLib/2019.1.3/axi_chip2chip_v5_0_6 -axi_dbg_hub = C:/Mentor/CompLib/2019.1.3/axi_dbg_hub -axi_infrastructure_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axi_infrastructure_v1_1_0 -axi_jtag_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_jtag_v1_0_0 -axi_lite_ipif_v3_0_4 = C:/Mentor/CompLib/2019.1.3/axi_lite_ipif_v3_0_4 -axi_pcie3_v3_0_9 = C:/Mentor/CompLib/2019.1.3/axi_pcie3_v3_0_9 -axi_perf_mon_v5_0_21 = C:/Mentor/CompLib/2019.1.3/axi_perf_mon_v5_0_21 -axi_pmon_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_pmon_v1_0_0 -blk_mem_gen_v8_3_6 = C:/Mentor/CompLib/2019.1.3/blk_mem_gen_v8_3_6 -blk_mem_gen_v8_4_3 = C:/Mentor/CompLib/2019.1.3/blk_mem_gen_v8_4_3 -bsip_v1_1_0 = C:/Mentor/CompLib/2019.1.3/bsip_v1_1_0 -bs_mux_v1_0_0 = C:/Mentor/CompLib/2019.1.3/bs_mux_v1_0_0 -clk_gen_sim_v1_0_0 = C:/Mentor/CompLib/2019.1.3/clk_gen_sim_v1_0_0 -clk_vip_v1_0_2 = C:/Mentor/CompLib/2019.1.3/clk_vip_v1_0_2 -cmac_usplus_v2_4_5 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_4_5 -cmac_usplus_v2_5_3 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_5_3 -cmac_usplus_v2_6_2 = C:/Mentor/CompLib/2019.1.3/cmac_usplus_v2_6_2 -cmac_v2_3_5 = C:/Mentor/CompLib/2019.1.3/cmac_v2_3_5 -cmac_v2_4_1 = C:/Mentor/CompLib/2019.1.3/cmac_v2_4_1 -cmac_v2_5_1 = C:/Mentor/CompLib/2019.1.3/cmac_v2_5_1 -compact_gt_v1_0_5 = C:/Mentor/CompLib/2019.1.3/compact_gt_v1_0_5 -ddr4_pl_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/ddr4_pl_phy_v1_0_0 -ddr4_pl_v1_0_2 = C:/Mentor/CompLib/2019.1.3/ddr4_pl_v1_0_2 -dist_mem_gen_v8_0_13 = C:/Mentor/CompLib/2019.1.3/dist_mem_gen_v8_0_13 -ecc_v2_0_13 = C:/Mentor/CompLib/2019.1.3/ecc_v2_0_13 -emb_fifo_gen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/emb_fifo_gen_v1_0_1 -emb_mem_gen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/emb_mem_gen_v1_0_1 -emc_common_v3_0_5 = C:/Mentor/CompLib/2019.1.3/emc_common_v3_0_5 -ethernet_1_10_25g_v2_0_5 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_0_5 -ethernet_1_10_25g_v2_1_4 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_1_4 -ethernet_1_10_25g_v2_2_3 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_2_3 -ethernet_1_10_25g_v2_3_3 = C:/Mentor/CompLib/2019.1.3/ethernet_1_10_25g_v2_3_3 -fifo_generator_v13_0_6 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_0_6 -fifo_generator_v13_1_4 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_1_4 -fifo_generator_v13_2_4 = C:/Mentor/CompLib/2019.1.3/fifo_generator_v13_2_4 -fit_timer_v2_0_10 = C:/Mentor/CompLib/2019.1.3/fit_timer_v2_0_10 -generic_baseblocks_v2_1_0 = C:/Mentor/CompLib/2019.1.3/generic_baseblocks_v2_1_0 -gigantic_mux = C:/Mentor/CompLib/2019.1.3/gigantic_mux -gig_ethernet_pcs_pma_v16_1_6 = C:/Mentor/CompLib/2019.1.3/gig_ethernet_pcs_pma_v16_1_6 -gmii_to_rgmii_v4_0_7 = C:/Mentor/CompLib/2019.1.3/gmii_to_rgmii_v4_0_7 -gtwizard_ultrascale_v1_5_4 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_5_4 -gtwizard_ultrascale_v1_6_11 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_6_11 -gtwizard_ultrascale_v1_7_6 = C:/Mentor/CompLib/2019.1.3/gtwizard_ultrascale_v1_7_6 -hbm_v1_0_4 = C:/Mentor/CompLib/2019.1.3/hbm_v1_0_4 -hdcp22_cipher_dp_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdcp22_cipher_dp_v1_0_0 -hdcp22_cipher_v1_0_3 = C:/Mentor/CompLib/2019.1.3/hdcp22_cipher_v1_0_3 -hdcp22_rng_v1_0_1 = C:/Mentor/CompLib/2019.1.3/hdcp22_rng_v1_0_1 -hdcp_keymngmt_blk_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdcp_keymngmt_blk_v1_0_0 -hdcp_v1_0_3 = C:/Mentor/CompLib/2019.1.3/hdcp_v1_0_3 -hdmi_gt_controller_v1_0_0 = C:/Mentor/CompLib/2019.1.3/hdmi_gt_controller_v1_0_0 -high_speed_selectio_wiz_v3_2_3 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_2_3 -high_speed_selectio_wiz_v3_3_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_3_1 -high_speed_selectio_wiz_v3_4_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_4_1 -high_speed_selectio_wiz_v3_5_1 = C:/Mentor/CompLib/2019.1.3/high_speed_selectio_wiz_v3_5_1 -i2s_receiver_v1_0_3 = C:/Mentor/CompLib/2019.1.3/i2s_receiver_v1_0_3 -i2s_transmitter_v1_0_3 = C:/Mentor/CompLib/2019.1.3/i2s_transmitter_v1_0_3 -ibert_lib_v1_0_6 = C:/Mentor/CompLib/2019.1.3/ibert_lib_v1_0_6 -ieee802d3_clause74_fec_v1_0_4 = C:/Mentor/CompLib/2019.1.3/ieee802d3_clause74_fec_v1_0_4 -interlaken_v2_4_3 = C:/Mentor/CompLib/2019.1.3/interlaken_v2_4_3 -in_system_ibert_v1_0_9 = C:/Mentor/CompLib/2019.1.3/in_system_ibert_v1_0_9 -iomodule_v3_1_4 = C:/Mentor/CompLib/2019.1.3/iomodule_v3_1_4 -jesd204c_v4_1_1 = C:/Mentor/CompLib/2019.1.3/jesd204c_v4_1_1 -jesd204_v7_2_6 = C:/Mentor/CompLib/2019.1.3/jesd204_v7_2_6 -jtag_axi = C:/Mentor/CompLib/2019.1.3/jtag_axi -lib_cdc_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_cdc_v1_0_2 -lib_pkg_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_pkg_v1_0_2 -lmb_bram_if_cntlr_v4_0_16 = C:/Mentor/CompLib/2019.1.3/lmb_bram_if_cntlr_v4_0_16 -lmb_v10_v3_0_9 = C:/Mentor/CompLib/2019.1.3/lmb_v10_v3_0_9 -ltlib_v1_0_0 = C:/Mentor/CompLib/2019.1.3/ltlib_v1_0_0 -lut_buffer_v1_0_0 = C:/Mentor/CompLib/2019.1.3/lut_buffer_v1_0_0 -lut_buffer_v2_0_0 = C:/Mentor/CompLib/2019.1.3/lut_buffer_v2_0_0 -l_ethernet_v2_3_5 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_3_5 -l_ethernet_v2_4_3 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_4_3 -l_ethernet_v2_5_2 = C:/Mentor/CompLib/2019.1.3/l_ethernet_v2_5_2 -mammoth_transcode_v1_0_0 = C:/Mentor/CompLib/2019.1.3/mammoth_transcode_v1_0_0 -microblaze_v10_0_7 = C:/Mentor/CompLib/2019.1.3/microblaze_v10_0_7 -microblaze_v11_0_1 = C:/Mentor/CompLib/2019.1.3/microblaze_v11_0_1 -microblaze_v9_5_4 = C:/Mentor/CompLib/2019.1.3/microblaze_v9_5_4 -mii_to_rmii_v2_0_21 = C:/Mentor/CompLib/2019.1.3/mii_to_rmii_v2_0_21 -mipi_csi2_rx_ctrl_v1_0_8 = C:/Mentor/CompLib/2019.1.3/mipi_csi2_rx_ctrl_v1_0_8 -mipi_csi2_tx_ctrl_v1_0_4 = C:/Mentor/CompLib/2019.1.3/mipi_csi2_tx_ctrl_v1_0_4 -mipi_dphy_v4_1_4 = C:/Mentor/CompLib/2019.1.3/mipi_dphy_v4_1_4 -mipi_dsi_tx_ctrl_v1_0_7 = C:/Mentor/CompLib/2019.1.3/mipi_dsi_tx_ctrl_v1_0_7 -mrmac_v1_0_0 = C:/Mentor/CompLib/2019.1.3/mrmac_v1_0_0 -multi_channel_25g_rs_fec_v1_0_5 = C:/Mentor/CompLib/2019.1.3/multi_channel_25g_rs_fec_v1_0_5 -mutex_v2_1_10 = C:/Mentor/CompLib/2019.1.3/mutex_v2_1_10 -axi_tg_lib = C:/Mentor/CompLib/2019.1.3/axi_tg_lib -noc_na_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_na_v1_0_0 -noc_nidb_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nidb_v1_0_0 -noc_nmu_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nmu_v1_0_0 -noc_nps_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_nps_v1_0_0 -nvmeha_v1_0_0 = C:/Mentor/CompLib/2019.1.3/nvmeha_v1_0_0 -oddr_v1_0_0 = C:/Mentor/CompLib/2019.1.3/oddr_v1_0_0 -pci32_v5_0_12 = C:/Mentor/CompLib/2019.1.3/pci32_v5_0_12 -pci64_v5_0_11 = C:/Mentor/CompLib/2019.1.3/pci64_v5_0_11 -pcie_jtag_v1_0_0 = C:/Mentor/CompLib/2019.1.3/pcie_jtag_v1_0_0 -pc_cfr_v6_0_8 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_0_8 -pc_cfr_v6_1_4 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_1_4 -pc_cfr_v6_2_2 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_2_2 -pc_cfr_v6_3_0 = C:/Mentor/CompLib/2019.1.3/pc_cfr_v6_3_0 -picxo = C:/Mentor/CompLib/2019.1.3/picxo -qdma_v3_0_2 = C:/Mentor/CompLib/2019.1.3/qdma_v3_0_2 -rama_v1_1_2_lib = C:/Mentor/CompLib/2019.1.3/rama_v1_1_2_lib -rld3_pl_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/rld3_pl_phy_v1_0_0 -rld3_pl_v1_0_1 = C:/Mentor/CompLib/2019.1.3/rld3_pl_v1_0_1 -roe_framer_v2_0_1 = C:/Mentor/CompLib/2019.1.3/roe_framer_v2_0_1 -rst_vip_v1_0_3 = C:/Mentor/CompLib/2019.1.3/rst_vip_v1_0_3 -smartconnect_v1_0 = C:/Mentor/CompLib/2019.1.3/smartconnect_v1_0 -sd_fec_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sd_fec_v1_0_2 -sem_ultra_v3_1_11 = C:/Mentor/CompLib/2019.1.3/sem_ultra_v3_1_11 -sem_v4_1_12 = C:/Mentor/CompLib/2019.1.3/sem_v4_1_12 -shell_utils_msp432_bsl_crc_gen_v1_0_0 = C:/Mentor/CompLib/2019.1.3/shell_utils_msp432_bsl_crc_gen_v1_0_0 -sim_clk_gen_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sim_clk_gen_v1_0_2 -sim_rst_gen_v1_0_2 = C:/Mentor/CompLib/2019.1.3/sim_rst_gen_v1_0_2 -sim_trig_top_v1_0 = C:/Mentor/CompLib/2019.1.3/sim_trig_top_v1_0 -stm_v1_0 = C:/Mentor/CompLib/2019.1.3/stm_v1_0 -stm_v1_0_0 = C:/Mentor/CompLib/2019.1.3/stm_v1_0_0 -system_cache_v4_0_6 = C:/Mentor/CompLib/2019.1.3/system_cache_v4_0_6 -ta_dma_v1_0_3 = C:/Mentor/CompLib/2019.1.3/ta_dma_v1_0_3 -tcc_decoder_3gpplte_v3_0_6 = C:/Mentor/CompLib/2019.1.3/tcc_decoder_3gpplte_v3_0_6 -ten_gig_eth_mac_v15_1_7 = C:/Mentor/CompLib/2019.1.3/ten_gig_eth_mac_v15_1_7 -ten_gig_eth_pcs_pma_v6_0_15 = C:/Mentor/CompLib/2019.1.3/ten_gig_eth_pcs_pma_v6_0_15 -timer_sync_1588_v1_2_4 = C:/Mentor/CompLib/2019.1.3/timer_sync_1588_v1_2_4 -tmr_inject_v1_0_3 = C:/Mentor/CompLib/2019.1.3/tmr_inject_v1_0_3 -tmr_manager_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tmr_manager_v1_0_4 -tmr_voter_v1_0_2 = C:/Mentor/CompLib/2019.1.3/tmr_voter_v1_0_2 -tsn_endpoint_ethernet_mac_block_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tsn_endpoint_ethernet_mac_block_v1_0_4 -uhdsdi_gt_v1_0_3 = C:/Mentor/CompLib/2019.1.3/uhdsdi_gt_v1_0_3 -uhdsdi_gt_v2_0_0 = C:/Mentor/CompLib/2019.1.3/uhdsdi_gt_v2_0_0 -usxgmii_v1_0_5 = C:/Mentor/CompLib/2019.1.3/usxgmii_v1_0_5 -usxgmii_v1_1_0 = C:/Mentor/CompLib/2019.1.3/usxgmii_v1_1_0 -util_idelay_ctrl_v1_0_1 = C:/Mentor/CompLib/2019.1.3/util_idelay_ctrl_v1_0_1 -util_reduced_logic_v2_0_4 = C:/Mentor/CompLib/2019.1.3/util_reduced_logic_v2_0_4 -util_vector_logic_v2_0_1 = C:/Mentor/CompLib/2019.1.3/util_vector_logic_v2_0_1 -ba317 = C:/Mentor/CompLib/2019.1.3/ba317 -vfb_v1_0_13 = C:/Mentor/CompLib/2019.1.3/vfb_v1_0_13 -video_frame_crc_v1_0_1 = C:/Mentor/CompLib/2019.1.3/video_frame_crc_v1_0_1 -vid_edid_v1_0_0 = C:/Mentor/CompLib/2019.1.3/vid_edid_v1_0_0 -vid_phy_controller_v2_1_5 = C:/Mentor/CompLib/2019.1.3/vid_phy_controller_v2_1_5 -vid_phy_controller_v2_2_3 = C:/Mentor/CompLib/2019.1.3/vid_phy_controller_v2_2_3 -v_axi4s_remap_v1_0_11 = C:/Mentor/CompLib/2019.1.3/v_axi4s_remap_v1_0_11 -v_csc_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_csc_v1_0_13 -v_deinterlacer_v4_0_12 = C:/Mentor/CompLib/2019.1.3/v_deinterlacer_v4_0_12 -v_deinterlacer_v5_0_13 = C:/Mentor/CompLib/2019.1.3/v_deinterlacer_v5_0_13 -v_demosaic_v1_0_5 = C:/Mentor/CompLib/2019.1.3/v_demosaic_v1_0_5 -v_frmbuf_rd_v2_1_2 = C:/Mentor/CompLib/2019.1.3/v_frmbuf_rd_v2_1_2 -v_frmbuf_wr_v2_1_2 = C:/Mentor/CompLib/2019.1.3/v_frmbuf_wr_v2_1_2 -v_gamma_lut_v1_0_5 = C:/Mentor/CompLib/2019.1.3/v_gamma_lut_v1_0_5 -v_hcresampler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_hcresampler_v1_0_13 -v_hdmi_rx_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_rx_v2_0_0 -v_hdmi_rx_v3_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_rx_v3_0_0 -v_hdmi_tx_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_tx_v2_0_0 -v_hdmi_tx_v3_0_0 = C:/Mentor/CompLib/2019.1.3/v_hdmi_tx_v3_0_0 -v_hscaler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_hscaler_v1_0_13 -v_letterbox_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_letterbox_v1_0_13 -v_mix_v3_0_3 = C:/Mentor/CompLib/2019.1.3/v_mix_v3_0_3 -v_mix_v4_0_0 = C:/Mentor/CompLib/2019.1.3/v_mix_v4_0_0 -v_multi_scaler_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_multi_scaler_v1_0_1 -v_scenechange_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_scenechange_v1_0_1 -v_sdi_rx_vid_bridge_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_sdi_rx_vid_bridge_v2_0_0 -v_smpte_sdi_v3_0_8 = C:/Mentor/CompLib/2019.1.3/v_smpte_sdi_v3_0_8 -v_smpte_uhdsdi_rx_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_rx_v1_0_0 -v_smpte_uhdsdi_tx_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_tx_v1_0_0 -v_smpte_uhdsdi_v1_0_7 = C:/Mentor/CompLib/2019.1.3/v_smpte_uhdsdi_v1_0_7 -v_tpg_v7_0_13 = C:/Mentor/CompLib/2019.1.3/v_tpg_v7_0_13 -v_tpg_v8_0_1 = C:/Mentor/CompLib/2019.1.3/v_tpg_v8_0_1 -v_uhdsdi_audio_v1_0_0 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v1_0_0 -v_uhdsdi_audio_v1_1_0 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v1_1_0 -v_uhdsdi_audio_v2_0_1 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_audio_v2_0_1 -v_uhdsdi_vidgen_v1_0_1 = C:/Mentor/CompLib/2019.1.3/v_uhdsdi_vidgen_v1_0_1 -v_vcresampler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_vcresampler_v1_0_13 -v_vid_in_axi4s_v4_0_9 = C:/Mentor/CompLib/2019.1.3/v_vid_in_axi4s_v4_0_9 -v_vscaler_v1_0_13 = C:/Mentor/CompLib/2019.1.3/v_vscaler_v1_0_13 -xaui_v12_3_6 = C:/Mentor/CompLib/2019.1.3/xaui_v12_3_6 -xbip_dsp48_wrapper_v3_0_4 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_wrapper_v3_0_4 -xbip_utils_v3_0_10 = C:/Mentor/CompLib/2019.1.3/xbip_utils_v3_0_10 -xdma_v4_1_3 = C:/Mentor/CompLib/2019.1.3/xdma_v4_1_3 -xhmc_v1_0_9 = C:/Mentor/CompLib/2019.1.3/xhmc_v1_0_9 -xlconcat_v2_1_3 = C:/Mentor/CompLib/2019.1.3/xlconcat_v2_1_3 -xlconstant_v1_1_6 = C:/Mentor/CompLib/2019.1.3/xlconstant_v1_1_6 -xlslice_v1_0_2 = C:/Mentor/CompLib/2019.1.3/xlslice_v1_0_2 -xsdbm_v2_0_0 = C:/Mentor/CompLib/2019.1.3/xsdbm_v2_0_0 -xsdbm_v3_0_0 = C:/Mentor/CompLib/2019.1.3/xsdbm_v3_0_0 -xxv_ethernet_v2_4_5 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v2_4_5 -xxv_ethernet_v2_5_3 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v2_5_3 -xxv_ethernet_v3_0_3 = C:/Mentor/CompLib/2019.1.3/xxv_ethernet_v3_0_3 -zynq_ultra_ps_e_v3_2_3 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_v3_2_3 -zynq_ultra_ps_e_v3_3_0 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_v3_3_0 -lib_srl_fifo_v1_0_2 = C:/Mentor/CompLib/2019.1.3/lib_srl_fifo_v1_0_2 -lib_fifo_v1_0_13 = C:/Mentor/CompLib/2019.1.3/lib_fifo_v1_0_13 -axi_datamover_v5_1_21 = C:/Mentor/CompLib/2019.1.3/axi_datamover_v5_1_21 -amm_axi_bridge_v1_0_5 = C:/Mentor/CompLib/2019.1.3/amm_axi_bridge_v1_0_5 -axis_interconnect_v1_1_17 = C:/Mentor/CompLib/2019.1.3/axis_interconnect_v1_1_17 -ats_switch_v1_0_2 = C:/Mentor/CompLib/2019.1.3/ats_switch_v1_0_2 -audio_formatter_v1_0_1 = C:/Mentor/CompLib/2019.1.3/audio_formatter_v1_0_1 -axi4stream_vip_v1_1_5 = C:/Mentor/CompLib/2019.1.3/axi4stream_vip_v1_1_5 -v_tc_v6_1_13 = C:/Mentor/CompLib/2019.1.3/v_tc_v6_1_13 -v_axi4s_vid_out_v4_0_10 = C:/Mentor/CompLib/2019.1.3/v_axi4s_vid_out_v4_0_10 -axi4svideo_bridge_v1_0_10 = C:/Mentor/CompLib/2019.1.3/axi4svideo_bridge_v1_0_10 -axis_accelerator_adapter_v2_1_15 = C:/Mentor/CompLib/2019.1.3/axis_accelerator_adapter_v2_1_15 -axis_broadcaster_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axis_broadcaster_v1_1_18 -axis_clock_converter_v1_1_20 = C:/Mentor/CompLib/2019.1.3/axis_clock_converter_v1_1_20 -axis_combiner_v1_1_17 = C:/Mentor/CompLib/2019.1.3/axis_combiner_v1_1_17 -axis_data_fifo_v1_1_20 = C:/Mentor/CompLib/2019.1.3/axis_data_fifo_v1_1_20 -axis_data_fifo_v2_0_1 = C:/Mentor/CompLib/2019.1.3/axis_data_fifo_v2_0_1 -axis_register_slice_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_register_slice_v1_1_19 -axis_dwidth_converter_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axis_dwidth_converter_v1_1_18 -axis_subset_converter_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_subset_converter_v1_1_19 -axis_switch_v1_1_19 = C:/Mentor/CompLib/2019.1.3/axis_switch_v1_1_19 -axis_vio_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axis_vio_v1_0_0 -axi_apb_bridge_v3_0_15 = C:/Mentor/CompLib/2019.1.3/axi_apb_bridge_v3_0_15 -axi_bram_ctrl_v4_0_14 = C:/Mentor/CompLib/2019.1.3/axi_bram_ctrl_v4_0_14 -axi_sg_v4_1_12 = C:/Mentor/CompLib/2019.1.3/axi_sg_v4_1_12 -axi_cdma_v4_1_19 = C:/Mentor/CompLib/2019.1.3/axi_cdma_v4_1_19 -axi_clock_converter_v2_1_18 = C:/Mentor/CompLib/2019.1.3/axi_clock_converter_v2_1_18 -axi_data_fifo_v2_1_18 = C:/Mentor/CompLib/2019.1.3/axi_data_fifo_v2_1_18 -axi_register_slice_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_register_slice_v2_1_19 -axi_crossbar_v2_1_20 = C:/Mentor/CompLib/2019.1.3/axi_crossbar_v2_1_20 -axi_dma_v7_1_20 = C:/Mentor/CompLib/2019.1.3/axi_dma_v7_1_20 -axi_protocol_converter_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_protocol_converter_v2_1_19 -axi_dwidth_converter_v2_1_19 = C:/Mentor/CompLib/2019.1.3/axi_dwidth_converter_v2_1_19 -axi_emc_v3_0_19 = C:/Mentor/CompLib/2019.1.3/axi_emc_v3_0_19 -axi_epc_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_epc_v2_0_22 -lib_bmg_v1_0_12 = C:/Mentor/CompLib/2019.1.3/lib_bmg_v1_0_12 -axi_ethernetlite_v3_0_17 = C:/Mentor/CompLib/2019.1.3/axi_ethernetlite_v3_0_17 -axi_ethernet_buffer_v2_0_20 = C:/Mentor/CompLib/2019.1.3/axi_ethernet_buffer_v2_0_20 -axi_fifo_mm_s_v4_1_16 = C:/Mentor/CompLib/2019.1.3/axi_fifo_mm_s_v4_1_16 -axi_fifo_mm_s_v4_2_1 = C:/Mentor/CompLib/2019.1.3/axi_fifo_mm_s_v4_2_1 -axi_firewall_v1_0_7 = C:/Mentor/CompLib/2019.1.3/axi_firewall_v1_0_7 -interrupt_control_v3_1_4 = C:/Mentor/CompLib/2019.1.3/interrupt_control_v3_1_4 -axi_gpio_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_gpio_v2_0_21 -axi_hwicap_v3_0_23 = C:/Mentor/CompLib/2019.1.3/axi_hwicap_v3_0_23 -axi_iic_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_iic_v2_0_22 -axi_intc_v4_1_13 = C:/Mentor/CompLib/2019.1.3/axi_intc_v4_1_13 -axi_interconnect_v1_7_16 = C:/Mentor/CompLib/2019.1.3/axi_interconnect_v1_7_16 -axi_master_burst_v2_0_7 = C:/Mentor/CompLib/2019.1.3/axi_master_burst_v2_0_7 -axi_msg_v1_0_5 = C:/Mentor/CompLib/2019.1.3/axi_msg_v1_0_5 -axi_mcdma_v1_0_5 = C:/Mentor/CompLib/2019.1.3/axi_mcdma_v1_0_5 -axi_mcdma_v1_1_0 = C:/Mentor/CompLib/2019.1.3/axi_mcdma_v1_1_0 -axi_memory_init_v1_0_0 = C:/Mentor/CompLib/2019.1.3/axi_memory_init_v1_0_0 -axi_mm2s_mapper_v1_1_18 = C:/Mentor/CompLib/2019.1.3/axi_mm2s_mapper_v1_1_18 -axi_mmu_v2_1_17 = C:/Mentor/CompLib/2019.1.3/axi_mmu_v2_1_17 -axi_pcie_v2_9_1 = C:/Mentor/CompLib/2019.1.3/axi_pcie_v2_9_1 -axi_protocol_checker_v2_0_5 = C:/Mentor/CompLib/2019.1.3/axi_protocol_checker_v2_0_5 -axi_quad_spi_v3_2_18 = C:/Mentor/CompLib/2019.1.3/axi_quad_spi_v3_2_18 -axi_sideband_util_v1_0_3 = C:/Mentor/CompLib/2019.1.3/axi_sideband_util_v1_0_3 -axi_tft_v2_0_22 = C:/Mentor/CompLib/2019.1.3/axi_tft_v2_0_22 -axi_timebase_wdt_v3_0_11 = C:/Mentor/CompLib/2019.1.3/axi_timebase_wdt_v3_0_11 -axi_timer_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_timer_v2_0_21 -axi_traffic_gen_v2_0_20 = C:/Mentor/CompLib/2019.1.3/axi_traffic_gen_v2_0_20 -axi_traffic_gen_v3_0_5 = C:/Mentor/CompLib/2019.1.3/axi_traffic_gen_v3_0_5 -axi_uart16550_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_uart16550_v2_0_21 -axi_uartlite_v2_0_23 = C:/Mentor/CompLib/2019.1.3/axi_uartlite_v2_0_23 -axi_usb2_device_v5_0_20 = C:/Mentor/CompLib/2019.1.3/axi_usb2_device_v5_0_20 -axi_utils_v2_0_6 = C:/Mentor/CompLib/2019.1.3/axi_utils_v2_0_6 -axi_vdma_v6_3_7 = C:/Mentor/CompLib/2019.1.3/axi_vdma_v6_3_7 -xbip_pipe_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_pipe_v3_0_6 -xbip_dsp48_addsub_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_addsub_v3_0_6 -xbip_addsub_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_addsub_v3_0_6 -c_reg_fd_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_reg_fd_v12_0_6 -c_addsub_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_addsub_v12_0_13 -axi_vfifo_ctrl_v2_0_21 = C:/Mentor/CompLib/2019.1.3/axi_vfifo_ctrl_v2_0_21 -axi_vip_v1_1_5 = C:/Mentor/CompLib/2019.1.3/axi_vip_v1_1_5 -bs_switch_v1_0_0 = C:/Mentor/CompLib/2019.1.3/bs_switch_v1_0_0 -canfd_v2_0_1 = C:/Mentor/CompLib/2019.1.3/canfd_v2_0_1 -can_v5_0_22 = C:/Mentor/CompLib/2019.1.3/can_v5_0_22 -cic_compiler_v4_0_14 = C:/Mentor/CompLib/2019.1.3/cic_compiler_v4_0_14 -xbip_bram18k_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_bram18k_v3_0_6 -mult_gen_v12_0_15 = C:/Mentor/CompLib/2019.1.3/mult_gen_v12_0_15 -cmpy_v6_0_17 = C:/Mentor/CompLib/2019.1.3/cmpy_v6_0_17 -c_mux_bit_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_mux_bit_v12_0_6 -c_shift_ram_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_shift_ram_v12_0_13 -c_mux_bus_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_mux_bus_v12_0_6 -c_gate_bit_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_gate_bit_v12_0_6 -xbip_counter_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_counter_v3_0_6 -c_counter_binary_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_counter_binary_v12_0_13 -c_compare_v12_0_6 = C:/Mentor/CompLib/2019.1.3/c_compare_v12_0_6 -convolution_v9_0_14 = C:/Mentor/CompLib/2019.1.3/convolution_v9_0_14 -cordic_v6_0_15 = C:/Mentor/CompLib/2019.1.3/cordic_v6_0_15 -cpri_v8_10_3 = C:/Mentor/CompLib/2019.1.3/cpri_v8_10_3 -xbip_dsp48_acc_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_acc_v3_0_6 -xbip_accum_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_accum_v3_0_6 -c_accum_v12_0_13 = C:/Mentor/CompLib/2019.1.3/c_accum_v12_0_13 -xbip_dsp48_multadd_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_multadd_v3_0_6 -dds_compiler_v6_0_18 = C:/Mentor/CompLib/2019.1.3/dds_compiler_v6_0_18 -dft_v4_0_16 = C:/Mentor/CompLib/2019.1.3/dft_v4_0_16 -dft_v4_1_1 = C:/Mentor/CompLib/2019.1.3/dft_v4_1_1 -displayport_v7_0_11 = C:/Mentor/CompLib/2019.1.3/displayport_v7_0_11 -displayport_v8_1_1 = C:/Mentor/CompLib/2019.1.3/displayport_v8_1_1 -displayport_v9_0_1 = C:/Mentor/CompLib/2019.1.3/displayport_v9_0_1 -xbip_dsp48_mult_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_mult_v3_0_6 -floating_point_v7_0_16 = C:/Mentor/CompLib/2019.1.3/floating_point_v7_0_16 -div_gen_v5_1_15 = C:/Mentor/CompLib/2019.1.3/div_gen_v5_1_15 -dp_videoaxi4s_bridge_v1_0_0 = C:/Mentor/CompLib/2019.1.3/dp_videoaxi4s_bridge_v1_0_0 -dsp_macro_v1_0_0 = C:/Mentor/CompLib/2019.1.3/dsp_macro_v1_0_0 -fir_compiler_v5_2_6 = C:/Mentor/CompLib/2019.1.3/fir_compiler_v5_2_6 -duc_ddc_compiler_v3_0_15 = C:/Mentor/CompLib/2019.1.3/duc_ddc_compiler_v3_0_15 -ernic_v1_0_1 = C:/Mentor/CompLib/2019.1.3/ernic_v1_0_1 -etrnic_v1_0_3 = C:/Mentor/CompLib/2019.1.3/etrnic_v1_0_3 -etrnic_v1_1_2 = C:/Mentor/CompLib/2019.1.3/etrnic_v1_1_2 -fc32_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/fc32_rs_fec_v1_0_11 -fec_5g_common_v1_0_1 = C:/Mentor/CompLib/2019.1.3/fec_5g_common_v1_0_1 -fec_5g_common_v1_1_1 = C:/Mentor/CompLib/2019.1.3/fec_5g_common_v1_1_1 -fir_compiler_v7_2_12 = C:/Mentor/CompLib/2019.1.3/fir_compiler_v7_2_12 -flexo_100g_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/flexo_100g_rs_fec_v1_0_11 -floating_point_v7_1_8 = C:/Mentor/CompLib/2019.1.3/floating_point_v7_1_8 -g709_rs_encoder_v2_2_6 = C:/Mentor/CompLib/2019.1.3/g709_rs_encoder_v2_2_6 -rs_toolbox_v9_0_7 = C:/Mentor/CompLib/2019.1.3/rs_toolbox_v9_0_7 -g709_rs_decoder_v2_2_8 = C:/Mentor/CompLib/2019.1.3/g709_rs_decoder_v2_2_8 -g709_fec_v2_3_5 = C:/Mentor/CompLib/2019.1.3/g709_fec_v2_3_5 -g709_fec_v2_4_1 = C:/Mentor/CompLib/2019.1.3/g709_fec_v2_4_1 -g975_efec_i4_v1_0_17 = C:/Mentor/CompLib/2019.1.3/g975_efec_i4_v1_0_17 -g975_efec_i7_v2_0_18 = C:/Mentor/CompLib/2019.1.3/g975_efec_i7_v2_0_18 -ieee802d3_200g_rs_fec_v1_0_7 = C:/Mentor/CompLib/2019.1.3/ieee802d3_200g_rs_fec_v1_0_7 -ieee802d3_25g_rs_fec_v1_0_13 = C:/Mentor/CompLib/2019.1.3/ieee802d3_25g_rs_fec_v1_0_13 -ieee802d3_400g_rs_fec_v1_0_7 = C:/Mentor/CompLib/2019.1.3/ieee802d3_400g_rs_fec_v1_0_7 -ieee802d3_50g_rs_fec_v1_0_11 = C:/Mentor/CompLib/2019.1.3/ieee802d3_50g_rs_fec_v1_0_11 -ieee802d3_50g_rs_fec_v2_0_1 = C:/Mentor/CompLib/2019.1.3/ieee802d3_50g_rs_fec_v2_0_1 -ieee802d3_rs_fec_v1_0_15 = C:/Mentor/CompLib/2019.1.3/ieee802d3_rs_fec_v1_0_15 -ieee802d3_rs_fec_v2_0_5 = C:/Mentor/CompLib/2019.1.3/ieee802d3_rs_fec_v2_0_5 -ldpc_v2_0_3 = C:/Mentor/CompLib/2019.1.3/ldpc_v2_0_3 -lte_3gpp_channel_estimator_v2_0_16 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_channel_estimator_v2_0_16 -lte_3gpp_mimo_decoder_v3_0_15 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_mimo_decoder_v3_0_15 -lte_3gpp_mimo_encoder_v4_0_14 = C:/Mentor/CompLib/2019.1.3/lte_3gpp_mimo_encoder_v4_0_14 -tcc_encoder_3gpplte_v4_0_15 = C:/Mentor/CompLib/2019.1.3/tcc_encoder_3gpplte_v4_0_15 -lte_dl_channel_encoder_v3_0_15 = C:/Mentor/CompLib/2019.1.3/lte_dl_channel_encoder_v3_0_15 -lte_dl_channel_encoder_v4_0_0 = C:/Mentor/CompLib/2019.1.3/lte_dl_channel_encoder_v4_0_0 -xfft_v7_2_9 = C:/Mentor/CompLib/2019.1.3/xfft_v7_2_9 -lte_fft_v2_0_18 = C:/Mentor/CompLib/2019.1.3/lte_fft_v2_0_18 -xfft_v9_1_2 = C:/Mentor/CompLib/2019.1.3/xfft_v9_1_2 -lte_fft_v2_1_0 = C:/Mentor/CompLib/2019.1.3/lte_fft_v2_1_0 -xbip_dsp48_multacc_v3_0_6 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_multacc_v3_0_6 -lte_pucch_receiver_v2_0_16 = C:/Mentor/CompLib/2019.1.3/lte_pucch_receiver_v2_0_16 -xbip_multadd_v3_0_14 = C:/Mentor/CompLib/2019.1.3/xbip_multadd_v3_0_14 -lte_rach_detector_v3_1_5 = C:/Mentor/CompLib/2019.1.3/lte_rach_detector_v3_1_5 -lte_ul_channel_decoder_v4_0_16 = C:/Mentor/CompLib/2019.1.3/lte_ul_channel_decoder_v4_0_16 -mailbox_v2_1_11 = C:/Mentor/CompLib/2019.1.3/mailbox_v2_1_11 -mdm_v3_2_16 = C:/Mentor/CompLib/2019.1.3/mdm_v3_2_16 -iomodule_v3_0 = C:/Mentor/CompLib/2019.1.3/iomodule_v3_0 -lmb_bram_if_cntlr_v4_0 = C:/Mentor/CompLib/2019.1.3/lmb_bram_if_cntlr_v4_0 -lmb_v10_v3_0 = C:/Mentor/CompLib/2019.1.3/lmb_v10_v3_0 -axi_lite_ipif_v3_0 = C:/Mentor/CompLib/2019.1.3/axi_lite_ipif_v3_0 -mdm_v3_2 = C:/Mentor/CompLib/2019.1.3/mdm_v3_2 -microblaze_mcs_v2_3_6 = C:/Mentor/CompLib/2019.1.3/microblaze_mcs_v2_3_6 -noc_mc_ddr4_phy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/noc_mc_ddr4_phy_v1_0_0 -perf_axi_tg_v1_0_8 = C:/Mentor/CompLib/2019.1.3/perf_axi_tg_v1_0_8 -polar_v1_0_3 = C:/Mentor/CompLib/2019.1.3/polar_v1_0_3 -prc_v1_3_2 = C:/Mentor/CompLib/2019.1.3/prc_v1_3_2 -processing_system7_vip_v1_0_7 = C:/Mentor/CompLib/2019.1.3/processing_system7_vip_v1_0_7 -proc_sys_reset_v5_0_13 = C:/Mentor/CompLib/2019.1.3/proc_sys_reset_v5_0_13 -pr_axi_shutdown_manager_v1_0_1 = C:/Mentor/CompLib/2019.1.3/pr_axi_shutdown_manager_v1_0_1 -pr_bitstream_monitor_v1_0_1 = C:/Mentor/CompLib/2019.1.3/pr_bitstream_monitor_v1_0_1 -pr_decoupler_v1_0_7 = C:/Mentor/CompLib/2019.1.3/pr_decoupler_v1_0_7 -quadsgmii_v3_4_6 = C:/Mentor/CompLib/2019.1.3/quadsgmii_v3_4_6 -rs_decoder_v9_0_16 = C:/Mentor/CompLib/2019.1.3/rs_decoder_v9_0_16 -rs_encoder_v9_0_15 = C:/Mentor/CompLib/2019.1.3/rs_encoder_v9_0_15 -rxaui_v4_4_6 = C:/Mentor/CompLib/2019.1.3/rxaui_v4_4_6 -sd_fec_v1_1_3 = C:/Mentor/CompLib/2019.1.3/sd_fec_v1_1_3 -sid_v8_0_14 = C:/Mentor/CompLib/2019.1.3/sid_v8_0_14 -soft_ecc_proxy_v1_0_0 = C:/Mentor/CompLib/2019.1.3/soft_ecc_proxy_v1_0_0 -spdif_v2_0_21 = C:/Mentor/CompLib/2019.1.3/spdif_v2_0_21 -srio_gen2_v4_1_6 = C:/Mentor/CompLib/2019.1.3/srio_gen2_v4_1_6 -switch_core_top_v1_0_7 = C:/Mentor/CompLib/2019.1.3/switch_core_top_v1_0_7 -sync_ip = C:/Mentor/CompLib/2019.1.3/sync_ip -tcc_decoder_3gppmm_v2_0_18 = C:/Mentor/CompLib/2019.1.3/tcc_decoder_3gppmm_v2_0_18 -tcc_encoder_3gpp_v5_0_15 = C:/Mentor/CompLib/2019.1.3/tcc_encoder_3gpp_v5_0_15 -tmr_comparator_v1_0_2 = C:/Mentor/CompLib/2019.1.3/tmr_comparator_v1_0_2 -tmr_sem_v1_0_9 = C:/Mentor/CompLib/2019.1.3/tmr_sem_v1_0_9 -tri_mode_ethernet_mac_v9_0_14 = C:/Mentor/CompLib/2019.1.3/tri_mode_ethernet_mac_v9_0_14 -tsn_temac_v1_0_4 = C:/Mentor/CompLib/2019.1.3/tsn_temac_v1_0_4 -videoaxi4s_bridge_v1_0_5 = C:/Mentor/CompLib/2019.1.3/videoaxi4s_bridge_v1_0_5 -viterbi_v9_1_11 = C:/Mentor/CompLib/2019.1.3/viterbi_v9_1_11 -v_ccm_v6_0_15 = C:/Mentor/CompLib/2019.1.3/v_ccm_v6_0_15 -v_cfa_v7_0_14 = C:/Mentor/CompLib/2019.1.3/v_cfa_v7_0_14 -v_cresample_v4_0_14 = C:/Mentor/CompLib/2019.1.3/v_cresample_v4_0_14 -v_dual_splitter_v1_0_9 = C:/Mentor/CompLib/2019.1.3/v_dual_splitter_v1_0_9 -v_enhance_v8_0_15 = C:/Mentor/CompLib/2019.1.3/v_enhance_v8_0_15 -v_gamma_v7_0_15 = C:/Mentor/CompLib/2019.1.3/v_gamma_v7_0_15 -v_osd_v6_0_16 = C:/Mentor/CompLib/2019.1.3/v_osd_v6_0_16 -v_rgb2ycrcb_v7_1_13 = C:/Mentor/CompLib/2019.1.3/v_rgb2ycrcb_v7_1_13 -v_vid_sdi_tx_bridge_v2_0_0 = C:/Mentor/CompLib/2019.1.3/v_vid_sdi_tx_bridge_v2_0_0 -v_ycrcb2rgb_v7_1_13 = C:/Mentor/CompLib/2019.1.3/v_ycrcb2rgb_v7_1_13 -xbip_dsp48_macro_v3_0_17 = C:/Mentor/CompLib/2019.1.3/xbip_dsp48_macro_v3_0_17 -xfft_v9_0_17 = C:/Mentor/CompLib/2019.1.3/xfft_v9_0_17 -xsdbs_v1_0_2 = C:/Mentor/CompLib/2019.1.3/xsdbs_v1_0_2 -zynq_ultra_ps_e_vip_v1_0_5 = C:/Mentor/CompLib/2019.1.3/zynq_ultra_ps_e_vip_v1_0_5 -[DefineOptionset] -; Define optionset entries for the various compilers, vmake, and vsim. -; These option sets can be used with the "-optionset " syntax. -; i.e. -; vlog -optionset COMPILEDEBUG top.sv -; vsim -optionset UVMDEBUG my_top -; -; Following are some useful examples. - -; define a vsim optionset for uvm debugging -UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop - -; define a vopt optionset for debugging -VOPTDEBUG = +acc -debugdb - -[encryption] -; For vencrypt and vhencrypt. - -; Controls whether to encrypt whole files by ignoring all protect directives -; (except "viewport" and "interface_viewport") that are present in the input. -; The default is 0, use embedded protect directives to control the encryption. -; Set this to 1 to encrypt whole files by ignoring embedded protect directives. -; wholefile = 0 - -; Sets the data_method to use for the symmetric session key. -; The session key is a symmetric key that is randomly generated for each -; protected region (envelope) and is the heart of all encryption. This is used -; to set the length of the session key to generate and use when encrypting the -; HDL text. Supported values are aes128, aes192, and aes256. -; data_method = aes128 - -; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption -; "recipe" comprising an optional common block, at least one tool block (which -; contains the key public key), and the text to be encrypted. The common block -; and any of the tool blocks may contain rights in the form of the "control" -; directive. The text to be encrypted is specified either by setting -; "wholefile" to 1 or by embedding protect "begin" and "end" directives in -; the input HDL files. - -; Common recipe specification file. This file is optional. Its presence will -; require at least one "toolblock" to be specified. -; Directives such as "author" "author_info" and "data_method", -; as well as the common block license specification, go in this file. -; common = - -; Tool block specification recipe(s). Public key file with optional tool block -; file name. May be multiply-defined; at least one tool block is required if -; a recipe is being specified. -; Key file is a file name with no extension (.deprecated or .active will be -; supplied by the encryption tool). -; Rights file name is optional. -; toolblock = [,]{:[,]} - -; Location of directory containing recipe files. -; The default location is in the product installation directory. -; keyring = $MODEL_TECH/../keyring - -; Enable encryption statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list] -; Add '-' to disable specific statistics. Default is [cmd,msg]. -Stats = cmd,msg - -[vcom] -; VHDL93 variable selects language version as the default. -; Default is VHDL-2002. -; Value of 0 or 1987 for VHDL-1987. -; Value of 1 or 1993 for VHDL-1993. -; Default or value of 2 or 2002 for VHDL-2002. -; Value of 3 or 2008 for VHDL-2008 -; Value of 4 or ams99 for VHDL-AMS-1999 -; Value of 5 or ams07 for VHDL-AMS-2007 -VHDL93 = 2002 - -; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. -; ignoreStandardRealVector = 1 - -; Show source line containing error. Default is off. -; Show_source = 1 - -; Turn off unbound-component warnings. Default is on. -; Show_Warning1 = 0 - -; Turn off process-without-a-wait-statement warnings. Default is on. -; Show_Warning2 = 0 - -; Turn off null-range warnings. Default is on. -; Show_Warning3 = 0 - -; Turn off no-space-in-time-literal warnings. Default is on. -; Show_Warning4 = 0 - -; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. -; Show_Warning5 = 0 - -; Turn off optimization for IEEE std_logic_1164 package. Default is on. -; Optimize_1164 = 0 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Turn on resolving of ambiguous function overloading in favor of the -; "explicit" function declaration (not the one automatically created by -; the compiler for each type declaration). Default is off. -; The .ini file has Explicit enabled so that std_logic_signed/unsigned -; will match the behavior of synthesis tools. -Explicit = 1 - -; Turn off acceleration of the VITAL packages. Default is to accelerate. -; NoVital = 1 - -; Turn off VITAL compliance checking. Default is checking on. -; NoVitalCheck = 1 - -; Ignore VITAL compliance checking errors. Default is to not ignore. -; IgnoreVitalErrors = 1 - -; Turn off VITAL compliance checking warnings. Default is to show warnings. -; Show_VitalChecksWarnings = 0 - -; Turn off PSL assertion warning messages. Default is to show warnings. -; Show_PslChecksWarnings = 0 - -; Enable parsing of embedded PSL assertions. Default is enabled. -; EmbeddedPsl = 0 - -; Keep silent about case statement static warnings. -; Default is to give a warning. -; NoCaseStaticError = 1 - -; Keep silent about warnings caused by aggregates that are not locally static. -; Default is to give a warning. -; NoOthersStaticError = 1 - -; Treat as errors: -; case statement static warnings -; warnings caused by aggregates that are not locally static -; Overrides NoCaseStaticError, NoOthersStaticError settings. -; PedanticErrors = 1 - -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn off "Loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on some limited synthesis rule compliance checking. Checks only: -; -- signals used (read) by a process must be in the sensitivity list -; CheckSynthesis = 1 - -; Activate optimizations on expressions that do not involve signals, -; waits, or function/procedure/task invocations. Default is off. -; ScalarOpts = 1 - -; Turns on lint-style checking. -; Show_Lint = 1 - -; Require the user to specify a configuration for all bindings, -; and do not generate a compile time default binding for the -; component. This will result in an elaboration error of -; 'component not bound' if the user fails to do so. Avoids the rare -; issue of a false dependency upon the unused default binding. -; RequireConfigForAllDefaultBinding = 1 - -; Perform default binding at compile time. -; Default is to do default binding at load time. -; BindAtCompile = 1; - -; Inhibit range checking on subscripts of arrays. Range checking on -; scalars defined with subtypes is inhibited by default. -; NoIndexCheck = 1 - -; Inhibit range checks on all (implicit and explicit) assignments to -; scalar objects defined with subtypes. -; NoRangeCheck = 1 - -; Set the prefix to be honored for synthesis/coverage pragma recognition. -; Default is "". -; AddPragmaPrefix = "" - -; Ignore synthesis and coverage pragmas with this prefix. -; Default is "". -; IgnorePragmaPrefix = "" - -; Turn on code coverage in VHDL design units. Default is off. -; Coverage = sbceft - -; Turn off code coverage in VHDL subprograms. Default is on. -; CoverSub = 0 - -; Automatically exclude VHDL case statement OTHERS choice branches. -; This includes OTHERS choices in selected signal assigment statements. -; Default is to not exclude. -; CoverExcludeDefault = 1 - -; Control compiler and VOPT optimizations that are allowed when -; code coverage is on. Refer to the comment for this in the [vlog] area. -; CoverOpt = 3 - -; Turn on or off clkOpt optimization for code coverage. Default is on. -; CoverClkOpt = 1 - -; Turn on or off clkOpt optimization builtins for code coverage. Default is on. -; CoverClkOptBuiltins = 0 - -; Inform code coverage optimizations to respect VHDL 'H' and 'L' -; values on signals in conditions and expressions, and to not automatically -; convert them to '1' and '0'. Default is to not convert. -; CoverRespectHandL = 0 - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable or disable Focused Expression Coverage analysis for conditions and -; expressions. Focused Expression Coverage data is provided by default when -; expression and/or condition coverage is active. -; CoverFEC = 0 - -; Enable or disable UDP Coverage analysis for conditions and expressions. -; UDP Coverage data is disabled by default when expression and/or condition -; coverage is active. -; CoverUDP = 1 - -; Enable or disable Rapid Expression Coverage mode for conditions and expressions. -; Disabling this would convert non-masking conditions in FEC tables to matching -; input patterns. -; CoverREC = 1 - -; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions -; for expression/condition coverage. -; NOTE: Enabling this may have a negative impact on simulation performance. -; CoverExpandReductionPrefix = 0 - -; Enable or disable short circuit evaluation of conditions and expressions when -; condition or expression coverage is active. Short circuit evaluation is enabled -; by default. -; CoverShortCircuit = 0 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Use this directory for compiler temporary files instead of "work/_temp" -; CompilerTempDir = /tmp - -; Set this to cause the compilers to force data to be committed to disk -; when the files are closed. -; SyncCompilerFiles = 1 - -; Add VHDL-AMS declarations to package STANDARD -; Default is not to add -; AmsStandard = 1 - -; Range and length checking will be performed on array indices and discrete -; ranges, and when violations are found within subprograms, errors will be -; reported. Default is to issue warnings for violations, because subprograms -; may not be invoked. -; NoDeferSubpgmCheck = 0 - -; Turn ON detection of FSMs having single bit current state variable. -; FsmSingle = 1 - -; Turn off reset state transitions in FSM. -; FsmResetTrans = 0 - -; Turn ON detection of FSM Implicit Transitions. -; FsmImplicitTrans = 1 - -; Controls whether or not to show immediate assertions with constant expressions -; in GUI/report/UCDB etc. By default, immediate assertions with constant -; expressions are shown in GUI/report/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Controls how VHDL basic identifiers are stored with the design unit. -; Does not make the language case-sensitive, affects only how declarations -; declared with basic identifiers have their names stored and printed -; (in the GUI, examine, etc.). -; Default is to preserve the case as originally depicted in the VHDL source. -; Value of 0 indicates to change all basic identifiers to lower case. -; PreserveCase = 0 - -; For Configuration Declarations, controls the effect that USE clauses have -; on visibility inside the configuration items being configured. If 1 -; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, -; extend the visibility of objects made visible through USE clauses into nested -; component configurations. -; OldVHDLConfigurationVisibility = 0 - -; Allows VHDL configuration declarations to be in a different library from -; the corresponding configured entity. Default is to not allow this for -; stricter LRM-compliance. -; SeparateConfigLibrary = 1; - -; Determine how mode OUT subprogram parameters of type array and record are treated. -; If 0 (the default), then only VHDL 2008 will do this initialization. -; If 1, always initialize the mode OUT parameter to its default value. -; If 2, do not initialize the mode OUT out parameter. -; Note that prior to release 10.1, all language versions did not initialize mode -; OUT array and record type parameters, unless overridden here via this mechanism. -; In release 10.1 and later, only files compiled with VHDL 2008 will cause this -; initialization, unless overridden here. -; InitOutCompositeParam = 0 - -; Generate symbols debugging database in only some special cases to save on -; the number of files in the library. For other design-units, this database is -; generated on-demand in vsim. -; Default is to to generate debugging database for all design-units. -; SmartDbgSym = 1 - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -; Describe compilation options according to matching file patterns. -; File pattern * matches all printing characters other than '/'. -; File pattern **/x matches all paths containing file/directory x. -; File pattern x/** matches all paths beginning at directory x. -; FileOptMap = (**/*.vhd => -2008); - -; Describe library targets of compilation according to matching file patterns. -; LibMap = (**/*.vhd => work); - -[vlog] -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn off "Loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on Verilog hazard checking (order-dependent accessing of global vars). -; Default is off. -; Hazard = 1 - -; Turn on converting regular Verilog identifiers to uppercase. Allows case -; insensitivity for module names. Default is no conversion. -; UpCase = 1 - -; Activate optimizations on expressions that do not involve signals, -; waits, or function/procedure/task invocations. Default is off. -; ScalarOpts = 1 - -; Turns on lint-style checking. -; Show_Lint = 1 - -; Show source line containing error. Default is off. -; Show_source = 1 - -; Turn on bad option warning. Default is off. -; Show_BadOptionWarning = 1 - -; Revert back to IEEE 1364-1995 syntax, default is 0 (off). -; vlog95compat = 1 - -; Turn off PSL warning messages. Default is to show warnings. -; Show_PslChecksWarnings = 0 - -; Enable parsing of embedded PSL assertions. Default is enabled. -; EmbeddedPsl = 0 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Set the threshold for automatically identifying sparse Verilog memories. -; A memory with total size in bytes equal to or more than the sparse memory -; threshold gets marked as sparse automatically, unless specified otherwise -; in source code or by the +nosparse commandline option of vlog or vopt. -; The default is 1M. (i.e. memories with total size equal -; to or greater than 1Mb are marked as sparse) -; SparseMemThreshold = 1048576 - -; Set the prefix to be honored for synthesis and coverage pragma recognition. -; Default is "". -; AddPragmaPrefix = "" - -; Ignore synthesis and coverage pragmas with this prefix. -; Default is "". -; IgnorePragmaPrefix = "" - -; Set the option to treat all files specified in a vlog invocation as a -; single compilation unit. The default value is set to 0 which will treat -; each file as a separate compilation unit as specified in the P1800 draft standard. -; MultiFileCompilationUnit = 1 - -; Turn on code coverage in Verilog design units. Default is off. -; Coverage = sbceft - -; Automatically exclude Verilog case statement default branches. -; Default is to not automatically exclude defaults. -; CoverExcludeDefault = 1 - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Enable Multi Bit Expression Coverage in a Design, If design has expression with -; multi bit operands, this option enables its Expression Coverage. -; The default value is 0. -; CoverFecMultiBit = 1 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable or disable Focused Expression Coverage analysis for conditions and -; expressions. Focused Expression Coverage data is provided by default when -; expression and/or condition coverage is active. -; CoverFEC = 0 - -; Enable or disable UDP Coverage analysis for conditions and expressions. -; UDP Coverage data is disabled by default when expression and/or condition -; coverage is active. -; CoverUDP = 1 - -; Enable or disable Rapid Expression Coverage mode for conditions and expressions. -; Disabling this would convert non-masking conditions in FEC tables to matching -; input patterns. -; CoverREC = 1 - -; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions -; for expression/condition coverage. -; NOTE: Enabling this may have a negative impact on simulation performance. -; CoverExpandReductionPrefix = 0 - -; Enable or disable short circuit evaluation of conditions and expressions when -; condition or expression coverage is active. Short circuit evaluation is enabled -; by default. -; CoverShortCircuit = 0 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Turn on code coverage in VLOG `celldefine modules, modules containing -; specify blocks, and modules included using vlog -v and -y. Default is off. -; CoverCells = 1 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Control compiler and VOPT optimizations that are allowed when -; code coverage is on. This is a number from 0 to 5, with the following -; meanings (the default is 3): -; 5 -- All allowable optimizations are on. -; 4 -- Turn off removing unreferenced code. -; 3 -- Turn off process, always block and if statement merging. -; 2 -- Turn off expression optimization, converting primitives -; to continuous assignments, VHDL subprogram inlining. -; and VHDL clkOpt (converting FF's to builtins). -; 1 -- Turn off continuous assignment optimizations and clock suppression. -; 0 -- Turn off Verilog module inlining and VHDL arch inlining. -; HOWEVER, if fsm coverage is turned on, optimizations will be forced to -; level 3, with also turning off converting primitives to continuous assigns. -; CoverOpt = 3 - -; Specify the override for the default value of "cross_num_print_missing" -; option for the Cross in Covergroups. If not specified then LRM default -; value of 0 (zero) is used. This is a compile time option. -; SVCrossNumPrintMissingDefault = 0 - -; Setting following to 1 would cause creation of variables which -; would represent the value of Coverpoint expressions. This is used -; in conjunction with "SVCoverpointExprVariablePrefix" option -; in the modelsim.ini -; EnableSVCoverpointExprVariable = 0 - -; Specify the override for the prefix used in forming the variable names -; which represent the Coverpoint expressions. This is used in conjunction with -; "EnableSVCoverpointExprVariable" option of the modelsim.ini -; The default prefix is "expr". -; The variable name is -; variable name => _ -; SVCoverpointExprVariablePrefix = expr - -; Override for the default value of the SystemVerilog covergroup, -; coverpoint, and cross option.goal (defined to be 100 in the LRM). -; NOTE: It does not override specific assignments in SystemVerilog -; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" -; in the [vsim] section can override this value. -; SVCovergroupGoalDefault = 100 - -; Override for the default value of the SystemVerilog covergroup, -; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) -; NOTE: It does not override specific assignments in SystemVerilog -; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" -; in the [vsim] section can override this value. -; SVCovergroupTypeGoalDefault = 100 - -; Specify the override for the default value of "strobe" option for the -; Covergroup Type. This is a compile time option which forces "strobe" to -; a user specified default value and supersedes SystemVerilog specified -; default value of '0'(zero). NOTE: This can be overriden by a runtime -; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. -; SVCovergroupStrobeDefault = 0 - -; Specify the override for the default value of "per_instance" option for the -; Covergroup variables. This is a compile time option which forces "per_instance" -; to a user specified default value and supersedes SystemVerilog specified -; default value of '0'(zero). -; SVCovergroupPerInstanceDefault = 0 - -; Specify the override for the default value of "get_inst_coverage" option for the -; Covergroup variables. This is a compile time option which forces -; "get_inst_coverage" to a user specified default value and supersedes -; SystemVerilog specified default value of '0'(zero). -; SVCovergroupGetInstCoverageDefault = 0 - -; -; A space separated list of resource libraries that contain precompiled -; packages. The behavior is identical to using the "-L" switch. -; -; LibrarySearchPath = [ ...] -LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact - -; The behavior is identical to the "-mixedansiports" switch. Default is off. -; MixedAnsiPorts = 1 - -; Enable SystemVerilog 3.1a $typeof() function. Default is off. -; EnableTypeOf = 1 - -; Only allow lower case pragmas. Default is disabled. -; AcceptLowerCasePragmaOnly = 1 - -; Set the maximum depth permitted for a recursive include file nesting. -; IncludeRecursionDepthMax = 5 - -; Turn ON detection of FSMs having single bit current state variable. -; FsmSingle = 1 - -; Turn off reset state transitions in FSM. -; FsmResetTrans = 0 - -; Turn off detections of FSMs having x-assignment. -; FsmXAssign = 0 - -; Turn ON detection of FSM Implicit Transitions. -; FsmImplicitTrans = 1 - -; List of file suffixes which will be read as SystemVerilog. White space -; in extensions can be specified with a back-slash: "\ ". Back-slashes -; can be specified with two consecutive back-slashes: "\\"; -; SvFileSuffixes = sv svp svh - -; This setting is the same as the vlog -sv command line switch. -; Enables SystemVerilog features and keywords when true (1). -; When false (0), the rules of IEEE Std 1364-2005 are followed and -; SystemVerilog keywords are ignored. -; Svlog = 0 - -; Prints attribute placed upon SV packages during package import -; when true (1). The attribute will be ignored when this -; entry is false (0). The attribute name is "mti_design_element_load_message". -; The value of this attribute is a string literal. -; Default is true (1). -; PrintSVPackageLoadingAttribute = 1 - -; Do not show immediate assertions with constant expressions in -; GUI/reports/UCDB etc. By default immediate assertions with constant -; expressions are shown in GUI/reports/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Controls if untyped parameters that are initialized with values greater -; than 2147483647 are mapped to generics of type INTEGER or ignored. -; If mapped to VHDL Integers, values greater than 2147483647 -; are mapped to negative values. -; Default is to map these parameter to generic of type INTEGER -; ForceUnsignedToVHDLInteger = 1 - -; Enable AMS wreal (wired real) extensions. Default is 0. -; WrealType = 1 - -; Controls SystemVerilog Language Extensions. These options enable -; some non-LRM compliant behavior. -; SvExtensions = [+|-][,[+|-]*] - -; Generate symbols debugging database in only some special cases to save on -; the number of files in the library. For other design-units, this database is -; generated on-demand in vsim. -; Default is to to generate debugging database for all design-units. -; SmartDbgSym = 1 - -; Controls how $unit library entries are named. Valid options are: -; "file" (generate name based on the first file on the command line) -; "du" (generate name based on first design unit following an item -; found in $unit scope) -; CUAutoName = file - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -[sccom] -; Enable use of SCV include files and library. Default is off. -; UseScv = 1 - -; Add C++ compiler options to the sccom command line by using this variable. -; CppOptions = -g - -; Use custom C++ compiler located at this path rather than the default path. -; The path should point directly at a compiler executable. -; CppPath = /usr/bin/g++ - -; Specify the compiler version from the list of support GNU compilers. -; examples 4.7.4, 5.3.0, 7.4.0 -; CppInstall = 7.4.0 - -; Enable verbose messages from sccom. Default is off. -; SccomVerbose = 1 - -; sccom logfile. Default is no logfile. -; SccomLogfile = sccom.log - -; Enable use of SC_MS include files and library. Default is off. -; UseScMs = 1 - -; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. -; Sc22Mode = 1 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -; Enable use of UVMC library. Default is off. -; UseUvmc = 1 - -[vopt] -; Turn on code coverage in vopt. Default is off. -; Coverage = sbceft - -; enable or disable param saving in UCDB. -; CoverageSaveParam = 0 - -; Control compiler optimizations that are allowed when -; code coverage is on. Refer to the comment for this in the [vlog] area. -; CoverOpt = 3 - -; Controls set of CoverConstructs that are being considered for Coverage -; Collection. -; Some of Valid options are: default,set1,set2 -; Covermode = default - -; Controls set of HDL cover constructs that would be considered(or not considered) -; for Coverage Collection. (Default corresponds to covermode default). -; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". -; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Enable Multi Bit Expression Coverage in a Design, If design has expression with -; multi bit operands, this option enables its Expression Coverage. -; The default value is 0. -; CoverFecMultiBit = 1 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Do not show immediate assertions with constant expressions in -; GUI/reports/UCDB etc. By default immediate assertions with constant -; expressions are shown in GUI/reports/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Set the maximum number of iterations permitted for a generate loop. -; Restricting this permits the implementation to recognize infinite -; generate loops. -; GenerateLoopIterationMax = 100000 - -; Set the maximum depth permitted for a recursive generate instantiation. -; Restricting this permits the implementation to recognize infinite -; recursions. -; GenerateRecursionDepthMax = 200 - -; Set the number of processes created during the code generation phase. -; By default a heuristic is used to set this value. This may be set to 0 -; to disable this feature completely. -; ParallelJobs = 0 - -; Controls SystemVerilog Language Extensions. These options enable -; some non-LRM compliant behavior. -; SvExtensions = [+|-][,[+|-]*] - -; Load the specified shared objects with the RTLD_GLOBAL flag. -; This gives global visibility to all symbols in the shared objects, -; meaning that subsequently loaded shared objects can bind to symbols -; in the global shared objects. The list of shared objects should -; be whitespace delimited. This option is not supported on the -; Windows or AIX platforms. -; GlobalSharedObjectList = example1.so example2.so example3.so - -; Disable SystemVerilog elaboration system task messages -; IgnoreSVAInfo = 1 -; IgnoreSVAWarning = 1 -; IgnoreSVAError = 1 -; IgnoreSVAFatal = 1 - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -[vsim] -; vopt flow -; Set to turn on automatic optimization of a design. -; Default is on -VoptFlow = 1 - -; Simulator resolution -; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. -Resolution = fs - -; Disable certain code coverage exclusions automatically. -; Assertions and FSM are exluded from the code coverage by default -; Set AutoExclusionsDisable = fsm to enable code coverage for fsm -; Set AutoExclusionsDisable = assertions to enable code coverage for assertions -; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions -; Or specify comma or space separated list -;AutoExclusionsDisable = fsm,assertions - -; User time unit for run commands -; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the -; unit specified for Resolution. For example, if Resolution is 100ps, -; then UserTimeUnit defaults to ps. -; Should generally be set to default. -UserTimeUnit = default - -; Default run length -RunLength = 100 - -; Maximum iterations that can be run without advancing simulation time -IterationLimit = 10000000 - -; Specify libraries to be searched for precompiled modules -; LibrarySearchPath = [ ...] - -; Set XPROP assertion fail limit. Default is 5. -; Any positive integer, -1 for infinity. -; XpropAssertionLimit = 5 - -; Control PSL and Verilog Assume directives during simulation -; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts -; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts -; SimulateAssumeDirectives = 1 - -; Control the simulation of PSL and SVA -; These switches can be overridden by the vsim command line switches: -; -psl, -nopsl, -sva, -nosva. -; Set SimulatePSL = 0 to disable PSL simulation -; Set SimulatePSL = 1 to enable PSL simulation (default) -; SimulatePSL = 1 -; Set SimulateSVA = 0 to disable SVA simulation -; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) -; SimulateSVA = 1 - -; Control SVA and VHDL immediate assertion directives during simulation -; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts -; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts -; SimulateImmedAsserts = 1 - -; License feature mappings for Verilog and VHDL -; qhsimvh Single language VHDL license -; qhsimvl Single language Verilog license -; msimhdlsim Language neutral license for either Verilog or VHDL -; msimhdlmix Second language only, language neutral license for either -; Verilog or VHDL -; -; Directives to license manager can be set either as single value or as -; space separated multi-values: -; vhdl Immediately checkout and hold a VHDL license (i.e., one of -; qhsimvh, msimhdlsim, or msimhdlmix) -; vlog Immediately checkout and hold a Verilog license (i.e., one of -; qhsimvl, msimhdlsim, or msimhdlmix) -; plus Immediately checkout and hold a VHDL license and a Verilog license -; noqueue Do not wait in the license queue when a license is not available -; viewsim Try for viewer license but accept simulator license(s) instead -; of queuing for viewer license (PE ONLY) -; noviewer Disable checkout of msimviewer license feature (PE ONLY) -; noslvhdl Disable checkout of qhsimvh license feature -; noslvlog Disable checkout of qhsimvl license feature -; nomix Disable checkout of msimhdlmix license feature -; nolnl Disable checkout of msimhdlsim license feature -; mixedonly Disable checkout of qhsimvh and qhsimvl license features -; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features -; -; Examples (remove ";" comment character to activate licensing directives): -; Single directive: -; License = plus -; Multi-directive (Note: space delimited directives): -; License = noqueue plus - -; Severity level of a VHDL assertion message or of a SystemVerilog severity system task -; which will cause a running simulation to stop. -; VHDL assertions and SystemVerilog severity system task that occur with the -; given severity or higher will cause a running simulation to stop. -; This value is ignored during elaboration. -; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal -BreakOnAssertion = 3 - -; Severity level of a tool message which will cause a running simulation to -; stop. This value is ignored during elaboration. Default is to not break. -; 0 = Note 1 = Warning 2 = Error 3 = Fatal -;BreakOnMessage = 2 - -; The class debug feature enables more visibility and tracking of class instances -; during simulation. By default this feature is disabled (0). To enable this -; feature set ClassDebug to 1. -; ClassDebug = 1 - -; Message Format conversion specifications: -; %S - Severity Level of message/assertion -; %R - Text of message -; %T - Time of message -; %D - Delta value (iteration number) of Time -; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected -; %i - Instance/Region/Signal pathname with Process name (if available) -; %I - shorthand for one of these: -; " %K: %i" -; " %K: %i File: %F" (when path is not Process or Signal) -; except that the %i in this case does not report the Process name -; %O - Process name -; %P - Instance/Region path without leaf process -; %F - File name -; %L - Line number; if assertion message, then line number of assertion or, if -; assertion is in a subprogram, line from which the call is made -; %u - Design unit name in form library.primary -; %U - Design unit name in form library.primary(secondary) -; %% - The '%' character itself -; -; If specific format for Severity Level is defined, use that format. -; Else, for a message that occurs during elaboration: -; -- Failure/Fatal message in VHDL region that is not a Process, and in -; certain non-VHDL regions, uses MessageFormatBreakLine; -; -- Failure/Fatal message otherwise uses MessageFormatBreak; -; -- Note/Warning/Error message uses MessageFormat. -; Else, for a message that occurs during runtime and triggers a breakpoint because -; of the BreakOnAssertion setting: -; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; -; -- otherwise uses MessageFormatBreak. -; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. -; -; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" -; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" -; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" -; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" - -; Error File - alternate file for storing error messages -; ErrorFile = error.log - -; Simulation Breakpoint messages -; This flag controls the display of function names when reporting the location -; where the simulator stops because of a breakpoint or fatal error. -; Example with function name: # Break in Process ctr at counter.vhd line 44 -; Example without function name: # Break at counter.vhd line 44 -; Default value is 1. -ShowFunctions = 1 - -; Default radix for all windows and commands. -; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned -; Flags may be one of: enumnumeric, showbase, wreal -DefaultRadix = hexadecimal -DefaultRadixFlags = showbase -; Set to 1 for make the signal_force VHDL and Verilog functions use the -; default radix when processing the force value. Prior to 10.2 signal_force -; used the default radix, now it always uses symbolic unless value explicitly indicates base -;SignalForceFunctionUseDefaultRadix = 0 - -; VSIM Startup command -; Startup = do startup.do - -; VSIM Shutdown file -; Filename to save u/i formats and configurations. -; ShutdownFile = restart.do -; To explicitly disable auto save: -; ShutdownFile = --disable-auto-save - -; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. -; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. -; BatchMode = 1 - -; File for saving command transcript when -batch option used -; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero -; default is unset so command transcript only goes to stdout for better performance -; BatchTranscriptFile = transcript - -; File for saving command transcript, this option is ignored when -batch option is used -TranscriptFile = transcript - -; Transcript file long line wrapping mode(s) -; mode == 0 :: no wrapping, line recorded as is -; mode == 1 :: wrap at first whitespace after WSColumn -; or at Column. -; mode == 2 :: wrap as above, but add continuation -; character ('\') at end of each wrapped line -; -; WrapMode = 0 -; WrapColumn = 30000 -; WrapWSColumn = 27000 - -; File for saving command history -; CommandHistory = cmdhist.log - -; Specify whether paths in simulator commands should be described -; in VHDL or Verilog format. -; For VHDL, PathSeparator = / -; For Verilog, PathSeparator = . -; Must not be the same character as DatasetSeparator. -PathSeparator = / - -; Specify the dataset separator for fully rooted contexts. -; The default is ':'. For example: sim:/top -; Must not be the same character as PathSeparator. -DatasetSeparator = : - -; Specify a unique path separator for the Signal Spy set of functions. -; The default will be to use the PathSeparator variable. -; Must not be the same character as DatasetSeparator. -; SignalSpyPathSeparator = / - -; Used to control parsing of HDL identifiers input to the tool. -; This includes CLI commands, vsim/vopt/vlog/vcom options, -; string arguments to FLI/VPI/DPI calls, etc. -; If set to 1, accept either Verilog escaped Id syntax or -; VHDL extended id syntax, regardless of source language. -; If set to 0, the syntax of the source language must be used. -; Each identifier in a hierarchical name may need different syntax, -; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or -; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" -; GenerousIdentifierParsing = 1 - -; Disable VHDL assertion messages -; IgnoreNote = 1 -; IgnoreWarning = 1 -; IgnoreError = 1 -; IgnoreFailure = 1 - -; Disable SystemVerilog assertion messages -; IgnoreSVAInfo = 1 -; IgnoreSVAWarning = 1 -; IgnoreSVAError = 1 -; IgnoreSVAFatal = 1 - -; Do not print any additional information from Severity System tasks. -; Only the message provided by the user is printed along with severity -; information. -; SVAPrintOnlyUserMessage = 1; - -; Default force kind. May be freeze, drive, deposit, or default -; or in other terms, fixed, wired, or charged. -; A value of "default" will use the signal kind to determine the -; force kind, drive for resolved signals, freeze for unresolved signals -; DefaultForceKind = freeze - -; Control the iteration of events when a VHDL signal is forced to a value -; This flag can be set to honour the signal update event in next iteration, -; the default is to update and propagate in the same iteration. -; ForceSigNextIter = 1 - -; Enable simulation statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; If zero, open files when elaborated; otherwise, open files on -; first read or write. Default is 0. -; DelayFileOpen = 1 - -; Control VHDL files opened for write. -; 0 = Buffered, 1 = Unbuffered -UnbufferedOutput = 0 - -; Control the number of VHDL files open concurrently. -; This number should always be less than the current ulimit -; setting for max file descriptors. -; 0 = unlimited -ConcurrentFileLimit = 40 - -; If nonzero, close files as soon as there is either an explicit call to -; file_close, or when the file variable's scope is closed. When zero, a -; file opened in append mode is not closed in case it is immediately -; reopened in append mode; otherwise, the file will be closed at the -; point it is reopened. -; AppendClose = 1 - -; Control the number of hierarchical regions displayed as -; part of a signal name shown in the Wave window. -; A value of zero tells VSIM to display the full name. -; The default is 0. -; WaveSignalNameWidth = 0 - -; Turn off warnings when changing VHDL constants and generics -; Default is 1 to generate warning messages -; WarnConstantChange = 0 - -; Turn off warnings from accelerated versions of the std_logic_arith, -; std_logic_unsigned, and std_logic_signed packages. -; StdArithNoWarnings = 1 - -; Turn off warnings from accelerated versions of the IEEE numeric_std -; and numeric_bit packages. -; NumericStdNoWarnings = 1 - -; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names -; in the design hierarchy. -; This style is controlled by the value of the GenerateFormat -; value described next. Default is to use new-style names, which -; comprise the generate statement label, '(', the value of the generate -; parameter, and a closing ')'. -; Set this to 1 to use old-style names. -; OldVhdlForGenNames = 1 - -; Control the format of the old-style VHDL FOR generate statement region -; name for each iteration. Do not quote the value. -; The format string here must contain the conversion codes %s and %d, -; in that order, and no other conversion codes. The %s represents -; the generate statement label; the %d represents the generate parameter value -; at a particular iteration (this is the position number if the generate parameter -; is of an enumeration type). Embedded whitespace is allowed (but discouraged); -; leading and trailing whitespace is ignored. -; Application of the format must result in a unique region name over all -; loop iterations for a particular immediately enclosing scope so that name -; lookup can function properly. The default is %s__%d. -; GenerateFormat = %s__%d - -; Enable more efficient logging of VHDL Variables. -; Logging VHDL variables without this enabled, while possible, is very -; inefficient. Enabling this will provide a more efficient logging methodology -; at the expense of more memory usage. By default this feature is disabled (0). -; To enabled this feature, set this variable to 1. -; VhdlVariableLogging = 1 - -; Enable logging of VHDL access type variables and their designated objects. -; This setting will allow both variables of an access type ("access variables") -; and their designated objects ("access objects") to be logged. Logging a -; variable of an access type will automatically also cause the designated -; object(s) of that variable to be logged as the simulation progresses. -; Further, enabling this allows access objects to be logged by name. By default -; this feature is disabled (0). To enable this feature, set this variable to 1. -; Enabling this will automatically enable the VhdlVariableLogging feature also. -; AccessObjDebug = 1 - -; Make each VHDL package in a PDU has its own separate copy of the package instead -; of sharing the package between PDUs. The default is to share packages. -; To ensure that each PDU has its own set of packages, set this variable to 1. -; VhdlSeparatePduPackage = 1 - -; Specify whether checkpoint files should be compressed. -; The default is 1 (compressed). -; CheckpointCompressMode = 0 - -; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. -; Use custom gcc compiler located at this path rather than the default path. -; The path should point directly at a compiler executable. -; DpiCppPath = /bin/gcc -; -; Specify the compiler version from the list of support GNU compilers. -; examples 4.7.4, 5.3.0, 7.4.0 -; DpiCppInstall = 7.4.0 - -; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. -; The term "out-of-the-blue" refers to SystemVerilog export function calls -; made from C functions that don't have the proper context setup -; (as is the case when running under "DPI-C" import functions). -; When this is enabled, one can call a DPI export function -; (but not task) from any C code. -; the setting of this variable can be one of the following values: -; 0 : dpioutoftheblue call is disabled (default) -; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. -; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. -; DpiOutOfTheBlue = 1 - -; Specify whether continuous assignments are run before other normal priority -; processes scheduled in the same iteration. This event ordering minimizes race -; differences between optimized and non-optimized designs, and is the default -; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set -; ImmediateContinuousAssign to 0. -; The default is 1 (enabled). -; ImmediateContinuousAssign = 0 - -; List of dynamically loaded objects for Verilog PLI applications -; Veriuser = veriuser.sl - -; Which default VPI object model should the tool conform to? -; The 1364 modes are Verilog-only, for backwards compatibility with older -; libraries, and SystemVerilog objects are not available in these modes. -; -; In the absence of a user-specified default, the tool default is the -; latest available LRM behavior. -; Options for PliCompatDefault are: -; VPI_COMPATIBILITY_VERSION_1364v1995 -; VPI_COMPATIBILITY_VERSION_1364v2001 -; VPI_COMPATIBILITY_VERSION_1364v2005 -; VPI_COMPATIBILITY_VERSION_1800v2005 -; VPI_COMPATIBILITY_VERSION_1800v2008 -; -; Synonyms for each string are also recognized: -; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) -; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) -; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) -; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) -; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) - - -; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 - -; Specify whether the Verilog system task $fopen or vpi_mcd_open() -; will create directories that do not exist when opening the file -; in "a" or "w" mode. -; The default is 0 (do not create non-existent directories) -; CreateDirForFileAccess = 1 - -; Specify default options for the restart command. Options can be one -; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions -; DefaultRestartOptions = -force - - -; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. -; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. -; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". -; The list of options must be delimited by commas, without spaces or tabs. -; -; Some examples -; To turn on all available UVM-aware debug features: -; UVMControl = all -; To turn on the struct window, mesage logging, and transaction logging: -; UVMControl = struct,msglog,trlog -; To turn on all options except certe: -; UVMControl = all,-certe -; To completely disable all UVM-aware debug functionality: -; UVMControl = disable - -; Specify the WildcardFilter setting. -; A space separated list of object types to be excluded when performing -; wildcard matches with log, wave, etc commands. The default value for this variable is: -; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" -; See "Using the WildcardFilter Preference Variable" in the documentation for -; details on how to use this variable and for descriptions of the filter types. -WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile - -; Specify the WildcardSizeThreshold setting. -; This integer setting specifies the size at which objects will be excluded when -; performing wildcard matches with log, wave, etc commands. Objects of size equal -; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard -; matches. The size is a simple calculation of number of bits or items in the object. -; The default value is 8k (8192). Setting this value to 0 will disable the checking -; of object size against this threshold and allow all objects of any size to be logged. -WildcardSizeThreshold = 8192 - -; Specify whether warning messages are output when objects are filtered out due to the -; WildcardSizeThreshold. The default is 0 (no messages generated). -WildcardSizeThresholdVerbose = 0 - -; Turn on (1) or off (0) WLF file compression. -; The default is 1 (compress WLF file). -; WLFCompress = 0 - -; Specify whether to save all design hierarchy (1) in the WLF file -; or only regions containing logged signals (0). -; The default is 0 (save only regions with logged signals). -; WLFSaveAllRegions = 1 - -; WLF file time limit. Limit WLF file by time, as closely as possible, -; to the specified amount of simulation time. When the limit is exceeded -; the earliest times get truncated from the file. -; If both time and size limits are specified the most restrictive is used. -; UserTimeUnits are used if time units are not specified. -; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} -; WLFTimeLimit = 0 - -; WLF file size limit. Limit WLF file size, as closely as possible, -; to the specified number of megabytes. If both time and size limits -; are specified then the most restrictive is used. -; The default is 0 (no limit). -; WLFSizeLimit = 1000 - -; Specify whether or not a WLF file should be deleted when the -; simulation ends. A value of 1 will cause the WLF file to be deleted. -; The default is 0 (do not delete WLF file when simulation ends). -; WLFDeleteOnQuit = 1 - -; Specify whether or not a WLF file should be optimized during -; simulation. If set to 0, the WLF file will not be optimized. -; The default is 1, optimize the WLF file. -; WLFOptimize = 0 - -; Specify the name of the WLF file. -; The default is vsim.wlf -; WLFFilename = vsim.wlf - -; Specify whether to lock the WLF file. -; Locking the file prevents other invocations of ModelSim/Questa tools from -; inadvertently overwriting the WLF file. -; The default is 1, lock the WLF file. -; WLFFileLock = 0 - -; Specify the update interval for the WLF file in live simulation. -; The interval is given in seconds. -; The value is the smallest interval between WLF file updates. The WLF file -; will be flushed (updated) after (at least) the interval has elapsed, ensuring -; that the data is correct when viewed from a separate viewer. -; A value of 0 means that no updating will occur. -; The default value is 10 seconds. -; WLFUpdateInterval = 10 - -; Specify the WLF cache size limit for WLF files. -; The value is given in megabytes. A value of 0 turns off the cache. -; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). -; On Windows, the default value is 1000 (megabytes) to help to avoid filling -; process memory. -; WLFSimCacheSize allows a different cache size to be set for a live simulation -; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize -; is not set, it defaults to the WLFCacheSize value. -; WLFCacheSize = 2000 -; WLFSimCacheSize = 500 - -; Specify the WLF file event collapse mode. -; 0 = Preserve all events and event order. (same as -wlfnocollapse) -; 1 = Only record values of logged objects at the end of a simulator iteration. -; (same as -wlfcollapsedelta) -; 2 = Only record values of logged objects at the end of a simulator time step. -; (same as -wlfcollapsetime) -; The default is 1. -; WLFCollapseMode = 0 - -; Specify whether WLF file logging can use threads on multi-processor machines. -; If 0, no threads will be used; if 1, threads will be used if the system has -; more than one processor. -; WLFUseThreads = 1 - -; Specify the size of objects that will trigger "large object" messages -; at log/wave/list time. The size calculation of the object is the same as that -; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. -; Setting LargeObjectSize to 0 will disable these messages. -; LargeObjectSize = 500000 - -; Specify the depth of stack frames returned by $stacktrace([level]). -; This depth will be picked up when the optional 'level' argument -; is not specified or its value is not a positive integer. -; StackTraceDepth = 100 - -; Turn on/off undebuggable SystemC type warnings. Default is on. -; ShowUndebuggableScTypeWarning = 0 - -; Turn on/off unassociated SystemC name warnings. Default is off. -; ShowUnassociatedScNameWarning = 1 - -; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. -; ScShowIeeeDeprecationWarnings = 1 - -; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. -; For SystemC-2.3.2 the valid values are 0,1 and 2 -; 0 = SC_SIGNAL_WRITE_CHECK_DISABLE_ -; 1 = SC_SIGNAL_WRITE_CHECK_DEFAULT_ -; 2 = SC_SIGNAL_WRITE_CHECK_CONFLICT_ -; For SystemC-2.2 the valid values are 0 and 1 -; 0 = DISABLE -; 1 = ENABLE -; ScEnableScSignalWriteCheck = 1 - -; Set SystemC default time unit. -; Set to fs, ps, ns, us, ms, or sec with optional -; prefix of 1, 10, or 100. The default is 1 ns. -; The ScTimeUnit value is honored if it is coarser than Resolution. -; If ScTimeUnit is finer than Resolution, it is set to the value -; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, -; then the default time unit will be 1 ns. However if Resolution -; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. -ScTimeUnit = ns - -; Set SystemC sc_main stack size. The stack size is set as an integer -; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or -; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends -; on the amount of data on the sc_main() stack and the memory required -; to succesfully execute the longest function call chain of sc_main(). -ScMainStackSize = 10 Mb - -; Set SystemC thread stack size. The stack size is set as an integer -; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or -; Gb(Giga-byte). The stack size for sc_thread depends -; on the amount of data on the sc_thread stack and the memory required -; to succesfully execute the thread. -; ScStackSize = 1 Mb - -; Turn on/off execution of remainder of sc_main upon quitting the current -; simulation session. If the cumulative length of sc_main() in terms of -; simulation time units is less than the length of the current simulation -; run upon quit or restart, sc_main() will be in the middle of execution. -; This switch gives the option to execute the remainder of sc_main upon -; quitting simulation. The drawback of not running sc_main till the end -; is memory leaks for objects created by sc_main. If on, the remainder of -; sc_main will be executed ignoring all delays. This may cause the simulator -; to crash if the code in sc_main is dependent on some simulation state. -; Default is on. -ScMainFinishOnQuit = 1 - -; Enable calling of the DPI export taks/functions from the -; SystemC start_of_simulation() callback. -; The default is off. -; EnableDpiSosCb = 1 - - -; Set the SCV relationship name that will be used to identify phase -; relations. If the name given to a transactor relation matches this -; name, the transactions involved will be treated as phase transactions -ScvPhaseRelationName = mti_phase - -; Customize the vsim kernel shutdown behavior at the end of the simulation. -; Some common causes of the end of simulation are $finish (implicit or explicit), -; sc_stop(), tf_dofinish(), and assertion failures. -; This should be set to "ask", "exit", or "stop". The default is "ask". -; "ask" -- In batch mode, the vsim kernel will abruptly exit. -; In GUI mode, a dialog box will pop up and ask for user confirmation -; whether or not to quit the simulation. -; "stop" -- Cause the simulation to stay loaded in memory. This can make some -; post-simulation tasks easier. -; "exit" -- The simulation will abruptly exit without asking for any confirmation. -; "final" -- Run SystemVerilog final blocks then behave as "stop". -; Note: This variable can be overridden with the vsim "-onfinish" command line switch. -OnFinish = ask - -; Print pending deferred assertion messages. -; Deferred assertion messages may be scheduled after the $finish in the same -; time step. Deferred assertions scheduled to print after the $finish are -; printed before exiting with severity level NOTE since it's not known whether -; the assertion is still valid due to being printed in the active region -; instead of the reactive region where they are normally printed. -; OnFinishPendingAssert = 1; - -; Print "simstats" result. Default is 0. -; 0 == do not print simstats -; 1 == print at end of simulation -; 2 == print at end of each run command and end of simulation -; PrintSimStats = 1 - -; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages -; AssertFile = assert.log - -; Enable assertion counts. Default is off. -; AssertionCounts = 1 - -; Run simulator in assertion debug mode. Default is off. -; AssertionDebug = 1 - -; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. -; AssertionEnable = 0 - -; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. -; Any positive integer, -1 for infinity. -; AssertionLimit = 1 - -; Turn on/off concurrent assertion pass log. Default is off. -; Assertion pass logging is only enabled when assertion is browseable -; and assertion debug is enabled. -; AssertionPassLog = 1 - -; Turn on/off PSL concurrent assertion fail log. Default is on. -; The flag does not affect SVA -; AssertionFailLog = 0 - -; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. -; AssertionFailLocalVarLog = 0 - -; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. -; 0 = Continue 1 = Break 2 = Exit -; AssertionFailAction = 1 - -; Enable the active thread monitor in the waveform display when assertion debug is enabled. -; AssertionActiveThreadMonitor = 1 - -; Control how many waveform rows will be used for displaying the active threads. Default is 5. -; AssertionActiveThreadMonitorLimit = 5 - -; Assertion thread limit after which assertion would be killed/switched off. -; The default is -1 (unlimited). If the number of threads for an assertion go -; beyond this limit, the assertion would be either switched off or killed. This -; limit applies to only assert directives. -;AssertionThreadLimit = -1 - -; Action to be taken once the assertion thread limit is reached. Default -; is kill. It can have a value of off or kill. In case of kill, all the existing -; threads are terminated and no new attempts are started. In case of off, the -; existing attempts keep on evaluating but no new attempts are started. This -; variable applies to only assert directives. -;AssertionThreadLimitAction = kill - -; Cover thread limit after which cover would be killed/switched off. -; The default is -1 (unlimited). If the number of threads for a cover go -; beyond this limit, the cover would be either switched off or killed. This -; limit applies to only cover directives. -;CoverThreadLimit = -1 - -; Action to be taken once the cover thread limit is reached. Default -; is kill. It can have a value of off or kill. In case of kill, all the existing -; threads are terminated and no new attempts are started. In case of off, the -; existing attempts keep on evaluating but no new attempts are started. This -; variable applies to only cover directives. -;CoverThreadLimitAction = kill - - -; By default immediate assertions do not participate in Assertion Coverage calculations -; unless they are executed. This switch causes all immediate assertions in the design -; to participate in Assertion Coverage calculations, whether attempted or not. -; UnattemptedImmediateAssertions = 0 - -; By default immediate covers participate in Coverage calculations -; whether they are attempted or not. This switch causes all unattempted -; immediate covers in the design to stop participating in Coverage -; calculations. -; UnattemptedImmediateCovers = 0 - -; By default pass action block is not executed for assertions on vacuous -; success. The following variable is provided to enable execution of -; pass action block on vacuous success. The following variable is only effective -; if the user does not disable pass action block execution by using either -; system tasks or CLI. Also there is a performance penalty for enabling -; the following variable. -;AssertionEnableVacuousPassActionBlock = 1 - -; As per strict 1850-2005 PSL LRM, an always property can either pass -; or fail. However, by default, Questa reports multiple passes and -; multiple fails on top always/never property (always/never operator -; is the top operator under Verification Directive). The reason -; being that Questa reports passes and fails on per attempt of the -; top always/never property. Use the following flag to instruct -; Questa to strictly follow LRM. With this flag, all assert/never -; directives will start an attempt once at start of simulation. -; The attempt can either fail, match or match vacuously. -; For e.g. if always is the top operator under assert, the always will -; keep on checking the property at every clock. If the property under -; always fails, the directive will be considered failed and no more -; checking will be done for that directive. A top always property, -; if it does not fail, will show a pass at end of simulation. -; The default value is '0' (i.e. zero is off). For example: -; PslOneAttempt = 1 - -; Specify the number of clock ticks to represent infinite clock ticks. -; This affects eventually!, until! and until_!. If at End of Simulation -; (EOS) an active strong-property has not clocked this number of -; clock ticks then neither pass or fail (vacuous match) is returned -; else respective fail/pass is returned. The default value is '0' (zero) -; which effectively does not check for clock tick condition. For example: -; PslInfinityThreshold = 5000 - -; Control how many thread start times will be preserved for ATV viewing for a given assertion -; instance. Default is -1 (ALL). -; ATVStartTimeKeepCount = -1 - -; Turn on/off code coverage -; CodeCoverage = 0 - -; This option applies to condition and expression coverage UDP tables. It -; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. -; If this option is used and a match occurs in more than one row in the UDP table, -; none of the counts for all matching rows is incremented. By default, counts are -; incremented for all matching rows. -; CoverCountAll = 1 - -; Turn off automatic inclusion of VHDL integers in toggle coverage. Default -; is to include them. -; ToggleNoIntegers = 1 - -; Set the maximum number of values that are collected for toggle coverage of -; VHDL integers. Default is 100; -; ToggleMaxIntValues = 100 - -; Set the maximum number of values that are collected for toggle coverage of -; Verilog real. Default is 100; -; ToggleMaxRealValues = 100 - -; Turn on automatic inclusion of Verilog integers in toggle coverage, except -; for enumeration types. Default is to include them. -; ToggleVlogIntegers = 0 - -; Turn on automatic inclusion of Verilog real type in toggle coverage, except -; for shortreal types. Default is to not include them. -; ToggleVlogReal = 1 - -; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays -; and VHDL arrays-of-arrays in toggle coverage. -; Default is to not include them. -; ToggleFixedSizeArray = 1 - -; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, -; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. -; This leads to a longer simulation time with bigger arrays covered with toggle coverage. -; Default is 1024. -; ToggleMaxFixedSizeArray = 1024 - -; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized -; one-dimensional packed vectors for toggle coverage. Default is 0. -; TogglePackedAsVec = 0 - -; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for -; toggle coverage. Default is 0. -; ToggleVlogEnumBits = 0 - -; Turn off automatic inclusion of VHDL records in toggle coverage. -; Default is to include them. -; ToggleVHDLRecords = 0 - -; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. -; For unlimited width, set to 0. -; ToggleWidthLimit = 128 - -; Limit the counts that are tracked for toggle coverage. When all edges for a bit have -; reached this count, further activity on the bit is ignored. Default is 1. -; For unlimited counts, set to 0. -; ToggleCountLimit = 1 - -; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. -; Following is the toggle coverage calculation criteria based on extended toggle mode: -; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). -; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. -; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. -; ExtendedToggleMode = 3 - -; Enable toggle statistics collection only for ports. Default is 0. -; TogglePortsOnly = 1 - -; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has -; reached this count, further tracking of the input patterns linked to it is ignored. -; Default is 1. For unlimited counts, set to 0. -; NOTE: Changing this value from its default value may affect simulation performance. -; FecCountLimit = 1 - -; Limit the counts that are tracked for UDP Coverage. When a bin has -; reached this count, further tracking of the input patterns linked to it is ignored. -; Default is 1. For unlimited counts, set to 0. -; NOTE: Changing this value from its default value may affect simulation performance. -; UdpCountLimit = 1 - -; Control toggle coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either -; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; ToggleDeglitchPeriod = 10.0ps - -; Turn on/off all PSL/SVA cover directive enables. Default is on. -; CoverEnable = 0 - -; Turn on/off PSL/SVA cover log. Default is off "0". -; CoverLog = 1 - -; Set "at_least" value for all PSL/SVA cover directives. Default is 1. -; CoverAtLeast = 2 - -; Set "limit" value for all PSL/SVA cover directives. Default is -1. -; Any positive integer, -1 for infinity. -; CoverLimit = 1 - -; Specify the coverage database filename. -; Default is "" (i.e. database is NOT automatically saved on close). -; UCDBFilename = vsim.ucdb - -; Specify the maximum limit for the number of Cross (bin) products reported -; in XML and UCDB report against a Cross. A warning is issued if the limit -; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this -; setting. -; MaxReportRhsSVCrossProducts = 1000 - -; Specify the override for the "auto_bin_max" option for the Covergroups. -; If not specified then value from Covergroup "option" is used. -; SVCoverpointAutoBinMax = 64 - -; Specify the override for the value of "cross_num_print_missing" -; option for the Cross in Covergroups. If not specified then value -; specified in the "option.cross_num_print_missing" is used. This -; is a runtime option. NOTE: This overrides any "cross_num_print_missing" -; value specified by user in source file and any SVCrossNumPrintMissingDefault -; specified in modelsim.ini. -; SVCrossNumPrintMissing = 0 - -; Specify whether to use the value of "cross_num_print_missing" -; option in report and GUI for the Cross in Covergroups. If not specified then -; cross_num_print_missing is ignored for creating reports and displaying -; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". -; UseSVCrossNumPrintMissing = 0 - -; Specify the threshold of Coverpoint wildcard bin value range size, above which -; a warning will be triggered. The default is 4K -- 12 wildcard bits. -; SVCoverpointWildCardBinValueSizeWarn = 4096 - -; Specify the override for the value of "strobe" option for the -; Covergroup Type. If not specified then value in "type_option.strobe" -; will be used. This is runtime option which forces "strobe" to -; user specified value and supersedes user specified values in the -; SystemVerilog Code. NOTE: This also overrides the compile time -; default value override specified using "SVCovergroupStrobeDefault" -; SVCovergroupStrobe = 0 - -; Override for explicit assignments in source code to "option.goal" of -; SystemVerilog covergroup, coverpoint, and cross. It also overrides the -; default value of "option.goal" (defined to be 100 in the SystemVerilog -; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". -; SVCovergroupGoal = 100 - -; Override for explicit assignments in source code to "type_option.goal" of -; SystemVerilog covergroup, coverpoint, and cross. It also overrides the -; default value of "type_option.goal" (defined to be 100 in the SystemVerilog -; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". -; SVCovergroupTypeGoal = 100 - -; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() -; builtin functions, and report. This setting changes the default values of -; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 -; behavior if explicit assignments are not made on option.get_inst_coverage and -; type_option.merge_instances by the user. There are two vsim command line -; options, -cvg63 and -nocvg63 to override this setting from vsim command line. -; The default value of this variable from release 6.6 onwards is 0. This default -; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. -; SVCovergroup63Compatibility = 0 - -; Enforce the default behavior of covergroup get_coverage() builtin function, GUI -; and report. This variable sets the default value of type_option.merge_instances. -; There are two vsim command line options, -cvgmergeinstances and -; -nocvgmergeinstances to override this setting from vsim command line. -; The default value of this variable, -1 (don't care), allows the tool to determine -; the effective value, based on factors related to capacity and optimization. -; The type_option.merge_instances appears in the GUI and coverage reports as either -; auto(1) or auto(0), depending on whether the effective value was determined to -; be a 1 or a 0. -; SVCovergroupMergeInstancesDefault = -1 - -; Enable or disable generation of more detailed information about the sampling -; of covergroup, cross, and coverpoints. It provides the details of the number -; of times the covergroup instance and type were sampled, as well as details -; about why covergroup, cross and coverpoint were not covered. A non-zero value -; is to enable this feature. 0 is to disable this feature. Default is 0 -; SVCovergroupSampleInfo = 0 - -; Specify the maximum number of Coverpoint bins in whole design for -; all Covergroups. -; MaxSVCoverpointBinsDesign = 2147483648 - -; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins -; MaxSVCoverpointBinsInst = 1048576 - -; Specify the maximum number of Cross bins in whole design for -; all Covergroups. -; MaxSVCrossBinsDesign = 2147483648 - -; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins -; MaxSVCrossBinsInst = 67108864 - -; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. -; By default, this variable is set 0, in which case option.no_collect setting will take effect. -; If this variable is set to 1, all zero-weight coverage items will not be saved. -; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting -; of this variable. -; CvgZWNoCollect = 1 - -; Specify a space delimited list of double quoted TCL style -; regular expressions which will be matched against the text of all messages. -; If any regular expression is found to be contained within any message, the -; status for that message will not be propagated to the UCDB TESTSTATUS. -; If no match is detected, then the status will be propagated to the -; UCDB TESTSTATUS. More than one such regular expression text is allowed, -; and each message text is compared for each regular expression in the list. -; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" - -; Set weight for all PSL/SVA cover directives. Default is 1. -; CoverWeight = 2 - -; Check vsim plusargs. Default is 0 (off). -; 0 = Don't check plusargs -; 1 = Warning on unrecognized plusarg -; 2 = Error and exit on unrecognized plusarg -; CheckPlusargs = 1 - -; Load the specified shared objects with the RTLD_GLOBAL flag. -; This gives global visibility to all symbols in the shared objects, -; meaning that subsequently loaded shared objects can bind to symbols -; in the global shared objects. The list of shared objects should -; be whitespace delimited. This option is not supported on the -; Windows or AIX platforms. -; GlobalSharedObjectList = example1.so example2.so example3.so - -; Generate the stub definitions for the undefined symbols in the shared libraries being -; loaded in the simulation. When this flow is turned on, the undefined symbols will not -; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. -; The valid arguments are: on, off, verbose. -; on : turn on the automatic generation of stub definitions. -; off: turn off the flow. The undefined symbols will trigger an immediate load failure. -; verbose: Turn on the flow and report the undefined symbols for each shared library. -; NOTE: This variable can be overriden with vsim switch "-undefsyms". -; The default is on. -; -; UndefSyms = off - -; Enable the support for checkpointing foreign C/C++ libraries. -; The valid arguments are: 0, 1, 2 -; 0: off (default) -; 1: on (manually save/restore user shared library data) -; 2: auto (automatically save/restore user shared library data) -; This option is not supported on the Windows platforms. -; -; AllowCheckpointCpp = 2 - -; Initial seed for the random number generator of the root thread (SystemVerilog). -; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. -; The default value is 0. -; Sv_Seed = 0 - -; Specify the solver "engine" that vsim will select for constrained random -; generation. -; Valid values are: -; "auto" - automatically select the best engine for the current -; constraint scenario -; "bdd" - evaluate all constraint scenarios using the BDD solver engine -; "act" - evaluate all constraint scenarios using the ACT solver engine -; While the BDD solver engine is generally efficient with constraint scenarios -; involving bitwise logical relationships, the ACT solver engine can exhibit -; superior performance with constraint scenarios involving large numbers of -; random variables related via arithmetic operators (+, *, etc). -; NOTE: This variable can be overridden with the vsim "-solveengine" command -; line switch. -; The default value is "auto". -; SolveEngine = auto - -; Specifies the maximum size that a dynamic array may be resized to by the -; solver. If the solver attempts to resize a dynamic array to a size greater -; than the specified limit, the solver will abort with an error. -; The default value is 10000. A value of 0 indicates no limit. -; SolveArrayResizeMax = 10000 - -; Specify error message severity when randomize() and randomize(null) failures -; are detected. -; -; Integer value up to two digits are allowed with each digit having the following legal values: -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; -; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents -; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit) -; represents the setting for randomize(null) calls. -; -; 2) When a single digit value is used, the setting is applied to both normal randomize() call -; and randomize(null) call. -; -; Example: Fatal error for randomize() failures and NO error for randomize(null) failures -; -solvefailseverity=40 -; -; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is -; enabled, a constraint contradiction report will be displayed for randomize() calls that -; have a message severity >= warning (i.e. constraint contradiction reports will not be -; generated for randomize() calls having a "no error" severity level) -; -; NOTE: This variable can be overridden with the vsim "-solvefailseverity" command -; line switch. -; -; The default is 1 (warning). -; SolveFailSeverity = 1 - -; Error message severity for suppressible errors that are detected in a -; solve/before constraint. -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" -; command line switch. -; The default is 3 (failure). -; SolveBeforeErrorSeverity = 3 - -; Error message severity for suppressible errors that are related to -; solve engine capacity limits -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" -; command line switch. -; The default is 3 (failure). -; SolveEngineErrorSeverity = 3 - -; Enable/disable constraint conflicts on randomize() failure -; Valid values: -; 0 - disable solvefaildebug -; 1 - basic debug (no performance penalty) -; 2 - enhanced debug (runtime performance penalty) -; -; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is -; enabled, a constraint contradiction report will be displayed for randomize() calls that -; have a message severity >= warning (i.e. constraint contradiction reports will not be -; generated for randomize() calls having a "no error" severity level) -; -; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command -; line switch. -; -; The default is 1 (basic debug). -; SolveFailDebug = 1 - -; Upon encountering a randomize() failure, generate a simplified testcase that -; will reproduce the failure. Optionally output the testcase to a file. -; Testcases for 'no-solution' failures will only be produced if SolveFailDebug -; is enabled (see above). -; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" -; command line switch. -; The default is OFF (do not generate a testcase). To enable testcase -; generation, uncomment this variable. To redirect testcase generation to a -; file, specify the name of the output file. -; SolveFailTestcase = - -; Specify solver timeout threshold (in seconds). randomize() will fail if the -; CPU time required to evaluate any randset exceeds the specified timeout. -; The default value is 500. A value of 0 will disable timeout failures. -; SolveTimeout = 500 - -; Specify the alternative behavior during solver replay. Must be used when combined with -solvereplay switch. -; SolveReplayOpt=[+|-][,[+|-]]*" -' Valid settings: -; validate : toggle the checking of value changes of non-random variables involved in randomize(). (default is off)" -; SolveReplayOpt=validate - -; Specify the maximum size of the solution graph generated by the BDD solver. -; This value can be used to force the BDD solver to abort the evaluation of a -; complex constraint scenario that cannot be evaluated with finite memory. -; This value is specified in 1000s of nodes. -; The default value is 10000. A value of 0 indicates no limit. -; SolveGraphMaxSize = 10000 - -; Specify the maximum number of evaluations that may be performed on the -; solution graph by the BDD solver. This value can be used to force the BDD -; solver to abort the evaluation of a complex constraint scenario that cannot -; be evaluated in finite time. This value is specified in 10000s of evaluations. -; The default value is 10000. A value of 0 indicates no limit. -; SolveGraphMaxEval = 10000 - -; Specify random sequence compatiblity with a prior release. This -; option is used to get the same random sequences during simulation as -; as a prior release. Only prior releases with the same major version -; as the current release are allowed. -; NOTE: Only those random sequence changes due to solver optimizations are -; reverted by this variable. Random sequence changes due to solver bugfixes -; cannot be un-done. -; NOTE: This variable can be overridden with the vsim "-solverev" command -; line switch. -; Default value set to "" (no compatibility). -; SolveRev = - -; Environment variable expansion of command line arguments has been depricated -; in favor shell level expansion. Universal environment variable expansion -; inside -f files is support and continued support for MGC Location Maps provide -; alternative methods for handling flexible pathnames. -; The following line may be uncommented and the value set to 1 to re-enable this -; deprecated behavior. The default value is 0. -; DeprecatedEnvironmentVariableExpansion = 0 - -; Specify the memory threshold for the System Verilog garbage collector. -; The value is the number of megabytes of class objects that must accumulate -; before the garbage collector is run. -; The GCThreshold setting is used when class debug mode is disabled to allow -; less frequent garbage collection and better simulation performance. -; The GCThresholdClassDebug setting is used when class debug mode is enabled -; to allow for more frequent garbage collection. -; GCThreshold = 100 -; GCThresholdClassDebug = 5 - -; Turn on/off collapsing of bus ports in VCD dumpports output -DumpportsCollapse = 1 - -; Location of Multi-Level Verification Component (MVC) installation. -; The default location is the product installation directory. -MvcHome = $QUESTA_MVC_HOME - -; Location of InFact installation. The default is $MODEL_TECH/../../infact -; -; InFactHome = $MODEL_TECH/../../infact - -; Initialize SystemVerilog enums using the base type's default value -; instead of the leftmost value. -; EnumBaseInit = 1 - -; Suppress file type registration. -; SuppressFileTypeReg = 1 - -; Enable/disable non-LRM compliant SystemVerilog language extensions. -; Valid extensions are: -; altdpiheader - Alternative style function signature generated in DPI header", -; cfce - generate an error if $cast fails as a function -; cfmt - C like formatting for specifiers with '#' prefix ('%#x', '%#h') -; dfsp - sets default format specifier as %p, if no format specifier is given for unpacked array in $display and related systasks -; expdfmt - enable format string extensions for $display/$sformatf -; extscan - support values greater than 32 bit for string builtin methods (atohex, atobin, atooct, atoi) -; fmtcap - prints capital hex digits with %X/%H in display calls -; iddp - ignore DPI disable protocol check -; lfmt - zero-pad data if '0' prefixes width in format specifier (e.g. "%04h") -; noexptc - ignore DPI export type name overloading check -; realrand - support randomize() with real variables and constraints (Default) -; SvExtensions = [+|-][,[+|-]*] - -; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions. -; Valid extensions are: -; arraymode - consider rand_mode of unpacked array field independently from its elements -; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles (Default) -; funcback - enable function backtracking (ACT only) -; genmodseedfix - enable LRM-compliant seeding of module/interface instances under for-generate blocks (Default) -; nodist - interpret 'dist' constraint as 'inside' (ACT only) -; noorder - ignore solve/before ordering constraints (ACT only) -; pathseed - enable unique seeding of module instances based on hierarchical path name -; prerandfirst - execute all pre_randomize() functions before evaluating any constraints -; promotedist - promote priority of 'dist' constraint if LHS has no solve/before -; purecheck - suppress pre_randomize() and post_randomize() calls for randomize(null) -; randindex - allow random index in constraint (Default) -; randstruct - consider all fields of unpacked structs as 'rand' -; skew - skew randomize results (ACT only) -; strictstab - strict random stability -; SvRandExtensions = [+|-][,[+|-]*] - -; Controls the formatting of '%p' and '%P' conversion specification, used in $display -; and similar system tasks. -; 1. SVPrettyPrintFlags=I use spaces(S) or tabs(T) per indentation level. -; The 'I' flag when present causes relevant data types to be expanded and indented into -; a more readable format. -; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). -; 2. SVPrettyPrintFlags=L limits the output to lines. -; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). -; 3. SVPrettyPrintFlags=C limits the output to characters. -; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). -; 4. SVPrettyPrintFlags=F limits the output to of relevant datatypes -; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). -; 5. SVPrettyPrintFlags=E limits the output to of relevant datatypes -; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). -; 6. SVPrettyPrintFlags=D suppresses the output of sub-elements below . -; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). -; 7. SVPrettyPrintFlags=R shows the output of specifier %p as per the specifed radix. -; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)). -; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format. -; 8. Items 1-7 above can be combined as a comma separated list. -; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb) -; SVPrettyPrintFlags=I4S - -[lmc] -; The simulator's interface to Logic Modeling's SmartModel SWIFT software -libsm = $MODEL_TECH/libsm.sl -; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) -; libsm = $MODEL_TECH/libsm.dll -; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) -; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl -; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) -; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o -; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) -; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so -; Logic Modeling's SmartModel SWIFT software (Windows NT) -; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll -; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) -; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so -; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) -; libswift = $LMC_HOME/lib/linux.lib/libswift.so - -; The simulator's interface to Logic Modeling's hardware modeler SFI software -libhm = $MODEL_TECH/libhm.sl -; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) -; libhm = $MODEL_TECH/libhm.dll -; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) -; libsfi = /lib/hp700/libsfi.sl -; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) -; libsfi = /lib/rs6000/libsfi.a -; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) -; libsfi = /lib/sun4.solaris/libsfi.so -; Logic Modeling's hardware modeler SFI software (Windows NT) -; libsfi = /lib/pcnt/lm_sfi.dll -; Logic Modeling's hardware modeler SFI software (Linux) -; libsfi = /lib/linux/libsfi.so - -[msg_system] -; Change a message severity or suppress a message. -; The format is: = [,...] -; suppress can be used to achieve +nowarn functionality -; The format is: suppress = ,,[,,...] -; Examples: -suppress = 8780 ;an explanation can be had by running: verror 8780 -; note = 3009 -; warning = 3033 -; error = 3010,3016 -; fatal = 3016,3033 -; suppress = 3009,3016,3601 -; suppress = 3009,CNNODP,3601,TFMPC -; suppress = 8683,8684 -; The command verror can be used to get the complete -; description of a message. - -; Control transcripting of Verilog display system task messages and -; PLI/FLI print function call messages. The system tasks include -; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They -; also include the analogous file I/O tasks that write to STDOUT -; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, -; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default -; is to have messages appear only in the transcript. The other -; settings are to send messages to the wlf file only (messages that -; are recorded in the wlf file can be viewed in the MsgViewer) or -; to both the transcript and the wlf file. The valid values are -; tran {transcript only (default)} -; wlf {wlf file only} -; both {transcript and wlf file} -; displaymsgmode = tran - -; Control transcripting of elaboration/runtime messages not -; addressed by the displaymsgmode setting. The default is to -; have messages appear only in the transcript. The other settings -; are to send messages to the wlf file only (messages that are -; recorded in the wlf file can be viewed in the MsgViewer) or to both -; the transcript and the wlf file. The valid values are -; tran {transcript only (default)} -; wlf {wlf file only} -; both {transcript and wlf file} -; msgmode = tran - -; Controls number of displays of a particluar message -; default value is 5 -; MsgLimitCount = 5 - -[utils] -; Default Library Type (while creating a library with "vlib") -; 0 - legacy library using subdirectories for design units -; 2 - flat library -; DefaultLibType = 2 - -; Flat Library Page Size (while creating a library with "vlib") -; Set the size in bytes for flat library file pages. Libraries containing -; very large files may benefit from a larger value. -; FlatLibPageSize = 8192 - -; Flat Library Page Cleanup Percentage (while creating a library with "vlib") -; Set the percentage of total pages deleted before library cleanup can occur. -; This setting is applied together with FlatLibPageDeleteThreshold. -; FlatLibPageDeletePercentage = 50 - -; Flat Library Page Cleanup Threshold (while creating a library with "vlib") -; Set the number of pages deleted before library cleanup can occur. -; This setting is applied together with FlatLibPageDeletePercentage. -; FlatLibPageDeleteThreshold = 1000 - - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/simulate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/simulate.do deleted file mode 100644 index 5721abca..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/simulate.do +++ /dev/null @@ -1,16 +0,0 @@ -onbreak {quit -f} -onerror {quit -f} - -vsim -voptargs="+acc" -t 1ps -L blk_mem_gen_v8_4_3 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.data_1p5m xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure -view signals - -do {data_1p5m.udo} - -run -all - -quit -force diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/wave.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/modelsim/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/README.txt deleted file mode 100644 index d3e5c3fa..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:35:28 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./data_1p5m.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './data_1p5m.sh' script. - -./data_1p5m.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./data_1p5m.sh -noclean_files - -For more information on the script, please type './data_1p5m.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/compile.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/compile.do deleted file mode 100644 index be47f761..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/compile.do +++ /dev/null @@ -1,27 +0,0 @@ -vlib questa_lib/work -vlib questa_lib/msim - -vlib questa_lib/msim/xil_defaultlib -vlib questa_lib/msim/xpm -vlib questa_lib/msim/blk_mem_gen_v8_4_3 - -vmap xil_defaultlib questa_lib/msim/xil_defaultlib -vmap xpm questa_lib/msim/xpm -vmap blk_mem_gen_v8_4_3 questa_lib/msim/blk_mem_gen_v8_4_3 - -vlog -work xil_defaultlib -64 -sv \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -64 -93 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work blk_mem_gen_v8_4_3 -64 \ -"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ - -vlog -work xil_defaultlib -64 \ -"../../../ip/data_1p5m/sim/data_1p5m.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/data_1m5.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/data_1m5.coe deleted file mode 100644 index 3dd9526c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/data_1m5.coe +++ /dev/null @@ -1,2051 +0,0 @@ -memory_initialization_radix = 2; -memory_initialization_vector = -1 -0 -1 -0 -1 -0 -1 -1 -0 -1 -1 -1 -0 -1 -1 -0 -1 -1 -1 -0 -0 -1 -1 -0 -1 -1 -1 -1 -0 -0 -1 -1 -1 -1 -0 -0 -1 -0 -0 -1 -0 -1 -1 -1 -0 -1 -0 -0 -1 -1 -0 -1 -0 -0 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-#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : data_1p5m.sh -# Simulator : Mentor Graphics Questa Advanced Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:35:28 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: data_1p5m.sh [-help] -# usage: data_1p5m.sh [-lib_map_path] -# usage: data_1p5m.sh [-noclean_files] -# usage: data_1p5m.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'data_1p5m.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "data_1p5m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -elaborate() -{ - source elaborate.do 2>&1 | tee -a elaborate.log -} - -# RUN_STEP: -simulate() -{ - vsim -64 -c -do "do {simulate.do}" -l simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./data_1p5m.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Copy modelsim.ini file -copy_setup_file() -{ - file="modelsim.ini" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then - lib_map_path="$1" - else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - cp $src_file . - fi -} - -# Create design library directory -create_lib_dir() -{ - lib_dir="questa_lib" - if [[ -e $lib_dir ]]; then - rm -rf $lib_dir - fi - - mkdir $lib_dir - -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./data_1p5m.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: data_1p5m.sh [-help]\n\ -Usage: data_1p5m.sh [-lib_map_path]\n\ -Usage: data_1p5m.sh [-reset_run]\n\ -Usage: data_1p5m.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/data_1p5m.udo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/data_1p5m.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/elaborate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/elaborate.do deleted file mode 100644 index 595fd6c9..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/elaborate.do +++ /dev/null @@ -1 +0,0 @@ -vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.data_1p5m xil_defaultlib.glbl -o data_1p5m_opt diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/file_info.txt deleted file mode 100644 index 8f539960..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, -data_1p5m.v,verilog,xil_defaultlib,../../../ip/data_1p5m/sim/data_1p5m.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/simulate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/simulate.do deleted file mode 100644 index c9c36801..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/simulate.do +++ /dev/null @@ -1,16 +0,0 @@ -onbreak {quit -f} -onerror {quit -f} - -vsim -t 1ps -lib xil_defaultlib data_1p5m_opt - -do {wave.do} - -view wave -view structure -view signals - -do {data_1p5m.udo} - -run -all - -quit -force diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/wave.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/questa/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/README.txt deleted file mode 100644 index d3e5c3fa..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:35:28 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./data_1p5m.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './data_1p5m.sh' script. - -./data_1p5m.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./data_1p5m.sh -noclean_files - -For more information on the script, please type './data_1p5m.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/compile.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/compile.do deleted file mode 100644 index 83432937..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/compile.do +++ /dev/null @@ -1,27 +0,0 @@ -vlib work -vlib riviera - -vlib riviera/xil_defaultlib -vlib riviera/xpm -vlib riviera/blk_mem_gen_v8_4_3 - -vmap xil_defaultlib riviera/xil_defaultlib -vmap xpm riviera/xpm -vmap blk_mem_gen_v8_4_3 riviera/blk_mem_gen_v8_4_3 - -vlog -work xil_defaultlib -sv2k12 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -93 \ -"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work blk_mem_gen_v8_4_3 -v2k5 \ -"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ - -vlog -work xil_defaultlib -v2k5 \ -"../../../ip/data_1p5m/sim/data_1p5m.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/data_1m5.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/data_1m5.coe deleted file mode 100644 index 3dd9526c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/data_1m5.coe +++ /dev/null @@ -1,2051 +0,0 @@ -memory_initialization_radix = 2; -memory_initialization_vector = -1 -0 -1 -0 -1 -0 -1 -1 -0 -1 -1 -1 -0 -1 -1 -0 -1 -1 -1 -0 -0 -1 -1 -0 -1 -1 -1 -1 -0 -0 -1 -1 -1 -1 -0 -0 -1 -0 -0 -1 -0 -1 -1 -1 -0 -1 -0 -0 -1 -1 -0 -1 -0 -0 -1 -1 -0 -0 -0 -1 -0 -1 -0 -0 -1 -0 -1 -1 -0 -0 -0 -1 -1 -0 -0 -0 -0 -1 -1 -0 -1 -0 -1 -1 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-#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : data_1p5m.sh -# Simulator : Aldec Riviera-PRO Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:35:28 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: data_1p5m.sh [-help] -# usage: data_1p5m.sh [-lib_map_path] -# usage: data_1p5m.sh [-noclean_files] -# usage: data_1p5m.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'data_1p5m.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "data_1p5m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - runvsimsa -l simulate.log -do "do {simulate.do}" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./data_1p5m.sh -help\" for more information)\n" - exit 1 - fi - map_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - map_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Map library.cfg file -map_setup_file() -{ - file="library.cfg" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then - lib_map_path="$1" - else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - vmap -link $lib_map_path - fi - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./data_1p5m.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: data_1p5m.sh [-help]\n\ -Usage: data_1p5m.sh [-lib_map_path]\n\ -Usage: data_1p5m.sh [-reset_run]\n\ -Usage: data_1p5m.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/data_1p5m.udo b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/data_1p5m.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/file_info.txt deleted file mode 100644 index 8f539960..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, -data_1p5m.v,verilog,xil_defaultlib,../../../ip/data_1p5m/sim/data_1p5m.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/simulate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/simulate.do deleted file mode 100644 index 0b05c93d..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/simulate.do +++ /dev/null @@ -1,17 +0,0 @@ -onbreak {quit -force} -onerror {quit -force} - -asim -t 1ps +access +r +m+data_1p5m -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.data_1p5m xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure - -do {data_1p5m.udo} - -run -all - -endsim - -quit -force diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/wave.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/riviera/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/vcs/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/vcs/README.txt deleted file mode 100644 index d3e5c3fa..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/vcs/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:35:28 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./data_1p5m.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './data_1p5m.sh' script. - -./data_1p5m.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./data_1p5m.sh -noclean_files - -For more information on the script, please type './data_1p5m.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/vcs/data_1m5.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/vcs/data_1m5.coe deleted file mode 100644 index 3dd9526c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/vcs/data_1m5.coe +++ /dev/null @@ -1,2051 +0,0 @@ -memory_initialization_radix = 2; -memory_initialization_vector = -1 -0 -1 -0 -1 -0 -1 -1 -0 -1 -1 -1 -0 -1 -1 -0 -1 -1 -1 -0 -0 -1 -1 -0 -1 -1 -1 -1 -0 -0 -1 -1 -1 -1 -0 -0 -1 -0 -0 -1 -0 -1 -1 -1 -0 -1 -0 -0 -1 -1 -0 -1 -0 -0 -1 -1 -0 -0 -0 -1 -0 -1 -0 -0 -1 -0 -1 -1 -0 -0 -0 -1 -1 -0 -0 -0 -0 -1 -1 -0 -1 -0 -1 -1 -1 -0 -0 -1 -1 -0 -1 -0 -0 -0 -1 -0 -1 -0 -0 -1 -1 -0 -0 -0 -0 -1 -0 -0 -0 -0 -1 -1 -1 -0 -0 -0 -1 -0 -0 -1 -0 -1 -0 -1 -1 -0 -0 -1 -0 -0 -1 -1 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elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:35:28 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: data_1p5m.sh [-help] -# usage: data_1p5m.sh [-lib_map_path] -# usage: data_1p5m.sh [-noclean_files] -# usage: data_1p5m.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'data_1p5m.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Command line options -vlogan_opts="-full64" -vhdlan_opts="-full64" -vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" -vcs_sim_opts="-ucli -licqueue -l simulate.log" - -# Design libraries -design_libs=(xil_defaultlib xpm blk_mem_gen_v8_4_3) - -# Simulation root library directory -sim_lib_dir="vcs_lib" - -# Script info -echo -e "data_1p5m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - vlogan -work xil_defaultlib $vlogan_opts -sverilog \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - 2>&1 | tee -a vlogan.log - - vhdlan -work xpm $vhdlan_opts \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - 2>&1 | tee -a vhdlan.log - - vlogan -work blk_mem_gen_v8_4_3 $vlogan_opts +v2k \ - "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ - 2>&1 | tee -a vlogan.log - - vlogan -work xil_defaultlib $vlogan_opts +v2k \ - "$ref_dir/../../../ip/data_1p5m/sim/data_1p5m.v" \ - 2>&1 | tee -a vlogan.log - - - vlogan -work xil_defaultlib $vlogan_opts +v2k \ - glbl.v \ - 2>&1 | tee -a vlogan.log - -} - -# RUN_STEP: -elaborate() -{ - vcs $vcs_elab_opts xil_defaultlib.data_1p5m xil_defaultlib.glbl -o data_1p5m_simv -} - -# RUN_STEP: -simulate() -{ - ./data_1p5m_simv $vcs_sim_opts -do simulate.do -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./data_1p5m.sh -help\" for more information)\n" - exit 1 - fi - create_lib_mappings $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - create_lib_mappings $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Define design library mappings -create_lib_mappings() -{ - file="synopsys_sim.setup" - if [[ -e $file ]]; then - if [[ ($1 == "") ]]; then - return - else - rm -rf $file - fi - fi - - touch $file - - lib_map_path="" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - mapping="$lib:$sim_lib_dir/$lib" - echo $mapping >> $file - done - - if [[ ($lib_map_path != "") ]]; then - incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" - echo $incl_ref >> $file - fi -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(ucli.key data_1p5m_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc data_1p5m_simv.daidir) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./data_1p5m.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: data_1p5m.sh [-help]\n\ -Usage: data_1p5m.sh [-lib_map_path]\n\ -Usage: data_1p5m.sh [-reset_run]\n\ -Usage: data_1p5m.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/vcs/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/vcs/file_info.txt deleted file mode 100644 index 8f539960..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/vcs/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, -data_1p5m.v,verilog,xil_defaultlib,../../../ip/data_1p5m/sim/data_1p5m.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/vcs/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/vcs/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/vcs/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/vcs/simulate.do b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/vcs/simulate.do deleted file mode 100644 index 58afc787..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/vcs/simulate.do +++ /dev/null @@ -1,2 +0,0 @@ -run -quit diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xcelium/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xcelium/README.txt deleted file mode 100644 index 3e1510d2..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xcelium/README.txt +++ /dev/null @@ -1,48 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:35:28 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./data_1p5m.sh - -This command will launch the 'execute' function for the single-step flow. This -function is called from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './data_1p5m.sh' script. - -./data_1p5m.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./data_1p5m.sh -noclean_files - -For more information on the script, please type './data_1p5m.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xcelium/data_1m5.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xcelium/data_1m5.coe deleted file mode 100644 index 3dd9526c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xcelium/data_1m5.coe +++ /dev/null @@ -1,2051 +0,0 @@ -memory_initialization_radix = 2; -memory_initialization_vector = -1 -0 -1 -0 -1 -0 -1 -1 -0 -1 -1 -1 -0 -1 -1 -0 -1 -1 -1 -0 -0 -1 -1 -0 -1 -1 -1 -1 -0 -0 -1 -1 -1 -1 -0 -0 -1 -0 -0 -1 -0 -1 -1 -1 -0 -1 -0 -0 -1 -1 -0 -1 -0 -0 -1 -1 -0 -0 -0 -1 -0 -1 -0 -0 -1 -0 -1 -1 -0 -0 -0 -1 -1 -0 -0 -0 -0 -1 -1 -0 -1 -0 -1 -1 -1 -0 -0 -1 -1 -0 -1 -0 -0 -0 -1 -0 -1 -0 -0 -1 -1 -0 -0 -0 -0 -1 -0 -0 -0 -0 -1 -1 -1 -0 -0 -0 -1 -0 -0 -1 -0 -1 -0 -1 -1 -0 -0 -1 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Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:35:28 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: data_1p5m.sh [-help] -# usage: data_1p5m.sh [-lib_map_path] -# usage: data_1p5m.sh [-noclean_files] -# usage: data_1p5m.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'data_1p5m.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Set the compiled library directory -ref_lib_dir="." - -# Command line options -xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" - -# Design libraries -design_libs=(xil_defaultlib xpm blk_mem_gen_v8_4_3) - -# Simulation root library directory -sim_lib_dir="xcelium_lib" - -# Script info -echo -e "data_1p5m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - execute -} - -# RUN_STEP: -execute() -{ - xrun $xrun_opts \ - -reflib "$ref_lib_dir/unisim:unisim" \ - -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ - -reflib "$ref_lib_dir/secureip:secureip" \ - -reflib "$ref_lib_dir/unimacro:unimacro" \ - -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.data_1p5m \ - -f run.f \ - -top glbl \ - glbl.v -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./data_1p5m.sh -help\" for more information)\n" - exit 1 - else - ref_lib_dir=$2 - fi - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./data_1p5m.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: data_1p5m.sh [-help]\n\ -Usage: data_1p5m.sh [-lib_map_path]\n\ -Usage: data_1p5m.sh [-reset_run]\n\ -Usage: data_1p5m.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xcelium/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xcelium/file_info.txt deleted file mode 100644 index 8f539960..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xcelium/file_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, -blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, -data_1p5m.v,verilog,xil_defaultlib,../../../ip/data_1p5m/sim/data_1p5m.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xcelium/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xcelium/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xcelium/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xcelium/run.f b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xcelium/run.f deleted file mode 100644 index bbd4ba5f..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xcelium/run.f +++ /dev/null @@ -1,17 +0,0 @@ --makelib xcelium_lib/xil_defaultlib -sv \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ --endlib --makelib xcelium_lib/xpm \ - "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ --endlib --makelib xcelium_lib/blk_mem_gen_v8_4_3 \ - "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ --endlib --makelib xcelium_lib/xil_defaultlib \ - "../../../ip/data_1p5m/sim/data_1p5m.v" \ --endlib --makelib xcelium_lib/xil_defaultlib \ - glbl.v --endlib - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/README.txt deleted file mode 100644 index d3e5c3fa..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Sat Mar 18 23:35:28 +0800 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./data_1p5m.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './data_1p5m.sh' script. - -./data_1p5m.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./data_1p5m.sh -noclean_files - -For more information on the script, please type './data_1p5m.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/cmd.tcl b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/cmd.tcl deleted file mode 100644 index eef7a0f0..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/cmd.tcl +++ /dev/null @@ -1,12 +0,0 @@ -set curr_wave [current_wave_config] -if { [string length $curr_wave] == 0 } { - if { [llength [get_objects]] > 0} { - add_wave / - set_property needs_save false [current_wave_config] - } else { - send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." - } -} - -run -all -quit diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/data_1m5.coe b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/data_1m5.coe deleted file mode 100644 index 3dd9526c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/data_1m5.coe +++ /dev/null @@ -1,2051 +0,0 @@ -memory_initialization_radix = 2; -memory_initialization_vector = -1 -0 -1 -0 -1 -0 -1 -1 -0 -1 -1 -1 -0 -1 -1 -0 -1 -1 -1 -0 -0 -1 -1 -0 -1 -1 -1 -1 -0 -0 -1 -1 -1 -1 -0 -0 -1 -0 -0 -1 -0 -1 -1 -1 -0 -1 -0 -0 -1 -1 -0 -1 -0 -0 -1 -1 -0 -0 -0 -1 -0 -1 -0 -0 -1 -0 -1 -1 -0 -0 -0 -1 -1 -0 -0 -0 -0 -1 -1 -0 -1 -0 -1 -1 -1 -0 -0 -1 -1 -0 -1 -0 -0 -0 -1 -0 -1 -0 -0 -1 -1 -0 -0 -0 -0 -1 -0 -0 -0 -0 -1 -1 -1 -0 -0 -0 -1 -0 -0 -1 -0 -1 -0 -1 -1 -0 -0 -1 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elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Sat Mar 18 23:35:28 +0800 2023 -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: data_1p5m.sh [-help] -# usage: data_1p5m.sh [-lib_map_path] -# usage: data_1p5m.sh [-noclean_files] -# usage: data_1p5m.sh [-reset_run] -# -#********************************************************************************************************* - -# Command line options -xv_boost_lib_path=C:/Xilinx/Vivado/2019.1/tps/boost_1_64_0 -xvlog_opts="--relax" - - -# Script info -echo -e "data_1p5m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log - -} - -# RUN_STEP: -elaborate() -{ - xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_3 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot data_1p5m xil_defaultlib.data_1p5m xil_defaultlib.glbl -log elaborate.log -} - -# RUN_STEP: -simulate() -{ - xsim data_1p5m -key {Behavioral:sim_1:Functional:data_1p5m} -tclbatch cmd.tcl -log simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./data_1p5m.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Copy xsim.ini file -copy_setup_file() -{ - file="xsim.ini" - lib_map_path="C:/Xilinx/Vivado/2019.1/data/xsim" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - cp $src_file . - fi - - # Map local design libraries to xsim.ini - map_local_libs - - fi -} - -# Map local design libraries -map_local_libs() -{ - updated_mappings=() - local_mappings=() - - # Local design libraries - local_libs=() - - if [[ 0 == ${#local_libs[@]} ]]; then - return - fi - - file="xsim.ini" - file_backup="xsim.ini.bak" - - if [[ -e $file ]]; then - rm -f $file_backup - # Create a backup copy of the xsim.ini file - cp $file $file_backup - # Read libraries from backup file and search in local library collection - while read -r line - do - IN=$line - # Split mapping entry with '=' delimiter to fetch library name and mapping - read lib_name mapping <<<$(IFS="="; echo $IN) - # If local library found, then construct the local mapping and add to local mapping collection - if `echo ${local_libs[@]} | grep -wq $lib_name` ; then - line="$lib_name=xsim.dir/$lib_name" - local_mappings+=("$lib_name") - fi - # Add to updated library mapping collection - updated_mappings+=("$line") - done < "$file_backup" - # Append local libraries not found originally from xsim.ini - for (( i=0; i<${#local_libs[*]}; i++ )); do - lib_name="${local_libs[i]}" - if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then - line="$lib_name=xsim.dir/$lib_name" - updated_mappings+=("$line") - fi - done - # Write updated mappings in xsim.ini - rm -f $file - for (( i=0; i<${#updated_mappings[*]}; i++ )); do - lib_name="${updated_mappings[i]}" - echo $lib_name >> $file - done - else - for (( i=0; i<${#local_libs[*]}; i++ )); do - lib_name="${local_libs[i]}" - mapping="$lib_name=xsim.dir/$lib_name" - echo $mapping >> $file - done - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb data_1p5m.wdb xsim.dir) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./data_1p5m.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: data_1p5m.sh [-help]\n\ -Usage: data_1p5m.sh [-lib_map_path]\n\ -Usage: data_1p5m.sh [-reset_run]\n\ -Usage: data_1p5m.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/elab.opt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/elab.opt deleted file mode 100644 index ed1f7460..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/elab.opt +++ /dev/null @@ -1 +0,0 @@ ---relax --debug typical --mt auto -L blk_mem_gen_v8_4_3 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot data_1p5m xil_defaultlib.data_1p5m xil_defaultlib.glbl -log elaborate.log diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/file_info.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/file_info.txt deleted file mode 100644 index 05d525e8..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/file_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -data_1p5m.v,verilog,xil_defaultlib,../../../ip/data_1p5m/sim/data_1p5m.v, -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/glbl.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/vlog.prj b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/vlog.prj deleted file mode 100644 index 0fa38c70..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/vlog.prj +++ /dev/null @@ -1,6 +0,0 @@ -verilog xil_defaultlib \ -"../../../ip/data_1p5m/sim/data_1p5m.v" \ - -verilog xil_defaultlib "glbl.v" - -nosort diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/xsim.ini b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/xsim.ini deleted file mode 100644 index 6cb07f57..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/data_1p5m/xsim/xsim.ini +++ /dev/null @@ -1,430 +0,0 @@ -std=$RDI_DATADIR/xsim/vhdl/std -ieee=$RDI_DATADIR/xsim/vhdl/ieee -ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed -vl=$RDI_DATADIR/xsim/vhdl/vl -synopsys=$RDI_DATADIR/xsim/vhdl/synopsys -secureip=$RDI_DATADIR/xsim/verilog/secureip -unisim=$RDI_DATADIR/xsim/vhdl/unisim -unimacro=$RDI_DATADIR/xsim/vhdl/unimacro -unifast=$RDI_DATADIR/xsim/vhdl/unifast -unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver -unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver -unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver -simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver -system_cache_v4_0_6=$RDI_DATADIR/xsim/ip/system_cache_v4_0_6 -bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0 -g709_rs_decoder_v2_2_8=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_8 -xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0 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-axi_amm_bridge_v1_0_9=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_9 -axi_datamover_v5_1_21=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_21 -v_axi4s_vid_out_v4_0_10=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_10 -jesd204_v7_2_6=$RDI_DATADIR/xsim/ip/jesd204_v7_2_6 -v_letterbox_v1_0_13=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_13 -interlaken_v2_4_3=$RDI_DATADIR/xsim/ip/interlaken_v2_4_3 -uhdsdi_gt_v2_0_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_0 -axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7 -rst_vip_v1_0_3=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_3 -audio_formatter_v1_0_1=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_1 -lte_3gpp_channel_estimator_v2_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_16 -v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13 -g709_fec_v2_3_5=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_5 -xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6 -axi_chip2chip_v5_0_6=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_6 -fc32_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_11 -v_mix_v3_0_3=$RDI_DATADIR/xsim/ip/v_mix_v3_0_3 -multi_channel_25g_rs_fec_v1_0_5=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_5 -in_system_ibert_v1_0_9=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_9 -ethernet_1_10_25g_v2_1_4=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_1_4 -axis_broadcaster_v1_1_18=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_18 -axis_combiner_v1_1_17=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_17 -axi_apb_bridge_v3_0_15=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_15 -displayport_v9_0_1=$RDI_DATADIR/xsim/ip/displayport_v9_0_1 -clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2 -hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1 -axi_register_slice_v2_1_19=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_19 -vid_phy_controller_v2_1_5=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_5 -picxo=$RDI_DATADIR/xsim/ip/picxo -usxgmii_v1_1_0=$RDI_DATADIR/xsim/ip/usxgmii_v1_1_0 -v_vcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_13 -bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0 -prc_v1_3_2=$RDI_DATADIR/xsim/ip/prc_v1_3_2 -axi_usb2_device_v5_0_20=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_20 -lte_3gpp_mimo_encoder_v4_0_14=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_14 -l_ethernet_v2_5_2=$RDI_DATADIR/xsim/ip/l_ethernet_v2_5_2 -xdma_v4_1_3=$RDI_DATADIR/xsim/ip/xdma_v4_1_3 -axis_vio_v1_0_0=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_0 -c_counter_binary_v12_0_13=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_13 -noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0 -xbip_dsp48_macro_v3_0_17=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_17 -c_accum_v12_0_13=$RDI_DATADIR/xsim/ip/c_accum_v12_0_13 -xbip_multadd_v3_0_14=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_14 -axi_uartlite_v2_0_23=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_23 -noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0 -axi_intc_v4_1_13=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_13 -i2s_transmitter_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_3 -pc_cfr_v6_0_8=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_8 -mutex_v2_1_10=$RDI_DATADIR/xsim/ip/mutex_v2_1_10 -c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6 -sid_v8_0_14=$RDI_DATADIR/xsim/ip/sid_v8_0_14 -fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6 -quadsgmii_v3_4_6=$RDI_DATADIR/xsim/ip/quadsgmii_v3_4_6 -microblaze_v11_0_1=$RDI_DATADIR/xsim/ip/microblaze_v11_0_1 -lib_bmg_v1_0_12=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_12 -dds_compiler_v6_0_18=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_18 -me_pl_v1_0=$RDI_DATADIR/xsim/ip/me_pl_v1_0 -gtwizard_ultrascale_v1_7_6=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_6 -axis_clock_converter_v1_1_20=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_20 -nvmeha_v1_0_0=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_0 -tmr_inject_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_3 -axi_mcdma_v1_1_0=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_0 -axi_hwicap_v3_0_23=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_23 -v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0 -v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0 -canfd_v2_0_1=$RDI_DATADIR/xsim/ip/canfd_v2_0_1 -gig_ethernet_pcs_pma_v16_1_6=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_6 -lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2 -ieee802d3_rs_fec_v2_0_5=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_5 -ibert_lib_v1_0_6=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_6 -high_speed_selectio_wiz_v3_4_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_1 -xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6 -fec_5g_common_v1_0_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_1 -tmr_voter_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_2 -hdmi_gt_controller_v1_0_0=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_0 -axi_traffic_gen_v2_0_20=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_20 -flexo_100g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_11 -v_smpte_uhdsdi_v1_0_7=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_7 -xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6 -fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10 -ieee802d3_rs_fec_v1_0_15=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_15 -axis_subset_converter_v1_1_19=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_19 -noc_nmu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_v1_0_0 -duc_ddc_compiler_v3_0_15=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_15 -dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13 -mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0 -ieee802d3_200g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_7 -sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1 -mrmac_v1_0_0=$RDI_DATADIR/xsim/ip/mrmac_v1_0_0 -sem_ultra_v3_1_11=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_11 -v_tpg_v8_0_1=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_1 -axi_tft_v2_0_22=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_22 -ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13 -switch_core_top_v1_0_7=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_7 -rama_v1_1_2_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_2_lib -v_hcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_13 -emb_fifo_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_1 -hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3 -axis_data_fifo_v2_0_1=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_1 -hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0 -rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1 -displayport_v8_1_1=$RDI_DATADIR/xsim/ip/displayport_v8_1_1 -axi_mmu_v2_1_17=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_17 -proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13 -pc_cfr_v6_3_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_3_0 -v_osd_v6_0_16=$RDI_DATADIR/xsim/ip/v_osd_v6_0_16 -pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12 -xfft_v9_0_17=$RDI_DATADIR/xsim/ip/xfft_v9_0_17 -axi_cdma_v4_1_19=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_19 -audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0 -lib_fifo_v1_0_13=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_13 -v_enhance_v8_0_15=$RDI_DATADIR/xsim/ip/v_enhance_v8_0_15 -axi_clock_converter_v2_1_18=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_18 -xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0 -emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5 -axi_mm2s_mapper_v1_1_18=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_18 -xfft_v7_2_9=$RDI_DATADIR/xsim/ip/xfft_v7_2_9 -pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0 -v_smpte_sdi_v3_0_8=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_8 -fir_compiler_v7_2_12=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_12 -div_gen_v5_1_15=$RDI_DATADIR/xsim/ip/div_gen_v5_1_15 -mdm_v3_2_16=$RDI_DATADIR/xsim/ip/mdm_v3_2_16 -v_axi4s_remap_v1_0_11=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_11 -xxv_ethernet_v2_5_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_5_3 -xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2 -ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig -remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4 -pr_axi_shutdown_manager_v1_0_1=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_1 -axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0 -smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0 -axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib -axi_dwidth_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_19 -xlconstant_v1_1_6=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_6 -tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6 -mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2 -v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1 -axi_fifo_mm_s_v4_2_1=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_1 -util_idelay_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_1 -rs_toolbox_v9_0_7=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_7 -v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0 -dsp_macro_v1_0_0=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_0 -pc_cfr_v6_2_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_2 -axi_timer_v2_0_21=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_21 -high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1 -axi_sideband_util_v1_0_3=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_3 -sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2 -gmii_to_rgmii_v4_0_7=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_0_7 -xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2 -high_speed_selectio_wiz_v3_5_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_5_1 -axi_msg_v1_0_5=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_5 -axi_ahblite_bridge_v3_0_16=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_16 -v_rgb2ycrcb_v7_1_13=$RDI_DATADIR/xsim/ip/v_rgb2ycrcb_v7_1_13 -v_mix_v4_0_0=$RDI_DATADIR/xsim/ip/v_mix_v4_0_0 -axi_ethernetlite_v3_0_17=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_17 -axi_uart16550_v2_0_21=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_21 -axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0 -vfb_v1_0_13=$RDI_DATADIR/xsim/ip/vfb_v1_0_13 -advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0 -ats_switch_v1_0_2=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_2 -interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4 -axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub -cpri_v8_10_3=$RDI_DATADIR/xsim/ip/cpri_v8_10_3 -c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6 -v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0 -stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0 -rld3_pl_v1_0_1=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_1 -ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0 -lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0 -axi_epc_v2_0_22=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_22 -g709_rs_encoder_v2_2_6=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_6 -blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6 -tmr_sem_v1_0_9=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_9 -fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6 -axi_vdma_v6_3_7=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_7 -axis_data_fifo_v1_1_20=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_20 -xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip -axi_ethernet_buffer_v2_0_20=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_20 -rs_encoder_v9_0_15=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_15 -axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0 -ta_dma_v1_0_3=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_3 -tcc_encoder_3gpp_v5_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_15 -axi_perf_mon_v5_0_21=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_21 -noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0 -sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1 -lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2 -v_csc_v1_0_13=$RDI_DATADIR/xsim/ip/v_csc_v1_0_13 -shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0 -lte_fft_v2_0_18=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_18 -gtwizard_ultrascale_v1_6_11=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_11 -amm_axi_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_5 -mii_to_rmii_v2_0_21=$RDI_DATADIR/xsim/ip/mii_to_rmii_v2_0_21 -videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5 -audio_clock_recovery_v1_0=$RDI_DATADIR/xsim/ip/audio_clock_recovery_v1_0 -cmac_v2_4_1=$RDI_DATADIR/xsim/ip/cmac_v2_4_1 -i2s_receiver_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_3 -v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0 -v_demosaic_v1_0_5=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_5 -remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4 -microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4 -hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3 -etrnic_v1_0_3=$RDI_DATADIR/xsim/ip/etrnic_v1_0_3 -xfft_v9_1_2=$RDI_DATADIR/xsim/ip/xfft_v9_1_2 -ddr4_pl_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_2 -xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6 -cmac_usplus_v2_5_3=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_5_3 -jesd204c_v4_1_1=$RDI_DATADIR/xsim/ip/jesd204c_v4_1_1 -debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1 -axis_protocol_checker_v2_0_3=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_3 -v_frmbuf_wr_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_2 -v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9 -mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4 -lte_dl_channel_encoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_15 -axi_protocol_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_19 -xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0 -clk_gen_sim_v1_0_0=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_0 -axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0 -microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7 -cmpy_v6_0_17=$RDI_DATADIR/xsim/ip/cmpy_v6_0_17 -cmac_v2_3_5=$RDI_DATADIR/xsim/ip/cmac_v2_3_5 -ieee802d3_400g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_7 -xxv_ethernet_v2_4_5=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_4_5 -axi_timebase_wdt_v3_0_11=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_11 -tcc_decoder_3gppmm_v2_0_18=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_18 -v_deinterlacer_v5_0_13=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_13 -dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16 -axi_fifo_mm_s_v4_1_16=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_16 -processing_system7_vip_v1_0_7=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_7 -g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18 -rs_decoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_16 -c_shift_ram_v12_0_13=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_13 -displayport_v7_0_11=$RDI_DATADIR/xsim/ip/displayport_v7_0_11 -v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0 -v_deinterlacer_v4_0_12=$RDI_DATADIR/xsim/ip/v_deinterlacer_v4_0_12 -sem_v4_1_12=$RDI_DATADIR/xsim/ip/sem_v4_1_12 -xaui_v12_3_6=$RDI_DATADIR/xsim/ip/xaui_v12_3_6 -ten_gig_eth_mac_v15_1_7=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_7 -oddr_v1_0_0=$RDI_DATADIR/xsim/ip/oddr_v1_0_0 -c_addsub_v12_0_13=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_13 -v_ccm_v6_0_15=$RDI_DATADIR/xsim/ip/v_ccm_v6_0_15 -zynq_ultra_ps_e_vip_v1_0_5=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_5 -cic_compiler_v4_0_14=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_14 -c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6 -axi_memory_init_v1_0_0=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_0 -pr_decoupler_v1_0_7=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_7 -timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4 -lte_pucch_receiver_v2_0_16=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_16 -zynq_ultra_ps_e_v3_2_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_3 -v_gamma_lut_v1_0_5=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_5 -bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0 -pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0 -tcc_encoder_3gpplte_v4_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_15 -polar_v1_0_3=$RDI_DATADIR/xsim/ip/polar_v1_0_3 -rxaui_v4_4_6=$RDI_DATADIR/xsim/ip/rxaui_v4_4_6 -xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6 -v_gamma_v7_0_15=$RDI_DATADIR/xsim/ip/v_gamma_v7_0_15 -ernic_v1_0_1=$RDI_DATADIR/xsim/ip/ernic_v1_0_1 -high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3 -mailbox_v2_1_11=$RDI_DATADIR/xsim/ip/mailbox_v2_1_11 -video_frame_crc_v1_0_1=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_1 -axi_sg_v4_1_12=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_12 -ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0 -lmb_bram_if_cntlr_v4_0_16=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_16 -l_ethernet_v2_4_3=$RDI_DATADIR/xsim/ip/l_ethernet_v2_4_3 -dft_v4_1_1=$RDI_DATADIR/xsim/ip/dft_v4_1_1 -rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0 -axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6 -v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0 -stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0 -lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0 -uhdsdi_gt_v1_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_3 -pc_cfr_v6_1_4=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_4 -lmb_v10_v3_0_9=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_9 -axis_interconnect_v1_1_17=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_17 -cordic_v6_0_15=$RDI_DATADIR/xsim/ip/cordic_v6_0_15 -axis_register_slice_v1_1_19=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_19 -axis_switch_v1_1_19=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_19 -axi_interconnect_v1_7_16=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_16 -mult_gen_v12_0_15=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_15 -spdif_v2_0_21=$RDI_DATADIR/xsim/ip/spdif_v2_0_21 -v_hscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_13 -ethernet_1_10_25g_v2_3_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_3_3 -xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6 -axi_quad_spi_v3_2_18=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_18 -axi_bram_ctrl_v4_1_1=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_1 -axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4 -axi_protocol_checker_v2_0_5=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_5 -axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0 -mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7 -ieee802d3_25g_rs_fec_v1_0_13=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_13 -aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0 -xtlm=$RDI_DATADIR/xsim/ip/xtlm -iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0 -ieee802d3_clause74_fec_v1_0_4=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_4 -xlconcat_v2_1_3=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_3 -perf_axi_tg_v1_0_8=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_8 -axi_crossbar_v2_1_20=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_20 -tsn_endpoint_ethernet_mac_block_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_4 -v_ycrcb2rgb_v7_1_13=$RDI_DATADIR/xsim/ip/v_ycrcb2rgb_v7_1_13 -xhmc_v1_0_9=$RDI_DATADIR/xsim/ip/xhmc_v1_0_9 -dp_videoaxi4s_bridge_v1_0_0=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_0 -lte_ul_channel_decoder_v4_0_16=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_16 -soft_ecc_proxy_v1_0_0=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_0 -pr_bitstream_monitor_v1_0_1=$RDI_DATADIR/xsim/ip/pr_bitstream_monitor_v1_0_1 -sync_ip=$RDI_DATADIR/xsim/ip/sync_ip -v_frmbuf_rd_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_1_2 -c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6 -cmac_usplus_v2_6_2=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_6_2 -axi_mcdma_v1_0_5=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_5 -c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6 -g709_fec_v2_4_1=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_1 -lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0 -ai_pl=$RDI_DATADIR/xsim/ip/ai_pl -fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4 -v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0 -l_ethernet_v2_3_5=$RDI_DATADIR/xsim/ip/l_ethernet_v2_3_5 -microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6 -v_uhdsdi_audio_v2_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_1 -ldpc_v2_0_3=$RDI_DATADIR/xsim/ip/ldpc_v2_0_3 -xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6 -xpm=$RDI_DATADIR/xsim/ip/xpm -srio_gen2_v4_1_6=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_6 -g975_efec_i4_v1_0_17=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_17 -noc_na_v1_0_0=$RDI_DATADIR/xsim/ip/noc_na_v1_0_0 -roe_framer_v2_0_1=$RDI_DATADIR/xsim/ip/roe_framer_v2_0_1 -xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10 -generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0 -ten_gig_eth_pcs_pma_v6_0_15=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_15 -can_v5_0_22=$RDI_DATADIR/xsim/ip/can_v5_0_22 -av_pat_gen_v1_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_0 -fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1 -lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0 -axis_dwidth_converter_v1_1_18=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_18 -lte_rach_detector_v3_1_5=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_5 -xxv_ethernet_v3_0_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v3_0_3 -axi_iic_v2_0_22=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_22 -axi_pcie_v2_9_1=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_1 -util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4 -sim_trig_top_v1_0=$RDI_DATADIR/xsim/ip/sim_trig_top_v1_0 -v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0 -v_tpg_v7_0_13=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_13 -sd_fec_v1_1_3=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_3 -xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6 -lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2 -v_multi_scaler_v1_0_1=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_0_1 -axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0 -advanced_io_wizard_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_0 -mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8 -axi_pcie3_v3_0_9=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_9 -axi_vfifo_ctrl_v2_0_21=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_21 -xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/README.txt index e36c9c36..d01b1e30 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/README.txt +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Mar 18 23:38:42 +0800 2023 +# Generated by export_simulation on Tue Mar 21 22:54:16 +0800 2023 # ################################################################################ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.sh index f95d58a1..efe9da05 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.sh +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Mar 18 23:38:42 +0800 2023 +# Generated by Vivado on Tue Mar 21 22:54:16 +0800 2023 # SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -93,11 +93,10 @@ setup() map_setup_file() { file="library.cfg" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then + if [[ ($1 != "") ]]; then lib_map_path="$1" else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + lib_map_path="D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/activehdl" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/README.txt index 1e60b187..0c24d1bd 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/README.txt +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Mar 18 23:38:42 +0800 2023 +# Generated by export_simulation on Tue Mar 21 22:54:16 +0800 2023 # ################################################################################ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/vio_manual_ctrl.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/vio_manual_ctrl.sh index ad712639..caaf7f1f 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/vio_manual_ctrl.sh +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/vio_manual_ctrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Mar 18 23:38:42 +0800 2023 +# Generated by Vivado on Tue Mar 21 22:54:16 +0800 2023 # SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/README.txt index e36c9c36..d01b1e30 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/README.txt +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Mar 18 23:38:42 +0800 2023 +# Generated by export_simulation on Tue Mar 21 22:54:16 +0800 2023 # ################################################################################ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.sh index cb373c84..d133e51f 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.sh +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Mar 18 23:38:42 +0800 2023 +# Generated by Vivado on Tue Mar 21 22:54:16 +0800 2023 # SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/README.txt index e36c9c36..d01b1e30 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/README.txt +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Mar 18 23:38:42 +0800 2023 +# Generated by export_simulation on Tue Mar 21 22:54:16 +0800 2023 # ################################################################################ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.sh index 13583ecc..084a49c8 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.sh +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Mar 18 23:38:42 +0800 2023 +# Generated by Vivado on Tue Mar 21 22:54:16 +0800 2023 # SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -102,11 +102,10 @@ setup() copy_setup_file() { file="modelsim.ini" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then + if [[ ($1 != "") ]]; then lib_map_path="$1" else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + lib_map_path="D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/README.txt index e36c9c36..d01b1e30 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/README.txt +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Mar 18 23:38:42 +0800 2023 +# Generated by export_simulation on Tue Mar 21 22:54:16 +0800 2023 # ################################################################################ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.sh index 9f900f39..9bc7c9ec 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.sh +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Mar 18 23:38:42 +0800 2023 +# Generated by Vivado on Tue Mar 21 22:54:16 +0800 2023 # SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -93,11 +93,10 @@ setup() map_setup_file() { file="library.cfg" - lib_map_path="" - if [[ ($1 != "" && -e $1) ]]; then + if [[ ($1 != "") ]]; then lib_map_path="$1" else - echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + lib_map_path="D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/README.txt index e36c9c36..d01b1e30 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/README.txt +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Mar 18 23:38:42 +0800 2023 +# Generated by export_simulation on Tue Mar 21 22:54:16 +0800 2023 # ################################################################################ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/vio_manual_ctrl.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/vio_manual_ctrl.sh index 38ac00a4..58769e5b 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/vio_manual_ctrl.sh +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/vio_manual_ctrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Mar 18 23:38:42 +0800 2023 +# Generated by Vivado on Tue Mar 21 22:54:16 +0800 2023 # SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/README.txt index 1e60b187..0c24d1bd 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/README.txt +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Mar 18 23:38:42 +0800 2023 +# Generated by export_simulation on Tue Mar 21 22:54:16 +0800 2023 # ################################################################################ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/vio_manual_ctrl.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/vio_manual_ctrl.sh index 5e741cf4..b2d76830 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/vio_manual_ctrl.sh +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/vio_manual_ctrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Mar 18 23:38:42 +0800 2023 +# Generated by Vivado on Tue Mar 21 22:54:16 +0800 2023 # SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/README.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/README.txt index e36c9c36..d01b1e30 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/README.txt +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Sat Mar 18 23:38:42 +0800 2023 +# Generated by export_simulation on Tue Mar 21 22:54:16 +0800 2023 # ################################################################################ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vio_manual_ctrl.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vio_manual_ctrl.sh index bd7723c9..ece8da97 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vio_manual_ctrl.sh +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vio_manual_ctrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Sat Mar 18 23:38:42 +0800 2023 +# Generated by Vivado on Tue Mar 21 22:54:16 +0800 2023 # SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5d522090233ffcd/b5d522090233ffcd.xci b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5d522090233ffcd/b5d522090233ffcd.xci new file mode 100644 index 00000000..c897a4ae --- /dev/null +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5d522090233ffcd/b5d522090233ffcd.xci @@ -0,0 +1,810 @@ + + + xilinx.com + ipcache + b5d522090233ffcd + 0 + + + vio_manual_ctrl + + + 100000000 + 0 + 1 + 0 + 5 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 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1 + 0x1 + 3 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x1 + 3 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x1 + 4 + vio_manual_ctrl + kintex7 + xc7k410t + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + b5d522090233ffcd + 9a10a187 + 23 + IP_Unknown + 20 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5d522090233ffcd/vio_manual_ctrl.dcp b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5d522090233ffcd/vio_manual_ctrl.dcp new file mode 100644 index 00000000..ed6df12b Binary files /dev/null and b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5d522090233ffcd/vio_manual_ctrl.dcp differ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5d522090233ffcd/vio_manual_ctrl_sim_netlist.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5d522090233ffcd/vio_manual_ctrl_sim_netlist.v new file mode 100644 index 00000000..f433f3da --- /dev/null +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5d522090233ffcd/vio_manual_ctrl_sim_netlist.v @@ -0,0 +1,9027 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +// Date : Tue Mar 21 22:54:42 2023 +// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_sim_netlist.v +// Design : vio_manual_ctrl +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "vio_manual_ctrl,vio,{}" *) (* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +(* NotValidForBitStream *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix + (clk, + probe_out0, + probe_out1, + probe_out2, + probe_out3, + probe_out4); + input clk; + output [1:0]probe_out0; + output [0:0]probe_out1; + output [31:0]probe_out2; + output [1:0]probe_out3; + output [3:0]probe_out4; + + wire clk; + wire [1:0]probe_out0; + wire [0:0]probe_out1; + wire [31:0]probe_out2; + wire [1:0]probe_out3; + wire [3:0]probe_out4; + wire [0:0]NLW_inst_probe_out10_UNCONNECTED; + wire [0:0]NLW_inst_probe_out100_UNCONNECTED; + wire [0:0]NLW_inst_probe_out101_UNCONNECTED; + wire [0:0]NLW_inst_probe_out102_UNCONNECTED; + wire [0:0]NLW_inst_probe_out103_UNCONNECTED; + wire [0:0]NLW_inst_probe_out104_UNCONNECTED; + wire [0:0]NLW_inst_probe_out105_UNCONNECTED; + wire [0:0]NLW_inst_probe_out106_UNCONNECTED; + wire [0:0]NLW_inst_probe_out107_UNCONNECTED; + wire [0:0]NLW_inst_probe_out108_UNCONNECTED; + wire [0:0]NLW_inst_probe_out109_UNCONNECTED; + wire [0:0]NLW_inst_probe_out11_UNCONNECTED; + wire [0:0]NLW_inst_probe_out110_UNCONNECTED; + wire [0:0]NLW_inst_probe_out111_UNCONNECTED; + wire [0:0]NLW_inst_probe_out112_UNCONNECTED; + wire [0:0]NLW_inst_probe_out113_UNCONNECTED; + wire [0:0]NLW_inst_probe_out114_UNCONNECTED; + wire [0:0]NLW_inst_probe_out115_UNCONNECTED; + wire [0:0]NLW_inst_probe_out116_UNCONNECTED; + wire [0:0]NLW_inst_probe_out117_UNCONNECTED; + wire [0:0]NLW_inst_probe_out118_UNCONNECTED; + wire [0:0]NLW_inst_probe_out119_UNCONNECTED; + wire [0:0]NLW_inst_probe_out12_UNCONNECTED; + wire [0:0]NLW_inst_probe_out120_UNCONNECTED; + wire [0:0]NLW_inst_probe_out121_UNCONNECTED; + wire [0:0]NLW_inst_probe_out122_UNCONNECTED; + wire [0:0]NLW_inst_probe_out123_UNCONNECTED; + wire [0:0]NLW_inst_probe_out124_UNCONNECTED; + wire [0:0]NLW_inst_probe_out125_UNCONNECTED; + wire [0:0]NLW_inst_probe_out126_UNCONNECTED; + wire [0:0]NLW_inst_probe_out127_UNCONNECTED; + wire [0:0]NLW_inst_probe_out128_UNCONNECTED; + wire [0:0]NLW_inst_probe_out129_UNCONNECTED; + wire [0:0]NLW_inst_probe_out13_UNCONNECTED; + wire [0:0]NLW_inst_probe_out130_UNCONNECTED; + wire [0:0]NLW_inst_probe_out131_UNCONNECTED; + wire [0:0]NLW_inst_probe_out132_UNCONNECTED; + wire [0:0]NLW_inst_probe_out133_UNCONNECTED; + wire [0:0]NLW_inst_probe_out134_UNCONNECTED; + wire [0:0]NLW_inst_probe_out135_UNCONNECTED; + wire [0:0]NLW_inst_probe_out136_UNCONNECTED; + wire [0:0]NLW_inst_probe_out137_UNCONNECTED; + wire [0:0]NLW_inst_probe_out138_UNCONNECTED; + wire [0:0]NLW_inst_probe_out139_UNCONNECTED; + wire [0:0]NLW_inst_probe_out14_UNCONNECTED; + wire [0:0]NLW_inst_probe_out140_UNCONNECTED; + wire [0:0]NLW_inst_probe_out141_UNCONNECTED; + wire [0:0]NLW_inst_probe_out142_UNCONNECTED; + wire [0:0]NLW_inst_probe_out143_UNCONNECTED; + wire [0:0]NLW_inst_probe_out144_UNCONNECTED; + wire [0:0]NLW_inst_probe_out145_UNCONNECTED; + wire [0:0]NLW_inst_probe_out146_UNCONNECTED; + wire [0:0]NLW_inst_probe_out147_UNCONNECTED; + wire [0:0]NLW_inst_probe_out148_UNCONNECTED; + wire [0:0]NLW_inst_probe_out149_UNCONNECTED; + wire [0:0]NLW_inst_probe_out15_UNCONNECTED; + wire [0:0]NLW_inst_probe_out150_UNCONNECTED; + wire [0:0]NLW_inst_probe_out151_UNCONNECTED; + wire [0:0]NLW_inst_probe_out152_UNCONNECTED; + wire [0:0]NLW_inst_probe_out153_UNCONNECTED; + wire [0:0]NLW_inst_probe_out154_UNCONNECTED; + wire [0:0]NLW_inst_probe_out155_UNCONNECTED; + wire [0:0]NLW_inst_probe_out156_UNCONNECTED; + wire [0:0]NLW_inst_probe_out157_UNCONNECTED; + wire [0:0]NLW_inst_probe_out158_UNCONNECTED; + wire [0:0]NLW_inst_probe_out159_UNCONNECTED; + wire [0:0]NLW_inst_probe_out16_UNCONNECTED; + wire [0:0]NLW_inst_probe_out160_UNCONNECTED; + wire [0:0]NLW_inst_probe_out161_UNCONNECTED; + wire [0:0]NLW_inst_probe_out162_UNCONNECTED; + wire [0:0]NLW_inst_probe_out163_UNCONNECTED; + wire [0:0]NLW_inst_probe_out164_UNCONNECTED; + wire [0:0]NLW_inst_probe_out165_UNCONNECTED; + wire [0:0]NLW_inst_probe_out166_UNCONNECTED; + wire [0:0]NLW_inst_probe_out167_UNCONNECTED; + wire [0:0]NLW_inst_probe_out168_UNCONNECTED; + wire [0:0]NLW_inst_probe_out169_UNCONNECTED; + wire [0:0]NLW_inst_probe_out17_UNCONNECTED; + wire [0:0]NLW_inst_probe_out170_UNCONNECTED; + wire [0:0]NLW_inst_probe_out171_UNCONNECTED; + wire [0:0]NLW_inst_probe_out172_UNCONNECTED; + wire [0:0]NLW_inst_probe_out173_UNCONNECTED; + wire [0:0]NLW_inst_probe_out174_UNCONNECTED; + wire [0:0]NLW_inst_probe_out175_UNCONNECTED; + wire [0:0]NLW_inst_probe_out176_UNCONNECTED; + wire [0:0]NLW_inst_probe_out177_UNCONNECTED; + wire [0:0]NLW_inst_probe_out178_UNCONNECTED; + wire [0:0]NLW_inst_probe_out179_UNCONNECTED; + wire [0:0]NLW_inst_probe_out18_UNCONNECTED; + wire [0:0]NLW_inst_probe_out180_UNCONNECTED; + wire [0:0]NLW_inst_probe_out181_UNCONNECTED; + wire [0:0]NLW_inst_probe_out182_UNCONNECTED; + wire [0:0]NLW_inst_probe_out183_UNCONNECTED; + wire [0:0]NLW_inst_probe_out184_UNCONNECTED; + wire [0:0]NLW_inst_probe_out185_UNCONNECTED; + wire [0:0]NLW_inst_probe_out186_UNCONNECTED; + wire [0:0]NLW_inst_probe_out187_UNCONNECTED; + wire [0:0]NLW_inst_probe_out188_UNCONNECTED; + wire [0:0]NLW_inst_probe_out189_UNCONNECTED; + wire [0:0]NLW_inst_probe_out19_UNCONNECTED; + wire [0:0]NLW_inst_probe_out190_UNCONNECTED; + wire [0:0]NLW_inst_probe_out191_UNCONNECTED; + wire [0:0]NLW_inst_probe_out192_UNCONNECTED; + wire [0:0]NLW_inst_probe_out193_UNCONNECTED; + wire [0:0]NLW_inst_probe_out194_UNCONNECTED; + wire [0:0]NLW_inst_probe_out195_UNCONNECTED; + wire [0:0]NLW_inst_probe_out196_UNCONNECTED; + wire [0:0]NLW_inst_probe_out197_UNCONNECTED; + wire [0:0]NLW_inst_probe_out198_UNCONNECTED; + wire [0:0]NLW_inst_probe_out199_UNCONNECTED; + wire [0:0]NLW_inst_probe_out20_UNCONNECTED; + wire [0:0]NLW_inst_probe_out200_UNCONNECTED; + wire [0:0]NLW_inst_probe_out201_UNCONNECTED; + wire [0:0]NLW_inst_probe_out202_UNCONNECTED; + wire [0:0]NLW_inst_probe_out203_UNCONNECTED; + wire [0:0]NLW_inst_probe_out204_UNCONNECTED; + wire [0:0]NLW_inst_probe_out205_UNCONNECTED; + wire [0:0]NLW_inst_probe_out206_UNCONNECTED; + wire [0:0]NLW_inst_probe_out207_UNCONNECTED; + wire [0:0]NLW_inst_probe_out208_UNCONNECTED; + wire [0:0]NLW_inst_probe_out209_UNCONNECTED; + wire [0:0]NLW_inst_probe_out21_UNCONNECTED; + wire [0:0]NLW_inst_probe_out210_UNCONNECTED; + wire [0:0]NLW_inst_probe_out211_UNCONNECTED; + wire [0:0]NLW_inst_probe_out212_UNCONNECTED; + wire [0:0]NLW_inst_probe_out213_UNCONNECTED; + wire [0:0]NLW_inst_probe_out214_UNCONNECTED; + wire [0:0]NLW_inst_probe_out215_UNCONNECTED; + wire [0:0]NLW_inst_probe_out216_UNCONNECTED; + wire [0:0]NLW_inst_probe_out217_UNCONNECTED; + wire [0:0]NLW_inst_probe_out218_UNCONNECTED; + wire [0:0]NLW_inst_probe_out219_UNCONNECTED; + wire [0:0]NLW_inst_probe_out22_UNCONNECTED; + wire [0:0]NLW_inst_probe_out220_UNCONNECTED; + wire [0:0]NLW_inst_probe_out221_UNCONNECTED; + wire [0:0]NLW_inst_probe_out222_UNCONNECTED; + wire [0:0]NLW_inst_probe_out223_UNCONNECTED; + wire [0:0]NLW_inst_probe_out224_UNCONNECTED; + wire [0:0]NLW_inst_probe_out225_UNCONNECTED; + wire [0:0]NLW_inst_probe_out226_UNCONNECTED; + wire [0:0]NLW_inst_probe_out227_UNCONNECTED; + wire [0:0]NLW_inst_probe_out228_UNCONNECTED; + wire [0:0]NLW_inst_probe_out229_UNCONNECTED; + wire [0:0]NLW_inst_probe_out23_UNCONNECTED; + wire [0:0]NLW_inst_probe_out230_UNCONNECTED; + wire [0:0]NLW_inst_probe_out231_UNCONNECTED; + wire [0:0]NLW_inst_probe_out232_UNCONNECTED; + wire [0:0]NLW_inst_probe_out233_UNCONNECTED; + wire [0:0]NLW_inst_probe_out234_UNCONNECTED; + wire [0:0]NLW_inst_probe_out235_UNCONNECTED; + wire [0:0]NLW_inst_probe_out236_UNCONNECTED; + wire [0:0]NLW_inst_probe_out237_UNCONNECTED; + wire [0:0]NLW_inst_probe_out238_UNCONNECTED; + wire [0:0]NLW_inst_probe_out239_UNCONNECTED; + wire [0:0]NLW_inst_probe_out24_UNCONNECTED; + wire [0:0]NLW_inst_probe_out240_UNCONNECTED; + wire [0:0]NLW_inst_probe_out241_UNCONNECTED; + wire [0:0]NLW_inst_probe_out242_UNCONNECTED; + wire [0:0]NLW_inst_probe_out243_UNCONNECTED; + wire [0:0]NLW_inst_probe_out244_UNCONNECTED; + wire [0:0]NLW_inst_probe_out245_UNCONNECTED; + wire [0:0]NLW_inst_probe_out246_UNCONNECTED; + wire [0:0]NLW_inst_probe_out247_UNCONNECTED; + wire [0:0]NLW_inst_probe_out248_UNCONNECTED; + wire [0:0]NLW_inst_probe_out249_UNCONNECTED; + wire [0:0]NLW_inst_probe_out25_UNCONNECTED; + wire [0:0]NLW_inst_probe_out250_UNCONNECTED; + wire [0:0]NLW_inst_probe_out251_UNCONNECTED; + wire [0:0]NLW_inst_probe_out252_UNCONNECTED; + wire [0:0]NLW_inst_probe_out253_UNCONNECTED; + wire [0:0]NLW_inst_probe_out254_UNCONNECTED; + wire [0:0]NLW_inst_probe_out255_UNCONNECTED; + wire [0:0]NLW_inst_probe_out26_UNCONNECTED; + wire [0:0]NLW_inst_probe_out27_UNCONNECTED; + wire [0:0]NLW_inst_probe_out28_UNCONNECTED; + wire [0:0]NLW_inst_probe_out29_UNCONNECTED; + wire [0:0]NLW_inst_probe_out30_UNCONNECTED; + wire [0:0]NLW_inst_probe_out31_UNCONNECTED; + wire [0:0]NLW_inst_probe_out32_UNCONNECTED; + wire [0:0]NLW_inst_probe_out33_UNCONNECTED; + wire [0:0]NLW_inst_probe_out34_UNCONNECTED; + wire [0:0]NLW_inst_probe_out35_UNCONNECTED; + wire [0:0]NLW_inst_probe_out36_UNCONNECTED; + wire [0:0]NLW_inst_probe_out37_UNCONNECTED; + wire [0:0]NLW_inst_probe_out38_UNCONNECTED; + wire [0:0]NLW_inst_probe_out39_UNCONNECTED; + wire [0:0]NLW_inst_probe_out40_UNCONNECTED; + wire [0:0]NLW_inst_probe_out41_UNCONNECTED; + wire [0:0]NLW_inst_probe_out42_UNCONNECTED; + wire [0:0]NLW_inst_probe_out43_UNCONNECTED; + wire [0:0]NLW_inst_probe_out44_UNCONNECTED; + wire [0:0]NLW_inst_probe_out45_UNCONNECTED; + wire [0:0]NLW_inst_probe_out46_UNCONNECTED; + wire [0:0]NLW_inst_probe_out47_UNCONNECTED; + wire [0:0]NLW_inst_probe_out48_UNCONNECTED; + wire [0:0]NLW_inst_probe_out49_UNCONNECTED; + wire [0:0]NLW_inst_probe_out5_UNCONNECTED; + wire [0:0]NLW_inst_probe_out50_UNCONNECTED; + wire [0:0]NLW_inst_probe_out51_UNCONNECTED; + wire [0:0]NLW_inst_probe_out52_UNCONNECTED; + wire [0:0]NLW_inst_probe_out53_UNCONNECTED; + wire [0:0]NLW_inst_probe_out54_UNCONNECTED; + wire [0:0]NLW_inst_probe_out55_UNCONNECTED; + wire [0:0]NLW_inst_probe_out56_UNCONNECTED; + wire [0:0]NLW_inst_probe_out57_UNCONNECTED; + wire [0:0]NLW_inst_probe_out58_UNCONNECTED; + wire [0:0]NLW_inst_probe_out59_UNCONNECTED; + wire [0:0]NLW_inst_probe_out6_UNCONNECTED; + wire [0:0]NLW_inst_probe_out60_UNCONNECTED; + wire [0:0]NLW_inst_probe_out61_UNCONNECTED; + wire [0:0]NLW_inst_probe_out62_UNCONNECTED; + wire [0:0]NLW_inst_probe_out63_UNCONNECTED; + wire [0:0]NLW_inst_probe_out64_UNCONNECTED; + wire [0:0]NLW_inst_probe_out65_UNCONNECTED; + wire [0:0]NLW_inst_probe_out66_UNCONNECTED; + wire [0:0]NLW_inst_probe_out67_UNCONNECTED; + wire [0:0]NLW_inst_probe_out68_UNCONNECTED; + wire [0:0]NLW_inst_probe_out69_UNCONNECTED; + wire [0:0]NLW_inst_probe_out7_UNCONNECTED; + wire [0:0]NLW_inst_probe_out70_UNCONNECTED; + wire [0:0]NLW_inst_probe_out71_UNCONNECTED; + wire [0:0]NLW_inst_probe_out72_UNCONNECTED; + wire [0:0]NLW_inst_probe_out73_UNCONNECTED; + wire [0:0]NLW_inst_probe_out74_UNCONNECTED; + wire [0:0]NLW_inst_probe_out75_UNCONNECTED; + wire [0:0]NLW_inst_probe_out76_UNCONNECTED; + wire [0:0]NLW_inst_probe_out77_UNCONNECTED; + wire [0:0]NLW_inst_probe_out78_UNCONNECTED; + wire [0:0]NLW_inst_probe_out79_UNCONNECTED; + wire [0:0]NLW_inst_probe_out8_UNCONNECTED; + wire [0:0]NLW_inst_probe_out80_UNCONNECTED; + wire [0:0]NLW_inst_probe_out81_UNCONNECTED; + wire [0:0]NLW_inst_probe_out82_UNCONNECTED; + wire [0:0]NLW_inst_probe_out83_UNCONNECTED; + wire [0:0]NLW_inst_probe_out84_UNCONNECTED; + wire [0:0]NLW_inst_probe_out85_UNCONNECTED; + wire [0:0]NLW_inst_probe_out86_UNCONNECTED; + wire [0:0]NLW_inst_probe_out87_UNCONNECTED; + wire [0:0]NLW_inst_probe_out88_UNCONNECTED; + wire [0:0]NLW_inst_probe_out89_UNCONNECTED; + wire [0:0]NLW_inst_probe_out9_UNCONNECTED; + wire [0:0]NLW_inst_probe_out90_UNCONNECTED; + wire [0:0]NLW_inst_probe_out91_UNCONNECTED; + wire [0:0]NLW_inst_probe_out92_UNCONNECTED; + wire [0:0]NLW_inst_probe_out93_UNCONNECTED; + wire [0:0]NLW_inst_probe_out94_UNCONNECTED; + wire [0:0]NLW_inst_probe_out95_UNCONNECTED; + wire [0:0]NLW_inst_probe_out96_UNCONNECTED; + wire [0:0]NLW_inst_probe_out97_UNCONNECTED; + wire [0:0]NLW_inst_probe_out98_UNCONNECTED; + wire [0:0]NLW_inst_probe_out99_UNCONNECTED; + wire [16:0]NLW_inst_sl_oport0_UNCONNECTED; + + (* C_BUILD_REVISION = "0" *) + (* C_BUS_ADDR_WIDTH = "17" *) + (* C_BUS_DATA_WIDTH = "16" *) + (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) + (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) + (* C_CORE_MAJOR_VER = "2" *) + (* C_CORE_MINOR_ALPHA_VER = "97" *) + (* C_CORE_MINOR_VER = "0" *) + (* C_CORE_TYPE = "2" *) + (* C_CSE_DRV_VER = "1" *) + (* C_EN_PROBE_IN_ACTIVITY = "0" *) + (* C_EN_SYNCHRONIZATION = "1" *) + (* C_MAJOR_VERSION = "2013" *) + (* C_MAX_NUM_PROBE = "256" *) + (* C_MAX_WIDTH_PER_PROBE = "256" *) + (* C_MINOR_VERSION = "1" *) + (* C_NEXT_SLAVE = "0" *) + (* C_NUM_PROBE_IN = "0" *) + (* C_NUM_PROBE_OUT = "5" *) + (* C_PIPE_IFACE = "0" *) + (* C_PROBE_IN0_WIDTH = "1" *) + (* C_PROBE_IN100_WIDTH = "1" *) + (* C_PROBE_IN101_WIDTH = "1" *) + (* C_PROBE_IN102_WIDTH = "1" *) + (* C_PROBE_IN103_WIDTH = "1" *) + (* C_PROBE_IN104_WIDTH = "1" *) + (* C_PROBE_IN105_WIDTH = "1" *) + (* C_PROBE_IN106_WIDTH = "1" *) + (* C_PROBE_IN107_WIDTH = "1" *) + (* C_PROBE_IN108_WIDTH = "1" *) + (* C_PROBE_IN109_WIDTH = "1" *) + (* C_PROBE_IN10_WIDTH = "1" *) + (* C_PROBE_IN110_WIDTH = "1" *) + (* C_PROBE_IN111_WIDTH = "1" *) + (* C_PROBE_IN112_WIDTH = "1" *) + (* C_PROBE_IN113_WIDTH = "1" *) + (* C_PROBE_IN114_WIDTH = "1" *) + (* C_PROBE_IN115_WIDTH = "1" *) + (* C_PROBE_IN116_WIDTH = "1" *) + (* C_PROBE_IN117_WIDTH = "1" *) + (* C_PROBE_IN118_WIDTH = "1" *) + (* C_PROBE_IN119_WIDTH = "1" *) + (* C_PROBE_IN11_WIDTH = "1" *) + (* C_PROBE_IN120_WIDTH = "1" *) + (* C_PROBE_IN121_WIDTH = "1" *) + (* C_PROBE_IN122_WIDTH = "1" *) + (* C_PROBE_IN123_WIDTH = "1" *) + (* C_PROBE_IN124_WIDTH = "1" *) + (* C_PROBE_IN125_WIDTH = "1" *) + (* C_PROBE_IN126_WIDTH = "1" *) + (* C_PROBE_IN127_WIDTH = "1" *) + (* C_PROBE_IN128_WIDTH = "1" *) + (* C_PROBE_IN129_WIDTH = "1" *) + (* C_PROBE_IN12_WIDTH = "1" *) + (* C_PROBE_IN130_WIDTH = "1" *) + (* C_PROBE_IN131_WIDTH = "1" *) + (* C_PROBE_IN132_WIDTH = "1" *) + (* C_PROBE_IN133_WIDTH = "1" *) + (* C_PROBE_IN134_WIDTH = "1" *) + (* C_PROBE_IN135_WIDTH = "1" *) + (* C_PROBE_IN136_WIDTH = "1" *) + (* C_PROBE_IN137_WIDTH = "1" *) + (* C_PROBE_IN138_WIDTH = "1" *) + (* C_PROBE_IN139_WIDTH = "1" *) + (* C_PROBE_IN13_WIDTH = "1" *) + (* C_PROBE_IN140_WIDTH = "1" *) + (* C_PROBE_IN141_WIDTH = "1" *) + (* C_PROBE_IN142_WIDTH = "1" *) + (* C_PROBE_IN143_WIDTH = "1" *) + (* C_PROBE_IN144_WIDTH = "1" *) + (* C_PROBE_IN145_WIDTH = "1" *) + (* C_PROBE_IN146_WIDTH = "1" *) + (* C_PROBE_IN147_WIDTH = "1" *) + (* C_PROBE_IN148_WIDTH = "1" *) + (* C_PROBE_IN149_WIDTH = "1" *) + (* C_PROBE_IN14_WIDTH = "1" *) + (* C_PROBE_IN150_WIDTH = "1" *) + (* C_PROBE_IN151_WIDTH = "1" *) + (* C_PROBE_IN152_WIDTH = "1" *) + (* C_PROBE_IN153_WIDTH = "1" *) + (* C_PROBE_IN154_WIDTH = "1" *) + (* C_PROBE_IN155_WIDTH = "1" *) + (* C_PROBE_IN156_WIDTH = "1" *) + (* C_PROBE_IN157_WIDTH = "1" *) + (* C_PROBE_IN158_WIDTH = "1" *) + (* C_PROBE_IN159_WIDTH = "1" *) + (* C_PROBE_IN15_WIDTH = "1" *) + (* C_PROBE_IN160_WIDTH = "1" *) + (* C_PROBE_IN161_WIDTH = "1" *) + (* C_PROBE_IN162_WIDTH = "1" *) + (* C_PROBE_IN163_WIDTH = "1" *) + (* C_PROBE_IN164_WIDTH = "1" *) + (* C_PROBE_IN165_WIDTH = "1" *) + (* C_PROBE_IN166_WIDTH = "1" *) + (* C_PROBE_IN167_WIDTH = "1" *) + (* C_PROBE_IN168_WIDTH = "1" *) + (* C_PROBE_IN169_WIDTH = "1" *) + (* C_PROBE_IN16_WIDTH = "1" *) + (* C_PROBE_IN170_WIDTH = "1" *) + (* C_PROBE_IN171_WIDTH = "1" *) + (* C_PROBE_IN172_WIDTH = "1" *) + (* C_PROBE_IN173_WIDTH = "1" *) + (* C_PROBE_IN174_WIDTH = "1" *) + (* C_PROBE_IN175_WIDTH = "1" *) + (* C_PROBE_IN176_WIDTH = "1" *) + (* C_PROBE_IN177_WIDTH = "1" *) + (* C_PROBE_IN178_WIDTH = "1" *) + (* C_PROBE_IN179_WIDTH = "1" *) + (* C_PROBE_IN17_WIDTH = "1" *) + (* C_PROBE_IN180_WIDTH = "1" *) + (* C_PROBE_IN181_WIDTH = "1" *) + (* C_PROBE_IN182_WIDTH = "1" *) + (* C_PROBE_IN183_WIDTH = "1" *) + (* C_PROBE_IN184_WIDTH = "1" *) + (* C_PROBE_IN185_WIDTH = "1" *) + (* C_PROBE_IN186_WIDTH = "1" *) + (* C_PROBE_IN187_WIDTH = "1" *) + (* C_PROBE_IN188_WIDTH = "1" *) + (* C_PROBE_IN189_WIDTH = "1" *) + (* C_PROBE_IN18_WIDTH = "1" *) + (* C_PROBE_IN190_WIDTH = "1" *) + (* C_PROBE_IN191_WIDTH = "1" *) + (* C_PROBE_IN192_WIDTH = "1" *) + (* C_PROBE_IN193_WIDTH = "1" *) + (* C_PROBE_IN194_WIDTH = "1" *) + (* C_PROBE_IN195_WIDTH = "1" *) + (* C_PROBE_IN196_WIDTH = "1" *) + (* C_PROBE_IN197_WIDTH = "1" *) + (* C_PROBE_IN198_WIDTH = "1" *) + (* C_PROBE_IN199_WIDTH = "1" *) + (* C_PROBE_IN19_WIDTH = "1" *) + (* C_PROBE_IN1_WIDTH = "1" *) + (* C_PROBE_IN200_WIDTH = "1" *) + (* C_PROBE_IN201_WIDTH = "1" *) + (* C_PROBE_IN202_WIDTH = "1" *) + (* C_PROBE_IN203_WIDTH = "1" *) + (* C_PROBE_IN204_WIDTH = "1" *) + (* C_PROBE_IN205_WIDTH = "1" *) + (* C_PROBE_IN206_WIDTH = "1" *) + (* C_PROBE_IN207_WIDTH = "1" *) + (* C_PROBE_IN208_WIDTH = "1" *) + (* C_PROBE_IN209_WIDTH = "1" *) + (* C_PROBE_IN20_WIDTH = "1" *) + (* C_PROBE_IN210_WIDTH = "1" *) + (* C_PROBE_IN211_WIDTH = "1" *) + (* C_PROBE_IN212_WIDTH = "1" *) + (* C_PROBE_IN213_WIDTH = "1" *) + (* C_PROBE_IN214_WIDTH = "1" *) + (* C_PROBE_IN215_WIDTH = "1" *) + (* C_PROBE_IN216_WIDTH = "1" *) + (* C_PROBE_IN217_WIDTH = "1" *) + (* C_PROBE_IN218_WIDTH = "1" *) + (* C_PROBE_IN219_WIDTH = "1" *) + (* C_PROBE_IN21_WIDTH = "1" *) + (* C_PROBE_IN220_WIDTH = "1" *) + (* C_PROBE_IN221_WIDTH = "1" *) + (* C_PROBE_IN222_WIDTH = "1" *) + (* C_PROBE_IN223_WIDTH = "1" *) + (* C_PROBE_IN224_WIDTH = "1" *) + (* C_PROBE_IN225_WIDTH = "1" *) + (* C_PROBE_IN226_WIDTH = "1" *) + (* C_PROBE_IN227_WIDTH = "1" *) + (* C_PROBE_IN228_WIDTH = "1" *) + (* C_PROBE_IN229_WIDTH = "1" *) + (* C_PROBE_IN22_WIDTH = "1" *) + (* C_PROBE_IN230_WIDTH = "1" *) + (* C_PROBE_IN231_WIDTH = "1" *) + (* C_PROBE_IN232_WIDTH = "1" *) + (* C_PROBE_IN233_WIDTH = "1" *) + (* C_PROBE_IN234_WIDTH = "1" *) + (* C_PROBE_IN235_WIDTH = "1" *) + (* C_PROBE_IN236_WIDTH = "1" *) + (* C_PROBE_IN237_WIDTH = "1" *) + (* C_PROBE_IN238_WIDTH = "1" *) + (* C_PROBE_IN239_WIDTH = "1" *) + (* C_PROBE_IN23_WIDTH = "1" *) + (* C_PROBE_IN240_WIDTH = "1" *) + (* C_PROBE_IN241_WIDTH = "1" *) + (* C_PROBE_IN242_WIDTH = "1" *) + (* C_PROBE_IN243_WIDTH = "1" *) + (* C_PROBE_IN244_WIDTH = "1" *) + (* C_PROBE_IN245_WIDTH = "1" *) + (* C_PROBE_IN246_WIDTH = "1" *) + (* C_PROBE_IN247_WIDTH = "1" *) + (* C_PROBE_IN248_WIDTH = "1" *) + (* C_PROBE_IN249_WIDTH = "1" *) + (* C_PROBE_IN24_WIDTH = "1" *) + (* C_PROBE_IN250_WIDTH = "1" *) + (* C_PROBE_IN251_WIDTH = "1" *) + (* C_PROBE_IN252_WIDTH = "1" *) + (* C_PROBE_IN253_WIDTH = "1" *) + (* C_PROBE_IN254_WIDTH = "1" *) + (* C_PROBE_IN255_WIDTH = "1" *) + (* C_PROBE_IN25_WIDTH = "1" *) + (* C_PROBE_IN26_WIDTH = "1" *) + (* C_PROBE_IN27_WIDTH = "1" *) + (* C_PROBE_IN28_WIDTH = "1" *) + (* C_PROBE_IN29_WIDTH = "1" *) + (* C_PROBE_IN2_WIDTH = "1" *) + (* C_PROBE_IN30_WIDTH = "1" *) + (* C_PROBE_IN31_WIDTH = "1" *) + (* C_PROBE_IN32_WIDTH = "1" *) + (* C_PROBE_IN33_WIDTH = "1" *) + (* C_PROBE_IN34_WIDTH = "1" *) + (* C_PROBE_IN35_WIDTH = "1" *) + (* C_PROBE_IN36_WIDTH = "1" *) + (* C_PROBE_IN37_WIDTH = "1" *) + (* C_PROBE_IN38_WIDTH = "1" *) + (* C_PROBE_IN39_WIDTH = "1" *) + (* C_PROBE_IN3_WIDTH = "1" *) + (* C_PROBE_IN40_WIDTH = "1" *) + (* C_PROBE_IN41_WIDTH = "1" *) + (* C_PROBE_IN42_WIDTH = "1" *) + (* C_PROBE_IN43_WIDTH = "1" *) + (* C_PROBE_IN44_WIDTH = "1" *) + (* C_PROBE_IN45_WIDTH = "1" *) + (* C_PROBE_IN46_WIDTH = "1" *) + (* C_PROBE_IN47_WIDTH = "1" *) + (* C_PROBE_IN48_WIDTH = "1" *) + (* C_PROBE_IN49_WIDTH = "1" *) + (* C_PROBE_IN4_WIDTH = "1" *) + (* C_PROBE_IN50_WIDTH = "1" *) + (* C_PROBE_IN51_WIDTH = "1" *) + (* C_PROBE_IN52_WIDTH = "1" *) + (* C_PROBE_IN53_WIDTH = "1" *) + (* C_PROBE_IN54_WIDTH = "1" *) + (* C_PROBE_IN55_WIDTH = "1" *) + (* C_PROBE_IN56_WIDTH = "1" *) + (* C_PROBE_IN57_WIDTH = "1" *) + (* C_PROBE_IN58_WIDTH = "1" *) + (* C_PROBE_IN59_WIDTH = "1" *) + (* C_PROBE_IN5_WIDTH = "1" *) + (* C_PROBE_IN60_WIDTH = "1" *) + (* C_PROBE_IN61_WIDTH = "1" *) + (* C_PROBE_IN62_WIDTH = "1" *) + (* C_PROBE_IN63_WIDTH = "1" *) + (* C_PROBE_IN64_WIDTH = "1" *) + (* C_PROBE_IN65_WIDTH = "1" *) + (* C_PROBE_IN66_WIDTH = "1" *) + (* C_PROBE_IN67_WIDTH = "1" *) + (* C_PROBE_IN68_WIDTH = "1" *) + (* C_PROBE_IN69_WIDTH = "1" *) + (* C_PROBE_IN6_WIDTH = "1" *) + (* C_PROBE_IN70_WIDTH = "1" *) + (* C_PROBE_IN71_WIDTH = "1" *) + (* C_PROBE_IN72_WIDTH = "1" *) + (* C_PROBE_IN73_WIDTH = "1" *) + (* C_PROBE_IN74_WIDTH = "1" *) + (* C_PROBE_IN75_WIDTH = "1" *) + (* C_PROBE_IN76_WIDTH = "1" *) + (* C_PROBE_IN77_WIDTH = "1" *) + (* C_PROBE_IN78_WIDTH = "1" *) + (* C_PROBE_IN79_WIDTH = "1" *) + (* C_PROBE_IN7_WIDTH = "1" *) + (* C_PROBE_IN80_WIDTH = "1" *) + (* C_PROBE_IN81_WIDTH = "1" *) + (* C_PROBE_IN82_WIDTH = "1" *) + (* C_PROBE_IN83_WIDTH = "1" *) + (* C_PROBE_IN84_WIDTH = "1" *) + (* C_PROBE_IN85_WIDTH = "1" *) + (* C_PROBE_IN86_WIDTH = "1" *) + (* C_PROBE_IN87_WIDTH = "1" *) + (* C_PROBE_IN88_WIDTH = "1" *) + (* C_PROBE_IN89_WIDTH = "1" *) + (* C_PROBE_IN8_WIDTH = "1" *) + (* C_PROBE_IN90_WIDTH = "1" *) + (* C_PROBE_IN91_WIDTH = "1" *) + (* C_PROBE_IN92_WIDTH = "1" *) + (* C_PROBE_IN93_WIDTH = "1" *) + (* C_PROBE_IN94_WIDTH = "1" *) + (* C_PROBE_IN95_WIDTH = "1" *) + (* C_PROBE_IN96_WIDTH = "1" *) + (* C_PROBE_IN97_WIDTH = "1" *) + (* C_PROBE_IN98_WIDTH = "1" *) + (* C_PROBE_IN99_WIDTH = "1" *) + (* C_PROBE_IN9_WIDTH = "1" *) + (* C_PROBE_OUT0_INIT_VAL = "2'b10" *) + (* C_PROBE_OUT0_WIDTH = "2" *) + (* C_PROBE_OUT100_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT100_WIDTH = "1" *) + (* C_PROBE_OUT101_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT101_WIDTH = "1" *) + (* C_PROBE_OUT102_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT102_WIDTH = "1" *) + (* C_PROBE_OUT103_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT103_WIDTH = "1" *) + (* C_PROBE_OUT104_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT104_WIDTH = "1" *) + (* C_PROBE_OUT105_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT105_WIDTH = "1" *) + (* C_PROBE_OUT106_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT106_WIDTH = "1" *) + (* C_PROBE_OUT107_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT107_WIDTH = "1" *) + (* C_PROBE_OUT108_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT108_WIDTH = "1" *) + (* C_PROBE_OUT109_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT109_WIDTH = "1" *) + (* C_PROBE_OUT10_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT10_WIDTH = "1" *) + (* C_PROBE_OUT110_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT110_WIDTH = "1" *) + (* C_PROBE_OUT111_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT111_WIDTH = "1" *) + (* C_PROBE_OUT112_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT112_WIDTH = "1" *) + (* C_PROBE_OUT113_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT113_WIDTH = "1" *) + (* C_PROBE_OUT114_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT114_WIDTH = "1" *) + (* C_PROBE_OUT115_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT115_WIDTH = "1" *) + (* C_PROBE_OUT116_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT116_WIDTH = "1" *) + (* C_PROBE_OUT117_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT117_WIDTH = "1" *) + (* C_PROBE_OUT118_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT118_WIDTH = "1" *) + (* C_PROBE_OUT119_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT119_WIDTH = "1" *) + (* C_PROBE_OUT11_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT11_WIDTH = "1" *) + (* C_PROBE_OUT120_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT120_WIDTH = "1" *) + (* C_PROBE_OUT121_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT121_WIDTH = "1" *) + (* C_PROBE_OUT122_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT122_WIDTH = "1" *) + (* C_PROBE_OUT123_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT123_WIDTH = "1" *) + (* C_PROBE_OUT124_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT124_WIDTH = "1" *) + (* C_PROBE_OUT125_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT125_WIDTH = "1" *) + (* C_PROBE_OUT126_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT126_WIDTH = "1" *) + (* C_PROBE_OUT127_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT127_WIDTH = "1" *) + (* C_PROBE_OUT128_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT128_WIDTH = "1" *) + (* C_PROBE_OUT129_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT129_WIDTH = "1" *) + (* C_PROBE_OUT12_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT12_WIDTH = "1" *) + (* C_PROBE_OUT130_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT130_WIDTH = "1" *) + (* C_PROBE_OUT131_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT131_WIDTH = "1" *) + (* C_PROBE_OUT132_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT132_WIDTH = "1" *) + (* C_PROBE_OUT133_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT133_WIDTH = "1" *) + (* C_PROBE_OUT134_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT134_WIDTH = "1" *) + (* C_PROBE_OUT135_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT135_WIDTH = "1" *) + (* C_PROBE_OUT136_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT136_WIDTH = "1" *) + (* C_PROBE_OUT137_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT137_WIDTH = "1" *) + (* C_PROBE_OUT138_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT138_WIDTH = "1" *) + (* C_PROBE_OUT139_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT139_WIDTH = "1" *) + (* C_PROBE_OUT13_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT13_WIDTH = "1" *) + (* C_PROBE_OUT140_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT140_WIDTH = "1" *) + (* C_PROBE_OUT141_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT141_WIDTH = "1" *) + (* C_PROBE_OUT142_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT142_WIDTH = "1" *) + (* C_PROBE_OUT143_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT143_WIDTH = "1" *) + (* C_PROBE_OUT144_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT144_WIDTH = "1" *) + (* C_PROBE_OUT145_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT145_WIDTH = "1" *) + (* C_PROBE_OUT146_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT146_WIDTH = "1" *) + (* C_PROBE_OUT147_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT147_WIDTH = "1" *) + (* C_PROBE_OUT148_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT148_WIDTH = "1" *) + (* C_PROBE_OUT149_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT149_WIDTH = "1" *) + (* C_PROBE_OUT14_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT14_WIDTH = "1" *) + (* C_PROBE_OUT150_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT150_WIDTH = "1" *) + (* C_PROBE_OUT151_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT151_WIDTH = "1" *) + (* C_PROBE_OUT152_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT152_WIDTH = "1" *) + (* C_PROBE_OUT153_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT153_WIDTH = "1" *) + (* C_PROBE_OUT154_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT154_WIDTH = "1" *) + (* C_PROBE_OUT155_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT155_WIDTH = "1" *) + (* C_PROBE_OUT156_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT156_WIDTH = "1" *) + (* C_PROBE_OUT157_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT157_WIDTH = "1" *) + (* C_PROBE_OUT158_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT158_WIDTH = "1" *) + (* C_PROBE_OUT159_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT159_WIDTH = "1" *) + (* C_PROBE_OUT15_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT15_WIDTH = "1" *) + (* C_PROBE_OUT160_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT160_WIDTH = "1" *) + (* C_PROBE_OUT161_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT161_WIDTH = "1" *) + (* C_PROBE_OUT162_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT162_WIDTH = "1" *) + (* C_PROBE_OUT163_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT163_WIDTH = "1" *) + (* C_PROBE_OUT164_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT164_WIDTH = "1" *) + (* C_PROBE_OUT165_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT165_WIDTH = "1" *) + (* C_PROBE_OUT166_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT166_WIDTH = "1" *) + (* C_PROBE_OUT167_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT167_WIDTH = "1" *) + (* C_PROBE_OUT168_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT168_WIDTH = "1" *) + (* C_PROBE_OUT169_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT169_WIDTH = "1" *) + (* C_PROBE_OUT16_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT16_WIDTH = "1" *) + (* C_PROBE_OUT170_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT170_WIDTH = "1" *) + (* C_PROBE_OUT171_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT171_WIDTH = "1" *) + (* C_PROBE_OUT172_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT172_WIDTH = "1" *) + (* C_PROBE_OUT173_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT173_WIDTH = "1" *) + (* C_PROBE_OUT174_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT174_WIDTH = "1" *) + (* C_PROBE_OUT175_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT175_WIDTH = "1" *) + (* C_PROBE_OUT176_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT176_WIDTH = "1" *) + (* C_PROBE_OUT177_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT177_WIDTH = "1" *) + (* C_PROBE_OUT178_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT178_WIDTH = "1" *) + (* C_PROBE_OUT179_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT179_WIDTH = "1" *) + (* C_PROBE_OUT17_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT17_WIDTH = "1" *) + (* C_PROBE_OUT180_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT180_WIDTH = "1" *) + (* C_PROBE_OUT181_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT181_WIDTH = "1" *) + (* C_PROBE_OUT182_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT182_WIDTH = "1" *) + (* C_PROBE_OUT183_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT183_WIDTH = "1" *) + (* C_PROBE_OUT184_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT184_WIDTH = "1" *) + (* C_PROBE_OUT185_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT185_WIDTH = "1" *) + (* C_PROBE_OUT186_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT186_WIDTH = "1" *) + (* C_PROBE_OUT187_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT187_WIDTH = "1" *) + (* C_PROBE_OUT188_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT188_WIDTH = "1" *) + (* C_PROBE_OUT189_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT189_WIDTH = "1" *) + (* C_PROBE_OUT18_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT18_WIDTH = "1" *) + (* C_PROBE_OUT190_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT190_WIDTH = "1" *) + (* C_PROBE_OUT191_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT191_WIDTH = "1" *) + (* C_PROBE_OUT192_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT192_WIDTH = "1" *) + (* C_PROBE_OUT193_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT193_WIDTH = "1" *) + (* C_PROBE_OUT194_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT194_WIDTH = "1" *) + (* C_PROBE_OUT195_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT195_WIDTH = "1" *) + (* C_PROBE_OUT196_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT196_WIDTH = "1" *) + (* C_PROBE_OUT197_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT197_WIDTH = "1" *) + (* C_PROBE_OUT198_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT198_WIDTH = "1" *) + (* C_PROBE_OUT199_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT199_WIDTH = "1" *) + (* C_PROBE_OUT19_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT19_WIDTH = "1" *) + (* C_PROBE_OUT1_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT1_WIDTH = "1" *) + (* C_PROBE_OUT200_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT200_WIDTH = "1" *) + (* C_PROBE_OUT201_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT201_WIDTH = "1" *) + (* C_PROBE_OUT202_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT202_WIDTH = "1" *) + (* C_PROBE_OUT203_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT203_WIDTH = "1" *) + (* C_PROBE_OUT204_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT204_WIDTH = "1" *) + (* C_PROBE_OUT205_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT205_WIDTH = "1" *) + (* C_PROBE_OUT206_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT206_WIDTH = "1" *) + (* C_PROBE_OUT207_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT207_WIDTH = "1" *) + (* C_PROBE_OUT208_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT208_WIDTH = "1" *) + (* C_PROBE_OUT209_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT209_WIDTH = "1" *) + (* C_PROBE_OUT20_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT20_WIDTH = "1" *) + (* C_PROBE_OUT210_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT210_WIDTH = "1" *) + (* C_PROBE_OUT211_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT211_WIDTH = "1" *) + (* C_PROBE_OUT212_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT212_WIDTH = "1" *) + (* C_PROBE_OUT213_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT213_WIDTH = "1" *) + (* C_PROBE_OUT214_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT214_WIDTH = "1" *) + (* C_PROBE_OUT215_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT215_WIDTH = "1" *) + (* C_PROBE_OUT216_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT216_WIDTH = "1" *) + (* C_PROBE_OUT217_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT217_WIDTH = "1" *) + (* C_PROBE_OUT218_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT218_WIDTH = "1" *) + (* C_PROBE_OUT219_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT219_WIDTH = "1" *) + (* C_PROBE_OUT21_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT21_WIDTH = "1" *) + (* C_PROBE_OUT220_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT220_WIDTH = "1" *) + (* C_PROBE_OUT221_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT221_WIDTH = "1" *) + (* C_PROBE_OUT222_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT222_WIDTH = "1" *) + (* C_PROBE_OUT223_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT223_WIDTH = "1" *) + (* C_PROBE_OUT224_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT224_WIDTH = "1" *) + (* C_PROBE_OUT225_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT225_WIDTH = "1" *) + (* C_PROBE_OUT226_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT226_WIDTH = "1" *) + (* C_PROBE_OUT227_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT227_WIDTH = "1" *) + (* C_PROBE_OUT228_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT228_WIDTH = "1" *) + (* C_PROBE_OUT229_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT229_WIDTH = "1" *) + (* C_PROBE_OUT22_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT22_WIDTH = "1" *) + (* C_PROBE_OUT230_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT230_WIDTH = "1" *) + (* C_PROBE_OUT231_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT231_WIDTH = "1" *) + (* C_PROBE_OUT232_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT232_WIDTH = "1" *) + (* C_PROBE_OUT233_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT233_WIDTH = "1" *) + (* C_PROBE_OUT234_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT234_WIDTH = "1" *) + (* C_PROBE_OUT235_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT235_WIDTH = "1" *) + (* C_PROBE_OUT236_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT236_WIDTH = "1" *) + (* C_PROBE_OUT237_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT237_WIDTH = "1" *) + (* C_PROBE_OUT238_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT238_WIDTH = "1" *) + (* C_PROBE_OUT239_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT239_WIDTH = "1" *) + (* C_PROBE_OUT23_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT23_WIDTH = "1" *) + (* C_PROBE_OUT240_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT240_WIDTH = "1" *) + (* C_PROBE_OUT241_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT241_WIDTH = "1" *) + (* C_PROBE_OUT242_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT242_WIDTH = "1" *) + (* C_PROBE_OUT243_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT243_WIDTH = "1" *) + (* C_PROBE_OUT244_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT244_WIDTH = "1" *) + (* C_PROBE_OUT245_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT245_WIDTH = "1" *) + (* C_PROBE_OUT246_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT246_WIDTH = "1" *) + (* C_PROBE_OUT247_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT247_WIDTH = "1" *) + (* C_PROBE_OUT248_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT248_WIDTH = "1" *) + (* C_PROBE_OUT249_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT249_WIDTH = "1" *) + (* C_PROBE_OUT24_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT24_WIDTH = "1" *) + (* C_PROBE_OUT250_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT250_WIDTH = "1" *) + (* C_PROBE_OUT251_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT251_WIDTH = "1" *) + (* C_PROBE_OUT252_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT252_WIDTH = "1" *) + (* C_PROBE_OUT253_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT253_WIDTH = "1" *) + (* C_PROBE_OUT254_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT254_WIDTH = "1" *) + (* C_PROBE_OUT255_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT255_WIDTH = "1" *) + (* C_PROBE_OUT25_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT25_WIDTH = "1" *) + (* C_PROBE_OUT26_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT26_WIDTH = "1" *) + (* C_PROBE_OUT27_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT27_WIDTH = "1" *) + (* C_PROBE_OUT28_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT28_WIDTH = "1" *) + (* C_PROBE_OUT29_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT29_WIDTH = "1" *) + (* C_PROBE_OUT2_INIT_VAL = "32'b00000000000000000000000000000000" *) + (* C_PROBE_OUT2_WIDTH = "32" *) + (* C_PROBE_OUT30_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT30_WIDTH = "1" *) + (* C_PROBE_OUT31_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT31_WIDTH = "1" *) + (* C_PROBE_OUT32_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT32_WIDTH = "1" *) + (* C_PROBE_OUT33_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT33_WIDTH = "1" *) + (* C_PROBE_OUT34_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT34_WIDTH = "1" *) + (* C_PROBE_OUT35_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT35_WIDTH = "1" *) + (* C_PROBE_OUT36_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT36_WIDTH = "1" *) + (* C_PROBE_OUT37_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT37_WIDTH = "1" *) + (* C_PROBE_OUT38_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT38_WIDTH = "1" *) + (* C_PROBE_OUT39_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT39_WIDTH = "1" *) + (* C_PROBE_OUT3_INIT_VAL = "2'b11" *) + (* C_PROBE_OUT3_WIDTH = "2" *) + (* C_PROBE_OUT40_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT40_WIDTH = "1" *) + (* C_PROBE_OUT41_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT41_WIDTH = "1" *) + (* C_PROBE_OUT42_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT42_WIDTH = "1" *) + (* C_PROBE_OUT43_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT43_WIDTH = "1" *) + (* C_PROBE_OUT44_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT44_WIDTH = "1" *) + (* C_PROBE_OUT45_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT45_WIDTH = "1" *) + (* C_PROBE_OUT46_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT46_WIDTH = "1" *) + (* C_PROBE_OUT47_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT47_WIDTH = "1" *) + (* C_PROBE_OUT48_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT48_WIDTH = "1" *) + (* C_PROBE_OUT49_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT49_WIDTH = "1" *) + (* C_PROBE_OUT4_INIT_VAL = "4'b0000" *) + (* C_PROBE_OUT4_WIDTH = "4" *) + (* C_PROBE_OUT50_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT50_WIDTH = "1" *) + (* C_PROBE_OUT51_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT51_WIDTH = "1" *) + (* C_PROBE_OUT52_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT52_WIDTH = "1" *) + (* C_PROBE_OUT53_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT53_WIDTH = "1" *) + (* C_PROBE_OUT54_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT54_WIDTH = "1" *) + (* C_PROBE_OUT55_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT55_WIDTH = "1" *) + (* C_PROBE_OUT56_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT56_WIDTH = "1" *) + (* C_PROBE_OUT57_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT57_WIDTH = "1" *) + (* C_PROBE_OUT58_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT58_WIDTH = "1" *) + (* C_PROBE_OUT59_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT59_WIDTH = "1" *) + (* C_PROBE_OUT5_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT5_WIDTH = "1" *) + (* C_PROBE_OUT60_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT60_WIDTH = "1" *) + (* C_PROBE_OUT61_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT61_WIDTH = "1" *) + (* C_PROBE_OUT62_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT62_WIDTH = "1" *) + (* C_PROBE_OUT63_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT63_WIDTH = "1" *) + (* C_PROBE_OUT64_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT64_WIDTH = "1" *) + (* C_PROBE_OUT65_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT65_WIDTH = "1" *) + (* C_PROBE_OUT66_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT66_WIDTH = "1" *) + (* C_PROBE_OUT67_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT67_WIDTH = "1" *) + (* C_PROBE_OUT68_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT68_WIDTH = "1" *) + (* C_PROBE_OUT69_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT69_WIDTH = "1" *) + (* C_PROBE_OUT6_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT6_WIDTH = "1" *) + (* C_PROBE_OUT70_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT70_WIDTH = "1" *) + (* C_PROBE_OUT71_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT71_WIDTH = "1" *) + (* C_PROBE_OUT72_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT72_WIDTH = "1" *) + (* C_PROBE_OUT73_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT73_WIDTH = "1" *) + (* C_PROBE_OUT74_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT74_WIDTH = "1" *) + (* C_PROBE_OUT75_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT75_WIDTH = "1" *) + (* C_PROBE_OUT76_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT76_WIDTH = "1" *) + (* C_PROBE_OUT77_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT77_WIDTH = "1" *) + (* C_PROBE_OUT78_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT78_WIDTH = "1" *) + (* C_PROBE_OUT79_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT79_WIDTH = "1" *) + (* C_PROBE_OUT7_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT7_WIDTH = "1" *) + (* C_PROBE_OUT80_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT80_WIDTH = "1" *) + (* C_PROBE_OUT81_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT81_WIDTH = "1" *) + (* C_PROBE_OUT82_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT82_WIDTH = "1" *) + (* C_PROBE_OUT83_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT83_WIDTH = "1" *) + (* C_PROBE_OUT84_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT84_WIDTH = "1" *) + (* C_PROBE_OUT85_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT85_WIDTH = "1" *) + (* C_PROBE_OUT86_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT86_WIDTH = "1" *) + (* C_PROBE_OUT87_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT87_WIDTH = "1" *) + (* C_PROBE_OUT88_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT88_WIDTH = "1" *) + (* C_PROBE_OUT89_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT89_WIDTH = "1" *) + (* C_PROBE_OUT8_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT8_WIDTH = "1" *) + (* C_PROBE_OUT90_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT90_WIDTH = "1" *) + (* C_PROBE_OUT91_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT91_WIDTH = "1" *) + (* C_PROBE_OUT92_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT92_WIDTH = "1" *) + (* C_PROBE_OUT93_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT93_WIDTH = "1" *) + (* C_PROBE_OUT94_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT94_WIDTH = "1" *) + (* C_PROBE_OUT95_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT95_WIDTH = "1" *) + (* C_PROBE_OUT96_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT96_WIDTH = "1" *) + (* C_PROBE_OUT97_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT97_WIDTH = "1" *) + (* C_PROBE_OUT98_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT98_WIDTH = "1" *) + (* C_PROBE_OUT99_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT99_WIDTH = "1" *) + (* C_PROBE_OUT9_INIT_VAL = "1'b0" *) + (* C_PROBE_OUT9_WIDTH = "1" *) + (* C_USE_TEST_REG = "1" *) + (* C_XDEVICEFAMILY = "kintex7" *) + (* C_XLNX_HW_PROBE_INFO = "DEFAULT" *) + (* C_XSDB_SLAVE_TYPE = "33" *) + (* DONT_TOUCH *) + (* DowngradeIPIdentifiedWarnings = "yes" *) + (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000101110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000010001000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000010001001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000010001010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000010001011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000010001100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000010001101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000010001110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000010001111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000010010000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000010010001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000101111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000010010010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000010010011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000010010100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000010010101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000010010110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000010010111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000010011000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000010011001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000010011010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000010011011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000110000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000010011100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000010011101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000010011110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000010011111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000010100000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000010100001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000010100010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000010100011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010100100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010100101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000110001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010100110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010100111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010101000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010101001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010101010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010101011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010101100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010101101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010101110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010101111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000110010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010110000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010110001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010110010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010110011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010110100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010110101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010110110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010110111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010111000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010111001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000110011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010111010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010111011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010111100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010111101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010111110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010111111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000011000000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000011000001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000011000010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000011000011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000110100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000011000100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000011000101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000011000110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000011000111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000011001000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000011001001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000011001010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000011001011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000011001100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000011001101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000110101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000011001110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000011001111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000011010000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000011010001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000011010010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000011010011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000011010100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000011010101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000011010110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000011010111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000110110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000011011000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000011011001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000011011010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000011011011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000011011100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000011011101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000011011110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000011011111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000011100000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000011100001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000110111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000011100010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000011100011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011100100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011100101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011100110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011100111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011101000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011101001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011101010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011101011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000100010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000111000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011101100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011101101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011101110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011101111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011110000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011110001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011110010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011110011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011110100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011110101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000111001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011110110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011110111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011111000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011111001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011111010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011111011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011111100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011111101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011111110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011111111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000111010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000100000000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000100000001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000100000010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000100000011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000100000100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000100000101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000100000110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000100000111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000100001000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000100001001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000111011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000100001010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000100001011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000100001100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000100001101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000100001110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000100001111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000100010000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000100010001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000100010010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000100010011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000111100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000100010100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000100010101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000100010110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000100010111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000100011000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000100011001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000100011010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000100011011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000100011100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000100011101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000111101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000100011110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000100011111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000100100000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000100100001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000100100010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000100100011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000111110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000111111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000001000000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000001000001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000100100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000001000010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000001000011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000001000100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000001000101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000001000110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000001000111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000001001000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000001001001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000001001010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000001001011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000101000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000001001100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000001001101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000001001110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000001001111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000001010000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000001010001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000001010010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000001010011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000001010100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000001010101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000101001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000001010110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000001010111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000001011000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000001011001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000001011010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000001011011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000001011100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000001011101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000001011110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000001011111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000101010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000001100000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000001100001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000001100010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000001100011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001100100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001100101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001100110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001100111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001101000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001101001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000101011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001101010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001101011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001101100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001101101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001101110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001101111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001110000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001110001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001110010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001110011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000101100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001110100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001110101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001110110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001110111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001111000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001111001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001111010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001111011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001111100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001111101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000101101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001111110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001111111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000010000000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000010000001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000010000010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000010000011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000010000100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000010000101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000010000110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000010000111" *) + (* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *) + (* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000010" *) + (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000101110" *) + (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000010001000" *) + (* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000010001001" *) + (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000010001010" *) + (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000010001011" *) + (* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000010001100" *) + (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000010001101" *) + (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000010001110" *) + (* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000010001111" *) + (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000010010000" *) + (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000010010001" *) + (* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000101111" *) + (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000010010010" *) + (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000010010011" *) + (* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000010010100" *) + (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000010010101" *) + (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000010010110" *) + (* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000010010111" *) + (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000010011000" *) + (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000010011001" *) + (* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000010011010" *) + (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000010011011" *) + (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000110000" *) + (* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000010011100" *) + (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000010011101" *) + (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000010011110" *) + (* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000010011111" *) + (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000010100000" *) + (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000010100001" *) + (* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000010100010" *) + (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000010100011" *) + (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010100100" *) + (* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010100101" *) + (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000110001" *) + (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010100110" *) + (* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010100111" *) + (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010101000" *) + (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010101001" *) + (* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010101010" *) + (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010101011" *) + (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010101100" *) + (* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010101101" *) + (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010101110" *) + (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010101111" *) + (* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000110010" *) + (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010110000" *) + (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010110001" *) + (* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010110010" *) + (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010110011" *) + (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010110100" *) + (* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010110101" *) + (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010110110" *) + (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010110111" *) + (* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010111000" *) + (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010111001" *) + (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000110011" *) + (* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010111010" *) + (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010111011" *) + (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010111100" *) + (* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010111101" *) + (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010111110" *) + (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010111111" *) + (* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000011000000" *) + (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000011000001" *) + (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000011000010" *) + (* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000011000011" *) + (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000110100" *) + (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000011000100" *) + (* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000011000101" *) + (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000011000110" *) + (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000011000111" *) + (* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000011001000" *) + (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000011001001" *) + (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000011001010" *) + (* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000011001011" *) + (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000011001100" *) + (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000011001101" *) + (* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000110101" *) + (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000011001110" *) + (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000011001111" *) + (* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000011010000" *) + (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000011010001" *) + (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000011010010" *) + (* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000011010011" *) + (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000011010100" *) + (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000011010101" *) + (* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000011010110" *) + (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000011010111" *) + (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000110110" *) + (* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000011011000" *) + (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000011011001" *) + (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000011011010" *) + (* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000011011011" *) + (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000011011100" *) + (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000011011101" *) + (* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000011011110" *) + (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000011011111" *) + (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000011100000" *) + (* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000011100001" *) + (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000110111" *) + (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000011100010" *) + (* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000011100011" *) + (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011100100" *) + (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011100101" *) + (* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011100110" *) + (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011100111" *) + (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011101000" *) + (* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011101001" *) + (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011101010" *) + (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011101011" *) + (* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000011" *) + (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000111000" *) + (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011101100" *) + (* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011101101" *) + (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011101110" *) + (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011101111" *) + (* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011110000" *) + (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011110001" *) + (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011110010" *) + (* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011110011" *) + (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011110100" *) + (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011110101" *) + (* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000111001" *) + (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011110110" *) + (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011110111" *) + (* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011111000" *) + (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011111001" *) + (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011111010" *) + (* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011111011" *) + (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011111100" *) + (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011111101" *) + (* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011111110" *) + (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011111111" *) + (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000111010" *) + (* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000100000000" *) + (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000100000001" *) + (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000100000010" *) + (* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000100000011" *) + (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000100000100" *) + (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000100000101" *) + (* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000100000110" *) + (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000100000111" *) + (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000100001000" *) + (* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000100001001" *) + (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000111011" *) + (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000100001010" *) + (* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000100001011" *) + (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000100001100" *) + (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000100001101" *) + (* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000100001110" *) + (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000100001111" *) + (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000100010000" *) + (* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000100010001" *) + (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000100010010" *) + (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000100010011" *) + (* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000111100" *) + (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000100010100" *) + (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000100010101" *) + (* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000100010110" *) + (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000100010111" *) + (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000100011000" *) + (* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000100011001" *) + (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000100011010" *) + (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000100011011" *) + (* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000100011100" *) + (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000100011101" *) + (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000111101" *) + (* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000100011110" *) + (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000100011111" *) + (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000100100000" *) + (* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000100100001" *) + (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000100100010" *) + (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000100100011" *) + (* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000111110" *) + (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000111111" *) + (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000001000000" *) + (* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000001000001" *) + (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000100011" *) + (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000001000010" *) + (* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000001000011" *) + (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000001000100" *) + (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000001000101" *) + (* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000001000110" *) + (* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000001000111" *) + (* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000001001000" *) + (* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000001001001" *) + (* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000001001010" *) + (* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000001001011" *) + (* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000100101" *) + (* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000001001100" *) + (* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000001001101" *) + (* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000001001110" *) + (* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000001001111" *) + (* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000001010000" *) + (* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000001010001" *) + (* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000001010010" *) + (* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000001010011" *) + (* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000001010100" *) + (* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000001010101" *) + (* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000101001" *) + (* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000001010110" *) + (* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000001010111" *) + (* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000001011000" *) + (* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000001011001" *) + (* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000001011010" *) + (* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000001011011" *) + (* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000001011100" *) + (* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000001011101" *) + (* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000001011110" *) + (* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000001011111" *) + (* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000101010" *) + (* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000001100000" *) + (* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000001100001" *) + (* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000001100010" *) + (* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000001100011" *) + (* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001100100" *) + (* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001100101" *) + (* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001100110" *) + (* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001100111" *) + (* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001101000" *) + (* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001101001" *) + (* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000101011" *) + (* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001101010" *) + (* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001101011" *) + (* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001101100" *) + (* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001101101" *) + (* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001101110" *) + (* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001101111" *) + (* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001110000" *) + (* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001110001" *) + (* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001110010" *) + (* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001110011" *) + (* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000101100" *) + (* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001110100" *) + (* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001110101" *) + (* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001110110" *) + (* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001110111" *) + (* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001111000" *) + (* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001111001" *) + (* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001111010" *) + (* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001111011" *) + (* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001111100" *) + (* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001111101" *) + (* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000101101" *) + (* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001111110" *) + (* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001111111" *) + (* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000010000000" *) + (* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000010000001" *) + (* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000010000010" *) + (* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000010000011" *) + (* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000010000100" *) + (* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000010000101" *) + (* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000010000110" *) + (* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000010000111" *) + (* LC_PROBE_IN_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) + (* LC_PROBE_OUT_HIGH_BIT_POS_STRING = "4096'b0000000100100011000000010010001000000001001000010000000100100000000000010001111100000001000111100000000100011101000000010001110000000001000110110000000100011010000000010001100100000001000110000000000100010111000000010001011000000001000101010000000100010100000000010001001100000001000100100000000100010001000000010001000000000001000011110000000100001110000000010000110100000001000011000000000100001011000000010000101000000001000010010000000100001000000000010000011100000001000001100000000100000101000000010000010000000001000000110000000100000010000000010000000100000001000000000000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100100000000000010001000000000000000100000000000000001" *) + (* LC_PROBE_OUT_INIT_VAL_STRING = "292'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000010" *) + (* LC_PROBE_OUT_LOW_BIT_POS_STRING = "4096'b0000000100100011000000010010001000000001001000010000000100100000000000010001111100000001000111100000000100011101000000010001110000000001000110110000000100011010000000010001100100000001000110000000000100010111000000010001011000000001000101010000000100010100000000010001001100000001000100100000000100010001000000010001000000000001000011110000000100001110000000010000110100000001000011000000000100001011000000010000101000000001000010010000000100001000000000010000011100000001000001100000000100000101000000010000010000000001000000110000000100000010000000010000000100000001000000000000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001001010000000000100011000000000000001100000000000000100000000000000000" *) + (* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000001000111110000000000000001" *) + (* LC_TOTAL_PROBE_IN_WIDTH = "0" *) + (* LC_TOTAL_PROBE_OUT_WIDTH = "41" *) + (* syn_noprune = "1" *) + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio inst + (.clk(clk), + .probe_in0(1'b0), + .probe_in1(1'b0), + .probe_in10(1'b0), + .probe_in100(1'b0), + .probe_in101(1'b0), + .probe_in102(1'b0), + .probe_in103(1'b0), + .probe_in104(1'b0), + .probe_in105(1'b0), + .probe_in106(1'b0), + .probe_in107(1'b0), + .probe_in108(1'b0), + .probe_in109(1'b0), + .probe_in11(1'b0), + .probe_in110(1'b0), + .probe_in111(1'b0), + .probe_in112(1'b0), + .probe_in113(1'b0), + .probe_in114(1'b0), + .probe_in115(1'b0), + .probe_in116(1'b0), + .probe_in117(1'b0), + .probe_in118(1'b0), + .probe_in119(1'b0), + .probe_in12(1'b0), + .probe_in120(1'b0), + .probe_in121(1'b0), + .probe_in122(1'b0), + .probe_in123(1'b0), + .probe_in124(1'b0), + .probe_in125(1'b0), + .probe_in126(1'b0), + .probe_in127(1'b0), + .probe_in128(1'b0), + .probe_in129(1'b0), + .probe_in13(1'b0), + .probe_in130(1'b0), + .probe_in131(1'b0), + .probe_in132(1'b0), + .probe_in133(1'b0), + .probe_in134(1'b0), + .probe_in135(1'b0), + .probe_in136(1'b0), + .probe_in137(1'b0), + .probe_in138(1'b0), + .probe_in139(1'b0), + .probe_in14(1'b0), + .probe_in140(1'b0), + .probe_in141(1'b0), + .probe_in142(1'b0), + .probe_in143(1'b0), + .probe_in144(1'b0), + .probe_in145(1'b0), + .probe_in146(1'b0), + .probe_in147(1'b0), + .probe_in148(1'b0), + .probe_in149(1'b0), + .probe_in15(1'b0), + .probe_in150(1'b0), + .probe_in151(1'b0), + .probe_in152(1'b0), + .probe_in153(1'b0), + .probe_in154(1'b0), + .probe_in155(1'b0), + .probe_in156(1'b0), + .probe_in157(1'b0), + .probe_in158(1'b0), + .probe_in159(1'b0), + .probe_in16(1'b0), + .probe_in160(1'b0), + .probe_in161(1'b0), + .probe_in162(1'b0), + .probe_in163(1'b0), + .probe_in164(1'b0), + .probe_in165(1'b0), + .probe_in166(1'b0), + .probe_in167(1'b0), + .probe_in168(1'b0), + .probe_in169(1'b0), + .probe_in17(1'b0), + .probe_in170(1'b0), + .probe_in171(1'b0), + .probe_in172(1'b0), + .probe_in173(1'b0), + .probe_in174(1'b0), + .probe_in175(1'b0), + .probe_in176(1'b0), + .probe_in177(1'b0), + .probe_in178(1'b0), + .probe_in179(1'b0), + .probe_in18(1'b0), + .probe_in180(1'b0), + .probe_in181(1'b0), + .probe_in182(1'b0), + .probe_in183(1'b0), + .probe_in184(1'b0), + .probe_in185(1'b0), + .probe_in186(1'b0), + .probe_in187(1'b0), + .probe_in188(1'b0), + .probe_in189(1'b0), + .probe_in19(1'b0), + .probe_in190(1'b0), + .probe_in191(1'b0), + .probe_in192(1'b0), + .probe_in193(1'b0), + .probe_in194(1'b0), + .probe_in195(1'b0), + .probe_in196(1'b0), + .probe_in197(1'b0), + .probe_in198(1'b0), + .probe_in199(1'b0), + .probe_in2(1'b0), + .probe_in20(1'b0), + .probe_in200(1'b0), + .probe_in201(1'b0), + .probe_in202(1'b0), + .probe_in203(1'b0), + .probe_in204(1'b0), + .probe_in205(1'b0), + .probe_in206(1'b0), + .probe_in207(1'b0), + .probe_in208(1'b0), + .probe_in209(1'b0), + .probe_in21(1'b0), + .probe_in210(1'b0), + .probe_in211(1'b0), + .probe_in212(1'b0), + .probe_in213(1'b0), + .probe_in214(1'b0), + .probe_in215(1'b0), + .probe_in216(1'b0), + .probe_in217(1'b0), + .probe_in218(1'b0), + .probe_in219(1'b0), + .probe_in22(1'b0), + .probe_in220(1'b0), + .probe_in221(1'b0), + .probe_in222(1'b0), + .probe_in223(1'b0), + .probe_in224(1'b0), + .probe_in225(1'b0), + .probe_in226(1'b0), + .probe_in227(1'b0), + .probe_in228(1'b0), + .probe_in229(1'b0), + .probe_in23(1'b0), + .probe_in230(1'b0), + .probe_in231(1'b0), + .probe_in232(1'b0), + .probe_in233(1'b0), + .probe_in234(1'b0), + .probe_in235(1'b0), + .probe_in236(1'b0), + .probe_in237(1'b0), + .probe_in238(1'b0), + .probe_in239(1'b0), + .probe_in24(1'b0), + .probe_in240(1'b0), + .probe_in241(1'b0), + .probe_in242(1'b0), + .probe_in243(1'b0), + .probe_in244(1'b0), + .probe_in245(1'b0), + .probe_in246(1'b0), + .probe_in247(1'b0), + .probe_in248(1'b0), + .probe_in249(1'b0), + .probe_in25(1'b0), + .probe_in250(1'b0), + .probe_in251(1'b0), + .probe_in252(1'b0), + .probe_in253(1'b0), + .probe_in254(1'b0), + .probe_in255(1'b0), + .probe_in26(1'b0), + .probe_in27(1'b0), + .probe_in28(1'b0), + .probe_in29(1'b0), + .probe_in3(1'b0), + .probe_in30(1'b0), + .probe_in31(1'b0), + .probe_in32(1'b0), + .probe_in33(1'b0), + .probe_in34(1'b0), + .probe_in35(1'b0), + .probe_in36(1'b0), + .probe_in37(1'b0), + .probe_in38(1'b0), + .probe_in39(1'b0), + .probe_in4(1'b0), + .probe_in40(1'b0), + .probe_in41(1'b0), + .probe_in42(1'b0), + .probe_in43(1'b0), + .probe_in44(1'b0), + .probe_in45(1'b0), + .probe_in46(1'b0), + .probe_in47(1'b0), + .probe_in48(1'b0), + .probe_in49(1'b0), + .probe_in5(1'b0), + .probe_in50(1'b0), + .probe_in51(1'b0), + .probe_in52(1'b0), + .probe_in53(1'b0), + .probe_in54(1'b0), + .probe_in55(1'b0), + .probe_in56(1'b0), + .probe_in57(1'b0), + .probe_in58(1'b0), + .probe_in59(1'b0), + .probe_in6(1'b0), + .probe_in60(1'b0), + .probe_in61(1'b0), + .probe_in62(1'b0), + .probe_in63(1'b0), + .probe_in64(1'b0), + .probe_in65(1'b0), + .probe_in66(1'b0), + .probe_in67(1'b0), + .probe_in68(1'b0), + .probe_in69(1'b0), + .probe_in7(1'b0), + .probe_in70(1'b0), + .probe_in71(1'b0), + .probe_in72(1'b0), + .probe_in73(1'b0), + .probe_in74(1'b0), + .probe_in75(1'b0), + .probe_in76(1'b0), + .probe_in77(1'b0), + .probe_in78(1'b0), + .probe_in79(1'b0), + .probe_in8(1'b0), + .probe_in80(1'b0), + .probe_in81(1'b0), + .probe_in82(1'b0), + .probe_in83(1'b0), + .probe_in84(1'b0), + .probe_in85(1'b0), + .probe_in86(1'b0), + .probe_in87(1'b0), + .probe_in88(1'b0), + .probe_in89(1'b0), + .probe_in9(1'b0), + .probe_in90(1'b0), + .probe_in91(1'b0), + .probe_in92(1'b0), + .probe_in93(1'b0), + .probe_in94(1'b0), + .probe_in95(1'b0), + .probe_in96(1'b0), + .probe_in97(1'b0), + .probe_in98(1'b0), + .probe_in99(1'b0), + .probe_out0(probe_out0), + .probe_out1(probe_out1), + .probe_out10(NLW_inst_probe_out10_UNCONNECTED[0]), + .probe_out100(NLW_inst_probe_out100_UNCONNECTED[0]), + .probe_out101(NLW_inst_probe_out101_UNCONNECTED[0]), + .probe_out102(NLW_inst_probe_out102_UNCONNECTED[0]), + .probe_out103(NLW_inst_probe_out103_UNCONNECTED[0]), + .probe_out104(NLW_inst_probe_out104_UNCONNECTED[0]), + .probe_out105(NLW_inst_probe_out105_UNCONNECTED[0]), + .probe_out106(NLW_inst_probe_out106_UNCONNECTED[0]), + .probe_out107(NLW_inst_probe_out107_UNCONNECTED[0]), + .probe_out108(NLW_inst_probe_out108_UNCONNECTED[0]), + .probe_out109(NLW_inst_probe_out109_UNCONNECTED[0]), + .probe_out11(NLW_inst_probe_out11_UNCONNECTED[0]), + .probe_out110(NLW_inst_probe_out110_UNCONNECTED[0]), + .probe_out111(NLW_inst_probe_out111_UNCONNECTED[0]), + .probe_out112(NLW_inst_probe_out112_UNCONNECTED[0]), + .probe_out113(NLW_inst_probe_out113_UNCONNECTED[0]), + .probe_out114(NLW_inst_probe_out114_UNCONNECTED[0]), + .probe_out115(NLW_inst_probe_out115_UNCONNECTED[0]), + .probe_out116(NLW_inst_probe_out116_UNCONNECTED[0]), + .probe_out117(NLW_inst_probe_out117_UNCONNECTED[0]), + .probe_out118(NLW_inst_probe_out118_UNCONNECTED[0]), + .probe_out119(NLW_inst_probe_out119_UNCONNECTED[0]), + .probe_out12(NLW_inst_probe_out12_UNCONNECTED[0]), + .probe_out120(NLW_inst_probe_out120_UNCONNECTED[0]), + .probe_out121(NLW_inst_probe_out121_UNCONNECTED[0]), + .probe_out122(NLW_inst_probe_out122_UNCONNECTED[0]), + .probe_out123(NLW_inst_probe_out123_UNCONNECTED[0]), + .probe_out124(NLW_inst_probe_out124_UNCONNECTED[0]), + .probe_out125(NLW_inst_probe_out125_UNCONNECTED[0]), + .probe_out126(NLW_inst_probe_out126_UNCONNECTED[0]), + .probe_out127(NLW_inst_probe_out127_UNCONNECTED[0]), + .probe_out128(NLW_inst_probe_out128_UNCONNECTED[0]), + .probe_out129(NLW_inst_probe_out129_UNCONNECTED[0]), + .probe_out13(NLW_inst_probe_out13_UNCONNECTED[0]), + .probe_out130(NLW_inst_probe_out130_UNCONNECTED[0]), + .probe_out131(NLW_inst_probe_out131_UNCONNECTED[0]), + .probe_out132(NLW_inst_probe_out132_UNCONNECTED[0]), + .probe_out133(NLW_inst_probe_out133_UNCONNECTED[0]), + .probe_out134(NLW_inst_probe_out134_UNCONNECTED[0]), + .probe_out135(NLW_inst_probe_out135_UNCONNECTED[0]), + .probe_out136(NLW_inst_probe_out136_UNCONNECTED[0]), + .probe_out137(NLW_inst_probe_out137_UNCONNECTED[0]), + .probe_out138(NLW_inst_probe_out138_UNCONNECTED[0]), + .probe_out139(NLW_inst_probe_out139_UNCONNECTED[0]), + .probe_out14(NLW_inst_probe_out14_UNCONNECTED[0]), + .probe_out140(NLW_inst_probe_out140_UNCONNECTED[0]), + .probe_out141(NLW_inst_probe_out141_UNCONNECTED[0]), + .probe_out142(NLW_inst_probe_out142_UNCONNECTED[0]), + .probe_out143(NLW_inst_probe_out143_UNCONNECTED[0]), + .probe_out144(NLW_inst_probe_out144_UNCONNECTED[0]), + .probe_out145(NLW_inst_probe_out145_UNCONNECTED[0]), + .probe_out146(NLW_inst_probe_out146_UNCONNECTED[0]), + .probe_out147(NLW_inst_probe_out147_UNCONNECTED[0]), + .probe_out148(NLW_inst_probe_out148_UNCONNECTED[0]), + .probe_out149(NLW_inst_probe_out149_UNCONNECTED[0]), + .probe_out15(NLW_inst_probe_out15_UNCONNECTED[0]), + .probe_out150(NLW_inst_probe_out150_UNCONNECTED[0]), + .probe_out151(NLW_inst_probe_out151_UNCONNECTED[0]), + .probe_out152(NLW_inst_probe_out152_UNCONNECTED[0]), + .probe_out153(NLW_inst_probe_out153_UNCONNECTED[0]), + .probe_out154(NLW_inst_probe_out154_UNCONNECTED[0]), + .probe_out155(NLW_inst_probe_out155_UNCONNECTED[0]), + .probe_out156(NLW_inst_probe_out156_UNCONNECTED[0]), + .probe_out157(NLW_inst_probe_out157_UNCONNECTED[0]), + .probe_out158(NLW_inst_probe_out158_UNCONNECTED[0]), + .probe_out159(NLW_inst_probe_out159_UNCONNECTED[0]), + .probe_out16(NLW_inst_probe_out16_UNCONNECTED[0]), + .probe_out160(NLW_inst_probe_out160_UNCONNECTED[0]), + .probe_out161(NLW_inst_probe_out161_UNCONNECTED[0]), + .probe_out162(NLW_inst_probe_out162_UNCONNECTED[0]), + .probe_out163(NLW_inst_probe_out163_UNCONNECTED[0]), + .probe_out164(NLW_inst_probe_out164_UNCONNECTED[0]), + .probe_out165(NLW_inst_probe_out165_UNCONNECTED[0]), + .probe_out166(NLW_inst_probe_out166_UNCONNECTED[0]), + .probe_out167(NLW_inst_probe_out167_UNCONNECTED[0]), + .probe_out168(NLW_inst_probe_out168_UNCONNECTED[0]), + .probe_out169(NLW_inst_probe_out169_UNCONNECTED[0]), + .probe_out17(NLW_inst_probe_out17_UNCONNECTED[0]), + .probe_out170(NLW_inst_probe_out170_UNCONNECTED[0]), + .probe_out171(NLW_inst_probe_out171_UNCONNECTED[0]), + .probe_out172(NLW_inst_probe_out172_UNCONNECTED[0]), + .probe_out173(NLW_inst_probe_out173_UNCONNECTED[0]), + .probe_out174(NLW_inst_probe_out174_UNCONNECTED[0]), + .probe_out175(NLW_inst_probe_out175_UNCONNECTED[0]), + .probe_out176(NLW_inst_probe_out176_UNCONNECTED[0]), + .probe_out177(NLW_inst_probe_out177_UNCONNECTED[0]), + .probe_out178(NLW_inst_probe_out178_UNCONNECTED[0]), + .probe_out179(NLW_inst_probe_out179_UNCONNECTED[0]), + .probe_out18(NLW_inst_probe_out18_UNCONNECTED[0]), + .probe_out180(NLW_inst_probe_out180_UNCONNECTED[0]), + .probe_out181(NLW_inst_probe_out181_UNCONNECTED[0]), + .probe_out182(NLW_inst_probe_out182_UNCONNECTED[0]), + .probe_out183(NLW_inst_probe_out183_UNCONNECTED[0]), + .probe_out184(NLW_inst_probe_out184_UNCONNECTED[0]), + .probe_out185(NLW_inst_probe_out185_UNCONNECTED[0]), + .probe_out186(NLW_inst_probe_out186_UNCONNECTED[0]), + .probe_out187(NLW_inst_probe_out187_UNCONNECTED[0]), + .probe_out188(NLW_inst_probe_out188_UNCONNECTED[0]), + .probe_out189(NLW_inst_probe_out189_UNCONNECTED[0]), + .probe_out19(NLW_inst_probe_out19_UNCONNECTED[0]), + .probe_out190(NLW_inst_probe_out190_UNCONNECTED[0]), + .probe_out191(NLW_inst_probe_out191_UNCONNECTED[0]), + .probe_out192(NLW_inst_probe_out192_UNCONNECTED[0]), + .probe_out193(NLW_inst_probe_out193_UNCONNECTED[0]), + .probe_out194(NLW_inst_probe_out194_UNCONNECTED[0]), + .probe_out195(NLW_inst_probe_out195_UNCONNECTED[0]), + .probe_out196(NLW_inst_probe_out196_UNCONNECTED[0]), + .probe_out197(NLW_inst_probe_out197_UNCONNECTED[0]), + .probe_out198(NLW_inst_probe_out198_UNCONNECTED[0]), + .probe_out199(NLW_inst_probe_out199_UNCONNECTED[0]), + .probe_out2(probe_out2), + .probe_out20(NLW_inst_probe_out20_UNCONNECTED[0]), + .probe_out200(NLW_inst_probe_out200_UNCONNECTED[0]), + .probe_out201(NLW_inst_probe_out201_UNCONNECTED[0]), + .probe_out202(NLW_inst_probe_out202_UNCONNECTED[0]), + .probe_out203(NLW_inst_probe_out203_UNCONNECTED[0]), + .probe_out204(NLW_inst_probe_out204_UNCONNECTED[0]), + .probe_out205(NLW_inst_probe_out205_UNCONNECTED[0]), + .probe_out206(NLW_inst_probe_out206_UNCONNECTED[0]), + .probe_out207(NLW_inst_probe_out207_UNCONNECTED[0]), + .probe_out208(NLW_inst_probe_out208_UNCONNECTED[0]), + .probe_out209(NLW_inst_probe_out209_UNCONNECTED[0]), + .probe_out21(NLW_inst_probe_out21_UNCONNECTED[0]), + .probe_out210(NLW_inst_probe_out210_UNCONNECTED[0]), + .probe_out211(NLW_inst_probe_out211_UNCONNECTED[0]), + .probe_out212(NLW_inst_probe_out212_UNCONNECTED[0]), + .probe_out213(NLW_inst_probe_out213_UNCONNECTED[0]), + .probe_out214(NLW_inst_probe_out214_UNCONNECTED[0]), + .probe_out215(NLW_inst_probe_out215_UNCONNECTED[0]), + .probe_out216(NLW_inst_probe_out216_UNCONNECTED[0]), + .probe_out217(NLW_inst_probe_out217_UNCONNECTED[0]), + .probe_out218(NLW_inst_probe_out218_UNCONNECTED[0]), + .probe_out219(NLW_inst_probe_out219_UNCONNECTED[0]), + .probe_out22(NLW_inst_probe_out22_UNCONNECTED[0]), + .probe_out220(NLW_inst_probe_out220_UNCONNECTED[0]), + .probe_out221(NLW_inst_probe_out221_UNCONNECTED[0]), + .probe_out222(NLW_inst_probe_out222_UNCONNECTED[0]), + .probe_out223(NLW_inst_probe_out223_UNCONNECTED[0]), + .probe_out224(NLW_inst_probe_out224_UNCONNECTED[0]), + .probe_out225(NLW_inst_probe_out225_UNCONNECTED[0]), + .probe_out226(NLW_inst_probe_out226_UNCONNECTED[0]), + .probe_out227(NLW_inst_probe_out227_UNCONNECTED[0]), + .probe_out228(NLW_inst_probe_out228_UNCONNECTED[0]), + .probe_out229(NLW_inst_probe_out229_UNCONNECTED[0]), + .probe_out23(NLW_inst_probe_out23_UNCONNECTED[0]), + .probe_out230(NLW_inst_probe_out230_UNCONNECTED[0]), + .probe_out231(NLW_inst_probe_out231_UNCONNECTED[0]), + .probe_out232(NLW_inst_probe_out232_UNCONNECTED[0]), + .probe_out233(NLW_inst_probe_out233_UNCONNECTED[0]), + .probe_out234(NLW_inst_probe_out234_UNCONNECTED[0]), + .probe_out235(NLW_inst_probe_out235_UNCONNECTED[0]), + .probe_out236(NLW_inst_probe_out236_UNCONNECTED[0]), + .probe_out237(NLW_inst_probe_out237_UNCONNECTED[0]), + .probe_out238(NLW_inst_probe_out238_UNCONNECTED[0]), + .probe_out239(NLW_inst_probe_out239_UNCONNECTED[0]), + .probe_out24(NLW_inst_probe_out24_UNCONNECTED[0]), + .probe_out240(NLW_inst_probe_out240_UNCONNECTED[0]), + .probe_out241(NLW_inst_probe_out241_UNCONNECTED[0]), + .probe_out242(NLW_inst_probe_out242_UNCONNECTED[0]), + .probe_out243(NLW_inst_probe_out243_UNCONNECTED[0]), + .probe_out244(NLW_inst_probe_out244_UNCONNECTED[0]), + .probe_out245(NLW_inst_probe_out245_UNCONNECTED[0]), + .probe_out246(NLW_inst_probe_out246_UNCONNECTED[0]), + .probe_out247(NLW_inst_probe_out247_UNCONNECTED[0]), + .probe_out248(NLW_inst_probe_out248_UNCONNECTED[0]), + .probe_out249(NLW_inst_probe_out249_UNCONNECTED[0]), + .probe_out25(NLW_inst_probe_out25_UNCONNECTED[0]), + .probe_out250(NLW_inst_probe_out250_UNCONNECTED[0]), + .probe_out251(NLW_inst_probe_out251_UNCONNECTED[0]), + .probe_out252(NLW_inst_probe_out252_UNCONNECTED[0]), + .probe_out253(NLW_inst_probe_out253_UNCONNECTED[0]), + .probe_out254(NLW_inst_probe_out254_UNCONNECTED[0]), + .probe_out255(NLW_inst_probe_out255_UNCONNECTED[0]), + .probe_out26(NLW_inst_probe_out26_UNCONNECTED[0]), + .probe_out27(NLW_inst_probe_out27_UNCONNECTED[0]), + .probe_out28(NLW_inst_probe_out28_UNCONNECTED[0]), + .probe_out29(NLW_inst_probe_out29_UNCONNECTED[0]), + .probe_out3(probe_out3), + .probe_out30(NLW_inst_probe_out30_UNCONNECTED[0]), + .probe_out31(NLW_inst_probe_out31_UNCONNECTED[0]), + .probe_out32(NLW_inst_probe_out32_UNCONNECTED[0]), + .probe_out33(NLW_inst_probe_out33_UNCONNECTED[0]), + .probe_out34(NLW_inst_probe_out34_UNCONNECTED[0]), + .probe_out35(NLW_inst_probe_out35_UNCONNECTED[0]), + .probe_out36(NLW_inst_probe_out36_UNCONNECTED[0]), + .probe_out37(NLW_inst_probe_out37_UNCONNECTED[0]), + .probe_out38(NLW_inst_probe_out38_UNCONNECTED[0]), + .probe_out39(NLW_inst_probe_out39_UNCONNECTED[0]), + .probe_out4(probe_out4), + .probe_out40(NLW_inst_probe_out40_UNCONNECTED[0]), + .probe_out41(NLW_inst_probe_out41_UNCONNECTED[0]), + .probe_out42(NLW_inst_probe_out42_UNCONNECTED[0]), + .probe_out43(NLW_inst_probe_out43_UNCONNECTED[0]), + .probe_out44(NLW_inst_probe_out44_UNCONNECTED[0]), + .probe_out45(NLW_inst_probe_out45_UNCONNECTED[0]), + .probe_out46(NLW_inst_probe_out46_UNCONNECTED[0]), + .probe_out47(NLW_inst_probe_out47_UNCONNECTED[0]), + .probe_out48(NLW_inst_probe_out48_UNCONNECTED[0]), + .probe_out49(NLW_inst_probe_out49_UNCONNECTED[0]), + .probe_out5(NLW_inst_probe_out5_UNCONNECTED[0]), + .probe_out50(NLW_inst_probe_out50_UNCONNECTED[0]), + .probe_out51(NLW_inst_probe_out51_UNCONNECTED[0]), + .probe_out52(NLW_inst_probe_out52_UNCONNECTED[0]), + .probe_out53(NLW_inst_probe_out53_UNCONNECTED[0]), + .probe_out54(NLW_inst_probe_out54_UNCONNECTED[0]), + .probe_out55(NLW_inst_probe_out55_UNCONNECTED[0]), + .probe_out56(NLW_inst_probe_out56_UNCONNECTED[0]), + .probe_out57(NLW_inst_probe_out57_UNCONNECTED[0]), + .probe_out58(NLW_inst_probe_out58_UNCONNECTED[0]), + .probe_out59(NLW_inst_probe_out59_UNCONNECTED[0]), + .probe_out6(NLW_inst_probe_out6_UNCONNECTED[0]), + .probe_out60(NLW_inst_probe_out60_UNCONNECTED[0]), + .probe_out61(NLW_inst_probe_out61_UNCONNECTED[0]), + .probe_out62(NLW_inst_probe_out62_UNCONNECTED[0]), + .probe_out63(NLW_inst_probe_out63_UNCONNECTED[0]), + .probe_out64(NLW_inst_probe_out64_UNCONNECTED[0]), + .probe_out65(NLW_inst_probe_out65_UNCONNECTED[0]), + .probe_out66(NLW_inst_probe_out66_UNCONNECTED[0]), + .probe_out67(NLW_inst_probe_out67_UNCONNECTED[0]), + .probe_out68(NLW_inst_probe_out68_UNCONNECTED[0]), + .probe_out69(NLW_inst_probe_out69_UNCONNECTED[0]), + .probe_out7(NLW_inst_probe_out7_UNCONNECTED[0]), + .probe_out70(NLW_inst_probe_out70_UNCONNECTED[0]), + .probe_out71(NLW_inst_probe_out71_UNCONNECTED[0]), + .probe_out72(NLW_inst_probe_out72_UNCONNECTED[0]), + .probe_out73(NLW_inst_probe_out73_UNCONNECTED[0]), + .probe_out74(NLW_inst_probe_out74_UNCONNECTED[0]), + .probe_out75(NLW_inst_probe_out75_UNCONNECTED[0]), + .probe_out76(NLW_inst_probe_out76_UNCONNECTED[0]), + .probe_out77(NLW_inst_probe_out77_UNCONNECTED[0]), + .probe_out78(NLW_inst_probe_out78_UNCONNECTED[0]), + .probe_out79(NLW_inst_probe_out79_UNCONNECTED[0]), + .probe_out8(NLW_inst_probe_out8_UNCONNECTED[0]), + .probe_out80(NLW_inst_probe_out80_UNCONNECTED[0]), + .probe_out81(NLW_inst_probe_out81_UNCONNECTED[0]), + .probe_out82(NLW_inst_probe_out82_UNCONNECTED[0]), + .probe_out83(NLW_inst_probe_out83_UNCONNECTED[0]), + .probe_out84(NLW_inst_probe_out84_UNCONNECTED[0]), + .probe_out85(NLW_inst_probe_out85_UNCONNECTED[0]), + .probe_out86(NLW_inst_probe_out86_UNCONNECTED[0]), + .probe_out87(NLW_inst_probe_out87_UNCONNECTED[0]), + .probe_out88(NLW_inst_probe_out88_UNCONNECTED[0]), + .probe_out89(NLW_inst_probe_out89_UNCONNECTED[0]), + .probe_out9(NLW_inst_probe_out9_UNCONNECTED[0]), + .probe_out90(NLW_inst_probe_out90_UNCONNECTED[0]), + .probe_out91(NLW_inst_probe_out91_UNCONNECTED[0]), + .probe_out92(NLW_inst_probe_out92_UNCONNECTED[0]), + .probe_out93(NLW_inst_probe_out93_UNCONNECTED[0]), + .probe_out94(NLW_inst_probe_out94_UNCONNECTED[0]), + .probe_out95(NLW_inst_probe_out95_UNCONNECTED[0]), + .probe_out96(NLW_inst_probe_out96_UNCONNECTED[0]), + .probe_out97(NLW_inst_probe_out97_UNCONNECTED[0]), + .probe_out98(NLW_inst_probe_out98_UNCONNECTED[0]), + .probe_out99(NLW_inst_probe_out99_UNCONNECTED[0]), + .sl_iport0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .sl_oport0(NLW_inst_sl_oport0_UNCONNECTED[16:0])); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_decoder + (s_drdy_i, + rd_probe_out_width, + in0, + SR, + internal_cnt_rst, + \G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 , + s_den_o_INST_0, + \G_PROBE_OUT[0].wr_probe_out[0]_i_3_0 , + \Bus_data_out_reg[15]_0 , + s_rst_o, + out, + s_daddr_o, + \rd_en_reg[6]_0 , + s_dwe_o, + s_den_o, + \Bus_data_out_reg[9]_0 , + \Bus_data_out_reg[10]_0 , + \Bus_data_out_reg[11]_0 , + \Bus_data_out_reg[12]_0 , + \Bus_data_out_reg[13]_0 , + \Bus_data_out_reg[14]_0 , + \Bus_data_out_reg[15]_1 , + \Bus_data_out_reg[8]_0 , + \Bus_data_out_reg[4]_0 , + Q, + \Bus_data_out_reg[3]_0 , + \Bus_data_out_reg[5]_0 , + \Bus_data_out_reg[6]_0 , + \Bus_data_out_reg[7]_0 , + \probe_out_modified_reg[15]_0 , + \xsdb_addr_2_0_p2_reg[2]_0 ); + output s_drdy_i; + output rd_probe_out_width; + output in0; + output [0:0]SR; + output internal_cnt_rst; + output \G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 ; + output s_den_o_INST_0; + output \G_PROBE_OUT[0].wr_probe_out[0]_i_3_0 ; + output [15:0]\Bus_data_out_reg[15]_0 ; + input s_rst_o; + input out; + input [16:0]s_daddr_o; + input \rd_en_reg[6]_0 ; + input s_dwe_o; + input s_den_o; + input \Bus_data_out_reg[9]_0 ; + input \Bus_data_out_reg[10]_0 ; + input \Bus_data_out_reg[11]_0 ; + input \Bus_data_out_reg[12]_0 ; + input \Bus_data_out_reg[13]_0 ; + input \Bus_data_out_reg[14]_0 ; + input \Bus_data_out_reg[15]_1 ; + input \Bus_data_out_reg[8]_0 ; + input \Bus_data_out_reg[4]_0 ; + input [3:0]Q; + input [2:0]\Bus_data_out_reg[3]_0 ; + input \Bus_data_out_reg[5]_0 ; + input \Bus_data_out_reg[6]_0 ; + input \Bus_data_out_reg[7]_0 ; + input [15:0]\probe_out_modified_reg[15]_0 ; + input [2:0]\xsdb_addr_2_0_p2_reg[2]_0 ; + + wire \Bus_data_out[0]_i_1_n_0 ; + wire \Bus_data_out[0]_i_2_n_0 ; + wire \Bus_data_out[10]_i_1_n_0 ; + wire \Bus_data_out[11]_i_1_n_0 ; + wire \Bus_data_out[12]_i_1_n_0 ; + wire \Bus_data_out[13]_i_1_n_0 ; + wire \Bus_data_out[14]_i_1_n_0 ; + wire \Bus_data_out[15]_i_1_n_0 ; + wire \Bus_data_out[1]_i_1_n_0 ; + wire \Bus_data_out[1]_i_2_n_0 ; + wire \Bus_data_out[2]_i_1_n_0 ; + wire \Bus_data_out[2]_i_2_n_0 ; + wire \Bus_data_out[3]_i_1_n_0 ; + wire \Bus_data_out[4]_i_1_n_0 ; + wire \Bus_data_out[5]_i_1_n_0 ; + wire \Bus_data_out[6]_i_1_n_0 ; + wire \Bus_data_out[7]_i_1_n_0 ; + wire \Bus_data_out[8]_i_1_n_0 ; + wire \Bus_data_out[8]_i_2_n_0 ; + wire \Bus_data_out[8]_i_3_n_0 ; + wire \Bus_data_out[9]_i_1_n_0 ; + wire \Bus_data_out_reg[10]_0 ; + wire \Bus_data_out_reg[11]_0 ; + wire \Bus_data_out_reg[12]_0 ; + wire \Bus_data_out_reg[13]_0 ; + wire \Bus_data_out_reg[14]_0 ; + wire [15:0]\Bus_data_out_reg[15]_0 ; + wire \Bus_data_out_reg[15]_1 ; + wire [2:0]\Bus_data_out_reg[3]_0 ; + wire \Bus_data_out_reg[4]_0 ; + wire \Bus_data_out_reg[5]_0 ; + wire \Bus_data_out_reg[6]_0 ; + wire \Bus_data_out_reg[7]_0 ; + wire \Bus_data_out_reg[8]_0 ; + wire \Bus_data_out_reg[9]_0 ; + wire \G_PROBE_OUT[0].wr_probe_out[0]_i_3_0 ; + wire \G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 ; + wire [3:0]Q; + wire [0:0]SR; + wire clear_int_i_1_n_0; + wire committ_int_i_1_n_0; + wire in0; + wire int_cnt_rst_i_1_n_0; + wire internal_cnt_rst; + wire out; + wire [15:0]probe_out_modified; + wire [15:0]\probe_out_modified_reg[15]_0 ; + wire \rd_en[6]_i_1_n_0 ; + wire \rd_en[6]_i_2_n_0 ; + wire rd_en_p1; + wire rd_en_p2; + wire \rd_en_reg[6]_0 ; + wire rd_probe_out_width; + wire [16:0]s_daddr_o; + wire s_den_o; + wire s_den_o_INST_0; + wire s_drdy_i; + wire s_dwe_o; + wire s_rst_o; + wire wr_control_reg; + wire \wr_en[2]_i_1_n_0 ; + wire \wr_en[2]_i_2_n_0 ; + wire \wr_en[2]_i_3_n_0 ; + wire \wr_en[4]_i_1_n_0 ; + wire \wr_en[4]_i_2_n_0 ; + wire wr_probe_out_modified; + wire [2:0]xsdb_addr_2_0_p2; + wire [2:0]\xsdb_addr_2_0_p2_reg[2]_0 ; + wire xsdb_addr_8_p1; + wire xsdb_addr_8_p2; + wire xsdb_drdy_i_1_n_0; + wire xsdb_rd; + + LUT6 #( + .INIT(64'hFFFF444E0000444E)) + \Bus_data_out[0]_i_1 + (.I0(xsdb_addr_2_0_p2[0]), + .I1(\Bus_data_out[0]_i_2_n_0 ), + .I2(xsdb_addr_2_0_p2[2]), + .I3(xsdb_addr_2_0_p2[1]), + .I4(xsdb_addr_8_p2), + .I5(Q[0]), + .O(\Bus_data_out[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFCA00CA0)) + \Bus_data_out[0]_i_2 + (.I0(in0), + .I1(probe_out_modified[0]), + .I2(xsdb_addr_2_0_p2[1]), + .I3(xsdb_addr_2_0_p2[2]), + .I4(\Bus_data_out_reg[3]_0 [0]), + .O(\Bus_data_out[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAAAA000CAAAA0000)) + \Bus_data_out[10]_i_1 + (.I0(\Bus_data_out_reg[10]_0 ), + .I1(probe_out_modified[10]), + .I2(xsdb_addr_2_0_p2[1]), + .I3(xsdb_addr_2_0_p2[0]), + .I4(xsdb_addr_8_p2), + .I5(xsdb_addr_2_0_p2[2]), + .O(\Bus_data_out[10]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAAAA000CAAAA0000)) + \Bus_data_out[11]_i_1 + (.I0(\Bus_data_out_reg[11]_0 ), + .I1(probe_out_modified[11]), + .I2(xsdb_addr_2_0_p2[1]), + .I3(xsdb_addr_2_0_p2[0]), + .I4(xsdb_addr_8_p2), + .I5(xsdb_addr_2_0_p2[2]), + .O(\Bus_data_out[11]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAAAA000CAAAA0000)) + \Bus_data_out[12]_i_1 + (.I0(\Bus_data_out_reg[12]_0 ), + .I1(probe_out_modified[12]), + .I2(xsdb_addr_2_0_p2[1]), + .I3(xsdb_addr_2_0_p2[0]), + .I4(xsdb_addr_8_p2), + .I5(xsdb_addr_2_0_p2[2]), + .O(\Bus_data_out[12]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAAAA000CAAAA0000)) + \Bus_data_out[13]_i_1 + (.I0(\Bus_data_out_reg[13]_0 ), + .I1(probe_out_modified[13]), + .I2(xsdb_addr_2_0_p2[1]), + .I3(xsdb_addr_2_0_p2[0]), + .I4(xsdb_addr_8_p2), + .I5(xsdb_addr_2_0_p2[2]), + .O(\Bus_data_out[13]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAAAA000CAAAA0000)) + \Bus_data_out[14]_i_1 + (.I0(\Bus_data_out_reg[14]_0 ), + .I1(probe_out_modified[14]), + .I2(xsdb_addr_2_0_p2[1]), + .I3(xsdb_addr_2_0_p2[0]), + .I4(xsdb_addr_8_p2), + .I5(xsdb_addr_2_0_p2[2]), + .O(\Bus_data_out[14]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAAAA000CAAAA0000)) + \Bus_data_out[15]_i_1 + (.I0(\Bus_data_out_reg[15]_1 ), + .I1(probe_out_modified[15]), + .I2(xsdb_addr_2_0_p2[1]), + .I3(xsdb_addr_2_0_p2[0]), + .I4(xsdb_addr_8_p2), + .I5(xsdb_addr_2_0_p2[2]), + .O(\Bus_data_out[15]_i_1_n_0 )); + LUT4 #( + .INIT(16'hA0AC)) + \Bus_data_out[1]_i_1 + (.I0(Q[1]), + .I1(\Bus_data_out[1]_i_2_n_0 ), + .I2(xsdb_addr_8_p2), + .I3(xsdb_addr_2_0_p2[0]), + .O(\Bus_data_out[1]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFCA00CA0)) + \Bus_data_out[1]_i_2 + (.I0(SR), + .I1(probe_out_modified[1]), + .I2(xsdb_addr_2_0_p2[1]), + .I3(xsdb_addr_2_0_p2[2]), + .I4(\Bus_data_out_reg[3]_0 [1]), + .O(\Bus_data_out[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFF444E0000444E)) + \Bus_data_out[2]_i_1 + (.I0(xsdb_addr_2_0_p2[0]), + .I1(\Bus_data_out[2]_i_2_n_0 ), + .I2(xsdb_addr_2_0_p2[2]), + .I3(xsdb_addr_2_0_p2[1]), + .I4(xsdb_addr_8_p2), + .I5(Q[2]), + .O(\Bus_data_out[2]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFA0AC0C0)) + \Bus_data_out[2]_i_2 + (.I0(internal_cnt_rst), + .I1(probe_out_modified[2]), + .I2(xsdb_addr_2_0_p2[2]), + .I3(\Bus_data_out_reg[3]_0 [2]), + .I4(xsdb_addr_2_0_p2[1]), + .O(\Bus_data_out[2]_i_2_n_0 )); + LUT5 #( + .INIT(32'hFFF8F8F8)) + \Bus_data_out[3]_i_1 + (.I0(\Bus_data_out[8]_i_2_n_0 ), + .I1(probe_out_modified[3]), + .I2(\Bus_data_out[8]_i_3_n_0 ), + .I3(xsdb_addr_8_p2), + .I4(Q[3]), + .O(\Bus_data_out[3]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFFF8F8F8)) + \Bus_data_out[4]_i_1 + (.I0(\Bus_data_out[8]_i_2_n_0 ), + .I1(probe_out_modified[4]), + .I2(\Bus_data_out[8]_i_3_n_0 ), + .I3(xsdb_addr_8_p2), + .I4(\Bus_data_out_reg[4]_0 ), + .O(\Bus_data_out[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'hA0A0A0A0A0A0ACA0)) + \Bus_data_out[5]_i_1 + (.I0(\Bus_data_out_reg[5]_0 ), + .I1(probe_out_modified[5]), + .I2(xsdb_addr_8_p2), + .I3(xsdb_addr_2_0_p2[2]), + .I4(xsdb_addr_2_0_p2[0]), + .I5(xsdb_addr_2_0_p2[1]), + .O(\Bus_data_out[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'hA0A0A0A0A0A0ACA0)) + \Bus_data_out[6]_i_1 + (.I0(\Bus_data_out_reg[6]_0 ), + .I1(probe_out_modified[6]), + .I2(xsdb_addr_8_p2), + .I3(xsdb_addr_2_0_p2[2]), + .I4(xsdb_addr_2_0_p2[0]), + .I5(xsdb_addr_2_0_p2[1]), + .O(\Bus_data_out[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'hA0A0A0A0A0A0ACA0)) + \Bus_data_out[7]_i_1 + (.I0(\Bus_data_out_reg[7]_0 ), + .I1(probe_out_modified[7]), + .I2(xsdb_addr_8_p2), + .I3(xsdb_addr_2_0_p2[2]), + .I4(xsdb_addr_2_0_p2[0]), + .I5(xsdb_addr_2_0_p2[1]), + .O(\Bus_data_out[7]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFFF8F8F8)) + \Bus_data_out[8]_i_1 + (.I0(\Bus_data_out[8]_i_2_n_0 ), + .I1(probe_out_modified[8]), + .I2(\Bus_data_out[8]_i_3_n_0 ), + .I3(xsdb_addr_8_p2), + .I4(\Bus_data_out_reg[8]_0 ), + .O(\Bus_data_out[8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT4 #( + .INIT(16'h0004)) + \Bus_data_out[8]_i_2 + (.I0(xsdb_addr_8_p2), + .I1(xsdb_addr_2_0_p2[2]), + .I2(xsdb_addr_2_0_p2[0]), + .I3(xsdb_addr_2_0_p2[1]), + .O(\Bus_data_out[8]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT5 #( + .INIT(32'h00000800)) + \Bus_data_out[8]_i_3 + (.I0(xsdb_addr_2_0_p2[1]), + .I1(\Bus_data_out_reg[3]_0 [2]), + .I2(xsdb_addr_8_p2), + .I3(xsdb_addr_2_0_p2[2]), + .I4(xsdb_addr_2_0_p2[0]), + .O(\Bus_data_out[8]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAA000CAAAA0000)) + \Bus_data_out[9]_i_1 + (.I0(\Bus_data_out_reg[9]_0 ), + .I1(probe_out_modified[9]), + .I2(xsdb_addr_2_0_p2[1]), + .I3(xsdb_addr_2_0_p2[0]), + .I4(xsdb_addr_8_p2), + .I5(xsdb_addr_2_0_p2[2]), + .O(\Bus_data_out[9]_i_1_n_0 )); + FDRE \Bus_data_out_reg[0] + (.C(out), + .CE(1'b1), + .D(\Bus_data_out[0]_i_1_n_0 ), + .Q(\Bus_data_out_reg[15]_0 [0]), + .R(1'b0)); + FDRE \Bus_data_out_reg[10] + (.C(out), + .CE(1'b1), + .D(\Bus_data_out[10]_i_1_n_0 ), + .Q(\Bus_data_out_reg[15]_0 [10]), + .R(1'b0)); + FDRE \Bus_data_out_reg[11] + (.C(out), + .CE(1'b1), + .D(\Bus_data_out[11]_i_1_n_0 ), + .Q(\Bus_data_out_reg[15]_0 [11]), + .R(1'b0)); + FDRE \Bus_data_out_reg[12] + (.C(out), + .CE(1'b1), + .D(\Bus_data_out[12]_i_1_n_0 ), + .Q(\Bus_data_out_reg[15]_0 [12]), + .R(1'b0)); + FDRE \Bus_data_out_reg[13] + (.C(out), + .CE(1'b1), + .D(\Bus_data_out[13]_i_1_n_0 ), + .Q(\Bus_data_out_reg[15]_0 [13]), + .R(1'b0)); + FDRE \Bus_data_out_reg[14] + (.C(out), + .CE(1'b1), + .D(\Bus_data_out[14]_i_1_n_0 ), + .Q(\Bus_data_out_reg[15]_0 [14]), + .R(1'b0)); + FDRE \Bus_data_out_reg[15] + (.C(out), + .CE(1'b1), + .D(\Bus_data_out[15]_i_1_n_0 ), + .Q(\Bus_data_out_reg[15]_0 [15]), + .R(1'b0)); + FDRE \Bus_data_out_reg[1] + (.C(out), + .CE(1'b1), + .D(\Bus_data_out[1]_i_1_n_0 ), + .Q(\Bus_data_out_reg[15]_0 [1]), + .R(1'b0)); + FDRE \Bus_data_out_reg[2] + (.C(out), + .CE(1'b1), + .D(\Bus_data_out[2]_i_1_n_0 ), + .Q(\Bus_data_out_reg[15]_0 [2]), + .R(1'b0)); + FDRE \Bus_data_out_reg[3] + (.C(out), + .CE(1'b1), + .D(\Bus_data_out[3]_i_1_n_0 ), + .Q(\Bus_data_out_reg[15]_0 [3]), + .R(1'b0)); + FDRE \Bus_data_out_reg[4] + (.C(out), + .CE(1'b1), + .D(\Bus_data_out[4]_i_1_n_0 ), + .Q(\Bus_data_out_reg[15]_0 [4]), + .R(1'b0)); + FDRE \Bus_data_out_reg[5] + (.C(out), + .CE(1'b1), + .D(\Bus_data_out[5]_i_1_n_0 ), + .Q(\Bus_data_out_reg[15]_0 [5]), + .R(1'b0)); + FDRE \Bus_data_out_reg[6] + (.C(out), + .CE(1'b1), + .D(\Bus_data_out[6]_i_1_n_0 ), + .Q(\Bus_data_out_reg[15]_0 [6]), + .R(1'b0)); + FDRE \Bus_data_out_reg[7] + (.C(out), + .CE(1'b1), + .D(\Bus_data_out[7]_i_1_n_0 ), + .Q(\Bus_data_out_reg[15]_0 [7]), + .R(1'b0)); + FDRE \Bus_data_out_reg[8] + (.C(out), + .CE(1'b1), + .D(\Bus_data_out[8]_i_1_n_0 ), + .Q(\Bus_data_out_reg[15]_0 [8]), + .R(1'b0)); + FDRE \Bus_data_out_reg[9] + (.C(out), + .CE(1'b1), + .D(\Bus_data_out[9]_i_1_n_0 ), + .Q(\Bus_data_out_reg[15]_0 [9]), + .R(1'b0)); + LUT4 #( + .INIT(16'hFFFE)) + \G_PROBE_OUT[0].wr_probe_out[0]_i_3 + (.I0(s_daddr_o[12]), + .I1(s_daddr_o[13]), + .I2(s_daddr_o[14]), + .I3(s_daddr_o[15]), + .O(\G_PROBE_OUT[0].wr_probe_out[0]_i_3_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \G_PROBE_OUT[0].wr_probe_out[0]_i_4 + (.I0(s_daddr_o[4]), + .I1(s_daddr_o[5]), + .I2(s_daddr_o[6]), + .I3(s_daddr_o[7]), + .O(\G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT4 #( + .INIT(16'h0040)) + \G_PROBE_OUT[0].wr_probe_out[0]_i_5 + (.I0(s_daddr_o[16]), + .I1(s_den_o), + .I2(s_dwe_o), + .I3(s_daddr_o[1]), + .O(s_den_o_INST_0)); + LUT3 #( + .INIT(8'hB8)) + clear_int_i_1 + (.I0(\probe_out_modified_reg[15]_0 [1]), + .I1(wr_control_reg), + .I2(SR), + .O(clear_int_i_1_n_0)); + FDRE clear_int_reg + (.C(out), + .CE(1'b1), + .D(clear_int_i_1_n_0), + .Q(SR), + .R(s_rst_o)); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT3 #( + .INIT(8'hB8)) + committ_int_i_1 + (.I0(\probe_out_modified_reg[15]_0 [0]), + .I1(wr_control_reg), + .I2(in0), + .O(committ_int_i_1_n_0)); + FDRE committ_int_reg + (.C(out), + .CE(1'b1), + .D(committ_int_i_1_n_0), + .Q(in0), + .R(s_rst_o)); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT3 #( + .INIT(8'hB8)) + int_cnt_rst_i_1 + (.I0(\probe_out_modified_reg[15]_0 [2]), + .I1(wr_control_reg), + .I2(internal_cnt_rst), + .O(int_cnt_rst_i_1_n_0)); + FDRE int_cnt_rst_reg + (.C(out), + .CE(1'b1), + .D(int_cnt_rst_i_1_n_0), + .Q(internal_cnt_rst), + .R(s_rst_o)); + FDRE \probe_out_modified_reg[0] + (.C(out), + .CE(wr_probe_out_modified), + .D(\probe_out_modified_reg[15]_0 [0]), + .Q(probe_out_modified[0]), + .R(SR)); + FDRE \probe_out_modified_reg[10] + (.C(out), + .CE(wr_probe_out_modified), + .D(\probe_out_modified_reg[15]_0 [10]), + .Q(probe_out_modified[10]), + .R(SR)); + FDRE \probe_out_modified_reg[11] + (.C(out), + .CE(wr_probe_out_modified), + .D(\probe_out_modified_reg[15]_0 [11]), + .Q(probe_out_modified[11]), + .R(SR)); + FDRE \probe_out_modified_reg[12] + (.C(out), + .CE(wr_probe_out_modified), + .D(\probe_out_modified_reg[15]_0 [12]), + .Q(probe_out_modified[12]), + .R(SR)); + FDRE \probe_out_modified_reg[13] + (.C(out), + .CE(wr_probe_out_modified), + .D(\probe_out_modified_reg[15]_0 [13]), + .Q(probe_out_modified[13]), + .R(SR)); + FDRE \probe_out_modified_reg[14] + (.C(out), + .CE(wr_probe_out_modified), + .D(\probe_out_modified_reg[15]_0 [14]), + .Q(probe_out_modified[14]), + .R(SR)); + FDRE \probe_out_modified_reg[15] + (.C(out), + .CE(wr_probe_out_modified), + .D(\probe_out_modified_reg[15]_0 [15]), + .Q(probe_out_modified[15]), + .R(SR)); + FDRE \probe_out_modified_reg[1] + (.C(out), + .CE(wr_probe_out_modified), + .D(\probe_out_modified_reg[15]_0 [1]), + .Q(probe_out_modified[1]), + .R(SR)); + FDRE \probe_out_modified_reg[2] + (.C(out), + .CE(wr_probe_out_modified), + .D(\probe_out_modified_reg[15]_0 [2]), + .Q(probe_out_modified[2]), + .R(SR)); + FDRE \probe_out_modified_reg[3] + (.C(out), + .CE(wr_probe_out_modified), + .D(\probe_out_modified_reg[15]_0 [3]), + .Q(probe_out_modified[3]), + .R(SR)); + FDRE \probe_out_modified_reg[4] + (.C(out), + .CE(wr_probe_out_modified), + .D(\probe_out_modified_reg[15]_0 [4]), + .Q(probe_out_modified[4]), + .R(SR)); + FDRE \probe_out_modified_reg[5] + (.C(out), + .CE(wr_probe_out_modified), + .D(\probe_out_modified_reg[15]_0 [5]), + .Q(probe_out_modified[5]), + .R(SR)); + FDRE \probe_out_modified_reg[6] + (.C(out), + .CE(wr_probe_out_modified), + .D(\probe_out_modified_reg[15]_0 [6]), + .Q(probe_out_modified[6]), + .R(SR)); + FDRE \probe_out_modified_reg[7] + (.C(out), + .CE(wr_probe_out_modified), + .D(\probe_out_modified_reg[15]_0 [7]), + .Q(probe_out_modified[7]), + .R(SR)); + FDRE \probe_out_modified_reg[8] + (.C(out), + .CE(wr_probe_out_modified), + .D(\probe_out_modified_reg[15]_0 [8]), + .Q(probe_out_modified[8]), + .R(SR)); + FDRE \probe_out_modified_reg[9] + (.C(out), + .CE(wr_probe_out_modified), + .D(\probe_out_modified_reg[15]_0 [9]), + .Q(probe_out_modified[9]), + .R(SR)); + LUT5 #( + .INIT(32'h08000000)) + \rd_en[6]_i_1 + (.I0(s_daddr_o[2]), + .I1(s_daddr_o[1]), + .I2(s_daddr_o[0]), + .I3(\rd_en[6]_i_2_n_0 ), + .I4(\rd_en_reg[6]_0 ), + .O(\rd_en[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000100000000)) + \rd_en[6]_i_2 + (.I0(s_daddr_o[7]), + .I1(s_daddr_o[6]), + .I2(s_daddr_o[8]), + .I3(s_daddr_o[16]), + .I4(s_dwe_o), + .I5(s_den_o), + .O(\rd_en[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT2 #( + .INIT(4'h2)) + rd_en_p1_i_1 + (.I0(s_den_o), + .I1(s_dwe_o), + .O(xsdb_rd)); + FDRE rd_en_p1_reg + (.C(out), + .CE(1'b1), + .D(xsdb_rd), + .Q(rd_en_p1), + .R(s_rst_o)); + FDRE rd_en_p2_reg + (.C(out), + .CE(1'b1), + .D(rd_en_p1), + .Q(rd_en_p2), + .R(s_rst_o)); + FDRE \rd_en_reg[6] + (.C(out), + .CE(1'b1), + .D(\rd_en[6]_i_1_n_0 ), + .Q(rd_probe_out_width), + .R(1'b0)); + LUT6 #( + .INIT(64'h0000000000000080)) + \wr_en[2]_i_1 + (.I0(\wr_en[2]_i_2_n_0 ), + .I1(\wr_en[2]_i_3_n_0 ), + .I2(s_daddr_o[1]), + .I3(s_daddr_o[0]), + .I4(\G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 ), + .I5(\wr_en[4]_i_2_n_0 ), + .O(\wr_en[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT3 #( + .INIT(8'h08)) + \wr_en[2]_i_2 + (.I0(s_dwe_o), + .I1(s_den_o), + .I2(s_daddr_o[16]), + .O(\wr_en[2]_i_2_n_0 )); + LUT2 #( + .INIT(4'h1)) + \wr_en[2]_i_3 + (.I0(s_daddr_o[2]), + .I1(s_daddr_o[3]), + .O(\wr_en[2]_i_3_n_0 )); + LUT6 #( + .INIT(64'h0000000000000020)) + \wr_en[4]_i_1 + (.I0(s_den_o_INST_0), + .I1(s_daddr_o[0]), + .I2(s_daddr_o[2]), + .I3(s_daddr_o[3]), + .I4(\G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 ), + .I5(\wr_en[4]_i_2_n_0 ), + .O(\wr_en[4]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFFFFFFFE)) + \wr_en[4]_i_2 + (.I0(s_daddr_o[9]), + .I1(\G_PROBE_OUT[0].wr_probe_out[0]_i_3_0 ), + .I2(s_daddr_o[11]), + .I3(s_daddr_o[10]), + .I4(s_daddr_o[8]), + .O(\wr_en[4]_i_2_n_0 )); + FDRE \wr_en_reg[2] + (.C(out), + .CE(1'b1), + .D(\wr_en[2]_i_1_n_0 ), + .Q(wr_control_reg), + .R(1'b0)); + FDRE \wr_en_reg[4] + (.C(out), + .CE(1'b1), + .D(\wr_en[4]_i_1_n_0 ), + .Q(wr_probe_out_modified), + .R(1'b0)); + FDRE \xsdb_addr_2_0_p2_reg[0] + (.C(out), + .CE(1'b1), + .D(\xsdb_addr_2_0_p2_reg[2]_0 [0]), + .Q(xsdb_addr_2_0_p2[0]), + .R(1'b0)); + FDRE \xsdb_addr_2_0_p2_reg[1] + (.C(out), + .CE(1'b1), + .D(\xsdb_addr_2_0_p2_reg[2]_0 [1]), + .Q(xsdb_addr_2_0_p2[1]), + .R(1'b0)); + FDRE \xsdb_addr_2_0_p2_reg[2] + (.C(out), + .CE(1'b1), + .D(\xsdb_addr_2_0_p2_reg[2]_0 [2]), + .Q(xsdb_addr_2_0_p2[2]), + .R(1'b0)); + FDRE xsdb_addr_8_p1_reg + (.C(out), + .CE(1'b1), + .D(s_daddr_o[8]), + .Q(xsdb_addr_8_p1), + .R(1'b0)); + FDRE xsdb_addr_8_p2_reg + (.C(out), + .CE(1'b1), + .D(xsdb_addr_8_p1), + .Q(xsdb_addr_8_p2), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT3 #( + .INIT(8'hF8)) + xsdb_drdy_i_1 + (.I0(s_dwe_o), + .I1(s_den_o), + .I2(rd_en_p2), + .O(xsdb_drdy_i_1_n_0)); + FDRE xsdb_drdy_reg + (.C(out), + .CE(1'b1), + .D(xsdb_drdy_i_1_n_0), + .Q(s_drdy_i), + .R(s_rst_o)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_all + (probe_out0, + probe_out1, + probe_out2, + probe_out3, + probe_out4, + \addr_count[1]_i_5 , + \addr_p1_reg[2]_0 , + \Probe_out_reg_int_reg[3]_0 , + \Probe_out_reg_int_reg[15]_0 , + \Probe_out_reg_int_reg[14]_0 , + \Probe_out_reg_int_reg[13]_0 , + \Probe_out_reg_int_reg[12]_0 , + \Probe_out_reg_int_reg[11]_0 , + \Probe_out_reg_int_reg[10]_0 , + \Probe_out_reg_int_reg[9]_0 , + \Probe_out_reg_int_reg[8]_0 , + \Probe_out_reg_int_reg[7]_0 , + \Probe_out_reg_int_reg[6]_0 , + \Probe_out_reg_int_reg[5]_0 , + \Probe_out_reg_int_reg[4]_0 , + SR, + in0, + clk, + out, + s_daddr_o, + s_dwe_o, + s_den_o, + \G_PROBE_OUT[0].wr_probe_out_reg[0]_0 , + \G_PROBE_OUT[0].wr_probe_out_reg[0]_1 , + \G_PROBE_OUT[0].wr_probe_out_reg[0]_2 , + Q, + internal_cnt_rst); + output [1:0]probe_out0; + output [0:0]probe_out1; + output [31:0]probe_out2; + output [1:0]probe_out3; + output [3:0]probe_out4; + output \addr_count[1]_i_5 ; + output [2:0]\addr_p1_reg[2]_0 ; + output [3:0]\Probe_out_reg_int_reg[3]_0 ; + output \Probe_out_reg_int_reg[15]_0 ; + output \Probe_out_reg_int_reg[14]_0 ; + output \Probe_out_reg_int_reg[13]_0 ; + output \Probe_out_reg_int_reg[12]_0 ; + output \Probe_out_reg_int_reg[11]_0 ; + output \Probe_out_reg_int_reg[10]_0 ; + output \Probe_out_reg_int_reg[9]_0 ; + output \Probe_out_reg_int_reg[8]_0 ; + output \Probe_out_reg_int_reg[7]_0 ; + output \Probe_out_reg_int_reg[6]_0 ; + output \Probe_out_reg_int_reg[5]_0 ; + output \Probe_out_reg_int_reg[4]_0 ; + input [0:0]SR; + input in0; + input clk; + input out; + input [16:0]s_daddr_o; + input s_dwe_o; + input s_den_o; + input \G_PROBE_OUT[0].wr_probe_out_reg[0]_0 ; + input \G_PROBE_OUT[0].wr_probe_out_reg[0]_1 ; + input \G_PROBE_OUT[0].wr_probe_out_reg[0]_2 ; + input [15:0]Q; + input internal_cnt_rst; + + wire [15:0]Bus_Data_out_int; + (* async_reg = "true" *) wire Committ_1; + (* async_reg = "true" *) wire Committ_2; + wire \G_PROBE_OUT[0].PROBE_OUT0_INST_n_2 ; + wire \G_PROBE_OUT[0].PROBE_OUT0_INST_n_3 ; + wire \G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0 ; + wire \G_PROBE_OUT[0].wr_probe_out[0]_i_2_n_0 ; + wire \G_PROBE_OUT[0].wr_probe_out[0]_i_6_n_0 ; + wire \G_PROBE_OUT[0].wr_probe_out_reg[0]_0 ; + wire \G_PROBE_OUT[0].wr_probe_out_reg[0]_1 ; + wire \G_PROBE_OUT[0].wr_probe_out_reg[0]_2 ; + wire \G_PROBE_OUT[1].PROBE_OUT0_INST_n_1 ; + wire \G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0 ; + wire \G_PROBE_OUT[1].wr_probe_out[1]_i_2_n_0 ; + wire \G_PROBE_OUT[2].PROBE_OUT0_INST_n_32 ; + wire \G_PROBE_OUT[2].wr_probe_out[2]_i_1_n_0 ; + wire \G_PROBE_OUT[2].wr_probe_out_reg ; + wire \G_PROBE_OUT[3].PROBE_OUT0_INST_n_2 ; + wire \G_PROBE_OUT[3].PROBE_OUT0_INST_n_3 ; + wire \G_PROBE_OUT[3].wr_probe_out[3]_i_1_n_0 ; + wire \G_PROBE_OUT[4].PROBE_OUT0_INST_n_4 ; + wire \G_PROBE_OUT[4].PROBE_OUT0_INST_n_5 ; + wire \G_PROBE_OUT[4].PROBE_OUT0_INST_n_6 ; + wire \G_PROBE_OUT[4].PROBE_OUT0_INST_n_7 ; + wire \G_PROBE_OUT[4].wr_probe_out[4]_i_1_n_0 ; + wire \Probe_out_reg_int[0]_i_2_n_0 ; + wire \Probe_out_reg_int[10]_i_1_n_0 ; + wire \Probe_out_reg_int[11]_i_1_n_0 ; + wire \Probe_out_reg_int[12]_i_1_n_0 ; + wire \Probe_out_reg_int[13]_i_1_n_0 ; + wire \Probe_out_reg_int[14]_i_1_n_0 ; + wire \Probe_out_reg_int[15]_i_1_n_0 ; + wire \Probe_out_reg_int[1]_i_2_n_0 ; + wire \Probe_out_reg_int[4]_i_1_n_0 ; + wire \Probe_out_reg_int[5]_i_1_n_0 ; + wire \Probe_out_reg_int[6]_i_1_n_0 ; + wire \Probe_out_reg_int[7]_i_1_n_0 ; + wire \Probe_out_reg_int[8]_i_1_n_0 ; + wire \Probe_out_reg_int[9]_i_1_n_0 ; + wire \Probe_out_reg_int_reg[10]_0 ; + wire \Probe_out_reg_int_reg[11]_0 ; + wire \Probe_out_reg_int_reg[12]_0 ; + wire \Probe_out_reg_int_reg[13]_0 ; + wire \Probe_out_reg_int_reg[14]_0 ; + wire \Probe_out_reg_int_reg[15]_0 ; + wire [3:0]\Probe_out_reg_int_reg[3]_0 ; + wire \Probe_out_reg_int_reg[4]_0 ; + wire \Probe_out_reg_int_reg[5]_0 ; + wire \Probe_out_reg_int_reg[6]_0 ; + wire \Probe_out_reg_int_reg[7]_0 ; + wire \Probe_out_reg_int_reg[8]_0 ; + wire \Probe_out_reg_int_reg[9]_0 ; + wire [15:0]Q; + wire [0:0]SR; + wire \addr_count[1]_i_5 ; + wire [2:0]\addr_p1_reg[2]_0 ; + wire clk; + wire in0; + wire internal_cnt_rst; + wire out; + wire [1:0]probe_out0; + wire [0:0]probe_out1; + wire [31:0]probe_out2; + wire [1:0]probe_out3; + wire [3:0]probe_out4; + wire [3:0]probe_out_mem; + wire [16:0]s_daddr_o; + wire s_den_o; + wire s_dwe_o; + wire [4:0]wr_probe_out; + + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE Committ_1_reg + (.C(clk), + .CE(1'b1), + .D(in0), + .Q(Committ_1), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE Committ_2_reg + (.C(clk), + .CE(1'b1), + .D(Committ_1), + .Q(Committ_2), + .R(1'b0)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one \G_PROBE_OUT[0].PROBE_OUT0_INST + (.D({\G_PROBE_OUT[0].PROBE_OUT0_INST_n_2 ,\G_PROBE_OUT[0].PROBE_OUT0_INST_n_3 }), + .E(Committ_2), + .Q(Q[1:0]), + .SR(SR), + .clk(clk), + .out(out), + .probe_out0(probe_out0), + .wr_probe_out(wr_probe_out[0])); + LUT4 #( + .INIT(16'h0200)) + \G_PROBE_OUT[0].wr_probe_out[0]_i_1 + (.I0(\G_PROBE_OUT[0].wr_probe_out[0]_i_2_n_0 ), + .I1(\G_PROBE_OUT[0].wr_probe_out_reg[0]_0 ), + .I2(\G_PROBE_OUT[0].wr_probe_out_reg[0]_1 ), + .I3(\G_PROBE_OUT[0].wr_probe_out_reg[0]_2 ), + .O(\G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000000000004)) + \G_PROBE_OUT[0].wr_probe_out[0]_i_2 + (.I0(\G_PROBE_OUT[0].wr_probe_out[0]_i_6_n_0 ), + .I1(s_daddr_o[8]), + .I2(s_daddr_o[9]), + .I3(s_daddr_o[0]), + .I4(s_daddr_o[2]), + .I5(s_daddr_o[3]), + .O(\G_PROBE_OUT[0].wr_probe_out[0]_i_2_n_0 )); + LUT2 #( + .INIT(4'hE)) + \G_PROBE_OUT[0].wr_probe_out[0]_i_6 + (.I0(s_daddr_o[11]), + .I1(s_daddr_o[10]), + .O(\G_PROBE_OUT[0].wr_probe_out[0]_i_6_n_0 )); + FDRE \G_PROBE_OUT[0].wr_probe_out_reg[0] + (.C(out), + .CE(1'b1), + .D(\G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0 ), + .Q(wr_probe_out[0]), + .R(1'b0)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized0 \G_PROBE_OUT[1].PROBE_OUT0_INST + (.E(Committ_2), + .Q(Q[0]), + .SR(SR), + .clk(clk), + .\data_int_reg[0]_0 (\G_PROBE_OUT[1].PROBE_OUT0_INST_n_1 ), + .out(out), + .probe_out1(probe_out1), + .wr_probe_out(wr_probe_out[1])); + LUT4 #( + .INIT(16'hFFF7)) + \G_PROBE_OUT[1].wr_probe_out[1]_i_1 + (.I0(\addr_count[1]_i_5 ), + .I1(s_daddr_o[8]), + .I2(s_daddr_o[6]), + .I3(s_daddr_o[7]), + .O(\G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000004000000)) + \G_PROBE_OUT[1].wr_probe_out[1]_i_2 + (.I0(s_daddr_o[2]), + .I1(s_daddr_o[0]), + .I2(s_daddr_o[1]), + .I3(s_dwe_o), + .I4(s_den_o), + .I5(s_daddr_o[16]), + .O(\G_PROBE_OUT[1].wr_probe_out[1]_i_2_n_0 )); + LUT5 #( + .INIT(32'h00010000)) + \G_PROBE_OUT[1].wr_probe_out[1]_i_3 + (.I0(s_daddr_o[15]), + .I1(s_daddr_o[14]), + .I2(s_daddr_o[12]), + .I3(s_daddr_o[13]), + .I4(\G_PROBE_OUT[2].PROBE_OUT0_INST_n_32 ), + .O(\addr_count[1]_i_5 )); + FDRE \G_PROBE_OUT[1].wr_probe_out_reg[1] + (.C(out), + .CE(1'b1), + .D(\G_PROBE_OUT[1].wr_probe_out[1]_i_2_n_0 ), + .Q(wr_probe_out[1]), + .R(\G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0 )); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized1 \G_PROBE_OUT[2].PROBE_OUT0_INST + (.\Bus_Data_out_int_reg[15]_0 (Bus_Data_out_int), + .E(\G_PROBE_OUT[2].wr_probe_out_reg ), + .\Probe_out_reg[31]_0 (Committ_2), + .Q(Q), + .SR(SR), + .\addr_count[1]_i_5_0 (\G_PROBE_OUT[2].PROBE_OUT0_INST_n_32 ), + .clk(clk), + .internal_cnt_rst(internal_cnt_rst), + .out(out), + .probe_out2(probe_out2), + .s_daddr_o(s_daddr_o), + .s_den_o(s_den_o), + .s_dwe_o(s_dwe_o)); + LUT6 #( + .INIT(64'h0000000800000000)) + \G_PROBE_OUT[2].wr_probe_out[2]_i_1 + (.I0(s_dwe_o), + .I1(s_den_o), + .I2(s_daddr_o[16]), + .I3(s_daddr_o[2]), + .I4(s_daddr_o[0]), + .I5(s_daddr_o[1]), + .O(\G_PROBE_OUT[2].wr_probe_out[2]_i_1_n_0 )); + FDRE \G_PROBE_OUT[2].wr_probe_out_reg[2] + (.C(out), + .CE(1'b1), + .D(\G_PROBE_OUT[2].wr_probe_out[2]_i_1_n_0 ), + .Q(\G_PROBE_OUT[2].wr_probe_out_reg ), + .R(\G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0 )); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized2 \G_PROBE_OUT[3].PROBE_OUT0_INST + (.D({\G_PROBE_OUT[3].PROBE_OUT0_INST_n_2 ,\G_PROBE_OUT[3].PROBE_OUT0_INST_n_3 }), + .\Probe_out_reg[1]_0 (Committ_2), + .Q(Q[1:0]), + .SR(SR), + .clk(clk), + .out(out), + .probe_out3(probe_out3), + .wr_probe_out(wr_probe_out[3])); + LUT6 #( + .INIT(64'h0008000000000000)) + \G_PROBE_OUT[3].wr_probe_out[3]_i_1 + (.I0(s_dwe_o), + .I1(s_den_o), + .I2(s_daddr_o[16]), + .I3(s_daddr_o[2]), + .I4(s_daddr_o[0]), + .I5(s_daddr_o[1]), + .O(\G_PROBE_OUT[3].wr_probe_out[3]_i_1_n_0 )); + FDRE \G_PROBE_OUT[3].wr_probe_out_reg[3] + (.C(out), + .CE(1'b1), + .D(\G_PROBE_OUT[3].wr_probe_out[3]_i_1_n_0 ), + .Q(wr_probe_out[3]), + .R(\G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0 )); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized3 \G_PROBE_OUT[4].PROBE_OUT0_INST + (.E(wr_probe_out[4]), + .\Probe_out_reg[3]_0 (Committ_2), + .Q({\G_PROBE_OUT[4].PROBE_OUT0_INST_n_4 ,\G_PROBE_OUT[4].PROBE_OUT0_INST_n_5 ,\G_PROBE_OUT[4].PROBE_OUT0_INST_n_6 ,\G_PROBE_OUT[4].PROBE_OUT0_INST_n_7 }), + .SR(SR), + .clk(clk), + .\data_int_reg[3]_0 (Q[3:0]), + .out(out), + .probe_out4(probe_out4)); + LUT6 #( + .INIT(64'h0000000004000000)) + \G_PROBE_OUT[4].wr_probe_out[4]_i_1 + (.I0(s_daddr_o[0]), + .I1(s_daddr_o[2]), + .I2(s_daddr_o[1]), + .I3(s_dwe_o), + .I4(s_den_o), + .I5(s_daddr_o[16]), + .O(\G_PROBE_OUT[4].wr_probe_out[4]_i_1_n_0 )); + FDRE \G_PROBE_OUT[4].wr_probe_out_reg[4] + (.C(out), + .CE(1'b1), + .D(\G_PROBE_OUT[4].wr_probe_out[4]_i_1_n_0 ), + .Q(wr_probe_out[4]), + .R(\G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT3 #( + .INIT(8'hB8)) + \Probe_out_reg_int[0]_i_1 + (.I0(\G_PROBE_OUT[4].PROBE_OUT0_INST_n_7 ), + .I1(\addr_p1_reg[2]_0 [2]), + .I2(\Probe_out_reg_int[0]_i_2_n_0 ), + .O(probe_out_mem[0])); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \Probe_out_reg_int[0]_i_2 + (.I0(\G_PROBE_OUT[3].PROBE_OUT0_INST_n_3 ), + .I1(Bus_Data_out_int[0]), + .I2(\addr_p1_reg[2]_0 [1]), + .I3(\G_PROBE_OUT[1].PROBE_OUT0_INST_n_1 ), + .I4(\addr_p1_reg[2]_0 [0]), + .I5(\G_PROBE_OUT[0].PROBE_OUT0_INST_n_3 ), + .O(\Probe_out_reg_int[0]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT3 #( + .INIT(8'h20)) + \Probe_out_reg_int[10]_i_1 + (.I0(\addr_p1_reg[2]_0 [1]), + .I1(\addr_p1_reg[2]_0 [0]), + .I2(Bus_Data_out_int[10]), + .O(\Probe_out_reg_int[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'h20)) + \Probe_out_reg_int[11]_i_1 + (.I0(\addr_p1_reg[2]_0 [1]), + .I1(\addr_p1_reg[2]_0 [0]), + .I2(Bus_Data_out_int[11]), + .O(\Probe_out_reg_int[11]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT3 #( + .INIT(8'h20)) + \Probe_out_reg_int[12]_i_1 + (.I0(\addr_p1_reg[2]_0 [1]), + .I1(\addr_p1_reg[2]_0 [0]), + .I2(Bus_Data_out_int[12]), + .O(\Probe_out_reg_int[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT3 #( + .INIT(8'h20)) + \Probe_out_reg_int[13]_i_1 + (.I0(\addr_p1_reg[2]_0 [1]), + .I1(\addr_p1_reg[2]_0 [0]), + .I2(Bus_Data_out_int[13]), + .O(\Probe_out_reg_int[13]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT3 #( + .INIT(8'h20)) + \Probe_out_reg_int[14]_i_1 + (.I0(\addr_p1_reg[2]_0 [1]), + .I1(\addr_p1_reg[2]_0 [0]), + .I2(Bus_Data_out_int[14]), + .O(\Probe_out_reg_int[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT3 #( + .INIT(8'h20)) + \Probe_out_reg_int[15]_i_1 + (.I0(\addr_p1_reg[2]_0 [1]), + .I1(\addr_p1_reg[2]_0 [0]), + .I2(Bus_Data_out_int[15]), + .O(\Probe_out_reg_int[15]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT3 #( + .INIT(8'hB8)) + \Probe_out_reg_int[1]_i_1 + (.I0(\G_PROBE_OUT[4].PROBE_OUT0_INST_n_6 ), + .I1(\addr_p1_reg[2]_0 [2]), + .I2(\Probe_out_reg_int[1]_i_2_n_0 ), + .O(probe_out_mem[1])); + LUT5 #( + .INIT(32'hA0A0CFC0)) + \Probe_out_reg_int[1]_i_2 + (.I0(\G_PROBE_OUT[3].PROBE_OUT0_INST_n_2 ), + .I1(Bus_Data_out_int[1]), + .I2(\addr_p1_reg[2]_0 [1]), + .I3(\G_PROBE_OUT[0].PROBE_OUT0_INST_n_2 ), + .I4(\addr_p1_reg[2]_0 [0]), + .O(\Probe_out_reg_int[1]_i_2_n_0 )); + LUT5 #( + .INIT(32'h88B88888)) + \Probe_out_reg_int[2]_i_1 + (.I0(\G_PROBE_OUT[4].PROBE_OUT0_INST_n_5 ), + .I1(\addr_p1_reg[2]_0 [2]), + .I2(\addr_p1_reg[2]_0 [1]), + .I3(\addr_p1_reg[2]_0 [0]), + .I4(Bus_Data_out_int[2]), + .O(probe_out_mem[2])); + LUT5 #( + .INIT(32'h88B88888)) + \Probe_out_reg_int[3]_i_1 + (.I0(\G_PROBE_OUT[4].PROBE_OUT0_INST_n_4 ), + .I1(\addr_p1_reg[2]_0 [2]), + .I2(\addr_p1_reg[2]_0 [1]), + .I3(\addr_p1_reg[2]_0 [0]), + .I4(Bus_Data_out_int[3]), + .O(probe_out_mem[3])); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'h20)) + \Probe_out_reg_int[4]_i_1 + (.I0(\addr_p1_reg[2]_0 [1]), + .I1(\addr_p1_reg[2]_0 [0]), + .I2(Bus_Data_out_int[4]), + .O(\Probe_out_reg_int[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'h20)) + \Probe_out_reg_int[5]_i_1 + (.I0(\addr_p1_reg[2]_0 [1]), + .I1(\addr_p1_reg[2]_0 [0]), + .I2(Bus_Data_out_int[5]), + .O(\Probe_out_reg_int[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'h20)) + \Probe_out_reg_int[6]_i_1 + (.I0(\addr_p1_reg[2]_0 [1]), + .I1(\addr_p1_reg[2]_0 [0]), + .I2(Bus_Data_out_int[6]), + .O(\Probe_out_reg_int[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'h20)) + \Probe_out_reg_int[7]_i_1 + (.I0(\addr_p1_reg[2]_0 [1]), + .I1(\addr_p1_reg[2]_0 [0]), + .I2(Bus_Data_out_int[7]), + .O(\Probe_out_reg_int[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT3 #( + .INIT(8'h20)) + \Probe_out_reg_int[8]_i_1 + (.I0(\addr_p1_reg[2]_0 [1]), + .I1(\addr_p1_reg[2]_0 [0]), + .I2(Bus_Data_out_int[8]), + .O(\Probe_out_reg_int[8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'h20)) + \Probe_out_reg_int[9]_i_1 + (.I0(\addr_p1_reg[2]_0 [1]), + .I1(\addr_p1_reg[2]_0 [0]), + .I2(Bus_Data_out_int[9]), + .O(\Probe_out_reg_int[9]_i_1_n_0 )); + FDRE \Probe_out_reg_int_reg[0] + (.C(out), + .CE(1'b1), + .D(probe_out_mem[0]), + .Q(\Probe_out_reg_int_reg[3]_0 [0]), + .R(1'b0)); + FDRE \Probe_out_reg_int_reg[10] + (.C(out), + .CE(1'b1), + .D(\Probe_out_reg_int[10]_i_1_n_0 ), + .Q(\Probe_out_reg_int_reg[10]_0 ), + .R(\addr_p1_reg[2]_0 [2])); + FDRE \Probe_out_reg_int_reg[11] + (.C(out), + .CE(1'b1), + .D(\Probe_out_reg_int[11]_i_1_n_0 ), + .Q(\Probe_out_reg_int_reg[11]_0 ), + .R(\addr_p1_reg[2]_0 [2])); + FDRE \Probe_out_reg_int_reg[12] + (.C(out), + .CE(1'b1), + .D(\Probe_out_reg_int[12]_i_1_n_0 ), + .Q(\Probe_out_reg_int_reg[12]_0 ), + .R(\addr_p1_reg[2]_0 [2])); + FDRE \Probe_out_reg_int_reg[13] + (.C(out), + .CE(1'b1), + .D(\Probe_out_reg_int[13]_i_1_n_0 ), + .Q(\Probe_out_reg_int_reg[13]_0 ), + .R(\addr_p1_reg[2]_0 [2])); + FDRE \Probe_out_reg_int_reg[14] + (.C(out), + .CE(1'b1), + .D(\Probe_out_reg_int[14]_i_1_n_0 ), + .Q(\Probe_out_reg_int_reg[14]_0 ), + .R(\addr_p1_reg[2]_0 [2])); + FDRE \Probe_out_reg_int_reg[15] + (.C(out), + .CE(1'b1), + .D(\Probe_out_reg_int[15]_i_1_n_0 ), + .Q(\Probe_out_reg_int_reg[15]_0 ), + .R(\addr_p1_reg[2]_0 [2])); + FDRE \Probe_out_reg_int_reg[1] + (.C(out), + .CE(1'b1), + .D(probe_out_mem[1]), + .Q(\Probe_out_reg_int_reg[3]_0 [1]), + .R(1'b0)); + FDRE \Probe_out_reg_int_reg[2] + (.C(out), + .CE(1'b1), + .D(probe_out_mem[2]), + .Q(\Probe_out_reg_int_reg[3]_0 [2]), + .R(1'b0)); + FDRE \Probe_out_reg_int_reg[3] + (.C(out), + .CE(1'b1), + .D(probe_out_mem[3]), + .Q(\Probe_out_reg_int_reg[3]_0 [3]), + .R(1'b0)); + FDRE \Probe_out_reg_int_reg[4] + (.C(out), + .CE(1'b1), + .D(\Probe_out_reg_int[4]_i_1_n_0 ), + .Q(\Probe_out_reg_int_reg[4]_0 ), + .R(\addr_p1_reg[2]_0 [2])); + FDRE \Probe_out_reg_int_reg[5] + (.C(out), + .CE(1'b1), + .D(\Probe_out_reg_int[5]_i_1_n_0 ), + .Q(\Probe_out_reg_int_reg[5]_0 ), + .R(\addr_p1_reg[2]_0 [2])); + FDRE \Probe_out_reg_int_reg[6] + (.C(out), + .CE(1'b1), + .D(\Probe_out_reg_int[6]_i_1_n_0 ), + .Q(\Probe_out_reg_int_reg[6]_0 ), + .R(\addr_p1_reg[2]_0 [2])); + FDRE \Probe_out_reg_int_reg[7] + (.C(out), + .CE(1'b1), + .D(\Probe_out_reg_int[7]_i_1_n_0 ), + .Q(\Probe_out_reg_int_reg[7]_0 ), + .R(\addr_p1_reg[2]_0 [2])); + FDRE \Probe_out_reg_int_reg[8] + (.C(out), + .CE(1'b1), + .D(\Probe_out_reg_int[8]_i_1_n_0 ), + .Q(\Probe_out_reg_int_reg[8]_0 ), + .R(\addr_p1_reg[2]_0 [2])); + FDRE \Probe_out_reg_int_reg[9] + (.C(out), + .CE(1'b1), + .D(\Probe_out_reg_int[9]_i_1_n_0 ), + .Q(\Probe_out_reg_int_reg[9]_0 ), + .R(\addr_p1_reg[2]_0 [2])); + FDRE \addr_p1_reg[0] + (.C(out), + .CE(1'b1), + .D(s_daddr_o[0]), + .Q(\addr_p1_reg[2]_0 [0]), + .R(1'b0)); + FDRE \addr_p1_reg[1] + (.C(out), + .CE(1'b1), + .D(s_daddr_o[1]), + .Q(\addr_p1_reg[2]_0 [1]), + .R(1'b0)); + FDRE \addr_p1_reg[2] + (.C(out), + .CE(1'b1), + .D(s_daddr_o[2]), + .Q(\addr_p1_reg[2]_0 [2]), + .R(1'b0)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one + (probe_out0, + D, + SR, + Q, + wr_probe_out, + out, + E, + clk); + output [1:0]probe_out0; + output [1:0]D; + input [0:0]SR; + input [1:0]Q; + input [0:0]wr_probe_out; + input out; + input [0:0]E; + input clk; + + wire [1:0]D; + wire [0:0]E; + wire [1:0]Q; + (* DIRECT_RESET *) wire [0:0]SR; + wire clk; + wire \data_int[0]_i_1_n_0 ; + wire \data_int[1]_i_1_n_0 ; + wire out; + (* DONT_TOUCH *) wire [1:0]probe_out0; + wire [0:0]wr_probe_out; + + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[0] + (.C(clk), + .CE(E), + .D(D[0]), + .Q(probe_out0[0]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDSE \Probe_out_reg[1] + (.C(clk), + .CE(E), + .D(D[1]), + .Q(probe_out0[1]), + .S(SR)); + LUT3 #( + .INIT(8'hB8)) + \data_int[0]_i_1 + (.I0(Q[0]), + .I1(wr_probe_out), + .I2(D[0]), + .O(\data_int[0]_i_1_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \data_int[1]_i_1 + (.I0(Q[1]), + .I1(wr_probe_out), + .I2(D[1]), + .O(\data_int[1]_i_1_n_0 )); + FDRE \data_int_reg[0] + (.C(out), + .CE(1'b1), + .D(\data_int[0]_i_1_n_0 ), + .Q(D[0]), + .R(SR)); + FDSE \data_int_reg[1] + (.C(out), + .CE(1'b1), + .D(\data_int[1]_i_1_n_0 ), + .Q(D[1]), + .S(SR)); +endmodule + +(* ORIG_REF_NAME = "vio_v3_0_20_probe_out_one" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized0 + (probe_out1, + \data_int_reg[0]_0 , + SR, + E, + clk, + out, + Q, + wr_probe_out); + output [0:0]probe_out1; + output \data_int_reg[0]_0 ; + input [0:0]SR; + input [0:0]E; + input clk; + input out; + input [0:0]Q; + input [0:0]wr_probe_out; + + wire [0:0]E; + wire [0:0]Q; + (* DIRECT_RESET *) wire [0:0]SR; + wire clk; + wire \data_int[0]_i_1_n_0 ; + wire \data_int_reg[0]_0 ; + wire out; + (* DONT_TOUCH *) wire [0:0]probe_out1; + wire [0:0]wr_probe_out; + + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[0] + (.C(clk), + .CE(E), + .D(\data_int_reg[0]_0 ), + .Q(probe_out1), + .R(SR)); + LUT3 #( + .INIT(8'hB8)) + \data_int[0]_i_1 + (.I0(Q), + .I1(wr_probe_out), + .I2(\data_int_reg[0]_0 ), + .O(\data_int[0]_i_1_n_0 )); + FDRE \data_int_reg[0] + (.C(out), + .CE(1'b1), + .D(\data_int[0]_i_1_n_0 ), + .Q(\data_int_reg[0]_0 ), + .R(SR)); +endmodule + +(* ORIG_REF_NAME = "vio_v3_0_20_probe_out_one" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized1 + (probe_out2, + \addr_count[1]_i_5_0 , + \Bus_Data_out_int_reg[15]_0 , + SR, + s_daddr_o, + s_dwe_o, + s_den_o, + internal_cnt_rst, + out, + E, + Q, + \Probe_out_reg[31]_0 , + clk); + output [31:0]probe_out2; + output \addr_count[1]_i_5_0 ; + output [15:0]\Bus_Data_out_int_reg[15]_0 ; + input [0:0]SR; + input [16:0]s_daddr_o; + input s_dwe_o; + input s_den_o; + input internal_cnt_rst; + input out; + input [0:0]E; + input [15:0]Q; + input [0:0]\Probe_out_reg[31]_0 ; + input clk; + + wire \Bus_Data_out_int[0]_i_1_n_0 ; + wire \Bus_Data_out_int[10]_i_1_n_0 ; + wire \Bus_Data_out_int[11]_i_1_n_0 ; + wire \Bus_Data_out_int[12]_i_1_n_0 ; + wire \Bus_Data_out_int[13]_i_1_n_0 ; + wire \Bus_Data_out_int[14]_i_1_n_0 ; + wire \Bus_Data_out_int[15]_i_1_n_0 ; + wire \Bus_Data_out_int[1]_i_1_n_0 ; + wire \Bus_Data_out_int[2]_i_1_n_0 ; + wire \Bus_Data_out_int[3]_i_1_n_0 ; + wire \Bus_Data_out_int[4]_i_1_n_0 ; + wire \Bus_Data_out_int[5]_i_1_n_0 ; + wire \Bus_Data_out_int[6]_i_1_n_0 ; + wire \Bus_Data_out_int[7]_i_1_n_0 ; + wire \Bus_Data_out_int[8]_i_1_n_0 ; + wire \Bus_Data_out_int[9]_i_1_n_0 ; + wire [15:0]\Bus_Data_out_int_reg[15]_0 ; + wire [0:0]E; + wire [0:0]\Probe_out_reg[31]_0 ; + wire [15:0]Q; + (* DIRECT_RESET *) wire [0:0]SR; + wire [1:0]addr_count; + wire \addr_count[0]_i_1_n_0 ; + wire \addr_count[1]_i_1_n_0 ; + wire \addr_count[1]_i_3_n_0 ; + wire \addr_count[1]_i_4_n_0 ; + wire \addr_count[1]_i_5_0 ; + wire clk; + wire internal_cnt_rst; + wire [31:0]\mem_probe_out[0] ; + wire out; + (* DONT_TOUCH *) wire [31:0]probe_out2; + wire [2:2]rd_probe_out; + wire [16:0]s_daddr_o; + wire s_den_o; + wire s_dwe_o; + + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT3 #( + .INIT(8'hB8)) + \Bus_Data_out_int[0]_i_1 + (.I0(\mem_probe_out[0] [16]), + .I1(addr_count[0]), + .I2(\mem_probe_out[0] [0]), + .O(\Bus_Data_out_int[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT3 #( + .INIT(8'hB8)) + \Bus_Data_out_int[10]_i_1 + (.I0(\mem_probe_out[0] [26]), + .I1(addr_count[0]), + .I2(\mem_probe_out[0] [10]), + .O(\Bus_Data_out_int[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT3 #( + .INIT(8'hB8)) + \Bus_Data_out_int[11]_i_1 + (.I0(\mem_probe_out[0] [27]), + .I1(addr_count[0]), + .I2(\mem_probe_out[0] [11]), + .O(\Bus_Data_out_int[11]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT3 #( + .INIT(8'hB8)) + \Bus_Data_out_int[12]_i_1 + (.I0(\mem_probe_out[0] [28]), + .I1(addr_count[0]), + .I2(\mem_probe_out[0] [12]), + .O(\Bus_Data_out_int[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT3 #( + .INIT(8'hB8)) + \Bus_Data_out_int[13]_i_1 + (.I0(\mem_probe_out[0] [29]), + .I1(addr_count[0]), + .I2(\mem_probe_out[0] [13]), + .O(\Bus_Data_out_int[13]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT3 #( + .INIT(8'hB8)) + \Bus_Data_out_int[14]_i_1 + (.I0(\mem_probe_out[0] [30]), + .I1(addr_count[0]), + .I2(\mem_probe_out[0] [14]), + .O(\Bus_Data_out_int[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT3 #( + .INIT(8'hB8)) + \Bus_Data_out_int[15]_i_1 + (.I0(\mem_probe_out[0] [31]), + .I1(addr_count[0]), + .I2(\mem_probe_out[0] [15]), + .O(\Bus_Data_out_int[15]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT3 #( + .INIT(8'hB8)) + \Bus_Data_out_int[1]_i_1 + (.I0(\mem_probe_out[0] [17]), + .I1(addr_count[0]), + .I2(\mem_probe_out[0] [1]), + .O(\Bus_Data_out_int[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT3 #( + .INIT(8'hB8)) + \Bus_Data_out_int[2]_i_1 + (.I0(\mem_probe_out[0] [18]), + .I1(addr_count[0]), + .I2(\mem_probe_out[0] [2]), + .O(\Bus_Data_out_int[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT3 #( + .INIT(8'hB8)) + \Bus_Data_out_int[3]_i_1 + (.I0(\mem_probe_out[0] [19]), + .I1(addr_count[0]), + .I2(\mem_probe_out[0] [3]), + .O(\Bus_Data_out_int[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT3 #( + .INIT(8'hB8)) + \Bus_Data_out_int[4]_i_1 + (.I0(\mem_probe_out[0] [20]), + .I1(addr_count[0]), + .I2(\mem_probe_out[0] [4]), + .O(\Bus_Data_out_int[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT3 #( + .INIT(8'hB8)) + \Bus_Data_out_int[5]_i_1 + (.I0(\mem_probe_out[0] [21]), + .I1(addr_count[0]), + .I2(\mem_probe_out[0] [5]), + .O(\Bus_Data_out_int[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'hB8)) + \Bus_Data_out_int[6]_i_1 + (.I0(\mem_probe_out[0] [22]), + .I1(addr_count[0]), + .I2(\mem_probe_out[0] [6]), + .O(\Bus_Data_out_int[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'hB8)) + \Bus_Data_out_int[7]_i_1 + (.I0(\mem_probe_out[0] [23]), + .I1(addr_count[0]), + .I2(\mem_probe_out[0] [7]), + .O(\Bus_Data_out_int[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT3 #( + .INIT(8'hB8)) + \Bus_Data_out_int[8]_i_1 + (.I0(\mem_probe_out[0] [24]), + .I1(addr_count[0]), + .I2(\mem_probe_out[0] [8]), + .O(\Bus_Data_out_int[8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT3 #( + .INIT(8'hB8)) + \Bus_Data_out_int[9]_i_1 + (.I0(\mem_probe_out[0] [25]), + .I1(addr_count[0]), + .I2(\mem_probe_out[0] [9]), + .O(\Bus_Data_out_int[9]_i_1_n_0 )); + FDRE \Bus_Data_out_int_reg[0] + (.C(out), + .CE(1'b1), + .D(\Bus_Data_out_int[0]_i_1_n_0 ), + .Q(\Bus_Data_out_int_reg[15]_0 [0]), + .R(1'b0)); + FDRE \Bus_Data_out_int_reg[10] + (.C(out), + .CE(1'b1), + .D(\Bus_Data_out_int[10]_i_1_n_0 ), + .Q(\Bus_Data_out_int_reg[15]_0 [10]), + .R(1'b0)); + FDRE \Bus_Data_out_int_reg[11] + (.C(out), + .CE(1'b1), + .D(\Bus_Data_out_int[11]_i_1_n_0 ), + .Q(\Bus_Data_out_int_reg[15]_0 [11]), + .R(1'b0)); + FDRE \Bus_Data_out_int_reg[12] + (.C(out), + .CE(1'b1), + .D(\Bus_Data_out_int[12]_i_1_n_0 ), + .Q(\Bus_Data_out_int_reg[15]_0 [12]), + .R(1'b0)); + FDRE \Bus_Data_out_int_reg[13] + (.C(out), + .CE(1'b1), + .D(\Bus_Data_out_int[13]_i_1_n_0 ), + .Q(\Bus_Data_out_int_reg[15]_0 [13]), + .R(1'b0)); + FDRE \Bus_Data_out_int_reg[14] + (.C(out), + .CE(1'b1), + .D(\Bus_Data_out_int[14]_i_1_n_0 ), + .Q(\Bus_Data_out_int_reg[15]_0 [14]), + .R(1'b0)); + FDRE \Bus_Data_out_int_reg[15] + (.C(out), + .CE(1'b1), + .D(\Bus_Data_out_int[15]_i_1_n_0 ), + .Q(\Bus_Data_out_int_reg[15]_0 [15]), + .R(1'b0)); + FDRE \Bus_Data_out_int_reg[1] + (.C(out), + .CE(1'b1), + .D(\Bus_Data_out_int[1]_i_1_n_0 ), + .Q(\Bus_Data_out_int_reg[15]_0 [1]), + .R(1'b0)); + FDRE \Bus_Data_out_int_reg[2] + (.C(out), + .CE(1'b1), + .D(\Bus_Data_out_int[2]_i_1_n_0 ), + .Q(\Bus_Data_out_int_reg[15]_0 [2]), + .R(1'b0)); + FDRE \Bus_Data_out_int_reg[3] + (.C(out), + .CE(1'b1), + .D(\Bus_Data_out_int[3]_i_1_n_0 ), + .Q(\Bus_Data_out_int_reg[15]_0 [3]), + .R(1'b0)); + FDRE \Bus_Data_out_int_reg[4] + (.C(out), + .CE(1'b1), + .D(\Bus_Data_out_int[4]_i_1_n_0 ), + .Q(\Bus_Data_out_int_reg[15]_0 [4]), + .R(1'b0)); + FDRE \Bus_Data_out_int_reg[5] + (.C(out), + .CE(1'b1), + .D(\Bus_Data_out_int[5]_i_1_n_0 ), + .Q(\Bus_Data_out_int_reg[15]_0 [5]), + .R(1'b0)); + FDRE \Bus_Data_out_int_reg[6] + (.C(out), + .CE(1'b1), + .D(\Bus_Data_out_int[6]_i_1_n_0 ), + .Q(\Bus_Data_out_int_reg[15]_0 [6]), + .R(1'b0)); + FDRE \Bus_Data_out_int_reg[7] + (.C(out), + .CE(1'b1), + .D(\Bus_Data_out_int[7]_i_1_n_0 ), + .Q(\Bus_Data_out_int_reg[15]_0 [7]), + .R(1'b0)); + FDRE \Bus_Data_out_int_reg[8] + (.C(out), + .CE(1'b1), + .D(\Bus_Data_out_int[8]_i_1_n_0 ), + .Q(\Bus_Data_out_int_reg[15]_0 [8]), + .R(1'b0)); + FDRE \Bus_Data_out_int_reg[9] + (.C(out), + .CE(1'b1), + .D(\Bus_Data_out_int[9]_i_1_n_0 ), + .Q(\Bus_Data_out_int_reg[15]_0 [9]), + .R(1'b0)); + FDRE \LOOP_I[1].data_int_reg[16] + (.C(out), + .CE(E), + .D(\mem_probe_out[0] [0]), + .Q(\mem_probe_out[0] [16]), + .R(SR)); + FDRE \LOOP_I[1].data_int_reg[17] + (.C(out), + .CE(E), + .D(\mem_probe_out[0] [1]), + .Q(\mem_probe_out[0] [17]), + .R(SR)); + FDRE \LOOP_I[1].data_int_reg[18] + (.C(out), + .CE(E), + .D(\mem_probe_out[0] [2]), + .Q(\mem_probe_out[0] [18]), + .R(SR)); + FDRE \LOOP_I[1].data_int_reg[19] + (.C(out), + .CE(E), + .D(\mem_probe_out[0] [3]), + .Q(\mem_probe_out[0] [19]), + .R(SR)); + FDRE \LOOP_I[1].data_int_reg[20] + (.C(out), + .CE(E), + .D(\mem_probe_out[0] [4]), + .Q(\mem_probe_out[0] [20]), + .R(SR)); + FDRE \LOOP_I[1].data_int_reg[21] + (.C(out), + .CE(E), + .D(\mem_probe_out[0] [5]), + .Q(\mem_probe_out[0] [21]), + .R(SR)); + FDRE \LOOP_I[1].data_int_reg[22] + (.C(out), + .CE(E), + .D(\mem_probe_out[0] [6]), + .Q(\mem_probe_out[0] [22]), + .R(SR)); + FDRE \LOOP_I[1].data_int_reg[23] + (.C(out), + .CE(E), + .D(\mem_probe_out[0] [7]), + .Q(\mem_probe_out[0] [23]), + .R(SR)); + FDRE \LOOP_I[1].data_int_reg[24] + (.C(out), + .CE(E), + .D(\mem_probe_out[0] [8]), + .Q(\mem_probe_out[0] [24]), + .R(SR)); + FDRE \LOOP_I[1].data_int_reg[25] + (.C(out), + .CE(E), + .D(\mem_probe_out[0] [9]), + .Q(\mem_probe_out[0] [25]), + .R(SR)); + FDRE \LOOP_I[1].data_int_reg[26] + (.C(out), + .CE(E), + .D(\mem_probe_out[0] [10]), + .Q(\mem_probe_out[0] [26]), + .R(SR)); + FDRE \LOOP_I[1].data_int_reg[27] + (.C(out), + .CE(E), + .D(\mem_probe_out[0] [11]), + .Q(\mem_probe_out[0] [27]), + .R(SR)); + FDRE \LOOP_I[1].data_int_reg[28] + (.C(out), + .CE(E), + .D(\mem_probe_out[0] [12]), + .Q(\mem_probe_out[0] [28]), + .R(SR)); + FDRE \LOOP_I[1].data_int_reg[29] + (.C(out), + .CE(E), + .D(\mem_probe_out[0] [13]), + .Q(\mem_probe_out[0] [29]), + .R(SR)); + FDRE \LOOP_I[1].data_int_reg[30] + (.C(out), + .CE(E), + .D(\mem_probe_out[0] [14]), + .Q(\mem_probe_out[0] [30]), + .R(SR)); + FDRE \LOOP_I[1].data_int_reg[31] + (.C(out), + .CE(E), + .D(\mem_probe_out[0] [15]), + .Q(\mem_probe_out[0] [31]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[0] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [0]), + .Q(probe_out2[0]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[10] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [10]), + .Q(probe_out2[10]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[11] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [11]), + .Q(probe_out2[11]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[12] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [12]), + .Q(probe_out2[12]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[13] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [13]), + .Q(probe_out2[13]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[14] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [14]), + .Q(probe_out2[14]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[15] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [15]), + .Q(probe_out2[15]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[16] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [16]), + .Q(probe_out2[16]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[17] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [17]), + .Q(probe_out2[17]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[18] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [18]), + .Q(probe_out2[18]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[19] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [19]), + .Q(probe_out2[19]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[1] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [1]), + .Q(probe_out2[1]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[20] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [20]), + .Q(probe_out2[20]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[21] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [21]), + .Q(probe_out2[21]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[22] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [22]), + .Q(probe_out2[22]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[23] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [23]), + .Q(probe_out2[23]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[24] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [24]), + .Q(probe_out2[24]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[25] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [25]), + .Q(probe_out2[25]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[26] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [26]), + .Q(probe_out2[26]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[27] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [27]), + .Q(probe_out2[27]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[28] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [28]), + .Q(probe_out2[28]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[29] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [29]), + .Q(probe_out2[29]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[2] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [2]), + .Q(probe_out2[2]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[30] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [30]), + .Q(probe_out2[30]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[31] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [31]), + .Q(probe_out2[31]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[3] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [3]), + .Q(probe_out2[3]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[4] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [4]), + .Q(probe_out2[4]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[5] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [5]), + .Q(probe_out2[5]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[6] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [6]), + .Q(probe_out2[6]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[7] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [7]), + .Q(probe_out2[7]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[8] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [8]), + .Q(probe_out2[8]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[9] + (.C(clk), + .CE(\Probe_out_reg[31]_0 ), + .D(\mem_probe_out[0] [9]), + .Q(probe_out2[9]), + .R(SR)); + LUT4 #( + .INIT(16'h0322)) + \addr_count[0]_i_1 + (.I0(addr_count[0]), + .I1(internal_cnt_rst), + .I2(addr_count[0]), + .I3(rd_probe_out), + .O(\addr_count[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'h00302222)) + \addr_count[1]_i_1 + (.I0(addr_count[1]), + .I1(internal_cnt_rst), + .I2(addr_count[1]), + .I3(addr_count[0]), + .I4(rd_probe_out), + .O(\addr_count[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000000008000)) + \addr_count[1]_i_2 + (.I0(\addr_count[1]_i_3_n_0 ), + .I1(\addr_count[1]_i_4_n_0 ), + .I2(\addr_count[1]_i_5_0 ), + .I3(s_daddr_o[8]), + .I4(s_daddr_o[6]), + .I5(s_daddr_o[7]), + .O(rd_probe_out)); + LUT6 #( + .INIT(64'h0000000400000000)) + \addr_count[1]_i_3 + (.I0(s_dwe_o), + .I1(s_den_o), + .I2(s_daddr_o[16]), + .I3(s_daddr_o[2]), + .I4(s_daddr_o[0]), + .I5(s_daddr_o[1]), + .O(\addr_count[1]_i_3_n_0 )); + LUT4 #( + .INIT(16'h0001)) + \addr_count[1]_i_4 + (.I0(s_daddr_o[13]), + .I1(s_daddr_o[12]), + .I2(s_daddr_o[14]), + .I3(s_daddr_o[15]), + .O(\addr_count[1]_i_4_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \addr_count[1]_i_5 + (.I0(s_daddr_o[4]), + .I1(s_daddr_o[3]), + .I2(s_daddr_o[5]), + .I3(s_daddr_o[10]), + .I4(s_daddr_o[9]), + .I5(s_daddr_o[11]), + .O(\addr_count[1]_i_5_0 )); + (* MAX_FANOUT = "200" *) + FDRE \addr_count_reg[0] + (.C(out), + .CE(1'b1), + .D(\addr_count[0]_i_1_n_0 ), + .Q(addr_count[0]), + .R(1'b0)); + (* MAX_FANOUT = "200" *) + FDRE \addr_count_reg[1] + (.C(out), + .CE(1'b1), + .D(\addr_count[1]_i_1_n_0 ), + .Q(addr_count[1]), + .R(1'b0)); + FDRE \data_int_reg[0] + (.C(out), + .CE(E), + .D(Q[0]), + .Q(\mem_probe_out[0] [0]), + .R(SR)); + FDRE \data_int_reg[10] + (.C(out), + .CE(E), + .D(Q[10]), + .Q(\mem_probe_out[0] [10]), + .R(SR)); + FDRE \data_int_reg[11] + (.C(out), + .CE(E), + .D(Q[11]), + .Q(\mem_probe_out[0] [11]), + .R(SR)); + FDRE \data_int_reg[12] + (.C(out), + .CE(E), + .D(Q[12]), + .Q(\mem_probe_out[0] [12]), + .R(SR)); + FDRE \data_int_reg[13] + (.C(out), + .CE(E), + .D(Q[13]), + .Q(\mem_probe_out[0] [13]), + .R(SR)); + FDRE \data_int_reg[14] + (.C(out), + .CE(E), + .D(Q[14]), + .Q(\mem_probe_out[0] [14]), + .R(SR)); + FDRE \data_int_reg[15] + (.C(out), + .CE(E), + .D(Q[15]), + .Q(\mem_probe_out[0] [15]), + .R(SR)); + FDRE \data_int_reg[1] + (.C(out), + .CE(E), + .D(Q[1]), + .Q(\mem_probe_out[0] [1]), + .R(SR)); + FDRE \data_int_reg[2] + (.C(out), + .CE(E), + .D(Q[2]), + .Q(\mem_probe_out[0] [2]), + .R(SR)); + FDRE \data_int_reg[3] + (.C(out), + .CE(E), + .D(Q[3]), + .Q(\mem_probe_out[0] [3]), + .R(SR)); + FDRE \data_int_reg[4] + (.C(out), + .CE(E), + .D(Q[4]), + .Q(\mem_probe_out[0] [4]), + .R(SR)); + FDRE \data_int_reg[5] + (.C(out), + .CE(E), + .D(Q[5]), + .Q(\mem_probe_out[0] [5]), + .R(SR)); + FDRE \data_int_reg[6] + (.C(out), + .CE(E), + .D(Q[6]), + .Q(\mem_probe_out[0] [6]), + .R(SR)); + FDRE \data_int_reg[7] + (.C(out), + .CE(E), + .D(Q[7]), + .Q(\mem_probe_out[0] [7]), + .R(SR)); + FDRE \data_int_reg[8] + (.C(out), + .CE(E), + .D(Q[8]), + .Q(\mem_probe_out[0] [8]), + .R(SR)); + FDRE \data_int_reg[9] + (.C(out), + .CE(E), + .D(Q[9]), + .Q(\mem_probe_out[0] [9]), + .R(SR)); +endmodule + +(* ORIG_REF_NAME = "vio_v3_0_20_probe_out_one" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized2 + (probe_out3, + D, + SR, + Q, + wr_probe_out, + out, + \Probe_out_reg[1]_0 , + clk); + output [1:0]probe_out3; + output [1:0]D; + input [0:0]SR; + input [1:0]Q; + input [0:0]wr_probe_out; + input out; + input \Probe_out_reg[1]_0 ; + input clk; + + wire [1:0]D; + wire \Probe_out_reg[1]_0 ; + wire [1:0]Q; + (* DIRECT_RESET *) wire [0:0]SR; + wire clk; + wire \data_int[0]_i_1_n_0 ; + wire \data_int[1]_i_1_n_0 ; + wire out; + (* DONT_TOUCH *) wire [1:0]probe_out3; + wire [0:0]wr_probe_out; + + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDSE \Probe_out_reg[0] + (.C(clk), + .CE(\Probe_out_reg[1]_0 ), + .D(D[0]), + .Q(probe_out3[0]), + .S(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDSE \Probe_out_reg[1] + (.C(clk), + .CE(\Probe_out_reg[1]_0 ), + .D(D[1]), + .Q(probe_out3[1]), + .S(SR)); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT3 #( + .INIT(8'hB8)) + \data_int[0]_i_1 + (.I0(Q[0]), + .I1(wr_probe_out), + .I2(D[0]), + .O(\data_int[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT3 #( + .INIT(8'hB8)) + \data_int[1]_i_1 + (.I0(Q[1]), + .I1(wr_probe_out), + .I2(D[1]), + .O(\data_int[1]_i_1_n_0 )); + FDSE \data_int_reg[0] + (.C(out), + .CE(1'b1), + .D(\data_int[0]_i_1_n_0 ), + .Q(D[0]), + .S(SR)); + FDSE \data_int_reg[1] + (.C(out), + .CE(1'b1), + .D(\data_int[1]_i_1_n_0 ), + .Q(D[1]), + .S(SR)); +endmodule + +(* ORIG_REF_NAME = "vio_v3_0_20_probe_out_one" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized3 + (probe_out4, + Q, + SR, + E, + \data_int_reg[3]_0 , + out, + \Probe_out_reg[3]_0 , + clk); + output [3:0]probe_out4; + output [3:0]Q; + input [0:0]SR; + input [0:0]E; + input [3:0]\data_int_reg[3]_0 ; + input out; + input \Probe_out_reg[3]_0 ; + input clk; + + wire [0:0]E; + wire \Probe_out_reg[3]_0 ; + wire [3:0]Q; + (* DIRECT_RESET *) wire [0:0]SR; + wire clk; + wire [3:0]\data_int_reg[3]_0 ; + wire out; + (* DONT_TOUCH *) wire [3:0]probe_out4; + + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[0] + (.C(clk), + .CE(\Probe_out_reg[3]_0 ), + .D(Q[0]), + .Q(probe_out4[0]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[1] + (.C(clk), + .CE(\Probe_out_reg[3]_0 ), + .D(Q[1]), + .Q(probe_out4[1]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[2] + (.C(clk), + .CE(\Probe_out_reg[3]_0 ), + .D(Q[2]), + .Q(probe_out4[2]), + .R(SR)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + FDRE \Probe_out_reg[3] + (.C(clk), + .CE(\Probe_out_reg[3]_0 ), + .D(Q[3]), + .Q(probe_out4[3]), + .R(SR)); + FDRE \data_int_reg[0] + (.C(out), + .CE(E), + .D(\data_int_reg[3]_0 [0]), + .Q(Q[0]), + .R(SR)); + FDRE \data_int_reg[1] + (.C(out), + .CE(E), + .D(\data_int_reg[3]_0 [1]), + .Q(Q[1]), + .R(SR)); + FDRE \data_int_reg[2] + (.C(out), + .CE(E), + .D(\data_int_reg[3]_0 [2]), + .Q(Q[2]), + .R(SR)); + FDRE \data_int_reg[3] + (.C(out), + .CE(E), + .D(\data_int_reg[3]_0 [3]), + .Q(Q[3]), + .R(SR)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_width + (Q, + rd_probe_out_width, + s_rst_o, + internal_cnt_rst, + out); + output [2:0]Q; + input rd_probe_out_width; + input s_rst_o; + input internal_cnt_rst; + input out; + + wire [2:0]Q; + wire [1:0]addr_count; + wire \addr_count[0]_i_1_n_0 ; + wire \addr_count[1]_i_1_n_0 ; + wire internal_cnt_rst; + wire out; + wire [8:0]probe_width_mem; + wire rd_probe_out_width; + wire s_rst_o; + + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT5 #( + .INIT(32'h0000001A)) + \addr_count[0]_i_1 + (.I0(addr_count[0]), + .I1(addr_count[1]), + .I2(rd_probe_out_width), + .I3(s_rst_o), + .I4(internal_cnt_rst), + .O(\addr_count[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT5 #( + .INIT(32'h0000002C)) + \addr_count[1]_i_1 + (.I0(addr_count[0]), + .I1(addr_count[1]), + .I2(rd_probe_out_width), + .I3(s_rst_o), + .I4(internal_cnt_rst), + .O(\addr_count[1]_i_1_n_0 )); + FDRE \addr_count_reg[0] + (.C(out), + .CE(1'b1), + .D(\addr_count[0]_i_1_n_0 ), + .Q(addr_count[0]), + .R(1'b0)); + FDRE \addr_count_reg[1] + (.C(out), + .CE(1'b1), + .D(\addr_count[1]_i_1_n_0 ), + .Q(addr_count[1]), + .R(1'b0)); + LUT2 #( + .INIT(4'h7)) + \probe_width_int[0]_i_1 + (.I0(addr_count[1]), + .I1(addr_count[0]), + .O(probe_width_mem[0])); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT2 #( + .INIT(4'h6)) + \probe_width_int[1]_i_1 + (.I0(addr_count[0]), + .I1(addr_count[1]), + .O(probe_width_mem[1])); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT2 #( + .INIT(4'h2)) + \probe_width_int[8]_i_1 + (.I0(addr_count[0]), + .I1(addr_count[1]), + .O(probe_width_mem[8])); + FDRE \probe_width_int_reg[0] + (.C(out), + .CE(1'b1), + .D(probe_width_mem[0]), + .Q(Q[0]), + .R(1'b0)); + FDRE \probe_width_int_reg[1] + (.C(out), + .CE(1'b1), + .D(probe_width_mem[1]), + .Q(Q[1]), + .R(1'b0)); + FDRE \probe_width_int_reg[8] + (.C(out), + .CE(1'b1), + .D(probe_width_mem[8]), + .Q(Q[2]), + .R(1'b0)); +endmodule + +(* C_BUILD_REVISION = "0" *) (* C_BUS_ADDR_WIDTH = "17" *) (* C_BUS_DATA_WIDTH = "16" *) +(* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_MAJOR_VER = "2" *) +(* C_CORE_MINOR_ALPHA_VER = "97" *) (* C_CORE_MINOR_VER = "0" *) (* C_CORE_TYPE = "2" *) +(* C_CSE_DRV_VER = "1" *) (* C_EN_PROBE_IN_ACTIVITY = "0" *) (* C_EN_SYNCHRONIZATION = "1" *) +(* C_MAJOR_VERSION = "2013" *) (* C_MAX_NUM_PROBE = "256" *) (* C_MAX_WIDTH_PER_PROBE = "256" *) +(* C_MINOR_VERSION = "1" *) (* C_NEXT_SLAVE = "0" *) (* C_NUM_PROBE_IN = "0" *) +(* C_NUM_PROBE_OUT = "5" *) (* C_PIPE_IFACE = "0" *) (* C_PROBE_IN0_WIDTH = "1" *) +(* C_PROBE_IN100_WIDTH = "1" *) (* C_PROBE_IN101_WIDTH = "1" *) (* C_PROBE_IN102_WIDTH = "1" *) +(* C_PROBE_IN103_WIDTH = "1" *) (* C_PROBE_IN104_WIDTH = "1" *) (* C_PROBE_IN105_WIDTH = "1" *) +(* C_PROBE_IN106_WIDTH = "1" *) (* C_PROBE_IN107_WIDTH = "1" *) (* C_PROBE_IN108_WIDTH = "1" *) +(* C_PROBE_IN109_WIDTH = "1" *) (* C_PROBE_IN10_WIDTH = "1" *) (* C_PROBE_IN110_WIDTH = "1" *) +(* C_PROBE_IN111_WIDTH = "1" *) (* C_PROBE_IN112_WIDTH = "1" *) (* C_PROBE_IN113_WIDTH = "1" *) +(* C_PROBE_IN114_WIDTH = "1" *) (* C_PROBE_IN115_WIDTH = "1" *) (* C_PROBE_IN116_WIDTH = "1" *) +(* C_PROBE_IN117_WIDTH = "1" *) (* C_PROBE_IN118_WIDTH = "1" *) (* C_PROBE_IN119_WIDTH = "1" *) +(* C_PROBE_IN11_WIDTH = "1" *) (* C_PROBE_IN120_WIDTH = "1" *) (* C_PROBE_IN121_WIDTH = "1" *) +(* C_PROBE_IN122_WIDTH = "1" *) (* C_PROBE_IN123_WIDTH = "1" *) (* C_PROBE_IN124_WIDTH = "1" *) +(* C_PROBE_IN125_WIDTH = "1" *) (* C_PROBE_IN126_WIDTH = "1" *) (* C_PROBE_IN127_WIDTH = "1" *) +(* C_PROBE_IN128_WIDTH = "1" *) (* C_PROBE_IN129_WIDTH = "1" *) (* C_PROBE_IN12_WIDTH = "1" *) +(* C_PROBE_IN130_WIDTH = "1" *) (* C_PROBE_IN131_WIDTH = "1" *) (* C_PROBE_IN132_WIDTH = "1" *) +(* C_PROBE_IN133_WIDTH = "1" *) (* C_PROBE_IN134_WIDTH = "1" *) (* C_PROBE_IN135_WIDTH = "1" *) +(* C_PROBE_IN136_WIDTH = "1" *) (* C_PROBE_IN137_WIDTH = "1" *) (* C_PROBE_IN138_WIDTH = "1" *) +(* C_PROBE_IN139_WIDTH = "1" *) (* C_PROBE_IN13_WIDTH = "1" *) (* C_PROBE_IN140_WIDTH = "1" *) +(* C_PROBE_IN141_WIDTH = "1" *) (* C_PROBE_IN142_WIDTH = "1" *) (* C_PROBE_IN143_WIDTH = "1" *) +(* C_PROBE_IN144_WIDTH = "1" *) (* C_PROBE_IN145_WIDTH = "1" *) (* C_PROBE_IN146_WIDTH = "1" *) +(* C_PROBE_IN147_WIDTH = "1" *) (* C_PROBE_IN148_WIDTH = "1" *) (* C_PROBE_IN149_WIDTH = "1" *) +(* C_PROBE_IN14_WIDTH = "1" *) (* C_PROBE_IN150_WIDTH = "1" *) (* C_PROBE_IN151_WIDTH = "1" *) +(* C_PROBE_IN152_WIDTH = "1" *) (* C_PROBE_IN153_WIDTH = "1" *) (* C_PROBE_IN154_WIDTH = "1" *) +(* C_PROBE_IN155_WIDTH = "1" *) (* C_PROBE_IN156_WIDTH = "1" *) (* C_PROBE_IN157_WIDTH = "1" *) +(* C_PROBE_IN158_WIDTH = "1" *) (* C_PROBE_IN159_WIDTH = "1" *) (* C_PROBE_IN15_WIDTH = "1" *) +(* C_PROBE_IN160_WIDTH = "1" *) (* C_PROBE_IN161_WIDTH = "1" *) (* C_PROBE_IN162_WIDTH = "1" *) +(* C_PROBE_IN163_WIDTH = "1" *) (* C_PROBE_IN164_WIDTH = "1" *) (* C_PROBE_IN165_WIDTH = "1" *) +(* C_PROBE_IN166_WIDTH = "1" *) (* C_PROBE_IN167_WIDTH = "1" *) (* C_PROBE_IN168_WIDTH = "1" *) +(* C_PROBE_IN169_WIDTH = "1" *) (* C_PROBE_IN16_WIDTH = "1" *) (* C_PROBE_IN170_WIDTH = "1" *) +(* C_PROBE_IN171_WIDTH = "1" *) (* C_PROBE_IN172_WIDTH = "1" *) (* C_PROBE_IN173_WIDTH = "1" *) +(* C_PROBE_IN174_WIDTH = "1" *) (* C_PROBE_IN175_WIDTH = "1" *) (* C_PROBE_IN176_WIDTH = "1" *) +(* C_PROBE_IN177_WIDTH = "1" *) (* C_PROBE_IN178_WIDTH = "1" *) (* C_PROBE_IN179_WIDTH = "1" *) +(* C_PROBE_IN17_WIDTH = "1" *) (* C_PROBE_IN180_WIDTH = "1" *) (* C_PROBE_IN181_WIDTH = "1" *) +(* C_PROBE_IN182_WIDTH = "1" *) (* C_PROBE_IN183_WIDTH = "1" *) (* C_PROBE_IN184_WIDTH = "1" *) +(* C_PROBE_IN185_WIDTH = "1" *) (* C_PROBE_IN186_WIDTH = "1" *) (* C_PROBE_IN187_WIDTH = "1" *) +(* C_PROBE_IN188_WIDTH = "1" *) (* C_PROBE_IN189_WIDTH = "1" *) (* C_PROBE_IN18_WIDTH = "1" *) +(* C_PROBE_IN190_WIDTH = "1" *) (* C_PROBE_IN191_WIDTH = "1" *) (* C_PROBE_IN192_WIDTH = "1" *) +(* C_PROBE_IN193_WIDTH = "1" *) (* C_PROBE_IN194_WIDTH = "1" *) (* C_PROBE_IN195_WIDTH = "1" *) +(* C_PROBE_IN196_WIDTH = "1" *) (* C_PROBE_IN197_WIDTH = "1" *) (* C_PROBE_IN198_WIDTH = "1" *) +(* C_PROBE_IN199_WIDTH = "1" *) (* C_PROBE_IN19_WIDTH = "1" *) (* C_PROBE_IN1_WIDTH = "1" *) +(* C_PROBE_IN200_WIDTH = "1" *) (* C_PROBE_IN201_WIDTH = "1" *) (* C_PROBE_IN202_WIDTH = "1" *) +(* C_PROBE_IN203_WIDTH = "1" *) (* C_PROBE_IN204_WIDTH = "1" *) (* C_PROBE_IN205_WIDTH = "1" *) +(* C_PROBE_IN206_WIDTH = "1" *) (* C_PROBE_IN207_WIDTH = "1" *) (* C_PROBE_IN208_WIDTH = "1" *) +(* C_PROBE_IN209_WIDTH = "1" *) (* C_PROBE_IN20_WIDTH = "1" *) (* C_PROBE_IN210_WIDTH = "1" *) +(* C_PROBE_IN211_WIDTH = "1" *) (* C_PROBE_IN212_WIDTH = "1" *) (* C_PROBE_IN213_WIDTH = "1" *) +(* C_PROBE_IN214_WIDTH = "1" *) (* C_PROBE_IN215_WIDTH = "1" *) (* C_PROBE_IN216_WIDTH = "1" *) +(* C_PROBE_IN217_WIDTH = "1" *) (* C_PROBE_IN218_WIDTH = "1" *) (* C_PROBE_IN219_WIDTH = "1" *) +(* C_PROBE_IN21_WIDTH = "1" *) (* C_PROBE_IN220_WIDTH = "1" *) (* C_PROBE_IN221_WIDTH = "1" *) +(* C_PROBE_IN222_WIDTH = "1" *) (* C_PROBE_IN223_WIDTH = "1" *) (* C_PROBE_IN224_WIDTH = "1" *) +(* C_PROBE_IN225_WIDTH = "1" *) (* C_PROBE_IN226_WIDTH = "1" *) (* C_PROBE_IN227_WIDTH = "1" *) +(* C_PROBE_IN228_WIDTH = "1" *) (* C_PROBE_IN229_WIDTH = "1" *) (* C_PROBE_IN22_WIDTH = "1" *) +(* C_PROBE_IN230_WIDTH = "1" *) (* C_PROBE_IN231_WIDTH = "1" *) (* C_PROBE_IN232_WIDTH = "1" *) +(* C_PROBE_IN233_WIDTH = "1" *) (* C_PROBE_IN234_WIDTH = "1" *) (* C_PROBE_IN235_WIDTH = "1" *) +(* C_PROBE_IN236_WIDTH = "1" *) (* C_PROBE_IN237_WIDTH = "1" *) (* C_PROBE_IN238_WIDTH = "1" *) +(* C_PROBE_IN239_WIDTH = "1" *) (* C_PROBE_IN23_WIDTH = "1" *) (* C_PROBE_IN240_WIDTH = "1" *) +(* C_PROBE_IN241_WIDTH = "1" *) (* C_PROBE_IN242_WIDTH = "1" *) (* C_PROBE_IN243_WIDTH = "1" *) +(* C_PROBE_IN244_WIDTH = "1" *) (* C_PROBE_IN245_WIDTH = "1" *) (* C_PROBE_IN246_WIDTH = "1" *) +(* C_PROBE_IN247_WIDTH = "1" *) (* C_PROBE_IN248_WIDTH = "1" *) (* C_PROBE_IN249_WIDTH = "1" *) +(* C_PROBE_IN24_WIDTH = "1" *) (* C_PROBE_IN250_WIDTH = "1" *) (* C_PROBE_IN251_WIDTH = "1" *) +(* C_PROBE_IN252_WIDTH = "1" *) (* C_PROBE_IN253_WIDTH = "1" *) (* C_PROBE_IN254_WIDTH = "1" *) +(* C_PROBE_IN255_WIDTH = "1" *) (* C_PROBE_IN25_WIDTH = "1" *) (* C_PROBE_IN26_WIDTH = "1" *) +(* C_PROBE_IN27_WIDTH = "1" *) (* C_PROBE_IN28_WIDTH = "1" *) (* C_PROBE_IN29_WIDTH = "1" *) +(* C_PROBE_IN2_WIDTH = "1" *) (* C_PROBE_IN30_WIDTH = "1" *) (* C_PROBE_IN31_WIDTH = "1" *) +(* C_PROBE_IN32_WIDTH = "1" *) (* C_PROBE_IN33_WIDTH = "1" *) (* C_PROBE_IN34_WIDTH = "1" *) +(* C_PROBE_IN35_WIDTH = "1" *) (* C_PROBE_IN36_WIDTH = "1" *) (* C_PROBE_IN37_WIDTH = "1" *) +(* C_PROBE_IN38_WIDTH = "1" *) (* C_PROBE_IN39_WIDTH = "1" *) (* C_PROBE_IN3_WIDTH = "1" *) +(* C_PROBE_IN40_WIDTH = "1" *) (* C_PROBE_IN41_WIDTH = "1" *) (* C_PROBE_IN42_WIDTH = "1" *) +(* C_PROBE_IN43_WIDTH = "1" *) (* C_PROBE_IN44_WIDTH = "1" *) (* C_PROBE_IN45_WIDTH = "1" *) +(* C_PROBE_IN46_WIDTH = "1" *) (* C_PROBE_IN47_WIDTH = "1" *) (* C_PROBE_IN48_WIDTH = "1" *) +(* C_PROBE_IN49_WIDTH = "1" *) (* C_PROBE_IN4_WIDTH = "1" *) (* C_PROBE_IN50_WIDTH = "1" *) +(* C_PROBE_IN51_WIDTH = "1" *) (* C_PROBE_IN52_WIDTH = "1" *) (* C_PROBE_IN53_WIDTH = "1" *) +(* C_PROBE_IN54_WIDTH = "1" *) (* C_PROBE_IN55_WIDTH = "1" *) (* C_PROBE_IN56_WIDTH = "1" *) +(* C_PROBE_IN57_WIDTH = "1" *) (* C_PROBE_IN58_WIDTH = "1" *) (* C_PROBE_IN59_WIDTH = "1" *) +(* C_PROBE_IN5_WIDTH = "1" *) (* C_PROBE_IN60_WIDTH = "1" *) (* C_PROBE_IN61_WIDTH = "1" *) +(* C_PROBE_IN62_WIDTH = "1" *) (* C_PROBE_IN63_WIDTH = "1" *) (* C_PROBE_IN64_WIDTH = "1" *) +(* C_PROBE_IN65_WIDTH = "1" *) (* C_PROBE_IN66_WIDTH = "1" *) (* C_PROBE_IN67_WIDTH = "1" *) +(* C_PROBE_IN68_WIDTH = "1" *) (* C_PROBE_IN69_WIDTH = "1" *) (* C_PROBE_IN6_WIDTH = "1" *) +(* C_PROBE_IN70_WIDTH = "1" *) (* C_PROBE_IN71_WIDTH = "1" *) (* C_PROBE_IN72_WIDTH = "1" *) +(* C_PROBE_IN73_WIDTH = "1" *) (* C_PROBE_IN74_WIDTH = "1" *) (* C_PROBE_IN75_WIDTH = "1" *) +(* C_PROBE_IN76_WIDTH = "1" *) (* C_PROBE_IN77_WIDTH = "1" *) (* C_PROBE_IN78_WIDTH = "1" *) +(* C_PROBE_IN79_WIDTH = "1" *) (* C_PROBE_IN7_WIDTH = "1" *) (* C_PROBE_IN80_WIDTH = "1" *) +(* C_PROBE_IN81_WIDTH = "1" *) (* C_PROBE_IN82_WIDTH = "1" *) (* C_PROBE_IN83_WIDTH = "1" *) +(* C_PROBE_IN84_WIDTH = "1" *) (* C_PROBE_IN85_WIDTH = "1" *) (* C_PROBE_IN86_WIDTH = "1" *) +(* C_PROBE_IN87_WIDTH = "1" *) (* C_PROBE_IN88_WIDTH = "1" *) (* C_PROBE_IN89_WIDTH = "1" *) +(* C_PROBE_IN8_WIDTH = "1" *) (* C_PROBE_IN90_WIDTH = "1" *) (* C_PROBE_IN91_WIDTH = "1" *) +(* C_PROBE_IN92_WIDTH = "1" *) (* C_PROBE_IN93_WIDTH = "1" *) (* C_PROBE_IN94_WIDTH = "1" *) +(* C_PROBE_IN95_WIDTH = "1" *) (* C_PROBE_IN96_WIDTH = "1" *) (* C_PROBE_IN97_WIDTH = "1" *) +(* C_PROBE_IN98_WIDTH = "1" *) (* C_PROBE_IN99_WIDTH = "1" *) (* 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= "1'b0" *) (* C_PROBE_OUT149_WIDTH = "1" *) (* C_PROBE_OUT14_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT14_WIDTH = "1" *) (* C_PROBE_OUT150_INIT_VAL = "1'b0" *) (* C_PROBE_OUT150_WIDTH = "1" *) +(* C_PROBE_OUT151_INIT_VAL = "1'b0" *) (* C_PROBE_OUT151_WIDTH = "1" *) (* C_PROBE_OUT152_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT152_WIDTH = "1" *) (* C_PROBE_OUT153_INIT_VAL = "1'b0" *) (* C_PROBE_OUT153_WIDTH = "1" *) +(* C_PROBE_OUT154_INIT_VAL = "1'b0" *) (* C_PROBE_OUT154_WIDTH = "1" *) (* C_PROBE_OUT155_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT155_WIDTH = "1" *) (* C_PROBE_OUT156_INIT_VAL = "1'b0" *) (* C_PROBE_OUT156_WIDTH = "1" *) +(* C_PROBE_OUT157_INIT_VAL = "1'b0" *) (* C_PROBE_OUT157_WIDTH = "1" *) (* C_PROBE_OUT158_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT158_WIDTH = "1" *) (* C_PROBE_OUT159_INIT_VAL = "1'b0" *) (* C_PROBE_OUT159_WIDTH = "1" *) +(* C_PROBE_OUT15_INIT_VAL = "1'b0" *) (* C_PROBE_OUT15_WIDTH = "1" *) (* C_PROBE_OUT160_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT160_WIDTH = "1" *) (* C_PROBE_OUT161_INIT_VAL = "1'b0" *) (* C_PROBE_OUT161_WIDTH = "1" *) +(* C_PROBE_OUT162_INIT_VAL = "1'b0" *) (* C_PROBE_OUT162_WIDTH = "1" *) (* C_PROBE_OUT163_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT163_WIDTH = "1" *) (* C_PROBE_OUT164_INIT_VAL = "1'b0" *) (* C_PROBE_OUT164_WIDTH = "1" *) +(* C_PROBE_OUT165_INIT_VAL = "1'b0" *) (* C_PROBE_OUT165_WIDTH = "1" *) (* C_PROBE_OUT166_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT166_WIDTH = "1" *) (* C_PROBE_OUT167_INIT_VAL = "1'b0" *) (* C_PROBE_OUT167_WIDTH = "1" *) +(* C_PROBE_OUT168_INIT_VAL = "1'b0" *) (* C_PROBE_OUT168_WIDTH = "1" *) (* C_PROBE_OUT169_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT169_WIDTH = "1" *) (* C_PROBE_OUT16_INIT_VAL = "1'b0" *) (* C_PROBE_OUT16_WIDTH = "1" *) +(* C_PROBE_OUT170_INIT_VAL = "1'b0" *) (* C_PROBE_OUT170_WIDTH = "1" *) (* C_PROBE_OUT171_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT171_WIDTH = "1" *) (* C_PROBE_OUT172_INIT_VAL = "1'b0" *) (* C_PROBE_OUT172_WIDTH = "1" *) +(* C_PROBE_OUT173_INIT_VAL = "1'b0" *) (* C_PROBE_OUT173_WIDTH = "1" *) (* C_PROBE_OUT174_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT174_WIDTH = "1" *) (* C_PROBE_OUT175_INIT_VAL = "1'b0" *) (* C_PROBE_OUT175_WIDTH = "1" *) +(* C_PROBE_OUT176_INIT_VAL = "1'b0" *) (* C_PROBE_OUT176_WIDTH = "1" *) (* C_PROBE_OUT177_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT177_WIDTH = "1" *) (* C_PROBE_OUT178_INIT_VAL = "1'b0" *) (* C_PROBE_OUT178_WIDTH = "1" *) +(* C_PROBE_OUT179_INIT_VAL = "1'b0" *) (* C_PROBE_OUT179_WIDTH = "1" *) (* C_PROBE_OUT17_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT17_WIDTH = "1" *) (* C_PROBE_OUT180_INIT_VAL = "1'b0" *) (* C_PROBE_OUT180_WIDTH = "1" *) +(* C_PROBE_OUT181_INIT_VAL = "1'b0" *) (* C_PROBE_OUT181_WIDTH = "1" *) (* C_PROBE_OUT182_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT182_WIDTH = "1" *) (* C_PROBE_OUT183_INIT_VAL = "1'b0" *) (* C_PROBE_OUT183_WIDTH = "1" *) +(* C_PROBE_OUT184_INIT_VAL = "1'b0" *) (* C_PROBE_OUT184_WIDTH = "1" *) (* C_PROBE_OUT185_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT185_WIDTH = "1" *) (* C_PROBE_OUT186_INIT_VAL = "1'b0" *) (* C_PROBE_OUT186_WIDTH = "1" *) +(* C_PROBE_OUT187_INIT_VAL = "1'b0" *) (* C_PROBE_OUT187_WIDTH = "1" *) (* C_PROBE_OUT188_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT188_WIDTH = "1" *) (* C_PROBE_OUT189_INIT_VAL = "1'b0" *) (* C_PROBE_OUT189_WIDTH = "1" *) +(* C_PROBE_OUT18_INIT_VAL = "1'b0" *) (* C_PROBE_OUT18_WIDTH = "1" *) (* C_PROBE_OUT190_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT190_WIDTH = "1" *) (* C_PROBE_OUT191_INIT_VAL = "1'b0" *) (* C_PROBE_OUT191_WIDTH = "1" *) +(* C_PROBE_OUT192_INIT_VAL = "1'b0" *) (* C_PROBE_OUT192_WIDTH = "1" *) (* C_PROBE_OUT193_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT193_WIDTH = "1" *) (* C_PROBE_OUT194_INIT_VAL = "1'b0" *) (* C_PROBE_OUT194_WIDTH = "1" *) +(* C_PROBE_OUT195_INIT_VAL = "1'b0" *) (* C_PROBE_OUT195_WIDTH = "1" *) (* C_PROBE_OUT196_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT196_WIDTH = "1" *) (* C_PROBE_OUT197_INIT_VAL = "1'b0" *) (* C_PROBE_OUT197_WIDTH = "1" *) +(* C_PROBE_OUT198_INIT_VAL = "1'b0" *) (* C_PROBE_OUT198_WIDTH = "1" *) (* C_PROBE_OUT199_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT199_WIDTH = "1" *) (* C_PROBE_OUT19_INIT_VAL = "1'b0" *) (* C_PROBE_OUT19_WIDTH = "1" *) +(* C_PROBE_OUT1_INIT_VAL = "1'b0" *) (* C_PROBE_OUT1_WIDTH = "1" *) (* C_PROBE_OUT200_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT200_WIDTH = "1" *) (* C_PROBE_OUT201_INIT_VAL = "1'b0" *) (* C_PROBE_OUT201_WIDTH = "1" *) +(* C_PROBE_OUT202_INIT_VAL = "1'b0" *) (* C_PROBE_OUT202_WIDTH = "1" *) (* C_PROBE_OUT203_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT203_WIDTH = "1" *) (* C_PROBE_OUT204_INIT_VAL = "1'b0" *) (* C_PROBE_OUT204_WIDTH = "1" *) +(* C_PROBE_OUT205_INIT_VAL = "1'b0" *) (* C_PROBE_OUT205_WIDTH = "1" *) (* C_PROBE_OUT206_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT206_WIDTH = "1" *) (* C_PROBE_OUT207_INIT_VAL = "1'b0" *) (* C_PROBE_OUT207_WIDTH = "1" *) +(* C_PROBE_OUT208_INIT_VAL = "1'b0" *) (* C_PROBE_OUT208_WIDTH = "1" *) (* C_PROBE_OUT209_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT209_WIDTH = "1" *) (* C_PROBE_OUT20_INIT_VAL = "1'b0" *) (* C_PROBE_OUT20_WIDTH = "1" *) +(* C_PROBE_OUT210_INIT_VAL = "1'b0" *) (* C_PROBE_OUT210_WIDTH = "1" *) (* C_PROBE_OUT211_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT211_WIDTH = "1" *) (* C_PROBE_OUT212_INIT_VAL = "1'b0" *) (* C_PROBE_OUT212_WIDTH = "1" *) +(* C_PROBE_OUT213_INIT_VAL = "1'b0" *) (* C_PROBE_OUT213_WIDTH = "1" *) (* C_PROBE_OUT214_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT214_WIDTH = "1" *) (* C_PROBE_OUT215_INIT_VAL = "1'b0" *) (* C_PROBE_OUT215_WIDTH = "1" *) +(* C_PROBE_OUT216_INIT_VAL = "1'b0" *) (* C_PROBE_OUT216_WIDTH = "1" *) (* C_PROBE_OUT217_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT217_WIDTH = "1" *) (* C_PROBE_OUT218_INIT_VAL = "1'b0" *) (* C_PROBE_OUT218_WIDTH = "1" *) +(* C_PROBE_OUT219_INIT_VAL = "1'b0" *) (* C_PROBE_OUT219_WIDTH = "1" *) (* C_PROBE_OUT21_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT21_WIDTH = "1" *) (* C_PROBE_OUT220_INIT_VAL = "1'b0" *) (* C_PROBE_OUT220_WIDTH = "1" *) +(* C_PROBE_OUT221_INIT_VAL = "1'b0" *) (* C_PROBE_OUT221_WIDTH = "1" *) (* C_PROBE_OUT222_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT222_WIDTH = "1" *) (* C_PROBE_OUT223_INIT_VAL = "1'b0" *) (* C_PROBE_OUT223_WIDTH = "1" *) +(* C_PROBE_OUT224_INIT_VAL = "1'b0" *) (* C_PROBE_OUT224_WIDTH = "1" *) (* C_PROBE_OUT225_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT225_WIDTH = "1" *) (* C_PROBE_OUT226_INIT_VAL = "1'b0" *) (* C_PROBE_OUT226_WIDTH = "1" *) +(* C_PROBE_OUT227_INIT_VAL = "1'b0" *) (* C_PROBE_OUT227_WIDTH = "1" *) (* C_PROBE_OUT228_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT228_WIDTH = "1" *) (* C_PROBE_OUT229_INIT_VAL = "1'b0" *) (* C_PROBE_OUT229_WIDTH = "1" *) +(* C_PROBE_OUT22_INIT_VAL = "1'b0" *) (* C_PROBE_OUT22_WIDTH = "1" *) (* C_PROBE_OUT230_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT230_WIDTH = "1" *) (* C_PROBE_OUT231_INIT_VAL = "1'b0" *) (* C_PROBE_OUT231_WIDTH = "1" *) +(* C_PROBE_OUT232_INIT_VAL = "1'b0" *) (* C_PROBE_OUT232_WIDTH = "1" *) (* C_PROBE_OUT233_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT233_WIDTH = "1" *) (* C_PROBE_OUT234_INIT_VAL = "1'b0" *) (* C_PROBE_OUT234_WIDTH = "1" *) +(* C_PROBE_OUT235_INIT_VAL = "1'b0" *) (* C_PROBE_OUT235_WIDTH = "1" *) (* C_PROBE_OUT236_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT236_WIDTH = "1" *) (* C_PROBE_OUT237_INIT_VAL = "1'b0" *) (* C_PROBE_OUT237_WIDTH = "1" *) +(* C_PROBE_OUT238_INIT_VAL = "1'b0" *) (* C_PROBE_OUT238_WIDTH = "1" *) (* C_PROBE_OUT239_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT239_WIDTH = "1" *) (* C_PROBE_OUT23_INIT_VAL = "1'b0" *) (* C_PROBE_OUT23_WIDTH = "1" *) +(* C_PROBE_OUT240_INIT_VAL = "1'b0" *) (* C_PROBE_OUT240_WIDTH = "1" *) (* C_PROBE_OUT241_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT241_WIDTH = "1" *) (* C_PROBE_OUT242_INIT_VAL = "1'b0" *) (* C_PROBE_OUT242_WIDTH = "1" *) +(* C_PROBE_OUT243_INIT_VAL = "1'b0" *) (* C_PROBE_OUT243_WIDTH = "1" *) (* C_PROBE_OUT244_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT244_WIDTH = "1" *) (* C_PROBE_OUT245_INIT_VAL = "1'b0" *) (* C_PROBE_OUT245_WIDTH = "1" *) +(* C_PROBE_OUT246_INIT_VAL = "1'b0" *) (* C_PROBE_OUT246_WIDTH = "1" *) (* C_PROBE_OUT247_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT247_WIDTH = "1" *) (* C_PROBE_OUT248_INIT_VAL = "1'b0" *) (* C_PROBE_OUT248_WIDTH = "1" *) +(* C_PROBE_OUT249_INIT_VAL = "1'b0" *) (* C_PROBE_OUT249_WIDTH = "1" *) (* C_PROBE_OUT24_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT24_WIDTH = "1" *) (* C_PROBE_OUT250_INIT_VAL = "1'b0" *) (* C_PROBE_OUT250_WIDTH = "1" *) +(* C_PROBE_OUT251_INIT_VAL = "1'b0" *) (* C_PROBE_OUT251_WIDTH = "1" *) (* C_PROBE_OUT252_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT252_WIDTH = "1" *) (* C_PROBE_OUT253_INIT_VAL = "1'b0" *) (* C_PROBE_OUT253_WIDTH = "1" *) +(* C_PROBE_OUT254_INIT_VAL = "1'b0" *) (* C_PROBE_OUT254_WIDTH = "1" *) (* C_PROBE_OUT255_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT255_WIDTH = "1" *) (* C_PROBE_OUT25_INIT_VAL = "1'b0" *) (* C_PROBE_OUT25_WIDTH = "1" *) +(* C_PROBE_OUT26_INIT_VAL = "1'b0" *) (* C_PROBE_OUT26_WIDTH = "1" *) (* C_PROBE_OUT27_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT27_WIDTH = "1" *) (* C_PROBE_OUT28_INIT_VAL = "1'b0" *) (* C_PROBE_OUT28_WIDTH = "1" *) +(* C_PROBE_OUT29_INIT_VAL = "1'b0" *) (* C_PROBE_OUT29_WIDTH = "1" *) (* C_PROBE_OUT2_INIT_VAL = "32'b00000000000000000000000000000000" *) +(* C_PROBE_OUT2_WIDTH = "32" *) (* C_PROBE_OUT30_INIT_VAL = "1'b0" *) (* C_PROBE_OUT30_WIDTH = "1" *) +(* C_PROBE_OUT31_INIT_VAL = "1'b0" *) (* C_PROBE_OUT31_WIDTH = "1" *) (* C_PROBE_OUT32_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT32_WIDTH = "1" *) (* C_PROBE_OUT33_INIT_VAL = "1'b0" *) (* C_PROBE_OUT33_WIDTH = "1" *) +(* C_PROBE_OUT34_INIT_VAL = "1'b0" *) (* C_PROBE_OUT34_WIDTH = "1" *) (* C_PROBE_OUT35_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT35_WIDTH = "1" *) (* C_PROBE_OUT36_INIT_VAL = "1'b0" *) (* C_PROBE_OUT36_WIDTH = "1" *) +(* C_PROBE_OUT37_INIT_VAL = "1'b0" *) (* C_PROBE_OUT37_WIDTH = "1" *) (* C_PROBE_OUT38_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT38_WIDTH = "1" *) (* C_PROBE_OUT39_INIT_VAL = "1'b0" *) (* C_PROBE_OUT39_WIDTH = "1" *) +(* C_PROBE_OUT3_INIT_VAL = "2'b11" *) (* C_PROBE_OUT3_WIDTH = "2" *) (* C_PROBE_OUT40_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT40_WIDTH = "1" *) (* C_PROBE_OUT41_INIT_VAL = "1'b0" *) (* C_PROBE_OUT41_WIDTH = "1" *) +(* C_PROBE_OUT42_INIT_VAL = "1'b0" *) (* C_PROBE_OUT42_WIDTH = "1" *) (* C_PROBE_OUT43_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT43_WIDTH = "1" *) (* C_PROBE_OUT44_INIT_VAL = "1'b0" *) (* C_PROBE_OUT44_WIDTH = "1" *) +(* C_PROBE_OUT45_INIT_VAL = "1'b0" *) (* C_PROBE_OUT45_WIDTH = "1" *) (* C_PROBE_OUT46_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT46_WIDTH = "1" *) (* C_PROBE_OUT47_INIT_VAL = "1'b0" *) (* C_PROBE_OUT47_WIDTH = "1" *) +(* C_PROBE_OUT48_INIT_VAL = "1'b0" *) (* C_PROBE_OUT48_WIDTH = "1" *) (* C_PROBE_OUT49_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT49_WIDTH = "1" *) (* C_PROBE_OUT4_INIT_VAL = "4'b0000" *) (* C_PROBE_OUT4_WIDTH = "4" *) +(* C_PROBE_OUT50_INIT_VAL = "1'b0" *) (* C_PROBE_OUT50_WIDTH = "1" *) (* C_PROBE_OUT51_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT51_WIDTH = "1" *) (* C_PROBE_OUT52_INIT_VAL = "1'b0" *) (* C_PROBE_OUT52_WIDTH = "1" *) +(* C_PROBE_OUT53_INIT_VAL = "1'b0" *) (* C_PROBE_OUT53_WIDTH = "1" *) (* C_PROBE_OUT54_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT54_WIDTH = "1" *) (* C_PROBE_OUT55_INIT_VAL = "1'b0" *) (* C_PROBE_OUT55_WIDTH = "1" *) +(* C_PROBE_OUT56_INIT_VAL = "1'b0" *) (* C_PROBE_OUT56_WIDTH = "1" *) (* C_PROBE_OUT57_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT57_WIDTH = "1" *) (* C_PROBE_OUT58_INIT_VAL = "1'b0" *) (* C_PROBE_OUT58_WIDTH = "1" *) +(* C_PROBE_OUT59_INIT_VAL = "1'b0" *) (* C_PROBE_OUT59_WIDTH = "1" *) (* C_PROBE_OUT5_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT5_WIDTH = "1" *) (* C_PROBE_OUT60_INIT_VAL = "1'b0" *) (* C_PROBE_OUT60_WIDTH = "1" *) +(* C_PROBE_OUT61_INIT_VAL = "1'b0" *) (* C_PROBE_OUT61_WIDTH = "1" *) (* C_PROBE_OUT62_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT62_WIDTH = "1" *) (* C_PROBE_OUT63_INIT_VAL = "1'b0" *) (* C_PROBE_OUT63_WIDTH = "1" *) +(* C_PROBE_OUT64_INIT_VAL = "1'b0" *) (* C_PROBE_OUT64_WIDTH = "1" *) (* C_PROBE_OUT65_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT65_WIDTH = "1" *) (* C_PROBE_OUT66_INIT_VAL = "1'b0" *) (* C_PROBE_OUT66_WIDTH = "1" *) +(* C_PROBE_OUT67_INIT_VAL = "1'b0" *) (* C_PROBE_OUT67_WIDTH = "1" *) (* C_PROBE_OUT68_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT68_WIDTH = "1" *) (* C_PROBE_OUT69_INIT_VAL = "1'b0" *) (* C_PROBE_OUT69_WIDTH = "1" *) +(* C_PROBE_OUT6_INIT_VAL = "1'b0" *) (* C_PROBE_OUT6_WIDTH = "1" *) (* C_PROBE_OUT70_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT70_WIDTH = "1" *) (* C_PROBE_OUT71_INIT_VAL = "1'b0" *) (* C_PROBE_OUT71_WIDTH = "1" *) +(* C_PROBE_OUT72_INIT_VAL = "1'b0" *) (* C_PROBE_OUT72_WIDTH = "1" *) (* C_PROBE_OUT73_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT73_WIDTH = "1" *) (* C_PROBE_OUT74_INIT_VAL = "1'b0" *) (* C_PROBE_OUT74_WIDTH = "1" *) +(* C_PROBE_OUT75_INIT_VAL = "1'b0" *) (* C_PROBE_OUT75_WIDTH = "1" *) (* C_PROBE_OUT76_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT76_WIDTH = "1" *) (* C_PROBE_OUT77_INIT_VAL = "1'b0" *) (* C_PROBE_OUT77_WIDTH = "1" *) +(* C_PROBE_OUT78_INIT_VAL = "1'b0" *) (* C_PROBE_OUT78_WIDTH = "1" *) (* C_PROBE_OUT79_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT79_WIDTH = "1" *) (* C_PROBE_OUT7_INIT_VAL = "1'b0" *) (* C_PROBE_OUT7_WIDTH = "1" *) +(* C_PROBE_OUT80_INIT_VAL = "1'b0" *) (* C_PROBE_OUT80_WIDTH = "1" *) (* C_PROBE_OUT81_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT81_WIDTH = "1" *) (* C_PROBE_OUT82_INIT_VAL = "1'b0" *) (* C_PROBE_OUT82_WIDTH = "1" *) +(* C_PROBE_OUT83_INIT_VAL = "1'b0" *) (* C_PROBE_OUT83_WIDTH = "1" *) (* C_PROBE_OUT84_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT84_WIDTH = "1" *) (* C_PROBE_OUT85_INIT_VAL = "1'b0" *) (* C_PROBE_OUT85_WIDTH = "1" *) +(* C_PROBE_OUT86_INIT_VAL = "1'b0" *) (* C_PROBE_OUT86_WIDTH = "1" *) (* C_PROBE_OUT87_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT87_WIDTH = "1" *) (* C_PROBE_OUT88_INIT_VAL = "1'b0" *) (* C_PROBE_OUT88_WIDTH = "1" *) +(* C_PROBE_OUT89_INIT_VAL = "1'b0" *) (* C_PROBE_OUT89_WIDTH = "1" *) (* C_PROBE_OUT8_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT8_WIDTH = "1" *) (* C_PROBE_OUT90_INIT_VAL = "1'b0" *) (* C_PROBE_OUT90_WIDTH = "1" *) +(* C_PROBE_OUT91_INIT_VAL = "1'b0" *) (* C_PROBE_OUT91_WIDTH = "1" *) (* C_PROBE_OUT92_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT92_WIDTH = "1" *) (* C_PROBE_OUT93_INIT_VAL = "1'b0" *) (* C_PROBE_OUT93_WIDTH = "1" *) +(* C_PROBE_OUT94_INIT_VAL = "1'b0" *) (* C_PROBE_OUT94_WIDTH = "1" *) (* C_PROBE_OUT95_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT95_WIDTH = "1" *) (* C_PROBE_OUT96_INIT_VAL = "1'b0" *) (* C_PROBE_OUT96_WIDTH = "1" *) +(* C_PROBE_OUT97_INIT_VAL = "1'b0" *) (* C_PROBE_OUT97_WIDTH = "1" *) (* C_PROBE_OUT98_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT98_WIDTH = "1" *) (* C_PROBE_OUT99_INIT_VAL = "1'b0" *) (* C_PROBE_OUT99_WIDTH = "1" *) +(* C_PROBE_OUT9_INIT_VAL = "1'b0" *) (* C_PROBE_OUT9_WIDTH = "1" *) (* C_USE_TEST_REG = "1" *) +(* C_XDEVICEFAMILY = "kintex7" *) (* C_XLNX_HW_PROBE_INFO = "DEFAULT" *) (* C_XSDB_SLAVE_TYPE = "33" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000010001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000010001001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000010001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000010001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000010001100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000010001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000010001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000010001111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000010010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000010010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000101111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000010010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000010010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000010010100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000010010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000010010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000010010111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000010011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000010011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000010011010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000010011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000010011100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000010011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000010011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000010011111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000010100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000010100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000010100010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000010100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010100101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010100111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010101010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010101101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000110010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010110010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010110101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010111000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010111010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010111101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000011000000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000011000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000011000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000011000011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000011000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000011000101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000011000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000011000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000011001000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000011001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000011001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000011001011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000011001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000011001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000110101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000011001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000011001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000011010000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000011010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000011010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000011010011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000011010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000011010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000011010110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000011010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000011011000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000011011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000011011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000011011011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000011011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000011011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000011011110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000011011111" *) (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000011100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000011100001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000011100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000011100011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011100110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011101001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000100010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011101101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011110000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011110011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000111001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011111000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011111011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011111110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000100000000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000100000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000100000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000100000011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000100000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000100000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000100000110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000100000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000100001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000100001001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000100001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000100001011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000100001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000100001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000100001110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000100001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000100010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000100010001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000100010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000100010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000111100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000100010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000100010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000100010110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000100010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000100011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000100011001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000100011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000100011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000100011100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000100011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000100011110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000100011111" *) (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000100100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000100100001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000100100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000100100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000111110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000001000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000001000001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000001000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000001000011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000001000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000001000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000001000110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000001000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000001001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000001001001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000001001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000001001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000101000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000001001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000001001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000001001110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000001001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000001010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000001010001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000001010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000001010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000001010100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000001010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000001010110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000001010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000001011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000001011001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000001011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000001011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000001011100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000001011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000001011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000001011111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000001100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000001100001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000001100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000001100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001100100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001100111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000101011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001101100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001101111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001110010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001110100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001110111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001111010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001111101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001111111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000010000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000010000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000010000010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000010000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000010000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000010000101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000010000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000010000111" *) (* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *) +(* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000010" *) (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000101110" *) (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000010001000" *) +(* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000010001001" *) (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000010001010" *) (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000010001011" *) +(* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000010001100" *) (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000010001101" *) (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000010001110" *) +(* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000010001111" *) (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000010010000" *) (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000010010001" *) +(* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000101111" *) (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000010010010" *) (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000010010011" *) +(* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000010010100" *) (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000010010101" *) (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000010010110" *) +(* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000010010111" *) (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000010011000" *) (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000010011001" *) +(* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000010011010" *) (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000010011011" *) (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000110000" *) +(* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000010011100" *) (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000010011101" *) (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000010011110" *) +(* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000010011111" *) (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000010100000" *) (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000010100001" *) +(* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000010100010" *) (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000010100011" *) (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010100100" *) +(* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010100101" *) (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000110001" *) (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010100110" *) +(* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010100111" *) (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010101000" *) (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010101001" *) +(* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010101010" *) (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010101011" *) (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010101100" *) +(* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010101101" *) (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010101110" *) (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010101111" *) +(* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000110010" *) (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010110000" *) (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010110001" *) +(* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010110010" *) (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010110011" *) (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010110100" *) +(* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010110101" *) (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010110110" *) (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010110111" *) +(* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010111000" *) (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010111001" *) (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000110011" *) +(* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010111010" *) (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010111011" *) (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010111100" *) +(* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010111101" *) (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010111110" *) (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010111111" *) +(* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000011000000" *) (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000011000001" *) (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000011000010" *) +(* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000011000011" *) (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000110100" *) (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000011000100" *) +(* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000011000101" *) (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000011000110" *) (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000011000111" *) +(* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000011001000" *) (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000011001001" *) (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000011001010" *) +(* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000011001011" *) (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000011001100" *) (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000011001101" *) +(* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000110101" *) (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000011001110" *) (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000011001111" *) +(* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000011010000" *) (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000011010001" *) (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000011010010" *) +(* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000011010011" *) (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000011010100" *) (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000011010101" *) +(* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000011010110" *) (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000011010111" *) (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000110110" *) +(* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000011011000" *) (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000011011001" *) (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000011011010" *) +(* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000011011011" *) (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000011011100" *) (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000011011101" *) +(* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000011011110" *) (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000011011111" *) (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000011100000" *) +(* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000011100001" *) (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000110111" *) (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000011100010" *) +(* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000011100011" *) (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011100100" *) (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011100101" *) +(* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011100110" *) (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011100111" *) (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011101000" *) +(* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011101001" *) (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011101010" *) (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011101011" *) +(* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000011" *) (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000111000" *) (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011101100" *) +(* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011101101" *) (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011101110" *) (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011101111" *) +(* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011110000" *) (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011110001" *) (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011110010" *) +(* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011110011" *) (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011110100" *) (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011110101" *) +(* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000111001" *) (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011110110" *) (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011110111" *) +(* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011111000" *) (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011111001" *) (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011111010" *) +(* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011111011" *) (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011111100" *) (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011111101" *) +(* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011111110" *) (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011111111" *) (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000111010" *) +(* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000100000000" *) (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000100000001" *) (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000100000010" *) +(* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000100000011" *) (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000100000100" *) (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000100000101" *) +(* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000100000110" *) (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000100000111" *) (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000100001000" *) +(* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000100001001" *) (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000111011" *) (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000100001010" *) +(* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000100001011" *) (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000100001100" *) (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000100001101" *) +(* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000100001110" *) (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000100001111" *) (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000100010000" *) +(* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000100010001" *) (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000100010010" *) (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000100010011" *) +(* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000111100" *) (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000100010100" *) (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000100010101" *) +(* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000100010110" *) (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000100010111" *) (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000100011000" *) +(* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000100011001" *) (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000100011010" *) (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000100011011" *) +(* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000100011100" *) (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000100011101" *) (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000111101" *) +(* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000100011110" *) (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000100011111" *) (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000100100000" *) +(* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000100100001" *) (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000100100010" *) (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000100100011" *) +(* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000111110" *) (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000111111" *) (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000001000000" *) +(* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000001000001" *) (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000100011" *) (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000001000010" *) +(* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000001000011" *) (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000001000100" *) (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000001000101" *) +(* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000001000110" *) (* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000001000111" *) (* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000001001000" *) +(* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000001001001" *) (* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000001001010" *) (* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000001001011" *) +(* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000100101" *) (* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000001001100" *) (* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000001001101" *) +(* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000001001110" *) (* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000001001111" *) (* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000001010000" *) +(* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000001010001" *) (* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000001010010" *) (* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000001010011" *) +(* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000001010100" *) (* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000001010101" *) (* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000101001" *) +(* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000001010110" *) (* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000001010111" *) (* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000001011000" *) +(* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000001011001" *) (* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000001011010" *) (* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000001011011" *) +(* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000001011100" *) (* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000001011101" *) (* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000001011110" *) +(* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000001011111" *) (* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000101010" *) (* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000001100000" *) +(* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000001100001" *) (* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000001100010" *) (* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000001100011" *) +(* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001100100" *) (* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001100101" *) (* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001100110" *) +(* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001100111" *) (* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001101000" *) (* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001101001" *) +(* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000101011" *) (* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001101010" *) (* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001101011" *) +(* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001101100" *) (* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001101101" *) (* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001101110" *) +(* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001101111" *) (* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001110000" *) (* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001110001" *) +(* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001110010" *) (* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001110011" *) (* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000101100" *) +(* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001110100" *) (* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001110101" *) (* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001110110" *) +(* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001110111" *) (* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001111000" *) (* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001111001" *) +(* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001111010" *) (* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001111011" *) (* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001111100" *) +(* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001111101" *) (* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000101101" *) (* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001111110" *) +(* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001111111" *) (* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000010000000" *) (* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000010000001" *) +(* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000010000010" *) (* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000010000011" *) (* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000010000100" *) +(* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000010000101" *) (* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000010000110" *) (* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000010000111" *) +(* LC_PROBE_IN_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* LC_PROBE_OUT_HIGH_BIT_POS_STRING = "4096'b0000000100100011000000010010001000000001001000010000000100100000000000010001111100000001000111100000000100011101000000010001110000000001000110110000000100011010000000010001100100000001000110000000000100010111000000010001011000000001000101010000000100010100000000010001001100000001000100100000000100010001000000010001000000000001000011110000000100001110000000010000110100000001000011000000000100001011000000010000101000000001000010010000000100001000000000010000011100000001000001100000000100000101000000010000010000000001000000110000000100000010000000010000000100000001000000000000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100100000000000010001000000000000000100000000000000001" *) (* LC_PROBE_OUT_INIT_VAL_STRING = "292'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000010" *) +(* LC_PROBE_OUT_LOW_BIT_POS_STRING = "4096'b0000000100100011000000010010001000000001001000010000000100100000000000010001111100000001000111100000000100011101000000010001110000000001000110110000000100011010000000010001100100000001000110000000000100010111000000010001011000000001000101010000000100010100000000010001001100000001000100100000000100010001000000010001000000000001000011110000000100001110000000010000110100000001000011000000000100001011000000010000101000000001000010010000000100001000000000010000011100000001000001100000000100000101000000010000010000000001000000110000000100000010000000010000000100000001000000000000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001001010000000000100011000000000000001100000000000000100000000000000000" *) (* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000001000111110000000000000001" *) (* LC_TOTAL_PROBE_IN_WIDTH = "0" *) +(* LC_TOTAL_PROBE_OUT_WIDTH = "41" *) (* dont_touch = "true" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio + (clk, + probe_in0, + probe_in1, + probe_in2, + probe_in3, + probe_in4, + probe_in5, + probe_in6, + probe_in7, + probe_in8, + probe_in9, + probe_in10, + probe_in11, + probe_in12, + probe_in13, + probe_in14, + probe_in15, + probe_in16, + probe_in17, + probe_in18, + probe_in19, + probe_in20, + probe_in21, + probe_in22, + probe_in23, + probe_in24, + probe_in25, + probe_in26, + probe_in27, + probe_in28, + probe_in29, + probe_in30, + probe_in31, + probe_in32, + probe_in33, + probe_in34, + probe_in35, + probe_in36, + probe_in37, + probe_in38, + probe_in39, + probe_in40, + probe_in41, + probe_in42, + probe_in43, + probe_in44, + probe_in45, + probe_in46, + probe_in47, + probe_in48, + probe_in49, + probe_in50, + probe_in51, + probe_in52, + probe_in53, + probe_in54, + probe_in55, + probe_in56, + probe_in57, + probe_in58, + probe_in59, + probe_in60, + probe_in61, + probe_in62, + probe_in63, + probe_in64, + probe_in65, + probe_in66, + probe_in67, + probe_in68, + probe_in69, + probe_in70, + probe_in71, + probe_in72, + probe_in73, + probe_in74, + probe_in75, + probe_in76, + probe_in77, + probe_in78, + probe_in79, + probe_in80, + probe_in81, + probe_in82, + probe_in83, + probe_in84, + probe_in85, + probe_in86, + probe_in87, + probe_in88, + probe_in89, + probe_in90, + probe_in91, + probe_in92, + probe_in93, + probe_in94, + probe_in95, + probe_in96, + probe_in97, + probe_in98, + probe_in99, + probe_in100, + probe_in101, + probe_in102, + probe_in103, + probe_in104, + probe_in105, + probe_in106, + probe_in107, + probe_in108, + probe_in109, + probe_in110, + probe_in111, + probe_in112, + probe_in113, + probe_in114, + probe_in115, + probe_in116, + probe_in117, + probe_in118, + probe_in119, + probe_in120, + probe_in121, + probe_in122, + probe_in123, + probe_in124, + probe_in125, + probe_in126, + probe_in127, + probe_in128, + probe_in129, + probe_in130, + probe_in131, + probe_in132, + probe_in133, + probe_in134, + probe_in135, + probe_in136, + probe_in137, + probe_in138, + probe_in139, + probe_in140, + probe_in141, + probe_in142, + probe_in143, + probe_in144, + probe_in145, + probe_in146, + probe_in147, + probe_in148, + probe_in149, + probe_in150, + probe_in151, + probe_in152, + probe_in153, + probe_in154, + probe_in155, + probe_in156, + probe_in157, + probe_in158, + probe_in159, + probe_in160, + probe_in161, + probe_in162, + probe_in163, + probe_in164, + probe_in165, + probe_in166, + probe_in167, + probe_in168, + probe_in169, + probe_in170, + probe_in171, + probe_in172, + probe_in173, + probe_in174, + probe_in175, + probe_in176, + probe_in177, + probe_in178, + probe_in179, + probe_in180, + probe_in181, + probe_in182, + probe_in183, + probe_in184, + probe_in185, + probe_in186, + probe_in187, + probe_in188, + probe_in189, + probe_in190, + probe_in191, + probe_in192, + probe_in193, + probe_in194, + probe_in195, + probe_in196, + probe_in197, + probe_in198, + probe_in199, + probe_in200, + probe_in201, + probe_in202, + probe_in203, + probe_in204, + probe_in205, + probe_in206, + probe_in207, + probe_in208, + probe_in209, + probe_in210, + probe_in211, + probe_in212, + probe_in213, + probe_in214, + probe_in215, + probe_in216, + probe_in217, + probe_in218, + probe_in219, + probe_in220, + probe_in221, + probe_in222, + probe_in223, + probe_in224, + probe_in225, + probe_in226, + probe_in227, + probe_in228, + probe_in229, + probe_in230, + probe_in231, + probe_in232, + probe_in233, + probe_in234, + probe_in235, + probe_in236, + probe_in237, + probe_in238, + probe_in239, + probe_in240, + probe_in241, + probe_in242, + probe_in243, + probe_in244, + probe_in245, + probe_in246, + probe_in247, + probe_in248, + probe_in249, + probe_in250, + probe_in251, + probe_in252, + probe_in253, + probe_in254, + probe_in255, + sl_iport0, + sl_oport0, + probe_out0, + probe_out1, + probe_out2, + probe_out3, + probe_out4, + probe_out5, + probe_out6, + probe_out7, + probe_out8, + probe_out9, + probe_out10, + probe_out11, + probe_out12, + probe_out13, + probe_out14, + probe_out15, + probe_out16, + probe_out17, + probe_out18, + probe_out19, + probe_out20, + probe_out21, + probe_out22, + probe_out23, + probe_out24, + probe_out25, + probe_out26, + probe_out27, + probe_out28, + probe_out29, + probe_out30, + probe_out31, + probe_out32, + probe_out33, + probe_out34, + probe_out35, + probe_out36, + probe_out37, + probe_out38, + probe_out39, + probe_out40, + probe_out41, + probe_out42, + probe_out43, + probe_out44, + probe_out45, + probe_out46, + probe_out47, + probe_out48, + probe_out49, + probe_out50, + probe_out51, + probe_out52, + probe_out53, + probe_out54, + probe_out55, + probe_out56, + probe_out57, + probe_out58, + probe_out59, + probe_out60, + probe_out61, + probe_out62, + probe_out63, + probe_out64, + probe_out65, + probe_out66, + probe_out67, + probe_out68, + probe_out69, + probe_out70, + probe_out71, + probe_out72, + probe_out73, + probe_out74, + probe_out75, + probe_out76, + probe_out77, + probe_out78, + probe_out79, + probe_out80, + probe_out81, + probe_out82, + probe_out83, + probe_out84, + probe_out85, + probe_out86, + probe_out87, + probe_out88, + probe_out89, + probe_out90, + probe_out91, + probe_out92, + probe_out93, + probe_out94, + probe_out95, + probe_out96, + probe_out97, + probe_out98, + probe_out99, + probe_out100, + probe_out101, + probe_out102, + probe_out103, + probe_out104, + probe_out105, + probe_out106, + probe_out107, + probe_out108, + probe_out109, + probe_out110, + probe_out111, + probe_out112, + probe_out113, + probe_out114, + probe_out115, + probe_out116, + probe_out117, + probe_out118, + probe_out119, + probe_out120, + probe_out121, + probe_out122, + probe_out123, + probe_out124, + probe_out125, + probe_out126, + probe_out127, + probe_out128, + probe_out129, + probe_out130, + probe_out131, + probe_out132, + probe_out133, + probe_out134, + probe_out135, + probe_out136, + probe_out137, + probe_out138, + probe_out139, + probe_out140, + probe_out141, + probe_out142, + probe_out143, + probe_out144, + probe_out145, + probe_out146, + probe_out147, + probe_out148, + probe_out149, + probe_out150, + probe_out151, + probe_out152, + probe_out153, + probe_out154, + probe_out155, + probe_out156, + probe_out157, + probe_out158, + probe_out159, + probe_out160, + probe_out161, + probe_out162, + probe_out163, + probe_out164, + probe_out165, + probe_out166, + probe_out167, + probe_out168, + probe_out169, + probe_out170, + probe_out171, + probe_out172, + probe_out173, + probe_out174, + probe_out175, + probe_out176, + probe_out177, + probe_out178, + probe_out179, + probe_out180, + probe_out181, + probe_out182, + probe_out183, + probe_out184, + probe_out185, + probe_out186, + probe_out187, + probe_out188, + probe_out189, + probe_out190, + probe_out191, + probe_out192, + probe_out193, + probe_out194, + probe_out195, + probe_out196, + probe_out197, + probe_out198, + probe_out199, + probe_out200, + probe_out201, + probe_out202, + probe_out203, + probe_out204, + probe_out205, + probe_out206, + probe_out207, + probe_out208, + probe_out209, + probe_out210, + probe_out211, + probe_out212, + probe_out213, + probe_out214, + probe_out215, + probe_out216, + probe_out217, + probe_out218, + probe_out219, + probe_out220, + probe_out221, + probe_out222, + probe_out223, + probe_out224, + probe_out225, + probe_out226, + probe_out227, + probe_out228, + probe_out229, + probe_out230, + probe_out231, + probe_out232, + probe_out233, + probe_out234, + probe_out235, + probe_out236, + probe_out237, + probe_out238, + probe_out239, + probe_out240, + probe_out241, + probe_out242, + probe_out243, + probe_out244, + probe_out245, + probe_out246, + probe_out247, + probe_out248, + probe_out249, + probe_out250, + probe_out251, + probe_out252, + probe_out253, + probe_out254, + probe_out255); + input clk; + input [0:0]probe_in0; + input [0:0]probe_in1; + input [0:0]probe_in2; + input [0:0]probe_in3; + input [0:0]probe_in4; + input [0:0]probe_in5; + input [0:0]probe_in6; + input [0:0]probe_in7; + input [0:0]probe_in8; + input [0:0]probe_in9; + input [0:0]probe_in10; + input [0:0]probe_in11; + input [0:0]probe_in12; + input [0:0]probe_in13; + input [0:0]probe_in14; + input [0:0]probe_in15; + input [0:0]probe_in16; + input [0:0]probe_in17; + input [0:0]probe_in18; + input [0:0]probe_in19; + input [0:0]probe_in20; + input [0:0]probe_in21; + input [0:0]probe_in22; + input [0:0]probe_in23; + input [0:0]probe_in24; + input [0:0]probe_in25; + input [0:0]probe_in26; + input [0:0]probe_in27; + input [0:0]probe_in28; + input [0:0]probe_in29; + input [0:0]probe_in30; + input [0:0]probe_in31; + input [0:0]probe_in32; + input [0:0]probe_in33; + input [0:0]probe_in34; + input [0:0]probe_in35; + input [0:0]probe_in36; + input [0:0]probe_in37; + input [0:0]probe_in38; + input [0:0]probe_in39; + input [0:0]probe_in40; + input [0:0]probe_in41; + input [0:0]probe_in42; + input [0:0]probe_in43; + input [0:0]probe_in44; + input [0:0]probe_in45; + input [0:0]probe_in46; + input [0:0]probe_in47; + input [0:0]probe_in48; + input [0:0]probe_in49; + input [0:0]probe_in50; + input [0:0]probe_in51; + input [0:0]probe_in52; + input [0:0]probe_in53; + input [0:0]probe_in54; + input [0:0]probe_in55; + input [0:0]probe_in56; + input [0:0]probe_in57; + input [0:0]probe_in58; + input [0:0]probe_in59; + input [0:0]probe_in60; + input [0:0]probe_in61; + input [0:0]probe_in62; + input [0:0]probe_in63; + input [0:0]probe_in64; + input [0:0]probe_in65; + input [0:0]probe_in66; + input [0:0]probe_in67; + input [0:0]probe_in68; + input [0:0]probe_in69; + input [0:0]probe_in70; + input [0:0]probe_in71; + input [0:0]probe_in72; + input [0:0]probe_in73; + input [0:0]probe_in74; + input [0:0]probe_in75; + input [0:0]probe_in76; + input [0:0]probe_in77; + input [0:0]probe_in78; + input [0:0]probe_in79; + input [0:0]probe_in80; + input [0:0]probe_in81; + input [0:0]probe_in82; + input [0:0]probe_in83; + input [0:0]probe_in84; + input [0:0]probe_in85; + input [0:0]probe_in86; + input [0:0]probe_in87; + input [0:0]probe_in88; + input [0:0]probe_in89; + input [0:0]probe_in90; + input [0:0]probe_in91; + input [0:0]probe_in92; + input [0:0]probe_in93; + input [0:0]probe_in94; + input [0:0]probe_in95; + input [0:0]probe_in96; + input [0:0]probe_in97; + input [0:0]probe_in98; + input [0:0]probe_in99; + input [0:0]probe_in100; + input [0:0]probe_in101; + input [0:0]probe_in102; + input [0:0]probe_in103; + input [0:0]probe_in104; + input [0:0]probe_in105; + input [0:0]probe_in106; + input [0:0]probe_in107; + input [0:0]probe_in108; + input [0:0]probe_in109; + input [0:0]probe_in110; + input [0:0]probe_in111; + input [0:0]probe_in112; + input [0:0]probe_in113; + input [0:0]probe_in114; + input [0:0]probe_in115; + input [0:0]probe_in116; + input [0:0]probe_in117; + input [0:0]probe_in118; + input [0:0]probe_in119; + input [0:0]probe_in120; + input [0:0]probe_in121; + input [0:0]probe_in122; + input [0:0]probe_in123; + input [0:0]probe_in124; + input [0:0]probe_in125; + input [0:0]probe_in126; + input [0:0]probe_in127; + input [0:0]probe_in128; + input [0:0]probe_in129; + input [0:0]probe_in130; + input [0:0]probe_in131; + input [0:0]probe_in132; + input [0:0]probe_in133; + input [0:0]probe_in134; + input [0:0]probe_in135; + input [0:0]probe_in136; + input [0:0]probe_in137; + input [0:0]probe_in138; + input [0:0]probe_in139; + input [0:0]probe_in140; + input [0:0]probe_in141; + input [0:0]probe_in142; + input [0:0]probe_in143; + input [0:0]probe_in144; + input [0:0]probe_in145; + input [0:0]probe_in146; + input [0:0]probe_in147; + input [0:0]probe_in148; + input [0:0]probe_in149; + input [0:0]probe_in150; + input [0:0]probe_in151; + input [0:0]probe_in152; + input [0:0]probe_in153; + input [0:0]probe_in154; + input [0:0]probe_in155; + input [0:0]probe_in156; + input [0:0]probe_in157; + input [0:0]probe_in158; + input [0:0]probe_in159; + input [0:0]probe_in160; + input [0:0]probe_in161; + input [0:0]probe_in162; + input [0:0]probe_in163; + input [0:0]probe_in164; + input [0:0]probe_in165; + input [0:0]probe_in166; + input [0:0]probe_in167; + input [0:0]probe_in168; + input [0:0]probe_in169; + input [0:0]probe_in170; + input [0:0]probe_in171; + input [0:0]probe_in172; + input [0:0]probe_in173; + input [0:0]probe_in174; + input [0:0]probe_in175; + input [0:0]probe_in176; + input [0:0]probe_in177; + input [0:0]probe_in178; + input [0:0]probe_in179; + input [0:0]probe_in180; + input [0:0]probe_in181; + input [0:0]probe_in182; + input [0:0]probe_in183; + input [0:0]probe_in184; + input [0:0]probe_in185; + input [0:0]probe_in186; + input [0:0]probe_in187; + input [0:0]probe_in188; + input [0:0]probe_in189; + input [0:0]probe_in190; + input [0:0]probe_in191; + input [0:0]probe_in192; + input [0:0]probe_in193; + input [0:0]probe_in194; + input [0:0]probe_in195; + input [0:0]probe_in196; + input [0:0]probe_in197; + input [0:0]probe_in198; + input [0:0]probe_in199; + input [0:0]probe_in200; + input [0:0]probe_in201; + input [0:0]probe_in202; + input [0:0]probe_in203; + input [0:0]probe_in204; + input [0:0]probe_in205; + input [0:0]probe_in206; + input [0:0]probe_in207; + input [0:0]probe_in208; + input [0:0]probe_in209; + input [0:0]probe_in210; + input [0:0]probe_in211; + input [0:0]probe_in212; + input [0:0]probe_in213; + input [0:0]probe_in214; + input [0:0]probe_in215; + input [0:0]probe_in216; + input [0:0]probe_in217; + input [0:0]probe_in218; + input [0:0]probe_in219; + input [0:0]probe_in220; + input [0:0]probe_in221; + input [0:0]probe_in222; + input [0:0]probe_in223; + input [0:0]probe_in224; + input [0:0]probe_in225; + input [0:0]probe_in226; + input [0:0]probe_in227; + input [0:0]probe_in228; + input [0:0]probe_in229; + input [0:0]probe_in230; + input [0:0]probe_in231; + input [0:0]probe_in232; + input [0:0]probe_in233; + input [0:0]probe_in234; + input [0:0]probe_in235; + input [0:0]probe_in236; + input [0:0]probe_in237; + input [0:0]probe_in238; + input [0:0]probe_in239; + input [0:0]probe_in240; + input [0:0]probe_in241; + input [0:0]probe_in242; + input [0:0]probe_in243; + input [0:0]probe_in244; + input [0:0]probe_in245; + input [0:0]probe_in246; + input [0:0]probe_in247; + input [0:0]probe_in248; + input [0:0]probe_in249; + input [0:0]probe_in250; + input [0:0]probe_in251; + input [0:0]probe_in252; + input [0:0]probe_in253; + input [0:0]probe_in254; + input [0:0]probe_in255; + (* dont_touch = "true" *) input [36:0]sl_iport0; + (* dont_touch = "true" *) output [16:0]sl_oport0; + output [1:0]probe_out0; + output [0:0]probe_out1; + output [31:0]probe_out2; + output [1:0]probe_out3; + output [3:0]probe_out4; + output [0:0]probe_out5; + output [0:0]probe_out6; + output [0:0]probe_out7; + output [0:0]probe_out8; + output [0:0]probe_out9; + output [0:0]probe_out10; + output [0:0]probe_out11; + output [0:0]probe_out12; + output [0:0]probe_out13; + output [0:0]probe_out14; + output [0:0]probe_out15; + output [0:0]probe_out16; + output [0:0]probe_out17; + output [0:0]probe_out18; + output [0:0]probe_out19; + output [0:0]probe_out20; + output [0:0]probe_out21; + output [0:0]probe_out22; + output [0:0]probe_out23; + output [0:0]probe_out24; + output [0:0]probe_out25; + output [0:0]probe_out26; + output [0:0]probe_out27; + output [0:0]probe_out28; + output [0:0]probe_out29; + output [0:0]probe_out30; + output [0:0]probe_out31; + output [0:0]probe_out32; + output [0:0]probe_out33; + output [0:0]probe_out34; + output [0:0]probe_out35; + output [0:0]probe_out36; + output [0:0]probe_out37; + output [0:0]probe_out38; + output [0:0]probe_out39; + output [0:0]probe_out40; + output [0:0]probe_out41; + output [0:0]probe_out42; + output [0:0]probe_out43; + output [0:0]probe_out44; + output [0:0]probe_out45; + output [0:0]probe_out46; + output [0:0]probe_out47; + output [0:0]probe_out48; + output [0:0]probe_out49; + output [0:0]probe_out50; + output [0:0]probe_out51; + output [0:0]probe_out52; + output [0:0]probe_out53; + output [0:0]probe_out54; + output [0:0]probe_out55; + output [0:0]probe_out56; + output [0:0]probe_out57; + output [0:0]probe_out58; + output [0:0]probe_out59; + output [0:0]probe_out60; + output [0:0]probe_out61; + output [0:0]probe_out62; + output [0:0]probe_out63; + output [0:0]probe_out64; + output [0:0]probe_out65; + output [0:0]probe_out66; + output [0:0]probe_out67; + output [0:0]probe_out68; + output [0:0]probe_out69; + output [0:0]probe_out70; + output [0:0]probe_out71; + output [0:0]probe_out72; + output [0:0]probe_out73; + output [0:0]probe_out74; + output [0:0]probe_out75; + output [0:0]probe_out76; + output [0:0]probe_out77; + output [0:0]probe_out78; + output [0:0]probe_out79; + output [0:0]probe_out80; + output [0:0]probe_out81; + output [0:0]probe_out82; + output [0:0]probe_out83; + output [0:0]probe_out84; + output [0:0]probe_out85; + output [0:0]probe_out86; + output [0:0]probe_out87; + output [0:0]probe_out88; + output [0:0]probe_out89; + output [0:0]probe_out90; + output [0:0]probe_out91; + output [0:0]probe_out92; + output [0:0]probe_out93; + output [0:0]probe_out94; + output [0:0]probe_out95; + output [0:0]probe_out96; + output [0:0]probe_out97; + output [0:0]probe_out98; + output [0:0]probe_out99; + output [0:0]probe_out100; + output [0:0]probe_out101; + output [0:0]probe_out102; + output [0:0]probe_out103; + output [0:0]probe_out104; + output [0:0]probe_out105; + output [0:0]probe_out106; + output [0:0]probe_out107; + output [0:0]probe_out108; + output [0:0]probe_out109; + output [0:0]probe_out110; + output [0:0]probe_out111; + output [0:0]probe_out112; + output [0:0]probe_out113; + output [0:0]probe_out114; + output [0:0]probe_out115; + output [0:0]probe_out116; + output [0:0]probe_out117; + output [0:0]probe_out118; + output [0:0]probe_out119; + output [0:0]probe_out120; + output [0:0]probe_out121; + output [0:0]probe_out122; + output [0:0]probe_out123; + output [0:0]probe_out124; + output [0:0]probe_out125; + output [0:0]probe_out126; + output [0:0]probe_out127; + output [0:0]probe_out128; + output [0:0]probe_out129; + output [0:0]probe_out130; + output [0:0]probe_out131; + output [0:0]probe_out132; + output [0:0]probe_out133; + output [0:0]probe_out134; + output [0:0]probe_out135; + output [0:0]probe_out136; + output [0:0]probe_out137; + output [0:0]probe_out138; + output [0:0]probe_out139; + output [0:0]probe_out140; + output [0:0]probe_out141; + output [0:0]probe_out142; + output [0:0]probe_out143; + output [0:0]probe_out144; + output [0:0]probe_out145; + output [0:0]probe_out146; + output [0:0]probe_out147; + output [0:0]probe_out148; + output [0:0]probe_out149; + output [0:0]probe_out150; + output [0:0]probe_out151; + output [0:0]probe_out152; + output [0:0]probe_out153; + output [0:0]probe_out154; + output [0:0]probe_out155; + output [0:0]probe_out156; + output [0:0]probe_out157; + output [0:0]probe_out158; + output [0:0]probe_out159; + output [0:0]probe_out160; + output [0:0]probe_out161; + output [0:0]probe_out162; + output [0:0]probe_out163; + output [0:0]probe_out164; + output [0:0]probe_out165; + output [0:0]probe_out166; + output [0:0]probe_out167; + output [0:0]probe_out168; + output [0:0]probe_out169; + output [0:0]probe_out170; + output [0:0]probe_out171; + output [0:0]probe_out172; + output [0:0]probe_out173; + output [0:0]probe_out174; + output [0:0]probe_out175; + output [0:0]probe_out176; + output [0:0]probe_out177; + output [0:0]probe_out178; + output [0:0]probe_out179; + output [0:0]probe_out180; + output [0:0]probe_out181; + output [0:0]probe_out182; + output [0:0]probe_out183; + output [0:0]probe_out184; + output [0:0]probe_out185; + output [0:0]probe_out186; + output [0:0]probe_out187; + output [0:0]probe_out188; + output [0:0]probe_out189; + output [0:0]probe_out190; + output [0:0]probe_out191; + output [0:0]probe_out192; + output [0:0]probe_out193; + output [0:0]probe_out194; + output [0:0]probe_out195; + output [0:0]probe_out196; + output [0:0]probe_out197; + output [0:0]probe_out198; + output [0:0]probe_out199; + output [0:0]probe_out200; + output [0:0]probe_out201; + output [0:0]probe_out202; + output [0:0]probe_out203; + output [0:0]probe_out204; + output [0:0]probe_out205; + output [0:0]probe_out206; + output [0:0]probe_out207; + output [0:0]probe_out208; + output [0:0]probe_out209; + output [0:0]probe_out210; + output [0:0]probe_out211; + output [0:0]probe_out212; + output [0:0]probe_out213; + output [0:0]probe_out214; + output [0:0]probe_out215; + output [0:0]probe_out216; + output [0:0]probe_out217; + output [0:0]probe_out218; + output [0:0]probe_out219; + output [0:0]probe_out220; + output [0:0]probe_out221; + output [0:0]probe_out222; + output [0:0]probe_out223; + output [0:0]probe_out224; + output [0:0]probe_out225; + output [0:0]probe_out226; + output [0:0]probe_out227; + output [0:0]probe_out228; + output [0:0]probe_out229; + output [0:0]probe_out230; + output [0:0]probe_out231; + output [0:0]probe_out232; + output [0:0]probe_out233; + output [0:0]probe_out234; + output [0:0]probe_out235; + output [0:0]probe_out236; + output [0:0]probe_out237; + output [0:0]probe_out238; + output [0:0]probe_out239; + output [0:0]probe_out240; + output [0:0]probe_out241; + output [0:0]probe_out242; + output [0:0]probe_out243; + output [0:0]probe_out244; + output [0:0]probe_out245; + output [0:0]probe_out246; + output [0:0]probe_out247; + output [0:0]probe_out248; + output [0:0]probe_out249; + output [0:0]probe_out250; + output [0:0]probe_out251; + output [0:0]probe_out252; + output [0:0]probe_out253; + output [0:0]probe_out254; + output [0:0]probe_out255; + + wire \ ; + wire DECODER_INST_n_5; + wire DECODER_INST_n_6; + wire DECODER_INST_n_7; + wire PROBE_OUT_ALL_INST_n_41; + wire PROBE_OUT_ALL_INST_n_45; + wire PROBE_OUT_ALL_INST_n_46; + wire PROBE_OUT_ALL_INST_n_47; + wire PROBE_OUT_ALL_INST_n_48; + wire PROBE_OUT_ALL_INST_n_49; + wire PROBE_OUT_ALL_INST_n_50; + wire PROBE_OUT_ALL_INST_n_51; + wire PROBE_OUT_ALL_INST_n_52; + wire PROBE_OUT_ALL_INST_n_53; + wire PROBE_OUT_ALL_INST_n_54; + wire PROBE_OUT_ALL_INST_n_55; + wire PROBE_OUT_ALL_INST_n_56; + wire PROBE_OUT_ALL_INST_n_57; + wire PROBE_OUT_ALL_INST_n_58; + wire PROBE_OUT_ALL_INST_n_59; + wire PROBE_OUT_ALL_INST_n_60; + wire [16:0]bus_addr; + (* DONT_TOUCH *) wire bus_clk; + wire \bus_data_int_reg_n_0_[0] ; + wire \bus_data_int_reg_n_0_[10] ; + wire \bus_data_int_reg_n_0_[11] ; + wire \bus_data_int_reg_n_0_[12] ; + wire \bus_data_int_reg_n_0_[13] ; + wire \bus_data_int_reg_n_0_[14] ; + wire \bus_data_int_reg_n_0_[15] ; + wire \bus_data_int_reg_n_0_[2] ; + wire \bus_data_int_reg_n_0_[3] ; + wire \bus_data_int_reg_n_0_[4] ; + wire \bus_data_int_reg_n_0_[5] ; + wire \bus_data_int_reg_n_0_[6] ; + wire \bus_data_int_reg_n_0_[7] ; + wire \bus_data_int_reg_n_0_[8] ; + wire \bus_data_int_reg_n_0_[9] ; + wire bus_den; + wire [15:0]bus_di; + wire [15:0]bus_do; + wire bus_drdy; + wire bus_dwe; + wire bus_rst; + wire clear; + wire clk; + wire committ; + wire internal_cnt_rst; + wire p_0_in; + wire [1:0]probe_out0; + wire [0:0]probe_out1; + wire [31:0]probe_out2; + wire [1:0]probe_out3; + wire [3:0]probe_out4; + wire [8:0]probe_width_int; + wire rd_probe_out_width; + (* DONT_TOUCH *) wire [36:0]sl_iport0; + (* DONT_TOUCH *) wire [16:0]sl_oport0; + wire [2:0]xsdb_addr_2_0_p1; + + assign probe_out10[0] = \ ; + assign probe_out100[0] = \ ; + assign probe_out101[0] = \ ; + assign probe_out102[0] = \ ; + assign probe_out103[0] = \ ; + assign probe_out104[0] = \ ; + assign probe_out105[0] = \ ; + assign probe_out106[0] = \ ; + assign probe_out107[0] = \ ; + assign probe_out108[0] = \ ; + assign probe_out109[0] = \ ; + assign probe_out11[0] = \ ; + assign probe_out110[0] = \ ; + assign probe_out111[0] = \ ; + assign probe_out112[0] = \ ; + assign probe_out113[0] = \ ; + assign probe_out114[0] = \ ; + assign probe_out115[0] = \ ; + assign probe_out116[0] = \ ; + assign probe_out117[0] = \ ; + assign probe_out118[0] = \ ; + assign probe_out119[0] = \ ; + assign probe_out12[0] = \ ; + assign probe_out120[0] = \ ; + assign probe_out121[0] = \ ; + assign probe_out122[0] = \ ; + assign probe_out123[0] = \ ; + assign probe_out124[0] = \ ; + assign probe_out125[0] = \ ; + assign probe_out126[0] = \ ; + assign probe_out127[0] = \ ; + assign probe_out128[0] = \ ; + assign probe_out129[0] = \ ; + assign probe_out13[0] = \ ; + assign probe_out130[0] = \ ; + assign probe_out131[0] = \ ; + assign probe_out132[0] = \ ; + assign probe_out133[0] = \ ; + assign probe_out134[0] = \ ; + assign probe_out135[0] = \ ; + assign probe_out136[0] = \ ; + assign probe_out137[0] = \ ; + assign probe_out138[0] = \ ; + assign probe_out139[0] = \ ; + assign probe_out14[0] = \ ; + assign probe_out140[0] = \ ; + assign probe_out141[0] = \ ; + assign probe_out142[0] = \ ; + assign probe_out143[0] = \ ; + assign probe_out144[0] = \ ; + assign probe_out145[0] = \ ; + assign probe_out146[0] = \ ; + assign probe_out147[0] = \ ; + assign probe_out148[0] = \ ; + assign probe_out149[0] = \ ; + assign probe_out15[0] = \ ; + assign probe_out150[0] = \ ; + assign probe_out151[0] = \ ; + assign probe_out152[0] = \ ; + assign probe_out153[0] = \ ; + assign probe_out154[0] = \ ; + assign probe_out155[0] = \ ; + assign probe_out156[0] = \ ; + assign probe_out157[0] = \ ; + assign probe_out158[0] = \ ; + assign probe_out159[0] = \ ; + assign probe_out16[0] = \ ; + assign probe_out160[0] = \ ; + assign probe_out161[0] = \ ; + assign probe_out162[0] = \ ; + assign probe_out163[0] = \ ; + assign probe_out164[0] = \ ; + assign probe_out165[0] = \ ; + assign probe_out166[0] = \ ; + assign probe_out167[0] = \ ; + assign probe_out168[0] = \ ; + assign probe_out169[0] = \ ; + assign probe_out17[0] = \ ; + assign probe_out170[0] = \ ; + assign probe_out171[0] = \ ; + assign probe_out172[0] = \ ; + assign probe_out173[0] = \ ; + assign probe_out174[0] = \ ; + assign probe_out175[0] = \ ; + assign probe_out176[0] = \ ; + assign probe_out177[0] = \ ; + assign probe_out178[0] = \ ; + assign probe_out179[0] = \ ; + assign probe_out18[0] = \ ; + assign probe_out180[0] = \ ; + assign probe_out181[0] = \ ; + assign probe_out182[0] = \ ; + assign probe_out183[0] = \ ; + assign probe_out184[0] = \ ; + assign probe_out185[0] = \ ; + assign probe_out186[0] = \ ; + assign probe_out187[0] = \ ; + assign probe_out188[0] = \ ; + assign probe_out189[0] = \ ; + assign probe_out19[0] = \ ; + assign probe_out190[0] = \ ; + assign probe_out191[0] = \ ; + assign probe_out192[0] = \ ; + assign probe_out193[0] = \ ; + assign probe_out194[0] = \ ; + assign probe_out195[0] = \ ; + assign probe_out196[0] = \ ; + assign probe_out197[0] = \ ; + assign probe_out198[0] = \ ; + assign probe_out199[0] = \ ; + assign probe_out20[0] = \ ; + assign probe_out200[0] = \ ; + assign probe_out201[0] = \ ; + assign probe_out202[0] = \ ; + assign probe_out203[0] = \ ; + assign probe_out204[0] = \ ; + assign probe_out205[0] = \ ; + assign probe_out206[0] = \ ; + assign probe_out207[0] = \ ; + assign probe_out208[0] = \ ; + assign probe_out209[0] = \ ; + assign probe_out21[0] = \ ; + assign probe_out210[0] = \ ; + assign probe_out211[0] = \ ; + assign probe_out212[0] = \ ; + assign probe_out213[0] = \ ; + assign probe_out214[0] = \ ; + assign probe_out215[0] = \ ; + assign probe_out216[0] = \ ; + assign probe_out217[0] = \ ; + assign probe_out218[0] = \ ; + assign probe_out219[0] = \ ; + assign probe_out22[0] = \ ; + assign probe_out220[0] = \ ; + assign probe_out221[0] = \ ; + assign probe_out222[0] = \ ; + assign probe_out223[0] = \ ; + assign probe_out224[0] = \ ; + assign probe_out225[0] = \ ; + assign probe_out226[0] = \ ; + assign probe_out227[0] = \ ; + assign probe_out228[0] = \ ; + assign probe_out229[0] = \ ; + assign probe_out23[0] = \ ; + assign probe_out230[0] = \ ; + assign probe_out231[0] = \ ; + assign probe_out232[0] = \ ; + assign probe_out233[0] = \ ; + assign probe_out234[0] = \ ; + assign probe_out235[0] = \ ; + assign probe_out236[0] = \ ; + assign probe_out237[0] = \ ; + assign probe_out238[0] = \ ; + assign probe_out239[0] = \ ; + assign probe_out24[0] = \ ; + assign probe_out240[0] = \ ; + assign probe_out241[0] = \ ; + assign probe_out242[0] = \ ; + assign probe_out243[0] = \ ; + assign probe_out244[0] = \ ; + assign probe_out245[0] = \ ; + assign probe_out246[0] = \ ; + assign probe_out247[0] = \ ; + assign probe_out248[0] = \ ; + assign probe_out249[0] = \ ; + assign probe_out25[0] = \ ; + assign probe_out250[0] = \ ; + assign probe_out251[0] = \ ; + assign probe_out252[0] = \ ; + assign probe_out253[0] = \ ; + assign probe_out254[0] = \ ; + assign probe_out255[0] = \ ; + assign probe_out26[0] = \ ; + assign probe_out27[0] = \ ; + assign probe_out28[0] = \ ; + assign probe_out29[0] = \ ; + assign probe_out30[0] = \ ; + assign probe_out31[0] = \ ; + assign probe_out32[0] = \ ; + assign probe_out33[0] = \ ; + assign probe_out34[0] = \ ; + assign probe_out35[0] = \ ; + assign probe_out36[0] = \ ; + assign probe_out37[0] = \ ; + assign probe_out38[0] = \ ; + assign probe_out39[0] = \ ; + assign probe_out40[0] = \ ; + assign probe_out41[0] = \ ; + assign probe_out42[0] = \ ; + assign probe_out43[0] = \ ; + assign probe_out44[0] = \ ; + assign probe_out45[0] = \ ; + assign probe_out46[0] = \ ; + assign probe_out47[0] = \ ; + assign probe_out48[0] = \ ; + assign probe_out49[0] = \ ; + assign probe_out5[0] = \ ; + assign probe_out50[0] = \ ; + assign probe_out51[0] = \ ; + assign probe_out52[0] = \ ; + assign probe_out53[0] = \ ; + assign probe_out54[0] = \ ; + assign probe_out55[0] = \ ; + assign probe_out56[0] = \ ; + assign probe_out57[0] = \ ; + assign probe_out58[0] = \ ; + assign probe_out59[0] = \ ; + assign probe_out6[0] = \ ; + assign probe_out60[0] = \ ; + assign probe_out61[0] = \ ; + assign probe_out62[0] = \ ; + assign probe_out63[0] = \ ; + assign probe_out64[0] = \ ; + assign probe_out65[0] = \ ; + assign probe_out66[0] = \ ; + assign probe_out67[0] = \ ; + assign probe_out68[0] = \ ; + assign probe_out69[0] = \ ; + assign probe_out7[0] = \ ; + assign probe_out70[0] = \ ; + assign probe_out71[0] = \ ; + assign probe_out72[0] = \ ; + assign probe_out73[0] = \ ; + assign probe_out74[0] = \ ; + assign probe_out75[0] = \ ; + assign probe_out76[0] = \ ; + assign probe_out77[0] = \ ; + assign probe_out78[0] = \ ; + assign probe_out79[0] = \ ; + assign probe_out8[0] = \ ; + assign probe_out80[0] = \ ; + assign probe_out81[0] = \ ; + assign probe_out82[0] = \ ; + assign probe_out83[0] = \ ; + assign probe_out84[0] = \ ; + assign probe_out85[0] = \ ; + assign probe_out86[0] = \ ; + assign probe_out87[0] = \ ; + assign probe_out88[0] = \ ; + assign probe_out89[0] = \ ; + assign probe_out9[0] = \ ; + assign probe_out90[0] = \ ; + assign probe_out91[0] = \ ; + assign probe_out92[0] = \ ; + assign probe_out93[0] = \ ; + assign probe_out94[0] = \ ; + assign probe_out95[0] = \ ; + assign probe_out96[0] = \ ; + assign probe_out97[0] = \ ; + assign probe_out98[0] = \ ; + assign probe_out99[0] = \ ; + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_decoder DECODER_INST + (.\Bus_data_out_reg[10]_0 (PROBE_OUT_ALL_INST_n_54), + .\Bus_data_out_reg[11]_0 (PROBE_OUT_ALL_INST_n_53), + .\Bus_data_out_reg[12]_0 (PROBE_OUT_ALL_INST_n_52), + .\Bus_data_out_reg[13]_0 (PROBE_OUT_ALL_INST_n_51), + .\Bus_data_out_reg[14]_0 (PROBE_OUT_ALL_INST_n_50), + .\Bus_data_out_reg[15]_0 (bus_do), + .\Bus_data_out_reg[15]_1 (PROBE_OUT_ALL_INST_n_49), + .\Bus_data_out_reg[3]_0 ({probe_width_int[8],probe_width_int[1:0]}), + .\Bus_data_out_reg[4]_0 (PROBE_OUT_ALL_INST_n_60), + .\Bus_data_out_reg[5]_0 (PROBE_OUT_ALL_INST_n_59), + .\Bus_data_out_reg[6]_0 (PROBE_OUT_ALL_INST_n_58), + .\Bus_data_out_reg[7]_0 (PROBE_OUT_ALL_INST_n_57), + .\Bus_data_out_reg[8]_0 (PROBE_OUT_ALL_INST_n_56), + .\Bus_data_out_reg[9]_0 (PROBE_OUT_ALL_INST_n_55), + .\G_PROBE_OUT[0].wr_probe_out[0]_i_3_0 (DECODER_INST_n_7), + .\G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 (DECODER_INST_n_5), + .Q({PROBE_OUT_ALL_INST_n_45,PROBE_OUT_ALL_INST_n_46,PROBE_OUT_ALL_INST_n_47,PROBE_OUT_ALL_INST_n_48}), + .SR(clear), + .in0(committ), + .internal_cnt_rst(internal_cnt_rst), + .out(bus_clk), + .\probe_out_modified_reg[15]_0 ({\bus_data_int_reg_n_0_[15] ,\bus_data_int_reg_n_0_[14] ,\bus_data_int_reg_n_0_[13] ,\bus_data_int_reg_n_0_[12] ,\bus_data_int_reg_n_0_[11] ,\bus_data_int_reg_n_0_[10] ,\bus_data_int_reg_n_0_[9] ,\bus_data_int_reg_n_0_[8] ,\bus_data_int_reg_n_0_[7] ,\bus_data_int_reg_n_0_[6] ,\bus_data_int_reg_n_0_[5] ,\bus_data_int_reg_n_0_[4] ,\bus_data_int_reg_n_0_[3] ,\bus_data_int_reg_n_0_[2] ,p_0_in,\bus_data_int_reg_n_0_[0] }), + .\rd_en_reg[6]_0 (PROBE_OUT_ALL_INST_n_41), + .rd_probe_out_width(rd_probe_out_width), + .s_daddr_o(bus_addr), + .s_den_o(bus_den), + .s_den_o_INST_0(DECODER_INST_n_6), + .s_drdy_i(bus_drdy), + .s_dwe_o(bus_dwe), + .s_rst_o(bus_rst), + .\xsdb_addr_2_0_p2_reg[2]_0 (xsdb_addr_2_0_p1)); + GND GND + (.G(\ )); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_all PROBE_OUT_ALL_INST + (.\G_PROBE_OUT[0].wr_probe_out_reg[0]_0 (DECODER_INST_n_7), + .\G_PROBE_OUT[0].wr_probe_out_reg[0]_1 (DECODER_INST_n_5), + .\G_PROBE_OUT[0].wr_probe_out_reg[0]_2 (DECODER_INST_n_6), + .\Probe_out_reg_int_reg[10]_0 (PROBE_OUT_ALL_INST_n_54), + .\Probe_out_reg_int_reg[11]_0 (PROBE_OUT_ALL_INST_n_53), + .\Probe_out_reg_int_reg[12]_0 (PROBE_OUT_ALL_INST_n_52), + .\Probe_out_reg_int_reg[13]_0 (PROBE_OUT_ALL_INST_n_51), + .\Probe_out_reg_int_reg[14]_0 (PROBE_OUT_ALL_INST_n_50), + .\Probe_out_reg_int_reg[15]_0 (PROBE_OUT_ALL_INST_n_49), + .\Probe_out_reg_int_reg[3]_0 ({PROBE_OUT_ALL_INST_n_45,PROBE_OUT_ALL_INST_n_46,PROBE_OUT_ALL_INST_n_47,PROBE_OUT_ALL_INST_n_48}), + .\Probe_out_reg_int_reg[4]_0 (PROBE_OUT_ALL_INST_n_60), + .\Probe_out_reg_int_reg[5]_0 (PROBE_OUT_ALL_INST_n_59), + .\Probe_out_reg_int_reg[6]_0 (PROBE_OUT_ALL_INST_n_58), + .\Probe_out_reg_int_reg[7]_0 (PROBE_OUT_ALL_INST_n_57), + .\Probe_out_reg_int_reg[8]_0 (PROBE_OUT_ALL_INST_n_56), + .\Probe_out_reg_int_reg[9]_0 (PROBE_OUT_ALL_INST_n_55), + .Q({\bus_data_int_reg_n_0_[15] ,\bus_data_int_reg_n_0_[14] ,\bus_data_int_reg_n_0_[13] ,\bus_data_int_reg_n_0_[12] ,\bus_data_int_reg_n_0_[11] ,\bus_data_int_reg_n_0_[10] ,\bus_data_int_reg_n_0_[9] ,\bus_data_int_reg_n_0_[8] ,\bus_data_int_reg_n_0_[7] ,\bus_data_int_reg_n_0_[6] ,\bus_data_int_reg_n_0_[5] ,\bus_data_int_reg_n_0_[4] ,\bus_data_int_reg_n_0_[3] ,\bus_data_int_reg_n_0_[2] ,p_0_in,\bus_data_int_reg_n_0_[0] }), + .SR(clear), + .\addr_count[1]_i_5 (PROBE_OUT_ALL_INST_n_41), + .\addr_p1_reg[2]_0 (xsdb_addr_2_0_p1), + .clk(clk), + .in0(committ), + .internal_cnt_rst(internal_cnt_rst), + .out(bus_clk), + .probe_out0(probe_out0), + .probe_out1(probe_out1), + .probe_out2(probe_out2), + .probe_out3(probe_out3), + .probe_out4(probe_out4), + .s_daddr_o(bus_addr), + .s_den_o(bus_den), + .s_dwe_o(bus_dwe)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_width PROBE_OUT_WIDTH_INST + (.Q({probe_width_int[8],probe_width_int[1:0]}), + .internal_cnt_rst(internal_cnt_rst), + .out(bus_clk), + .rd_probe_out_width(rd_probe_out_width), + .s_rst_o(bus_rst)); + (* C_BUILD_REVISION = "0" *) + (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) + (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) + (* C_CORE_MAJOR_VER = "2" *) + (* C_CORE_MINOR_VER = "0" *) + (* C_CORE_TYPE = "2" *) + (* C_CSE_DRV_VER = "1" *) + (* C_MAJOR_VERSION = "2013" *) + (* C_MINOR_VERSION = "1" *) + (* C_NEXT_SLAVE = "0" *) + (* C_PIPE_IFACE = "0" *) + (* C_USE_TEST_REG = "1" *) + (* C_XDEVICEFAMILY = "kintex7" *) + (* C_XSDB_SLAVE_TYPE = "33" *) + (* DONT_TOUCH *) + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs U_XSDB_SLAVE + (.s_daddr_o(bus_addr), + .s_dclk_o(bus_clk), + .s_den_o(bus_den), + .s_di_o(bus_di), + .s_do_i(bus_do), + .s_drdy_i(bus_drdy), + .s_dwe_o(bus_dwe), + .s_rst_o(bus_rst), + .sl_iport_i(sl_iport0), + .sl_oport_o(sl_oport0)); + FDRE \bus_data_int_reg[0] + (.C(bus_clk), + .CE(1'b1), + .D(bus_di[0]), + .Q(\bus_data_int_reg_n_0_[0] ), + .R(1'b0)); + FDRE \bus_data_int_reg[10] + (.C(bus_clk), + .CE(1'b1), + .D(bus_di[10]), + .Q(\bus_data_int_reg_n_0_[10] ), + .R(1'b0)); + FDRE \bus_data_int_reg[11] + (.C(bus_clk), + .CE(1'b1), + .D(bus_di[11]), + .Q(\bus_data_int_reg_n_0_[11] ), + .R(1'b0)); + FDRE \bus_data_int_reg[12] + (.C(bus_clk), + .CE(1'b1), + .D(bus_di[12]), + .Q(\bus_data_int_reg_n_0_[12] ), + .R(1'b0)); + FDRE \bus_data_int_reg[13] + (.C(bus_clk), + .CE(1'b1), + .D(bus_di[13]), + .Q(\bus_data_int_reg_n_0_[13] ), + .R(1'b0)); + FDRE \bus_data_int_reg[14] + (.C(bus_clk), + .CE(1'b1), + .D(bus_di[14]), + .Q(\bus_data_int_reg_n_0_[14] ), + .R(1'b0)); + FDRE \bus_data_int_reg[15] + (.C(bus_clk), + .CE(1'b1), + .D(bus_di[15]), + .Q(\bus_data_int_reg_n_0_[15] ), + .R(1'b0)); + FDRE \bus_data_int_reg[1] + (.C(bus_clk), + .CE(1'b1), + .D(bus_di[1]), + .Q(p_0_in), + .R(1'b0)); + FDRE \bus_data_int_reg[2] + (.C(bus_clk), + .CE(1'b1), + .D(bus_di[2]), + .Q(\bus_data_int_reg_n_0_[2] ), + .R(1'b0)); + FDRE \bus_data_int_reg[3] + (.C(bus_clk), + .CE(1'b1), + .D(bus_di[3]), + .Q(\bus_data_int_reg_n_0_[3] ), + .R(1'b0)); + FDRE \bus_data_int_reg[4] + (.C(bus_clk), + .CE(1'b1), + .D(bus_di[4]), + .Q(\bus_data_int_reg_n_0_[4] ), + .R(1'b0)); + FDRE \bus_data_int_reg[5] + (.C(bus_clk), + .CE(1'b1), + .D(bus_di[5]), + .Q(\bus_data_int_reg_n_0_[5] ), + .R(1'b0)); + FDRE \bus_data_int_reg[6] + (.C(bus_clk), + .CE(1'b1), + .D(bus_di[6]), + .Q(\bus_data_int_reg_n_0_[6] ), + .R(1'b0)); + FDRE \bus_data_int_reg[7] + (.C(bus_clk), + .CE(1'b1), + .D(bus_di[7]), + .Q(\bus_data_int_reg_n_0_[7] ), + .R(1'b0)); + FDRE \bus_data_int_reg[8] + (.C(bus_clk), + .CE(1'b1), + .D(bus_di[8]), + .Q(\bus_data_int_reg_n_0_[8] ), + .R(1'b0)); + FDRE \bus_data_int_reg[9] + (.C(bus_clk), + .CE(1'b1), + .D(bus_di[9]), + .Q(\bus_data_int_reg_n_0_[9] ), + .R(1'b0)); +endmodule + +(* C_BUILD_REVISION = "0" *) (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) +(* C_CORE_MAJOR_VER = "2" *) (* C_CORE_MINOR_VER = "0" *) (* C_CORE_TYPE = "2" *) +(* C_CSE_DRV_VER = "1" *) (* C_MAJOR_VERSION = "2013" *) (* C_MINOR_VERSION = "1" *) +(* C_NEXT_SLAVE = "0" *) (* C_PIPE_IFACE = "0" *) (* C_USE_TEST_REG = "1" *) +(* C_XDEVICEFAMILY = "kintex7" *) (* C_XSDB_SLAVE_TYPE = "33" *) (* dont_touch = "true" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs + (s_rst_o, + s_dclk_o, + s_den_o, + s_dwe_o, + s_daddr_o, + s_di_o, + sl_oport_o, + s_do_i, + sl_iport_i, + s_drdy_i); + output s_rst_o; + output s_dclk_o; + output s_den_o; + output s_dwe_o; + output [16:0]s_daddr_o; + output [15:0]s_di_o; + output [16:0]sl_oport_o; + input [15:0]s_do_i; + input [36:0]sl_iport_i; + input s_drdy_i; + + wire [15:0]reg_do; + wire \reg_do[0]_i_2_n_0 ; + wire \reg_do[0]_i_3_n_0 ; + wire \reg_do[0]_i_4_n_0 ; + wire \reg_do[10]_i_2_n_0 ; + wire \reg_do[10]_i_3_n_0 ; + wire \reg_do[10]_i_4_n_0 ; + wire \reg_do[10]_i_5_n_0 ; + wire \reg_do[11]_i_2_n_0 ; + wire \reg_do[11]_i_3_n_0 ; + wire \reg_do[12]_i_2_n_0 ; + wire \reg_do[12]_i_3_n_0 ; + wire \reg_do[13]_i_2_n_0 ; + wire \reg_do[13]_i_3_n_0 ; + wire \reg_do[14]_i_2_n_0 ; + wire \reg_do[14]_i_3_n_0 ; + wire \reg_do[15]_i_2_n_0 ; + wire \reg_do[15]_i_3_n_0 ; + wire \reg_do[15]_i_4_n_0 ; + wire \reg_do[15]_i_5_n_0 ; + wire \reg_do[15]_i_6_n_0 ; + wire \reg_do[1]_i_2_n_0 ; + wire \reg_do[1]_i_3_n_0 ; + wire \reg_do[1]_i_4_n_0 ; + wire \reg_do[2]_i_2_n_0 ; + wire \reg_do[2]_i_3_n_0 ; + wire \reg_do[2]_i_4_n_0 ; + wire \reg_do[3]_i_2_n_0 ; + wire \reg_do[3]_i_3_n_0 ; + wire \reg_do[3]_i_4_n_0 ; + wire \reg_do[4]_i_2_n_0 ; + wire \reg_do[4]_i_3_n_0 ; + wire \reg_do[4]_i_4_n_0 ; + wire \reg_do[5]_i_2_n_0 ; + wire \reg_do[5]_i_3_n_0 ; + wire \reg_do[5]_i_4_n_0 ; + wire \reg_do[5]_i_5_n_0 ; + wire \reg_do[6]_i_2_n_0 ; + wire \reg_do[6]_i_3_n_0 ; + wire \reg_do[6]_i_4_n_0 ; + wire \reg_do[7]_i_2_n_0 ; + wire \reg_do[7]_i_3_n_0 ; + wire \reg_do[7]_i_4_n_0 ; + wire \reg_do[8]_i_2_n_0 ; + wire \reg_do[8]_i_3_n_0 ; + wire \reg_do[8]_i_4_n_0 ; + wire \reg_do[9]_i_2_n_0 ; + wire \reg_do[9]_i_3_n_0 ; + wire \reg_do[9]_i_4_n_0 ; + wire \reg_do[9]_i_5_n_0 ; + wire \reg_do[9]_i_6_n_0 ; + wire \reg_do_reg_n_0_[0] ; + wire \reg_do_reg_n_0_[10] ; + wire \reg_do_reg_n_0_[11] ; + wire \reg_do_reg_n_0_[12] ; + wire \reg_do_reg_n_0_[13] ; + wire \reg_do_reg_n_0_[14] ; + wire \reg_do_reg_n_0_[15] ; + wire \reg_do_reg_n_0_[1] ; + wire \reg_do_reg_n_0_[2] ; + wire \reg_do_reg_n_0_[3] ; + wire \reg_do_reg_n_0_[4] ; + wire \reg_do_reg_n_0_[5] ; + wire \reg_do_reg_n_0_[6] ; + wire \reg_do_reg_n_0_[7] ; + wire \reg_do_reg_n_0_[8] ; + wire \reg_do_reg_n_0_[9] ; + wire reg_drdy; + wire reg_drdy_i_1_n_0; + wire [15:0]reg_test; + wire reg_test0; + wire s_den_o; + wire s_den_o_INST_0_i_1_n_0; + wire [15:0]s_do_i; + wire s_drdy_i; + wire [36:0]sl_iport_i; + wire [16:0]sl_oport_o; + (* DONT_TOUCH *) (* UUID = "1" *) wire [127:0]uuid_stamp; + + assign s_daddr_o[16:0] = sl_iport_i[20:4]; + assign s_dclk_o = sl_iport_i[1]; + assign s_di_o[15:0] = sl_iport_i[36:21]; + assign s_dwe_o = sl_iport_i[3]; + assign s_rst_o = sl_iport_i[0]; + LUT6 #( + .INIT(64'hAAAAAAAA0020AAAA)) + \reg_do[0]_i_1 + (.I0(\reg_do[0]_i_2_n_0 ), + .I1(\reg_do[9]_i_3_n_0 ), + .I2(reg_test[0]), + .I3(sl_iport_i[4]), + .I4(sl_iport_i[5]), + .I5(\reg_do[9]_i_2_n_0 ), + .O(reg_do[0])); + LUT6 #( + .INIT(64'hABABABAAAAAAABAA)) + \reg_do[0]_i_2 + (.I0(\reg_do[5]_i_3_n_0 ), + .I1(sl_iport_i[8]), + .I2(sl_iport_i[7]), + .I3(\reg_do[0]_i_3_n_0 ), + .I4(sl_iport_i[6]), + .I5(\reg_do[0]_i_4_n_0 ), + .O(\reg_do[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[0]_i_3 + (.I0(uuid_stamp[48]), + .I1(uuid_stamp[32]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[16]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[0]), + .O(\reg_do[0]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[0]_i_4 + (.I0(uuid_stamp[112]), + .I1(uuid_stamp[96]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[80]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[64]), + .O(\reg_do[0]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFF2808)) + \reg_do[10]_i_1 + (.I0(\reg_do[10]_i_2_n_0 ), + .I1(sl_iport_i[4]), + .I2(sl_iport_i[5]), + .I3(reg_test[10]), + .I4(\reg_do[10]_i_3_n_0 ), + .O(reg_do[10])); + LUT6 #( + .INIT(64'h0800000000000000)) + \reg_do[10]_i_2 + (.I0(sl_iport_i[6]), + .I1(sl_iport_i[9]), + .I2(sl_iport_i[7]), + .I3(sl_iport_i[8]), + .I4(sl_iport_i[11]), + .I5(sl_iport_i[10]), + .O(\reg_do[10]_i_2_n_0 )); + LUT6 #( + .INIT(64'h00000000AAFBAA08)) + \reg_do[10]_i_3 + (.I0(\reg_do[10]_i_4_n_0 ), + .I1(sl_iport_i[6]), + .I2(sl_iport_i[7]), + .I3(sl_iport_i[8]), + .I4(\reg_do[10]_i_5_n_0 ), + .I5(\reg_do[15]_i_4_n_0 ), + .O(\reg_do[10]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[10]_i_4 + (.I0(uuid_stamp[122]), + .I1(uuid_stamp[106]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[90]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[74]), + .O(\reg_do[10]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[10]_i_5 + (.I0(uuid_stamp[58]), + .I1(uuid_stamp[42]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[26]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[10]), + .O(\reg_do[10]_i_5_n_0 )); + LUT6 #( + .INIT(64'h4540FFFF45404540)) + \reg_do[11]_i_1 + (.I0(\reg_do[15]_i_4_n_0 ), + .I1(\reg_do[11]_i_2_n_0 ), + .I2(\reg_do[15]_i_2_n_0 ), + .I3(\reg_do[11]_i_3_n_0 ), + .I4(\reg_do[15]_i_6_n_0 ), + .I5(reg_test[11]), + .O(reg_do[11])); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[11]_i_2 + (.I0(uuid_stamp[59]), + .I1(uuid_stamp[43]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[27]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[11]), + .O(\reg_do[11]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[11]_i_3 + (.I0(uuid_stamp[123]), + .I1(uuid_stamp[107]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[91]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[75]), + .O(\reg_do[11]_i_3_n_0 )); + LUT6 #( + .INIT(64'h5404FFFF54045404)) + \reg_do[12]_i_1 + (.I0(\reg_do[15]_i_4_n_0 ), + .I1(\reg_do[12]_i_2_n_0 ), + .I2(\reg_do[15]_i_2_n_0 ), + .I3(\reg_do[12]_i_3_n_0 ), + .I4(\reg_do[15]_i_6_n_0 ), + .I5(reg_test[12]), + .O(reg_do[12])); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[12]_i_2 + (.I0(uuid_stamp[124]), + .I1(uuid_stamp[108]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[92]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[76]), + .O(\reg_do[12]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[12]_i_3 + (.I0(uuid_stamp[60]), + .I1(uuid_stamp[44]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[28]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[12]), + .O(\reg_do[12]_i_3_n_0 )); + LUT6 #( + .INIT(64'h4540FFFF45404540)) + \reg_do[13]_i_1 + (.I0(\reg_do[15]_i_4_n_0 ), + .I1(\reg_do[13]_i_2_n_0 ), + .I2(\reg_do[15]_i_2_n_0 ), + .I3(\reg_do[13]_i_3_n_0 ), + .I4(\reg_do[15]_i_6_n_0 ), + .I5(reg_test[13]), + .O(reg_do[13])); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[13]_i_2 + (.I0(uuid_stamp[61]), + .I1(uuid_stamp[45]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[29]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[13]), + .O(\reg_do[13]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[13]_i_3 + (.I0(uuid_stamp[125]), + .I1(uuid_stamp[109]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[93]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[77]), + .O(\reg_do[13]_i_3_n_0 )); + LUT6 #( + .INIT(64'h4540FFFF45404540)) + \reg_do[14]_i_1 + (.I0(\reg_do[15]_i_4_n_0 ), + .I1(\reg_do[14]_i_2_n_0 ), + .I2(\reg_do[15]_i_2_n_0 ), + .I3(\reg_do[14]_i_3_n_0 ), + .I4(\reg_do[15]_i_6_n_0 ), + .I5(reg_test[14]), + .O(reg_do[14])); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[14]_i_2 + (.I0(uuid_stamp[62]), + .I1(uuid_stamp[46]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[30]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[14]), + .O(\reg_do[14]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[14]_i_3 + (.I0(uuid_stamp[126]), + .I1(uuid_stamp[110]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[94]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[78]), + .O(\reg_do[14]_i_3_n_0 )); + LUT6 #( + .INIT(64'h0B01FFFF0B010B01)) + \reg_do[15]_i_1 + (.I0(\reg_do[15]_i_2_n_0 ), + .I1(\reg_do[15]_i_3_n_0 ), + .I2(\reg_do[15]_i_4_n_0 ), + .I3(\reg_do[15]_i_5_n_0 ), + .I4(\reg_do[15]_i_6_n_0 ), + .I5(reg_test[15]), + .O(reg_do[15])); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT3 #( + .INIT(8'h45)) + \reg_do[15]_i_2 + (.I0(sl_iport_i[8]), + .I1(sl_iport_i[7]), + .I2(sl_iport_i[6]), + .O(\reg_do[15]_i_2_n_0 )); + LUT6 #( + .INIT(64'h505F3030505F3F3F)) + \reg_do[15]_i_3 + (.I0(uuid_stamp[127]), + .I1(uuid_stamp[111]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[95]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[79]), + .O(\reg_do[15]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hFFFFFFFE)) + \reg_do[15]_i_4 + (.I0(sl_iport_i[7]), + .I1(sl_iport_i[8]), + .I2(sl_iport_i[9]), + .I3(sl_iport_i[11]), + .I4(sl_iport_i[10]), + .O(\reg_do[15]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[15]_i_5 + (.I0(uuid_stamp[63]), + .I1(uuid_stamp[47]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[31]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[15]), + .O(\reg_do[15]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFD0FFFFFFFF)) + \reg_do[15]_i_6 + (.I0(sl_iport_i[6]), + .I1(sl_iport_i[7]), + .I2(sl_iport_i[8]), + .I3(\reg_do[9]_i_2_n_0 ), + .I4(sl_iport_i[4]), + .I5(sl_iport_i[5]), + .O(\reg_do[15]_i_6_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAAAAAAAFEAA)) + \reg_do[1]_i_1 + (.I0(\reg_do[1]_i_2_n_0 ), + .I1(reg_test[1]), + .I2(\reg_do[9]_i_3_n_0 ), + .I3(sl_iport_i[5]), + .I4(sl_iport_i[4]), + .I5(\reg_do[9]_i_2_n_0 ), + .O(reg_do[1])); + LUT6 #( + .INIT(64'h00000000FFAE00A2)) + \reg_do[1]_i_2 + (.I0(\reg_do[1]_i_3_n_0 ), + .I1(sl_iport_i[6]), + .I2(sl_iport_i[7]), + .I3(sl_iport_i[8]), + .I4(\reg_do[1]_i_4_n_0 ), + .I5(\reg_do[15]_i_4_n_0 ), + .O(\reg_do[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[1]_i_3 + (.I0(uuid_stamp[49]), + .I1(uuid_stamp[33]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[17]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[1]), + .O(\reg_do[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[1]_i_4 + (.I0(uuid_stamp[113]), + .I1(uuid_stamp[97]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[81]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[65]), + .O(\reg_do[1]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFF6200)) + \reg_do[2]_i_1 + (.I0(sl_iport_i[4]), + .I1(sl_iport_i[5]), + .I2(reg_test[2]), + .I3(\reg_do[10]_i_2_n_0 ), + .I4(\reg_do[2]_i_2_n_0 ), + .O(reg_do[2])); + LUT6 #( + .INIT(64'h00000000AAFBAA08)) + \reg_do[2]_i_2 + (.I0(\reg_do[2]_i_3_n_0 ), + .I1(sl_iport_i[6]), + .I2(sl_iport_i[7]), + .I3(sl_iport_i[8]), + .I4(\reg_do[2]_i_4_n_0 ), + .I5(\reg_do[15]_i_4_n_0 ), + .O(\reg_do[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[2]_i_3 + (.I0(uuid_stamp[114]), + .I1(uuid_stamp[98]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[82]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[66]), + .O(\reg_do[2]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[2]_i_4 + (.I0(uuid_stamp[50]), + .I1(uuid_stamp[34]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[18]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[2]), + .O(\reg_do[2]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFF6200)) + \reg_do[3]_i_1 + (.I0(sl_iport_i[4]), + .I1(sl_iport_i[5]), + .I2(reg_test[3]), + .I3(\reg_do[10]_i_2_n_0 ), + .I4(\reg_do[3]_i_2_n_0 ), + .O(reg_do[3])); + LUT6 #( + .INIT(64'h000000003333AA3A)) + \reg_do[3]_i_2 + (.I0(\reg_do[3]_i_3_n_0 ), + .I1(\reg_do[3]_i_4_n_0 ), + .I2(sl_iport_i[6]), + .I3(sl_iport_i[7]), + .I4(sl_iport_i[8]), + .I5(\reg_do[15]_i_4_n_0 ), + .O(\reg_do[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[3]_i_3 + (.I0(uuid_stamp[51]), + .I1(uuid_stamp[35]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[19]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[3]), + .O(\reg_do[3]_i_3_n_0 )); + LUT6 #( + .INIT(64'h05F5030305F5F3F3)) + \reg_do[3]_i_4 + (.I0(uuid_stamp[83]), + .I1(uuid_stamp[67]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[115]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[99]), + .O(\reg_do[3]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFF6200)) + \reg_do[4]_i_1 + (.I0(sl_iport_i[4]), + .I1(sl_iport_i[5]), + .I2(reg_test[4]), + .I3(\reg_do[10]_i_2_n_0 ), + .I4(\reg_do[4]_i_2_n_0 ), + .O(reg_do[4])); + LUT6 #( + .INIT(64'h00000000FFAE00A2)) + \reg_do[4]_i_2 + (.I0(\reg_do[4]_i_3_n_0 ), + .I1(sl_iport_i[6]), + .I2(sl_iport_i[7]), + .I3(sl_iport_i[8]), + .I4(\reg_do[4]_i_4_n_0 ), + .I5(\reg_do[15]_i_4_n_0 ), + .O(\reg_do[4]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[4]_i_3 + (.I0(uuid_stamp[52]), + .I1(uuid_stamp[36]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[20]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[4]), + .O(\reg_do[4]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[4]_i_4 + (.I0(uuid_stamp[116]), + .I1(uuid_stamp[100]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[84]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[68]), + .O(\reg_do[4]_i_4_n_0 )); + LUT6 #( + .INIT(64'h888888888A88A8A8)) + \reg_do[5]_i_1 + (.I0(\reg_do[5]_i_2_n_0 ), + .I1(\reg_do[9]_i_2_n_0 ), + .I2(\reg_do[9]_i_3_n_0 ), + .I3(reg_test[5]), + .I4(sl_iport_i[5]), + .I5(sl_iport_i[4]), + .O(reg_do[5])); + LUT6 #( + .INIT(64'hABABABAAAAAAABAA)) + \reg_do[5]_i_2 + (.I0(\reg_do[5]_i_3_n_0 ), + .I1(sl_iport_i[8]), + .I2(sl_iport_i[7]), + .I3(\reg_do[5]_i_4_n_0 ), + .I4(sl_iport_i[6]), + .I5(\reg_do[5]_i_5_n_0 ), + .O(\reg_do[5]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \reg_do[5]_i_3 + (.I0(sl_iport_i[10]), + .I1(sl_iport_i[11]), + .I2(sl_iport_i[9]), + .I3(sl_iport_i[8]), + .O(\reg_do[5]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[5]_i_4 + (.I0(uuid_stamp[53]), + .I1(uuid_stamp[37]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[21]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[5]), + .O(\reg_do[5]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[5]_i_5 + (.I0(uuid_stamp[117]), + .I1(uuid_stamp[101]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[85]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[69]), + .O(\reg_do[5]_i_5_n_0 )); + LUT5 #( + .INIT(32'hFFFF6200)) + \reg_do[6]_i_1 + (.I0(sl_iport_i[4]), + .I1(sl_iport_i[5]), + .I2(reg_test[6]), + .I3(\reg_do[10]_i_2_n_0 ), + .I4(\reg_do[6]_i_2_n_0 ), + .O(reg_do[6])); + LUT6 #( + .INIT(64'h00000000AAFBAA08)) + \reg_do[6]_i_2 + (.I0(\reg_do[6]_i_3_n_0 ), + .I1(sl_iport_i[6]), + .I2(sl_iport_i[7]), + .I3(sl_iport_i[8]), + .I4(\reg_do[6]_i_4_n_0 ), + .I5(\reg_do[15]_i_4_n_0 ), + .O(\reg_do[6]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[6]_i_3 + (.I0(uuid_stamp[118]), + .I1(uuid_stamp[102]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[86]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[70]), + .O(\reg_do[6]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[6]_i_4 + (.I0(uuid_stamp[54]), + .I1(uuid_stamp[38]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[22]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[6]), + .O(\reg_do[6]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFF6200)) + \reg_do[7]_i_1 + (.I0(sl_iport_i[4]), + .I1(sl_iport_i[5]), + .I2(reg_test[7]), + .I3(\reg_do[10]_i_2_n_0 ), + .I4(\reg_do[7]_i_2_n_0 ), + .O(reg_do[7])); + LUT6 #( + .INIT(64'h00000000AAFBAA08)) + \reg_do[7]_i_2 + (.I0(\reg_do[7]_i_3_n_0 ), + .I1(sl_iport_i[6]), + .I2(sl_iport_i[7]), + .I3(sl_iport_i[8]), + .I4(\reg_do[7]_i_4_n_0 ), + .I5(\reg_do[15]_i_4_n_0 ), + .O(\reg_do[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[7]_i_3 + (.I0(uuid_stamp[119]), + .I1(uuid_stamp[103]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[87]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[71]), + .O(\reg_do[7]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[7]_i_4 + (.I0(uuid_stamp[55]), + .I1(uuid_stamp[39]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[23]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[7]), + .O(\reg_do[7]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFF7500)) + \reg_do[8]_i_1 + (.I0(sl_iport_i[5]), + .I1(sl_iport_i[4]), + .I2(reg_test[8]), + .I3(\reg_do[10]_i_2_n_0 ), + .I4(\reg_do[8]_i_2_n_0 ), + .O(reg_do[8])); + LUT6 #( + .INIT(64'h00000000AAFBAA08)) + \reg_do[8]_i_2 + (.I0(\reg_do[8]_i_3_n_0 ), + .I1(sl_iport_i[6]), + .I2(sl_iport_i[7]), + .I3(sl_iport_i[8]), + .I4(\reg_do[8]_i_4_n_0 ), + .I5(\reg_do[15]_i_4_n_0 ), + .O(\reg_do[8]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[8]_i_3 + (.I0(uuid_stamp[120]), + .I1(uuid_stamp[104]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[88]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[72]), + .O(\reg_do[8]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[8]_i_4 + (.I0(uuid_stamp[56]), + .I1(uuid_stamp[40]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[24]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[8]), + .O(\reg_do[8]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF40144010)) + \reg_do[9]_i_1 + (.I0(\reg_do[9]_i_2_n_0 ), + .I1(sl_iport_i[5]), + .I2(sl_iport_i[4]), + .I3(\reg_do[9]_i_3_n_0 ), + .I4(reg_test[9]), + .I5(\reg_do[9]_i_4_n_0 ), + .O(reg_do[9])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hFF7FFFFF)) + \reg_do[9]_i_2 + (.I0(sl_iport_i[10]), + .I1(sl_iport_i[11]), + .I2(sl_iport_i[8]), + .I3(sl_iport_i[7]), + .I4(sl_iport_i[9]), + .O(\reg_do[9]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT3 #( + .INIT(8'h8A)) + \reg_do[9]_i_3 + (.I0(sl_iport_i[8]), + .I1(sl_iport_i[7]), + .I2(sl_iport_i[6]), + .O(\reg_do[9]_i_3_n_0 )); + LUT6 #( + .INIT(64'h00000000AAFBAA08)) + \reg_do[9]_i_4 + (.I0(\reg_do[9]_i_5_n_0 ), + .I1(sl_iport_i[6]), + .I2(sl_iport_i[7]), + .I3(sl_iport_i[8]), + .I4(\reg_do[9]_i_6_n_0 ), + .I5(\reg_do[15]_i_4_n_0 ), + .O(\reg_do[9]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[9]_i_5 + (.I0(uuid_stamp[121]), + .I1(uuid_stamp[105]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[89]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[73]), + .O(\reg_do[9]_i_5_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \reg_do[9]_i_6 + (.I0(uuid_stamp[57]), + .I1(uuid_stamp[41]), + .I2(sl_iport_i[5]), + .I3(uuid_stamp[25]), + .I4(sl_iport_i[4]), + .I5(uuid_stamp[9]), + .O(\reg_do[9]_i_6_n_0 )); + FDRE #( + .INIT(1'b0)) + \reg_do_reg[0] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(reg_do[0]), + .Q(\reg_do_reg_n_0_[0] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_do_reg[10] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(reg_do[10]), + .Q(\reg_do_reg_n_0_[10] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_do_reg[11] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(reg_do[11]), + .Q(\reg_do_reg_n_0_[11] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_do_reg[12] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(reg_do[12]), + .Q(\reg_do_reg_n_0_[12] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_do_reg[13] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(reg_do[13]), + .Q(\reg_do_reg_n_0_[13] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_do_reg[14] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(reg_do[14]), + .Q(\reg_do_reg_n_0_[14] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_do_reg[15] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(reg_do[15]), + .Q(\reg_do_reg_n_0_[15] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_do_reg[1] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(reg_do[1]), + .Q(\reg_do_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_do_reg[2] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(reg_do[2]), + .Q(\reg_do_reg_n_0_[2] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_do_reg[3] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(reg_do[3]), + .Q(\reg_do_reg_n_0_[3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_do_reg[4] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(reg_do[4]), + .Q(\reg_do_reg_n_0_[4] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_do_reg[5] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(reg_do[5]), + .Q(\reg_do_reg_n_0_[5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_do_reg[6] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(reg_do[6]), + .Q(\reg_do_reg_n_0_[6] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_do_reg[7] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(reg_do[7]), + .Q(\reg_do_reg_n_0_[7] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_do_reg[8] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(reg_do[8]), + .Q(\reg_do_reg_n_0_[8] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_do_reg[9] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(reg_do[9]), + .Q(\reg_do_reg_n_0_[9] ), + .R(1'b0)); + LUT6 #( + .INIT(64'h0000800000000000)) + reg_drdy_i_1 + (.I0(s_den_o_INST_0_i_1_n_0), + .I1(sl_iport_i[12]), + .I2(sl_iport_i[13]), + .I3(sl_iport_i[14]), + .I4(sl_iport_i[0]), + .I5(sl_iport_i[2]), + .O(reg_drdy_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + reg_drdy_reg + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(reg_drdy_i_1_n_0), + .Q(reg_drdy), + .R(1'b0)); + LUT6 #( + .INIT(64'h8000000000000000)) + \reg_test[15]_i_1 + (.I0(s_den_o_INST_0_i_1_n_0), + .I1(sl_iport_i[12]), + .I2(sl_iport_i[13]), + .I3(sl_iport_i[14]), + .I4(sl_iport_i[3]), + .I5(sl_iport_i[2]), + .O(reg_test0)); + FDRE #( + .INIT(1'b0)) + \reg_test_reg[0] + (.C(sl_iport_i[1]), + .CE(reg_test0), + .D(sl_iport_i[21]), + .Q(reg_test[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_test_reg[10] + (.C(sl_iport_i[1]), + .CE(reg_test0), + .D(sl_iport_i[31]), + .Q(reg_test[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_test_reg[11] + (.C(sl_iport_i[1]), + .CE(reg_test0), + .D(sl_iport_i[32]), + .Q(reg_test[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_test_reg[12] + (.C(sl_iport_i[1]), + .CE(reg_test0), + .D(sl_iport_i[33]), + .Q(reg_test[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_test_reg[13] + (.C(sl_iport_i[1]), + .CE(reg_test0), + .D(sl_iport_i[34]), + .Q(reg_test[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_test_reg[14] + (.C(sl_iport_i[1]), + .CE(reg_test0), + .D(sl_iport_i[35]), + .Q(reg_test[14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_test_reg[15] + (.C(sl_iport_i[1]), + .CE(reg_test0), + .D(sl_iport_i[36]), + .Q(reg_test[15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_test_reg[1] + (.C(sl_iport_i[1]), + .CE(reg_test0), + .D(sl_iport_i[22]), + .Q(reg_test[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_test_reg[2] + (.C(sl_iport_i[1]), + .CE(reg_test0), + .D(sl_iport_i[23]), + .Q(reg_test[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_test_reg[3] + (.C(sl_iport_i[1]), + .CE(reg_test0), + .D(sl_iport_i[24]), + .Q(reg_test[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_test_reg[4] + (.C(sl_iport_i[1]), + .CE(reg_test0), + .D(sl_iport_i[25]), + .Q(reg_test[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_test_reg[5] + (.C(sl_iport_i[1]), + .CE(reg_test0), + .D(sl_iport_i[26]), + .Q(reg_test[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_test_reg[6] + (.C(sl_iport_i[1]), + .CE(reg_test0), + .D(sl_iport_i[27]), + .Q(reg_test[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_test_reg[7] + (.C(sl_iport_i[1]), + .CE(reg_test0), + .D(sl_iport_i[28]), + .Q(reg_test[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_test_reg[8] + (.C(sl_iport_i[1]), + .CE(reg_test0), + .D(sl_iport_i[29]), + .Q(reg_test[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \reg_test_reg[9] + (.C(sl_iport_i[1]), + .CE(reg_test0), + .D(sl_iport_i[30]), + .Q(reg_test[9]), + .R(1'b0)); + LUT5 #( + .INIT(32'h7FFF0000)) + s_den_o_INST_0 + (.I0(s_den_o_INST_0_i_1_n_0), + .I1(sl_iport_i[12]), + .I2(sl_iport_i[13]), + .I3(sl_iport_i[14]), + .I4(sl_iport_i[2]), + .O(s_den_o)); + LUT6 #( + .INIT(64'h8000000000000000)) + s_den_o_INST_0_i_1 + (.I0(sl_iport_i[15]), + .I1(sl_iport_i[16]), + .I2(sl_iport_i[17]), + .I3(sl_iport_i[18]), + .I4(sl_iport_i[20]), + .I5(sl_iport_i[19]), + .O(s_den_o_INST_0_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'hE)) + \sl_oport_o[0]_INST_0 + (.I0(reg_drdy), + .I1(s_drdy_i), + .O(sl_oport_o[0])); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT3 #( + .INIT(8'hB8)) + \sl_oport_o[10]_INST_0 + (.I0(\reg_do_reg_n_0_[9] ), + .I1(reg_drdy), + .I2(s_do_i[9]), + .O(sl_oport_o[10])); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT3 #( + .INIT(8'hB8)) + \sl_oport_o[11]_INST_0 + (.I0(\reg_do_reg_n_0_[10] ), + .I1(reg_drdy), + .I2(s_do_i[10]), + .O(sl_oport_o[11])); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT3 #( + .INIT(8'hB8)) + \sl_oport_o[12]_INST_0 + (.I0(\reg_do_reg_n_0_[11] ), + .I1(reg_drdy), + .I2(s_do_i[11]), + .O(sl_oport_o[12])); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT3 #( + .INIT(8'hB8)) + \sl_oport_o[13]_INST_0 + (.I0(\reg_do_reg_n_0_[12] ), + .I1(reg_drdy), + .I2(s_do_i[12]), + .O(sl_oport_o[13])); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'hB8)) + \sl_oport_o[14]_INST_0 + (.I0(\reg_do_reg_n_0_[13] ), + .I1(reg_drdy), + .I2(s_do_i[13]), + .O(sl_oport_o[14])); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'hB8)) + \sl_oport_o[15]_INST_0 + (.I0(\reg_do_reg_n_0_[14] ), + .I1(reg_drdy), + .I2(s_do_i[14]), + .O(sl_oport_o[15])); + LUT3 #( + .INIT(8'hB8)) + \sl_oport_o[16]_INST_0 + (.I0(\reg_do_reg_n_0_[15] ), + .I1(reg_drdy), + .I2(s_do_i[15]), + .O(sl_oport_o[16])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'hB8)) + \sl_oport_o[1]_INST_0 + (.I0(\reg_do_reg_n_0_[0] ), + .I1(reg_drdy), + .I2(s_do_i[0]), + .O(sl_oport_o[1])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT3 #( + .INIT(8'hB8)) + \sl_oport_o[2]_INST_0 + (.I0(\reg_do_reg_n_0_[1] ), + .I1(reg_drdy), + .I2(s_do_i[1]), + .O(sl_oport_o[2])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT3 #( + .INIT(8'hB8)) + \sl_oport_o[3]_INST_0 + (.I0(\reg_do_reg_n_0_[2] ), + .I1(reg_drdy), + .I2(s_do_i[2]), + .O(sl_oport_o[3])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'hB8)) + \sl_oport_o[4]_INST_0 + (.I0(\reg_do_reg_n_0_[3] ), + .I1(reg_drdy), + .I2(s_do_i[3]), + .O(sl_oport_o[4])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT3 #( + .INIT(8'hB8)) + \sl_oport_o[5]_INST_0 + (.I0(\reg_do_reg_n_0_[4] ), + .I1(reg_drdy), + .I2(s_do_i[4]), + .O(sl_oport_o[5])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'hB8)) + \sl_oport_o[6]_INST_0 + (.I0(\reg_do_reg_n_0_[5] ), + .I1(reg_drdy), + .I2(s_do_i[5]), + .O(sl_oport_o[6])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'hB8)) + \sl_oport_o[7]_INST_0 + (.I0(\reg_do_reg_n_0_[6] ), + .I1(reg_drdy), + .I2(s_do_i[6]), + .O(sl_oport_o[7])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'hB8)) + \sl_oport_o[8]_INST_0 + (.I0(\reg_do_reg_n_0_[7] ), + .I1(reg_drdy), + .I2(s_do_i[7]), + .O(sl_oport_o[8])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'hB8)) + \sl_oport_o[9]_INST_0 + (.I0(\reg_do_reg_n_0_[8] ), + .I1(reg_drdy), + .I2(s_do_i[8]), + .O(sl_oport_o[9])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[0] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[0]), + .Q(uuid_stamp[0]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[100] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[100]), + .Q(uuid_stamp[100]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[101] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[101]), + .Q(uuid_stamp[101]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[102] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[102]), + .Q(uuid_stamp[102]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[103] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[103]), + .Q(uuid_stamp[103]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[104] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[104]), + .Q(uuid_stamp[104]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[105] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[105]), + .Q(uuid_stamp[105]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[106] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[106]), + .Q(uuid_stamp[106]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[107] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[107]), + .Q(uuid_stamp[107]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[108] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[108]), + .Q(uuid_stamp[108]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[109] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[109]), + .Q(uuid_stamp[109]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[10] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[10]), + .Q(uuid_stamp[10]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[110] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[110]), + .Q(uuid_stamp[110]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[111] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[111]), + .Q(uuid_stamp[111]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[112] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[112]), + .Q(uuid_stamp[112]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[113] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[113]), + .Q(uuid_stamp[113]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[114] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[114]), + .Q(uuid_stamp[114]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[115] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[115]), + .Q(uuid_stamp[115]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[116] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[116]), + .Q(uuid_stamp[116]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[117] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[117]), + .Q(uuid_stamp[117]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[118] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[118]), + .Q(uuid_stamp[118]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[119] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[119]), + .Q(uuid_stamp[119]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[11] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[11]), + .Q(uuid_stamp[11]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[120] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[120]), + .Q(uuid_stamp[120]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[121] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[121]), + .Q(uuid_stamp[121]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[122] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[122]), + .Q(uuid_stamp[122]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[123] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[123]), + .Q(uuid_stamp[123]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[124] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[124]), + .Q(uuid_stamp[124]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[125] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[125]), + .Q(uuid_stamp[125]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[126] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[126]), + .Q(uuid_stamp[126]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[127] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[127]), + .Q(uuid_stamp[127]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[12] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[12]), + .Q(uuid_stamp[12]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[13] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[13]), + .Q(uuid_stamp[13]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[14] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[14]), + .Q(uuid_stamp[14]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[15] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[15]), + .Q(uuid_stamp[15]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[16] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[16]), + .Q(uuid_stamp[16]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[17] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[17]), + .Q(uuid_stamp[17]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[18] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[18]), + .Q(uuid_stamp[18]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[19] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[19]), + .Q(uuid_stamp[19]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[1] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[1]), + .Q(uuid_stamp[1]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[20] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[20]), + .Q(uuid_stamp[20]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[21] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[21]), + .Q(uuid_stamp[21]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[22] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[22]), + .Q(uuid_stamp[22]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[23] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[23]), + .Q(uuid_stamp[23]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[24] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[24]), + .Q(uuid_stamp[24]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[25] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[25]), + .Q(uuid_stamp[25]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[26] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[26]), + .Q(uuid_stamp[26]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[27] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[27]), + .Q(uuid_stamp[27]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[28] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[28]), + .Q(uuid_stamp[28]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[29] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[29]), + .Q(uuid_stamp[29]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[2] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[2]), + .Q(uuid_stamp[2]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[30] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[30]), + .Q(uuid_stamp[30]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[31] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[31]), + .Q(uuid_stamp[31]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[32] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[32]), + .Q(uuid_stamp[32]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[33] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[33]), + .Q(uuid_stamp[33]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[34] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[34]), + .Q(uuid_stamp[34]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[35] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[35]), + .Q(uuid_stamp[35]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[36] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[36]), + .Q(uuid_stamp[36]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[37] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[37]), + .Q(uuid_stamp[37]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[38] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[38]), + .Q(uuid_stamp[38]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[39] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[39]), + .Q(uuid_stamp[39]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[3] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[3]), + .Q(uuid_stamp[3]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[40] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[40]), + .Q(uuid_stamp[40]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[41] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[41]), + .Q(uuid_stamp[41]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[42] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[42]), + .Q(uuid_stamp[42]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[43] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[43]), + .Q(uuid_stamp[43]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[44] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[44]), + .Q(uuid_stamp[44]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[45] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[45]), + .Q(uuid_stamp[45]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[46] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[46]), + .Q(uuid_stamp[46]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[47] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[47]), + .Q(uuid_stamp[47]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[48] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[48]), + .Q(uuid_stamp[48]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[49] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[49]), + .Q(uuid_stamp[49]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[4] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[4]), + .Q(uuid_stamp[4]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[50] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[50]), + .Q(uuid_stamp[50]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[51] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[51]), + .Q(uuid_stamp[51]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[52] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[52]), + .Q(uuid_stamp[52]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[53] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[53]), + .Q(uuid_stamp[53]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[54] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[54]), + .Q(uuid_stamp[54]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[55] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[55]), + .Q(uuid_stamp[55]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[56] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[56]), + .Q(uuid_stamp[56]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[57] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[57]), + .Q(uuid_stamp[57]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[58] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[58]), + .Q(uuid_stamp[58]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[59] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[59]), + .Q(uuid_stamp[59]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[5] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[5]), + .Q(uuid_stamp[5]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[60] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[60]), + .Q(uuid_stamp[60]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[61] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[61]), + .Q(uuid_stamp[61]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[62] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[62]), + .Q(uuid_stamp[62]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[63] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[63]), + .Q(uuid_stamp[63]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[64] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[64]), + .Q(uuid_stamp[64]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[65] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[65]), + .Q(uuid_stamp[65]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[66] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[66]), + .Q(uuid_stamp[66]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[67] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[67]), + .Q(uuid_stamp[67]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[68] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[68]), + .Q(uuid_stamp[68]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[69] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[69]), + .Q(uuid_stamp[69]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[6] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[6]), + .Q(uuid_stamp[6]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[70] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[70]), + .Q(uuid_stamp[70]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[71] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[71]), + .Q(uuid_stamp[71]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[72] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[72]), + .Q(uuid_stamp[72]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[73] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[73]), + .Q(uuid_stamp[73]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[74] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[74]), + .Q(uuid_stamp[74]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[75] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[75]), + .Q(uuid_stamp[75]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[76] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[76]), + .Q(uuid_stamp[76]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[77] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[77]), + .Q(uuid_stamp[77]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[78] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[78]), + .Q(uuid_stamp[78]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[79] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[79]), + .Q(uuid_stamp[79]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[7] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[7]), + .Q(uuid_stamp[7]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[80] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[80]), + .Q(uuid_stamp[80]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[81] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[81]), + .Q(uuid_stamp[81]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[82] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[82]), + .Q(uuid_stamp[82]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[83] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[83]), + .Q(uuid_stamp[83]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[84] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[84]), + .Q(uuid_stamp[84]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[85] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[85]), + .Q(uuid_stamp[85]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[86] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[86]), + .Q(uuid_stamp[86]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[87] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[87]), + .Q(uuid_stamp[87]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[88] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[88]), + .Q(uuid_stamp[88]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[89] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[89]), + .Q(uuid_stamp[89]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[8] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[8]), + .Q(uuid_stamp[8]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[90] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[90]), + .Q(uuid_stamp[90]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[91] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[91]), + .Q(uuid_stamp[91]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[92] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[92]), + .Q(uuid_stamp[92]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[93] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[93]), + .Q(uuid_stamp[93]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[94] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[94]), + .Q(uuid_stamp[94]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[95] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[95]), + .Q(uuid_stamp[95]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[96] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[96]), + .Q(uuid_stamp[96]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[97] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[97]), + .Q(uuid_stamp[97]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[98] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[98]), + .Q(uuid_stamp[98]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[99] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[99]), + .Q(uuid_stamp[99]), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* UUID = "1" *) + FDRE \uuid_stamp_reg[9] + (.C(sl_iport_i[1]), + .CE(1'b1), + .D(uuid_stamp[9]), + .Q(uuid_stamp[9]), + .R(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5d522090233ffcd/vio_manual_ctrl_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5d522090233ffcd/vio_manual_ctrl_sim_netlist.vhdl new file mode 100644 index 00000000..dddc1de1 --- /dev/null +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5d522090233ffcd/vio_manual_ctrl_sim_netlist.vhdl @@ -0,0 +1,13203 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Tue Mar 21 22:54:42 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_sim_netlist.vhdl +-- Design : vio_manual_ctrl +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_decoder is + port ( + s_drdy_i : out STD_LOGIC; + rd_probe_out_width : out STD_LOGIC; + in0 : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + internal_cnt_rst : out STD_LOGIC; + \G_PROBE_OUT[0].wr_probe_out[0]_i_4_0\ : out STD_LOGIC; + s_den_o_INST_0 : out STD_LOGIC; + \G_PROBE_OUT[0].wr_probe_out[0]_i_3_0\ : out STD_LOGIC; + \Bus_data_out_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + s_rst_o : in STD_LOGIC; + \out\ : in STD_LOGIC; + s_daddr_o : in STD_LOGIC_VECTOR ( 16 downto 0 ); + \rd_en_reg[6]_0\ : in STD_LOGIC; + s_dwe_o : in STD_LOGIC; + s_den_o : in STD_LOGIC; + \Bus_data_out_reg[9]_0\ : in STD_LOGIC; + \Bus_data_out_reg[10]_0\ : in STD_LOGIC; + \Bus_data_out_reg[11]_0\ : in STD_LOGIC; + \Bus_data_out_reg[12]_0\ : in STD_LOGIC; + \Bus_data_out_reg[13]_0\ : in STD_LOGIC; + \Bus_data_out_reg[14]_0\ : in STD_LOGIC; + \Bus_data_out_reg[15]_1\ : in STD_LOGIC; + \Bus_data_out_reg[8]_0\ : in STD_LOGIC; + \Bus_data_out_reg[4]_0\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \Bus_data_out_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \Bus_data_out_reg[5]_0\ : in STD_LOGIC; + \Bus_data_out_reg[6]_0\ : in STD_LOGIC; + \Bus_data_out_reg[7]_0\ : in STD_LOGIC; + \probe_out_modified_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \xsdb_addr_2_0_p2_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ) + ); +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_decoder; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_decoder is + signal \Bus_data_out[0]_i_1_n_0\ : STD_LOGIC; + signal \Bus_data_out[0]_i_2_n_0\ : STD_LOGIC; + signal \Bus_data_out[10]_i_1_n_0\ : STD_LOGIC; + signal \Bus_data_out[11]_i_1_n_0\ : STD_LOGIC; + signal \Bus_data_out[12]_i_1_n_0\ : STD_LOGIC; + signal \Bus_data_out[13]_i_1_n_0\ : STD_LOGIC; + signal \Bus_data_out[14]_i_1_n_0\ : STD_LOGIC; + signal \Bus_data_out[15]_i_1_n_0\ : STD_LOGIC; + signal \Bus_data_out[1]_i_1_n_0\ : STD_LOGIC; + signal \Bus_data_out[1]_i_2_n_0\ : STD_LOGIC; + signal \Bus_data_out[2]_i_1_n_0\ : STD_LOGIC; + signal \Bus_data_out[2]_i_2_n_0\ : STD_LOGIC; + signal \Bus_data_out[3]_i_1_n_0\ : STD_LOGIC; + signal \Bus_data_out[4]_i_1_n_0\ : STD_LOGIC; + signal \Bus_data_out[5]_i_1_n_0\ : STD_LOGIC; + signal \Bus_data_out[6]_i_1_n_0\ : STD_LOGIC; + signal \Bus_data_out[7]_i_1_n_0\ : STD_LOGIC; + signal \Bus_data_out[8]_i_1_n_0\ : STD_LOGIC; + signal \Bus_data_out[8]_i_2_n_0\ : STD_LOGIC; + signal \Bus_data_out[8]_i_3_n_0\ : STD_LOGIC; + signal \Bus_data_out[9]_i_1_n_0\ : STD_LOGIC; + signal \^g_probe_out[0].wr_probe_out[0]_i_3_0\ : STD_LOGIC; + signal \^g_probe_out[0].wr_probe_out[0]_i_4_0\ : STD_LOGIC; + signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal clear_int_i_1_n_0 : STD_LOGIC; + signal committ_int_i_1_n_0 : STD_LOGIC; + signal \^in0\ : STD_LOGIC; + signal int_cnt_rst_i_1_n_0 : STD_LOGIC; + signal \^internal_cnt_rst\ : STD_LOGIC; + signal probe_out_modified : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \rd_en[6]_i_1_n_0\ : STD_LOGIC; + signal \rd_en[6]_i_2_n_0\ : STD_LOGIC; + signal rd_en_p1 : STD_LOGIC; + signal rd_en_p2 : STD_LOGIC; + signal \^s_den_o_inst_0\ : STD_LOGIC; + signal wr_control_reg : STD_LOGIC; + signal \wr_en[2]_i_1_n_0\ : STD_LOGIC; + signal \wr_en[2]_i_2_n_0\ : STD_LOGIC; + signal \wr_en[2]_i_3_n_0\ : STD_LOGIC; + signal \wr_en[4]_i_1_n_0\ : STD_LOGIC; + signal \wr_en[4]_i_2_n_0\ : STD_LOGIC; + signal wr_probe_out_modified : STD_LOGIC; + signal xsdb_addr_2_0_p2 : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal xsdb_addr_8_p1 : STD_LOGIC; + signal xsdb_addr_8_p2 : STD_LOGIC; + signal xsdb_drdy_i_1_n_0 : STD_LOGIC; + signal xsdb_rd : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \Bus_data_out[8]_i_2\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \Bus_data_out[8]_i_3\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \G_PROBE_OUT[0].wr_probe_out[0]_i_5\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of committ_int_i_1 : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of int_cnt_rst_i_1 : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of rd_en_p1_i_1 : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of \wr_en[2]_i_2\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of xsdb_drdy_i_1 : label is "soft_lutpair12"; +begin + \G_PROBE_OUT[0].wr_probe_out[0]_i_3_0\ <= \^g_probe_out[0].wr_probe_out[0]_i_3_0\; + \G_PROBE_OUT[0].wr_probe_out[0]_i_4_0\ <= \^g_probe_out[0].wr_probe_out[0]_i_4_0\; + SR(0) <= \^sr\(0); + in0 <= \^in0\; + internal_cnt_rst <= \^internal_cnt_rst\; + s_den_o_INST_0 <= \^s_den_o_inst_0\; +\Bus_data_out[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF444E0000444E" + ) + port map ( + I0 => xsdb_addr_2_0_p2(0), + I1 => \Bus_data_out[0]_i_2_n_0\, + I2 => xsdb_addr_2_0_p2(2), + I3 => xsdb_addr_2_0_p2(1), + I4 => xsdb_addr_8_p2, + I5 => Q(0), + O => \Bus_data_out[0]_i_1_n_0\ + ); +\Bus_data_out[0]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FCA00CA0" + ) + port map ( + I0 => \^in0\, + I1 => probe_out_modified(0), + I2 => xsdb_addr_2_0_p2(1), + I3 => xsdb_addr_2_0_p2(2), + I4 => \Bus_data_out_reg[3]_0\(0), + O => \Bus_data_out[0]_i_2_n_0\ + ); +\Bus_data_out[10]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAA000CAAAA0000" + ) + port map ( + I0 => \Bus_data_out_reg[10]_0\, + I1 => probe_out_modified(10), + I2 => xsdb_addr_2_0_p2(1), + I3 => xsdb_addr_2_0_p2(0), + I4 => xsdb_addr_8_p2, + I5 => xsdb_addr_2_0_p2(2), + O => \Bus_data_out[10]_i_1_n_0\ + ); +\Bus_data_out[11]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAA000CAAAA0000" + ) + port map ( + I0 => \Bus_data_out_reg[11]_0\, + I1 => probe_out_modified(11), + I2 => xsdb_addr_2_0_p2(1), + I3 => xsdb_addr_2_0_p2(0), + I4 => xsdb_addr_8_p2, + I5 => xsdb_addr_2_0_p2(2), + O => \Bus_data_out[11]_i_1_n_0\ + ); +\Bus_data_out[12]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAA000CAAAA0000" + ) + port map ( + I0 => \Bus_data_out_reg[12]_0\, + I1 => probe_out_modified(12), + I2 => xsdb_addr_2_0_p2(1), + I3 => xsdb_addr_2_0_p2(0), + I4 => xsdb_addr_8_p2, + I5 => xsdb_addr_2_0_p2(2), + O => \Bus_data_out[12]_i_1_n_0\ + ); +\Bus_data_out[13]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAA000CAAAA0000" + ) + port map ( + I0 => \Bus_data_out_reg[13]_0\, + I1 => probe_out_modified(13), + I2 => xsdb_addr_2_0_p2(1), + I3 => xsdb_addr_2_0_p2(0), + I4 => xsdb_addr_8_p2, + I5 => xsdb_addr_2_0_p2(2), + O => \Bus_data_out[13]_i_1_n_0\ + ); +\Bus_data_out[14]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAA000CAAAA0000" + ) + port map ( + I0 => \Bus_data_out_reg[14]_0\, + I1 => probe_out_modified(14), + I2 => xsdb_addr_2_0_p2(1), + I3 => xsdb_addr_2_0_p2(0), + I4 => xsdb_addr_8_p2, + I5 => xsdb_addr_2_0_p2(2), + O => \Bus_data_out[14]_i_1_n_0\ + ); +\Bus_data_out[15]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAA000CAAAA0000" + ) + port map ( + I0 => \Bus_data_out_reg[15]_1\, + I1 => probe_out_modified(15), + I2 => xsdb_addr_2_0_p2(1), + I3 => xsdb_addr_2_0_p2(0), + I4 => xsdb_addr_8_p2, + I5 => xsdb_addr_2_0_p2(2), + O => \Bus_data_out[15]_i_1_n_0\ + ); +\Bus_data_out[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A0AC" + ) + port map ( + I0 => Q(1), + I1 => \Bus_data_out[1]_i_2_n_0\, + I2 => xsdb_addr_8_p2, + I3 => xsdb_addr_2_0_p2(0), + O => \Bus_data_out[1]_i_1_n_0\ + ); +\Bus_data_out[1]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FCA00CA0" + ) + port map ( + I0 => \^sr\(0), + I1 => probe_out_modified(1), + I2 => xsdb_addr_2_0_p2(1), + I3 => xsdb_addr_2_0_p2(2), + I4 => \Bus_data_out_reg[3]_0\(1), + O => \Bus_data_out[1]_i_2_n_0\ + ); +\Bus_data_out[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF444E0000444E" + ) + port map ( + I0 => xsdb_addr_2_0_p2(0), + I1 => \Bus_data_out[2]_i_2_n_0\, + I2 => xsdb_addr_2_0_p2(2), + I3 => xsdb_addr_2_0_p2(1), + I4 => xsdb_addr_8_p2, + I5 => Q(2), + O => \Bus_data_out[2]_i_1_n_0\ + ); +\Bus_data_out[2]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FA0AC0C0" + ) + port map ( + I0 => \^internal_cnt_rst\, + I1 => probe_out_modified(2), + I2 => xsdb_addr_2_0_p2(2), + I3 => \Bus_data_out_reg[3]_0\(2), + I4 => xsdb_addr_2_0_p2(1), + O => \Bus_data_out[2]_i_2_n_0\ + ); +\Bus_data_out[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFF8F8F8" + ) + port map ( + I0 => \Bus_data_out[8]_i_2_n_0\, + I1 => probe_out_modified(3), + I2 => \Bus_data_out[8]_i_3_n_0\, + I3 => xsdb_addr_8_p2, + I4 => Q(3), + O => \Bus_data_out[3]_i_1_n_0\ + ); +\Bus_data_out[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFF8F8F8" + ) + port map ( + I0 => \Bus_data_out[8]_i_2_n_0\, + I1 => probe_out_modified(4), + I2 => \Bus_data_out[8]_i_3_n_0\, + I3 => xsdb_addr_8_p2, + I4 => \Bus_data_out_reg[4]_0\, + O => \Bus_data_out[4]_i_1_n_0\ + ); +\Bus_data_out[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A0A0A0A0A0A0ACA0" + ) + port map ( + I0 => \Bus_data_out_reg[5]_0\, + I1 => probe_out_modified(5), + I2 => xsdb_addr_8_p2, + I3 => xsdb_addr_2_0_p2(2), + I4 => xsdb_addr_2_0_p2(0), + I5 => xsdb_addr_2_0_p2(1), + O => \Bus_data_out[5]_i_1_n_0\ + ); +\Bus_data_out[6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A0A0A0A0A0A0ACA0" + ) + port map ( + I0 => \Bus_data_out_reg[6]_0\, + I1 => probe_out_modified(6), + I2 => xsdb_addr_8_p2, + I3 => xsdb_addr_2_0_p2(2), + I4 => xsdb_addr_2_0_p2(0), + I5 => xsdb_addr_2_0_p2(1), + O => \Bus_data_out[6]_i_1_n_0\ + ); +\Bus_data_out[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A0A0A0A0A0A0ACA0" + ) + port map ( + I0 => \Bus_data_out_reg[7]_0\, + I1 => probe_out_modified(7), + I2 => xsdb_addr_8_p2, + I3 => xsdb_addr_2_0_p2(2), + I4 => xsdb_addr_2_0_p2(0), + I5 => xsdb_addr_2_0_p2(1), + O => \Bus_data_out[7]_i_1_n_0\ + ); +\Bus_data_out[8]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFF8F8F8" + ) + port map ( + I0 => \Bus_data_out[8]_i_2_n_0\, + I1 => probe_out_modified(8), + I2 => \Bus_data_out[8]_i_3_n_0\, + I3 => xsdb_addr_8_p2, + I4 => \Bus_data_out_reg[8]_0\, + O => \Bus_data_out[8]_i_1_n_0\ + ); +\Bus_data_out[8]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0004" + ) + port map ( + I0 => xsdb_addr_8_p2, + I1 => xsdb_addr_2_0_p2(2), + I2 => xsdb_addr_2_0_p2(0), + I3 => xsdb_addr_2_0_p2(1), + O => \Bus_data_out[8]_i_2_n_0\ + ); +\Bus_data_out[8]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000800" + ) + port map ( + I0 => xsdb_addr_2_0_p2(1), + I1 => \Bus_data_out_reg[3]_0\(2), + I2 => xsdb_addr_8_p2, + I3 => xsdb_addr_2_0_p2(2), + I4 => xsdb_addr_2_0_p2(0), + O => \Bus_data_out[8]_i_3_n_0\ + ); +\Bus_data_out[9]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAA000CAAAA0000" + ) + port map ( + I0 => \Bus_data_out_reg[9]_0\, + I1 => probe_out_modified(9), + I2 => xsdb_addr_2_0_p2(1), + I3 => xsdb_addr_2_0_p2(0), + I4 => xsdb_addr_8_p2, + I5 => xsdb_addr_2_0_p2(2), + O => \Bus_data_out[9]_i_1_n_0\ + ); +\Bus_data_out_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_data_out[0]_i_1_n_0\, + Q => \Bus_data_out_reg[15]_0\(0), + R => '0' + ); +\Bus_data_out_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_data_out[10]_i_1_n_0\, + Q => \Bus_data_out_reg[15]_0\(10), + R => '0' + ); +\Bus_data_out_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_data_out[11]_i_1_n_0\, + Q => \Bus_data_out_reg[15]_0\(11), + R => '0' + ); +\Bus_data_out_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_data_out[12]_i_1_n_0\, + Q => \Bus_data_out_reg[15]_0\(12), + R => '0' + ); +\Bus_data_out_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_data_out[13]_i_1_n_0\, + Q => \Bus_data_out_reg[15]_0\(13), + R => '0' + ); +\Bus_data_out_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_data_out[14]_i_1_n_0\, + Q => \Bus_data_out_reg[15]_0\(14), + R => '0' + ); +\Bus_data_out_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_data_out[15]_i_1_n_0\, + Q => \Bus_data_out_reg[15]_0\(15), + R => '0' + ); +\Bus_data_out_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_data_out[1]_i_1_n_0\, + Q => \Bus_data_out_reg[15]_0\(1), + R => '0' + ); +\Bus_data_out_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_data_out[2]_i_1_n_0\, + Q => \Bus_data_out_reg[15]_0\(2), + R => '0' + ); +\Bus_data_out_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_data_out[3]_i_1_n_0\, + Q => \Bus_data_out_reg[15]_0\(3), + R => '0' + ); +\Bus_data_out_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_data_out[4]_i_1_n_0\, + Q => \Bus_data_out_reg[15]_0\(4), + R => '0' + ); +\Bus_data_out_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_data_out[5]_i_1_n_0\, + Q => \Bus_data_out_reg[15]_0\(5), + R => '0' + ); +\Bus_data_out_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_data_out[6]_i_1_n_0\, + Q => \Bus_data_out_reg[15]_0\(6), + R => '0' + ); +\Bus_data_out_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_data_out[7]_i_1_n_0\, + Q => \Bus_data_out_reg[15]_0\(7), + R => '0' + ); +\Bus_data_out_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_data_out[8]_i_1_n_0\, + Q => \Bus_data_out_reg[15]_0\(8), + R => '0' + ); +\Bus_data_out_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_data_out[9]_i_1_n_0\, + Q => \Bus_data_out_reg[15]_0\(9), + R => '0' + ); +\G_PROBE_OUT[0].wr_probe_out[0]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => s_daddr_o(12), + I1 => s_daddr_o(13), + I2 => s_daddr_o(14), + I3 => s_daddr_o(15), + O => \^g_probe_out[0].wr_probe_out[0]_i_3_0\ + ); +\G_PROBE_OUT[0].wr_probe_out[0]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => s_daddr_o(4), + I1 => s_daddr_o(5), + I2 => s_daddr_o(6), + I3 => s_daddr_o(7), + O => \^g_probe_out[0].wr_probe_out[0]_i_4_0\ + ); +\G_PROBE_OUT[0].wr_probe_out[0]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0040" + ) + port map ( + I0 => s_daddr_o(16), + I1 => s_den_o, + I2 => s_dwe_o, + I3 => s_daddr_o(1), + O => \^s_den_o_inst_0\ + ); +clear_int_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \probe_out_modified_reg[15]_0\(1), + I1 => wr_control_reg, + I2 => \^sr\(0), + O => clear_int_i_1_n_0 + ); +clear_int_reg: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => clear_int_i_1_n_0, + Q => \^sr\(0), + R => s_rst_o + ); +committ_int_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \probe_out_modified_reg[15]_0\(0), + I1 => wr_control_reg, + I2 => \^in0\, + O => committ_int_i_1_n_0 + ); +committ_int_reg: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => committ_int_i_1_n_0, + Q => \^in0\, + R => s_rst_o + ); +int_cnt_rst_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \probe_out_modified_reg[15]_0\(2), + I1 => wr_control_reg, + I2 => \^internal_cnt_rst\, + O => int_cnt_rst_i_1_n_0 + ); +int_cnt_rst_reg: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => int_cnt_rst_i_1_n_0, + Q => \^internal_cnt_rst\, + R => s_rst_o + ); +\probe_out_modified_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => wr_probe_out_modified, + D => \probe_out_modified_reg[15]_0\(0), + Q => probe_out_modified(0), + R => \^sr\(0) + ); +\probe_out_modified_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => wr_probe_out_modified, + D => \probe_out_modified_reg[15]_0\(10), + Q => probe_out_modified(10), + R => \^sr\(0) + ); +\probe_out_modified_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => wr_probe_out_modified, + D => \probe_out_modified_reg[15]_0\(11), + Q => probe_out_modified(11), + R => \^sr\(0) + ); +\probe_out_modified_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => wr_probe_out_modified, + D => \probe_out_modified_reg[15]_0\(12), + Q => probe_out_modified(12), + R => \^sr\(0) + ); +\probe_out_modified_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => wr_probe_out_modified, + D => \probe_out_modified_reg[15]_0\(13), + Q => probe_out_modified(13), + R => \^sr\(0) + ); +\probe_out_modified_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => wr_probe_out_modified, + D => \probe_out_modified_reg[15]_0\(14), + Q => probe_out_modified(14), + R => \^sr\(0) + ); +\probe_out_modified_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => wr_probe_out_modified, + D => \probe_out_modified_reg[15]_0\(15), + Q => probe_out_modified(15), + R => \^sr\(0) + ); +\probe_out_modified_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => wr_probe_out_modified, + D => \probe_out_modified_reg[15]_0\(1), + Q => probe_out_modified(1), + R => \^sr\(0) + ); +\probe_out_modified_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => wr_probe_out_modified, + D => \probe_out_modified_reg[15]_0\(2), + Q => probe_out_modified(2), + R => \^sr\(0) + ); +\probe_out_modified_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => wr_probe_out_modified, + D => \probe_out_modified_reg[15]_0\(3), + Q => probe_out_modified(3), + R => \^sr\(0) + ); +\probe_out_modified_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => wr_probe_out_modified, + D => \probe_out_modified_reg[15]_0\(4), + Q => probe_out_modified(4), + R => \^sr\(0) + ); +\probe_out_modified_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => wr_probe_out_modified, + D => \probe_out_modified_reg[15]_0\(5), + Q => probe_out_modified(5), + R => \^sr\(0) + ); +\probe_out_modified_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => wr_probe_out_modified, + D => \probe_out_modified_reg[15]_0\(6), + Q => probe_out_modified(6), + R => \^sr\(0) + ); +\probe_out_modified_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => wr_probe_out_modified, + D => \probe_out_modified_reg[15]_0\(7), + Q => probe_out_modified(7), + R => \^sr\(0) + ); +\probe_out_modified_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => wr_probe_out_modified, + D => \probe_out_modified_reg[15]_0\(8), + Q => probe_out_modified(8), + R => \^sr\(0) + ); +\probe_out_modified_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => wr_probe_out_modified, + D => \probe_out_modified_reg[15]_0\(9), + Q => probe_out_modified(9), + R => \^sr\(0) + ); +\rd_en[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"08000000" + ) + port map ( + I0 => s_daddr_o(2), + I1 => s_daddr_o(1), + I2 => s_daddr_o(0), + I3 => \rd_en[6]_i_2_n_0\, + I4 => \rd_en_reg[6]_0\, + O => \rd_en[6]_i_1_n_0\ + ); +\rd_en[6]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000100000000" + ) + port map ( + I0 => s_daddr_o(7), + I1 => s_daddr_o(6), + I2 => s_daddr_o(8), + I3 => s_daddr_o(16), + I4 => s_dwe_o, + I5 => s_den_o, + O => \rd_en[6]_i_2_n_0\ + ); +rd_en_p1_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => s_den_o, + I1 => s_dwe_o, + O => xsdb_rd + ); +rd_en_p1_reg: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => xsdb_rd, + Q => rd_en_p1, + R => s_rst_o + ); +rd_en_p2_reg: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => rd_en_p1, + Q => rd_en_p2, + R => s_rst_o + ); +\rd_en_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \rd_en[6]_i_1_n_0\, + Q => rd_probe_out_width, + R => '0' + ); +\wr_en[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000080" + ) + port map ( + I0 => \wr_en[2]_i_2_n_0\, + I1 => \wr_en[2]_i_3_n_0\, + I2 => s_daddr_o(1), + I3 => s_daddr_o(0), + I4 => \^g_probe_out[0].wr_probe_out[0]_i_4_0\, + I5 => \wr_en[4]_i_2_n_0\, + O => \wr_en[2]_i_1_n_0\ + ); +\wr_en[2]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => s_dwe_o, + I1 => s_den_o, + I2 => s_daddr_o(16), + O => \wr_en[2]_i_2_n_0\ + ); +\wr_en[2]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => s_daddr_o(2), + I1 => s_daddr_o(3), + O => \wr_en[2]_i_3_n_0\ + ); +\wr_en[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000020" + ) + port map ( + I0 => \^s_den_o_inst_0\, + I1 => s_daddr_o(0), + I2 => s_daddr_o(2), + I3 => s_daddr_o(3), + I4 => \^g_probe_out[0].wr_probe_out[0]_i_4_0\, + I5 => \wr_en[4]_i_2_n_0\, + O => \wr_en[4]_i_1_n_0\ + ); +\wr_en[4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => s_daddr_o(9), + I1 => \^g_probe_out[0].wr_probe_out[0]_i_3_0\, + I2 => s_daddr_o(11), + I3 => s_daddr_o(10), + I4 => s_daddr_o(8), + O => \wr_en[4]_i_2_n_0\ + ); +\wr_en_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \wr_en[2]_i_1_n_0\, + Q => wr_control_reg, + R => '0' + ); +\wr_en_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \wr_en[4]_i_1_n_0\, + Q => wr_probe_out_modified, + R => '0' + ); +\xsdb_addr_2_0_p2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \xsdb_addr_2_0_p2_reg[2]_0\(0), + Q => xsdb_addr_2_0_p2(0), + R => '0' + ); +\xsdb_addr_2_0_p2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \xsdb_addr_2_0_p2_reg[2]_0\(1), + Q => xsdb_addr_2_0_p2(1), + R => '0' + ); +\xsdb_addr_2_0_p2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \xsdb_addr_2_0_p2_reg[2]_0\(2), + Q => xsdb_addr_2_0_p2(2), + R => '0' + ); +xsdb_addr_8_p1_reg: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => s_daddr_o(8), + Q => xsdb_addr_8_p1, + R => '0' + ); +xsdb_addr_8_p2_reg: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => xsdb_addr_8_p1, + Q => xsdb_addr_8_p2, + R => '0' + ); +xsdb_drdy_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"F8" + ) + port map ( + I0 => s_dwe_o, + I1 => s_den_o, + I2 => rd_en_p2, + O => xsdb_drdy_i_1_n_0 + ); +xsdb_drdy_reg: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => xsdb_drdy_i_1_n_0, + Q => s_drdy_i, + R => s_rst_o + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one is + port ( + probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + D : out STD_LOGIC_VECTOR ( 1 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); + wr_probe_out : in STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + clk : in STD_LOGIC + ); +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one is + signal \^d\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \data_int[0]_i_1_n_0\ : STD_LOGIC; + signal \data_int[1]_i_1_n_0\ : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of \Probe_out_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Probe_out_reg[0]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[1]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[1]\ : label is "yes"; +begin + D(1 downto 0) <= \^d\(1 downto 0); +\Probe_out_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => E(0), + D => \^d\(0), + Q => probe_out0(0), + R => SR(0) + ); +\Probe_out_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => E(0), + D => \^d\(1), + Q => probe_out0(1), + S => SR(0) + ); +\data_int[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => Q(0), + I1 => wr_probe_out(0), + I2 => \^d\(0), + O => \data_int[0]_i_1_n_0\ + ); +\data_int[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => Q(1), + I1 => wr_probe_out(0), + I2 => \^d\(1), + O => \data_int[1]_i_1_n_0\ + ); +\data_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \data_int[0]_i_1_n_0\, + Q => \^d\(0), + R => SR(0) + ); +\data_int_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => \out\, + CE => '1', + D => \data_int[1]_i_1_n_0\, + Q => \^d\(1), + S => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized0\ is + port ( + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + \data_int_reg[0]_0\ : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + clk : in STD_LOGIC; + \out\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + wr_probe_out : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized0\ : entity is "vio_v3_0_20_probe_out_one"; +end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized0\; + +architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized0\ is + signal \data_int[0]_i_1_n_0\ : STD_LOGIC; + signal \^data_int_reg[0]_0\ : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of \Probe_out_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Probe_out_reg[0]\ : label is "yes"; +begin + \data_int_reg[0]_0\ <= \^data_int_reg[0]_0\; +\Probe_out_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => E(0), + D => \^data_int_reg[0]_0\, + Q => probe_out1(0), + R => SR(0) + ); +\data_int[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => Q(0), + I1 => wr_probe_out(0), + I2 => \^data_int_reg[0]_0\, + O => \data_int[0]_i_1_n_0\ + ); +\data_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \data_int[0]_i_1_n_0\, + Q => \^data_int_reg[0]_0\, + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized1\ is + port ( + probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \addr_count[1]_i_5_0\ : out STD_LOGIC; + \Bus_Data_out_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_daddr_o : in STD_LOGIC_VECTOR ( 16 downto 0 ); + s_dwe_o : in STD_LOGIC; + s_den_o : in STD_LOGIC; + internal_cnt_rst : in STD_LOGIC; + \out\ : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \Probe_out_reg[31]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized1\ : entity is "vio_v3_0_20_probe_out_one"; +end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized1\; + +architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized1\ is + signal \Bus_Data_out_int[0]_i_1_n_0\ : STD_LOGIC; + signal \Bus_Data_out_int[10]_i_1_n_0\ : STD_LOGIC; + signal \Bus_Data_out_int[11]_i_1_n_0\ : STD_LOGIC; + signal \Bus_Data_out_int[12]_i_1_n_0\ : STD_LOGIC; + signal \Bus_Data_out_int[13]_i_1_n_0\ : STD_LOGIC; + signal \Bus_Data_out_int[14]_i_1_n_0\ : STD_LOGIC; + signal \Bus_Data_out_int[15]_i_1_n_0\ : STD_LOGIC; + signal \Bus_Data_out_int[1]_i_1_n_0\ : STD_LOGIC; + signal \Bus_Data_out_int[2]_i_1_n_0\ : STD_LOGIC; + signal \Bus_Data_out_int[3]_i_1_n_0\ : STD_LOGIC; + signal \Bus_Data_out_int[4]_i_1_n_0\ : STD_LOGIC; + signal \Bus_Data_out_int[5]_i_1_n_0\ : STD_LOGIC; + signal \Bus_Data_out_int[6]_i_1_n_0\ : STD_LOGIC; + signal \Bus_Data_out_int[7]_i_1_n_0\ : STD_LOGIC; + signal \Bus_Data_out_int[8]_i_1_n_0\ : STD_LOGIC; + signal \Bus_Data_out_int[9]_i_1_n_0\ : STD_LOGIC; + signal addr_count : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \addr_count[0]_i_1_n_0\ : STD_LOGIC; + signal \addr_count[1]_i_1_n_0\ : STD_LOGIC; + signal \addr_count[1]_i_3_n_0\ : STD_LOGIC; + signal \addr_count[1]_i_4_n_0\ : STD_LOGIC; + signal \^addr_count[1]_i_5_0\ : STD_LOGIC; + signal \mem_probe_out[0]\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal rd_probe_out : STD_LOGIC_VECTOR ( 2 to 2 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \Bus_Data_out_int[0]_i_1\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[10]_i_1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[11]_i_1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[12]_i_1\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[13]_i_1\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[14]_i_1\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[15]_i_1\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[1]_i_1\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[2]_i_1\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[3]_i_1\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[4]_i_1\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[5]_i_1\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[6]_i_1\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[7]_i_1\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[8]_i_1\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[9]_i_1\ : label is "soft_lutpair17"; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of \Probe_out_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Probe_out_reg[0]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[10]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[10]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[11]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[11]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[12]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[12]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[13]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[13]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[14]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[14]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[15]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[15]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[16]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[16]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[17]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[17]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[18]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[18]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[19]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[19]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[1]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[1]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[20]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[20]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[21]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[21]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[22]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[22]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[23]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[23]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[24]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[24]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[25]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[25]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[26]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[26]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[27]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[27]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[28]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[28]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[29]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[29]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[2]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[2]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[30]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[30]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[31]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[31]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[3]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[3]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[4]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[4]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[5]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[5]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[6]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[6]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[7]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[7]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[8]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[8]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[9]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[9]\ : label is "yes"; + attribute MAX_FANOUT : string; + attribute MAX_FANOUT of \addr_count_reg[0]\ : label is "200"; + attribute MAX_FANOUT of \addr_count_reg[1]\ : label is "200"; +begin + \addr_count[1]_i_5_0\ <= \^addr_count[1]_i_5_0\; +\Bus_Data_out_int[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \mem_probe_out[0]\(16), + I1 => addr_count(0), + I2 => \mem_probe_out[0]\(0), + O => \Bus_Data_out_int[0]_i_1_n_0\ + ); +\Bus_Data_out_int[10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \mem_probe_out[0]\(26), + I1 => addr_count(0), + I2 => \mem_probe_out[0]\(10), + O => \Bus_Data_out_int[10]_i_1_n_0\ + ); +\Bus_Data_out_int[11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \mem_probe_out[0]\(27), + I1 => addr_count(0), + I2 => \mem_probe_out[0]\(11), + O => \Bus_Data_out_int[11]_i_1_n_0\ + ); +\Bus_Data_out_int[12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \mem_probe_out[0]\(28), + I1 => addr_count(0), + I2 => \mem_probe_out[0]\(12), + O => \Bus_Data_out_int[12]_i_1_n_0\ + ); +\Bus_Data_out_int[13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \mem_probe_out[0]\(29), + I1 => addr_count(0), + I2 => \mem_probe_out[0]\(13), + O => \Bus_Data_out_int[13]_i_1_n_0\ + ); +\Bus_Data_out_int[14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \mem_probe_out[0]\(30), + I1 => addr_count(0), + I2 => \mem_probe_out[0]\(14), + O => \Bus_Data_out_int[14]_i_1_n_0\ + ); +\Bus_Data_out_int[15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \mem_probe_out[0]\(31), + I1 => addr_count(0), + I2 => \mem_probe_out[0]\(15), + O => \Bus_Data_out_int[15]_i_1_n_0\ + ); +\Bus_Data_out_int[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \mem_probe_out[0]\(17), + I1 => addr_count(0), + I2 => \mem_probe_out[0]\(1), + O => \Bus_Data_out_int[1]_i_1_n_0\ + ); +\Bus_Data_out_int[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \mem_probe_out[0]\(18), + I1 => addr_count(0), + I2 => \mem_probe_out[0]\(2), + O => \Bus_Data_out_int[2]_i_1_n_0\ + ); +\Bus_Data_out_int[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \mem_probe_out[0]\(19), + I1 => addr_count(0), + I2 => \mem_probe_out[0]\(3), + O => \Bus_Data_out_int[3]_i_1_n_0\ + ); +\Bus_Data_out_int[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \mem_probe_out[0]\(20), + I1 => addr_count(0), + I2 => \mem_probe_out[0]\(4), + O => \Bus_Data_out_int[4]_i_1_n_0\ + ); +\Bus_Data_out_int[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \mem_probe_out[0]\(21), + I1 => addr_count(0), + I2 => \mem_probe_out[0]\(5), + O => \Bus_Data_out_int[5]_i_1_n_0\ + ); +\Bus_Data_out_int[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \mem_probe_out[0]\(22), + I1 => addr_count(0), + I2 => \mem_probe_out[0]\(6), + O => \Bus_Data_out_int[6]_i_1_n_0\ + ); +\Bus_Data_out_int[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \mem_probe_out[0]\(23), + I1 => addr_count(0), + I2 => \mem_probe_out[0]\(7), + O => \Bus_Data_out_int[7]_i_1_n_0\ + ); +\Bus_Data_out_int[8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \mem_probe_out[0]\(24), + I1 => addr_count(0), + I2 => \mem_probe_out[0]\(8), + O => \Bus_Data_out_int[8]_i_1_n_0\ + ); +\Bus_Data_out_int[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \mem_probe_out[0]\(25), + I1 => addr_count(0), + I2 => \mem_probe_out[0]\(9), + O => \Bus_Data_out_int[9]_i_1_n_0\ + ); +\Bus_Data_out_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_Data_out_int[0]_i_1_n_0\, + Q => \Bus_Data_out_int_reg[15]_0\(0), + R => '0' + ); +\Bus_Data_out_int_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_Data_out_int[10]_i_1_n_0\, + Q => \Bus_Data_out_int_reg[15]_0\(10), + R => '0' + ); +\Bus_Data_out_int_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_Data_out_int[11]_i_1_n_0\, + Q => \Bus_Data_out_int_reg[15]_0\(11), + R => '0' + ); +\Bus_Data_out_int_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_Data_out_int[12]_i_1_n_0\, + Q => \Bus_Data_out_int_reg[15]_0\(12), + R => '0' + ); +\Bus_Data_out_int_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_Data_out_int[13]_i_1_n_0\, + Q => \Bus_Data_out_int_reg[15]_0\(13), + R => '0' + ); +\Bus_Data_out_int_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_Data_out_int[14]_i_1_n_0\, + Q => \Bus_Data_out_int_reg[15]_0\(14), + R => '0' + ); +\Bus_Data_out_int_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_Data_out_int[15]_i_1_n_0\, + Q => \Bus_Data_out_int_reg[15]_0\(15), + R => '0' + ); +\Bus_Data_out_int_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_Data_out_int[1]_i_1_n_0\, + Q => \Bus_Data_out_int_reg[15]_0\(1), + R => '0' + ); +\Bus_Data_out_int_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_Data_out_int[2]_i_1_n_0\, + Q => \Bus_Data_out_int_reg[15]_0\(2), + R => '0' + ); +\Bus_Data_out_int_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_Data_out_int[3]_i_1_n_0\, + Q => \Bus_Data_out_int_reg[15]_0\(3), + R => '0' + ); +\Bus_Data_out_int_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_Data_out_int[4]_i_1_n_0\, + Q => \Bus_Data_out_int_reg[15]_0\(4), + R => '0' + ); +\Bus_Data_out_int_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_Data_out_int[5]_i_1_n_0\, + Q => \Bus_Data_out_int_reg[15]_0\(5), + R => '0' + ); +\Bus_Data_out_int_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_Data_out_int[6]_i_1_n_0\, + Q => \Bus_Data_out_int_reg[15]_0\(6), + R => '0' + ); +\Bus_Data_out_int_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_Data_out_int[7]_i_1_n_0\, + Q => \Bus_Data_out_int_reg[15]_0\(7), + R => '0' + ); +\Bus_Data_out_int_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_Data_out_int[8]_i_1_n_0\, + Q => \Bus_Data_out_int_reg[15]_0\(8), + R => '0' + ); +\Bus_Data_out_int_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Bus_Data_out_int[9]_i_1_n_0\, + Q => \Bus_Data_out_int_reg[15]_0\(9), + R => '0' + ); +\LOOP_I[1].data_int_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => \mem_probe_out[0]\(0), + Q => \mem_probe_out[0]\(16), + R => SR(0) + ); +\LOOP_I[1].data_int_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => \mem_probe_out[0]\(1), + Q => \mem_probe_out[0]\(17), + R => SR(0) + ); +\LOOP_I[1].data_int_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => \mem_probe_out[0]\(2), + Q => \mem_probe_out[0]\(18), + R => SR(0) + ); +\LOOP_I[1].data_int_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => \mem_probe_out[0]\(3), + Q => \mem_probe_out[0]\(19), + R => SR(0) + ); +\LOOP_I[1].data_int_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => \mem_probe_out[0]\(4), + Q => \mem_probe_out[0]\(20), + R => SR(0) + ); +\LOOP_I[1].data_int_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => \mem_probe_out[0]\(5), + Q => \mem_probe_out[0]\(21), + R => SR(0) + ); +\LOOP_I[1].data_int_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => \mem_probe_out[0]\(6), + Q => \mem_probe_out[0]\(22), + R => SR(0) + ); +\LOOP_I[1].data_int_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => \mem_probe_out[0]\(7), + Q => \mem_probe_out[0]\(23), + R => SR(0) + ); +\LOOP_I[1].data_int_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => \mem_probe_out[0]\(8), + Q => \mem_probe_out[0]\(24), + R => SR(0) + ); +\LOOP_I[1].data_int_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => \mem_probe_out[0]\(9), + Q => \mem_probe_out[0]\(25), + R => SR(0) + ); +\LOOP_I[1].data_int_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => \mem_probe_out[0]\(10), + Q => \mem_probe_out[0]\(26), + R => SR(0) + ); +\LOOP_I[1].data_int_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => \mem_probe_out[0]\(11), + Q => \mem_probe_out[0]\(27), + R => SR(0) + ); +\LOOP_I[1].data_int_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => \mem_probe_out[0]\(12), + Q => \mem_probe_out[0]\(28), + R => SR(0) + ); +\LOOP_I[1].data_int_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => \mem_probe_out[0]\(13), + Q => \mem_probe_out[0]\(29), + R => SR(0) + ); +\LOOP_I[1].data_int_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => \mem_probe_out[0]\(14), + Q => \mem_probe_out[0]\(30), + R => SR(0) + ); +\LOOP_I[1].data_int_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => \mem_probe_out[0]\(15), + Q => \mem_probe_out[0]\(31), + R => SR(0) + ); +\Probe_out_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(0), + Q => probe_out2(0), + R => SR(0) + ); +\Probe_out_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(10), + Q => probe_out2(10), + R => SR(0) + ); +\Probe_out_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(11), + Q => probe_out2(11), + R => SR(0) + ); +\Probe_out_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(12), + Q => probe_out2(12), + R => SR(0) + ); +\Probe_out_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(13), + Q => probe_out2(13), + R => SR(0) + ); +\Probe_out_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(14), + Q => probe_out2(14), + R => SR(0) + ); +\Probe_out_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(15), + Q => probe_out2(15), + R => SR(0) + ); +\Probe_out_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(16), + Q => probe_out2(16), + R => SR(0) + ); +\Probe_out_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(17), + Q => probe_out2(17), + R => SR(0) + ); +\Probe_out_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(18), + Q => probe_out2(18), + R => SR(0) + ); +\Probe_out_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(19), + Q => probe_out2(19), + R => SR(0) + ); +\Probe_out_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(1), + Q => probe_out2(1), + R => SR(0) + ); +\Probe_out_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(20), + Q => probe_out2(20), + R => SR(0) + ); +\Probe_out_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(21), + Q => probe_out2(21), + R => SR(0) + ); +\Probe_out_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(22), + Q => probe_out2(22), + R => SR(0) + ); +\Probe_out_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(23), + Q => probe_out2(23), + R => SR(0) + ); +\Probe_out_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(24), + Q => probe_out2(24), + R => SR(0) + ); +\Probe_out_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(25), + Q => probe_out2(25), + R => SR(0) + ); +\Probe_out_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(26), + Q => probe_out2(26), + R => SR(0) + ); +\Probe_out_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(27), + Q => probe_out2(27), + R => SR(0) + ); +\Probe_out_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(28), + Q => probe_out2(28), + R => SR(0) + ); +\Probe_out_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(29), + Q => probe_out2(29), + R => SR(0) + ); +\Probe_out_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(2), + Q => probe_out2(2), + R => SR(0) + ); +\Probe_out_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(30), + Q => probe_out2(30), + R => SR(0) + ); +\Probe_out_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(31), + Q => probe_out2(31), + R => SR(0) + ); +\Probe_out_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(3), + Q => probe_out2(3), + R => SR(0) + ); +\Probe_out_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(4), + Q => probe_out2(4), + R => SR(0) + ); +\Probe_out_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(5), + Q => probe_out2(5), + R => SR(0) + ); +\Probe_out_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(6), + Q => probe_out2(6), + R => SR(0) + ); +\Probe_out_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(7), + Q => probe_out2(7), + R => SR(0) + ); +\Probe_out_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(8), + Q => probe_out2(8), + R => SR(0) + ); +\Probe_out_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[31]_0\(0), + D => \mem_probe_out[0]\(9), + Q => probe_out2(9), + R => SR(0) + ); +\addr_count[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0322" + ) + port map ( + I0 => addr_count(0), + I1 => internal_cnt_rst, + I2 => addr_count(0), + I3 => rd_probe_out(2), + O => \addr_count[0]_i_1_n_0\ + ); +\addr_count[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00302222" + ) + port map ( + I0 => addr_count(1), + I1 => internal_cnt_rst, + I2 => addr_count(1), + I3 => addr_count(0), + I4 => rd_probe_out(2), + O => \addr_count[1]_i_1_n_0\ + ); +\addr_count[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000008000" + ) + port map ( + I0 => \addr_count[1]_i_3_n_0\, + I1 => \addr_count[1]_i_4_n_0\, + I2 => \^addr_count[1]_i_5_0\, + I3 => s_daddr_o(8), + I4 => s_daddr_o(6), + I5 => s_daddr_o(7), + O => rd_probe_out(2) + ); +\addr_count[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000400000000" + ) + port map ( + I0 => s_dwe_o, + I1 => s_den_o, + I2 => s_daddr_o(16), + I3 => s_daddr_o(2), + I4 => s_daddr_o(0), + I5 => s_daddr_o(1), + O => \addr_count[1]_i_3_n_0\ + ); +\addr_count[1]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => s_daddr_o(13), + I1 => s_daddr_o(12), + I2 => s_daddr_o(14), + I3 => s_daddr_o(15), + O => \addr_count[1]_i_4_n_0\ + ); +\addr_count[1]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => s_daddr_o(4), + I1 => s_daddr_o(3), + I2 => s_daddr_o(5), + I3 => s_daddr_o(10), + I4 => s_daddr_o(9), + I5 => s_daddr_o(11), + O => \^addr_count[1]_i_5_0\ + ); +\addr_count_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \addr_count[0]_i_1_n_0\, + Q => addr_count(0), + R => '0' + ); +\addr_count_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \addr_count[1]_i_1_n_0\, + Q => addr_count(1), + R => '0' + ); +\data_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => Q(0), + Q => \mem_probe_out[0]\(0), + R => SR(0) + ); +\data_int_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => Q(10), + Q => \mem_probe_out[0]\(10), + R => SR(0) + ); +\data_int_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => Q(11), + Q => \mem_probe_out[0]\(11), + R => SR(0) + ); +\data_int_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => Q(12), + Q => \mem_probe_out[0]\(12), + R => SR(0) + ); +\data_int_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => Q(13), + Q => \mem_probe_out[0]\(13), + R => SR(0) + ); +\data_int_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => Q(14), + Q => \mem_probe_out[0]\(14), + R => SR(0) + ); +\data_int_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => Q(15), + Q => \mem_probe_out[0]\(15), + R => SR(0) + ); +\data_int_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => Q(1), + Q => \mem_probe_out[0]\(1), + R => SR(0) + ); +\data_int_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => Q(2), + Q => \mem_probe_out[0]\(2), + R => SR(0) + ); +\data_int_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => Q(3), + Q => \mem_probe_out[0]\(3), + R => SR(0) + ); +\data_int_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => Q(4), + Q => \mem_probe_out[0]\(4), + R => SR(0) + ); +\data_int_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => Q(5), + Q => \mem_probe_out[0]\(5), + R => SR(0) + ); +\data_int_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => Q(6), + Q => \mem_probe_out[0]\(6), + R => SR(0) + ); +\data_int_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => Q(7), + Q => \mem_probe_out[0]\(7), + R => SR(0) + ); +\data_int_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => Q(8), + Q => \mem_probe_out[0]\(8), + R => SR(0) + ); +\data_int_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => Q(9), + Q => \mem_probe_out[0]\(9), + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized2\ is + port ( + probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + D : out STD_LOGIC_VECTOR ( 1 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); + wr_probe_out : in STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : in STD_LOGIC; + \Probe_out_reg[1]_0\ : in STD_LOGIC; + clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized2\ : entity is "vio_v3_0_20_probe_out_one"; +end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized2\; + +architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized2\ is + signal \^d\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \data_int[0]_i_1_n_0\ : STD_LOGIC; + signal \data_int[1]_i_1_n_0\ : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of \Probe_out_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Probe_out_reg[0]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[1]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[1]\ : label is "yes"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \data_int[0]_i_1\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \data_int[1]_i_1\ : label is "soft_lutpair22"; +begin + D(1 downto 0) <= \^d\(1 downto 0); +\Probe_out_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \Probe_out_reg[1]_0\, + D => \^d\(0), + Q => probe_out3(0), + S => SR(0) + ); +\Probe_out_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \Probe_out_reg[1]_0\, + D => \^d\(1), + Q => probe_out3(1), + S => SR(0) + ); +\data_int[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => Q(0), + I1 => wr_probe_out(0), + I2 => \^d\(0), + O => \data_int[0]_i_1_n_0\ + ); +\data_int[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => Q(1), + I1 => wr_probe_out(0), + I2 => \^d\(1), + O => \data_int[1]_i_1_n_0\ + ); +\data_int_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => \out\, + CE => '1', + D => \data_int[0]_i_1_n_0\, + Q => \^d\(0), + S => SR(0) + ); +\data_int_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => \out\, + CE => '1', + D => \data_int[1]_i_1_n_0\, + Q => \^d\(1), + S => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized3\ is + port ( + probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 3 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \data_int_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \out\ : in STD_LOGIC; + \Probe_out_reg[3]_0\ : in STD_LOGIC; + clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized3\ : entity is "vio_v3_0_20_probe_out_one"; +end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized3\; + +architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized3\ is + signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of \Probe_out_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Probe_out_reg[0]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[1]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[1]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[2]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[2]\ : label is "yes"; + attribute DONT_TOUCH of \Probe_out_reg[3]\ : label is std.standard.true; + attribute KEEP of \Probe_out_reg[3]\ : label is "yes"; +begin + Q(3 downto 0) <= \^q\(3 downto 0); +\Probe_out_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[3]_0\, + D => \^q\(0), + Q => probe_out4(0), + R => SR(0) + ); +\Probe_out_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[3]_0\, + D => \^q\(1), + Q => probe_out4(1), + R => SR(0) + ); +\Probe_out_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[3]_0\, + D => \^q\(2), + Q => probe_out4(2), + R => SR(0) + ); +\Probe_out_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \Probe_out_reg[3]_0\, + D => \^q\(3), + Q => probe_out4(3), + R => SR(0) + ); +\data_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => \data_int_reg[3]_0\(0), + Q => \^q\(0), + R => SR(0) + ); +\data_int_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => \data_int_reg[3]_0\(1), + Q => \^q\(1), + R => SR(0) + ); +\data_int_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => \data_int_reg[3]_0\(2), + Q => \^q\(2), + R => SR(0) + ); +\data_int_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => E(0), + D => \data_int_reg[3]_0\(3), + Q => \^q\(3), + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_width is + port ( + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + rd_probe_out_width : in STD_LOGIC; + s_rst_o : in STD_LOGIC; + internal_cnt_rst : in STD_LOGIC; + \out\ : in STD_LOGIC + ); +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_width; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_width is + signal addr_count : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \addr_count[0]_i_1_n_0\ : STD_LOGIC; + signal \addr_count[1]_i_1_n_0\ : STD_LOGIC; + signal probe_width_mem : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \addr_count[0]_i_1\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \addr_count[1]_i_1\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \probe_width_int[1]_i_1\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \probe_width_int[8]_i_1\ : label is "soft_lutpair31"; +begin +\addr_count[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000001A" + ) + port map ( + I0 => addr_count(0), + I1 => addr_count(1), + I2 => rd_probe_out_width, + I3 => s_rst_o, + I4 => internal_cnt_rst, + O => \addr_count[0]_i_1_n_0\ + ); +\addr_count[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000002C" + ) + port map ( + I0 => addr_count(0), + I1 => addr_count(1), + I2 => rd_probe_out_width, + I3 => s_rst_o, + I4 => internal_cnt_rst, + O => \addr_count[1]_i_1_n_0\ + ); +\addr_count_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \addr_count[0]_i_1_n_0\, + Q => addr_count(0), + R => '0' + ); +\addr_count_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \addr_count[1]_i_1_n_0\, + Q => addr_count(1), + R => '0' + ); +\probe_width_int[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => addr_count(1), + I1 => addr_count(0), + O => probe_width_mem(0) + ); +\probe_width_int[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => addr_count(0), + I1 => addr_count(1), + O => probe_width_mem(1) + ); +\probe_width_int[8]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => addr_count(0), + I1 => addr_count(1), + O => probe_width_mem(8) + ); +\probe_width_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => probe_width_mem(0), + Q => Q(0), + R => '0' + ); +\probe_width_int_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => probe_width_mem(1), + Q => Q(1), + R => '0' + ); +\probe_width_int_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => probe_width_mem(8), + Q => Q(2), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs is + port ( + s_rst_o : out STD_LOGIC; + s_dclk_o : out STD_LOGIC; + s_den_o : out STD_LOGIC; + s_dwe_o : out STD_LOGIC; + s_daddr_o : out STD_LOGIC_VECTOR ( 16 downto 0 ); + s_di_o : out STD_LOGIC_VECTOR ( 15 downto 0 ); + sl_oport_o : out STD_LOGIC_VECTOR ( 16 downto 0 ); + s_do_i : in STD_LOGIC_VECTOR ( 15 downto 0 ); + sl_iport_i : in STD_LOGIC_VECTOR ( 36 downto 0 ); + s_drdy_i : in STD_LOGIC + ); + attribute C_BUILD_REVISION : integer; + attribute C_BUILD_REVISION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0; + attribute C_CORE_INFO1 : string; + attribute C_CORE_INFO1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_CORE_INFO2 : string; + attribute C_CORE_INFO2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_CORE_MAJOR_VER : integer; + attribute C_CORE_MAJOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2; + attribute C_CORE_MINOR_VER : integer; + attribute C_CORE_MINOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0; + attribute C_CORE_TYPE : integer; + attribute C_CORE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2; + attribute C_CSE_DRV_VER : integer; + attribute C_CSE_DRV_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1; + attribute C_MAJOR_VERSION : integer; + attribute C_MAJOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2013; + attribute C_MINOR_VERSION : integer; + attribute C_MINOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1; + attribute C_NEXT_SLAVE : integer; + attribute C_NEXT_SLAVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0; + attribute C_PIPE_IFACE : integer; + attribute C_PIPE_IFACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0; + attribute C_USE_TEST_REG : integer; + attribute C_USE_TEST_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1; + attribute C_XDEVICEFAMILY : string; + attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "kintex7"; + attribute C_XSDB_SLAVE_TYPE : integer; + attribute C_XSDB_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 33; + attribute dont_touch : string; + attribute dont_touch of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "true"; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs is + signal reg_do : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \reg_do[0]_i_2_n_0\ : STD_LOGIC; + signal \reg_do[0]_i_3_n_0\ : STD_LOGIC; + signal \reg_do[0]_i_4_n_0\ : STD_LOGIC; + signal \reg_do[10]_i_2_n_0\ : STD_LOGIC; + signal \reg_do[10]_i_3_n_0\ : STD_LOGIC; + signal \reg_do[10]_i_4_n_0\ : STD_LOGIC; + signal \reg_do[10]_i_5_n_0\ : STD_LOGIC; + signal \reg_do[11]_i_2_n_0\ : STD_LOGIC; + signal \reg_do[11]_i_3_n_0\ : STD_LOGIC; + signal \reg_do[12]_i_2_n_0\ : STD_LOGIC; + signal \reg_do[12]_i_3_n_0\ : STD_LOGIC; + signal \reg_do[13]_i_2_n_0\ : STD_LOGIC; + signal \reg_do[13]_i_3_n_0\ : STD_LOGIC; + signal \reg_do[14]_i_2_n_0\ : STD_LOGIC; + signal \reg_do[14]_i_3_n_0\ : STD_LOGIC; + signal \reg_do[15]_i_2_n_0\ : STD_LOGIC; + signal \reg_do[15]_i_3_n_0\ : STD_LOGIC; + signal \reg_do[15]_i_4_n_0\ : STD_LOGIC; + signal \reg_do[15]_i_5_n_0\ : STD_LOGIC; + signal \reg_do[15]_i_6_n_0\ : STD_LOGIC; + signal \reg_do[1]_i_2_n_0\ : STD_LOGIC; + signal \reg_do[1]_i_3_n_0\ : STD_LOGIC; + signal \reg_do[1]_i_4_n_0\ : STD_LOGIC; + signal \reg_do[2]_i_2_n_0\ : STD_LOGIC; + signal \reg_do[2]_i_3_n_0\ : STD_LOGIC; + signal \reg_do[2]_i_4_n_0\ : STD_LOGIC; + signal \reg_do[3]_i_2_n_0\ : STD_LOGIC; + signal \reg_do[3]_i_3_n_0\ : STD_LOGIC; + signal \reg_do[3]_i_4_n_0\ : STD_LOGIC; + signal \reg_do[4]_i_2_n_0\ : STD_LOGIC; + signal \reg_do[4]_i_3_n_0\ : STD_LOGIC; + signal \reg_do[4]_i_4_n_0\ : STD_LOGIC; + signal \reg_do[5]_i_2_n_0\ : STD_LOGIC; + signal \reg_do[5]_i_3_n_0\ : STD_LOGIC; + signal \reg_do[5]_i_4_n_0\ : STD_LOGIC; + signal \reg_do[5]_i_5_n_0\ : STD_LOGIC; + signal \reg_do[6]_i_2_n_0\ : STD_LOGIC; + signal \reg_do[6]_i_3_n_0\ : STD_LOGIC; + signal \reg_do[6]_i_4_n_0\ : STD_LOGIC; + signal \reg_do[7]_i_2_n_0\ : STD_LOGIC; + signal \reg_do[7]_i_3_n_0\ : STD_LOGIC; + signal \reg_do[7]_i_4_n_0\ : STD_LOGIC; + signal \reg_do[8]_i_2_n_0\ : STD_LOGIC; + signal \reg_do[8]_i_3_n_0\ : STD_LOGIC; + signal \reg_do[8]_i_4_n_0\ : STD_LOGIC; + signal \reg_do[9]_i_2_n_0\ : STD_LOGIC; + signal \reg_do[9]_i_3_n_0\ : STD_LOGIC; + signal \reg_do[9]_i_4_n_0\ : STD_LOGIC; + signal \reg_do[9]_i_5_n_0\ : STD_LOGIC; + signal \reg_do[9]_i_6_n_0\ : STD_LOGIC; + signal \reg_do_reg_n_0_[0]\ : STD_LOGIC; + signal \reg_do_reg_n_0_[10]\ : STD_LOGIC; + signal \reg_do_reg_n_0_[11]\ : STD_LOGIC; + signal \reg_do_reg_n_0_[12]\ : STD_LOGIC; + signal \reg_do_reg_n_0_[13]\ : STD_LOGIC; + signal \reg_do_reg_n_0_[14]\ : STD_LOGIC; + signal \reg_do_reg_n_0_[15]\ : STD_LOGIC; + signal \reg_do_reg_n_0_[1]\ : STD_LOGIC; + signal \reg_do_reg_n_0_[2]\ : STD_LOGIC; + signal \reg_do_reg_n_0_[3]\ : STD_LOGIC; + signal \reg_do_reg_n_0_[4]\ : STD_LOGIC; + signal \reg_do_reg_n_0_[5]\ : STD_LOGIC; + signal \reg_do_reg_n_0_[6]\ : STD_LOGIC; + signal \reg_do_reg_n_0_[7]\ : STD_LOGIC; + signal \reg_do_reg_n_0_[8]\ : STD_LOGIC; + signal \reg_do_reg_n_0_[9]\ : STD_LOGIC; + signal reg_drdy : STD_LOGIC; + signal reg_drdy_i_1_n_0 : STD_LOGIC; + signal reg_test : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal reg_test0 : STD_LOGIC; + signal s_den_o_INST_0_i_1_n_0 : STD_LOGIC; + signal \^sl_iport_i\ : STD_LOGIC_VECTOR ( 36 downto 0 ); + signal uuid_stamp : STD_LOGIC_VECTOR ( 127 downto 0 ); + attribute DONT_TOUCH_boolean : boolean; + attribute DONT_TOUCH_boolean of uuid_stamp : signal is std.standard.true; + attribute UUID : string; + attribute UUID of uuid_stamp : signal is "1"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \reg_do[15]_i_2\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \reg_do[15]_i_4\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \reg_do[9]_i_2\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \reg_do[9]_i_3\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \sl_oport_o[0]_INST_0\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \sl_oport_o[10]_INST_0\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \sl_oport_o[11]_INST_0\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \sl_oport_o[12]_INST_0\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \sl_oport_o[13]_INST_0\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \sl_oport_o[14]_INST_0\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \sl_oport_o[15]_INST_0\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \sl_oport_o[1]_INST_0\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \sl_oport_o[2]_INST_0\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \sl_oport_o[3]_INST_0\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \sl_oport_o[4]_INST_0\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \sl_oport_o[5]_INST_0\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \sl_oport_o[6]_INST_0\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \sl_oport_o[7]_INST_0\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \sl_oport_o[8]_INST_0\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \sl_oport_o[9]_INST_0\ : label is "soft_lutpair5"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \uuid_stamp_reg[0]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[0]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[100]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[100]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[100]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[101]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[101]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[101]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[102]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[102]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[102]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[103]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[103]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[103]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[104]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[104]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[104]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[105]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[105]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[105]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[106]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[106]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[106]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[107]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[107]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[107]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[108]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[108]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[108]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[109]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[109]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[109]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[10]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[10]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[10]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[110]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[110]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[110]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[111]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[111]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[111]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[112]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[112]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[112]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[113]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[113]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[113]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[114]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[114]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[114]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[115]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[115]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[115]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[116]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[116]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[116]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[117]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[117]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[117]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[118]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[118]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[118]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[119]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[119]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[119]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[11]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[11]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[11]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[120]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[120]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[120]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[121]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[121]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[121]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[122]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[122]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[122]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[123]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[123]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[123]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[124]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[124]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[124]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[125]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[125]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[125]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[126]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[126]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[126]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[127]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[127]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[127]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[12]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[12]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[12]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[13]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[13]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[13]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[14]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[14]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[14]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[15]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[15]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[15]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[16]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[16]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[16]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[17]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[17]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[17]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[18]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[18]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[18]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[19]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[19]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[19]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[1]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[1]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[1]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[20]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[20]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[20]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[21]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[21]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[21]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[22]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[22]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[22]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[23]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[23]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[23]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[24]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[24]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[24]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[25]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[25]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[25]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[26]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[26]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[26]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[27]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[27]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[27]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[28]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[28]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[28]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[29]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[29]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[29]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[2]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[2]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[2]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[30]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[30]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[30]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[31]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[31]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[31]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[32]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[32]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[32]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[33]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[33]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[33]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[34]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[34]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[34]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[35]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[35]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[35]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[36]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[36]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[36]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[37]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[37]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[37]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[38]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[38]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[38]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[39]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[39]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[39]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[3]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[3]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[3]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[40]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[40]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[40]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[41]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[41]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[41]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[42]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[42]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[42]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[43]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[43]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[43]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[44]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[44]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[44]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[45]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[45]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[45]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[46]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[46]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[46]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[47]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[47]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[47]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[48]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[48]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[48]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[49]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[49]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[49]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[4]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[4]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[4]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[50]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[50]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[50]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[51]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[51]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[51]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[52]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[52]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[52]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[53]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[53]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[53]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[54]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[54]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[54]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[55]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[55]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[55]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[56]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[56]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[56]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[57]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[57]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[57]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[58]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[58]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[58]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[59]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[59]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[59]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[5]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[5]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[5]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[60]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[60]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[60]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[61]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[61]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[61]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[62]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[62]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[62]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[63]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[63]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[63]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[64]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[64]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[64]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[65]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[65]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[65]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[66]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[66]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[66]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[67]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[67]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[67]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[68]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[68]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[68]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[69]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[69]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[69]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[6]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[6]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[6]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[70]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[70]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[70]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[71]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[71]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[71]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[72]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[72]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[72]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[73]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[73]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[73]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[74]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[74]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[74]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[75]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[75]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[75]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[76]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[76]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[76]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[77]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[77]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[77]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[78]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[78]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[78]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[79]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[79]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[79]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[7]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[7]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[7]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[80]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[80]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[80]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[81]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[81]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[81]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[82]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[82]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[82]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[83]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[83]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[83]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[84]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[84]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[84]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[85]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[85]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[85]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[86]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[86]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[86]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[87]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[87]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[87]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[88]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[88]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[88]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[89]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[89]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[89]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[8]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[8]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[8]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[90]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[90]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[90]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[91]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[91]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[91]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[92]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[92]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[92]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[93]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[93]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[93]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[94]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[94]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[94]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[95]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[95]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[95]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[96]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[96]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[96]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[97]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[97]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[97]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[98]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[98]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[98]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[99]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[99]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[99]\ : label is "1"; + attribute DONT_TOUCH_boolean of \uuid_stamp_reg[9]\ : label is std.standard.true; + attribute KEEP of \uuid_stamp_reg[9]\ : label is "yes"; + attribute UUID of \uuid_stamp_reg[9]\ : label is "1"; +begin + \^sl_iport_i\(36 downto 0) <= sl_iport_i(36 downto 0); + s_daddr_o(16 downto 0) <= \^sl_iport_i\(20 downto 4); + s_dclk_o <= \^sl_iport_i\(1); + s_di_o(15 downto 0) <= \^sl_iport_i\(36 downto 21); + s_dwe_o <= \^sl_iport_i\(3); + s_rst_o <= \^sl_iport_i\(0); +\reg_do[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAA0020AAAA" + ) + port map ( + I0 => \reg_do[0]_i_2_n_0\, + I1 => \reg_do[9]_i_3_n_0\, + I2 => reg_test(0), + I3 => \^sl_iport_i\(4), + I4 => \^sl_iport_i\(5), + I5 => \reg_do[9]_i_2_n_0\, + O => reg_do(0) + ); +\reg_do[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"ABABABAAAAAAABAA" + ) + port map ( + I0 => \reg_do[5]_i_3_n_0\, + I1 => \^sl_iport_i\(8), + I2 => \^sl_iport_i\(7), + I3 => \reg_do[0]_i_3_n_0\, + I4 => \^sl_iport_i\(6), + I5 => \reg_do[0]_i_4_n_0\, + O => \reg_do[0]_i_2_n_0\ + ); +\reg_do[0]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(48), + I1 => uuid_stamp(32), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(16), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(0), + O => \reg_do[0]_i_3_n_0\ + ); +\reg_do[0]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(112), + I1 => uuid_stamp(96), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(80), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(64), + O => \reg_do[0]_i_4_n_0\ + ); +\reg_do[10]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF2808" + ) + port map ( + I0 => \reg_do[10]_i_2_n_0\, + I1 => \^sl_iport_i\(4), + I2 => \^sl_iport_i\(5), + I3 => reg_test(10), + I4 => \reg_do[10]_i_3_n_0\, + O => reg_do(10) + ); +\reg_do[10]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0800000000000000" + ) + port map ( + I0 => \^sl_iport_i\(6), + I1 => \^sl_iport_i\(9), + I2 => \^sl_iport_i\(7), + I3 => \^sl_iport_i\(8), + I4 => \^sl_iport_i\(11), + I5 => \^sl_iport_i\(10), + O => \reg_do[10]_i_2_n_0\ + ); +\reg_do[10]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AAFBAA08" + ) + port map ( + I0 => \reg_do[10]_i_4_n_0\, + I1 => \^sl_iport_i\(6), + I2 => \^sl_iport_i\(7), + I3 => \^sl_iport_i\(8), + I4 => \reg_do[10]_i_5_n_0\, + I5 => \reg_do[15]_i_4_n_0\, + O => \reg_do[10]_i_3_n_0\ + ); +\reg_do[10]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(122), + I1 => uuid_stamp(106), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(90), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(74), + O => \reg_do[10]_i_4_n_0\ + ); +\reg_do[10]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(58), + I1 => uuid_stamp(42), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(26), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(10), + O => \reg_do[10]_i_5_n_0\ + ); +\reg_do[11]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4540FFFF45404540" + ) + port map ( + I0 => \reg_do[15]_i_4_n_0\, + I1 => \reg_do[11]_i_2_n_0\, + I2 => \reg_do[15]_i_2_n_0\, + I3 => \reg_do[11]_i_3_n_0\, + I4 => \reg_do[15]_i_6_n_0\, + I5 => reg_test(11), + O => reg_do(11) + ); +\reg_do[11]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(59), + I1 => uuid_stamp(43), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(27), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(11), + O => \reg_do[11]_i_2_n_0\ + ); +\reg_do[11]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(123), + I1 => uuid_stamp(107), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(91), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(75), + O => \reg_do[11]_i_3_n_0\ + ); +\reg_do[12]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5404FFFF54045404" + ) + port map ( + I0 => \reg_do[15]_i_4_n_0\, + I1 => \reg_do[12]_i_2_n_0\, + I2 => \reg_do[15]_i_2_n_0\, + I3 => \reg_do[12]_i_3_n_0\, + I4 => \reg_do[15]_i_6_n_0\, + I5 => reg_test(12), + O => reg_do(12) + ); +\reg_do[12]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(124), + I1 => uuid_stamp(108), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(92), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(76), + O => \reg_do[12]_i_2_n_0\ + ); +\reg_do[12]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(60), + I1 => uuid_stamp(44), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(28), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(12), + O => \reg_do[12]_i_3_n_0\ + ); +\reg_do[13]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4540FFFF45404540" + ) + port map ( + I0 => \reg_do[15]_i_4_n_0\, + I1 => \reg_do[13]_i_2_n_0\, + I2 => \reg_do[15]_i_2_n_0\, + I3 => \reg_do[13]_i_3_n_0\, + I4 => \reg_do[15]_i_6_n_0\, + I5 => reg_test(13), + O => reg_do(13) + ); +\reg_do[13]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(61), + I1 => uuid_stamp(45), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(29), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(13), + O => \reg_do[13]_i_2_n_0\ + ); +\reg_do[13]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(125), + I1 => uuid_stamp(109), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(93), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(77), + O => \reg_do[13]_i_3_n_0\ + ); +\reg_do[14]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4540FFFF45404540" + ) + port map ( + I0 => \reg_do[15]_i_4_n_0\, + I1 => \reg_do[14]_i_2_n_0\, + I2 => \reg_do[15]_i_2_n_0\, + I3 => \reg_do[14]_i_3_n_0\, + I4 => \reg_do[15]_i_6_n_0\, + I5 => reg_test(14), + O => reg_do(14) + ); +\reg_do[14]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(62), + I1 => uuid_stamp(46), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(30), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(14), + O => \reg_do[14]_i_2_n_0\ + ); +\reg_do[14]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(126), + I1 => uuid_stamp(110), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(94), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(78), + O => \reg_do[14]_i_3_n_0\ + ); +\reg_do[15]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0B01FFFF0B010B01" + ) + port map ( + I0 => \reg_do[15]_i_2_n_0\, + I1 => \reg_do[15]_i_3_n_0\, + I2 => \reg_do[15]_i_4_n_0\, + I3 => \reg_do[15]_i_5_n_0\, + I4 => \reg_do[15]_i_6_n_0\, + I5 => reg_test(15), + O => reg_do(15) + ); +\reg_do[15]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"45" + ) + port map ( + I0 => \^sl_iport_i\(8), + I1 => \^sl_iport_i\(7), + I2 => \^sl_iport_i\(6), + O => \reg_do[15]_i_2_n_0\ + ); +\reg_do[15]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"505F3030505F3F3F" + ) + port map ( + I0 => uuid_stamp(127), + I1 => uuid_stamp(111), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(95), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(79), + O => \reg_do[15]_i_3_n_0\ + ); +\reg_do[15]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \^sl_iport_i\(7), + I1 => \^sl_iport_i\(8), + I2 => \^sl_iport_i\(9), + I3 => \^sl_iport_i\(11), + I4 => \^sl_iport_i\(10), + O => \reg_do[15]_i_4_n_0\ + ); +\reg_do[15]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(63), + I1 => uuid_stamp(47), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(31), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(15), + O => \reg_do[15]_i_5_n_0\ + ); +\reg_do[15]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFD0FFFFFFFF" + ) + port map ( + I0 => \^sl_iport_i\(6), + I1 => \^sl_iport_i\(7), + I2 => \^sl_iport_i\(8), + I3 => \reg_do[9]_i_2_n_0\, + I4 => \^sl_iport_i\(4), + I5 => \^sl_iport_i\(5), + O => \reg_do[15]_i_6_n_0\ + ); +\reg_do[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAAFEAA" + ) + port map ( + I0 => \reg_do[1]_i_2_n_0\, + I1 => reg_test(1), + I2 => \reg_do[9]_i_3_n_0\, + I3 => \^sl_iport_i\(5), + I4 => \^sl_iport_i\(4), + I5 => \reg_do[9]_i_2_n_0\, + O => reg_do(1) + ); +\reg_do[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFAE00A2" + ) + port map ( + I0 => \reg_do[1]_i_3_n_0\, + I1 => \^sl_iport_i\(6), + I2 => \^sl_iport_i\(7), + I3 => \^sl_iport_i\(8), + I4 => \reg_do[1]_i_4_n_0\, + I5 => \reg_do[15]_i_4_n_0\, + O => \reg_do[1]_i_2_n_0\ + ); +\reg_do[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(49), + I1 => uuid_stamp(33), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(17), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(1), + O => \reg_do[1]_i_3_n_0\ + ); +\reg_do[1]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(113), + I1 => uuid_stamp(97), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(81), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(65), + O => \reg_do[1]_i_4_n_0\ + ); +\reg_do[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF6200" + ) + port map ( + I0 => \^sl_iport_i\(4), + I1 => \^sl_iport_i\(5), + I2 => reg_test(2), + I3 => \reg_do[10]_i_2_n_0\, + I4 => \reg_do[2]_i_2_n_0\, + O => reg_do(2) + ); +\reg_do[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AAFBAA08" + ) + port map ( + I0 => \reg_do[2]_i_3_n_0\, + I1 => \^sl_iport_i\(6), + I2 => \^sl_iport_i\(7), + I3 => \^sl_iport_i\(8), + I4 => \reg_do[2]_i_4_n_0\, + I5 => \reg_do[15]_i_4_n_0\, + O => \reg_do[2]_i_2_n_0\ + ); +\reg_do[2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(114), + I1 => uuid_stamp(98), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(82), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(66), + O => \reg_do[2]_i_3_n_0\ + ); +\reg_do[2]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(50), + I1 => uuid_stamp(34), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(18), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(2), + O => \reg_do[2]_i_4_n_0\ + ); +\reg_do[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF6200" + ) + port map ( + I0 => \^sl_iport_i\(4), + I1 => \^sl_iport_i\(5), + I2 => reg_test(3), + I3 => \reg_do[10]_i_2_n_0\, + I4 => \reg_do[3]_i_2_n_0\, + O => reg_do(3) + ); +\reg_do[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000003333AA3A" + ) + port map ( + I0 => \reg_do[3]_i_3_n_0\, + I1 => \reg_do[3]_i_4_n_0\, + I2 => \^sl_iport_i\(6), + I3 => \^sl_iport_i\(7), + I4 => \^sl_iport_i\(8), + I5 => \reg_do[15]_i_4_n_0\, + O => \reg_do[3]_i_2_n_0\ + ); +\reg_do[3]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(51), + I1 => uuid_stamp(35), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(19), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(3), + O => \reg_do[3]_i_3_n_0\ + ); +\reg_do[3]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"05F5030305F5F3F3" + ) + port map ( + I0 => uuid_stamp(83), + I1 => uuid_stamp(67), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(115), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(99), + O => \reg_do[3]_i_4_n_0\ + ); +\reg_do[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF6200" + ) + port map ( + I0 => \^sl_iport_i\(4), + I1 => \^sl_iport_i\(5), + I2 => reg_test(4), + I3 => \reg_do[10]_i_2_n_0\, + I4 => \reg_do[4]_i_2_n_0\, + O => reg_do(4) + ); +\reg_do[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFAE00A2" + ) + port map ( + I0 => \reg_do[4]_i_3_n_0\, + I1 => \^sl_iport_i\(6), + I2 => \^sl_iport_i\(7), + I3 => \^sl_iport_i\(8), + I4 => \reg_do[4]_i_4_n_0\, + I5 => \reg_do[15]_i_4_n_0\, + O => \reg_do[4]_i_2_n_0\ + ); +\reg_do[4]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(52), + I1 => uuid_stamp(36), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(20), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(4), + O => \reg_do[4]_i_3_n_0\ + ); +\reg_do[4]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(116), + I1 => uuid_stamp(100), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(84), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(68), + O => \reg_do[4]_i_4_n_0\ + ); +\reg_do[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"888888888A88A8A8" + ) + port map ( + I0 => \reg_do[5]_i_2_n_0\, + I1 => \reg_do[9]_i_2_n_0\, + I2 => \reg_do[9]_i_3_n_0\, + I3 => reg_test(5), + I4 => \^sl_iport_i\(5), + I5 => \^sl_iport_i\(4), + O => reg_do(5) + ); +\reg_do[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"ABABABAAAAAAABAA" + ) + port map ( + I0 => \reg_do[5]_i_3_n_0\, + I1 => \^sl_iport_i\(8), + I2 => \^sl_iport_i\(7), + I3 => \reg_do[5]_i_4_n_0\, + I4 => \^sl_iport_i\(6), + I5 => \reg_do[5]_i_5_n_0\, + O => \reg_do[5]_i_2_n_0\ + ); +\reg_do[5]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \^sl_iport_i\(10), + I1 => \^sl_iport_i\(11), + I2 => \^sl_iport_i\(9), + I3 => \^sl_iport_i\(8), + O => \reg_do[5]_i_3_n_0\ + ); +\reg_do[5]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(53), + I1 => uuid_stamp(37), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(21), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(5), + O => \reg_do[5]_i_4_n_0\ + ); +\reg_do[5]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(117), + I1 => uuid_stamp(101), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(85), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(69), + O => \reg_do[5]_i_5_n_0\ + ); +\reg_do[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF6200" + ) + port map ( + I0 => \^sl_iport_i\(4), + I1 => \^sl_iport_i\(5), + I2 => reg_test(6), + I3 => \reg_do[10]_i_2_n_0\, + I4 => \reg_do[6]_i_2_n_0\, + O => reg_do(6) + ); +\reg_do[6]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AAFBAA08" + ) + port map ( + I0 => \reg_do[6]_i_3_n_0\, + I1 => \^sl_iport_i\(6), + I2 => \^sl_iport_i\(7), + I3 => \^sl_iport_i\(8), + I4 => \reg_do[6]_i_4_n_0\, + I5 => \reg_do[15]_i_4_n_0\, + O => \reg_do[6]_i_2_n_0\ + ); +\reg_do[6]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(118), + I1 => uuid_stamp(102), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(86), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(70), + O => \reg_do[6]_i_3_n_0\ + ); +\reg_do[6]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(54), + I1 => uuid_stamp(38), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(22), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(6), + O => \reg_do[6]_i_4_n_0\ + ); +\reg_do[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF6200" + ) + port map ( + I0 => \^sl_iport_i\(4), + I1 => \^sl_iport_i\(5), + I2 => reg_test(7), + I3 => \reg_do[10]_i_2_n_0\, + I4 => \reg_do[7]_i_2_n_0\, + O => reg_do(7) + ); +\reg_do[7]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AAFBAA08" + ) + port map ( + I0 => \reg_do[7]_i_3_n_0\, + I1 => \^sl_iport_i\(6), + I2 => \^sl_iport_i\(7), + I3 => \^sl_iport_i\(8), + I4 => \reg_do[7]_i_4_n_0\, + I5 => \reg_do[15]_i_4_n_0\, + O => \reg_do[7]_i_2_n_0\ + ); +\reg_do[7]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(119), + I1 => uuid_stamp(103), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(87), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(71), + O => \reg_do[7]_i_3_n_0\ + ); +\reg_do[7]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(55), + I1 => uuid_stamp(39), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(23), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(7), + O => \reg_do[7]_i_4_n_0\ + ); +\reg_do[8]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7500" + ) + port map ( + I0 => \^sl_iport_i\(5), + I1 => \^sl_iport_i\(4), + I2 => reg_test(8), + I3 => \reg_do[10]_i_2_n_0\, + I4 => \reg_do[8]_i_2_n_0\, + O => reg_do(8) + ); +\reg_do[8]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AAFBAA08" + ) + port map ( + I0 => \reg_do[8]_i_3_n_0\, + I1 => \^sl_iport_i\(6), + I2 => \^sl_iport_i\(7), + I3 => \^sl_iport_i\(8), + I4 => \reg_do[8]_i_4_n_0\, + I5 => \reg_do[15]_i_4_n_0\, + O => \reg_do[8]_i_2_n_0\ + ); +\reg_do[8]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(120), + I1 => uuid_stamp(104), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(88), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(72), + O => \reg_do[8]_i_3_n_0\ + ); +\reg_do[8]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(56), + I1 => uuid_stamp(40), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(24), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(8), + O => \reg_do[8]_i_4_n_0\ + ); +\reg_do[9]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF40144010" + ) + port map ( + I0 => \reg_do[9]_i_2_n_0\, + I1 => \^sl_iport_i\(5), + I2 => \^sl_iport_i\(4), + I3 => \reg_do[9]_i_3_n_0\, + I4 => reg_test(9), + I5 => \reg_do[9]_i_4_n_0\, + O => reg_do(9) + ); +\reg_do[9]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF7FFFFF" + ) + port map ( + I0 => \^sl_iport_i\(10), + I1 => \^sl_iport_i\(11), + I2 => \^sl_iport_i\(8), + I3 => \^sl_iport_i\(7), + I4 => \^sl_iport_i\(9), + O => \reg_do[9]_i_2_n_0\ + ); +\reg_do[9]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8A" + ) + port map ( + I0 => \^sl_iport_i\(8), + I1 => \^sl_iport_i\(7), + I2 => \^sl_iport_i\(6), + O => \reg_do[9]_i_3_n_0\ + ); +\reg_do[9]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AAFBAA08" + ) + port map ( + I0 => \reg_do[9]_i_5_n_0\, + I1 => \^sl_iport_i\(6), + I2 => \^sl_iport_i\(7), + I3 => \^sl_iport_i\(8), + I4 => \reg_do[9]_i_6_n_0\, + I5 => \reg_do[15]_i_4_n_0\, + O => \reg_do[9]_i_4_n_0\ + ); +\reg_do[9]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(121), + I1 => uuid_stamp(105), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(89), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(73), + O => \reg_do[9]_i_5_n_0\ + ); +\reg_do[9]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => uuid_stamp(57), + I1 => uuid_stamp(41), + I2 => \^sl_iport_i\(5), + I3 => uuid_stamp(25), + I4 => \^sl_iport_i\(4), + I5 => uuid_stamp(9), + O => \reg_do[9]_i_6_n_0\ + ); +\reg_do_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => reg_do(0), + Q => \reg_do_reg_n_0_[0]\, + R => '0' + ); +\reg_do_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => reg_do(10), + Q => \reg_do_reg_n_0_[10]\, + R => '0' + ); +\reg_do_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => reg_do(11), + Q => \reg_do_reg_n_0_[11]\, + R => '0' + ); +\reg_do_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => reg_do(12), + Q => \reg_do_reg_n_0_[12]\, + R => '0' + ); +\reg_do_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => reg_do(13), + Q => \reg_do_reg_n_0_[13]\, + R => '0' + ); +\reg_do_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => reg_do(14), + Q => \reg_do_reg_n_0_[14]\, + R => '0' + ); +\reg_do_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => reg_do(15), + Q => \reg_do_reg_n_0_[15]\, + R => '0' + ); +\reg_do_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => reg_do(1), + Q => \reg_do_reg_n_0_[1]\, + R => '0' + ); +\reg_do_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => reg_do(2), + Q => \reg_do_reg_n_0_[2]\, + R => '0' + ); +\reg_do_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => reg_do(3), + Q => \reg_do_reg_n_0_[3]\, + R => '0' + ); +\reg_do_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => reg_do(4), + Q => \reg_do_reg_n_0_[4]\, + R => '0' + ); +\reg_do_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => reg_do(5), + Q => \reg_do_reg_n_0_[5]\, + R => '0' + ); +\reg_do_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => reg_do(6), + Q => \reg_do_reg_n_0_[6]\, + R => '0' + ); +\reg_do_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => reg_do(7), + Q => \reg_do_reg_n_0_[7]\, + R => '0' + ); +\reg_do_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => reg_do(8), + Q => \reg_do_reg_n_0_[8]\, + R => '0' + ); +\reg_do_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => reg_do(9), + Q => \reg_do_reg_n_0_[9]\, + R => '0' + ); +reg_drdy_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000800000000000" + ) + port map ( + I0 => s_den_o_INST_0_i_1_n_0, + I1 => \^sl_iport_i\(12), + I2 => \^sl_iport_i\(13), + I3 => \^sl_iport_i\(14), + I4 => \^sl_iport_i\(0), + I5 => \^sl_iport_i\(2), + O => reg_drdy_i_1_n_0 + ); +reg_drdy_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => reg_drdy_i_1_n_0, + Q => reg_drdy, + R => '0' + ); +\reg_test[15]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => s_den_o_INST_0_i_1_n_0, + I1 => \^sl_iport_i\(12), + I2 => \^sl_iport_i\(13), + I3 => \^sl_iport_i\(14), + I4 => \^sl_iport_i\(3), + I5 => \^sl_iport_i\(2), + O => reg_test0 + ); +\reg_test_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => reg_test0, + D => \^sl_iport_i\(21), + Q => reg_test(0), + R => '0' + ); +\reg_test_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => reg_test0, + D => \^sl_iport_i\(31), + Q => reg_test(10), + R => '0' + ); +\reg_test_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => reg_test0, + D => \^sl_iport_i\(32), + Q => reg_test(11), + R => '0' + ); +\reg_test_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => reg_test0, + D => \^sl_iport_i\(33), + Q => reg_test(12), + R => '0' + ); +\reg_test_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => reg_test0, + D => \^sl_iport_i\(34), + Q => reg_test(13), + R => '0' + ); +\reg_test_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => reg_test0, + D => \^sl_iport_i\(35), + Q => reg_test(14), + R => '0' + ); +\reg_test_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => reg_test0, + D => \^sl_iport_i\(36), + Q => reg_test(15), + R => '0' + ); +\reg_test_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => reg_test0, + D => \^sl_iport_i\(22), + Q => reg_test(1), + R => '0' + ); +\reg_test_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => reg_test0, + D => \^sl_iport_i\(23), + Q => reg_test(2), + R => '0' + ); +\reg_test_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => reg_test0, + D => \^sl_iport_i\(24), + Q => reg_test(3), + R => '0' + ); +\reg_test_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => reg_test0, + D => \^sl_iport_i\(25), + Q => reg_test(4), + R => '0' + ); +\reg_test_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => reg_test0, + D => \^sl_iport_i\(26), + Q => reg_test(5), + R => '0' + ); +\reg_test_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => reg_test0, + D => \^sl_iport_i\(27), + Q => reg_test(6), + R => '0' + ); +\reg_test_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => reg_test0, + D => \^sl_iport_i\(28), + Q => reg_test(7), + R => '0' + ); +\reg_test_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => reg_test0, + D => \^sl_iport_i\(29), + Q => reg_test(8), + R => '0' + ); +\reg_test_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \^sl_iport_i\(1), + CE => reg_test0, + D => \^sl_iport_i\(30), + Q => reg_test(9), + R => '0' + ); +s_den_o_INST_0: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF0000" + ) + port map ( + I0 => s_den_o_INST_0_i_1_n_0, + I1 => \^sl_iport_i\(12), + I2 => \^sl_iport_i\(13), + I3 => \^sl_iport_i\(14), + I4 => \^sl_iport_i\(2), + O => s_den_o + ); +s_den_o_INST_0_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => \^sl_iport_i\(15), + I1 => \^sl_iport_i\(16), + I2 => \^sl_iport_i\(17), + I3 => \^sl_iport_i\(18), + I4 => \^sl_iport_i\(20), + I5 => \^sl_iport_i\(19), + O => s_den_o_INST_0_i_1_n_0 + ); +\sl_oport_o[0]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => reg_drdy, + I1 => s_drdy_i, + O => sl_oport_o(0) + ); +\sl_oport_o[10]_INST_0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \reg_do_reg_n_0_[9]\, + I1 => reg_drdy, + I2 => s_do_i(9), + O => sl_oport_o(10) + ); +\sl_oport_o[11]_INST_0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \reg_do_reg_n_0_[10]\, + I1 => reg_drdy, + I2 => s_do_i(10), + O => sl_oport_o(11) + ); +\sl_oport_o[12]_INST_0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \reg_do_reg_n_0_[11]\, + I1 => reg_drdy, + I2 => s_do_i(11), + O => sl_oport_o(12) + ); +\sl_oport_o[13]_INST_0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \reg_do_reg_n_0_[12]\, + I1 => reg_drdy, + I2 => s_do_i(12), + O => sl_oport_o(13) + ); +\sl_oport_o[14]_INST_0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \reg_do_reg_n_0_[13]\, + I1 => reg_drdy, + I2 => s_do_i(13), + O => sl_oport_o(14) + ); +\sl_oport_o[15]_INST_0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \reg_do_reg_n_0_[14]\, + I1 => reg_drdy, + I2 => s_do_i(14), + O => sl_oport_o(15) + ); +\sl_oport_o[16]_INST_0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \reg_do_reg_n_0_[15]\, + I1 => reg_drdy, + I2 => s_do_i(15), + O => sl_oport_o(16) + ); +\sl_oport_o[1]_INST_0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \reg_do_reg_n_0_[0]\, + I1 => reg_drdy, + I2 => s_do_i(0), + O => sl_oport_o(1) + ); +\sl_oport_o[2]_INST_0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \reg_do_reg_n_0_[1]\, + I1 => reg_drdy, + I2 => s_do_i(1), + O => sl_oport_o(2) + ); +\sl_oport_o[3]_INST_0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \reg_do_reg_n_0_[2]\, + I1 => reg_drdy, + I2 => s_do_i(2), + O => sl_oport_o(3) + ); +\sl_oport_o[4]_INST_0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \reg_do_reg_n_0_[3]\, + I1 => reg_drdy, + I2 => s_do_i(3), + O => sl_oport_o(4) + ); +\sl_oport_o[5]_INST_0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \reg_do_reg_n_0_[4]\, + I1 => reg_drdy, + I2 => s_do_i(4), + O => sl_oport_o(5) + ); +\sl_oport_o[6]_INST_0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \reg_do_reg_n_0_[5]\, + I1 => reg_drdy, + I2 => s_do_i(5), + O => sl_oport_o(6) + ); +\sl_oport_o[7]_INST_0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \reg_do_reg_n_0_[6]\, + I1 => reg_drdy, + I2 => s_do_i(6), + O => sl_oport_o(7) + ); +\sl_oport_o[8]_INST_0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \reg_do_reg_n_0_[7]\, + I1 => reg_drdy, + I2 => s_do_i(7), + O => sl_oport_o(8) + ); +\sl_oport_o[9]_INST_0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \reg_do_reg_n_0_[8]\, + I1 => reg_drdy, + I2 => s_do_i(8), + O => sl_oport_o(9) + ); +\uuid_stamp_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(0), + Q => uuid_stamp(0), + R => '0' + ); +\uuid_stamp_reg[100]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(100), + Q => uuid_stamp(100), + R => '0' + ); +\uuid_stamp_reg[101]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(101), + Q => uuid_stamp(101), + R => '0' + ); +\uuid_stamp_reg[102]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(102), + Q => uuid_stamp(102), + R => '0' + ); +\uuid_stamp_reg[103]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(103), + Q => uuid_stamp(103), + R => '0' + ); +\uuid_stamp_reg[104]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(104), + Q => uuid_stamp(104), + R => '0' + ); +\uuid_stamp_reg[105]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(105), + Q => uuid_stamp(105), + R => '0' + ); +\uuid_stamp_reg[106]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(106), + Q => uuid_stamp(106), + R => '0' + ); +\uuid_stamp_reg[107]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(107), + Q => uuid_stamp(107), + R => '0' + ); +\uuid_stamp_reg[108]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(108), + Q => uuid_stamp(108), + R => '0' + ); +\uuid_stamp_reg[109]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(109), + Q => uuid_stamp(109), + R => '0' + ); +\uuid_stamp_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(10), + Q => uuid_stamp(10), + R => '0' + ); +\uuid_stamp_reg[110]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(110), + Q => uuid_stamp(110), + R => '0' + ); +\uuid_stamp_reg[111]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(111), + Q => uuid_stamp(111), + R => '0' + ); +\uuid_stamp_reg[112]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(112), + Q => uuid_stamp(112), + R => '0' + ); +\uuid_stamp_reg[113]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(113), + Q => uuid_stamp(113), + R => '0' + ); +\uuid_stamp_reg[114]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(114), + Q => uuid_stamp(114), + R => '0' + ); +\uuid_stamp_reg[115]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(115), + Q => uuid_stamp(115), + R => '0' + ); +\uuid_stamp_reg[116]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(116), + Q => uuid_stamp(116), + R => '0' + ); +\uuid_stamp_reg[117]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(117), + Q => uuid_stamp(117), + R => '0' + ); +\uuid_stamp_reg[118]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(118), + Q => uuid_stamp(118), + R => '0' + ); +\uuid_stamp_reg[119]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(119), + Q => uuid_stamp(119), + R => '0' + ); +\uuid_stamp_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(11), + Q => uuid_stamp(11), + R => '0' + ); +\uuid_stamp_reg[120]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(120), + Q => uuid_stamp(120), + R => '0' + ); +\uuid_stamp_reg[121]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(121), + Q => uuid_stamp(121), + R => '0' + ); +\uuid_stamp_reg[122]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(122), + Q => uuid_stamp(122), + R => '0' + ); +\uuid_stamp_reg[123]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(123), + Q => uuid_stamp(123), + R => '0' + ); +\uuid_stamp_reg[124]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(124), + Q => uuid_stamp(124), + R => '0' + ); +\uuid_stamp_reg[125]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(125), + Q => uuid_stamp(125), + R => '0' + ); +\uuid_stamp_reg[126]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(126), + Q => uuid_stamp(126), + R => '0' + ); +\uuid_stamp_reg[127]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(127), + Q => uuid_stamp(127), + R => '0' + ); +\uuid_stamp_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(12), + Q => uuid_stamp(12), + R => '0' + ); +\uuid_stamp_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(13), + Q => uuid_stamp(13), + R => '0' + ); +\uuid_stamp_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(14), + Q => uuid_stamp(14), + R => '0' + ); +\uuid_stamp_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(15), + Q => uuid_stamp(15), + R => '0' + ); +\uuid_stamp_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(16), + Q => uuid_stamp(16), + R => '0' + ); +\uuid_stamp_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(17), + Q => uuid_stamp(17), + R => '0' + ); +\uuid_stamp_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(18), + Q => uuid_stamp(18), + R => '0' + ); +\uuid_stamp_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(19), + Q => uuid_stamp(19), + R => '0' + ); +\uuid_stamp_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(1), + Q => uuid_stamp(1), + R => '0' + ); +\uuid_stamp_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(20), + Q => uuid_stamp(20), + R => '0' + ); +\uuid_stamp_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(21), + Q => uuid_stamp(21), + R => '0' + ); +\uuid_stamp_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(22), + Q => uuid_stamp(22), + R => '0' + ); +\uuid_stamp_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(23), + Q => uuid_stamp(23), + R => '0' + ); +\uuid_stamp_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(24), + Q => uuid_stamp(24), + R => '0' + ); +\uuid_stamp_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(25), + Q => uuid_stamp(25), + R => '0' + ); +\uuid_stamp_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(26), + Q => uuid_stamp(26), + R => '0' + ); +\uuid_stamp_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(27), + Q => uuid_stamp(27), + R => '0' + ); +\uuid_stamp_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(28), + Q => uuid_stamp(28), + R => '0' + ); +\uuid_stamp_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(29), + Q => uuid_stamp(29), + R => '0' + ); +\uuid_stamp_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(2), + Q => uuid_stamp(2), + R => '0' + ); +\uuid_stamp_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(30), + Q => uuid_stamp(30), + R => '0' + ); +\uuid_stamp_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(31), + Q => uuid_stamp(31), + R => '0' + ); +\uuid_stamp_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(32), + Q => uuid_stamp(32), + R => '0' + ); +\uuid_stamp_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(33), + Q => uuid_stamp(33), + R => '0' + ); +\uuid_stamp_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(34), + Q => uuid_stamp(34), + R => '0' + ); +\uuid_stamp_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(35), + Q => uuid_stamp(35), + R => '0' + ); +\uuid_stamp_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(36), + Q => uuid_stamp(36), + R => '0' + ); +\uuid_stamp_reg[37]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(37), + Q => uuid_stamp(37), + R => '0' + ); +\uuid_stamp_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(38), + Q => uuid_stamp(38), + R => '0' + ); +\uuid_stamp_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(39), + Q => uuid_stamp(39), + R => '0' + ); +\uuid_stamp_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(3), + Q => uuid_stamp(3), + R => '0' + ); +\uuid_stamp_reg[40]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(40), + Q => uuid_stamp(40), + R => '0' + ); +\uuid_stamp_reg[41]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(41), + Q => uuid_stamp(41), + R => '0' + ); +\uuid_stamp_reg[42]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(42), + Q => uuid_stamp(42), + R => '0' + ); +\uuid_stamp_reg[43]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(43), + Q => uuid_stamp(43), + R => '0' + ); +\uuid_stamp_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(44), + Q => uuid_stamp(44), + R => '0' + ); +\uuid_stamp_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(45), + Q => uuid_stamp(45), + R => '0' + ); +\uuid_stamp_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(46), + Q => uuid_stamp(46), + R => '0' + ); +\uuid_stamp_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(47), + Q => uuid_stamp(47), + R => '0' + ); +\uuid_stamp_reg[48]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(48), + Q => uuid_stamp(48), + R => '0' + ); +\uuid_stamp_reg[49]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(49), + Q => uuid_stamp(49), + R => '0' + ); +\uuid_stamp_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(4), + Q => uuid_stamp(4), + R => '0' + ); +\uuid_stamp_reg[50]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(50), + Q => uuid_stamp(50), + R => '0' + ); +\uuid_stamp_reg[51]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(51), + Q => uuid_stamp(51), + R => '0' + ); +\uuid_stamp_reg[52]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(52), + Q => uuid_stamp(52), + R => '0' + ); +\uuid_stamp_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(53), + Q => uuid_stamp(53), + R => '0' + ); +\uuid_stamp_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(54), + Q => uuid_stamp(54), + R => '0' + ); +\uuid_stamp_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(55), + Q => uuid_stamp(55), + R => '0' + ); +\uuid_stamp_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(56), + Q => uuid_stamp(56), + R => '0' + ); +\uuid_stamp_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(57), + Q => uuid_stamp(57), + R => '0' + ); +\uuid_stamp_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(58), + Q => uuid_stamp(58), + R => '0' + ); +\uuid_stamp_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(59), + Q => uuid_stamp(59), + R => '0' + ); +\uuid_stamp_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(5), + Q => uuid_stamp(5), + R => '0' + ); +\uuid_stamp_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(60), + Q => uuid_stamp(60), + R => '0' + ); +\uuid_stamp_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(61), + Q => uuid_stamp(61), + R => '0' + ); +\uuid_stamp_reg[62]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(62), + Q => uuid_stamp(62), + R => '0' + ); +\uuid_stamp_reg[63]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(63), + Q => uuid_stamp(63), + R => '0' + ); +\uuid_stamp_reg[64]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(64), + Q => uuid_stamp(64), + R => '0' + ); +\uuid_stamp_reg[65]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(65), + Q => uuid_stamp(65), + R => '0' + ); +\uuid_stamp_reg[66]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(66), + Q => uuid_stamp(66), + R => '0' + ); +\uuid_stamp_reg[67]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(67), + Q => uuid_stamp(67), + R => '0' + ); +\uuid_stamp_reg[68]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(68), + Q => uuid_stamp(68), + R => '0' + ); +\uuid_stamp_reg[69]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(69), + Q => uuid_stamp(69), + R => '0' + ); +\uuid_stamp_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(6), + Q => uuid_stamp(6), + R => '0' + ); +\uuid_stamp_reg[70]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(70), + Q => uuid_stamp(70), + R => '0' + ); +\uuid_stamp_reg[71]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(71), + Q => uuid_stamp(71), + R => '0' + ); +\uuid_stamp_reg[72]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(72), + Q => uuid_stamp(72), + R => '0' + ); +\uuid_stamp_reg[73]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(73), + Q => uuid_stamp(73), + R => '0' + ); +\uuid_stamp_reg[74]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(74), + Q => uuid_stamp(74), + R => '0' + ); +\uuid_stamp_reg[75]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(75), + Q => uuid_stamp(75), + R => '0' + ); +\uuid_stamp_reg[76]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(76), + Q => uuid_stamp(76), + R => '0' + ); +\uuid_stamp_reg[77]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(77), + Q => uuid_stamp(77), + R => '0' + ); +\uuid_stamp_reg[78]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(78), + Q => uuid_stamp(78), + R => '0' + ); +\uuid_stamp_reg[79]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(79), + Q => uuid_stamp(79), + R => '0' + ); +\uuid_stamp_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(7), + Q => uuid_stamp(7), + R => '0' + ); +\uuid_stamp_reg[80]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(80), + Q => uuid_stamp(80), + R => '0' + ); +\uuid_stamp_reg[81]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(81), + Q => uuid_stamp(81), + R => '0' + ); +\uuid_stamp_reg[82]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(82), + Q => uuid_stamp(82), + R => '0' + ); +\uuid_stamp_reg[83]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(83), + Q => uuid_stamp(83), + R => '0' + ); +\uuid_stamp_reg[84]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(84), + Q => uuid_stamp(84), + R => '0' + ); +\uuid_stamp_reg[85]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(85), + Q => uuid_stamp(85), + R => '0' + ); +\uuid_stamp_reg[86]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(86), + Q => uuid_stamp(86), + R => '0' + ); +\uuid_stamp_reg[87]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(87), + Q => uuid_stamp(87), + R => '0' + ); +\uuid_stamp_reg[88]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(88), + Q => uuid_stamp(88), + R => '0' + ); +\uuid_stamp_reg[89]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(89), + Q => uuid_stamp(89), + R => '0' + ); +\uuid_stamp_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(8), + Q => uuid_stamp(8), + R => '0' + ); +\uuid_stamp_reg[90]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(90), + Q => uuid_stamp(90), + R => '0' + ); +\uuid_stamp_reg[91]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(91), + Q => uuid_stamp(91), + R => '0' + ); +\uuid_stamp_reg[92]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(92), + Q => uuid_stamp(92), + R => '0' + ); +\uuid_stamp_reg[93]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(93), + Q => uuid_stamp(93), + R => '0' + ); +\uuid_stamp_reg[94]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(94), + Q => uuid_stamp(94), + R => '0' + ); +\uuid_stamp_reg[95]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(95), + Q => uuid_stamp(95), + R => '0' + ); +\uuid_stamp_reg[96]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(96), + Q => uuid_stamp(96), + R => '0' + ); +\uuid_stamp_reg[97]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(97), + Q => uuid_stamp(97), + R => '0' + ); +\uuid_stamp_reg[98]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(98), + Q => uuid_stamp(98), + R => '0' + ); +\uuid_stamp_reg[99]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(99), + Q => uuid_stamp(99), + R => '0' + ); +\uuid_stamp_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => \^sl_iport_i\(1), + CE => '1', + D => uuid_stamp(9), + Q => uuid_stamp(9), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_all is + port ( + probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \addr_count[1]_i_5\ : out STD_LOGIC; + \addr_p1_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \Probe_out_reg_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \Probe_out_reg_int_reg[15]_0\ : out STD_LOGIC; + \Probe_out_reg_int_reg[14]_0\ : out STD_LOGIC; + \Probe_out_reg_int_reg[13]_0\ : out STD_LOGIC; + \Probe_out_reg_int_reg[12]_0\ : out STD_LOGIC; + \Probe_out_reg_int_reg[11]_0\ : out STD_LOGIC; + \Probe_out_reg_int_reg[10]_0\ : out STD_LOGIC; + \Probe_out_reg_int_reg[9]_0\ : out STD_LOGIC; + \Probe_out_reg_int_reg[8]_0\ : out STD_LOGIC; + \Probe_out_reg_int_reg[7]_0\ : out STD_LOGIC; + \Probe_out_reg_int_reg[6]_0\ : out STD_LOGIC; + \Probe_out_reg_int_reg[5]_0\ : out STD_LOGIC; + \Probe_out_reg_int_reg[4]_0\ : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + in0 : in STD_LOGIC; + clk : in STD_LOGIC; + \out\ : in STD_LOGIC; + s_daddr_o : in STD_LOGIC_VECTOR ( 16 downto 0 ); + s_dwe_o : in STD_LOGIC; + s_den_o : in STD_LOGIC; + \G_PROBE_OUT[0].wr_probe_out_reg[0]_0\ : in STD_LOGIC; + \G_PROBE_OUT[0].wr_probe_out_reg[0]_1\ : in STD_LOGIC; + \G_PROBE_OUT[0].wr_probe_out_reg[0]_2\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 15 downto 0 ); + internal_cnt_rst : in STD_LOGIC + ); +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_all; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_all is + signal Bus_Data_out_int : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal Committ_1 : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Committ_1 : signal is "true"; + signal Committ_2 : STD_LOGIC; + attribute async_reg of Committ_2 : signal is "true"; + signal \G_PROBE_OUT[0].PROBE_OUT0_INST_n_2\ : STD_LOGIC; + signal \G_PROBE_OUT[0].PROBE_OUT0_INST_n_3\ : STD_LOGIC; + signal \G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0\ : STD_LOGIC; + signal \G_PROBE_OUT[0].wr_probe_out[0]_i_2_n_0\ : STD_LOGIC; + signal \G_PROBE_OUT[0].wr_probe_out[0]_i_6_n_0\ : STD_LOGIC; + signal \G_PROBE_OUT[1].PROBE_OUT0_INST_n_1\ : STD_LOGIC; + signal \G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0\ : STD_LOGIC; + signal \G_PROBE_OUT[1].wr_probe_out[1]_i_2_n_0\ : STD_LOGIC; + signal \G_PROBE_OUT[2].PROBE_OUT0_INST_n_32\ : STD_LOGIC; + signal \G_PROBE_OUT[2].wr_probe_out[2]_i_1_n_0\ : STD_LOGIC; + signal \G_PROBE_OUT[2].wr_probe_out_reg\ : STD_LOGIC; + signal \G_PROBE_OUT[3].PROBE_OUT0_INST_n_2\ : STD_LOGIC; + signal \G_PROBE_OUT[3].PROBE_OUT0_INST_n_3\ : STD_LOGIC; + signal \G_PROBE_OUT[3].wr_probe_out[3]_i_1_n_0\ : STD_LOGIC; + signal \G_PROBE_OUT[4].PROBE_OUT0_INST_n_4\ : STD_LOGIC; + signal \G_PROBE_OUT[4].PROBE_OUT0_INST_n_5\ : STD_LOGIC; + signal \G_PROBE_OUT[4].PROBE_OUT0_INST_n_6\ : STD_LOGIC; + signal \G_PROBE_OUT[4].PROBE_OUT0_INST_n_7\ : STD_LOGIC; + signal \G_PROBE_OUT[4].wr_probe_out[4]_i_1_n_0\ : STD_LOGIC; + signal \Probe_out_reg_int[0]_i_2_n_0\ : STD_LOGIC; + signal \Probe_out_reg_int[10]_i_1_n_0\ : STD_LOGIC; + signal \Probe_out_reg_int[11]_i_1_n_0\ : STD_LOGIC; + signal \Probe_out_reg_int[12]_i_1_n_0\ : STD_LOGIC; + signal \Probe_out_reg_int[13]_i_1_n_0\ : STD_LOGIC; + signal \Probe_out_reg_int[14]_i_1_n_0\ : STD_LOGIC; + signal \Probe_out_reg_int[15]_i_1_n_0\ : STD_LOGIC; + signal \Probe_out_reg_int[1]_i_2_n_0\ : STD_LOGIC; + signal \Probe_out_reg_int[4]_i_1_n_0\ : STD_LOGIC; + signal \Probe_out_reg_int[5]_i_1_n_0\ : STD_LOGIC; + signal \Probe_out_reg_int[6]_i_1_n_0\ : STD_LOGIC; + signal \Probe_out_reg_int[7]_i_1_n_0\ : STD_LOGIC; + signal \Probe_out_reg_int[8]_i_1_n_0\ : STD_LOGIC; + signal \Probe_out_reg_int[9]_i_1_n_0\ : STD_LOGIC; + signal \^addr_count[1]_i_5\ : STD_LOGIC; + signal \^addr_p1_reg[2]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal probe_out_mem : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal wr_probe_out : STD_LOGIC_VECTOR ( 4 downto 0 ); + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of Committ_1_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of Committ_1_reg : label is "yes"; + attribute ASYNC_REG_boolean of Committ_2_reg : label is std.standard.true; + attribute KEEP of Committ_2_reg : label is "yes"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \Probe_out_reg_int[0]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[10]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[11]_i_1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[12]_i_1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[13]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[14]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[15]_i_1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[1]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[4]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[5]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[6]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[7]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[8]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[9]_i_1\ : label is "soft_lutpair26"; +begin + \addr_count[1]_i_5\ <= \^addr_count[1]_i_5\; + \addr_p1_reg[2]_0\(2 downto 0) <= \^addr_p1_reg[2]_0\(2 downto 0); +Committ_1_reg: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => in0, + Q => Committ_1, + R => '0' + ); +Committ_2_reg: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => Committ_1, + Q => Committ_2, + R => '0' + ); +\G_PROBE_OUT[0].PROBE_OUT0_INST\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one + port map ( + D(1) => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_2\, + D(0) => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_3\, + E(0) => Committ_2, + Q(1 downto 0) => Q(1 downto 0), + SR(0) => SR(0), + clk => clk, + \out\ => \out\, + probe_out0(1 downto 0) => probe_out0(1 downto 0), + wr_probe_out(0) => wr_probe_out(0) + ); +\G_PROBE_OUT[0].wr_probe_out[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0200" + ) + port map ( + I0 => \G_PROBE_OUT[0].wr_probe_out[0]_i_2_n_0\, + I1 => \G_PROBE_OUT[0].wr_probe_out_reg[0]_0\, + I2 => \G_PROBE_OUT[0].wr_probe_out_reg[0]_1\, + I3 => \G_PROBE_OUT[0].wr_probe_out_reg[0]_2\, + O => \G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0\ + ); +\G_PROBE_OUT[0].wr_probe_out[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000004" + ) + port map ( + I0 => \G_PROBE_OUT[0].wr_probe_out[0]_i_6_n_0\, + I1 => s_daddr_o(8), + I2 => s_daddr_o(9), + I3 => s_daddr_o(0), + I4 => s_daddr_o(2), + I5 => s_daddr_o(3), + O => \G_PROBE_OUT[0].wr_probe_out[0]_i_2_n_0\ + ); +\G_PROBE_OUT[0].wr_probe_out[0]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => s_daddr_o(11), + I1 => s_daddr_o(10), + O => \G_PROBE_OUT[0].wr_probe_out[0]_i_6_n_0\ + ); +\G_PROBE_OUT[0].wr_probe_out_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0\, + Q => wr_probe_out(0), + R => '0' + ); +\G_PROBE_OUT[1].PROBE_OUT0_INST\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized0\ + port map ( + E(0) => Committ_2, + Q(0) => Q(0), + SR(0) => SR(0), + clk => clk, + \data_int_reg[0]_0\ => \G_PROBE_OUT[1].PROBE_OUT0_INST_n_1\, + \out\ => \out\, + probe_out1(0) => probe_out1(0), + wr_probe_out(0) => wr_probe_out(1) + ); +\G_PROBE_OUT[1].wr_probe_out[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFF7" + ) + port map ( + I0 => \^addr_count[1]_i_5\, + I1 => s_daddr_o(8), + I2 => s_daddr_o(6), + I3 => s_daddr_o(7), + O => \G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0\ + ); +\G_PROBE_OUT[1].wr_probe_out[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000004000000" + ) + port map ( + I0 => s_daddr_o(2), + I1 => s_daddr_o(0), + I2 => s_daddr_o(1), + I3 => s_dwe_o, + I4 => s_den_o, + I5 => s_daddr_o(16), + O => \G_PROBE_OUT[1].wr_probe_out[1]_i_2_n_0\ + ); +\G_PROBE_OUT[1].wr_probe_out[1]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00010000" + ) + port map ( + I0 => s_daddr_o(15), + I1 => s_daddr_o(14), + I2 => s_daddr_o(12), + I3 => s_daddr_o(13), + I4 => \G_PROBE_OUT[2].PROBE_OUT0_INST_n_32\, + O => \^addr_count[1]_i_5\ + ); +\G_PROBE_OUT[1].wr_probe_out_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \G_PROBE_OUT[1].wr_probe_out[1]_i_2_n_0\, + Q => wr_probe_out(1), + R => \G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0\ + ); +\G_PROBE_OUT[2].PROBE_OUT0_INST\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized1\ + port map ( + \Bus_Data_out_int_reg[15]_0\(15 downto 0) => Bus_Data_out_int(15 downto 0), + E(0) => \G_PROBE_OUT[2].wr_probe_out_reg\, + \Probe_out_reg[31]_0\(0) => Committ_2, + Q(15 downto 0) => Q(15 downto 0), + SR(0) => SR(0), + \addr_count[1]_i_5_0\ => \G_PROBE_OUT[2].PROBE_OUT0_INST_n_32\, + clk => clk, + internal_cnt_rst => internal_cnt_rst, + \out\ => \out\, + probe_out2(31 downto 0) => probe_out2(31 downto 0), + s_daddr_o(16 downto 0) => s_daddr_o(16 downto 0), + s_den_o => s_den_o, + s_dwe_o => s_dwe_o + ); +\G_PROBE_OUT[2].wr_probe_out[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000800000000" + ) + port map ( + I0 => s_dwe_o, + I1 => s_den_o, + I2 => s_daddr_o(16), + I3 => s_daddr_o(2), + I4 => s_daddr_o(0), + I5 => s_daddr_o(1), + O => \G_PROBE_OUT[2].wr_probe_out[2]_i_1_n_0\ + ); +\G_PROBE_OUT[2].wr_probe_out_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \G_PROBE_OUT[2].wr_probe_out[2]_i_1_n_0\, + Q => \G_PROBE_OUT[2].wr_probe_out_reg\, + R => \G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0\ + ); +\G_PROBE_OUT[3].PROBE_OUT0_INST\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized2\ + port map ( + D(1) => \G_PROBE_OUT[3].PROBE_OUT0_INST_n_2\, + D(0) => \G_PROBE_OUT[3].PROBE_OUT0_INST_n_3\, + \Probe_out_reg[1]_0\ => Committ_2, + Q(1 downto 0) => Q(1 downto 0), + SR(0) => SR(0), + clk => clk, + \out\ => \out\, + probe_out3(1 downto 0) => probe_out3(1 downto 0), + wr_probe_out(0) => wr_probe_out(3) + ); +\G_PROBE_OUT[3].wr_probe_out[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0008000000000000" + ) + port map ( + I0 => s_dwe_o, + I1 => s_den_o, + I2 => s_daddr_o(16), + I3 => s_daddr_o(2), + I4 => s_daddr_o(0), + I5 => s_daddr_o(1), + O => \G_PROBE_OUT[3].wr_probe_out[3]_i_1_n_0\ + ); +\G_PROBE_OUT[3].wr_probe_out_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \G_PROBE_OUT[3].wr_probe_out[3]_i_1_n_0\, + Q => wr_probe_out(3), + R => \G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0\ + ); +\G_PROBE_OUT[4].PROBE_OUT0_INST\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_one__parameterized3\ + port map ( + E(0) => wr_probe_out(4), + \Probe_out_reg[3]_0\ => Committ_2, + Q(3) => \G_PROBE_OUT[4].PROBE_OUT0_INST_n_4\, + Q(2) => \G_PROBE_OUT[4].PROBE_OUT0_INST_n_5\, + Q(1) => \G_PROBE_OUT[4].PROBE_OUT0_INST_n_6\, + Q(0) => \G_PROBE_OUT[4].PROBE_OUT0_INST_n_7\, + SR(0) => SR(0), + clk => clk, + \data_int_reg[3]_0\(3 downto 0) => Q(3 downto 0), + \out\ => \out\, + probe_out4(3 downto 0) => probe_out4(3 downto 0) + ); +\G_PROBE_OUT[4].wr_probe_out[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000004000000" + ) + port map ( + I0 => s_daddr_o(0), + I1 => s_daddr_o(2), + I2 => s_daddr_o(1), + I3 => s_dwe_o, + I4 => s_den_o, + I5 => s_daddr_o(16), + O => \G_PROBE_OUT[4].wr_probe_out[4]_i_1_n_0\ + ); +\G_PROBE_OUT[4].wr_probe_out_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \G_PROBE_OUT[4].wr_probe_out[4]_i_1_n_0\, + Q => wr_probe_out(4), + R => \G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0\ + ); +\Probe_out_reg_int[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \G_PROBE_OUT[4].PROBE_OUT0_INST_n_7\, + I1 => \^addr_p1_reg[2]_0\(2), + I2 => \Probe_out_reg_int[0]_i_2_n_0\, + O => probe_out_mem(0) + ); +\Probe_out_reg_int[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \G_PROBE_OUT[3].PROBE_OUT0_INST_n_3\, + I1 => Bus_Data_out_int(0), + I2 => \^addr_p1_reg[2]_0\(1), + I3 => \G_PROBE_OUT[1].PROBE_OUT0_INST_n_1\, + I4 => \^addr_p1_reg[2]_0\(0), + I5 => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_3\, + O => \Probe_out_reg_int[0]_i_2_n_0\ + ); +\Probe_out_reg_int[10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => \^addr_p1_reg[2]_0\(1), + I1 => \^addr_p1_reg[2]_0\(0), + I2 => Bus_Data_out_int(10), + O => \Probe_out_reg_int[10]_i_1_n_0\ + ); +\Probe_out_reg_int[11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => \^addr_p1_reg[2]_0\(1), + I1 => \^addr_p1_reg[2]_0\(0), + I2 => Bus_Data_out_int(11), + O => \Probe_out_reg_int[11]_i_1_n_0\ + ); +\Probe_out_reg_int[12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => \^addr_p1_reg[2]_0\(1), + I1 => \^addr_p1_reg[2]_0\(0), + I2 => Bus_Data_out_int(12), + O => \Probe_out_reg_int[12]_i_1_n_0\ + ); +\Probe_out_reg_int[13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => \^addr_p1_reg[2]_0\(1), + I1 => \^addr_p1_reg[2]_0\(0), + I2 => Bus_Data_out_int(13), + O => \Probe_out_reg_int[13]_i_1_n_0\ + ); +\Probe_out_reg_int[14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => \^addr_p1_reg[2]_0\(1), + I1 => \^addr_p1_reg[2]_0\(0), + I2 => Bus_Data_out_int(14), + O => \Probe_out_reg_int[14]_i_1_n_0\ + ); +\Probe_out_reg_int[15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => \^addr_p1_reg[2]_0\(1), + I1 => \^addr_p1_reg[2]_0\(0), + I2 => Bus_Data_out_int(15), + O => \Probe_out_reg_int[15]_i_1_n_0\ + ); +\Probe_out_reg_int[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \G_PROBE_OUT[4].PROBE_OUT0_INST_n_6\, + I1 => \^addr_p1_reg[2]_0\(2), + I2 => \Probe_out_reg_int[1]_i_2_n_0\, + O => probe_out_mem(1) + ); +\Probe_out_reg_int[1]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A0A0CFC0" + ) + port map ( + I0 => \G_PROBE_OUT[3].PROBE_OUT0_INST_n_2\, + I1 => Bus_Data_out_int(1), + I2 => \^addr_p1_reg[2]_0\(1), + I3 => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_2\, + I4 => \^addr_p1_reg[2]_0\(0), + O => \Probe_out_reg_int[1]_i_2_n_0\ + ); +\Probe_out_reg_int[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88B88888" + ) + port map ( + I0 => \G_PROBE_OUT[4].PROBE_OUT0_INST_n_5\, + I1 => \^addr_p1_reg[2]_0\(2), + I2 => \^addr_p1_reg[2]_0\(1), + I3 => \^addr_p1_reg[2]_0\(0), + I4 => Bus_Data_out_int(2), + O => probe_out_mem(2) + ); +\Probe_out_reg_int[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88B88888" + ) + port map ( + I0 => \G_PROBE_OUT[4].PROBE_OUT0_INST_n_4\, + I1 => \^addr_p1_reg[2]_0\(2), + I2 => \^addr_p1_reg[2]_0\(1), + I3 => \^addr_p1_reg[2]_0\(0), + I4 => Bus_Data_out_int(3), + O => probe_out_mem(3) + ); +\Probe_out_reg_int[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => \^addr_p1_reg[2]_0\(1), + I1 => \^addr_p1_reg[2]_0\(0), + I2 => Bus_Data_out_int(4), + O => \Probe_out_reg_int[4]_i_1_n_0\ + ); +\Probe_out_reg_int[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => \^addr_p1_reg[2]_0\(1), + I1 => \^addr_p1_reg[2]_0\(0), + I2 => Bus_Data_out_int(5), + O => \Probe_out_reg_int[5]_i_1_n_0\ + ); +\Probe_out_reg_int[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => \^addr_p1_reg[2]_0\(1), + I1 => \^addr_p1_reg[2]_0\(0), + I2 => Bus_Data_out_int(6), + O => \Probe_out_reg_int[6]_i_1_n_0\ + ); +\Probe_out_reg_int[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => \^addr_p1_reg[2]_0\(1), + I1 => \^addr_p1_reg[2]_0\(0), + I2 => Bus_Data_out_int(7), + O => \Probe_out_reg_int[7]_i_1_n_0\ + ); +\Probe_out_reg_int[8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => \^addr_p1_reg[2]_0\(1), + I1 => \^addr_p1_reg[2]_0\(0), + I2 => Bus_Data_out_int(8), + O => \Probe_out_reg_int[8]_i_1_n_0\ + ); +\Probe_out_reg_int[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => \^addr_p1_reg[2]_0\(1), + I1 => \^addr_p1_reg[2]_0\(0), + I2 => Bus_Data_out_int(9), + O => \Probe_out_reg_int[9]_i_1_n_0\ + ); +\Probe_out_reg_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => probe_out_mem(0), + Q => \Probe_out_reg_int_reg[3]_0\(0), + R => '0' + ); +\Probe_out_reg_int_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Probe_out_reg_int[10]_i_1_n_0\, + Q => \Probe_out_reg_int_reg[10]_0\, + R => \^addr_p1_reg[2]_0\(2) + ); +\Probe_out_reg_int_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Probe_out_reg_int[11]_i_1_n_0\, + Q => \Probe_out_reg_int_reg[11]_0\, + R => \^addr_p1_reg[2]_0\(2) + ); +\Probe_out_reg_int_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Probe_out_reg_int[12]_i_1_n_0\, + Q => \Probe_out_reg_int_reg[12]_0\, + R => \^addr_p1_reg[2]_0\(2) + ); +\Probe_out_reg_int_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Probe_out_reg_int[13]_i_1_n_0\, + Q => \Probe_out_reg_int_reg[13]_0\, + R => \^addr_p1_reg[2]_0\(2) + ); +\Probe_out_reg_int_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Probe_out_reg_int[14]_i_1_n_0\, + Q => \Probe_out_reg_int_reg[14]_0\, + R => \^addr_p1_reg[2]_0\(2) + ); +\Probe_out_reg_int_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Probe_out_reg_int[15]_i_1_n_0\, + Q => \Probe_out_reg_int_reg[15]_0\, + R => \^addr_p1_reg[2]_0\(2) + ); +\Probe_out_reg_int_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => probe_out_mem(1), + Q => \Probe_out_reg_int_reg[3]_0\(1), + R => '0' + ); +\Probe_out_reg_int_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => probe_out_mem(2), + Q => \Probe_out_reg_int_reg[3]_0\(2), + R => '0' + ); +\Probe_out_reg_int_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => probe_out_mem(3), + Q => \Probe_out_reg_int_reg[3]_0\(3), + R => '0' + ); +\Probe_out_reg_int_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Probe_out_reg_int[4]_i_1_n_0\, + Q => \Probe_out_reg_int_reg[4]_0\, + R => \^addr_p1_reg[2]_0\(2) + ); +\Probe_out_reg_int_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Probe_out_reg_int[5]_i_1_n_0\, + Q => \Probe_out_reg_int_reg[5]_0\, + R => \^addr_p1_reg[2]_0\(2) + ); +\Probe_out_reg_int_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Probe_out_reg_int[6]_i_1_n_0\, + Q => \Probe_out_reg_int_reg[6]_0\, + R => \^addr_p1_reg[2]_0\(2) + ); +\Probe_out_reg_int_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Probe_out_reg_int[7]_i_1_n_0\, + Q => \Probe_out_reg_int_reg[7]_0\, + R => \^addr_p1_reg[2]_0\(2) + ); +\Probe_out_reg_int_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Probe_out_reg_int[8]_i_1_n_0\, + Q => \Probe_out_reg_int_reg[8]_0\, + R => \^addr_p1_reg[2]_0\(2) + ); +\Probe_out_reg_int_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => \Probe_out_reg_int[9]_i_1_n_0\, + Q => \Probe_out_reg_int_reg[9]_0\, + R => \^addr_p1_reg[2]_0\(2) + ); +\addr_p1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => s_daddr_o(0), + Q => \^addr_p1_reg[2]_0\(0), + R => '0' + ); +\addr_p1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => s_daddr_o(1), + Q => \^addr_p1_reg[2]_0\(1), + R => '0' + ); +\addr_p1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => \out\, + CE => '1', + D => s_daddr_o(2), + Q => \^addr_p1_reg[2]_0\(2), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio is + port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in4 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in5 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in6 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in7 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in8 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in9 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in10 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in11 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in12 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in13 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in14 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in15 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in16 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in17 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in18 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in19 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in20 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in21 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in22 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in23 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in24 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in25 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in26 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in27 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in28 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in29 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in30 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in31 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in32 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in33 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in34 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in35 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in36 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in37 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in38 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in39 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in40 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in41 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in42 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in43 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in44 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in45 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in46 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in47 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in48 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in49 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in50 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in51 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in52 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in53 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in54 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in55 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in56 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in57 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in58 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in59 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in60 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in61 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in62 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in63 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in64 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in65 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in66 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in67 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in68 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in69 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in70 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in71 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in72 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in73 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in74 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in75 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in76 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in77 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in78 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in79 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in80 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in81 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in82 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in83 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in84 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in85 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in86 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in87 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in88 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in89 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in90 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in91 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in92 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in93 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in94 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in95 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in96 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in97 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in98 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in99 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in100 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in101 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in102 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in103 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in104 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in105 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in106 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in107 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in108 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in109 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in110 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in111 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in112 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in113 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in114 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in115 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in116 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in117 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in118 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in119 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in120 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in121 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in122 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in123 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in124 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in125 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in126 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in127 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in128 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in129 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in130 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in131 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in132 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in133 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in134 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in135 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in136 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in137 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in138 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in139 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in140 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in141 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in142 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in143 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in144 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in145 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in146 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in147 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in148 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in149 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in150 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in151 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in152 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in153 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in154 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in155 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in156 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in157 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in158 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in159 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in160 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in161 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in162 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in163 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in164 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in165 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in166 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in167 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in168 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in169 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in170 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in171 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in172 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in173 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in174 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in175 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in176 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in177 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in178 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in179 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in180 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in181 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in182 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in183 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in184 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in185 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in186 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in187 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in188 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in189 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in190 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in191 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in192 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in193 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in194 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in195 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in196 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in197 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in198 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in199 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in200 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in201 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in202 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in203 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in204 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in205 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in206 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in207 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in208 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in209 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in210 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in211 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in212 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in213 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in214 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in215 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in216 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in217 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in218 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in219 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in220 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in221 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in222 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in223 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in224 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in225 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in226 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in227 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in228 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in229 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in230 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in231 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in232 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in233 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in234 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in235 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in236 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in237 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in238 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in239 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in240 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in241 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in242 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in243 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in244 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in245 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in246 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in247 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in248 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in249 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in250 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in251 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in252 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in253 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in254 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in255 : in STD_LOGIC_VECTOR ( 0 to 0 ); + sl_iport0 : in STD_LOGIC_VECTOR ( 36 downto 0 ); + sl_oport0 : out STD_LOGIC_VECTOR ( 16 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out13 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out17 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out18 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out19 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out20 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out21 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out22 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out23 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out24 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out25 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out26 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out27 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out28 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out29 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out30 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out31 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out32 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out33 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out34 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out35 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out36 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out37 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out38 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out39 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out40 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out41 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out42 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out43 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out44 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out45 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out46 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out47 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out48 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out49 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out50 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out51 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out52 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out53 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out54 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out55 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out56 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out57 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out58 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out59 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out60 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out61 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out62 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out63 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out64 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out65 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out66 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out67 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out68 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out69 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out70 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out71 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out72 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out73 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out74 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out75 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out76 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out77 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out78 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out79 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out80 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out81 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out82 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out83 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out84 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out85 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out86 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out87 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out88 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out89 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out90 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out91 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out92 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out93 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out94 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out95 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out96 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out97 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out98 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out99 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out100 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out101 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out102 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out103 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out104 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out105 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out106 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out107 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out108 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out109 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out110 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out111 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out112 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out113 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out114 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out115 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out116 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out117 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out118 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out119 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out120 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out121 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out122 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out123 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out124 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out125 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out126 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out127 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out128 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out129 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out130 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out131 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out132 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out133 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out134 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out135 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out136 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out137 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out138 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out139 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out140 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out141 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out142 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out143 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out144 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out145 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out146 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out147 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out148 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out149 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out150 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out151 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out152 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out153 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out154 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out155 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out156 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out157 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out158 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out159 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out160 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out161 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out162 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out163 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out164 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out165 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out166 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out167 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out168 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out169 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out170 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out171 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out172 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out173 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out174 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out175 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out176 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out177 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out178 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out179 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out180 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out181 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out182 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out183 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out184 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out185 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out186 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out187 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out188 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out189 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out190 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out191 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out192 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out193 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out194 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out195 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out196 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out197 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out198 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out199 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out200 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out201 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out202 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out203 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out204 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out205 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out206 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out207 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out208 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out209 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out210 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out211 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out212 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out213 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out214 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out215 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out216 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out217 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out218 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out219 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out220 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out221 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out222 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out223 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out224 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out225 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out226 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out227 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out228 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out229 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out230 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out231 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out232 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out233 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out234 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out235 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out236 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out237 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out238 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out239 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out240 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out241 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out242 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out243 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out244 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out245 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out246 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out247 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out248 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out249 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out250 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out251 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out252 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out253 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out254 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out255 : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute C_BUILD_REVISION : integer; + attribute C_BUILD_REVISION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 0; + attribute C_BUS_ADDR_WIDTH : integer; + attribute C_BUS_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 17; + attribute C_BUS_DATA_WIDTH : integer; + attribute C_BUS_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 16; + attribute C_CORE_INFO1 : string; + attribute C_CORE_INFO1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_CORE_INFO2 : string; + attribute C_CORE_INFO2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_CORE_MAJOR_VER : integer; + attribute C_CORE_MAJOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 2; + attribute C_CORE_MINOR_ALPHA_VER : integer; + attribute C_CORE_MINOR_ALPHA_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 97; + attribute C_CORE_MINOR_VER : integer; + attribute C_CORE_MINOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 0; + attribute C_CORE_TYPE : integer; + attribute C_CORE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 2; + attribute C_CSE_DRV_VER : integer; + attribute C_CSE_DRV_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_EN_PROBE_IN_ACTIVITY : integer; + attribute C_EN_PROBE_IN_ACTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 0; + attribute C_EN_SYNCHRONIZATION : integer; + attribute C_EN_SYNCHRONIZATION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_MAJOR_VERSION : integer; + attribute C_MAJOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 2013; + attribute C_MAX_NUM_PROBE : integer; + attribute C_MAX_NUM_PROBE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 256; + attribute C_MAX_WIDTH_PER_PROBE : integer; + attribute C_MAX_WIDTH_PER_PROBE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 256; + attribute C_MINOR_VERSION : integer; + attribute C_MINOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_NEXT_SLAVE : integer; + attribute C_NEXT_SLAVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 0; + attribute C_NUM_PROBE_IN : integer; + attribute C_NUM_PROBE_IN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 0; + attribute C_NUM_PROBE_OUT : integer; + attribute C_NUM_PROBE_OUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 5; + attribute C_PIPE_IFACE : integer; + attribute C_PIPE_IFACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 0; + attribute C_PROBE_IN0_WIDTH : integer; + attribute C_PROBE_IN0_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN100_WIDTH : integer; + attribute C_PROBE_IN100_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN101_WIDTH : integer; + attribute C_PROBE_IN101_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN102_WIDTH : integer; + attribute C_PROBE_IN102_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN103_WIDTH : integer; + attribute C_PROBE_IN103_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN104_WIDTH : integer; + attribute C_PROBE_IN104_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN105_WIDTH : integer; + attribute C_PROBE_IN105_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN106_WIDTH : integer; + attribute C_PROBE_IN106_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN107_WIDTH : integer; + attribute C_PROBE_IN107_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN108_WIDTH : integer; + attribute C_PROBE_IN108_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN109_WIDTH : integer; + attribute C_PROBE_IN109_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN10_WIDTH : integer; + attribute C_PROBE_IN10_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN110_WIDTH : integer; + attribute C_PROBE_IN110_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN111_WIDTH : integer; + attribute C_PROBE_IN111_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN112_WIDTH : integer; + attribute C_PROBE_IN112_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN113_WIDTH : integer; + attribute C_PROBE_IN113_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN114_WIDTH : integer; + attribute C_PROBE_IN114_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN115_WIDTH : integer; + attribute C_PROBE_IN115_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN116_WIDTH : integer; + attribute C_PROBE_IN116_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN117_WIDTH : integer; + attribute C_PROBE_IN117_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN118_WIDTH : integer; + attribute C_PROBE_IN118_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN119_WIDTH : integer; + attribute C_PROBE_IN119_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN11_WIDTH : integer; + attribute C_PROBE_IN11_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN120_WIDTH : integer; + attribute C_PROBE_IN120_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN121_WIDTH : integer; + attribute C_PROBE_IN121_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN122_WIDTH : integer; + attribute C_PROBE_IN122_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN123_WIDTH : integer; + attribute C_PROBE_IN123_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN124_WIDTH : integer; + attribute C_PROBE_IN124_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN125_WIDTH : integer; + attribute C_PROBE_IN125_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN126_WIDTH : integer; + attribute C_PROBE_IN126_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN127_WIDTH : integer; + attribute C_PROBE_IN127_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN128_WIDTH : integer; + attribute C_PROBE_IN128_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN129_WIDTH : integer; + attribute C_PROBE_IN129_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN12_WIDTH : integer; + attribute C_PROBE_IN12_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN130_WIDTH : integer; + attribute C_PROBE_IN130_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN131_WIDTH : integer; + attribute C_PROBE_IN131_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN132_WIDTH : integer; + attribute C_PROBE_IN132_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN133_WIDTH : integer; + attribute C_PROBE_IN133_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN134_WIDTH : integer; + attribute C_PROBE_IN134_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN135_WIDTH : integer; + attribute C_PROBE_IN135_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN136_WIDTH : integer; + attribute C_PROBE_IN136_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN137_WIDTH : integer; + attribute C_PROBE_IN137_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN138_WIDTH : integer; + attribute C_PROBE_IN138_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN139_WIDTH : integer; + attribute C_PROBE_IN139_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN13_WIDTH : integer; + attribute C_PROBE_IN13_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN140_WIDTH : integer; + attribute C_PROBE_IN140_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN141_WIDTH : integer; + attribute C_PROBE_IN141_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN142_WIDTH : integer; + attribute C_PROBE_IN142_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN143_WIDTH : integer; + attribute C_PROBE_IN143_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN144_WIDTH : integer; + attribute C_PROBE_IN144_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN145_WIDTH : integer; + attribute C_PROBE_IN145_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN146_WIDTH : integer; + attribute C_PROBE_IN146_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN147_WIDTH : integer; + attribute C_PROBE_IN147_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN148_WIDTH : integer; + attribute C_PROBE_IN148_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN149_WIDTH : integer; + attribute C_PROBE_IN149_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN14_WIDTH : integer; + attribute C_PROBE_IN14_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN150_WIDTH : integer; + attribute C_PROBE_IN150_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN151_WIDTH : integer; + attribute C_PROBE_IN151_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN152_WIDTH : integer; + attribute C_PROBE_IN152_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN153_WIDTH : integer; + attribute C_PROBE_IN153_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN154_WIDTH : integer; + attribute C_PROBE_IN154_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN155_WIDTH : integer; + attribute C_PROBE_IN155_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN156_WIDTH : integer; + attribute C_PROBE_IN156_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN157_WIDTH : integer; + attribute C_PROBE_IN157_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN158_WIDTH : integer; + attribute C_PROBE_IN158_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN159_WIDTH : integer; + attribute C_PROBE_IN159_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN15_WIDTH : integer; + attribute C_PROBE_IN15_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN160_WIDTH : integer; + attribute C_PROBE_IN160_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN161_WIDTH : integer; + attribute C_PROBE_IN161_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN162_WIDTH : integer; + attribute C_PROBE_IN162_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN163_WIDTH : integer; + attribute C_PROBE_IN163_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN164_WIDTH : integer; + attribute C_PROBE_IN164_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN165_WIDTH : integer; + attribute C_PROBE_IN165_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN166_WIDTH : integer; + attribute C_PROBE_IN166_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN167_WIDTH : integer; + attribute C_PROBE_IN167_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN168_WIDTH : integer; + attribute C_PROBE_IN168_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN169_WIDTH : integer; + attribute C_PROBE_IN169_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN16_WIDTH : integer; + attribute C_PROBE_IN16_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN170_WIDTH : integer; + attribute C_PROBE_IN170_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN171_WIDTH : integer; + attribute C_PROBE_IN171_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN172_WIDTH : integer; + attribute C_PROBE_IN172_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN173_WIDTH : integer; + attribute C_PROBE_IN173_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN174_WIDTH : integer; + attribute C_PROBE_IN174_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN175_WIDTH : integer; + attribute C_PROBE_IN175_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN176_WIDTH : integer; + attribute C_PROBE_IN176_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN177_WIDTH : integer; + attribute C_PROBE_IN177_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN178_WIDTH : integer; + attribute C_PROBE_IN178_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN179_WIDTH : integer; + attribute C_PROBE_IN179_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN17_WIDTH : integer; + attribute C_PROBE_IN17_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN180_WIDTH : integer; + attribute C_PROBE_IN180_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN181_WIDTH : integer; + attribute C_PROBE_IN181_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN182_WIDTH : integer; + attribute C_PROBE_IN182_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN183_WIDTH : integer; + attribute C_PROBE_IN183_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN184_WIDTH : integer; + attribute C_PROBE_IN184_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN185_WIDTH : integer; + attribute C_PROBE_IN185_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN186_WIDTH : integer; + attribute C_PROBE_IN186_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN187_WIDTH : integer; + attribute C_PROBE_IN187_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN188_WIDTH : integer; + attribute C_PROBE_IN188_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN189_WIDTH : integer; + attribute C_PROBE_IN189_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN18_WIDTH : integer; + attribute C_PROBE_IN18_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN190_WIDTH : integer; + attribute C_PROBE_IN190_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN191_WIDTH : integer; + attribute C_PROBE_IN191_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN192_WIDTH : integer; + attribute C_PROBE_IN192_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN193_WIDTH : integer; + attribute C_PROBE_IN193_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN194_WIDTH : integer; + attribute C_PROBE_IN194_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN195_WIDTH : integer; + attribute C_PROBE_IN195_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN196_WIDTH : integer; + attribute C_PROBE_IN196_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN197_WIDTH : integer; + attribute C_PROBE_IN197_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN198_WIDTH : integer; + attribute C_PROBE_IN198_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN199_WIDTH : integer; + attribute C_PROBE_IN199_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN19_WIDTH : integer; + attribute C_PROBE_IN19_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN1_WIDTH : integer; + attribute C_PROBE_IN1_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN200_WIDTH : integer; + attribute C_PROBE_IN200_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN201_WIDTH : integer; + attribute C_PROBE_IN201_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN202_WIDTH : integer; + attribute C_PROBE_IN202_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN203_WIDTH : integer; + attribute C_PROBE_IN203_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN204_WIDTH : integer; + attribute C_PROBE_IN204_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN205_WIDTH : integer; + attribute C_PROBE_IN205_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN206_WIDTH : integer; + attribute C_PROBE_IN206_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN207_WIDTH : integer; + attribute C_PROBE_IN207_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN208_WIDTH : integer; + attribute C_PROBE_IN208_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN209_WIDTH : integer; + attribute C_PROBE_IN209_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN20_WIDTH : integer; + attribute C_PROBE_IN20_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN210_WIDTH : integer; + attribute C_PROBE_IN210_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN211_WIDTH : integer; + attribute C_PROBE_IN211_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN212_WIDTH : integer; + attribute C_PROBE_IN212_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN213_WIDTH : integer; + attribute C_PROBE_IN213_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN214_WIDTH : integer; + attribute C_PROBE_IN214_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN215_WIDTH : integer; + attribute C_PROBE_IN215_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN216_WIDTH : integer; + attribute C_PROBE_IN216_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN217_WIDTH : integer; + attribute C_PROBE_IN217_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN218_WIDTH : integer; + attribute C_PROBE_IN218_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN219_WIDTH : integer; + attribute C_PROBE_IN219_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN21_WIDTH : integer; + attribute C_PROBE_IN21_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN220_WIDTH : integer; + attribute C_PROBE_IN220_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN221_WIDTH : integer; + attribute C_PROBE_IN221_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN222_WIDTH : integer; + attribute C_PROBE_IN222_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN223_WIDTH : integer; + attribute C_PROBE_IN223_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN224_WIDTH : integer; + attribute C_PROBE_IN224_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN225_WIDTH : integer; + attribute C_PROBE_IN225_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN226_WIDTH : integer; + attribute C_PROBE_IN226_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN227_WIDTH : integer; + attribute C_PROBE_IN227_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN228_WIDTH : integer; + attribute C_PROBE_IN228_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN229_WIDTH : integer; + attribute C_PROBE_IN229_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN22_WIDTH : integer; + attribute C_PROBE_IN22_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN230_WIDTH : integer; + attribute C_PROBE_IN230_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN231_WIDTH : integer; + attribute C_PROBE_IN231_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN232_WIDTH : integer; + attribute C_PROBE_IN232_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN233_WIDTH : integer; + attribute C_PROBE_IN233_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN234_WIDTH : integer; + attribute C_PROBE_IN234_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN235_WIDTH : integer; + attribute C_PROBE_IN235_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN236_WIDTH : integer; + attribute C_PROBE_IN236_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN237_WIDTH : integer; + attribute C_PROBE_IN237_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN238_WIDTH : integer; + attribute C_PROBE_IN238_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN239_WIDTH : integer; + attribute C_PROBE_IN239_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN23_WIDTH : integer; + attribute C_PROBE_IN23_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN240_WIDTH : integer; + attribute C_PROBE_IN240_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN241_WIDTH : integer; + attribute C_PROBE_IN241_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN242_WIDTH : integer; + attribute C_PROBE_IN242_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN243_WIDTH : integer; + attribute C_PROBE_IN243_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN244_WIDTH : integer; + attribute C_PROBE_IN244_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN245_WIDTH : integer; + attribute C_PROBE_IN245_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN246_WIDTH : integer; + attribute C_PROBE_IN246_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN247_WIDTH : integer; + attribute C_PROBE_IN247_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN248_WIDTH : integer; + attribute C_PROBE_IN248_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN249_WIDTH : integer; + attribute C_PROBE_IN249_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN24_WIDTH : integer; + attribute C_PROBE_IN24_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN250_WIDTH : integer; + attribute C_PROBE_IN250_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN251_WIDTH : integer; + attribute C_PROBE_IN251_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN252_WIDTH : integer; + attribute C_PROBE_IN252_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN253_WIDTH : integer; + attribute C_PROBE_IN253_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN254_WIDTH : integer; + attribute C_PROBE_IN254_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN255_WIDTH : integer; + attribute C_PROBE_IN255_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN25_WIDTH : integer; + attribute C_PROBE_IN25_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN26_WIDTH : integer; + attribute C_PROBE_IN26_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN27_WIDTH : integer; + attribute C_PROBE_IN27_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN28_WIDTH : integer; + attribute C_PROBE_IN28_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN29_WIDTH : integer; + attribute C_PROBE_IN29_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN2_WIDTH : integer; + attribute C_PROBE_IN2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN30_WIDTH : integer; + attribute C_PROBE_IN30_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN31_WIDTH : integer; + attribute C_PROBE_IN31_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN32_WIDTH : integer; + attribute C_PROBE_IN32_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN33_WIDTH : integer; + attribute C_PROBE_IN33_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN34_WIDTH : integer; + attribute C_PROBE_IN34_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN35_WIDTH : integer; + attribute C_PROBE_IN35_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN36_WIDTH : integer; + attribute C_PROBE_IN36_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN37_WIDTH : integer; + attribute C_PROBE_IN37_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN38_WIDTH : integer; + attribute C_PROBE_IN38_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN39_WIDTH : integer; + attribute C_PROBE_IN39_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN3_WIDTH : integer; + attribute C_PROBE_IN3_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN40_WIDTH : integer; + attribute C_PROBE_IN40_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN41_WIDTH : integer; + attribute C_PROBE_IN41_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN42_WIDTH : integer; + attribute C_PROBE_IN42_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN43_WIDTH : integer; + attribute C_PROBE_IN43_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN44_WIDTH : integer; + attribute C_PROBE_IN44_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN45_WIDTH : integer; + attribute C_PROBE_IN45_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN46_WIDTH : integer; + attribute C_PROBE_IN46_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN47_WIDTH : integer; + attribute C_PROBE_IN47_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN48_WIDTH : integer; + attribute C_PROBE_IN48_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN49_WIDTH : integer; + attribute C_PROBE_IN49_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN4_WIDTH : integer; + attribute C_PROBE_IN4_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN50_WIDTH : integer; + attribute C_PROBE_IN50_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN51_WIDTH : integer; + attribute C_PROBE_IN51_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN52_WIDTH : integer; + attribute C_PROBE_IN52_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN53_WIDTH : integer; + attribute C_PROBE_IN53_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN54_WIDTH : integer; + attribute C_PROBE_IN54_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN55_WIDTH : integer; + attribute C_PROBE_IN55_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN56_WIDTH : integer; + attribute C_PROBE_IN56_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN57_WIDTH : integer; + attribute C_PROBE_IN57_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN58_WIDTH : integer; + attribute C_PROBE_IN58_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN59_WIDTH : integer; + attribute C_PROBE_IN59_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN5_WIDTH : integer; + attribute C_PROBE_IN5_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN60_WIDTH : integer; + attribute C_PROBE_IN60_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN61_WIDTH : integer; + attribute C_PROBE_IN61_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN62_WIDTH : integer; + attribute C_PROBE_IN62_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN63_WIDTH : integer; + attribute C_PROBE_IN63_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN64_WIDTH : integer; + attribute C_PROBE_IN64_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN65_WIDTH : integer; + attribute C_PROBE_IN65_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN66_WIDTH : integer; + attribute C_PROBE_IN66_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN67_WIDTH : integer; + attribute C_PROBE_IN67_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN68_WIDTH : integer; + attribute C_PROBE_IN68_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN69_WIDTH : integer; + attribute C_PROBE_IN69_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN6_WIDTH : integer; + attribute C_PROBE_IN6_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN70_WIDTH : integer; + attribute C_PROBE_IN70_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN71_WIDTH : integer; + attribute C_PROBE_IN71_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN72_WIDTH : integer; + attribute C_PROBE_IN72_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN73_WIDTH : integer; + attribute C_PROBE_IN73_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN74_WIDTH : integer; + attribute C_PROBE_IN74_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN75_WIDTH : integer; + attribute C_PROBE_IN75_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN76_WIDTH : integer; + attribute C_PROBE_IN76_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN77_WIDTH : integer; + attribute C_PROBE_IN77_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN78_WIDTH : integer; + attribute C_PROBE_IN78_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN79_WIDTH : integer; + attribute C_PROBE_IN79_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN7_WIDTH : integer; + attribute C_PROBE_IN7_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN80_WIDTH : integer; + attribute C_PROBE_IN80_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN81_WIDTH : integer; + attribute C_PROBE_IN81_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN82_WIDTH : integer; + attribute C_PROBE_IN82_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN83_WIDTH : integer; + attribute C_PROBE_IN83_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN84_WIDTH : integer; + attribute C_PROBE_IN84_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN85_WIDTH : integer; + attribute C_PROBE_IN85_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN86_WIDTH : integer; + attribute C_PROBE_IN86_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN87_WIDTH : integer; + attribute C_PROBE_IN87_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN88_WIDTH : integer; + attribute C_PROBE_IN88_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN89_WIDTH : integer; + attribute C_PROBE_IN89_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN8_WIDTH : integer; + attribute C_PROBE_IN8_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN90_WIDTH : integer; + attribute C_PROBE_IN90_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN91_WIDTH : integer; + attribute C_PROBE_IN91_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN92_WIDTH : integer; + attribute C_PROBE_IN92_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN93_WIDTH : integer; + attribute C_PROBE_IN93_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN94_WIDTH : integer; + attribute C_PROBE_IN94_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN95_WIDTH : integer; + attribute C_PROBE_IN95_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN96_WIDTH : integer; + attribute C_PROBE_IN96_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN97_WIDTH : integer; + attribute C_PROBE_IN97_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN98_WIDTH : integer; + attribute C_PROBE_IN98_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN99_WIDTH : integer; + attribute C_PROBE_IN99_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_IN9_WIDTH : integer; + attribute C_PROBE_IN9_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT0_INIT_VAL : string; + attribute C_PROBE_OUT0_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "2'b10"; + attribute C_PROBE_OUT0_WIDTH : integer; + attribute C_PROBE_OUT0_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 2; + attribute C_PROBE_OUT100_INIT_VAL : string; + attribute C_PROBE_OUT100_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT100_WIDTH : integer; + attribute C_PROBE_OUT100_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT101_INIT_VAL : string; + attribute C_PROBE_OUT101_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT101_WIDTH : integer; + attribute C_PROBE_OUT101_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT102_INIT_VAL : string; + attribute C_PROBE_OUT102_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT102_WIDTH : integer; + attribute C_PROBE_OUT102_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT103_INIT_VAL : string; + attribute C_PROBE_OUT103_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT103_WIDTH : integer; + attribute C_PROBE_OUT103_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT104_INIT_VAL : string; + attribute C_PROBE_OUT104_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT104_WIDTH : integer; + attribute C_PROBE_OUT104_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT105_INIT_VAL : string; + attribute C_PROBE_OUT105_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT105_WIDTH : integer; + attribute C_PROBE_OUT105_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT106_INIT_VAL : string; + attribute C_PROBE_OUT106_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT106_WIDTH : integer; + attribute C_PROBE_OUT106_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT107_INIT_VAL : string; + attribute C_PROBE_OUT107_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT107_WIDTH : integer; + attribute C_PROBE_OUT107_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT108_INIT_VAL : string; + attribute C_PROBE_OUT108_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT108_WIDTH : integer; + attribute C_PROBE_OUT108_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT109_INIT_VAL : string; + attribute C_PROBE_OUT109_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT109_WIDTH : integer; + attribute C_PROBE_OUT109_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT10_INIT_VAL : string; + attribute C_PROBE_OUT10_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT10_WIDTH : integer; + attribute C_PROBE_OUT10_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT110_INIT_VAL : string; + attribute C_PROBE_OUT110_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT110_WIDTH : integer; + attribute C_PROBE_OUT110_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT111_INIT_VAL : string; + attribute C_PROBE_OUT111_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT111_WIDTH : integer; + attribute C_PROBE_OUT111_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT112_INIT_VAL : string; + attribute C_PROBE_OUT112_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT112_WIDTH : integer; + attribute C_PROBE_OUT112_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT113_INIT_VAL : string; + attribute C_PROBE_OUT113_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT113_WIDTH : integer; + attribute C_PROBE_OUT113_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT114_INIT_VAL : string; + attribute C_PROBE_OUT114_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT114_WIDTH : integer; + attribute C_PROBE_OUT114_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT115_INIT_VAL : string; + attribute C_PROBE_OUT115_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT115_WIDTH : integer; + attribute C_PROBE_OUT115_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT116_INIT_VAL : string; + attribute C_PROBE_OUT116_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT116_WIDTH : integer; + attribute C_PROBE_OUT116_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT117_INIT_VAL : string; + attribute C_PROBE_OUT117_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT117_WIDTH : integer; + attribute C_PROBE_OUT117_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT118_INIT_VAL : string; + attribute C_PROBE_OUT118_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT118_WIDTH : integer; + attribute C_PROBE_OUT118_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT119_INIT_VAL : string; + attribute C_PROBE_OUT119_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT119_WIDTH : integer; + attribute C_PROBE_OUT119_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT11_INIT_VAL : string; + attribute C_PROBE_OUT11_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT11_WIDTH : integer; + attribute C_PROBE_OUT11_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT120_INIT_VAL : string; + attribute C_PROBE_OUT120_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT120_WIDTH : integer; + attribute C_PROBE_OUT120_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT121_INIT_VAL : string; + attribute C_PROBE_OUT121_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT121_WIDTH : integer; + attribute C_PROBE_OUT121_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT122_INIT_VAL : string; + attribute C_PROBE_OUT122_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT122_WIDTH : integer; + attribute C_PROBE_OUT122_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT123_INIT_VAL : string; + attribute C_PROBE_OUT123_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT123_WIDTH : integer; + attribute C_PROBE_OUT123_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT124_INIT_VAL : string; + attribute C_PROBE_OUT124_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT124_WIDTH : integer; + attribute C_PROBE_OUT124_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT125_INIT_VAL : string; + attribute C_PROBE_OUT125_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT125_WIDTH : integer; + attribute C_PROBE_OUT125_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT126_INIT_VAL : string; + attribute C_PROBE_OUT126_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT126_WIDTH : integer; + attribute C_PROBE_OUT126_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT127_INIT_VAL : string; + attribute C_PROBE_OUT127_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT127_WIDTH : integer; + attribute C_PROBE_OUT127_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT128_INIT_VAL : string; + attribute C_PROBE_OUT128_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT128_WIDTH : integer; + attribute C_PROBE_OUT128_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT129_INIT_VAL : string; + attribute C_PROBE_OUT129_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT129_WIDTH : integer; + attribute C_PROBE_OUT129_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT12_INIT_VAL : string; + attribute C_PROBE_OUT12_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT12_WIDTH : integer; + attribute C_PROBE_OUT12_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT130_INIT_VAL : string; + attribute C_PROBE_OUT130_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT130_WIDTH : integer; + attribute C_PROBE_OUT130_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT131_INIT_VAL : string; + attribute C_PROBE_OUT131_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT131_WIDTH : integer; + attribute C_PROBE_OUT131_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT132_INIT_VAL : string; + attribute C_PROBE_OUT132_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT132_WIDTH : integer; + attribute C_PROBE_OUT132_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT133_INIT_VAL : string; + attribute C_PROBE_OUT133_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT133_WIDTH : integer; + attribute C_PROBE_OUT133_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT134_INIT_VAL : string; + attribute C_PROBE_OUT134_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT134_WIDTH : integer; + attribute C_PROBE_OUT134_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT135_INIT_VAL : string; + attribute C_PROBE_OUT135_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT135_WIDTH : integer; + attribute C_PROBE_OUT135_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT136_INIT_VAL : string; + attribute C_PROBE_OUT136_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT136_WIDTH : integer; + attribute C_PROBE_OUT136_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT137_INIT_VAL : string; + attribute C_PROBE_OUT137_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT137_WIDTH : integer; + attribute C_PROBE_OUT137_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT138_INIT_VAL : string; + attribute C_PROBE_OUT138_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT138_WIDTH : integer; + attribute C_PROBE_OUT138_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT139_INIT_VAL : string; + attribute C_PROBE_OUT139_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT139_WIDTH : integer; + attribute C_PROBE_OUT139_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT13_INIT_VAL : string; + attribute C_PROBE_OUT13_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT13_WIDTH : integer; + attribute C_PROBE_OUT13_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT140_INIT_VAL : string; + attribute C_PROBE_OUT140_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT140_WIDTH : integer; + attribute C_PROBE_OUT140_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT141_INIT_VAL : string; + attribute C_PROBE_OUT141_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT141_WIDTH : integer; + attribute C_PROBE_OUT141_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT142_INIT_VAL : string; + attribute C_PROBE_OUT142_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT142_WIDTH : integer; + attribute C_PROBE_OUT142_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT143_INIT_VAL : string; + attribute C_PROBE_OUT143_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT143_WIDTH : integer; + attribute C_PROBE_OUT143_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT144_INIT_VAL : string; + attribute C_PROBE_OUT144_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT144_WIDTH : integer; + attribute C_PROBE_OUT144_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT145_INIT_VAL : string; + attribute C_PROBE_OUT145_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT145_WIDTH : integer; + attribute C_PROBE_OUT145_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT146_INIT_VAL : string; + attribute C_PROBE_OUT146_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT146_WIDTH : integer; + attribute C_PROBE_OUT146_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT147_INIT_VAL : string; + attribute C_PROBE_OUT147_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT147_WIDTH : integer; + attribute C_PROBE_OUT147_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT148_INIT_VAL : string; + attribute C_PROBE_OUT148_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT148_WIDTH : integer; + attribute C_PROBE_OUT148_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT149_INIT_VAL : string; + attribute C_PROBE_OUT149_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT149_WIDTH : integer; + attribute C_PROBE_OUT149_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT14_INIT_VAL : string; + attribute C_PROBE_OUT14_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT14_WIDTH : integer; + attribute C_PROBE_OUT14_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT150_INIT_VAL : string; + attribute C_PROBE_OUT150_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT150_WIDTH : integer; + attribute C_PROBE_OUT150_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT151_INIT_VAL : string; + attribute C_PROBE_OUT151_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT151_WIDTH : integer; + attribute C_PROBE_OUT151_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT152_INIT_VAL : string; + attribute C_PROBE_OUT152_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT152_WIDTH : integer; + attribute C_PROBE_OUT152_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT153_INIT_VAL : string; + attribute C_PROBE_OUT153_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT153_WIDTH : integer; + attribute C_PROBE_OUT153_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT154_INIT_VAL : string; + attribute C_PROBE_OUT154_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT154_WIDTH : integer; + attribute C_PROBE_OUT154_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT155_INIT_VAL : string; + attribute C_PROBE_OUT155_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT155_WIDTH : integer; + attribute C_PROBE_OUT155_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT156_INIT_VAL : string; + attribute C_PROBE_OUT156_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT156_WIDTH : integer; + attribute C_PROBE_OUT156_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT157_INIT_VAL : string; + attribute C_PROBE_OUT157_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT157_WIDTH : integer; + attribute C_PROBE_OUT157_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT158_INIT_VAL : string; + attribute C_PROBE_OUT158_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT158_WIDTH : integer; + attribute C_PROBE_OUT158_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT159_INIT_VAL : string; + attribute C_PROBE_OUT159_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT159_WIDTH : integer; + attribute C_PROBE_OUT159_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT15_INIT_VAL : string; + attribute C_PROBE_OUT15_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT15_WIDTH : integer; + attribute C_PROBE_OUT15_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT160_INIT_VAL : string; + attribute C_PROBE_OUT160_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT160_WIDTH : integer; + attribute C_PROBE_OUT160_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT161_INIT_VAL : string; + attribute C_PROBE_OUT161_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT161_WIDTH : integer; + attribute C_PROBE_OUT161_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT162_INIT_VAL : string; + attribute C_PROBE_OUT162_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT162_WIDTH : integer; + attribute C_PROBE_OUT162_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT163_INIT_VAL : string; + attribute C_PROBE_OUT163_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT163_WIDTH : integer; + attribute C_PROBE_OUT163_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT164_INIT_VAL : string; + attribute C_PROBE_OUT164_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT164_WIDTH : integer; + attribute C_PROBE_OUT164_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT165_INIT_VAL : string; + attribute C_PROBE_OUT165_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT165_WIDTH : integer; + attribute C_PROBE_OUT165_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT166_INIT_VAL : string; + attribute C_PROBE_OUT166_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT166_WIDTH : integer; + attribute C_PROBE_OUT166_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT167_INIT_VAL : string; + attribute C_PROBE_OUT167_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT167_WIDTH : integer; + attribute C_PROBE_OUT167_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT168_INIT_VAL : string; + attribute C_PROBE_OUT168_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT168_WIDTH : integer; + attribute C_PROBE_OUT168_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT169_INIT_VAL : string; + attribute C_PROBE_OUT169_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT169_WIDTH : integer; + attribute C_PROBE_OUT169_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT16_INIT_VAL : string; + attribute C_PROBE_OUT16_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT16_WIDTH : integer; + attribute C_PROBE_OUT16_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT170_INIT_VAL : string; + attribute C_PROBE_OUT170_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT170_WIDTH : integer; + attribute C_PROBE_OUT170_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT171_INIT_VAL : string; + attribute C_PROBE_OUT171_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT171_WIDTH : integer; + attribute C_PROBE_OUT171_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT172_INIT_VAL : string; + attribute C_PROBE_OUT172_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT172_WIDTH : integer; + attribute C_PROBE_OUT172_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT173_INIT_VAL : string; + attribute C_PROBE_OUT173_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT173_WIDTH : integer; + attribute C_PROBE_OUT173_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT174_INIT_VAL : string; + attribute C_PROBE_OUT174_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT174_WIDTH : integer; + attribute C_PROBE_OUT174_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT175_INIT_VAL : string; + attribute C_PROBE_OUT175_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT175_WIDTH : integer; + attribute C_PROBE_OUT175_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT176_INIT_VAL : string; + attribute C_PROBE_OUT176_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT176_WIDTH : integer; + attribute C_PROBE_OUT176_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT177_INIT_VAL : string; + attribute C_PROBE_OUT177_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT177_WIDTH : integer; + attribute C_PROBE_OUT177_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT178_INIT_VAL : string; + attribute C_PROBE_OUT178_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT178_WIDTH : integer; + attribute C_PROBE_OUT178_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT179_INIT_VAL : string; + attribute C_PROBE_OUT179_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT179_WIDTH : integer; + attribute C_PROBE_OUT179_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT17_INIT_VAL : string; + attribute C_PROBE_OUT17_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT17_WIDTH : integer; + attribute C_PROBE_OUT17_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT180_INIT_VAL : string; + attribute C_PROBE_OUT180_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT180_WIDTH : integer; + attribute C_PROBE_OUT180_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT181_INIT_VAL : string; + attribute C_PROBE_OUT181_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT181_WIDTH : integer; + attribute C_PROBE_OUT181_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT182_INIT_VAL : string; + attribute C_PROBE_OUT182_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT182_WIDTH : integer; + attribute C_PROBE_OUT182_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT183_INIT_VAL : string; + attribute C_PROBE_OUT183_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT183_WIDTH : integer; + attribute C_PROBE_OUT183_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT184_INIT_VAL : string; + attribute C_PROBE_OUT184_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT184_WIDTH : integer; + attribute C_PROBE_OUT184_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT185_INIT_VAL : string; + attribute C_PROBE_OUT185_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT185_WIDTH : integer; + attribute C_PROBE_OUT185_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT186_INIT_VAL : string; + attribute C_PROBE_OUT186_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT186_WIDTH : integer; + attribute C_PROBE_OUT186_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT187_INIT_VAL : string; + attribute C_PROBE_OUT187_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT187_WIDTH : integer; + attribute C_PROBE_OUT187_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT188_INIT_VAL : string; + attribute C_PROBE_OUT188_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT188_WIDTH : integer; + attribute C_PROBE_OUT188_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT189_INIT_VAL : string; + attribute C_PROBE_OUT189_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT189_WIDTH : integer; + attribute C_PROBE_OUT189_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT18_INIT_VAL : string; + attribute C_PROBE_OUT18_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT18_WIDTH : integer; + attribute C_PROBE_OUT18_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT190_INIT_VAL : string; + attribute C_PROBE_OUT190_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT190_WIDTH : integer; + attribute C_PROBE_OUT190_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT191_INIT_VAL : string; + attribute C_PROBE_OUT191_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT191_WIDTH : integer; + attribute C_PROBE_OUT191_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT192_INIT_VAL : string; + attribute C_PROBE_OUT192_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT192_WIDTH : integer; + attribute C_PROBE_OUT192_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT193_INIT_VAL : string; + attribute C_PROBE_OUT193_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT193_WIDTH : integer; + attribute C_PROBE_OUT193_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT194_INIT_VAL : string; + attribute C_PROBE_OUT194_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT194_WIDTH : integer; + attribute C_PROBE_OUT194_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT195_INIT_VAL : string; + attribute C_PROBE_OUT195_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT195_WIDTH : integer; + attribute C_PROBE_OUT195_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT196_INIT_VAL : string; + attribute C_PROBE_OUT196_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT196_WIDTH : integer; + attribute C_PROBE_OUT196_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT197_INIT_VAL : string; + attribute C_PROBE_OUT197_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT197_WIDTH : integer; + attribute C_PROBE_OUT197_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT198_INIT_VAL : string; + attribute C_PROBE_OUT198_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT198_WIDTH : integer; + attribute C_PROBE_OUT198_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT199_INIT_VAL : string; + attribute C_PROBE_OUT199_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT199_WIDTH : integer; + attribute C_PROBE_OUT199_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT19_INIT_VAL : string; + attribute C_PROBE_OUT19_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT19_WIDTH : integer; + attribute C_PROBE_OUT19_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT1_INIT_VAL : string; + attribute C_PROBE_OUT1_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT1_WIDTH : integer; + attribute C_PROBE_OUT1_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT200_INIT_VAL : string; + attribute C_PROBE_OUT200_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT200_WIDTH : integer; + attribute C_PROBE_OUT200_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT201_INIT_VAL : string; + attribute C_PROBE_OUT201_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT201_WIDTH : integer; + attribute C_PROBE_OUT201_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT202_INIT_VAL : string; + attribute C_PROBE_OUT202_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT202_WIDTH : integer; + attribute C_PROBE_OUT202_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT203_INIT_VAL : string; + attribute C_PROBE_OUT203_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT203_WIDTH : integer; + attribute C_PROBE_OUT203_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT204_INIT_VAL : string; + attribute C_PROBE_OUT204_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT204_WIDTH : integer; + attribute C_PROBE_OUT204_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT205_INIT_VAL : string; + attribute C_PROBE_OUT205_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT205_WIDTH : integer; + attribute C_PROBE_OUT205_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT206_INIT_VAL : string; + attribute C_PROBE_OUT206_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT206_WIDTH : integer; + attribute C_PROBE_OUT206_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT207_INIT_VAL : string; + attribute C_PROBE_OUT207_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT207_WIDTH : integer; + attribute C_PROBE_OUT207_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT208_INIT_VAL : string; + attribute C_PROBE_OUT208_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT208_WIDTH : integer; + attribute C_PROBE_OUT208_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT209_INIT_VAL : string; + attribute C_PROBE_OUT209_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT209_WIDTH : integer; + attribute C_PROBE_OUT209_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT20_INIT_VAL : string; + attribute C_PROBE_OUT20_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT20_WIDTH : integer; + attribute C_PROBE_OUT20_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT210_INIT_VAL : string; + attribute C_PROBE_OUT210_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT210_WIDTH : integer; + attribute C_PROBE_OUT210_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT211_INIT_VAL : string; + attribute C_PROBE_OUT211_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT211_WIDTH : integer; + attribute C_PROBE_OUT211_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT212_INIT_VAL : string; + attribute C_PROBE_OUT212_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT212_WIDTH : integer; + attribute C_PROBE_OUT212_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT213_INIT_VAL : string; + attribute C_PROBE_OUT213_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT213_WIDTH : integer; + attribute C_PROBE_OUT213_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT214_INIT_VAL : string; + attribute C_PROBE_OUT214_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT214_WIDTH : integer; + attribute C_PROBE_OUT214_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT215_INIT_VAL : string; + attribute C_PROBE_OUT215_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT215_WIDTH : integer; + attribute C_PROBE_OUT215_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT216_INIT_VAL : string; + attribute C_PROBE_OUT216_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT216_WIDTH : integer; + attribute C_PROBE_OUT216_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT217_INIT_VAL : string; + attribute C_PROBE_OUT217_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT217_WIDTH : integer; + attribute C_PROBE_OUT217_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT218_INIT_VAL : string; + attribute C_PROBE_OUT218_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT218_WIDTH : integer; + attribute C_PROBE_OUT218_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT219_INIT_VAL : string; + attribute C_PROBE_OUT219_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT219_WIDTH : integer; + attribute C_PROBE_OUT219_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT21_INIT_VAL : string; + attribute C_PROBE_OUT21_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT21_WIDTH : integer; + attribute C_PROBE_OUT21_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT220_INIT_VAL : string; + attribute C_PROBE_OUT220_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT220_WIDTH : integer; + attribute C_PROBE_OUT220_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT221_INIT_VAL : string; + attribute C_PROBE_OUT221_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT221_WIDTH : integer; + attribute C_PROBE_OUT221_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT222_INIT_VAL : string; + attribute C_PROBE_OUT222_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT222_WIDTH : integer; + attribute C_PROBE_OUT222_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT223_INIT_VAL : string; + attribute C_PROBE_OUT223_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT223_WIDTH : integer; + attribute C_PROBE_OUT223_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT224_INIT_VAL : string; + attribute C_PROBE_OUT224_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT224_WIDTH : integer; + attribute C_PROBE_OUT224_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT225_INIT_VAL : string; + attribute C_PROBE_OUT225_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT225_WIDTH : integer; + attribute C_PROBE_OUT225_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT226_INIT_VAL : string; + attribute C_PROBE_OUT226_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT226_WIDTH : integer; + attribute C_PROBE_OUT226_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT227_INIT_VAL : string; + attribute C_PROBE_OUT227_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT227_WIDTH : integer; + attribute C_PROBE_OUT227_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT228_INIT_VAL : string; + attribute C_PROBE_OUT228_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT228_WIDTH : integer; + attribute C_PROBE_OUT228_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT229_INIT_VAL : string; + attribute C_PROBE_OUT229_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT229_WIDTH : integer; + attribute C_PROBE_OUT229_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT22_INIT_VAL : string; + attribute C_PROBE_OUT22_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT22_WIDTH : integer; + attribute C_PROBE_OUT22_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT230_INIT_VAL : string; + attribute C_PROBE_OUT230_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT230_WIDTH : integer; + attribute C_PROBE_OUT230_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT231_INIT_VAL : string; + attribute C_PROBE_OUT231_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT231_WIDTH : integer; + attribute C_PROBE_OUT231_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT232_INIT_VAL : string; + attribute C_PROBE_OUT232_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT232_WIDTH : integer; + attribute C_PROBE_OUT232_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT233_INIT_VAL : string; + attribute C_PROBE_OUT233_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT233_WIDTH : integer; + attribute C_PROBE_OUT233_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT234_INIT_VAL : string; + attribute C_PROBE_OUT234_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT234_WIDTH : integer; + attribute C_PROBE_OUT234_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT235_INIT_VAL : string; + attribute C_PROBE_OUT235_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT235_WIDTH : integer; + attribute C_PROBE_OUT235_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT236_INIT_VAL : string; + attribute C_PROBE_OUT236_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT236_WIDTH : integer; + attribute C_PROBE_OUT236_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT237_INIT_VAL : string; + attribute C_PROBE_OUT237_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT237_WIDTH : integer; + attribute C_PROBE_OUT237_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT238_INIT_VAL : string; + attribute C_PROBE_OUT238_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT238_WIDTH : integer; + attribute C_PROBE_OUT238_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT239_INIT_VAL : string; + attribute C_PROBE_OUT239_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT239_WIDTH : integer; + attribute C_PROBE_OUT239_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT23_INIT_VAL : string; + attribute C_PROBE_OUT23_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT23_WIDTH : integer; + attribute C_PROBE_OUT23_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT240_INIT_VAL : string; + attribute C_PROBE_OUT240_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT240_WIDTH : integer; + attribute C_PROBE_OUT240_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT241_INIT_VAL : string; + attribute C_PROBE_OUT241_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT241_WIDTH : integer; + attribute C_PROBE_OUT241_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT242_INIT_VAL : string; + attribute C_PROBE_OUT242_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT242_WIDTH : integer; + attribute C_PROBE_OUT242_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT243_INIT_VAL : string; + attribute C_PROBE_OUT243_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT243_WIDTH : integer; + attribute C_PROBE_OUT243_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT244_INIT_VAL : string; + attribute C_PROBE_OUT244_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT244_WIDTH : integer; + attribute C_PROBE_OUT244_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT245_INIT_VAL : string; + attribute C_PROBE_OUT245_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT245_WIDTH : integer; + attribute C_PROBE_OUT245_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT246_INIT_VAL : string; + attribute C_PROBE_OUT246_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT246_WIDTH : integer; + attribute C_PROBE_OUT246_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT247_INIT_VAL : string; + attribute C_PROBE_OUT247_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT247_WIDTH : integer; + attribute C_PROBE_OUT247_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT248_INIT_VAL : string; + attribute C_PROBE_OUT248_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT248_WIDTH : integer; + attribute C_PROBE_OUT248_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT249_INIT_VAL : string; + attribute C_PROBE_OUT249_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT249_WIDTH : integer; + attribute C_PROBE_OUT249_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT24_INIT_VAL : string; + attribute C_PROBE_OUT24_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT24_WIDTH : integer; + attribute C_PROBE_OUT24_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT250_INIT_VAL : string; + attribute C_PROBE_OUT250_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT250_WIDTH : integer; + attribute C_PROBE_OUT250_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT251_INIT_VAL : string; + attribute C_PROBE_OUT251_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT251_WIDTH : integer; + attribute C_PROBE_OUT251_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT252_INIT_VAL : string; + attribute C_PROBE_OUT252_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT252_WIDTH : integer; + attribute C_PROBE_OUT252_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT253_INIT_VAL : string; + attribute C_PROBE_OUT253_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT253_WIDTH : integer; + attribute C_PROBE_OUT253_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT254_INIT_VAL : string; + attribute C_PROBE_OUT254_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT254_WIDTH : integer; + attribute C_PROBE_OUT254_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT255_INIT_VAL : string; + attribute C_PROBE_OUT255_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT255_WIDTH : integer; + attribute C_PROBE_OUT255_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT25_INIT_VAL : string; + attribute C_PROBE_OUT25_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT25_WIDTH : integer; + attribute C_PROBE_OUT25_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT26_INIT_VAL : string; + attribute C_PROBE_OUT26_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT26_WIDTH : integer; + attribute C_PROBE_OUT26_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT27_INIT_VAL : string; + attribute C_PROBE_OUT27_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT27_WIDTH : integer; + attribute C_PROBE_OUT27_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT28_INIT_VAL : string; + attribute C_PROBE_OUT28_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT28_WIDTH : integer; + attribute C_PROBE_OUT28_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT29_INIT_VAL : string; + attribute C_PROBE_OUT29_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT29_WIDTH : integer; + attribute C_PROBE_OUT29_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT2_INIT_VAL : string; + attribute C_PROBE_OUT2_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "32'b00000000000000000000000000000000"; + attribute C_PROBE_OUT2_WIDTH : integer; + attribute C_PROBE_OUT2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 32; + attribute C_PROBE_OUT30_INIT_VAL : string; + attribute C_PROBE_OUT30_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT30_WIDTH : integer; + attribute C_PROBE_OUT30_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT31_INIT_VAL : string; + attribute C_PROBE_OUT31_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT31_WIDTH : integer; + attribute C_PROBE_OUT31_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT32_INIT_VAL : string; + attribute C_PROBE_OUT32_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT32_WIDTH : integer; + attribute C_PROBE_OUT32_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT33_INIT_VAL : string; + attribute C_PROBE_OUT33_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT33_WIDTH : integer; + attribute C_PROBE_OUT33_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT34_INIT_VAL : string; + attribute C_PROBE_OUT34_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT34_WIDTH : integer; + attribute C_PROBE_OUT34_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT35_INIT_VAL : string; + attribute C_PROBE_OUT35_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT35_WIDTH : integer; + attribute C_PROBE_OUT35_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT36_INIT_VAL : string; + attribute C_PROBE_OUT36_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT36_WIDTH : integer; + attribute C_PROBE_OUT36_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT37_INIT_VAL : string; + attribute C_PROBE_OUT37_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT37_WIDTH : integer; + attribute C_PROBE_OUT37_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT38_INIT_VAL : string; + attribute C_PROBE_OUT38_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT38_WIDTH : integer; + attribute C_PROBE_OUT38_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT39_INIT_VAL : string; + attribute C_PROBE_OUT39_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT39_WIDTH : integer; + attribute C_PROBE_OUT39_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT3_INIT_VAL : string; + attribute C_PROBE_OUT3_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "2'b11"; + attribute C_PROBE_OUT3_WIDTH : integer; + attribute C_PROBE_OUT3_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 2; + attribute C_PROBE_OUT40_INIT_VAL : string; + attribute C_PROBE_OUT40_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT40_WIDTH : integer; + attribute C_PROBE_OUT40_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT41_INIT_VAL : string; + attribute C_PROBE_OUT41_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT41_WIDTH : integer; + attribute C_PROBE_OUT41_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT42_INIT_VAL : string; + attribute C_PROBE_OUT42_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT42_WIDTH : integer; + attribute C_PROBE_OUT42_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT43_INIT_VAL : string; + attribute C_PROBE_OUT43_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT43_WIDTH : integer; + attribute C_PROBE_OUT43_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT44_INIT_VAL : string; + attribute C_PROBE_OUT44_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT44_WIDTH : integer; + attribute C_PROBE_OUT44_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT45_INIT_VAL : string; + attribute C_PROBE_OUT45_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT45_WIDTH : integer; + attribute C_PROBE_OUT45_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT46_INIT_VAL : string; + attribute C_PROBE_OUT46_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT46_WIDTH : integer; + attribute C_PROBE_OUT46_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT47_INIT_VAL : string; + attribute C_PROBE_OUT47_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT47_WIDTH : integer; + attribute C_PROBE_OUT47_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT48_INIT_VAL : string; + attribute C_PROBE_OUT48_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT48_WIDTH : integer; + attribute C_PROBE_OUT48_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT49_INIT_VAL : string; + attribute C_PROBE_OUT49_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT49_WIDTH : integer; + attribute C_PROBE_OUT49_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT4_INIT_VAL : string; + attribute C_PROBE_OUT4_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "4'b0000"; + attribute C_PROBE_OUT4_WIDTH : integer; + attribute C_PROBE_OUT4_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 4; + attribute C_PROBE_OUT50_INIT_VAL : string; + attribute C_PROBE_OUT50_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT50_WIDTH : integer; + attribute C_PROBE_OUT50_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT51_INIT_VAL : string; + attribute C_PROBE_OUT51_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT51_WIDTH : integer; + attribute C_PROBE_OUT51_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT52_INIT_VAL : string; + attribute C_PROBE_OUT52_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT52_WIDTH : integer; + attribute C_PROBE_OUT52_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT53_INIT_VAL : string; + attribute C_PROBE_OUT53_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT53_WIDTH : integer; + attribute C_PROBE_OUT53_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT54_INIT_VAL : string; + attribute C_PROBE_OUT54_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT54_WIDTH : integer; + attribute C_PROBE_OUT54_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT55_INIT_VAL : string; + attribute C_PROBE_OUT55_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT55_WIDTH : integer; + attribute C_PROBE_OUT55_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT56_INIT_VAL : string; + attribute C_PROBE_OUT56_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT56_WIDTH : integer; + attribute C_PROBE_OUT56_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT57_INIT_VAL : string; + attribute C_PROBE_OUT57_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT57_WIDTH : integer; + attribute C_PROBE_OUT57_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT58_INIT_VAL : string; + attribute C_PROBE_OUT58_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT58_WIDTH : integer; + attribute C_PROBE_OUT58_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT59_INIT_VAL : string; + attribute C_PROBE_OUT59_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT59_WIDTH : integer; + attribute C_PROBE_OUT59_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT5_INIT_VAL : string; + attribute C_PROBE_OUT5_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT5_WIDTH : integer; + attribute C_PROBE_OUT5_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT60_INIT_VAL : string; + attribute C_PROBE_OUT60_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT60_WIDTH : integer; + attribute C_PROBE_OUT60_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT61_INIT_VAL : string; + attribute C_PROBE_OUT61_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT61_WIDTH : integer; + attribute C_PROBE_OUT61_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT62_INIT_VAL : string; + attribute C_PROBE_OUT62_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT62_WIDTH : integer; + attribute C_PROBE_OUT62_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT63_INIT_VAL : string; + attribute C_PROBE_OUT63_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT63_WIDTH : integer; + attribute C_PROBE_OUT63_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT64_INIT_VAL : string; + attribute C_PROBE_OUT64_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT64_WIDTH : integer; + attribute C_PROBE_OUT64_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT65_INIT_VAL : string; + attribute C_PROBE_OUT65_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT65_WIDTH : integer; + attribute C_PROBE_OUT65_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT66_INIT_VAL : string; + attribute C_PROBE_OUT66_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT66_WIDTH : integer; + attribute C_PROBE_OUT66_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT67_INIT_VAL : string; + attribute C_PROBE_OUT67_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT67_WIDTH : integer; + attribute C_PROBE_OUT67_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT68_INIT_VAL : string; + attribute C_PROBE_OUT68_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT68_WIDTH : integer; + attribute C_PROBE_OUT68_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT69_INIT_VAL : string; + attribute C_PROBE_OUT69_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT69_WIDTH : integer; + attribute C_PROBE_OUT69_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT6_INIT_VAL : string; + attribute C_PROBE_OUT6_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT6_WIDTH : integer; + attribute C_PROBE_OUT6_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT70_INIT_VAL : string; + attribute C_PROBE_OUT70_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT70_WIDTH : integer; + attribute C_PROBE_OUT70_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT71_INIT_VAL : string; + attribute C_PROBE_OUT71_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT71_WIDTH : integer; + attribute C_PROBE_OUT71_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT72_INIT_VAL : string; + attribute C_PROBE_OUT72_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT72_WIDTH : integer; + attribute C_PROBE_OUT72_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT73_INIT_VAL : string; + attribute C_PROBE_OUT73_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT73_WIDTH : integer; + attribute C_PROBE_OUT73_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT74_INIT_VAL : string; + attribute C_PROBE_OUT74_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT74_WIDTH : integer; + attribute C_PROBE_OUT74_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT75_INIT_VAL : string; + attribute C_PROBE_OUT75_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT75_WIDTH : integer; + attribute C_PROBE_OUT75_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT76_INIT_VAL : string; + attribute C_PROBE_OUT76_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT76_WIDTH : integer; + attribute C_PROBE_OUT76_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT77_INIT_VAL : string; + attribute C_PROBE_OUT77_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT77_WIDTH : integer; + attribute C_PROBE_OUT77_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT78_INIT_VAL : string; + attribute C_PROBE_OUT78_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT78_WIDTH : integer; + attribute C_PROBE_OUT78_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT79_INIT_VAL : string; + attribute C_PROBE_OUT79_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT79_WIDTH : integer; + attribute C_PROBE_OUT79_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT7_INIT_VAL : string; + attribute C_PROBE_OUT7_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT7_WIDTH : integer; + attribute C_PROBE_OUT7_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT80_INIT_VAL : string; + attribute C_PROBE_OUT80_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT80_WIDTH : integer; + attribute C_PROBE_OUT80_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT81_INIT_VAL : string; + attribute C_PROBE_OUT81_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT81_WIDTH : integer; + attribute C_PROBE_OUT81_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT82_INIT_VAL : string; + attribute C_PROBE_OUT82_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT82_WIDTH : integer; + attribute C_PROBE_OUT82_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT83_INIT_VAL : string; + attribute C_PROBE_OUT83_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT83_WIDTH : integer; + attribute C_PROBE_OUT83_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT84_INIT_VAL : string; + attribute C_PROBE_OUT84_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT84_WIDTH : integer; + attribute C_PROBE_OUT84_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT85_INIT_VAL : string; + attribute C_PROBE_OUT85_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT85_WIDTH : integer; + attribute C_PROBE_OUT85_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT86_INIT_VAL : string; + attribute C_PROBE_OUT86_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT86_WIDTH : integer; + attribute C_PROBE_OUT86_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT87_INIT_VAL : string; + attribute C_PROBE_OUT87_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT87_WIDTH : integer; + attribute C_PROBE_OUT87_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT88_INIT_VAL : string; + attribute C_PROBE_OUT88_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT88_WIDTH : integer; + attribute C_PROBE_OUT88_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT89_INIT_VAL : string; + attribute C_PROBE_OUT89_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT89_WIDTH : integer; + attribute C_PROBE_OUT89_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT8_INIT_VAL : string; + attribute C_PROBE_OUT8_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT8_WIDTH : integer; + attribute C_PROBE_OUT8_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT90_INIT_VAL : string; + attribute C_PROBE_OUT90_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT90_WIDTH : integer; + attribute C_PROBE_OUT90_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT91_INIT_VAL : string; + attribute C_PROBE_OUT91_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT91_WIDTH : integer; + attribute C_PROBE_OUT91_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT92_INIT_VAL : string; + attribute C_PROBE_OUT92_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT92_WIDTH : integer; + attribute C_PROBE_OUT92_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT93_INIT_VAL : string; + attribute C_PROBE_OUT93_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT93_WIDTH : integer; + attribute C_PROBE_OUT93_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT94_INIT_VAL : string; + attribute C_PROBE_OUT94_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT94_WIDTH : integer; + attribute C_PROBE_OUT94_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT95_INIT_VAL : string; + attribute C_PROBE_OUT95_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT95_WIDTH : integer; + attribute C_PROBE_OUT95_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT96_INIT_VAL : string; + attribute C_PROBE_OUT96_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT96_WIDTH : integer; + attribute C_PROBE_OUT96_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT97_INIT_VAL : string; + attribute C_PROBE_OUT97_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT97_WIDTH : integer; + attribute C_PROBE_OUT97_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT98_INIT_VAL : string; + attribute C_PROBE_OUT98_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT98_WIDTH : integer; + attribute C_PROBE_OUT98_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT99_INIT_VAL : string; + attribute C_PROBE_OUT99_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT99_WIDTH : integer; + attribute C_PROBE_OUT99_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_PROBE_OUT9_INIT_VAL : string; + attribute C_PROBE_OUT9_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "1'b0"; + attribute C_PROBE_OUT9_WIDTH : integer; + attribute C_PROBE_OUT9_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_USE_TEST_REG : integer; + attribute C_USE_TEST_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 1; + attribute C_XDEVICEFAMILY : string; + attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "kintex7"; + attribute C_XLNX_HW_PROBE_INFO : string; + attribute C_XLNX_HW_PROBE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "DEFAULT"; + attribute C_XSDB_SLAVE_TYPE : integer; + attribute C_XSDB_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 33; + attribute DowngradeIPIdentifiedWarnings : string; + attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "yes"; + attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT10 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT100 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT101 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT102 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT103 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT104 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT105 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT106 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT107 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT108 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT109 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT11 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT110 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT111 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT112 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT113 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT114 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT115 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT116 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT117 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT118 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT119 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT12 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT120 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT121 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT122 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT123 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT124 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT125 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT126 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT127 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT128 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT129 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT13 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT130 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010100110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT131 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010100111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT132 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010101000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT133 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT134 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT135 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT136 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT137 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT138 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT139 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT14 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT140 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT141 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT142 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT143 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT144 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT145 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT146 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT147 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT148 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT149 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT15 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT150 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT151 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT152 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT153 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT154 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT155 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT156 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT157 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT158 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT159 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT16 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT160 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT161 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT162 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT163 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT164 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT165 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT166 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT167 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT168 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT169 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT17 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT170 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT171 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT172 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT173 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT174 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT175 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT176 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT177 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT178 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT179 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT18 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT180 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT181 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT182 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT183 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT184 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT185 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT186 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT187 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT188 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT189 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT19 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT190 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT191 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT192 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT193 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT194 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011100110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT195 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011100111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT196 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011101000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT197 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT198 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT199 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT20 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT200 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT201 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT202 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT203 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT204 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT205 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT206 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT207 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT208 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT209 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT21 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT210 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT211 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT212 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT213 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT214 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT215 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT216 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT217 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT218 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT219 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT22 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT220 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT221 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT222 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT223 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT224 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT225 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT226 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT227 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT228 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT229 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT23 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT230 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT231 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT232 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT233 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT234 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT235 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT236 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT237 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT238 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT239 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT24 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT240 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT241 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT242 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT243 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT244 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT245 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT246 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT247 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT248 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT249 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT25 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT250 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT251 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT252 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT253 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT254 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT255 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT26 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT27 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT28 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT29 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT30 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT31 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT32 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT33 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT34 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT35 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT36 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT37 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT38 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT39 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000101000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT40 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT41 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT42 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT43 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT44 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT45 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT46 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT47 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT48 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT49 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT5 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT50 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT51 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT52 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT53 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT54 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT55 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT56 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT57 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT58 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT59 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT6 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT60 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT61 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT62 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT63 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT64 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT65 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT66 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001100110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT67 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001100111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT68 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001101000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT69 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT7 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT70 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT71 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT72 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT73 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT74 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT75 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT76 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT77 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT78 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT79 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT8 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT80 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT81 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT82 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT83 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT84 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT85 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT86 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT87 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT88 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT89 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT9 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT90 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT91 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT92 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT93 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT94 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT95 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT96 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT97 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT98 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT99 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT0 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT1 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT10 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT10 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT100 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT100 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT101 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT101 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT102 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT102 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT103 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT103 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT104 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT104 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT105 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT105 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT106 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT106 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT107 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT107 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT108 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT108 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT109 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT109 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT11 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT11 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT110 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT110 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT111 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT111 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT112 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT112 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT113 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT113 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT114 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT114 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT115 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT115 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT116 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT116 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT117 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT117 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT118 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT118 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT119 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT119 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT12 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT12 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT120 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT120 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT121 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT121 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT122 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT122 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT123 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT123 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT124 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT124 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT125 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT125 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT126 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT126 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT127 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT127 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT128 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT128 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT129 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT129 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010100101"; + attribute LC_LOW_BIT_POS_PROBE_OUT13 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT13 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT130 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT130 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT131 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT131 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010100111"; + attribute LC_LOW_BIT_POS_PROBE_OUT132 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT132 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010101000"; + attribute LC_LOW_BIT_POS_PROBE_OUT133 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT133 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010101001"; + attribute LC_LOW_BIT_POS_PROBE_OUT134 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT134 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT135 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT135 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT136 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT136 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT137 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT137 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT138 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT138 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT139 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT139 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT14 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT14 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT140 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT140 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT141 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT141 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT142 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT142 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT143 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT143 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT144 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT144 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT145 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT145 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT146 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT146 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT147 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT147 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT148 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT148 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT149 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT149 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT15 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT15 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT150 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT150 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT151 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT151 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT152 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT152 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT153 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT153 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT154 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT154 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT155 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT155 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT156 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT156 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT157 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT157 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT158 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT158 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT159 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT159 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT16 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT16 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT160 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT160 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT161 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT161 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT162 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT162 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT163 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT163 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT164 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT164 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT165 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT165 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT166 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT166 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT167 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT167 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT168 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT168 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT169 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT169 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT17 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT17 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT170 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT170 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT171 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT171 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT172 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT172 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT173 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT173 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT174 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT174 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT175 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT175 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT176 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT176 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT177 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT177 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT178 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT178 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT179 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT179 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT18 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT18 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT180 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT180 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT181 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT181 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT182 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT182 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT183 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT183 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT184 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT184 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT185 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT185 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT186 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT186 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT187 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT187 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT188 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT188 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT189 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT189 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT19 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT19 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT190 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT190 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT191 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT191 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT192 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT192 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT193 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT193 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011100101"; + attribute LC_LOW_BIT_POS_PROBE_OUT194 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT194 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT195 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT195 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011100111"; + attribute LC_LOW_BIT_POS_PROBE_OUT196 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT196 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011101000"; + attribute LC_LOW_BIT_POS_PROBE_OUT197 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT197 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011101001"; + attribute LC_LOW_BIT_POS_PROBE_OUT198 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT198 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT199 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT199 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT2 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT20 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT20 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT200 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT200 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT201 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT201 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT202 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT202 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT203 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT203 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT204 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT204 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT205 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT205 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT206 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT206 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT207 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT207 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT208 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT208 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT209 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT209 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT21 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT21 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT210 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT210 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT211 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT211 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT212 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT212 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT213 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT213 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT214 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT214 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT215 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT215 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT216 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT216 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT217 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT217 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT218 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT218 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT219 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT219 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000011111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT22 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT22 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT220 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT220 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT221 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT221 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT222 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT222 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT223 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT223 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT224 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT224 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT225 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT225 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT226 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT226 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT227 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT227 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT228 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT228 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT229 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT229 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT23 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT23 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT230 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT230 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT231 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT231 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT232 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT232 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT233 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT233 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT234 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT234 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT235 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT235 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT236 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT236 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT237 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT237 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT238 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT238 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT239 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT239 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT24 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT24 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT240 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT240 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT241 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT241 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT242 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT242 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT243 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT243 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT244 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT244 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT245 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT245 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT246 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT246 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT247 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT247 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT248 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT248 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT249 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT249 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT25 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT25 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT250 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT250 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT251 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT251 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT252 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT252 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT253 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT253 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT254 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT254 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT255 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT255 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000100100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT26 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT26 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT27 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT27 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT28 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT28 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT29 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT29 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT3 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT30 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT30 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT31 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT31 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT32 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT32 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT33 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT33 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT34 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT34 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT35 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT35 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT36 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT36 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT37 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT37 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT38 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT38 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT39 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT39 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT4 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000100101"; + attribute LC_LOW_BIT_POS_PROBE_OUT40 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT40 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT41 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT41 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT42 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT42 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT43 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT43 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT44 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT44 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT45 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT45 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT46 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT46 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT47 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT47 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT48 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT48 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT49 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT49 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT5 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT5 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000101001"; + attribute LC_LOW_BIT_POS_PROBE_OUT50 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT50 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT51 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT51 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT52 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT52 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT53 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT53 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT54 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT54 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT55 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT55 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT56 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT56 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT57 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT57 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT58 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT58 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT59 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT59 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT6 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT6 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT60 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT60 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT61 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT61 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT62 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT62 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT63 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT63 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT64 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT64 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT65 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT65 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001100101"; + attribute LC_LOW_BIT_POS_PROBE_OUT66 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT66 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT67 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT67 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001100111"; + attribute LC_LOW_BIT_POS_PROBE_OUT68 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT68 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001101000"; + attribute LC_LOW_BIT_POS_PROBE_OUT69 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT69 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001101001"; + attribute LC_LOW_BIT_POS_PROBE_OUT7 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT7 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT70 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT70 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT71 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT71 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT72 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT72 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT73 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT73 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT74 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT74 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT75 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT75 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT76 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT76 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT77 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT77 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT78 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT78 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT79 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT79 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT8 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT8 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT80 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT80 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT81 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT81 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT82 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT82 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT83 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT83 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT84 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT84 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT85 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT85 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT86 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT86 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT87 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT87 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT88 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT88 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT89 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT89 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT9 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT9 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000000101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT90 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT90 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT91 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT91 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000001111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT92 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT92 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT93 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT93 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT94 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT94 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT95 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT95 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT96 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT96 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT97 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT97 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT98 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT98 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT99 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT99 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "16'b0000000010000111"; + attribute LC_PROBE_IN_WIDTH_STRING : string; + attribute LC_PROBE_IN_WIDTH_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string; + attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "4096'b0000000100100011000000010010001000000001001000010000000100100000000000010001111100000001000111100000000100011101000000010001110000000001000110110000000100011010000000010001100100000001000110000000000100010111000000010001011000000001000101010000000100010100000000010001001100000001000100100000000100010001000000010001000000000001000011110000000100001110000000010000110100000001000011000000000100001011000000010000101000000001000010010000000100001000000000010000011100000001000001100000000100000101000000010000010000000001000000110000000100000010000000010000000100000001000000000000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100100000000000010001000000000000000100000000000000001"; + attribute LC_PROBE_OUT_INIT_VAL_STRING : string; + attribute LC_PROBE_OUT_INIT_VAL_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "292'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000010"; + attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string; + attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "4096'b0000000100100011000000010010001000000001001000010000000100100000000000010001111100000001000111100000000100011101000000010001110000000001000110110000000100011010000000010001100100000001000110000000000100010111000000010001011000000001000101010000000100010100000000010001001100000001000100100000000100010001000000010001000000000001000011110000000100001110000000010000110100000001000011000000000100001011000000010000101000000001000010010000000100001000000000010000011100000001000001100000000100000101000000010000010000000001000000110000000100000010000000010000000100000001000000000000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001001010000000000100011000000000000001100000000000000100000000000000000"; + attribute LC_PROBE_OUT_WIDTH_STRING : string; + attribute LC_PROBE_OUT_WIDTH_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000001000111110000000000000001"; + attribute LC_TOTAL_PROBE_IN_WIDTH : integer; + attribute LC_TOTAL_PROBE_IN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 0; + attribute LC_TOTAL_PROBE_OUT_WIDTH : integer; + attribute LC_TOTAL_PROBE_OUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is 41; + attribute dont_touch : string; + attribute dont_touch of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio : entity is "true"; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio is + signal \\ : STD_LOGIC; + signal DECODER_INST_n_5 : STD_LOGIC; + signal DECODER_INST_n_6 : STD_LOGIC; + signal DECODER_INST_n_7 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_41 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_45 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_46 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_47 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_48 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_49 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_50 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_51 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_52 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_53 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_54 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_55 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_56 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_57 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_58 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_59 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_60 : STD_LOGIC; + signal bus_addr : STD_LOGIC_VECTOR ( 16 downto 0 ); + signal bus_clk : STD_LOGIC; + attribute DONT_TOUCH_boolean : boolean; + attribute DONT_TOUCH_boolean of bus_clk : signal is std.standard.true; + signal \bus_data_int_reg_n_0_[0]\ : STD_LOGIC; + signal \bus_data_int_reg_n_0_[10]\ : STD_LOGIC; + signal \bus_data_int_reg_n_0_[11]\ : STD_LOGIC; + signal \bus_data_int_reg_n_0_[12]\ : STD_LOGIC; + signal \bus_data_int_reg_n_0_[13]\ : STD_LOGIC; + signal \bus_data_int_reg_n_0_[14]\ : STD_LOGIC; + signal \bus_data_int_reg_n_0_[15]\ : STD_LOGIC; + signal \bus_data_int_reg_n_0_[2]\ : STD_LOGIC; + signal \bus_data_int_reg_n_0_[3]\ : STD_LOGIC; + signal \bus_data_int_reg_n_0_[4]\ : STD_LOGIC; + signal \bus_data_int_reg_n_0_[5]\ : STD_LOGIC; + signal \bus_data_int_reg_n_0_[6]\ : STD_LOGIC; + signal \bus_data_int_reg_n_0_[7]\ : STD_LOGIC; + signal \bus_data_int_reg_n_0_[8]\ : STD_LOGIC; + signal \bus_data_int_reg_n_0_[9]\ : STD_LOGIC; + signal bus_den : STD_LOGIC; + signal bus_di : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal bus_do : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal bus_drdy : STD_LOGIC; + signal bus_dwe : STD_LOGIC; + signal bus_rst : STD_LOGIC; + signal clear : STD_LOGIC; + signal committ : STD_LOGIC; + signal internal_cnt_rst : STD_LOGIC; + signal p_0_in : STD_LOGIC; + signal probe_width_int : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal rd_probe_out_width : STD_LOGIC; + signal xsdb_addr_2_0_p1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute C_BUILD_REVISION of U_XSDB_SLAVE : label is 0; + attribute C_CORE_INFO1 of U_XSDB_SLAVE : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_CORE_INFO2 of U_XSDB_SLAVE : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_CORE_MAJOR_VER of U_XSDB_SLAVE : label is 2; + attribute C_CORE_MINOR_VER of U_XSDB_SLAVE : label is 0; + attribute C_CORE_TYPE of U_XSDB_SLAVE : label is 2; + attribute C_CSE_DRV_VER of U_XSDB_SLAVE : label is 1; + attribute C_MAJOR_VERSION of U_XSDB_SLAVE : label is 2013; + attribute C_MINOR_VERSION of U_XSDB_SLAVE : label is 1; + attribute C_NEXT_SLAVE of U_XSDB_SLAVE : label is 0; + attribute C_PIPE_IFACE of U_XSDB_SLAVE : label is 0; + attribute C_USE_TEST_REG of U_XSDB_SLAVE : label is 1; + attribute C_XDEVICEFAMILY of U_XSDB_SLAVE : label is "kintex7"; + attribute C_XSDB_SLAVE_TYPE of U_XSDB_SLAVE : label is 33; + attribute DONT_TOUCH_boolean of U_XSDB_SLAVE : label is std.standard.true; + attribute dont_touch of sl_iport0 : signal is "true"; + attribute dont_touch of sl_oport0 : signal is "true"; +begin + probe_out10(0) <= \\; + probe_out100(0) <= \\; + probe_out101(0) <= \\; + probe_out102(0) <= \\; + probe_out103(0) <= \\; + probe_out104(0) <= \\; + probe_out105(0) <= \\; + probe_out106(0) <= \\; + probe_out107(0) <= \\; + probe_out108(0) <= \\; + probe_out109(0) <= \\; + probe_out11(0) <= \\; + probe_out110(0) <= \\; + probe_out111(0) <= \\; + probe_out112(0) <= \\; + probe_out113(0) <= \\; + probe_out114(0) <= \\; + probe_out115(0) <= \\; + probe_out116(0) <= \\; + probe_out117(0) <= \\; + probe_out118(0) <= \\; + probe_out119(0) <= \\; + probe_out12(0) <= \\; + probe_out120(0) <= \\; + probe_out121(0) <= \\; + probe_out122(0) <= \\; + probe_out123(0) <= \\; + probe_out124(0) <= \\; + probe_out125(0) <= \\; + probe_out126(0) <= \\; + probe_out127(0) <= \\; + probe_out128(0) <= \\; + probe_out129(0) <= \\; + probe_out13(0) <= \\; + probe_out130(0) <= \\; + probe_out131(0) <= \\; + probe_out132(0) <= \\; + probe_out133(0) <= \\; + probe_out134(0) <= \\; + probe_out135(0) <= \\; + probe_out136(0) <= \\; + probe_out137(0) <= \\; + probe_out138(0) <= \\; + probe_out139(0) <= \\; + probe_out14(0) <= \\; + probe_out140(0) <= \\; + probe_out141(0) <= \\; + probe_out142(0) <= \\; + probe_out143(0) <= \\; + probe_out144(0) <= \\; + probe_out145(0) <= \\; + probe_out146(0) <= \\; + probe_out147(0) <= \\; + probe_out148(0) <= \\; + probe_out149(0) <= \\; + probe_out15(0) <= \\; + probe_out150(0) <= \\; + probe_out151(0) <= \\; + probe_out152(0) <= \\; + probe_out153(0) <= \\; + probe_out154(0) <= \\; + probe_out155(0) <= \\; + probe_out156(0) <= \\; + probe_out157(0) <= \\; + probe_out158(0) <= \\; + probe_out159(0) <= \\; + probe_out16(0) <= \\; + probe_out160(0) <= \\; + probe_out161(0) <= \\; + probe_out162(0) <= \\; + probe_out163(0) <= \\; + probe_out164(0) <= \\; + probe_out165(0) <= \\; + probe_out166(0) <= \\; + probe_out167(0) <= \\; + probe_out168(0) <= \\; + probe_out169(0) <= \\; + probe_out17(0) <= \\; + probe_out170(0) <= \\; + probe_out171(0) <= \\; + probe_out172(0) <= \\; + probe_out173(0) <= \\; + probe_out174(0) <= \\; + probe_out175(0) <= \\; + probe_out176(0) <= \\; + probe_out177(0) <= \\; + probe_out178(0) <= \\; + probe_out179(0) <= \\; + probe_out18(0) <= \\; + probe_out180(0) <= \\; + probe_out181(0) <= \\; + probe_out182(0) <= \\; + probe_out183(0) <= \\; + probe_out184(0) <= \\; + probe_out185(0) <= \\; + probe_out186(0) <= \\; + probe_out187(0) <= \\; + probe_out188(0) <= \\; + probe_out189(0) <= \\; + probe_out19(0) <= \\; + probe_out190(0) <= \\; + probe_out191(0) <= \\; + probe_out192(0) <= \\; + probe_out193(0) <= \\; + probe_out194(0) <= \\; + probe_out195(0) <= \\; + probe_out196(0) <= \\; + probe_out197(0) <= \\; + probe_out198(0) <= \\; + probe_out199(0) <= \\; + probe_out20(0) <= \\; + probe_out200(0) <= \\; + probe_out201(0) <= \\; + probe_out202(0) <= \\; + probe_out203(0) <= \\; + probe_out204(0) <= \\; + probe_out205(0) <= \\; + probe_out206(0) <= \\; + probe_out207(0) <= \\; + probe_out208(0) <= \\; + probe_out209(0) <= \\; + probe_out21(0) <= \\; + probe_out210(0) <= \\; + probe_out211(0) <= \\; + probe_out212(0) <= \\; + probe_out213(0) <= \\; + probe_out214(0) <= \\; + probe_out215(0) <= \\; + probe_out216(0) <= \\; + probe_out217(0) <= \\; + probe_out218(0) <= \\; + probe_out219(0) <= \\; + probe_out22(0) <= \\; + probe_out220(0) <= \\; + probe_out221(0) <= \\; + probe_out222(0) <= \\; + probe_out223(0) <= \\; + probe_out224(0) <= \\; + probe_out225(0) <= \\; + probe_out226(0) <= \\; + probe_out227(0) <= \\; + probe_out228(0) <= \\; + probe_out229(0) <= \\; + probe_out23(0) <= \\; + probe_out230(0) <= \\; + probe_out231(0) <= \\; + probe_out232(0) <= \\; + probe_out233(0) <= \\; + probe_out234(0) <= \\; + probe_out235(0) <= \\; + probe_out236(0) <= \\; + probe_out237(0) <= \\; + probe_out238(0) <= \\; + probe_out239(0) <= \\; + probe_out24(0) <= \\; + probe_out240(0) <= \\; + probe_out241(0) <= \\; + probe_out242(0) <= \\; + probe_out243(0) <= \\; + probe_out244(0) <= \\; + probe_out245(0) <= \\; + probe_out246(0) <= \\; + probe_out247(0) <= \\; + probe_out248(0) <= \\; + probe_out249(0) <= \\; + probe_out25(0) <= \\; + probe_out250(0) <= \\; + probe_out251(0) <= \\; + probe_out252(0) <= \\; + probe_out253(0) <= \\; + probe_out254(0) <= \\; + probe_out255(0) <= \\; + probe_out26(0) <= \\; + probe_out27(0) <= \\; + probe_out28(0) <= \\; + probe_out29(0) <= \\; + probe_out30(0) <= \\; + probe_out31(0) <= \\; + probe_out32(0) <= \\; + probe_out33(0) <= \\; + probe_out34(0) <= \\; + probe_out35(0) <= \\; + probe_out36(0) <= \\; + probe_out37(0) <= \\; + probe_out38(0) <= \\; + probe_out39(0) <= \\; + probe_out40(0) <= \\; + probe_out41(0) <= \\; + probe_out42(0) <= \\; + probe_out43(0) <= \\; + probe_out44(0) <= \\; + probe_out45(0) <= \\; + probe_out46(0) <= \\; + probe_out47(0) <= \\; + probe_out48(0) <= \\; + probe_out49(0) <= \\; + probe_out5(0) <= \\; + probe_out50(0) <= \\; + probe_out51(0) <= \\; + probe_out52(0) <= \\; + probe_out53(0) <= \\; + probe_out54(0) <= \\; + probe_out55(0) <= \\; + probe_out56(0) <= \\; + probe_out57(0) <= \\; + probe_out58(0) <= \\; + probe_out59(0) <= \\; + probe_out6(0) <= \\; + probe_out60(0) <= \\; + probe_out61(0) <= \\; + probe_out62(0) <= \\; + probe_out63(0) <= \\; + probe_out64(0) <= \\; + probe_out65(0) <= \\; + probe_out66(0) <= \\; + probe_out67(0) <= \\; + probe_out68(0) <= \\; + probe_out69(0) <= \\; + probe_out7(0) <= \\; + probe_out70(0) <= \\; + probe_out71(0) <= \\; + probe_out72(0) <= \\; + probe_out73(0) <= \\; + probe_out74(0) <= \\; + probe_out75(0) <= \\; + probe_out76(0) <= \\; + probe_out77(0) <= \\; + probe_out78(0) <= \\; + probe_out79(0) <= \\; + probe_out8(0) <= \\; + probe_out80(0) <= \\; + probe_out81(0) <= \\; + probe_out82(0) <= \\; + probe_out83(0) <= \\; + probe_out84(0) <= \\; + probe_out85(0) <= \\; + probe_out86(0) <= \\; + probe_out87(0) <= \\; + probe_out88(0) <= \\; + probe_out89(0) <= \\; + probe_out9(0) <= \\; + probe_out90(0) <= \\; + probe_out91(0) <= \\; + probe_out92(0) <= \\; + probe_out93(0) <= \\; + probe_out94(0) <= \\; + probe_out95(0) <= \\; + probe_out96(0) <= \\; + probe_out97(0) <= \\; + probe_out98(0) <= \\; + probe_out99(0) <= \\; +DECODER_INST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_decoder + port map ( + \Bus_data_out_reg[10]_0\ => PROBE_OUT_ALL_INST_n_54, + \Bus_data_out_reg[11]_0\ => PROBE_OUT_ALL_INST_n_53, + \Bus_data_out_reg[12]_0\ => PROBE_OUT_ALL_INST_n_52, + \Bus_data_out_reg[13]_0\ => PROBE_OUT_ALL_INST_n_51, + \Bus_data_out_reg[14]_0\ => PROBE_OUT_ALL_INST_n_50, + \Bus_data_out_reg[15]_0\(15 downto 0) => bus_do(15 downto 0), + \Bus_data_out_reg[15]_1\ => PROBE_OUT_ALL_INST_n_49, + \Bus_data_out_reg[3]_0\(2) => probe_width_int(8), + \Bus_data_out_reg[3]_0\(1 downto 0) => probe_width_int(1 downto 0), + \Bus_data_out_reg[4]_0\ => PROBE_OUT_ALL_INST_n_60, + \Bus_data_out_reg[5]_0\ => PROBE_OUT_ALL_INST_n_59, + \Bus_data_out_reg[6]_0\ => PROBE_OUT_ALL_INST_n_58, + \Bus_data_out_reg[7]_0\ => PROBE_OUT_ALL_INST_n_57, + \Bus_data_out_reg[8]_0\ => PROBE_OUT_ALL_INST_n_56, + \Bus_data_out_reg[9]_0\ => PROBE_OUT_ALL_INST_n_55, + \G_PROBE_OUT[0].wr_probe_out[0]_i_3_0\ => DECODER_INST_n_7, + \G_PROBE_OUT[0].wr_probe_out[0]_i_4_0\ => DECODER_INST_n_5, + Q(3) => PROBE_OUT_ALL_INST_n_45, + Q(2) => PROBE_OUT_ALL_INST_n_46, + Q(1) => PROBE_OUT_ALL_INST_n_47, + Q(0) => PROBE_OUT_ALL_INST_n_48, + SR(0) => clear, + in0 => committ, + internal_cnt_rst => internal_cnt_rst, + \out\ => bus_clk, + \probe_out_modified_reg[15]_0\(15) => \bus_data_int_reg_n_0_[15]\, + \probe_out_modified_reg[15]_0\(14) => \bus_data_int_reg_n_0_[14]\, + \probe_out_modified_reg[15]_0\(13) => \bus_data_int_reg_n_0_[13]\, + \probe_out_modified_reg[15]_0\(12) => \bus_data_int_reg_n_0_[12]\, + \probe_out_modified_reg[15]_0\(11) => \bus_data_int_reg_n_0_[11]\, + \probe_out_modified_reg[15]_0\(10) => \bus_data_int_reg_n_0_[10]\, + \probe_out_modified_reg[15]_0\(9) => \bus_data_int_reg_n_0_[9]\, + \probe_out_modified_reg[15]_0\(8) => \bus_data_int_reg_n_0_[8]\, + \probe_out_modified_reg[15]_0\(7) => \bus_data_int_reg_n_0_[7]\, + \probe_out_modified_reg[15]_0\(6) => \bus_data_int_reg_n_0_[6]\, + \probe_out_modified_reg[15]_0\(5) => \bus_data_int_reg_n_0_[5]\, + \probe_out_modified_reg[15]_0\(4) => \bus_data_int_reg_n_0_[4]\, + \probe_out_modified_reg[15]_0\(3) => \bus_data_int_reg_n_0_[3]\, + \probe_out_modified_reg[15]_0\(2) => \bus_data_int_reg_n_0_[2]\, + \probe_out_modified_reg[15]_0\(1) => p_0_in, + \probe_out_modified_reg[15]_0\(0) => \bus_data_int_reg_n_0_[0]\, + \rd_en_reg[6]_0\ => PROBE_OUT_ALL_INST_n_41, + rd_probe_out_width => rd_probe_out_width, + s_daddr_o(16 downto 0) => bus_addr(16 downto 0), + s_den_o => bus_den, + s_den_o_INST_0 => DECODER_INST_n_6, + s_drdy_i => bus_drdy, + s_dwe_o => bus_dwe, + s_rst_o => bus_rst, + \xsdb_addr_2_0_p2_reg[2]_0\(2 downto 0) => xsdb_addr_2_0_p1(2 downto 0) + ); +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +PROBE_OUT_ALL_INST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_out_all + port map ( + \G_PROBE_OUT[0].wr_probe_out_reg[0]_0\ => DECODER_INST_n_7, + \G_PROBE_OUT[0].wr_probe_out_reg[0]_1\ => DECODER_INST_n_5, + \G_PROBE_OUT[0].wr_probe_out_reg[0]_2\ => DECODER_INST_n_6, + \Probe_out_reg_int_reg[10]_0\ => PROBE_OUT_ALL_INST_n_54, + \Probe_out_reg_int_reg[11]_0\ => PROBE_OUT_ALL_INST_n_53, + \Probe_out_reg_int_reg[12]_0\ => PROBE_OUT_ALL_INST_n_52, + \Probe_out_reg_int_reg[13]_0\ => PROBE_OUT_ALL_INST_n_51, + \Probe_out_reg_int_reg[14]_0\ => PROBE_OUT_ALL_INST_n_50, + \Probe_out_reg_int_reg[15]_0\ => PROBE_OUT_ALL_INST_n_49, + \Probe_out_reg_int_reg[3]_0\(3) => PROBE_OUT_ALL_INST_n_45, + \Probe_out_reg_int_reg[3]_0\(2) => PROBE_OUT_ALL_INST_n_46, + \Probe_out_reg_int_reg[3]_0\(1) => PROBE_OUT_ALL_INST_n_47, + \Probe_out_reg_int_reg[3]_0\(0) => PROBE_OUT_ALL_INST_n_48, + \Probe_out_reg_int_reg[4]_0\ => PROBE_OUT_ALL_INST_n_60, + \Probe_out_reg_int_reg[5]_0\ => PROBE_OUT_ALL_INST_n_59, + \Probe_out_reg_int_reg[6]_0\ => PROBE_OUT_ALL_INST_n_58, + \Probe_out_reg_int_reg[7]_0\ => PROBE_OUT_ALL_INST_n_57, + \Probe_out_reg_int_reg[8]_0\ => PROBE_OUT_ALL_INST_n_56, + \Probe_out_reg_int_reg[9]_0\ => PROBE_OUT_ALL_INST_n_55, + Q(15) => \bus_data_int_reg_n_0_[15]\, + Q(14) => \bus_data_int_reg_n_0_[14]\, + Q(13) => \bus_data_int_reg_n_0_[13]\, + Q(12) => \bus_data_int_reg_n_0_[12]\, + Q(11) => \bus_data_int_reg_n_0_[11]\, + Q(10) => \bus_data_int_reg_n_0_[10]\, + Q(9) => \bus_data_int_reg_n_0_[9]\, + Q(8) => \bus_data_int_reg_n_0_[8]\, + Q(7) => \bus_data_int_reg_n_0_[7]\, + Q(6) => \bus_data_int_reg_n_0_[6]\, + Q(5) => \bus_data_int_reg_n_0_[5]\, + Q(4) => \bus_data_int_reg_n_0_[4]\, + Q(3) => \bus_data_int_reg_n_0_[3]\, + Q(2) => \bus_data_int_reg_n_0_[2]\, + Q(1) => p_0_in, + Q(0) => \bus_data_int_reg_n_0_[0]\, + SR(0) => clear, + \addr_count[1]_i_5\ => PROBE_OUT_ALL_INST_n_41, + \addr_p1_reg[2]_0\(2 downto 0) => xsdb_addr_2_0_p1(2 downto 0), + clk => clk, + in0 => committ, + internal_cnt_rst => internal_cnt_rst, + \out\ => bus_clk, + probe_out0(1 downto 0) => probe_out0(1 downto 0), + probe_out1(0) => probe_out1(0), + probe_out2(31 downto 0) => probe_out2(31 downto 0), + probe_out3(1 downto 0) => probe_out3(1 downto 0), + probe_out4(3 downto 0) => probe_out4(3 downto 0), + s_daddr_o(16 downto 0) => bus_addr(16 downto 0), + s_den_o => bus_den, + s_dwe_o => bus_dwe + ); +PROBE_OUT_WIDTH_INST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_probe_width + port map ( + Q(2) => probe_width_int(8), + Q(1 downto 0) => probe_width_int(1 downto 0), + internal_cnt_rst => internal_cnt_rst, + \out\ => bus_clk, + rd_probe_out_width => rd_probe_out_width, + s_rst_o => bus_rst + ); +U_XSDB_SLAVE: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs + port map ( + s_daddr_o(16 downto 0) => bus_addr(16 downto 0), + s_dclk_o => bus_clk, + s_den_o => bus_den, + s_di_o(15 downto 0) => bus_di(15 downto 0), + s_do_i(15 downto 0) => bus_do(15 downto 0), + s_drdy_i => bus_drdy, + s_dwe_o => bus_dwe, + s_rst_o => bus_rst, + sl_iport_i(36 downto 0) => sl_iport0(36 downto 0), + sl_oport_o(16 downto 0) => sl_oport0(16 downto 0) + ); +\bus_data_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => bus_clk, + CE => '1', + D => bus_di(0), + Q => \bus_data_int_reg_n_0_[0]\, + R => '0' + ); +\bus_data_int_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => bus_clk, + CE => '1', + D => bus_di(10), + Q => \bus_data_int_reg_n_0_[10]\, + R => '0' + ); +\bus_data_int_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => bus_clk, + CE => '1', + D => bus_di(11), + Q => \bus_data_int_reg_n_0_[11]\, + R => '0' + ); +\bus_data_int_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => bus_clk, + CE => '1', + D => bus_di(12), + Q => \bus_data_int_reg_n_0_[12]\, + R => '0' + ); +\bus_data_int_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => bus_clk, + CE => '1', + D => bus_di(13), + Q => \bus_data_int_reg_n_0_[13]\, + R => '0' + ); +\bus_data_int_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => bus_clk, + CE => '1', + D => bus_di(14), + Q => \bus_data_int_reg_n_0_[14]\, + R => '0' + ); +\bus_data_int_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => bus_clk, + CE => '1', + D => bus_di(15), + Q => \bus_data_int_reg_n_0_[15]\, + R => '0' + ); +\bus_data_int_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => bus_clk, + CE => '1', + D => bus_di(1), + Q => p_0_in, + R => '0' + ); +\bus_data_int_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => bus_clk, + CE => '1', + D => bus_di(2), + Q => \bus_data_int_reg_n_0_[2]\, + R => '0' + ); +\bus_data_int_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => bus_clk, + CE => '1', + D => bus_di(3), + Q => \bus_data_int_reg_n_0_[3]\, + R => '0' + ); +\bus_data_int_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => bus_clk, + CE => '1', + D => bus_di(4), + Q => \bus_data_int_reg_n_0_[4]\, + R => '0' + ); +\bus_data_int_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => bus_clk, + CE => '1', + D => bus_di(5), + Q => \bus_data_int_reg_n_0_[5]\, + R => '0' + ); +\bus_data_int_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => bus_clk, + CE => '1', + D => bus_di(6), + Q => \bus_data_int_reg_n_0_[6]\, + R => '0' + ); +\bus_data_int_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => bus_clk, + CE => '1', + D => bus_di(7), + Q => \bus_data_int_reg_n_0_[7]\, + R => '0' + ); +\bus_data_int_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => bus_clk, + CE => '1', + D => bus_di(8), + Q => \bus_data_int_reg_n_0_[8]\, + R => '0' + ); +\bus_data_int_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => bus_clk, + CE => '1', + D => bus_di(9), + Q => \bus_data_int_reg_n_0_[9]\, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + port ( + clk : in STD_LOGIC; + probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "vio_manual_ctrl,vio,{}"; + attribute X_CORE_INFO : string; + attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "vio,Vivado 2019.1.3"; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + signal NLW_inst_probe_out10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out100_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out101_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out102_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out103_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out104_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out105_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out106_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out107_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out108_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out109_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out110_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out111_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out112_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out113_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out114_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out115_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out116_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out117_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out118_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out119_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out120_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out121_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out122_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out123_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out124_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out125_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out126_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out127_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out128_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out129_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out130_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out131_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out132_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out133_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out134_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out135_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out136_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out137_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out138_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out139_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out140_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out141_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out142_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out143_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out144_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out145_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out146_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out147_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out148_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out149_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out150_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out151_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out152_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out153_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out154_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out155_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out156_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out157_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out158_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out159_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out160_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out161_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out162_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out163_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out164_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out165_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out166_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out167_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out168_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out169_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out170_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out171_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out172_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out173_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out174_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out175_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out176_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out177_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out178_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out179_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out180_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out181_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out182_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out183_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out184_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out185_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out186_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out187_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out188_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out189_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out190_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out191_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out192_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out193_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out194_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out195_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out196_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out197_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out198_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out199_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out200_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out201_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out202_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out203_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out204_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out205_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out206_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out207_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out208_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out209_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out210_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out211_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out212_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out213_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out214_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out215_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out216_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out217_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out218_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out219_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out220_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out221_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out222_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out223_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out224_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out225_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out226_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out227_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out228_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out229_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out230_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out231_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out232_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out233_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out234_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out235_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out236_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out237_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out238_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out239_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out240_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out241_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out242_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out243_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out244_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out245_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out246_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out247_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out248_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out249_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out250_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out251_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out252_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out253_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out254_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out255_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out32_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out33_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out34_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out35_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out36_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out37_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out38_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out39_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out40_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out41_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out42_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out43_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out44_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out45_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out46_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out47_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out48_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out49_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out50_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out51_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out52_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out53_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out54_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out55_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out56_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out57_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out58_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out59_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out60_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out61_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out62_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out63_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out64_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out65_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out66_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out67_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out68_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out69_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out70_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out71_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out72_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out73_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out74_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out75_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out76_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out77_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out78_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out79_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out80_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out81_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out82_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out83_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out84_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out85_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out86_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out87_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out88_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out89_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out90_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out91_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out92_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out93_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out94_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out95_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out96_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out97_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out98_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_probe_out99_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_sl_oport0_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 ); + attribute C_BUILD_REVISION : integer; + attribute C_BUILD_REVISION of inst : label is 0; + attribute C_BUS_ADDR_WIDTH : integer; + attribute C_BUS_ADDR_WIDTH of inst : label is 17; + attribute C_BUS_DATA_WIDTH : integer; + attribute C_BUS_DATA_WIDTH of inst : label is 16; + attribute C_CORE_INFO1 : string; + attribute C_CORE_INFO1 of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_CORE_INFO2 : string; + attribute C_CORE_INFO2 of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_CORE_MAJOR_VER : integer; + attribute C_CORE_MAJOR_VER of inst : label is 2; + attribute C_CORE_MINOR_ALPHA_VER : integer; + attribute C_CORE_MINOR_ALPHA_VER of inst : label is 97; + attribute C_CORE_MINOR_VER : integer; + attribute C_CORE_MINOR_VER of inst : label is 0; + attribute C_CORE_TYPE : integer; + attribute C_CORE_TYPE of inst : label is 2; + attribute C_CSE_DRV_VER : integer; + attribute C_CSE_DRV_VER of inst : label is 1; + attribute C_EN_PROBE_IN_ACTIVITY : integer; + attribute C_EN_PROBE_IN_ACTIVITY of inst : label is 0; + attribute C_EN_SYNCHRONIZATION : integer; + attribute C_EN_SYNCHRONIZATION of inst : label is 1; + attribute C_MAJOR_VERSION : integer; + attribute C_MAJOR_VERSION of inst : label is 2013; + attribute C_MAX_NUM_PROBE : integer; + attribute C_MAX_NUM_PROBE of inst : label is 256; + attribute C_MAX_WIDTH_PER_PROBE : integer; + attribute C_MAX_WIDTH_PER_PROBE of inst : label is 256; + attribute C_MINOR_VERSION : integer; + attribute C_MINOR_VERSION of inst : label is 1; + attribute C_NEXT_SLAVE : integer; + attribute C_NEXT_SLAVE of inst : label is 0; + attribute C_NUM_PROBE_IN : integer; + attribute C_NUM_PROBE_IN of inst : label is 0; + attribute C_NUM_PROBE_OUT : integer; + attribute C_NUM_PROBE_OUT of inst : label is 5; + attribute C_PIPE_IFACE : integer; + attribute C_PIPE_IFACE of inst : label is 0; + attribute C_PROBE_IN0_WIDTH : integer; + attribute C_PROBE_IN0_WIDTH of inst : label is 1; + attribute C_PROBE_IN100_WIDTH : integer; + attribute C_PROBE_IN100_WIDTH of inst : label is 1; + attribute C_PROBE_IN101_WIDTH : integer; + attribute C_PROBE_IN101_WIDTH of inst : label is 1; + attribute C_PROBE_IN102_WIDTH : integer; + attribute C_PROBE_IN102_WIDTH of inst : label is 1; + attribute C_PROBE_IN103_WIDTH : integer; + attribute C_PROBE_IN103_WIDTH of inst : label is 1; + attribute C_PROBE_IN104_WIDTH : integer; + attribute C_PROBE_IN104_WIDTH of inst : label is 1; + attribute C_PROBE_IN105_WIDTH : integer; + attribute C_PROBE_IN105_WIDTH of inst : label is 1; + attribute C_PROBE_IN106_WIDTH : integer; + attribute C_PROBE_IN106_WIDTH of inst : label is 1; + attribute C_PROBE_IN107_WIDTH : integer; + attribute C_PROBE_IN107_WIDTH of inst : label is 1; + attribute C_PROBE_IN108_WIDTH : integer; + attribute C_PROBE_IN108_WIDTH of inst : label is 1; + attribute C_PROBE_IN109_WIDTH : integer; + attribute C_PROBE_IN109_WIDTH of inst : label is 1; + attribute C_PROBE_IN10_WIDTH : integer; + attribute C_PROBE_IN10_WIDTH of inst : label is 1; + attribute C_PROBE_IN110_WIDTH : integer; + attribute C_PROBE_IN110_WIDTH of inst : label is 1; + attribute C_PROBE_IN111_WIDTH : integer; + attribute C_PROBE_IN111_WIDTH of inst : label is 1; + attribute C_PROBE_IN112_WIDTH : integer; + attribute C_PROBE_IN112_WIDTH of inst : label is 1; + attribute C_PROBE_IN113_WIDTH : integer; + attribute C_PROBE_IN113_WIDTH of inst : label is 1; + attribute C_PROBE_IN114_WIDTH : integer; + attribute C_PROBE_IN114_WIDTH of inst : label is 1; + attribute C_PROBE_IN115_WIDTH : integer; + attribute C_PROBE_IN115_WIDTH of inst : label is 1; + attribute C_PROBE_IN116_WIDTH : integer; + attribute C_PROBE_IN116_WIDTH of inst : label is 1; + attribute C_PROBE_IN117_WIDTH : integer; + attribute C_PROBE_IN117_WIDTH of inst : label is 1; + attribute C_PROBE_IN118_WIDTH : integer; + attribute C_PROBE_IN118_WIDTH of inst : label is 1; + attribute C_PROBE_IN119_WIDTH : integer; + attribute C_PROBE_IN119_WIDTH of inst : label is 1; + attribute C_PROBE_IN11_WIDTH : integer; + attribute C_PROBE_IN11_WIDTH of inst : label is 1; + attribute C_PROBE_IN120_WIDTH : integer; + attribute C_PROBE_IN120_WIDTH of inst : label is 1; + attribute C_PROBE_IN121_WIDTH : integer; + attribute C_PROBE_IN121_WIDTH of inst : label is 1; + attribute C_PROBE_IN122_WIDTH : integer; + attribute C_PROBE_IN122_WIDTH of inst : label is 1; + attribute C_PROBE_IN123_WIDTH : integer; + attribute C_PROBE_IN123_WIDTH of inst : label is 1; + attribute C_PROBE_IN124_WIDTH : integer; + attribute C_PROBE_IN124_WIDTH of inst : label is 1; + attribute C_PROBE_IN125_WIDTH : integer; + attribute C_PROBE_IN125_WIDTH of inst : label is 1; + attribute C_PROBE_IN126_WIDTH : integer; + attribute C_PROBE_IN126_WIDTH of inst : label is 1; + attribute C_PROBE_IN127_WIDTH : integer; + attribute C_PROBE_IN127_WIDTH of inst : label is 1; + attribute C_PROBE_IN128_WIDTH : integer; + attribute C_PROBE_IN128_WIDTH of inst : label is 1; + attribute C_PROBE_IN129_WIDTH : integer; + attribute C_PROBE_IN129_WIDTH of inst : label is 1; + attribute C_PROBE_IN12_WIDTH : integer; + attribute C_PROBE_IN12_WIDTH of inst : label is 1; + attribute C_PROBE_IN130_WIDTH : integer; + attribute C_PROBE_IN130_WIDTH of inst : label is 1; + attribute C_PROBE_IN131_WIDTH : integer; + attribute C_PROBE_IN131_WIDTH of inst : label is 1; + attribute C_PROBE_IN132_WIDTH : integer; + attribute C_PROBE_IN132_WIDTH of inst : label is 1; + attribute C_PROBE_IN133_WIDTH : integer; + attribute C_PROBE_IN133_WIDTH of inst : label is 1; + attribute C_PROBE_IN134_WIDTH : integer; + attribute C_PROBE_IN134_WIDTH of inst : label is 1; + attribute C_PROBE_IN135_WIDTH : integer; + attribute C_PROBE_IN135_WIDTH of inst : label is 1; + attribute C_PROBE_IN136_WIDTH : integer; + attribute C_PROBE_IN136_WIDTH of inst : label is 1; + attribute C_PROBE_IN137_WIDTH : integer; + attribute C_PROBE_IN137_WIDTH of inst : label is 1; + attribute C_PROBE_IN138_WIDTH : integer; + attribute C_PROBE_IN138_WIDTH of inst : label is 1; + attribute C_PROBE_IN139_WIDTH : integer; + attribute C_PROBE_IN139_WIDTH of inst : label is 1; + attribute C_PROBE_IN13_WIDTH : integer; + attribute C_PROBE_IN13_WIDTH of inst : label is 1; + attribute C_PROBE_IN140_WIDTH : integer; + attribute C_PROBE_IN140_WIDTH of inst : label is 1; + attribute C_PROBE_IN141_WIDTH : integer; + attribute C_PROBE_IN141_WIDTH of inst : label is 1; + attribute C_PROBE_IN142_WIDTH : integer; + attribute C_PROBE_IN142_WIDTH of inst : label is 1; + attribute C_PROBE_IN143_WIDTH : integer; + attribute C_PROBE_IN143_WIDTH of inst : label is 1; + attribute C_PROBE_IN144_WIDTH : integer; + attribute C_PROBE_IN144_WIDTH of inst : label is 1; + attribute C_PROBE_IN145_WIDTH : integer; + attribute C_PROBE_IN145_WIDTH of inst : label is 1; + attribute C_PROBE_IN146_WIDTH : integer; + attribute C_PROBE_IN146_WIDTH of inst : label is 1; + attribute C_PROBE_IN147_WIDTH : integer; + attribute C_PROBE_IN147_WIDTH of inst : label is 1; + attribute C_PROBE_IN148_WIDTH : integer; + attribute C_PROBE_IN148_WIDTH of inst : label is 1; + attribute C_PROBE_IN149_WIDTH : integer; + attribute C_PROBE_IN149_WIDTH of inst : label is 1; + attribute C_PROBE_IN14_WIDTH : integer; + attribute C_PROBE_IN14_WIDTH of inst : label is 1; + attribute C_PROBE_IN150_WIDTH : integer; + attribute C_PROBE_IN150_WIDTH of inst : label is 1; + attribute C_PROBE_IN151_WIDTH : integer; + attribute C_PROBE_IN151_WIDTH of inst : label is 1; + attribute C_PROBE_IN152_WIDTH : integer; + attribute C_PROBE_IN152_WIDTH of inst : label is 1; + attribute C_PROBE_IN153_WIDTH : integer; + attribute C_PROBE_IN153_WIDTH of inst : label is 1; + attribute C_PROBE_IN154_WIDTH : integer; + attribute C_PROBE_IN154_WIDTH of inst : label is 1; + attribute C_PROBE_IN155_WIDTH : integer; + attribute C_PROBE_IN155_WIDTH of inst : label is 1; + attribute C_PROBE_IN156_WIDTH : integer; + attribute C_PROBE_IN156_WIDTH of inst : label is 1; + attribute C_PROBE_IN157_WIDTH : integer; + attribute C_PROBE_IN157_WIDTH of inst : label is 1; + attribute C_PROBE_IN158_WIDTH : integer; + attribute C_PROBE_IN158_WIDTH of inst : label is 1; + attribute C_PROBE_IN159_WIDTH : integer; + attribute C_PROBE_IN159_WIDTH of inst : label is 1; + attribute C_PROBE_IN15_WIDTH : integer; + attribute C_PROBE_IN15_WIDTH of inst : label is 1; + attribute C_PROBE_IN160_WIDTH : integer; + attribute C_PROBE_IN160_WIDTH of inst : label is 1; + attribute C_PROBE_IN161_WIDTH : integer; + attribute C_PROBE_IN161_WIDTH of inst : label is 1; + attribute C_PROBE_IN162_WIDTH : integer; + attribute C_PROBE_IN162_WIDTH of inst : label is 1; + attribute C_PROBE_IN163_WIDTH : integer; + attribute C_PROBE_IN163_WIDTH of inst : label is 1; + attribute C_PROBE_IN164_WIDTH : integer; + attribute C_PROBE_IN164_WIDTH of inst : label is 1; + attribute C_PROBE_IN165_WIDTH : integer; + attribute C_PROBE_IN165_WIDTH of inst : label is 1; + attribute C_PROBE_IN166_WIDTH : integer; + attribute C_PROBE_IN166_WIDTH of inst : label is 1; + attribute C_PROBE_IN167_WIDTH : integer; + attribute C_PROBE_IN167_WIDTH of inst : label is 1; + attribute C_PROBE_IN168_WIDTH : integer; + attribute C_PROBE_IN168_WIDTH of inst : label is 1; + attribute C_PROBE_IN169_WIDTH : integer; + attribute C_PROBE_IN169_WIDTH of inst : label is 1; + attribute C_PROBE_IN16_WIDTH : integer; + attribute C_PROBE_IN16_WIDTH of inst : label is 1; + attribute C_PROBE_IN170_WIDTH : integer; + attribute C_PROBE_IN170_WIDTH of inst : label is 1; + attribute C_PROBE_IN171_WIDTH : integer; + attribute C_PROBE_IN171_WIDTH of inst : label is 1; + attribute C_PROBE_IN172_WIDTH : integer; + attribute C_PROBE_IN172_WIDTH of inst : label is 1; + attribute C_PROBE_IN173_WIDTH : integer; + attribute C_PROBE_IN173_WIDTH of inst : label is 1; + attribute C_PROBE_IN174_WIDTH : integer; + attribute C_PROBE_IN174_WIDTH of inst : label is 1; + attribute C_PROBE_IN175_WIDTH : integer; + attribute C_PROBE_IN175_WIDTH of inst : label is 1; + attribute C_PROBE_IN176_WIDTH : integer; + attribute C_PROBE_IN176_WIDTH of inst : label is 1; + attribute C_PROBE_IN177_WIDTH : integer; + attribute C_PROBE_IN177_WIDTH of inst : label is 1; + attribute C_PROBE_IN178_WIDTH : integer; + attribute C_PROBE_IN178_WIDTH of inst : label is 1; + attribute C_PROBE_IN179_WIDTH : integer; + attribute C_PROBE_IN179_WIDTH of inst : label is 1; + attribute C_PROBE_IN17_WIDTH : integer; + attribute C_PROBE_IN17_WIDTH of inst : label is 1; + attribute C_PROBE_IN180_WIDTH : integer; + attribute C_PROBE_IN180_WIDTH of inst : label is 1; + attribute C_PROBE_IN181_WIDTH : integer; + attribute C_PROBE_IN181_WIDTH of inst : label is 1; + attribute C_PROBE_IN182_WIDTH : integer; + attribute C_PROBE_IN182_WIDTH of inst : label is 1; + attribute C_PROBE_IN183_WIDTH : integer; + attribute C_PROBE_IN183_WIDTH of inst : label is 1; + attribute C_PROBE_IN184_WIDTH : integer; + attribute C_PROBE_IN184_WIDTH of inst : label is 1; + attribute C_PROBE_IN185_WIDTH : integer; + attribute C_PROBE_IN185_WIDTH of inst : label is 1; + attribute C_PROBE_IN186_WIDTH : integer; + attribute C_PROBE_IN186_WIDTH of inst : label is 1; + attribute C_PROBE_IN187_WIDTH : integer; + attribute C_PROBE_IN187_WIDTH of inst : label is 1; + attribute C_PROBE_IN188_WIDTH : integer; + attribute C_PROBE_IN188_WIDTH of inst : label is 1; + attribute C_PROBE_IN189_WIDTH : integer; + attribute C_PROBE_IN189_WIDTH of inst : label is 1; + attribute C_PROBE_IN18_WIDTH : integer; + attribute C_PROBE_IN18_WIDTH of inst : label is 1; + attribute C_PROBE_IN190_WIDTH : integer; + attribute C_PROBE_IN190_WIDTH of inst : label is 1; + attribute C_PROBE_IN191_WIDTH : integer; + attribute C_PROBE_IN191_WIDTH of inst : label is 1; + attribute C_PROBE_IN192_WIDTH : integer; + attribute C_PROBE_IN192_WIDTH of inst : label is 1; + attribute C_PROBE_IN193_WIDTH : integer; + attribute C_PROBE_IN193_WIDTH of inst : label is 1; + attribute C_PROBE_IN194_WIDTH : integer; + attribute C_PROBE_IN194_WIDTH of inst : label is 1; + attribute C_PROBE_IN195_WIDTH : integer; + attribute C_PROBE_IN195_WIDTH of inst : label is 1; + attribute C_PROBE_IN196_WIDTH : integer; + attribute C_PROBE_IN196_WIDTH of inst : label is 1; + attribute C_PROBE_IN197_WIDTH : integer; + attribute C_PROBE_IN197_WIDTH of inst : label is 1; + attribute C_PROBE_IN198_WIDTH : integer; + attribute C_PROBE_IN198_WIDTH of inst : label is 1; + attribute C_PROBE_IN199_WIDTH : integer; + attribute C_PROBE_IN199_WIDTH of inst : label is 1; + attribute C_PROBE_IN19_WIDTH : integer; + attribute C_PROBE_IN19_WIDTH of inst : label is 1; + attribute C_PROBE_IN1_WIDTH : integer; + attribute C_PROBE_IN1_WIDTH of inst : label is 1; + attribute C_PROBE_IN200_WIDTH : integer; + attribute C_PROBE_IN200_WIDTH of inst : label is 1; + attribute C_PROBE_IN201_WIDTH : integer; + attribute C_PROBE_IN201_WIDTH of inst : label is 1; + attribute C_PROBE_IN202_WIDTH : integer; + attribute C_PROBE_IN202_WIDTH of inst : label is 1; + attribute C_PROBE_IN203_WIDTH : integer; + attribute C_PROBE_IN203_WIDTH of inst : label is 1; + attribute C_PROBE_IN204_WIDTH : integer; + attribute C_PROBE_IN204_WIDTH of inst : label is 1; + attribute C_PROBE_IN205_WIDTH : integer; + attribute C_PROBE_IN205_WIDTH of inst : label is 1; + attribute C_PROBE_IN206_WIDTH : integer; + attribute C_PROBE_IN206_WIDTH of inst : label is 1; + attribute C_PROBE_IN207_WIDTH : integer; + attribute C_PROBE_IN207_WIDTH of inst : label is 1; + attribute C_PROBE_IN208_WIDTH : integer; + attribute C_PROBE_IN208_WIDTH of inst : label is 1; + attribute C_PROBE_IN209_WIDTH : integer; + attribute C_PROBE_IN209_WIDTH of inst : label is 1; + attribute C_PROBE_IN20_WIDTH : integer; + attribute C_PROBE_IN20_WIDTH of inst : label is 1; + attribute C_PROBE_IN210_WIDTH : integer; + attribute C_PROBE_IN210_WIDTH of inst : label is 1; + attribute C_PROBE_IN211_WIDTH : integer; + attribute C_PROBE_IN211_WIDTH of inst : label is 1; + attribute C_PROBE_IN212_WIDTH : integer; + attribute C_PROBE_IN212_WIDTH of inst : label is 1; + attribute C_PROBE_IN213_WIDTH : integer; + attribute C_PROBE_IN213_WIDTH of inst : label is 1; + attribute C_PROBE_IN214_WIDTH : integer; + attribute C_PROBE_IN214_WIDTH of inst : label is 1; + attribute C_PROBE_IN215_WIDTH : integer; + attribute C_PROBE_IN215_WIDTH of inst : label is 1; + attribute C_PROBE_IN216_WIDTH : integer; + attribute C_PROBE_IN216_WIDTH of inst : label is 1; + attribute C_PROBE_IN217_WIDTH : integer; + attribute C_PROBE_IN217_WIDTH of inst : label is 1; + attribute C_PROBE_IN218_WIDTH : integer; + attribute C_PROBE_IN218_WIDTH of inst : label is 1; + attribute C_PROBE_IN219_WIDTH : integer; + attribute C_PROBE_IN219_WIDTH of inst : label is 1; + attribute C_PROBE_IN21_WIDTH : integer; + attribute C_PROBE_IN21_WIDTH of inst : label is 1; + attribute C_PROBE_IN220_WIDTH : integer; + attribute C_PROBE_IN220_WIDTH of inst : label is 1; + attribute C_PROBE_IN221_WIDTH : integer; + attribute C_PROBE_IN221_WIDTH of inst : label is 1; + attribute C_PROBE_IN222_WIDTH : integer; + attribute C_PROBE_IN222_WIDTH of inst : label is 1; + attribute C_PROBE_IN223_WIDTH : integer; + attribute C_PROBE_IN223_WIDTH of inst : label is 1; + attribute C_PROBE_IN224_WIDTH : integer; + attribute C_PROBE_IN224_WIDTH of inst : label is 1; + attribute C_PROBE_IN225_WIDTH : integer; + attribute C_PROBE_IN225_WIDTH of inst : label is 1; + attribute C_PROBE_IN226_WIDTH : integer; + attribute C_PROBE_IN226_WIDTH of inst : label is 1; + attribute C_PROBE_IN227_WIDTH : integer; + attribute C_PROBE_IN227_WIDTH of inst : label is 1; + attribute C_PROBE_IN228_WIDTH : integer; + attribute C_PROBE_IN228_WIDTH of inst : label is 1; + attribute C_PROBE_IN229_WIDTH : integer; + attribute C_PROBE_IN229_WIDTH of inst : label is 1; + attribute C_PROBE_IN22_WIDTH : integer; + attribute C_PROBE_IN22_WIDTH of inst : label is 1; + attribute C_PROBE_IN230_WIDTH : integer; + attribute C_PROBE_IN230_WIDTH of inst : label is 1; + attribute C_PROBE_IN231_WIDTH : integer; + attribute C_PROBE_IN231_WIDTH of inst : label is 1; + attribute C_PROBE_IN232_WIDTH : integer; + attribute C_PROBE_IN232_WIDTH of inst : label is 1; + attribute C_PROBE_IN233_WIDTH : integer; + attribute C_PROBE_IN233_WIDTH of inst : label is 1; + attribute C_PROBE_IN234_WIDTH : integer; + attribute C_PROBE_IN234_WIDTH of inst : label is 1; + attribute C_PROBE_IN235_WIDTH : integer; + attribute C_PROBE_IN235_WIDTH of inst : label is 1; + attribute C_PROBE_IN236_WIDTH : integer; + attribute C_PROBE_IN236_WIDTH of inst : label is 1; + attribute C_PROBE_IN237_WIDTH : integer; + attribute C_PROBE_IN237_WIDTH of inst : label is 1; + attribute C_PROBE_IN238_WIDTH : integer; + attribute C_PROBE_IN238_WIDTH of inst : label is 1; + attribute C_PROBE_IN239_WIDTH : integer; + attribute C_PROBE_IN239_WIDTH of inst : label is 1; + attribute C_PROBE_IN23_WIDTH : integer; + attribute C_PROBE_IN23_WIDTH of inst : label is 1; + attribute C_PROBE_IN240_WIDTH : integer; + attribute C_PROBE_IN240_WIDTH of inst : label is 1; + attribute C_PROBE_IN241_WIDTH : integer; + attribute C_PROBE_IN241_WIDTH of inst : label is 1; + attribute C_PROBE_IN242_WIDTH : integer; + attribute C_PROBE_IN242_WIDTH of inst : label is 1; + attribute C_PROBE_IN243_WIDTH : integer; + attribute C_PROBE_IN243_WIDTH of inst : label is 1; + attribute C_PROBE_IN244_WIDTH : integer; + attribute C_PROBE_IN244_WIDTH of inst : label is 1; + attribute C_PROBE_IN245_WIDTH : integer; + attribute C_PROBE_IN245_WIDTH of inst : label is 1; + attribute C_PROBE_IN246_WIDTH : integer; + attribute C_PROBE_IN246_WIDTH of inst : label is 1; + attribute C_PROBE_IN247_WIDTH : integer; + attribute C_PROBE_IN247_WIDTH of inst : label is 1; + attribute C_PROBE_IN248_WIDTH : integer; + attribute C_PROBE_IN248_WIDTH of inst : label is 1; + attribute C_PROBE_IN249_WIDTH : integer; + attribute C_PROBE_IN249_WIDTH of inst : label is 1; + attribute C_PROBE_IN24_WIDTH : integer; + attribute C_PROBE_IN24_WIDTH of inst : label is 1; + attribute C_PROBE_IN250_WIDTH : integer; + attribute C_PROBE_IN250_WIDTH of inst : label is 1; + attribute C_PROBE_IN251_WIDTH : integer; + attribute C_PROBE_IN251_WIDTH of inst : label is 1; + attribute C_PROBE_IN252_WIDTH : integer; + attribute C_PROBE_IN252_WIDTH of inst : label is 1; + attribute C_PROBE_IN253_WIDTH : integer; + attribute C_PROBE_IN253_WIDTH of inst : label is 1; + attribute C_PROBE_IN254_WIDTH : integer; + attribute C_PROBE_IN254_WIDTH of inst : label is 1; + attribute C_PROBE_IN255_WIDTH : integer; + attribute C_PROBE_IN255_WIDTH of inst : label is 1; + attribute C_PROBE_IN25_WIDTH : integer; + attribute C_PROBE_IN25_WIDTH of inst : label is 1; + attribute C_PROBE_IN26_WIDTH : integer; + attribute C_PROBE_IN26_WIDTH of inst : label is 1; + attribute C_PROBE_IN27_WIDTH : integer; + attribute C_PROBE_IN27_WIDTH of inst : label is 1; + attribute C_PROBE_IN28_WIDTH : integer; + attribute C_PROBE_IN28_WIDTH of inst : label is 1; + attribute C_PROBE_IN29_WIDTH : integer; + attribute C_PROBE_IN29_WIDTH of inst : label is 1; + attribute C_PROBE_IN2_WIDTH : integer; + attribute C_PROBE_IN2_WIDTH of inst : label is 1; + attribute C_PROBE_IN30_WIDTH : integer; + attribute C_PROBE_IN30_WIDTH of inst : label is 1; + attribute C_PROBE_IN31_WIDTH : integer; + attribute C_PROBE_IN31_WIDTH of inst : label is 1; + attribute C_PROBE_IN32_WIDTH : integer; + attribute C_PROBE_IN32_WIDTH of inst : label is 1; + attribute C_PROBE_IN33_WIDTH : integer; + attribute C_PROBE_IN33_WIDTH of inst : label is 1; + attribute C_PROBE_IN34_WIDTH : integer; + attribute C_PROBE_IN34_WIDTH of inst : label is 1; + attribute C_PROBE_IN35_WIDTH : integer; + attribute C_PROBE_IN35_WIDTH of inst : label is 1; + attribute C_PROBE_IN36_WIDTH : integer; + attribute C_PROBE_IN36_WIDTH of inst : label is 1; + attribute C_PROBE_IN37_WIDTH : integer; + attribute C_PROBE_IN37_WIDTH of inst : label is 1; + attribute C_PROBE_IN38_WIDTH : integer; + attribute C_PROBE_IN38_WIDTH of inst : label is 1; + attribute C_PROBE_IN39_WIDTH : integer; + attribute C_PROBE_IN39_WIDTH of inst : label is 1; + attribute C_PROBE_IN3_WIDTH : integer; + attribute C_PROBE_IN3_WIDTH of inst : label is 1; + attribute C_PROBE_IN40_WIDTH : integer; + attribute C_PROBE_IN40_WIDTH of inst : label is 1; + attribute C_PROBE_IN41_WIDTH : integer; + attribute C_PROBE_IN41_WIDTH of inst : label is 1; + attribute C_PROBE_IN42_WIDTH : integer; + attribute C_PROBE_IN42_WIDTH of inst : label is 1; + attribute C_PROBE_IN43_WIDTH : integer; + attribute C_PROBE_IN43_WIDTH of inst : label is 1; + attribute C_PROBE_IN44_WIDTH : integer; + attribute C_PROBE_IN44_WIDTH of inst : label is 1; + attribute C_PROBE_IN45_WIDTH : integer; + attribute C_PROBE_IN45_WIDTH of inst : label is 1; + attribute C_PROBE_IN46_WIDTH : integer; + attribute C_PROBE_IN46_WIDTH of inst : label is 1; + attribute C_PROBE_IN47_WIDTH : integer; + attribute C_PROBE_IN47_WIDTH of inst : label is 1; + attribute C_PROBE_IN48_WIDTH : integer; + attribute C_PROBE_IN48_WIDTH of inst : label is 1; + attribute C_PROBE_IN49_WIDTH : integer; + attribute C_PROBE_IN49_WIDTH of inst : label is 1; + attribute C_PROBE_IN4_WIDTH : integer; + attribute C_PROBE_IN4_WIDTH of inst : label is 1; + attribute C_PROBE_IN50_WIDTH : integer; + attribute C_PROBE_IN50_WIDTH of inst : label is 1; + attribute C_PROBE_IN51_WIDTH : integer; + attribute C_PROBE_IN51_WIDTH of inst : label is 1; + attribute C_PROBE_IN52_WIDTH : integer; + attribute C_PROBE_IN52_WIDTH of inst : label is 1; + attribute C_PROBE_IN53_WIDTH : integer; + attribute C_PROBE_IN53_WIDTH of inst : label is 1; + attribute C_PROBE_IN54_WIDTH : integer; + attribute C_PROBE_IN54_WIDTH of inst : label is 1; + attribute C_PROBE_IN55_WIDTH : integer; + attribute C_PROBE_IN55_WIDTH of inst : label is 1; + attribute C_PROBE_IN56_WIDTH : integer; + attribute C_PROBE_IN56_WIDTH of inst : label is 1; + attribute C_PROBE_IN57_WIDTH : integer; + attribute C_PROBE_IN57_WIDTH of inst : label is 1; + attribute C_PROBE_IN58_WIDTH : integer; + attribute C_PROBE_IN58_WIDTH of inst : label is 1; + attribute C_PROBE_IN59_WIDTH : integer; + attribute C_PROBE_IN59_WIDTH of inst : label is 1; + attribute C_PROBE_IN5_WIDTH : integer; + attribute C_PROBE_IN5_WIDTH of inst : label is 1; + attribute C_PROBE_IN60_WIDTH : integer; + attribute C_PROBE_IN60_WIDTH of inst : label is 1; + attribute C_PROBE_IN61_WIDTH : integer; + attribute C_PROBE_IN61_WIDTH of inst : label is 1; + attribute C_PROBE_IN62_WIDTH : integer; + attribute C_PROBE_IN62_WIDTH of inst : label is 1; + attribute C_PROBE_IN63_WIDTH : integer; + attribute C_PROBE_IN63_WIDTH of inst : label is 1; + attribute C_PROBE_IN64_WIDTH : integer; + attribute C_PROBE_IN64_WIDTH of inst : label is 1; + attribute C_PROBE_IN65_WIDTH : integer; + attribute C_PROBE_IN65_WIDTH of inst : label is 1; + attribute C_PROBE_IN66_WIDTH : integer; + attribute C_PROBE_IN66_WIDTH of inst : label is 1; + attribute C_PROBE_IN67_WIDTH : integer; + attribute C_PROBE_IN67_WIDTH of inst : label is 1; + attribute C_PROBE_IN68_WIDTH : integer; + attribute C_PROBE_IN68_WIDTH of inst : label is 1; + attribute C_PROBE_IN69_WIDTH : integer; + attribute C_PROBE_IN69_WIDTH of inst : label is 1; + attribute C_PROBE_IN6_WIDTH : integer; + attribute C_PROBE_IN6_WIDTH of inst : label is 1; + attribute C_PROBE_IN70_WIDTH : integer; + attribute C_PROBE_IN70_WIDTH of inst : label is 1; + attribute C_PROBE_IN71_WIDTH : integer; + attribute C_PROBE_IN71_WIDTH of inst : label is 1; + attribute C_PROBE_IN72_WIDTH : integer; + attribute C_PROBE_IN72_WIDTH of inst : label is 1; + attribute C_PROBE_IN73_WIDTH : integer; + attribute C_PROBE_IN73_WIDTH of inst : label is 1; + attribute C_PROBE_IN74_WIDTH : integer; + attribute C_PROBE_IN74_WIDTH of inst : label is 1; + attribute C_PROBE_IN75_WIDTH : integer; + attribute C_PROBE_IN75_WIDTH of inst : label is 1; + attribute C_PROBE_IN76_WIDTH : integer; + attribute C_PROBE_IN76_WIDTH of inst : label is 1; + attribute C_PROBE_IN77_WIDTH : integer; + attribute C_PROBE_IN77_WIDTH of inst : label is 1; + attribute C_PROBE_IN78_WIDTH : integer; + attribute C_PROBE_IN78_WIDTH of inst : label is 1; + attribute C_PROBE_IN79_WIDTH : integer; + attribute C_PROBE_IN79_WIDTH of inst : label is 1; + attribute C_PROBE_IN7_WIDTH : integer; + attribute C_PROBE_IN7_WIDTH of inst : label is 1; + attribute C_PROBE_IN80_WIDTH : integer; + attribute C_PROBE_IN80_WIDTH of inst : label is 1; + attribute C_PROBE_IN81_WIDTH : integer; + attribute C_PROBE_IN81_WIDTH of inst : label is 1; + attribute C_PROBE_IN82_WIDTH : integer; + attribute C_PROBE_IN82_WIDTH of inst : label is 1; + attribute C_PROBE_IN83_WIDTH : integer; + attribute C_PROBE_IN83_WIDTH of inst : label is 1; + attribute C_PROBE_IN84_WIDTH : integer; + attribute C_PROBE_IN84_WIDTH of inst : label is 1; + attribute C_PROBE_IN85_WIDTH : integer; + attribute C_PROBE_IN85_WIDTH of inst : label is 1; + attribute C_PROBE_IN86_WIDTH : integer; + attribute C_PROBE_IN86_WIDTH of inst : label is 1; + attribute C_PROBE_IN87_WIDTH : integer; + attribute C_PROBE_IN87_WIDTH of inst : label is 1; + attribute C_PROBE_IN88_WIDTH : integer; + attribute C_PROBE_IN88_WIDTH of inst : label is 1; + attribute C_PROBE_IN89_WIDTH : integer; + attribute C_PROBE_IN89_WIDTH of inst : label is 1; + attribute C_PROBE_IN8_WIDTH : integer; + attribute C_PROBE_IN8_WIDTH of inst : label is 1; + attribute C_PROBE_IN90_WIDTH : integer; + attribute C_PROBE_IN90_WIDTH of inst : label is 1; + attribute C_PROBE_IN91_WIDTH : integer; + attribute C_PROBE_IN91_WIDTH of inst : label is 1; + attribute C_PROBE_IN92_WIDTH : integer; + attribute C_PROBE_IN92_WIDTH of inst : label is 1; + attribute C_PROBE_IN93_WIDTH : integer; + attribute C_PROBE_IN93_WIDTH of inst : label is 1; + attribute C_PROBE_IN94_WIDTH : integer; + attribute C_PROBE_IN94_WIDTH of inst : label is 1; + attribute C_PROBE_IN95_WIDTH : integer; + attribute C_PROBE_IN95_WIDTH of inst : label is 1; + attribute C_PROBE_IN96_WIDTH : integer; + attribute C_PROBE_IN96_WIDTH of inst : label is 1; + attribute C_PROBE_IN97_WIDTH : integer; + attribute C_PROBE_IN97_WIDTH of inst : label is 1; + attribute C_PROBE_IN98_WIDTH : integer; + attribute C_PROBE_IN98_WIDTH of inst : label is 1; + attribute C_PROBE_IN99_WIDTH : integer; + attribute C_PROBE_IN99_WIDTH of inst : label is 1; + attribute C_PROBE_IN9_WIDTH : integer; + attribute C_PROBE_IN9_WIDTH of inst : label is 1; + attribute C_PROBE_OUT0_INIT_VAL : string; + attribute C_PROBE_OUT0_INIT_VAL of inst : label is "2'b10"; + attribute C_PROBE_OUT0_WIDTH : integer; + attribute C_PROBE_OUT0_WIDTH of inst : label is 2; + attribute C_PROBE_OUT100_INIT_VAL : string; + attribute C_PROBE_OUT100_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT100_WIDTH : integer; + attribute C_PROBE_OUT100_WIDTH of inst : label is 1; + attribute C_PROBE_OUT101_INIT_VAL : string; + attribute C_PROBE_OUT101_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT101_WIDTH : integer; + attribute C_PROBE_OUT101_WIDTH of inst : label is 1; + attribute C_PROBE_OUT102_INIT_VAL : string; + attribute C_PROBE_OUT102_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT102_WIDTH : integer; + attribute C_PROBE_OUT102_WIDTH of inst : label is 1; + attribute C_PROBE_OUT103_INIT_VAL : string; + attribute C_PROBE_OUT103_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT103_WIDTH : integer; + attribute C_PROBE_OUT103_WIDTH of inst : label is 1; + attribute C_PROBE_OUT104_INIT_VAL : string; + attribute C_PROBE_OUT104_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT104_WIDTH : integer; + attribute C_PROBE_OUT104_WIDTH of inst : label is 1; + attribute C_PROBE_OUT105_INIT_VAL : string; + attribute C_PROBE_OUT105_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT105_WIDTH : integer; + attribute C_PROBE_OUT105_WIDTH of inst : label is 1; + attribute C_PROBE_OUT106_INIT_VAL : string; + attribute C_PROBE_OUT106_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT106_WIDTH : integer; + attribute C_PROBE_OUT106_WIDTH of inst : label is 1; + attribute C_PROBE_OUT107_INIT_VAL : string; + attribute C_PROBE_OUT107_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT107_WIDTH : integer; + attribute C_PROBE_OUT107_WIDTH of inst : label is 1; + attribute C_PROBE_OUT108_INIT_VAL : string; + attribute C_PROBE_OUT108_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT108_WIDTH : integer; + attribute C_PROBE_OUT108_WIDTH of inst : label is 1; + attribute C_PROBE_OUT109_INIT_VAL : string; + attribute C_PROBE_OUT109_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT109_WIDTH : integer; + attribute C_PROBE_OUT109_WIDTH of inst : label is 1; + attribute C_PROBE_OUT10_INIT_VAL : string; + attribute C_PROBE_OUT10_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT10_WIDTH : integer; + attribute C_PROBE_OUT10_WIDTH of inst : label is 1; + attribute C_PROBE_OUT110_INIT_VAL : string; + attribute C_PROBE_OUT110_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT110_WIDTH : integer; + attribute C_PROBE_OUT110_WIDTH of inst : label is 1; + attribute C_PROBE_OUT111_INIT_VAL : string; + attribute C_PROBE_OUT111_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT111_WIDTH : integer; + attribute C_PROBE_OUT111_WIDTH of inst : label is 1; + attribute C_PROBE_OUT112_INIT_VAL : string; + attribute C_PROBE_OUT112_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT112_WIDTH : integer; + attribute C_PROBE_OUT112_WIDTH of inst : label is 1; + attribute C_PROBE_OUT113_INIT_VAL : string; + attribute C_PROBE_OUT113_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT113_WIDTH : integer; + attribute C_PROBE_OUT113_WIDTH of inst : label is 1; + attribute C_PROBE_OUT114_INIT_VAL : string; + attribute C_PROBE_OUT114_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT114_WIDTH : integer; + attribute C_PROBE_OUT114_WIDTH of inst : label is 1; + attribute C_PROBE_OUT115_INIT_VAL : string; + attribute C_PROBE_OUT115_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT115_WIDTH : integer; + attribute C_PROBE_OUT115_WIDTH of inst : label is 1; + attribute C_PROBE_OUT116_INIT_VAL : string; + attribute C_PROBE_OUT116_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT116_WIDTH : integer; + attribute C_PROBE_OUT116_WIDTH of inst : label is 1; + attribute C_PROBE_OUT117_INIT_VAL : string; + attribute C_PROBE_OUT117_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT117_WIDTH : integer; + attribute C_PROBE_OUT117_WIDTH of inst : label is 1; + attribute C_PROBE_OUT118_INIT_VAL : string; + attribute C_PROBE_OUT118_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT118_WIDTH : integer; + attribute C_PROBE_OUT118_WIDTH of inst : label is 1; + attribute C_PROBE_OUT119_INIT_VAL : string; + attribute C_PROBE_OUT119_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT119_WIDTH : integer; + attribute C_PROBE_OUT119_WIDTH of inst : label is 1; + attribute C_PROBE_OUT11_INIT_VAL : string; + attribute C_PROBE_OUT11_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT11_WIDTH : integer; + attribute C_PROBE_OUT11_WIDTH of inst : label is 1; + attribute C_PROBE_OUT120_INIT_VAL : string; + attribute C_PROBE_OUT120_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT120_WIDTH : integer; + attribute C_PROBE_OUT120_WIDTH of inst : label is 1; + attribute C_PROBE_OUT121_INIT_VAL : string; + attribute C_PROBE_OUT121_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT121_WIDTH : integer; + attribute C_PROBE_OUT121_WIDTH of inst : label is 1; + attribute C_PROBE_OUT122_INIT_VAL : string; + attribute C_PROBE_OUT122_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT122_WIDTH : integer; + attribute C_PROBE_OUT122_WIDTH of inst : label is 1; + attribute C_PROBE_OUT123_INIT_VAL : string; + attribute C_PROBE_OUT123_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT123_WIDTH : integer; + attribute C_PROBE_OUT123_WIDTH of inst : label is 1; + attribute C_PROBE_OUT124_INIT_VAL : string; + attribute C_PROBE_OUT124_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT124_WIDTH : integer; + attribute C_PROBE_OUT124_WIDTH of inst : label is 1; + attribute C_PROBE_OUT125_INIT_VAL : string; + attribute C_PROBE_OUT125_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT125_WIDTH : integer; + attribute C_PROBE_OUT125_WIDTH of inst : label is 1; + attribute C_PROBE_OUT126_INIT_VAL : string; + attribute C_PROBE_OUT126_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT126_WIDTH : integer; + attribute C_PROBE_OUT126_WIDTH of inst : label is 1; + attribute C_PROBE_OUT127_INIT_VAL : string; + attribute C_PROBE_OUT127_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT127_WIDTH : integer; + attribute C_PROBE_OUT127_WIDTH of inst : label is 1; + attribute C_PROBE_OUT128_INIT_VAL : string; + attribute C_PROBE_OUT128_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT128_WIDTH : integer; + attribute C_PROBE_OUT128_WIDTH of inst : label is 1; + attribute C_PROBE_OUT129_INIT_VAL : string; + attribute C_PROBE_OUT129_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT129_WIDTH : integer; + attribute C_PROBE_OUT129_WIDTH of inst : label is 1; + attribute C_PROBE_OUT12_INIT_VAL : string; + attribute C_PROBE_OUT12_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT12_WIDTH : integer; + attribute C_PROBE_OUT12_WIDTH of inst : label is 1; + attribute C_PROBE_OUT130_INIT_VAL : string; + attribute C_PROBE_OUT130_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT130_WIDTH : integer; + attribute C_PROBE_OUT130_WIDTH of inst : label is 1; + attribute C_PROBE_OUT131_INIT_VAL : string; + attribute C_PROBE_OUT131_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT131_WIDTH : integer; + attribute C_PROBE_OUT131_WIDTH of inst : label is 1; + attribute C_PROBE_OUT132_INIT_VAL : string; + attribute C_PROBE_OUT132_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT132_WIDTH : integer; + attribute C_PROBE_OUT132_WIDTH of inst : label is 1; + attribute C_PROBE_OUT133_INIT_VAL : string; + attribute C_PROBE_OUT133_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT133_WIDTH : integer; + attribute C_PROBE_OUT133_WIDTH of inst : label is 1; + attribute C_PROBE_OUT134_INIT_VAL : string; + attribute C_PROBE_OUT134_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT134_WIDTH : integer; + attribute C_PROBE_OUT134_WIDTH of inst : label is 1; + attribute C_PROBE_OUT135_INIT_VAL : string; + attribute C_PROBE_OUT135_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT135_WIDTH : integer; + attribute C_PROBE_OUT135_WIDTH of inst : label is 1; + attribute C_PROBE_OUT136_INIT_VAL : string; + attribute C_PROBE_OUT136_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT136_WIDTH : integer; + attribute C_PROBE_OUT136_WIDTH of inst : label is 1; + attribute C_PROBE_OUT137_INIT_VAL : string; + attribute C_PROBE_OUT137_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT137_WIDTH : integer; + attribute C_PROBE_OUT137_WIDTH of inst : label is 1; + attribute C_PROBE_OUT138_INIT_VAL : string; + attribute C_PROBE_OUT138_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT138_WIDTH : integer; + attribute C_PROBE_OUT138_WIDTH of inst : label is 1; + attribute C_PROBE_OUT139_INIT_VAL : string; + attribute C_PROBE_OUT139_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT139_WIDTH : integer; + attribute C_PROBE_OUT139_WIDTH of inst : label is 1; + attribute C_PROBE_OUT13_INIT_VAL : string; + attribute C_PROBE_OUT13_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT13_WIDTH : integer; + attribute C_PROBE_OUT13_WIDTH of inst : label is 1; + attribute C_PROBE_OUT140_INIT_VAL : string; + attribute C_PROBE_OUT140_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT140_WIDTH : integer; + attribute C_PROBE_OUT140_WIDTH of inst : label is 1; + attribute C_PROBE_OUT141_INIT_VAL : string; + attribute C_PROBE_OUT141_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT141_WIDTH : integer; + attribute C_PROBE_OUT141_WIDTH of inst : label is 1; + attribute C_PROBE_OUT142_INIT_VAL : string; + attribute C_PROBE_OUT142_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT142_WIDTH : integer; + attribute C_PROBE_OUT142_WIDTH of inst : label is 1; + attribute C_PROBE_OUT143_INIT_VAL : string; + attribute C_PROBE_OUT143_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT143_WIDTH : integer; + attribute C_PROBE_OUT143_WIDTH of inst : label is 1; + attribute C_PROBE_OUT144_INIT_VAL : string; + attribute C_PROBE_OUT144_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT144_WIDTH : integer; + attribute C_PROBE_OUT144_WIDTH of inst : label is 1; + attribute C_PROBE_OUT145_INIT_VAL : string; + attribute C_PROBE_OUT145_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT145_WIDTH : integer; + attribute C_PROBE_OUT145_WIDTH of inst : label is 1; + attribute C_PROBE_OUT146_INIT_VAL : string; + attribute C_PROBE_OUT146_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT146_WIDTH : integer; + attribute C_PROBE_OUT146_WIDTH of inst : label is 1; + attribute C_PROBE_OUT147_INIT_VAL : string; + attribute C_PROBE_OUT147_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT147_WIDTH : integer; + attribute C_PROBE_OUT147_WIDTH of inst : label is 1; + attribute C_PROBE_OUT148_INIT_VAL : string; + attribute C_PROBE_OUT148_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT148_WIDTH : integer; + attribute C_PROBE_OUT148_WIDTH of inst : label is 1; + attribute C_PROBE_OUT149_INIT_VAL : string; + attribute C_PROBE_OUT149_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT149_WIDTH : integer; + attribute C_PROBE_OUT149_WIDTH of inst : label is 1; + attribute C_PROBE_OUT14_INIT_VAL : string; + attribute C_PROBE_OUT14_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT14_WIDTH : integer; + attribute C_PROBE_OUT14_WIDTH of inst : label is 1; + attribute C_PROBE_OUT150_INIT_VAL : string; + attribute C_PROBE_OUT150_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT150_WIDTH : integer; + attribute C_PROBE_OUT150_WIDTH of inst : label is 1; + attribute C_PROBE_OUT151_INIT_VAL : string; + attribute C_PROBE_OUT151_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT151_WIDTH : integer; + attribute C_PROBE_OUT151_WIDTH of inst : label is 1; + attribute C_PROBE_OUT152_INIT_VAL : string; + attribute C_PROBE_OUT152_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT152_WIDTH : integer; + attribute C_PROBE_OUT152_WIDTH of inst : label is 1; + attribute C_PROBE_OUT153_INIT_VAL : string; + attribute C_PROBE_OUT153_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT153_WIDTH : integer; + attribute C_PROBE_OUT153_WIDTH of inst : label is 1; + attribute C_PROBE_OUT154_INIT_VAL : string; + attribute C_PROBE_OUT154_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT154_WIDTH : integer; + attribute C_PROBE_OUT154_WIDTH of inst : label is 1; + attribute C_PROBE_OUT155_INIT_VAL : string; + attribute C_PROBE_OUT155_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT155_WIDTH : integer; + attribute C_PROBE_OUT155_WIDTH of inst : label is 1; + attribute C_PROBE_OUT156_INIT_VAL : string; + attribute C_PROBE_OUT156_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT156_WIDTH : integer; + attribute C_PROBE_OUT156_WIDTH of inst : label is 1; + attribute C_PROBE_OUT157_INIT_VAL : string; + attribute C_PROBE_OUT157_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT157_WIDTH : integer; + attribute C_PROBE_OUT157_WIDTH of inst : label is 1; + attribute C_PROBE_OUT158_INIT_VAL : string; + attribute C_PROBE_OUT158_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT158_WIDTH : integer; + attribute C_PROBE_OUT158_WIDTH of inst : label is 1; + attribute C_PROBE_OUT159_INIT_VAL : string; + attribute C_PROBE_OUT159_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT159_WIDTH : integer; + attribute C_PROBE_OUT159_WIDTH of inst : label is 1; + attribute C_PROBE_OUT15_INIT_VAL : string; + attribute C_PROBE_OUT15_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT15_WIDTH : integer; + attribute C_PROBE_OUT15_WIDTH of inst : label is 1; + attribute C_PROBE_OUT160_INIT_VAL : string; + attribute C_PROBE_OUT160_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT160_WIDTH : integer; + attribute C_PROBE_OUT160_WIDTH of inst : label is 1; + attribute C_PROBE_OUT161_INIT_VAL : string; + attribute C_PROBE_OUT161_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT161_WIDTH : integer; + attribute C_PROBE_OUT161_WIDTH of inst : label is 1; + attribute C_PROBE_OUT162_INIT_VAL : string; + attribute C_PROBE_OUT162_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT162_WIDTH : integer; + attribute C_PROBE_OUT162_WIDTH of inst : label is 1; + attribute C_PROBE_OUT163_INIT_VAL : string; + attribute C_PROBE_OUT163_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT163_WIDTH : integer; + attribute C_PROBE_OUT163_WIDTH of inst : label is 1; + attribute C_PROBE_OUT164_INIT_VAL : string; + attribute C_PROBE_OUT164_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT164_WIDTH : integer; + attribute C_PROBE_OUT164_WIDTH of inst : label is 1; + attribute C_PROBE_OUT165_INIT_VAL : string; + attribute C_PROBE_OUT165_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT165_WIDTH : integer; + attribute C_PROBE_OUT165_WIDTH of inst : label is 1; + attribute C_PROBE_OUT166_INIT_VAL : string; + attribute C_PROBE_OUT166_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT166_WIDTH : integer; + attribute C_PROBE_OUT166_WIDTH of inst : label is 1; + attribute C_PROBE_OUT167_INIT_VAL : string; + attribute C_PROBE_OUT167_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT167_WIDTH : integer; + attribute C_PROBE_OUT167_WIDTH of inst : label is 1; + attribute C_PROBE_OUT168_INIT_VAL : string; + attribute C_PROBE_OUT168_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT168_WIDTH : integer; + attribute C_PROBE_OUT168_WIDTH of inst : label is 1; + attribute C_PROBE_OUT169_INIT_VAL : string; + attribute C_PROBE_OUT169_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT169_WIDTH : integer; + attribute C_PROBE_OUT169_WIDTH of inst : label is 1; + attribute C_PROBE_OUT16_INIT_VAL : string; + attribute C_PROBE_OUT16_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT16_WIDTH : integer; + attribute C_PROBE_OUT16_WIDTH of inst : label is 1; + attribute C_PROBE_OUT170_INIT_VAL : string; + attribute C_PROBE_OUT170_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT170_WIDTH : integer; + attribute C_PROBE_OUT170_WIDTH of inst : label is 1; + attribute C_PROBE_OUT171_INIT_VAL : string; + attribute C_PROBE_OUT171_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT171_WIDTH : integer; + attribute C_PROBE_OUT171_WIDTH of inst : label is 1; + attribute C_PROBE_OUT172_INIT_VAL : string; + attribute C_PROBE_OUT172_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT172_WIDTH : integer; + attribute C_PROBE_OUT172_WIDTH of inst : label is 1; + attribute C_PROBE_OUT173_INIT_VAL : string; + attribute C_PROBE_OUT173_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT173_WIDTH : integer; + attribute C_PROBE_OUT173_WIDTH of inst : label is 1; + attribute C_PROBE_OUT174_INIT_VAL : string; + attribute C_PROBE_OUT174_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT174_WIDTH : integer; + attribute C_PROBE_OUT174_WIDTH of inst : label is 1; + attribute C_PROBE_OUT175_INIT_VAL : string; + attribute C_PROBE_OUT175_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT175_WIDTH : integer; + attribute C_PROBE_OUT175_WIDTH of inst : label is 1; + attribute C_PROBE_OUT176_INIT_VAL : string; + attribute C_PROBE_OUT176_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT176_WIDTH : integer; + attribute C_PROBE_OUT176_WIDTH of inst : label is 1; + attribute C_PROBE_OUT177_INIT_VAL : string; + attribute C_PROBE_OUT177_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT177_WIDTH : integer; + attribute C_PROBE_OUT177_WIDTH of inst : label is 1; + attribute C_PROBE_OUT178_INIT_VAL : string; + attribute C_PROBE_OUT178_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT178_WIDTH : integer; + attribute C_PROBE_OUT178_WIDTH of inst : label is 1; + attribute C_PROBE_OUT179_INIT_VAL : string; + attribute C_PROBE_OUT179_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT179_WIDTH : integer; + attribute C_PROBE_OUT179_WIDTH of inst : label is 1; + attribute C_PROBE_OUT17_INIT_VAL : string; + attribute C_PROBE_OUT17_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT17_WIDTH : integer; + attribute C_PROBE_OUT17_WIDTH of inst : label is 1; + attribute C_PROBE_OUT180_INIT_VAL : string; + attribute C_PROBE_OUT180_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT180_WIDTH : integer; + attribute C_PROBE_OUT180_WIDTH of inst : label is 1; + attribute C_PROBE_OUT181_INIT_VAL : string; + attribute C_PROBE_OUT181_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT181_WIDTH : integer; + attribute C_PROBE_OUT181_WIDTH of inst : label is 1; + attribute C_PROBE_OUT182_INIT_VAL : string; + attribute C_PROBE_OUT182_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT182_WIDTH : integer; + attribute C_PROBE_OUT182_WIDTH of inst : label is 1; + attribute C_PROBE_OUT183_INIT_VAL : string; + attribute C_PROBE_OUT183_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT183_WIDTH : integer; + attribute C_PROBE_OUT183_WIDTH of inst : label is 1; + attribute C_PROBE_OUT184_INIT_VAL : string; + attribute C_PROBE_OUT184_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT184_WIDTH : integer; + attribute C_PROBE_OUT184_WIDTH of inst : label is 1; + attribute C_PROBE_OUT185_INIT_VAL : string; + attribute C_PROBE_OUT185_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT185_WIDTH : integer; + attribute C_PROBE_OUT185_WIDTH of inst : label is 1; + attribute C_PROBE_OUT186_INIT_VAL : string; + attribute C_PROBE_OUT186_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT186_WIDTH : integer; + attribute C_PROBE_OUT186_WIDTH of inst : label is 1; + attribute C_PROBE_OUT187_INIT_VAL : string; + attribute C_PROBE_OUT187_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT187_WIDTH : integer; + attribute C_PROBE_OUT187_WIDTH of inst : label is 1; + attribute C_PROBE_OUT188_INIT_VAL : string; + attribute C_PROBE_OUT188_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT188_WIDTH : integer; + attribute C_PROBE_OUT188_WIDTH of inst : label is 1; + attribute C_PROBE_OUT189_INIT_VAL : string; + attribute C_PROBE_OUT189_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT189_WIDTH : integer; + attribute C_PROBE_OUT189_WIDTH of inst : label is 1; + attribute C_PROBE_OUT18_INIT_VAL : string; + attribute C_PROBE_OUT18_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT18_WIDTH : integer; + attribute C_PROBE_OUT18_WIDTH of inst : label is 1; + attribute C_PROBE_OUT190_INIT_VAL : string; + attribute C_PROBE_OUT190_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT190_WIDTH : integer; + attribute C_PROBE_OUT190_WIDTH of inst : label is 1; + attribute C_PROBE_OUT191_INIT_VAL : string; + attribute C_PROBE_OUT191_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT191_WIDTH : integer; + attribute C_PROBE_OUT191_WIDTH of inst : label is 1; + attribute C_PROBE_OUT192_INIT_VAL : string; + attribute C_PROBE_OUT192_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT192_WIDTH : integer; + attribute C_PROBE_OUT192_WIDTH of inst : label is 1; + attribute C_PROBE_OUT193_INIT_VAL : string; + attribute C_PROBE_OUT193_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT193_WIDTH : integer; + attribute C_PROBE_OUT193_WIDTH of inst : label is 1; + attribute C_PROBE_OUT194_INIT_VAL : string; + attribute C_PROBE_OUT194_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT194_WIDTH : integer; + attribute C_PROBE_OUT194_WIDTH of inst : label is 1; + attribute C_PROBE_OUT195_INIT_VAL : string; + attribute C_PROBE_OUT195_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT195_WIDTH : integer; + attribute C_PROBE_OUT195_WIDTH of inst : label is 1; + attribute C_PROBE_OUT196_INIT_VAL : string; + attribute C_PROBE_OUT196_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT196_WIDTH : integer; + attribute C_PROBE_OUT196_WIDTH of inst : label is 1; + attribute C_PROBE_OUT197_INIT_VAL : string; + attribute C_PROBE_OUT197_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT197_WIDTH : integer; + attribute C_PROBE_OUT197_WIDTH of inst : label is 1; + attribute C_PROBE_OUT198_INIT_VAL : string; + attribute C_PROBE_OUT198_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT198_WIDTH : integer; + attribute C_PROBE_OUT198_WIDTH of inst : label is 1; + attribute C_PROBE_OUT199_INIT_VAL : string; + attribute C_PROBE_OUT199_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT199_WIDTH : integer; + attribute C_PROBE_OUT199_WIDTH of inst : label is 1; + attribute C_PROBE_OUT19_INIT_VAL : string; + attribute C_PROBE_OUT19_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT19_WIDTH : integer; + attribute C_PROBE_OUT19_WIDTH of inst : label is 1; + attribute C_PROBE_OUT1_INIT_VAL : string; + attribute C_PROBE_OUT1_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT1_WIDTH : integer; + attribute C_PROBE_OUT1_WIDTH of inst : label is 1; + attribute C_PROBE_OUT200_INIT_VAL : string; + attribute C_PROBE_OUT200_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT200_WIDTH : integer; + attribute C_PROBE_OUT200_WIDTH of inst : label is 1; + attribute C_PROBE_OUT201_INIT_VAL : string; + attribute C_PROBE_OUT201_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT201_WIDTH : integer; + attribute C_PROBE_OUT201_WIDTH of inst : label is 1; + attribute C_PROBE_OUT202_INIT_VAL : string; + attribute C_PROBE_OUT202_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT202_WIDTH : integer; + attribute C_PROBE_OUT202_WIDTH of inst : label is 1; + attribute C_PROBE_OUT203_INIT_VAL : string; + attribute C_PROBE_OUT203_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT203_WIDTH : integer; + attribute C_PROBE_OUT203_WIDTH of inst : label is 1; + attribute C_PROBE_OUT204_INIT_VAL : string; + attribute C_PROBE_OUT204_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT204_WIDTH : integer; + attribute C_PROBE_OUT204_WIDTH of inst : label is 1; + attribute C_PROBE_OUT205_INIT_VAL : string; + attribute C_PROBE_OUT205_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT205_WIDTH : integer; + attribute C_PROBE_OUT205_WIDTH of inst : label is 1; + attribute C_PROBE_OUT206_INIT_VAL : string; + attribute C_PROBE_OUT206_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT206_WIDTH : integer; + attribute C_PROBE_OUT206_WIDTH of inst : label is 1; + attribute C_PROBE_OUT207_INIT_VAL : string; + attribute C_PROBE_OUT207_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT207_WIDTH : integer; + attribute C_PROBE_OUT207_WIDTH of inst : label is 1; + attribute C_PROBE_OUT208_INIT_VAL : string; + attribute C_PROBE_OUT208_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT208_WIDTH : integer; + attribute C_PROBE_OUT208_WIDTH of inst : label is 1; + attribute C_PROBE_OUT209_INIT_VAL : string; + attribute C_PROBE_OUT209_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT209_WIDTH : integer; + attribute C_PROBE_OUT209_WIDTH of inst : label is 1; + attribute C_PROBE_OUT20_INIT_VAL : string; + attribute C_PROBE_OUT20_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT20_WIDTH : integer; + attribute C_PROBE_OUT20_WIDTH of inst : label is 1; + attribute C_PROBE_OUT210_INIT_VAL : string; + attribute C_PROBE_OUT210_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT210_WIDTH : integer; + attribute C_PROBE_OUT210_WIDTH of inst : label is 1; + attribute C_PROBE_OUT211_INIT_VAL : string; + attribute C_PROBE_OUT211_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT211_WIDTH : integer; + attribute C_PROBE_OUT211_WIDTH of inst : label is 1; + attribute C_PROBE_OUT212_INIT_VAL : string; + attribute C_PROBE_OUT212_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT212_WIDTH : integer; + attribute C_PROBE_OUT212_WIDTH of inst : label is 1; + attribute C_PROBE_OUT213_INIT_VAL : string; + attribute C_PROBE_OUT213_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT213_WIDTH : integer; + attribute C_PROBE_OUT213_WIDTH of inst : label is 1; + attribute C_PROBE_OUT214_INIT_VAL : string; + attribute C_PROBE_OUT214_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT214_WIDTH : integer; + attribute C_PROBE_OUT214_WIDTH of inst : label is 1; + attribute C_PROBE_OUT215_INIT_VAL : string; + attribute C_PROBE_OUT215_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT215_WIDTH : integer; + attribute C_PROBE_OUT215_WIDTH of inst : label is 1; + attribute C_PROBE_OUT216_INIT_VAL : string; + attribute C_PROBE_OUT216_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT216_WIDTH : integer; + attribute C_PROBE_OUT216_WIDTH of inst : label is 1; + attribute C_PROBE_OUT217_INIT_VAL : string; + attribute C_PROBE_OUT217_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT217_WIDTH : integer; + attribute C_PROBE_OUT217_WIDTH of inst : label is 1; + attribute C_PROBE_OUT218_INIT_VAL : string; + attribute C_PROBE_OUT218_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT218_WIDTH : integer; + attribute C_PROBE_OUT218_WIDTH of inst : label is 1; + attribute C_PROBE_OUT219_INIT_VAL : string; + attribute C_PROBE_OUT219_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT219_WIDTH : integer; + attribute C_PROBE_OUT219_WIDTH of inst : label is 1; + attribute C_PROBE_OUT21_INIT_VAL : string; + attribute C_PROBE_OUT21_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT21_WIDTH : integer; + attribute C_PROBE_OUT21_WIDTH of inst : label is 1; + attribute C_PROBE_OUT220_INIT_VAL : string; + attribute C_PROBE_OUT220_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT220_WIDTH : integer; + attribute C_PROBE_OUT220_WIDTH of inst : label is 1; + attribute C_PROBE_OUT221_INIT_VAL : string; + attribute C_PROBE_OUT221_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT221_WIDTH : integer; + attribute C_PROBE_OUT221_WIDTH of inst : label is 1; + attribute C_PROBE_OUT222_INIT_VAL : string; + attribute C_PROBE_OUT222_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT222_WIDTH : integer; + attribute C_PROBE_OUT222_WIDTH of inst : label is 1; + attribute C_PROBE_OUT223_INIT_VAL : string; + attribute C_PROBE_OUT223_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT223_WIDTH : integer; + attribute C_PROBE_OUT223_WIDTH of inst : label is 1; + attribute C_PROBE_OUT224_INIT_VAL : string; + attribute C_PROBE_OUT224_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT224_WIDTH : integer; + attribute C_PROBE_OUT224_WIDTH of inst : label is 1; + attribute C_PROBE_OUT225_INIT_VAL : string; + attribute C_PROBE_OUT225_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT225_WIDTH : integer; + attribute C_PROBE_OUT225_WIDTH of inst : label is 1; + attribute C_PROBE_OUT226_INIT_VAL : string; + attribute C_PROBE_OUT226_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT226_WIDTH : integer; + attribute C_PROBE_OUT226_WIDTH of inst : label is 1; + attribute C_PROBE_OUT227_INIT_VAL : string; + attribute C_PROBE_OUT227_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT227_WIDTH : integer; + attribute C_PROBE_OUT227_WIDTH of inst : label is 1; + attribute C_PROBE_OUT228_INIT_VAL : string; + attribute C_PROBE_OUT228_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT228_WIDTH : integer; + attribute C_PROBE_OUT228_WIDTH of inst : label is 1; + attribute C_PROBE_OUT229_INIT_VAL : string; + attribute C_PROBE_OUT229_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT229_WIDTH : integer; + attribute C_PROBE_OUT229_WIDTH of inst : label is 1; + attribute C_PROBE_OUT22_INIT_VAL : string; + attribute C_PROBE_OUT22_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT22_WIDTH : integer; + attribute C_PROBE_OUT22_WIDTH of inst : label is 1; + attribute C_PROBE_OUT230_INIT_VAL : string; + attribute C_PROBE_OUT230_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT230_WIDTH : integer; + attribute C_PROBE_OUT230_WIDTH of inst : label is 1; + attribute C_PROBE_OUT231_INIT_VAL : string; + attribute C_PROBE_OUT231_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT231_WIDTH : integer; + attribute C_PROBE_OUT231_WIDTH of inst : label is 1; + attribute C_PROBE_OUT232_INIT_VAL : string; + attribute C_PROBE_OUT232_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT232_WIDTH : integer; + attribute C_PROBE_OUT232_WIDTH of inst : label is 1; + attribute C_PROBE_OUT233_INIT_VAL : string; + attribute C_PROBE_OUT233_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT233_WIDTH : integer; + attribute C_PROBE_OUT233_WIDTH of inst : label is 1; + attribute C_PROBE_OUT234_INIT_VAL : string; + attribute C_PROBE_OUT234_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT234_WIDTH : integer; + attribute C_PROBE_OUT234_WIDTH of inst : label is 1; + attribute C_PROBE_OUT235_INIT_VAL : string; + attribute C_PROBE_OUT235_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT235_WIDTH : integer; + attribute C_PROBE_OUT235_WIDTH of inst : label is 1; + attribute C_PROBE_OUT236_INIT_VAL : string; + attribute C_PROBE_OUT236_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT236_WIDTH : integer; + attribute C_PROBE_OUT236_WIDTH of inst : label is 1; + attribute C_PROBE_OUT237_INIT_VAL : string; + attribute C_PROBE_OUT237_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT237_WIDTH : integer; + attribute C_PROBE_OUT237_WIDTH of inst : label is 1; + attribute C_PROBE_OUT238_INIT_VAL : string; + attribute C_PROBE_OUT238_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT238_WIDTH : integer; + attribute C_PROBE_OUT238_WIDTH of inst : label is 1; + attribute C_PROBE_OUT239_INIT_VAL : string; + attribute C_PROBE_OUT239_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT239_WIDTH : integer; + attribute C_PROBE_OUT239_WIDTH of inst : label is 1; + attribute C_PROBE_OUT23_INIT_VAL : string; + attribute C_PROBE_OUT23_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT23_WIDTH : integer; + attribute C_PROBE_OUT23_WIDTH of inst : label is 1; + attribute C_PROBE_OUT240_INIT_VAL : string; + attribute C_PROBE_OUT240_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT240_WIDTH : integer; + attribute C_PROBE_OUT240_WIDTH of inst : label is 1; + attribute C_PROBE_OUT241_INIT_VAL : string; + attribute C_PROBE_OUT241_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT241_WIDTH : integer; + attribute C_PROBE_OUT241_WIDTH of inst : label is 1; + attribute C_PROBE_OUT242_INIT_VAL : string; + attribute C_PROBE_OUT242_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT242_WIDTH : integer; + attribute C_PROBE_OUT242_WIDTH of inst : label is 1; + attribute C_PROBE_OUT243_INIT_VAL : string; + attribute C_PROBE_OUT243_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT243_WIDTH : integer; + attribute C_PROBE_OUT243_WIDTH of inst : label is 1; + attribute C_PROBE_OUT244_INIT_VAL : string; + attribute C_PROBE_OUT244_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT244_WIDTH : integer; + attribute C_PROBE_OUT244_WIDTH of inst : label is 1; + attribute C_PROBE_OUT245_INIT_VAL : string; + attribute C_PROBE_OUT245_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT245_WIDTH : integer; + attribute C_PROBE_OUT245_WIDTH of inst : label is 1; + attribute C_PROBE_OUT246_INIT_VAL : string; + attribute C_PROBE_OUT246_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT246_WIDTH : integer; + attribute C_PROBE_OUT246_WIDTH of inst : label is 1; + attribute C_PROBE_OUT247_INIT_VAL : string; + attribute C_PROBE_OUT247_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT247_WIDTH : integer; + attribute C_PROBE_OUT247_WIDTH of inst : label is 1; + attribute C_PROBE_OUT248_INIT_VAL : string; + attribute C_PROBE_OUT248_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT248_WIDTH : integer; + attribute C_PROBE_OUT248_WIDTH of inst : label is 1; + attribute C_PROBE_OUT249_INIT_VAL : string; + attribute C_PROBE_OUT249_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT249_WIDTH : integer; + attribute C_PROBE_OUT249_WIDTH of inst : label is 1; + attribute C_PROBE_OUT24_INIT_VAL : string; + attribute C_PROBE_OUT24_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT24_WIDTH : integer; + attribute C_PROBE_OUT24_WIDTH of inst : label is 1; + attribute C_PROBE_OUT250_INIT_VAL : string; + attribute C_PROBE_OUT250_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT250_WIDTH : integer; + attribute C_PROBE_OUT250_WIDTH of inst : label is 1; + attribute C_PROBE_OUT251_INIT_VAL : string; + attribute C_PROBE_OUT251_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT251_WIDTH : integer; + attribute C_PROBE_OUT251_WIDTH of inst : label is 1; + attribute C_PROBE_OUT252_INIT_VAL : string; + attribute C_PROBE_OUT252_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT252_WIDTH : integer; + attribute C_PROBE_OUT252_WIDTH of inst : label is 1; + attribute C_PROBE_OUT253_INIT_VAL : string; + attribute C_PROBE_OUT253_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT253_WIDTH : integer; + attribute C_PROBE_OUT253_WIDTH of inst : label is 1; + attribute C_PROBE_OUT254_INIT_VAL : string; + attribute C_PROBE_OUT254_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT254_WIDTH : integer; + attribute C_PROBE_OUT254_WIDTH of inst : label is 1; + attribute C_PROBE_OUT255_INIT_VAL : string; + attribute C_PROBE_OUT255_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT255_WIDTH : integer; + attribute C_PROBE_OUT255_WIDTH of inst : label is 1; + attribute C_PROBE_OUT25_INIT_VAL : string; + attribute C_PROBE_OUT25_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT25_WIDTH : integer; + attribute C_PROBE_OUT25_WIDTH of inst : label is 1; + attribute C_PROBE_OUT26_INIT_VAL : string; + attribute C_PROBE_OUT26_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT26_WIDTH : integer; + attribute C_PROBE_OUT26_WIDTH of inst : label is 1; + attribute C_PROBE_OUT27_INIT_VAL : string; + attribute C_PROBE_OUT27_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT27_WIDTH : integer; + attribute C_PROBE_OUT27_WIDTH of inst : label is 1; + attribute C_PROBE_OUT28_INIT_VAL : string; + attribute C_PROBE_OUT28_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT28_WIDTH : integer; + attribute C_PROBE_OUT28_WIDTH of inst : label is 1; + attribute C_PROBE_OUT29_INIT_VAL : string; + attribute C_PROBE_OUT29_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT29_WIDTH : integer; + attribute C_PROBE_OUT29_WIDTH of inst : label is 1; + attribute C_PROBE_OUT2_INIT_VAL : string; + attribute C_PROBE_OUT2_INIT_VAL of inst : label is "32'b00000000000000000000000000000000"; + attribute C_PROBE_OUT2_WIDTH : integer; + attribute C_PROBE_OUT2_WIDTH of inst : label is 32; + attribute C_PROBE_OUT30_INIT_VAL : string; + attribute C_PROBE_OUT30_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT30_WIDTH : integer; + attribute C_PROBE_OUT30_WIDTH of inst : label is 1; + attribute C_PROBE_OUT31_INIT_VAL : string; + attribute C_PROBE_OUT31_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT31_WIDTH : integer; + attribute C_PROBE_OUT31_WIDTH of inst : label is 1; + attribute C_PROBE_OUT32_INIT_VAL : string; + attribute C_PROBE_OUT32_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT32_WIDTH : integer; + attribute C_PROBE_OUT32_WIDTH of inst : label is 1; + attribute C_PROBE_OUT33_INIT_VAL : string; + attribute C_PROBE_OUT33_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT33_WIDTH : integer; + attribute C_PROBE_OUT33_WIDTH of inst : label is 1; + attribute C_PROBE_OUT34_INIT_VAL : string; + attribute C_PROBE_OUT34_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT34_WIDTH : integer; + attribute C_PROBE_OUT34_WIDTH of inst : label is 1; + attribute C_PROBE_OUT35_INIT_VAL : string; + attribute C_PROBE_OUT35_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT35_WIDTH : integer; + attribute C_PROBE_OUT35_WIDTH of inst : label is 1; + attribute C_PROBE_OUT36_INIT_VAL : string; + attribute C_PROBE_OUT36_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT36_WIDTH : integer; + attribute C_PROBE_OUT36_WIDTH of inst : label is 1; + attribute C_PROBE_OUT37_INIT_VAL : string; + attribute C_PROBE_OUT37_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT37_WIDTH : integer; + attribute C_PROBE_OUT37_WIDTH of inst : label is 1; + attribute C_PROBE_OUT38_INIT_VAL : string; + attribute C_PROBE_OUT38_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT38_WIDTH : integer; + attribute C_PROBE_OUT38_WIDTH of inst : label is 1; + attribute C_PROBE_OUT39_INIT_VAL : string; + attribute C_PROBE_OUT39_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT39_WIDTH : integer; + attribute C_PROBE_OUT39_WIDTH of inst : label is 1; + attribute C_PROBE_OUT3_INIT_VAL : string; + attribute C_PROBE_OUT3_INIT_VAL of inst : label is "2'b11"; + attribute C_PROBE_OUT3_WIDTH : integer; + attribute C_PROBE_OUT3_WIDTH of inst : label is 2; + attribute C_PROBE_OUT40_INIT_VAL : string; + attribute C_PROBE_OUT40_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT40_WIDTH : integer; + attribute C_PROBE_OUT40_WIDTH of inst : label is 1; + attribute C_PROBE_OUT41_INIT_VAL : string; + attribute C_PROBE_OUT41_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT41_WIDTH : integer; + attribute C_PROBE_OUT41_WIDTH of inst : label is 1; + attribute C_PROBE_OUT42_INIT_VAL : string; + attribute C_PROBE_OUT42_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT42_WIDTH : integer; + attribute C_PROBE_OUT42_WIDTH of inst : label is 1; + attribute C_PROBE_OUT43_INIT_VAL : string; + attribute C_PROBE_OUT43_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT43_WIDTH : integer; + attribute C_PROBE_OUT43_WIDTH of inst : label is 1; + attribute C_PROBE_OUT44_INIT_VAL : string; + attribute C_PROBE_OUT44_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT44_WIDTH : integer; + attribute C_PROBE_OUT44_WIDTH of inst : label is 1; + attribute C_PROBE_OUT45_INIT_VAL : string; + attribute C_PROBE_OUT45_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT45_WIDTH : integer; + attribute C_PROBE_OUT45_WIDTH of inst : label is 1; + attribute C_PROBE_OUT46_INIT_VAL : string; + attribute C_PROBE_OUT46_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT46_WIDTH : integer; + attribute C_PROBE_OUT46_WIDTH of inst : label is 1; + attribute C_PROBE_OUT47_INIT_VAL : string; + attribute C_PROBE_OUT47_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT47_WIDTH : integer; + attribute C_PROBE_OUT47_WIDTH of inst : label is 1; + attribute C_PROBE_OUT48_INIT_VAL : string; + attribute C_PROBE_OUT48_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT48_WIDTH : integer; + attribute C_PROBE_OUT48_WIDTH of inst : label is 1; + attribute C_PROBE_OUT49_INIT_VAL : string; + attribute C_PROBE_OUT49_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT49_WIDTH : integer; + attribute C_PROBE_OUT49_WIDTH of inst : label is 1; + attribute C_PROBE_OUT4_INIT_VAL : string; + attribute C_PROBE_OUT4_INIT_VAL of inst : label is "4'b0000"; + attribute C_PROBE_OUT4_WIDTH : integer; + attribute C_PROBE_OUT4_WIDTH of inst : label is 4; + attribute C_PROBE_OUT50_INIT_VAL : string; + attribute C_PROBE_OUT50_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT50_WIDTH : integer; + attribute C_PROBE_OUT50_WIDTH of inst : label is 1; + attribute C_PROBE_OUT51_INIT_VAL : string; + attribute C_PROBE_OUT51_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT51_WIDTH : integer; + attribute C_PROBE_OUT51_WIDTH of inst : label is 1; + attribute C_PROBE_OUT52_INIT_VAL : string; + attribute C_PROBE_OUT52_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT52_WIDTH : integer; + attribute C_PROBE_OUT52_WIDTH of inst : label is 1; + attribute C_PROBE_OUT53_INIT_VAL : string; + attribute C_PROBE_OUT53_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT53_WIDTH : integer; + attribute C_PROBE_OUT53_WIDTH of inst : label is 1; + attribute C_PROBE_OUT54_INIT_VAL : string; + attribute C_PROBE_OUT54_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT54_WIDTH : integer; + attribute C_PROBE_OUT54_WIDTH of inst : label is 1; + attribute C_PROBE_OUT55_INIT_VAL : string; + attribute C_PROBE_OUT55_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT55_WIDTH : integer; + attribute C_PROBE_OUT55_WIDTH of inst : label is 1; + attribute C_PROBE_OUT56_INIT_VAL : string; + attribute C_PROBE_OUT56_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT56_WIDTH : integer; + attribute C_PROBE_OUT56_WIDTH of inst : label is 1; + attribute C_PROBE_OUT57_INIT_VAL : string; + attribute C_PROBE_OUT57_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT57_WIDTH : integer; + attribute C_PROBE_OUT57_WIDTH of inst : label is 1; + attribute C_PROBE_OUT58_INIT_VAL : string; + attribute C_PROBE_OUT58_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT58_WIDTH : integer; + attribute C_PROBE_OUT58_WIDTH of inst : label is 1; + attribute C_PROBE_OUT59_INIT_VAL : string; + attribute C_PROBE_OUT59_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT59_WIDTH : integer; + attribute C_PROBE_OUT59_WIDTH of inst : label is 1; + attribute C_PROBE_OUT5_INIT_VAL : string; + attribute C_PROBE_OUT5_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT5_WIDTH : integer; + attribute C_PROBE_OUT5_WIDTH of inst : label is 1; + attribute C_PROBE_OUT60_INIT_VAL : string; + attribute C_PROBE_OUT60_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT60_WIDTH : integer; + attribute C_PROBE_OUT60_WIDTH of inst : label is 1; + attribute C_PROBE_OUT61_INIT_VAL : string; + attribute C_PROBE_OUT61_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT61_WIDTH : integer; + attribute C_PROBE_OUT61_WIDTH of inst : label is 1; + attribute C_PROBE_OUT62_INIT_VAL : string; + attribute C_PROBE_OUT62_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT62_WIDTH : integer; + attribute C_PROBE_OUT62_WIDTH of inst : label is 1; + attribute C_PROBE_OUT63_INIT_VAL : string; + attribute C_PROBE_OUT63_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT63_WIDTH : integer; + attribute C_PROBE_OUT63_WIDTH of inst : label is 1; + attribute C_PROBE_OUT64_INIT_VAL : string; + attribute C_PROBE_OUT64_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT64_WIDTH : integer; + attribute C_PROBE_OUT64_WIDTH of inst : label is 1; + attribute C_PROBE_OUT65_INIT_VAL : string; + attribute C_PROBE_OUT65_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT65_WIDTH : integer; + attribute C_PROBE_OUT65_WIDTH of inst : label is 1; + attribute C_PROBE_OUT66_INIT_VAL : string; + attribute C_PROBE_OUT66_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT66_WIDTH : integer; + attribute C_PROBE_OUT66_WIDTH of inst : label is 1; + attribute C_PROBE_OUT67_INIT_VAL : string; + attribute C_PROBE_OUT67_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT67_WIDTH : integer; + attribute C_PROBE_OUT67_WIDTH of inst : label is 1; + attribute C_PROBE_OUT68_INIT_VAL : string; + attribute C_PROBE_OUT68_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT68_WIDTH : integer; + attribute C_PROBE_OUT68_WIDTH of inst : label is 1; + attribute C_PROBE_OUT69_INIT_VAL : string; + attribute C_PROBE_OUT69_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT69_WIDTH : integer; + attribute C_PROBE_OUT69_WIDTH of inst : label is 1; + attribute C_PROBE_OUT6_INIT_VAL : string; + attribute C_PROBE_OUT6_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT6_WIDTH : integer; + attribute C_PROBE_OUT6_WIDTH of inst : label is 1; + attribute C_PROBE_OUT70_INIT_VAL : string; + attribute C_PROBE_OUT70_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT70_WIDTH : integer; + attribute C_PROBE_OUT70_WIDTH of inst : label is 1; + attribute C_PROBE_OUT71_INIT_VAL : string; + attribute C_PROBE_OUT71_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT71_WIDTH : integer; + attribute C_PROBE_OUT71_WIDTH of inst : label is 1; + attribute C_PROBE_OUT72_INIT_VAL : string; + attribute C_PROBE_OUT72_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT72_WIDTH : integer; + attribute C_PROBE_OUT72_WIDTH of inst : label is 1; + attribute C_PROBE_OUT73_INIT_VAL : string; + attribute C_PROBE_OUT73_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT73_WIDTH : integer; + attribute C_PROBE_OUT73_WIDTH of inst : label is 1; + attribute C_PROBE_OUT74_INIT_VAL : string; + attribute C_PROBE_OUT74_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT74_WIDTH : integer; + attribute C_PROBE_OUT74_WIDTH of inst : label is 1; + attribute C_PROBE_OUT75_INIT_VAL : string; + attribute C_PROBE_OUT75_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT75_WIDTH : integer; + attribute C_PROBE_OUT75_WIDTH of inst : label is 1; + attribute C_PROBE_OUT76_INIT_VAL : string; + attribute C_PROBE_OUT76_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT76_WIDTH : integer; + attribute C_PROBE_OUT76_WIDTH of inst : label is 1; + attribute C_PROBE_OUT77_INIT_VAL : string; + attribute C_PROBE_OUT77_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT77_WIDTH : integer; + attribute C_PROBE_OUT77_WIDTH of inst : label is 1; + attribute C_PROBE_OUT78_INIT_VAL : string; + attribute C_PROBE_OUT78_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT78_WIDTH : integer; + attribute C_PROBE_OUT78_WIDTH of inst : label is 1; + attribute C_PROBE_OUT79_INIT_VAL : string; + attribute C_PROBE_OUT79_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT79_WIDTH : integer; + attribute C_PROBE_OUT79_WIDTH of inst : label is 1; + attribute C_PROBE_OUT7_INIT_VAL : string; + attribute C_PROBE_OUT7_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT7_WIDTH : integer; + attribute C_PROBE_OUT7_WIDTH of inst : label is 1; + attribute C_PROBE_OUT80_INIT_VAL : string; + attribute C_PROBE_OUT80_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT80_WIDTH : integer; + attribute C_PROBE_OUT80_WIDTH of inst : label is 1; + attribute C_PROBE_OUT81_INIT_VAL : string; + attribute C_PROBE_OUT81_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT81_WIDTH : integer; + attribute C_PROBE_OUT81_WIDTH of inst : label is 1; + attribute C_PROBE_OUT82_INIT_VAL : string; + attribute C_PROBE_OUT82_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT82_WIDTH : integer; + attribute C_PROBE_OUT82_WIDTH of inst : label is 1; + attribute C_PROBE_OUT83_INIT_VAL : string; + attribute C_PROBE_OUT83_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT83_WIDTH : integer; + attribute C_PROBE_OUT83_WIDTH of inst : label is 1; + attribute C_PROBE_OUT84_INIT_VAL : string; + attribute C_PROBE_OUT84_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT84_WIDTH : integer; + attribute C_PROBE_OUT84_WIDTH of inst : label is 1; + attribute C_PROBE_OUT85_INIT_VAL : string; + attribute C_PROBE_OUT85_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT85_WIDTH : integer; + attribute C_PROBE_OUT85_WIDTH of inst : label is 1; + attribute C_PROBE_OUT86_INIT_VAL : string; + attribute C_PROBE_OUT86_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT86_WIDTH : integer; + attribute C_PROBE_OUT86_WIDTH of inst : label is 1; + attribute C_PROBE_OUT87_INIT_VAL : string; + attribute C_PROBE_OUT87_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT87_WIDTH : integer; + attribute C_PROBE_OUT87_WIDTH of inst : label is 1; + attribute C_PROBE_OUT88_INIT_VAL : string; + attribute C_PROBE_OUT88_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT88_WIDTH : integer; + attribute C_PROBE_OUT88_WIDTH of inst : label is 1; + attribute C_PROBE_OUT89_INIT_VAL : string; + attribute C_PROBE_OUT89_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT89_WIDTH : integer; + attribute C_PROBE_OUT89_WIDTH of inst : label is 1; + attribute C_PROBE_OUT8_INIT_VAL : string; + attribute C_PROBE_OUT8_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT8_WIDTH : integer; + attribute C_PROBE_OUT8_WIDTH of inst : label is 1; + attribute C_PROBE_OUT90_INIT_VAL : string; + attribute C_PROBE_OUT90_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT90_WIDTH : integer; + attribute C_PROBE_OUT90_WIDTH of inst : label is 1; + attribute C_PROBE_OUT91_INIT_VAL : string; + attribute C_PROBE_OUT91_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT91_WIDTH : integer; + attribute C_PROBE_OUT91_WIDTH of inst : label is 1; + attribute C_PROBE_OUT92_INIT_VAL : string; + attribute C_PROBE_OUT92_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT92_WIDTH : integer; + attribute C_PROBE_OUT92_WIDTH of inst : label is 1; + attribute C_PROBE_OUT93_INIT_VAL : string; + attribute C_PROBE_OUT93_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT93_WIDTH : integer; + attribute C_PROBE_OUT93_WIDTH of inst : label is 1; + attribute C_PROBE_OUT94_INIT_VAL : string; + attribute C_PROBE_OUT94_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT94_WIDTH : integer; + attribute C_PROBE_OUT94_WIDTH of inst : label is 1; + attribute C_PROBE_OUT95_INIT_VAL : string; + attribute C_PROBE_OUT95_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT95_WIDTH : integer; + attribute C_PROBE_OUT95_WIDTH of inst : label is 1; + attribute C_PROBE_OUT96_INIT_VAL : string; + attribute C_PROBE_OUT96_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT96_WIDTH : integer; + attribute C_PROBE_OUT96_WIDTH of inst : label is 1; + attribute C_PROBE_OUT97_INIT_VAL : string; + attribute C_PROBE_OUT97_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT97_WIDTH : integer; + attribute C_PROBE_OUT97_WIDTH of inst : label is 1; + attribute C_PROBE_OUT98_INIT_VAL : string; + attribute C_PROBE_OUT98_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT98_WIDTH : integer; + attribute C_PROBE_OUT98_WIDTH of inst : label is 1; + attribute C_PROBE_OUT99_INIT_VAL : string; + attribute C_PROBE_OUT99_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT99_WIDTH : integer; + attribute C_PROBE_OUT99_WIDTH of inst : label is 1; + attribute C_PROBE_OUT9_INIT_VAL : string; + attribute C_PROBE_OUT9_INIT_VAL of inst : label is "1'b0"; + attribute C_PROBE_OUT9_WIDTH : integer; + attribute C_PROBE_OUT9_WIDTH of inst : label is 1; + attribute C_USE_TEST_REG : integer; + attribute C_USE_TEST_REG of inst : label is 1; + attribute C_XDEVICEFAMILY : string; + attribute C_XDEVICEFAMILY of inst : label is "kintex7"; + attribute C_XLNX_HW_PROBE_INFO : string; + attribute C_XLNX_HW_PROBE_INFO of inst : label is "DEFAULT"; + attribute C_XSDB_SLAVE_TYPE : integer; + attribute C_XSDB_SLAVE_TYPE of inst : label is 33; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of inst : label is std.standard.true; + attribute DowngradeIPIdentifiedWarnings : string; + attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; + attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000010001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000010001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000010001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000010001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000010001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000010001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000010001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000010001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000010010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000010010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000010010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000010010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000010010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000010010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000010010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000010010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000010011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000010011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000010011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000010011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000010011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000010011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000010011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000010011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000010100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000010100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000010100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000010100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010100110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010100111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010101000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000011000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000011000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000011000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000011000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000011000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000011000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000011000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000011000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000011001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000011001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000011001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000011001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000011001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000011001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000011001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000011001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000011010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000011010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000011010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000011010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000011010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000011010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000011010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000011010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000011011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000011011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000011011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000011011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000011011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000011011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000011011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000011011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000011100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000011100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000011100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000011100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011100110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011100111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011101000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000100000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000100000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000100000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000100000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000100000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000100000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000100000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000100000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000100001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000100001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000100001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000100001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000100001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000100001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000100001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000100001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000100010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000100010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000100010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000100010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000100010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000100010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000100010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000100010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000100011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000100011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000100011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000100011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000100011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000100011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000100011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000100011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000100100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000100100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000100100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000100100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000001000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000001000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000001000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000001000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000001000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000001000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000001000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000001000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000001001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000001001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000001001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000001001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000101000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000001001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000001001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000001001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000001001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000001010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000001010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000001010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000001010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000001010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000001010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000001010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000001010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000001011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000001011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000001011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000001011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000001011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000001011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000001011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000001011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000001100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000001100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000001100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000001100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001100110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001100111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001101000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000010000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000010000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000010000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000010000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000010000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000010000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000010000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string; + attribute LC_HIGH_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000010000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT0 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT1 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT10 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT100 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000010001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT101 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000010001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT102 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000010001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT103 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000010001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT104 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000010001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT105 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000010001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT106 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000010001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT107 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000010001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT108 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000010010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT109 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000010010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT11 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT110 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000010010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT111 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000010010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT112 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000010010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT113 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000010010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT114 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000010010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT115 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000010010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT116 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000010011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT117 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000010011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT118 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000010011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT119 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000010011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT12 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT120 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000010011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT121 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000010011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT122 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000010011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT123 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000010011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT124 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000010100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT125 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000010100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT126 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000010100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT127 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000010100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT128 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT129 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010100101"; + attribute LC_LOW_BIT_POS_PROBE_OUT13 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT130 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT131 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010100111"; + attribute LC_LOW_BIT_POS_PROBE_OUT132 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010101000"; + attribute LC_LOW_BIT_POS_PROBE_OUT133 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010101001"; + attribute LC_LOW_BIT_POS_PROBE_OUT134 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT135 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT136 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT137 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT138 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT139 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT14 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT140 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT141 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT142 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT143 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT144 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT145 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT146 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT147 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT148 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT149 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT15 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT150 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT151 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT152 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT153 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT154 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT155 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT156 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000011000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT157 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000011000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT158 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000011000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT159 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000011000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT16 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT160 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000011000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT161 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000011000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT162 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000011000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT163 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000011000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT164 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000011001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT165 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000011001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT166 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000011001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT167 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000011001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT168 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000011001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT169 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000011001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT17 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT170 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000011001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT171 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000011001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT172 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000011010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT173 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000011010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT174 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000011010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT175 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000011010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT176 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000011010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT177 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000011010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT178 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000011010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT179 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000011010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT18 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT180 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000011011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT181 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000011011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT182 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000011011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT183 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000011011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT184 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000011011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT185 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000011011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT186 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000011011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT187 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000011011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT188 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000011100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT189 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000011100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT19 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT190 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000011100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT191 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000011100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT192 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT193 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011100101"; + attribute LC_LOW_BIT_POS_PROBE_OUT194 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT195 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011100111"; + attribute LC_LOW_BIT_POS_PROBE_OUT196 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011101000"; + attribute LC_LOW_BIT_POS_PROBE_OUT197 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011101001"; + attribute LC_LOW_BIT_POS_PROBE_OUT198 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT199 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT2 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT20 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT200 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT201 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT202 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT203 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT204 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT205 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT206 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT207 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT208 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT209 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT21 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT210 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT211 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT212 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT213 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT214 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT215 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT216 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT217 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT218 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT219 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT22 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT220 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000100000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT221 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000100000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT222 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000100000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT223 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000100000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT224 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000100000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT225 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000100000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT226 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000100000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT227 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000100000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT228 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000100001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT229 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000100001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT23 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT230 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000100001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT231 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000100001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT232 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000100001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT233 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000100001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT234 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000100001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT235 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000100001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT236 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000100010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT237 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000100010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT238 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000100010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT239 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000100010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT24 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT240 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000100010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT241 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000100010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT242 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000100010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT243 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000100010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT244 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000100011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT245 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000100011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT246 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000100011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT247 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000100011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT248 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000100011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT249 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000100011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT25 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT250 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000100011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT251 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000100011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT252 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000100100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT253 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000100100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT254 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000100100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT255 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000100100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT26 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT27 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT28 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000001000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT29 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000001000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT3 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT30 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000001000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT31 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000001000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT32 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000001000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT33 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000001000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT34 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000001000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT35 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000001000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT36 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000001001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT37 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000001001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT38 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000001001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT39 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000001001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT4 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000100101"; + attribute LC_LOW_BIT_POS_PROBE_OUT40 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000001001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT41 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000001001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT42 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000001001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT43 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000001001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT44 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000001010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT45 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000001010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT46 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000001010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT47 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000001010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT48 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000001010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT49 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000001010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT5 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000101001"; + attribute LC_LOW_BIT_POS_PROBE_OUT50 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000001010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT51 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000001010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT52 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000001011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT53 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000001011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT54 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000001011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT55 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000001011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT56 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000001011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT57 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000001011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT58 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000001011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT59 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000001011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT6 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT60 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000001100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT61 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000001100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT62 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000001100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT63 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000001100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT64 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT65 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001100101"; + attribute LC_LOW_BIT_POS_PROBE_OUT66 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT67 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001100111"; + attribute LC_LOW_BIT_POS_PROBE_OUT68 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001101000"; + attribute LC_LOW_BIT_POS_PROBE_OUT69 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001101001"; + attribute LC_LOW_BIT_POS_PROBE_OUT7 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT70 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT71 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT72 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT73 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT74 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT75 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT76 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT77 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT78 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT79 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT8 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT80 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT81 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT82 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT83 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT84 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT85 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT86 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT87 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT88 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT89 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT9 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT90 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT91 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT92 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000010000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT93 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000010000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT94 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000010000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT95 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000010000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT96 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000010000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT97 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000010000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT98 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000010000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT99 : string; + attribute LC_LOW_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000010000111"; + attribute LC_PROBE_IN_WIDTH_STRING : string; + attribute LC_PROBE_IN_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string; + attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of inst : label is "4096'b0000000100100011000000010010001000000001001000010000000100100000000000010001111100000001000111100000000100011101000000010001110000000001000110110000000100011010000000010001100100000001000110000000000100010111000000010001011000000001000101010000000100010100000000010001001100000001000100100000000100010001000000010001000000000001000011110000000100001110000000010000110100000001000011000000000100001011000000010000101000000001000010010000000100001000000000010000011100000001000001100000000100000101000000010000010000000001000000110000000100000010000000010000000100000001000000000000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100100000000000010001000000000000000100000000000000001"; + attribute LC_PROBE_OUT_INIT_VAL_STRING : string; + attribute LC_PROBE_OUT_INIT_VAL_STRING of inst : label is "292'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000010"; + attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string; + attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of inst : label is "4096'b0000000100100011000000010010001000000001001000010000000100100000000000010001111100000001000111100000000100011101000000010001110000000001000110110000000100011010000000010001100100000001000110000000000100010111000000010001011000000001000101010000000100010100000000010001001100000001000100100000000100010001000000010001000000000001000011110000000100001110000000010000110100000001000011000000000100001011000000010000101000000001000010010000000100001000000000010000011100000001000001100000000100000101000000010000010000000001000000110000000100000010000000010000000100000001000000000000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001001010000000000100011000000000000001100000000000000100000000000000000"; + attribute LC_PROBE_OUT_WIDTH_STRING : string; + attribute LC_PROBE_OUT_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000001000111110000000000000001"; + attribute LC_TOTAL_PROBE_IN_WIDTH : integer; + attribute LC_TOTAL_PROBE_IN_WIDTH of inst : label is 0; + attribute LC_TOTAL_PROBE_OUT_WIDTH : integer; + attribute LC_TOTAL_PROBE_OUT_WIDTH of inst : label is 41; + attribute syn_noprune : string; + attribute syn_noprune of inst : label is "1"; +begin +inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_20_vio + port map ( + clk => clk, + probe_in0(0) => '0', + probe_in1(0) => '0', + probe_in10(0) => '0', + probe_in100(0) => '0', + probe_in101(0) => '0', + probe_in102(0) => '0', + probe_in103(0) => '0', + probe_in104(0) => '0', + probe_in105(0) => '0', + probe_in106(0) => '0', + probe_in107(0) => '0', + probe_in108(0) => '0', + probe_in109(0) => '0', + probe_in11(0) => '0', + probe_in110(0) => '0', + probe_in111(0) => '0', + probe_in112(0) => '0', + probe_in113(0) => '0', + probe_in114(0) => '0', + probe_in115(0) => '0', + probe_in116(0) => '0', + probe_in117(0) => '0', + probe_in118(0) => '0', + probe_in119(0) => '0', + probe_in12(0) => '0', + probe_in120(0) => '0', + probe_in121(0) => '0', + probe_in122(0) => '0', + probe_in123(0) => '0', + probe_in124(0) => '0', + probe_in125(0) => '0', + probe_in126(0) => '0', + probe_in127(0) => '0', + probe_in128(0) => '0', + probe_in129(0) => '0', + probe_in13(0) => '0', + probe_in130(0) => '0', + probe_in131(0) => '0', + probe_in132(0) => '0', + probe_in133(0) => '0', + probe_in134(0) => '0', + probe_in135(0) => '0', + probe_in136(0) => '0', + probe_in137(0) => '0', + probe_in138(0) => '0', + probe_in139(0) => '0', + probe_in14(0) => '0', + probe_in140(0) => '0', + probe_in141(0) => '0', + probe_in142(0) => '0', + probe_in143(0) => '0', + probe_in144(0) => '0', + probe_in145(0) => '0', + probe_in146(0) => '0', + probe_in147(0) => '0', + probe_in148(0) => '0', + probe_in149(0) => '0', + probe_in15(0) => '0', + probe_in150(0) => '0', + probe_in151(0) => '0', + probe_in152(0) => '0', + probe_in153(0) => '0', + probe_in154(0) => '0', + probe_in155(0) => '0', + probe_in156(0) => '0', + probe_in157(0) => '0', + probe_in158(0) => '0', + probe_in159(0) => '0', + probe_in16(0) => '0', + probe_in160(0) => '0', + probe_in161(0) => '0', + probe_in162(0) => '0', + probe_in163(0) => '0', + probe_in164(0) => '0', + probe_in165(0) => '0', + probe_in166(0) => '0', + probe_in167(0) => '0', + probe_in168(0) => '0', + probe_in169(0) => '0', + probe_in17(0) => '0', + probe_in170(0) => '0', + probe_in171(0) => '0', + probe_in172(0) => '0', + probe_in173(0) => '0', + probe_in174(0) => '0', + probe_in175(0) => '0', + probe_in176(0) => '0', + probe_in177(0) => '0', + probe_in178(0) => '0', + probe_in179(0) => '0', + probe_in18(0) => '0', + probe_in180(0) => '0', + probe_in181(0) => '0', + probe_in182(0) => '0', + probe_in183(0) => '0', + probe_in184(0) => '0', + probe_in185(0) => '0', + probe_in186(0) => '0', + probe_in187(0) => '0', + probe_in188(0) => '0', + probe_in189(0) => '0', + probe_in19(0) => '0', + probe_in190(0) => '0', + probe_in191(0) => '0', + probe_in192(0) => '0', + probe_in193(0) => '0', + probe_in194(0) => '0', + probe_in195(0) => '0', + probe_in196(0) => '0', + probe_in197(0) => '0', + probe_in198(0) => '0', + probe_in199(0) => '0', + probe_in2(0) => '0', + probe_in20(0) => '0', + probe_in200(0) => '0', + probe_in201(0) => '0', + probe_in202(0) => '0', + probe_in203(0) => '0', + probe_in204(0) => '0', + probe_in205(0) => '0', + probe_in206(0) => '0', + probe_in207(0) => '0', + probe_in208(0) => '0', + probe_in209(0) => '0', + probe_in21(0) => '0', + probe_in210(0) => '0', + probe_in211(0) => '0', + probe_in212(0) => '0', + probe_in213(0) => '0', + probe_in214(0) => '0', + probe_in215(0) => '0', + probe_in216(0) => '0', + probe_in217(0) => '0', + probe_in218(0) => '0', + probe_in219(0) => '0', + probe_in22(0) => '0', + probe_in220(0) => '0', + probe_in221(0) => '0', + probe_in222(0) => '0', + probe_in223(0) => '0', + probe_in224(0) => '0', + probe_in225(0) => '0', + probe_in226(0) => '0', + probe_in227(0) => '0', + probe_in228(0) => '0', + probe_in229(0) => '0', + probe_in23(0) => '0', + probe_in230(0) => '0', + probe_in231(0) => '0', + probe_in232(0) => '0', + probe_in233(0) => '0', + probe_in234(0) => '0', + probe_in235(0) => '0', + probe_in236(0) => '0', + probe_in237(0) => '0', + probe_in238(0) => '0', + probe_in239(0) => '0', + probe_in24(0) => '0', + probe_in240(0) => '0', + probe_in241(0) => '0', + probe_in242(0) => '0', + probe_in243(0) => '0', + probe_in244(0) => '0', + probe_in245(0) => '0', + probe_in246(0) => '0', + probe_in247(0) => '0', + probe_in248(0) => '0', + probe_in249(0) => '0', + probe_in25(0) => '0', + probe_in250(0) => '0', + probe_in251(0) => '0', + probe_in252(0) => '0', + probe_in253(0) => '0', + probe_in254(0) => '0', + probe_in255(0) => '0', + probe_in26(0) => '0', + probe_in27(0) => '0', + probe_in28(0) => '0', + probe_in29(0) => '0', + probe_in3(0) => '0', + probe_in30(0) => '0', + probe_in31(0) => '0', + probe_in32(0) => '0', + probe_in33(0) => '0', + probe_in34(0) => '0', + probe_in35(0) => '0', + probe_in36(0) => '0', + probe_in37(0) => '0', + probe_in38(0) => '0', + probe_in39(0) => '0', + probe_in4(0) => '0', + probe_in40(0) => '0', + probe_in41(0) => '0', + probe_in42(0) => '0', + probe_in43(0) => '0', + probe_in44(0) => '0', + probe_in45(0) => '0', + probe_in46(0) => '0', + probe_in47(0) => '0', + probe_in48(0) => '0', + probe_in49(0) => '0', + probe_in5(0) => '0', + probe_in50(0) => '0', + probe_in51(0) => '0', + probe_in52(0) => '0', + probe_in53(0) => '0', + probe_in54(0) => '0', + probe_in55(0) => '0', + probe_in56(0) => '0', + probe_in57(0) => '0', + probe_in58(0) => '0', + probe_in59(0) => '0', + probe_in6(0) => '0', + probe_in60(0) => '0', + probe_in61(0) => '0', + probe_in62(0) => '0', + probe_in63(0) => '0', + probe_in64(0) => '0', + probe_in65(0) => '0', + probe_in66(0) => '0', + probe_in67(0) => '0', + probe_in68(0) => '0', + probe_in69(0) => '0', + probe_in7(0) => '0', + probe_in70(0) => '0', + probe_in71(0) => '0', + probe_in72(0) => '0', + probe_in73(0) => '0', + probe_in74(0) => '0', + probe_in75(0) => '0', + probe_in76(0) => '0', + probe_in77(0) => '0', + probe_in78(0) => '0', + probe_in79(0) => '0', + probe_in8(0) => '0', + probe_in80(0) => '0', + probe_in81(0) => '0', + probe_in82(0) => '0', + probe_in83(0) => '0', + probe_in84(0) => '0', + probe_in85(0) => '0', + probe_in86(0) => '0', + probe_in87(0) => '0', + probe_in88(0) => '0', + probe_in89(0) => '0', + probe_in9(0) => '0', + probe_in90(0) => '0', + probe_in91(0) => '0', + probe_in92(0) => '0', + probe_in93(0) => '0', + probe_in94(0) => '0', + probe_in95(0) => '0', + probe_in96(0) => '0', + probe_in97(0) => '0', + probe_in98(0) => '0', + probe_in99(0) => '0', + probe_out0(1 downto 0) => probe_out0(1 downto 0), + probe_out1(0) => probe_out1(0), + probe_out10(0) => NLW_inst_probe_out10_UNCONNECTED(0), + probe_out100(0) => NLW_inst_probe_out100_UNCONNECTED(0), + probe_out101(0) => NLW_inst_probe_out101_UNCONNECTED(0), + probe_out102(0) => NLW_inst_probe_out102_UNCONNECTED(0), + probe_out103(0) => NLW_inst_probe_out103_UNCONNECTED(0), + probe_out104(0) => NLW_inst_probe_out104_UNCONNECTED(0), + probe_out105(0) => NLW_inst_probe_out105_UNCONNECTED(0), + probe_out106(0) => NLW_inst_probe_out106_UNCONNECTED(0), + probe_out107(0) => NLW_inst_probe_out107_UNCONNECTED(0), + probe_out108(0) => NLW_inst_probe_out108_UNCONNECTED(0), + probe_out109(0) => NLW_inst_probe_out109_UNCONNECTED(0), + probe_out11(0) => NLW_inst_probe_out11_UNCONNECTED(0), + probe_out110(0) => NLW_inst_probe_out110_UNCONNECTED(0), + probe_out111(0) => NLW_inst_probe_out111_UNCONNECTED(0), + probe_out112(0) => NLW_inst_probe_out112_UNCONNECTED(0), + probe_out113(0) => NLW_inst_probe_out113_UNCONNECTED(0), + probe_out114(0) => NLW_inst_probe_out114_UNCONNECTED(0), + probe_out115(0) => NLW_inst_probe_out115_UNCONNECTED(0), + probe_out116(0) => NLW_inst_probe_out116_UNCONNECTED(0), + probe_out117(0) => NLW_inst_probe_out117_UNCONNECTED(0), + probe_out118(0) => NLW_inst_probe_out118_UNCONNECTED(0), + probe_out119(0) => NLW_inst_probe_out119_UNCONNECTED(0), + probe_out12(0) => NLW_inst_probe_out12_UNCONNECTED(0), + probe_out120(0) => NLW_inst_probe_out120_UNCONNECTED(0), + probe_out121(0) => NLW_inst_probe_out121_UNCONNECTED(0), + probe_out122(0) => NLW_inst_probe_out122_UNCONNECTED(0), + probe_out123(0) => NLW_inst_probe_out123_UNCONNECTED(0), + probe_out124(0) => NLW_inst_probe_out124_UNCONNECTED(0), + probe_out125(0) => NLW_inst_probe_out125_UNCONNECTED(0), + probe_out126(0) => NLW_inst_probe_out126_UNCONNECTED(0), + probe_out127(0) => NLW_inst_probe_out127_UNCONNECTED(0), + probe_out128(0) => NLW_inst_probe_out128_UNCONNECTED(0), + probe_out129(0) => NLW_inst_probe_out129_UNCONNECTED(0), + probe_out13(0) => NLW_inst_probe_out13_UNCONNECTED(0), + probe_out130(0) => NLW_inst_probe_out130_UNCONNECTED(0), + probe_out131(0) => NLW_inst_probe_out131_UNCONNECTED(0), + probe_out132(0) => NLW_inst_probe_out132_UNCONNECTED(0), + probe_out133(0) => NLW_inst_probe_out133_UNCONNECTED(0), + probe_out134(0) => NLW_inst_probe_out134_UNCONNECTED(0), + probe_out135(0) => NLW_inst_probe_out135_UNCONNECTED(0), + probe_out136(0) => NLW_inst_probe_out136_UNCONNECTED(0), + probe_out137(0) => NLW_inst_probe_out137_UNCONNECTED(0), + probe_out138(0) => NLW_inst_probe_out138_UNCONNECTED(0), + probe_out139(0) => NLW_inst_probe_out139_UNCONNECTED(0), + probe_out14(0) => NLW_inst_probe_out14_UNCONNECTED(0), + probe_out140(0) => NLW_inst_probe_out140_UNCONNECTED(0), + probe_out141(0) => NLW_inst_probe_out141_UNCONNECTED(0), + probe_out142(0) => NLW_inst_probe_out142_UNCONNECTED(0), + probe_out143(0) => NLW_inst_probe_out143_UNCONNECTED(0), + probe_out144(0) => NLW_inst_probe_out144_UNCONNECTED(0), + probe_out145(0) => NLW_inst_probe_out145_UNCONNECTED(0), + probe_out146(0) => NLW_inst_probe_out146_UNCONNECTED(0), + probe_out147(0) => NLW_inst_probe_out147_UNCONNECTED(0), + probe_out148(0) => NLW_inst_probe_out148_UNCONNECTED(0), + probe_out149(0) => NLW_inst_probe_out149_UNCONNECTED(0), + probe_out15(0) => NLW_inst_probe_out15_UNCONNECTED(0), + probe_out150(0) => NLW_inst_probe_out150_UNCONNECTED(0), + probe_out151(0) => NLW_inst_probe_out151_UNCONNECTED(0), + probe_out152(0) => NLW_inst_probe_out152_UNCONNECTED(0), + probe_out153(0) => NLW_inst_probe_out153_UNCONNECTED(0), + probe_out154(0) => NLW_inst_probe_out154_UNCONNECTED(0), + probe_out155(0) => NLW_inst_probe_out155_UNCONNECTED(0), + probe_out156(0) => NLW_inst_probe_out156_UNCONNECTED(0), + probe_out157(0) => NLW_inst_probe_out157_UNCONNECTED(0), + probe_out158(0) => NLW_inst_probe_out158_UNCONNECTED(0), + probe_out159(0) => NLW_inst_probe_out159_UNCONNECTED(0), + probe_out16(0) => NLW_inst_probe_out16_UNCONNECTED(0), + probe_out160(0) => NLW_inst_probe_out160_UNCONNECTED(0), + probe_out161(0) => NLW_inst_probe_out161_UNCONNECTED(0), + probe_out162(0) => NLW_inst_probe_out162_UNCONNECTED(0), + probe_out163(0) => NLW_inst_probe_out163_UNCONNECTED(0), + probe_out164(0) => NLW_inst_probe_out164_UNCONNECTED(0), + probe_out165(0) => NLW_inst_probe_out165_UNCONNECTED(0), + probe_out166(0) => NLW_inst_probe_out166_UNCONNECTED(0), + probe_out167(0) => NLW_inst_probe_out167_UNCONNECTED(0), + probe_out168(0) => NLW_inst_probe_out168_UNCONNECTED(0), + probe_out169(0) => NLW_inst_probe_out169_UNCONNECTED(0), + probe_out17(0) => NLW_inst_probe_out17_UNCONNECTED(0), + probe_out170(0) => NLW_inst_probe_out170_UNCONNECTED(0), + probe_out171(0) => NLW_inst_probe_out171_UNCONNECTED(0), + probe_out172(0) => NLW_inst_probe_out172_UNCONNECTED(0), + probe_out173(0) => NLW_inst_probe_out173_UNCONNECTED(0), + probe_out174(0) => NLW_inst_probe_out174_UNCONNECTED(0), + probe_out175(0) => NLW_inst_probe_out175_UNCONNECTED(0), + probe_out176(0) => NLW_inst_probe_out176_UNCONNECTED(0), + probe_out177(0) => NLW_inst_probe_out177_UNCONNECTED(0), + probe_out178(0) => NLW_inst_probe_out178_UNCONNECTED(0), + probe_out179(0) => NLW_inst_probe_out179_UNCONNECTED(0), + probe_out18(0) => NLW_inst_probe_out18_UNCONNECTED(0), + probe_out180(0) => NLW_inst_probe_out180_UNCONNECTED(0), + probe_out181(0) => NLW_inst_probe_out181_UNCONNECTED(0), + probe_out182(0) => NLW_inst_probe_out182_UNCONNECTED(0), + probe_out183(0) => NLW_inst_probe_out183_UNCONNECTED(0), + probe_out184(0) => NLW_inst_probe_out184_UNCONNECTED(0), + probe_out185(0) => NLW_inst_probe_out185_UNCONNECTED(0), + probe_out186(0) => NLW_inst_probe_out186_UNCONNECTED(0), + probe_out187(0) => NLW_inst_probe_out187_UNCONNECTED(0), + probe_out188(0) => NLW_inst_probe_out188_UNCONNECTED(0), + probe_out189(0) => NLW_inst_probe_out189_UNCONNECTED(0), + probe_out19(0) => NLW_inst_probe_out19_UNCONNECTED(0), + probe_out190(0) => NLW_inst_probe_out190_UNCONNECTED(0), + probe_out191(0) => NLW_inst_probe_out191_UNCONNECTED(0), + probe_out192(0) => NLW_inst_probe_out192_UNCONNECTED(0), + probe_out193(0) => NLW_inst_probe_out193_UNCONNECTED(0), + probe_out194(0) => NLW_inst_probe_out194_UNCONNECTED(0), + probe_out195(0) => NLW_inst_probe_out195_UNCONNECTED(0), + probe_out196(0) => NLW_inst_probe_out196_UNCONNECTED(0), + probe_out197(0) => NLW_inst_probe_out197_UNCONNECTED(0), + probe_out198(0) => NLW_inst_probe_out198_UNCONNECTED(0), + probe_out199(0) => NLW_inst_probe_out199_UNCONNECTED(0), + probe_out2(31 downto 0) => probe_out2(31 downto 0), + probe_out20(0) => NLW_inst_probe_out20_UNCONNECTED(0), + probe_out200(0) => NLW_inst_probe_out200_UNCONNECTED(0), + probe_out201(0) => NLW_inst_probe_out201_UNCONNECTED(0), + probe_out202(0) => NLW_inst_probe_out202_UNCONNECTED(0), + probe_out203(0) => NLW_inst_probe_out203_UNCONNECTED(0), + probe_out204(0) => NLW_inst_probe_out204_UNCONNECTED(0), + probe_out205(0) => NLW_inst_probe_out205_UNCONNECTED(0), + probe_out206(0) => NLW_inst_probe_out206_UNCONNECTED(0), + probe_out207(0) => NLW_inst_probe_out207_UNCONNECTED(0), + probe_out208(0) => NLW_inst_probe_out208_UNCONNECTED(0), + probe_out209(0) => NLW_inst_probe_out209_UNCONNECTED(0), + probe_out21(0) => NLW_inst_probe_out21_UNCONNECTED(0), + probe_out210(0) => NLW_inst_probe_out210_UNCONNECTED(0), + probe_out211(0) => NLW_inst_probe_out211_UNCONNECTED(0), + probe_out212(0) => NLW_inst_probe_out212_UNCONNECTED(0), + probe_out213(0) => NLW_inst_probe_out213_UNCONNECTED(0), + probe_out214(0) => NLW_inst_probe_out214_UNCONNECTED(0), + probe_out215(0) => NLW_inst_probe_out215_UNCONNECTED(0), + probe_out216(0) => NLW_inst_probe_out216_UNCONNECTED(0), + probe_out217(0) => NLW_inst_probe_out217_UNCONNECTED(0), + probe_out218(0) => NLW_inst_probe_out218_UNCONNECTED(0), + probe_out219(0) => NLW_inst_probe_out219_UNCONNECTED(0), + probe_out22(0) => NLW_inst_probe_out22_UNCONNECTED(0), + probe_out220(0) => NLW_inst_probe_out220_UNCONNECTED(0), + probe_out221(0) => NLW_inst_probe_out221_UNCONNECTED(0), + probe_out222(0) => NLW_inst_probe_out222_UNCONNECTED(0), + probe_out223(0) => NLW_inst_probe_out223_UNCONNECTED(0), + probe_out224(0) => NLW_inst_probe_out224_UNCONNECTED(0), + probe_out225(0) => NLW_inst_probe_out225_UNCONNECTED(0), + probe_out226(0) => NLW_inst_probe_out226_UNCONNECTED(0), + probe_out227(0) => NLW_inst_probe_out227_UNCONNECTED(0), + probe_out228(0) => NLW_inst_probe_out228_UNCONNECTED(0), + probe_out229(0) => NLW_inst_probe_out229_UNCONNECTED(0), + probe_out23(0) => NLW_inst_probe_out23_UNCONNECTED(0), + probe_out230(0) => NLW_inst_probe_out230_UNCONNECTED(0), + probe_out231(0) => NLW_inst_probe_out231_UNCONNECTED(0), + probe_out232(0) => NLW_inst_probe_out232_UNCONNECTED(0), + probe_out233(0) => NLW_inst_probe_out233_UNCONNECTED(0), + probe_out234(0) => NLW_inst_probe_out234_UNCONNECTED(0), + probe_out235(0) => NLW_inst_probe_out235_UNCONNECTED(0), + probe_out236(0) => NLW_inst_probe_out236_UNCONNECTED(0), + probe_out237(0) => NLW_inst_probe_out237_UNCONNECTED(0), + probe_out238(0) => NLW_inst_probe_out238_UNCONNECTED(0), + probe_out239(0) => NLW_inst_probe_out239_UNCONNECTED(0), + probe_out24(0) => NLW_inst_probe_out24_UNCONNECTED(0), + probe_out240(0) => NLW_inst_probe_out240_UNCONNECTED(0), + probe_out241(0) => NLW_inst_probe_out241_UNCONNECTED(0), + probe_out242(0) => NLW_inst_probe_out242_UNCONNECTED(0), + probe_out243(0) => NLW_inst_probe_out243_UNCONNECTED(0), + probe_out244(0) => NLW_inst_probe_out244_UNCONNECTED(0), + probe_out245(0) => NLW_inst_probe_out245_UNCONNECTED(0), + probe_out246(0) => NLW_inst_probe_out246_UNCONNECTED(0), + probe_out247(0) => NLW_inst_probe_out247_UNCONNECTED(0), + probe_out248(0) => NLW_inst_probe_out248_UNCONNECTED(0), + probe_out249(0) => NLW_inst_probe_out249_UNCONNECTED(0), + probe_out25(0) => NLW_inst_probe_out25_UNCONNECTED(0), + probe_out250(0) => NLW_inst_probe_out250_UNCONNECTED(0), + probe_out251(0) => NLW_inst_probe_out251_UNCONNECTED(0), + probe_out252(0) => NLW_inst_probe_out252_UNCONNECTED(0), + probe_out253(0) => NLW_inst_probe_out253_UNCONNECTED(0), + probe_out254(0) => NLW_inst_probe_out254_UNCONNECTED(0), + probe_out255(0) => NLW_inst_probe_out255_UNCONNECTED(0), + probe_out26(0) => NLW_inst_probe_out26_UNCONNECTED(0), + probe_out27(0) => NLW_inst_probe_out27_UNCONNECTED(0), + probe_out28(0) => NLW_inst_probe_out28_UNCONNECTED(0), + probe_out29(0) => NLW_inst_probe_out29_UNCONNECTED(0), + probe_out3(1 downto 0) => probe_out3(1 downto 0), + probe_out30(0) => NLW_inst_probe_out30_UNCONNECTED(0), + probe_out31(0) => NLW_inst_probe_out31_UNCONNECTED(0), + probe_out32(0) => NLW_inst_probe_out32_UNCONNECTED(0), + probe_out33(0) => NLW_inst_probe_out33_UNCONNECTED(0), + probe_out34(0) => NLW_inst_probe_out34_UNCONNECTED(0), + probe_out35(0) => NLW_inst_probe_out35_UNCONNECTED(0), + probe_out36(0) => NLW_inst_probe_out36_UNCONNECTED(0), + probe_out37(0) => NLW_inst_probe_out37_UNCONNECTED(0), + probe_out38(0) => NLW_inst_probe_out38_UNCONNECTED(0), + probe_out39(0) => NLW_inst_probe_out39_UNCONNECTED(0), + probe_out4(3 downto 0) => probe_out4(3 downto 0), + probe_out40(0) => NLW_inst_probe_out40_UNCONNECTED(0), + probe_out41(0) => NLW_inst_probe_out41_UNCONNECTED(0), + probe_out42(0) => NLW_inst_probe_out42_UNCONNECTED(0), + probe_out43(0) => NLW_inst_probe_out43_UNCONNECTED(0), + probe_out44(0) => NLW_inst_probe_out44_UNCONNECTED(0), + probe_out45(0) => NLW_inst_probe_out45_UNCONNECTED(0), + probe_out46(0) => NLW_inst_probe_out46_UNCONNECTED(0), + probe_out47(0) => NLW_inst_probe_out47_UNCONNECTED(0), + probe_out48(0) => NLW_inst_probe_out48_UNCONNECTED(0), + probe_out49(0) => NLW_inst_probe_out49_UNCONNECTED(0), + probe_out5(0) => NLW_inst_probe_out5_UNCONNECTED(0), + probe_out50(0) => NLW_inst_probe_out50_UNCONNECTED(0), + probe_out51(0) => NLW_inst_probe_out51_UNCONNECTED(0), + probe_out52(0) => NLW_inst_probe_out52_UNCONNECTED(0), + probe_out53(0) => NLW_inst_probe_out53_UNCONNECTED(0), + probe_out54(0) => NLW_inst_probe_out54_UNCONNECTED(0), + probe_out55(0) => NLW_inst_probe_out55_UNCONNECTED(0), + probe_out56(0) => NLW_inst_probe_out56_UNCONNECTED(0), + probe_out57(0) => NLW_inst_probe_out57_UNCONNECTED(0), + probe_out58(0) => NLW_inst_probe_out58_UNCONNECTED(0), + probe_out59(0) => NLW_inst_probe_out59_UNCONNECTED(0), + probe_out6(0) => NLW_inst_probe_out6_UNCONNECTED(0), + probe_out60(0) => NLW_inst_probe_out60_UNCONNECTED(0), + probe_out61(0) => NLW_inst_probe_out61_UNCONNECTED(0), + probe_out62(0) => NLW_inst_probe_out62_UNCONNECTED(0), + probe_out63(0) => NLW_inst_probe_out63_UNCONNECTED(0), + probe_out64(0) => NLW_inst_probe_out64_UNCONNECTED(0), + probe_out65(0) => NLW_inst_probe_out65_UNCONNECTED(0), + probe_out66(0) => NLW_inst_probe_out66_UNCONNECTED(0), + probe_out67(0) => NLW_inst_probe_out67_UNCONNECTED(0), + probe_out68(0) => NLW_inst_probe_out68_UNCONNECTED(0), + probe_out69(0) => NLW_inst_probe_out69_UNCONNECTED(0), + probe_out7(0) => NLW_inst_probe_out7_UNCONNECTED(0), + probe_out70(0) => NLW_inst_probe_out70_UNCONNECTED(0), + probe_out71(0) => NLW_inst_probe_out71_UNCONNECTED(0), + probe_out72(0) => NLW_inst_probe_out72_UNCONNECTED(0), + probe_out73(0) => NLW_inst_probe_out73_UNCONNECTED(0), + probe_out74(0) => NLW_inst_probe_out74_UNCONNECTED(0), + probe_out75(0) => NLW_inst_probe_out75_UNCONNECTED(0), + probe_out76(0) => NLW_inst_probe_out76_UNCONNECTED(0), + probe_out77(0) => NLW_inst_probe_out77_UNCONNECTED(0), + probe_out78(0) => NLW_inst_probe_out78_UNCONNECTED(0), + probe_out79(0) => NLW_inst_probe_out79_UNCONNECTED(0), + probe_out8(0) => NLW_inst_probe_out8_UNCONNECTED(0), + probe_out80(0) => NLW_inst_probe_out80_UNCONNECTED(0), + probe_out81(0) => NLW_inst_probe_out81_UNCONNECTED(0), + probe_out82(0) => NLW_inst_probe_out82_UNCONNECTED(0), + probe_out83(0) => NLW_inst_probe_out83_UNCONNECTED(0), + probe_out84(0) => NLW_inst_probe_out84_UNCONNECTED(0), + probe_out85(0) => NLW_inst_probe_out85_UNCONNECTED(0), + probe_out86(0) => NLW_inst_probe_out86_UNCONNECTED(0), + probe_out87(0) => NLW_inst_probe_out87_UNCONNECTED(0), + probe_out88(0) => NLW_inst_probe_out88_UNCONNECTED(0), + probe_out89(0) => NLW_inst_probe_out89_UNCONNECTED(0), + probe_out9(0) => NLW_inst_probe_out9_UNCONNECTED(0), + probe_out90(0) => NLW_inst_probe_out90_UNCONNECTED(0), + probe_out91(0) => NLW_inst_probe_out91_UNCONNECTED(0), + probe_out92(0) => NLW_inst_probe_out92_UNCONNECTED(0), + probe_out93(0) => NLW_inst_probe_out93_UNCONNECTED(0), + probe_out94(0) => NLW_inst_probe_out94_UNCONNECTED(0), + probe_out95(0) => NLW_inst_probe_out95_UNCONNECTED(0), + probe_out96(0) => NLW_inst_probe_out96_UNCONNECTED(0), + probe_out97(0) => NLW_inst_probe_out97_UNCONNECTED(0), + probe_out98(0) => NLW_inst_probe_out98_UNCONNECTED(0), + probe_out99(0) => NLW_inst_probe_out99_UNCONNECTED(0), + sl_iport0(36 downto 0) => B"0000000000000000000000000000000000000", + sl_oport0(16 downto 0) => NLW_inst_sl_oport0_UNCONNECTED(16 downto 0) + ); +end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit_stub.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5d522090233ffcd/vio_manual_ctrl_stub.v similarity index 52% rename from projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit_stub.v rename to projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5d522090233ffcd/vio_manual_ctrl_stub.v index c3abbc51..e97e9abf 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit_stub.v +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5d522090233ffcd/vio_manual_ctrl_stub.v @@ -1,11 +1,11 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:34:22 2023 +// Date : Tue Mar 21 22:54:42 2023 // Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.v -// Design : COSLUT_10_16bit +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_stub.v +// Design : vio_manual_ctrl // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 // -------------------------------------------------------------------------------- @@ -13,13 +13,14 @@ // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. -(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) -module COSLUT_10_16bit(clka, addra, douta, clkb, addrb, doutb) -/* synthesis syn_black_box black_box_pad_pin="clka,addra[12:0],douta[17:0],clkb,addrb[12:0],doutb[17:0]" */; - input clka; - input [12:0]addra; - output [17:0]douta; - input clkb; - input [12:0]addrb; - output [17:0]doutb; +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_out0, probe_out1, probe_out2, + probe_out3, probe_out4) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */; + input clk; + output [1:0]probe_out0; + output [0:0]probe_out1; + output [31:0]probe_out2; + output [1:0]probe_out3; + output [3:0]probe_out4; endmodule diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5d522090233ffcd/vio_manual_ctrl_stub.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5d522090233ffcd/vio_manual_ctrl_stub.vhdl new file mode 100644 index 00000000..6374c55a --- /dev/null +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b5d522090233ffcd/vio_manual_ctrl_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Tue Mar 21 22:54:42 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_stub.vhdl +-- Design : vio_manual_ctrl +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf index c8546444..48fb4b84 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf @@ -1,40 +1,47 @@ version:1 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:37:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3132:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:39:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3137:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f70656e5f6d657373616765735f76696577:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6d6d616e6473696e7075745f747970655f74636c5f636f6d6d616e645f68657265:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7265747265657461626c6570616e656c5f636f72655f747265655f7461626c65:37:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e6d656e755f72657365745f616e645f67656e65726174655f6f75747075745f70726f6475637473:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:3135:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3836:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e6d656e755f72657365745f616e645f67656e65726174655f6f75747075745f70726f6475637473:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:3139:00:00 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b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf @@ -1,12 +1,14 @@ version:1 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6164646578697374696e67697068616e646c6572:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:31:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:32:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:35:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:35:00:00 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+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3133:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265706f72746970737461747573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:35:00:00 +eof:1443477536 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc index ccef59f4..94ba00c0 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc @@ -1,3 +1,3 @@ version:1 -6d6f64655f636f756e7465727c4755494d6f6465:9 +6d6f64655f636f756e7465727c4755494d6f6465:12 eof: diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf index fb22dd7f..297b1584 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf @@ -1,7 +1,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863376b343130746666673930302d32:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:696c615f7278:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:76696f5f6d616e75616c5f6374726c:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 @@ -33,8 +33,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30343a333373:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313538392e3733344d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313137362e3030344d42:00:00 -eof:1877898020 -05256063 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323073:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313039302e3837314d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3639372e3039344d42:00:00 +eof:1166853398 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml index ecb9f42e..7745f741 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -18,60 +18,69 @@ This means code written to parse this file will need to be revisited each subseq + - + - + - - + + + - - + + + - - - + + + - + + + + + - + + + - + - - + + - + - + - +
diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_8.xml b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_8.xml new file mode 100644 index 00000000..eb74415e --- /dev/null +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/.Vivado_Synthesis.queue.rst b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/.Vivado_Synthesis.queue.rst deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/.vivado.begin.rst b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/.vivado.begin.rst deleted file mode 100644 index 00fa2a6d..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/.vivado.end.rst b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/.vivado.end.rst deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit.dcp b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit.dcp deleted file mode 100644 index dad66e95..00000000 Binary files a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit.dcp and /dev/null differ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit.tcl b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit.tcl deleted file mode 100644 index 789579e0..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit.tcl +++ /dev/null @@ -1,156 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param general.maxThreads 20 -set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64 -set_param project.vivado.isBlockSynthRun true -set_msg_config -msgmgr_mode ooc_run -create_project -in_memory -part xc7k410tffg900-2 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] -set_property parent.project_path D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.xpr [current_project] -set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language Verilog [current_project] -set_property ip_output_repo d:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit.xci -set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit_ooc.xdc] - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -read_xdc dont_touch.xdc -set_property used_in_implementation false [get_files dont_touch.xdc] -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1 -new_name COSLUT_10_16bit -ip [get_ips COSLUT_10_16bit]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top COSLUT_10_16bit -part xc7k410tffg900-2 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix COSLUT_10_16bit_ COSLUT_10_16bit.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ COSLUT_10_16bit_stub.v - lappend ipCachedFiles COSLUT_10_16bit_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ COSLUT_10_16bit_stub.vhdl - lappend ipCachedFiles COSLUT_10_16bit_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ COSLUT_10_16bit_sim_netlist.v - lappend ipCachedFiles COSLUT_10_16bit_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ COSLUT_10_16bit_sim_netlist.vhdl - lappend ipCachedFiles COSLUT_10_16bit_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp COSLUT_10_16bit.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips COSLUT_10_16bit] -} - -rename_ref -prefix_all COSLUT_10_16bit_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef COSLUT_10_16bit.dcp -create_report "COSLUT_10_16bit_synth_1_synth_report_utilization_0" "report_utilization -file COSLUT_10_16bit_utilization_synth.rpt -pb COSLUT_10_16bit_utilization_synth.pb" - -if { [catch { - write_verilog -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -}; # end if cached_ip - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_sim_netlist.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit.dcp -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit.xci] - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/COSLUT_10_16bit]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_sim_netlist.v D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/COSLUT_10_16bit - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/COSLUT_10_16bit]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_sim_netlist.vhdl D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/COSLUT_10_16bit - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/COSLUT_10_16bit]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.v D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/COSLUT_10_16bit - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/COSLUT_10_16bit]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.vhdl D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/COSLUT_10_16bit - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit.vds b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit.vds deleted file mode 100644 index e5bed02c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit.vds +++ /dev/null @@ -1,497 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Sat Mar 18 23:32:54 2023 -# Process ID: 32368 -# Current directory: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1 -# Command line: vivado.exe -log COSLUT_10_16bit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source COSLUT_10_16bit.tcl -# Log file: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit.vds -# Journal file: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1\vivado.jou -#----------------------------------------------------------- -Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl' -source COSLUT_10_16bit.tcl -notrace -Command: synth_design -top COSLUT_10_16bit -part xc7k410tffg900-2 -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' -INFO: [Device 21-403] Loading part xc7k410tffg900-2 -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 18236 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:10 . Memory (MB): peak = 884.746 ; gain = 176.859 ---------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'COSLUT_10_16bit' [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/COSLUT_10_16bit/synth/COSLUT_10_16bit.vhd:70] - Parameter C_FAMILY bound to: kintex7 - type: string - Parameter C_XDEVICEFAMILY bound to: kintex7 - type: string - Parameter C_ELABORATION_DIR bound to: ./ - type: string - Parameter C_INTERFACE_TYPE bound to: 0 - type: integer - Parameter C_AXI_TYPE bound to: 1 - type: integer - Parameter C_AXI_SLAVE_TYPE bound to: 0 - type: integer - Parameter C_USE_BRAM_BLOCK bound to: 0 - type: integer - Parameter C_ENABLE_32BIT_ADDRESS bound to: 0 - type: integer - Parameter C_CTRL_ECC_ALGO bound to: NONE - type: string - Parameter C_HAS_AXI_ID bound to: 0 - type: integer - Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer - Parameter C_MEM_TYPE bound to: 4 - type: integer - Parameter C_BYTE_SIZE bound to: 9 - type: integer - Parameter C_ALGORITHM bound to: 1 - type: integer - Parameter C_PRIM_TYPE bound to: 1 - type: integer - Parameter C_LOAD_INIT_FILE bound to: 1 - type: integer - Parameter C_INIT_FILE_NAME bound to: COSLUT_10_16bit.mif - type: string - Parameter C_INIT_FILE bound to: COSLUT_10_16bit.mem - type: string - Parameter C_USE_DEFAULT_DATA bound to: 0 - type: integer - Parameter C_DEFAULT_DATA bound to: 0 - type: string - Parameter C_HAS_RSTA bound to: 0 - type: integer - Parameter C_RST_PRIORITY_A bound to: CE - type: string - Parameter C_RSTRAM_A bound to: 0 - type: integer - Parameter C_INITA_VAL bound to: 0 - type: string - Parameter C_HAS_ENA bound to: 0 - type: integer - Parameter C_HAS_REGCEA bound to: 0 - type: integer - Parameter C_USE_BYTE_WEA bound to: 0 - type: integer - Parameter C_WEA_WIDTH bound to: 1 - type: integer - Parameter C_WRITE_MODE_A bound to: WRITE_FIRST - type: string - Parameter C_WRITE_WIDTH_A bound to: 18 - type: integer - Parameter C_READ_WIDTH_A bound to: 18 - type: integer - Parameter C_WRITE_DEPTH_A bound to: 8192 - type: integer - Parameter C_READ_DEPTH_A bound to: 8192 - type: integer - Parameter C_ADDRA_WIDTH bound to: 13 - type: integer - Parameter C_HAS_RSTB bound to: 0 - type: integer - Parameter C_RST_PRIORITY_B bound to: CE - type: string - Parameter C_RSTRAM_B bound to: 0 - type: integer - Parameter C_INITB_VAL bound to: 0 - type: string - Parameter C_HAS_ENB bound to: 0 - type: integer - Parameter C_HAS_REGCEB bound to: 0 - type: integer - Parameter C_USE_BYTE_WEB bound to: 0 - type: integer - Parameter C_WEB_WIDTH bound to: 1 - type: integer - Parameter C_WRITE_MODE_B bound to: WRITE_FIRST - type: string - Parameter C_WRITE_WIDTH_B bound to: 18 - type: integer - Parameter C_READ_WIDTH_B bound to: 18 - type: integer - Parameter C_WRITE_DEPTH_B bound to: 8192 - type: integer - Parameter C_READ_DEPTH_B bound to: 8192 - type: integer - Parameter C_ADDRB_WIDTH bound to: 13 - type: integer - Parameter C_HAS_MEM_OUTPUT_REGS_A bound to: 1 - type: integer - Parameter C_HAS_MEM_OUTPUT_REGS_B bound to: 1 - type: integer - Parameter C_HAS_MUX_OUTPUT_REGS_A bound to: 1 - type: integer - Parameter C_HAS_MUX_OUTPUT_REGS_B bound to: 1 - type: integer - Parameter C_MUX_PIPELINE_STAGES bound to: 0 - type: integer - Parameter C_HAS_SOFTECC_INPUT_REGS_A bound to: 0 - type: integer - Parameter C_HAS_SOFTECC_OUTPUT_REGS_B bound to: 0 - type: integer - Parameter C_USE_SOFTECC bound to: 0 - type: integer - Parameter C_USE_ECC bound to: 0 - type: integer - Parameter C_EN_ECC_PIPE bound to: 0 - type: integer - Parameter C_READ_LATENCY_A bound to: 1 - type: integer - Parameter C_READ_LATENCY_B bound to: 1 - type: integer - Parameter C_HAS_INJECTERR bound to: 0 - type: integer - Parameter C_SIM_COLLISION_CHECK bound to: ALL - type: string - Parameter C_COMMON_CLK bound to: 0 - type: integer - Parameter C_DISABLE_WARN_BHV_COLL bound to: 0 - type: integer - Parameter C_EN_SLEEP_PIN bound to: 0 - type: integer - Parameter C_USE_URAM bound to: 0 - type: integer - Parameter C_EN_RDADDRA_CHG bound to: 0 - type: integer - Parameter C_EN_RDADDRB_CHG bound to: 0 - type: integer - Parameter C_EN_DEEPSLEEP_PIN bound to: 0 - type: integer - Parameter C_EN_SHUTDOWN_PIN bound to: 0 - type: integer - Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer - Parameter C_DISABLE_WARN_BHV_RANGE bound to: 0 - type: integer - Parameter C_COUNT_36K_BRAM bound to: 4 - type: string - Parameter C_COUNT_18K_BRAM bound to: 0 - type: string - Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP : 9.414399 mW - type: string -INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_3' declared at 'd:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/COSLUT_10_16bit/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195321' bound to instance 'U0' of component 'blk_mem_gen_v8_4_3' [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/COSLUT_10_16bit/synth/COSLUT_10_16bit.vhd:237] -INFO: [Synth 8-256] done synthesizing module 'COSLUT_10_16bit' (11#1) [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/COSLUT_10_16bit/synth/COSLUT_10_16bit.vhd:70] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port MEM_LAT_RST -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port WE -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[12] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[11] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[10] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[9] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[8] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[7] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[6] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[5] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[4] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[3] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[2] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[1] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[0] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[3] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[2] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[1] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[0] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[3] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[2] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[1] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port DBITERRIN[0] -WARNING: [Synth 8-3331] design blk_mem_gen_mux__parameterized0 has unconnected port ECCPIPECE -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port MEM_LAT_RST -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port WE -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port ADDR_IN[12] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port ADDR_IN[11] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port ADDR_IN[10] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port ADDR_IN[9] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port ADDR_IN[8] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port ADDR_IN[7] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port ADDR_IN[6] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port ADDR_IN[5] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port ADDR_IN[4] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port ADDR_IN[3] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port ADDR_IN[2] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port ADDR_IN[1] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port ADDR_IN[0] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port SBITERRIN[3] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port SBITERRIN[2] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port SBITERRIN[1] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port SBITERRIN[0] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port DBITERRIN[3] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port DBITERRIN[2] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port DBITERRIN[1] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port DBITERRIN[0] -WARNING: [Synth 8-3331] design blk_mem_gen_mux has unconnected port ECCPIPECE -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port SSRA -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port SSRB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port SLEEP -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port INJECTSBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port INJECTDBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized2 has unconnected port ECCPIPECE -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized1 has unconnected port SSRA -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized1 has unconnected port SSRB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized1 has unconnected port SLEEP -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized1 has unconnected port INJECTSBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized1 has unconnected port INJECTDBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized1 has unconnected port ECCPIPECE -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port SSRA -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port SSRB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port SLEEP -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port INJECTSBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port INJECTDBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init__parameterized0 has unconnected port ECCPIPECE -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRA -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SLEEP -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port INJECTSBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port INJECTDBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ECCPIPECE -WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port RSTA[1] -WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port RSTA[0] -WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port RSTB[1] -WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port RSTB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port INJECTSBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port INJECTDBITERR -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port CLKB -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port SBITERR_I -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DBITERR_I -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[12] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[11] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[10] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[9] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[8] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[7] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[6] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[5] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[4] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[3] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[2] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[1] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[0] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port RSTA -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port ENA -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port REGCEA -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port WEA[0] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[17] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[16] -INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:44 ; elapsed = 00:00:57 . Memory (MB): peak = 1165.465 ; gain = 457.578 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:44 ; elapsed = 00:00:57 . Memory (MB): peak = 1165.465 ; gain = 457.578 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:44 ; elapsed = 00:00:57 . Memory (MB): peak = 1165.465 ; gain = 457.578 ---------------------------------------------------------------------------------- -INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization - -Processing XDC Constraints -Initializing timing engine -Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit_ooc.xdc] for cell 'U0' -Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit_ooc.xdc] for cell 'U0' -Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/dont_touch.xdc] -Finished Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/dont_touch.xdc] -Completed Processing XDC Constraints - -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1194.652 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1194.707 ; gain = 0.055 ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:49 ; elapsed = 00:01:03 . Memory (MB): peak = 1194.707 ; gain = 486.820 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7k410tffg900-2 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:49 ; elapsed = 00:01:03 . Memory (MB): peak = 1194.707 ; gain = 486.820 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying 'set_property' XDC Constraints ---------------------------------------------------------------------------------- -Applied set_property DONT_TOUCH = true for U0. (constraint file D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/dont_touch.xdc, line 9). ---------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:49 ; elapsed = 00:01:03 . Memory (MB): peak = 1194.707 ; gain = 486.820 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:49 ; elapsed = 00:01:04 . Memory (MB): peak = 1194.707 ; gain = 486.820 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : -+---Registers : - 18 Bit Registers := 2 - 13 Bit Registers := 4 - 1 Bit Registers := 6 -+---Muxes : - 2 Input 18 Bit Muxes := 2 - 2 Input 1 Bit Muxes := 10 ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- -Hierarchical RTL Component report -Module bindec -Detailed RTL Component Info : -+---Muxes : - 2 Input 1 Bit Muxes := 2 -Module blk_mem_gen_mux -Detailed RTL Component Info : -+---Registers : - 18 Bit Registers := 1 - 13 Bit Registers := 2 - 1 Bit Registers := 3 -+---Muxes : - 2 Input 18 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 3 -Module blk_mem_gen_mux__parameterized0 -Detailed RTL Component Info : -+---Registers : - 18 Bit Registers := 1 - 13 Bit Registers := 2 - 1 Bit Registers := 3 -+---Muxes : - 2 Input 18 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 3 ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 1540 (col length:140) -BRAMs: 1590 (col length: RAMB18 140 RAMB36 70) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:50 ; elapsed = 00:01:05 . Memory (MB): peak = 1194.707 ; gain = 486.820 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Applying XDC Timing Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:54 ; elapsed = 00:01:11 . Memory (MB): peak = 1194.707 ; gain = 486.820 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:54 ; elapsed = 00:01:11 . Memory (MB): peak = 1194.707 ; gain = 486.820 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:54 ; elapsed = 00:01:11 . Memory (MB): peak = 1194.707 ; gain = 486.820 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:56 ; elapsed = 00:01:13 . Memory (MB): peak = 1194.707 ; gain = 486.820 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:56 ; elapsed = 00:01:13 . Memory (MB): peak = 1194.707 ; gain = 486.820 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:56 ; elapsed = 00:01:13 . Memory (MB): peak = 1194.707 ; gain = 486.820 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:56 ; elapsed = 00:01:13 . Memory (MB): peak = 1194.707 ; gain = 486.820 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:56 ; elapsed = 00:01:13 . Memory (MB): peak = 1194.707 ; gain = 486.820 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:56 ; elapsed = 00:01:13 . Memory (MB): peak = 1194.707 ; gain = 486.820 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+-----------+------+ -| |Cell |Count | -+------+-----------+------+ -|1 |LUT1 | 2| -|2 |LUT3 | 36| -|3 |RAMB36E1 | 1| -|4 |RAMB36E1_1 | 1| -|5 |RAMB36E1_2 | 1| -|6 |RAMB36E1_3 | 1| -|7 |FDRE | 40| -+------+-----------+------+ - -Report Instance Areas: -+------+---------------------------------------------+----------------------------------------------+------+ -| |Instance |Module |Cells | -+------+---------------------------------------------+----------------------------------------------+------+ -|1 |top | | 82| -|2 | U0 |blk_mem_gen_v8_4_3 | 82| -|3 | inst_blk_mem_gen |blk_mem_gen_v8_4_3_synth | 82| -|4 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_top | 82| -|5 | \valid.cstr |blk_mem_gen_generic_cstr | 82| -|6 | \has_mux_a.A |blk_mem_gen_mux | 38| -|7 | \has_mux_b.B |blk_mem_gen_mux__parameterized0 | 38| -|8 | \ramloop[0].ram.r |blk_mem_gen_prim_width | 1| -|9 | \prim_init.ram |blk_mem_gen_prim_wrapper_init | 1| -|10 | \ramloop[1].ram.r |blk_mem_gen_prim_width__parameterized0 | 1| -|11 | \prim_init.ram |blk_mem_gen_prim_wrapper_init__parameterized0 | 1| -|12 | \ramloop[2].ram.r |blk_mem_gen_prim_width__parameterized1 | 3| -|13 | \prim_init.ram |blk_mem_gen_prim_wrapper_init__parameterized1 | 3| -|14 | \ramloop[3].ram.r |blk_mem_gen_prim_width__parameterized2 | 1| -|15 | \prim_init.ram |blk_mem_gen_prim_wrapper_init__parameterized2 | 1| -+------+---------------------------------------------+----------------------------------------------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:56 ; elapsed = 00:01:13 . Memory (MB): peak = 1194.707 ; gain = 486.820 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 176 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:01:10 . Memory (MB): peak = 1194.707 ; gain = 457.578 -Synthesis Optimization Complete : Time (s): cpu = 00:00:56 ; elapsed = 00:01:13 . Memory (MB): peak = 1194.707 ; gain = 486.820 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1197.273 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -17 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:01:01 ; elapsed = 00:01:21 . Memory (MB): peak = 1197.273 ; gain = 810.555 -INFO: [Common 17-600] The following parameters have non-default value. -general.maxThreads -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1197.273 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit.dcp' has been generated. -WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP COSLUT_10_16bit, cache-ID = bad0cfd1050e82a4 -INFO: [Coretcl 2-1174] Renamed 14 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1197.273 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file COSLUT_10_16bit_utilization_synth.rpt -pb COSLUT_10_16bit_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sat Mar 18 23:34:22 2023... diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_sim_netlist.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_sim_netlist.v deleted file mode 100644 index b277c79f..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_sim_netlist.v +++ /dev/null @@ -1,2445 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:34:22 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_sim_netlist.v -// Design : COSLUT_10_16bit -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* CHECK_LICENSE_TYPE = "COSLUT_10_16bit,blk_mem_gen_v8_4_3,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) -(* NotValidForBitStream *) -module COSLUT_10_16bit - (clka, - addra, - douta, - clkb, - addrb, - doutb); - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) input clka; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [12:0]addra; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [17:0]douta; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) input clkb; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input [12:0]addrb; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output [17:0]doutb; - - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [17:0]douta; - wire [17:0]doutb; - wire NLW_U0_dbiterr_UNCONNECTED; - wire NLW_U0_rsta_busy_UNCONNECTED; - wire NLW_U0_rstb_busy_UNCONNECTED; - wire NLW_U0_s_axi_arready_UNCONNECTED; - wire NLW_U0_s_axi_awready_UNCONNECTED; - wire NLW_U0_s_axi_bvalid_UNCONNECTED; - wire NLW_U0_s_axi_dbiterr_UNCONNECTED; - wire NLW_U0_s_axi_rlast_UNCONNECTED; - wire NLW_U0_s_axi_rvalid_UNCONNECTED; - wire NLW_U0_s_axi_sbiterr_UNCONNECTED; - wire NLW_U0_s_axi_wready_UNCONNECTED; - wire NLW_U0_sbiterr_UNCONNECTED; - wire [12:0]NLW_U0_rdaddrecc_UNCONNECTED; - wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED; - wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; - wire [12:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED; - wire [17:0]NLW_U0_s_axi_rdata_UNCONNECTED; - wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED; - wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; - - (* C_ADDRA_WIDTH = "13" *) - (* C_ADDRB_WIDTH = "13" *) - (* C_ALGORITHM = "1" *) - (* C_AXI_ID_WIDTH = "4" *) - (* C_AXI_SLAVE_TYPE = "0" *) - (* C_AXI_TYPE = "1" *) - (* C_BYTE_SIZE = "9" *) - (* C_COMMON_CLK = "0" *) - (* C_COUNT_18K_BRAM = "0" *) - (* C_COUNT_36K_BRAM = "4" *) - (* C_CTRL_ECC_ALGO = "NONE" *) - (* C_DEFAULT_DATA = "0" *) - (* C_DISABLE_WARN_BHV_COLL = "0" *) - (* C_DISABLE_WARN_BHV_RANGE = "0" *) - (* C_ELABORATION_DIR = "./" *) - (* C_ENABLE_32BIT_ADDRESS = "0" *) - (* C_EN_DEEPSLEEP_PIN = "0" *) - (* C_EN_ECC_PIPE = "0" *) - (* C_EN_RDADDRA_CHG = "0" *) - (* C_EN_RDADDRB_CHG = "0" *) - (* C_EN_SAFETY_CKT = "0" *) - (* C_EN_SHUTDOWN_PIN = "0" *) - (* C_EN_SLEEP_PIN = "0" *) - (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 9.414399 mW" *) - (* C_FAMILY = "kintex7" *) - (* C_HAS_AXI_ID = "0" *) - (* C_HAS_ENA = "0" *) - (* C_HAS_ENB = "0" *) - (* C_HAS_INJECTERR = "0" *) - (* C_HAS_MEM_OUTPUT_REGS_A = "1" *) - (* C_HAS_MEM_OUTPUT_REGS_B = "1" *) - (* C_HAS_MUX_OUTPUT_REGS_A = "1" *) - (* C_HAS_MUX_OUTPUT_REGS_B = "1" *) - (* C_HAS_REGCEA = "0" *) - (* C_HAS_REGCEB = "0" *) - (* C_HAS_RSTA = "0" *) - (* C_HAS_RSTB = "0" *) - (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) - (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) - (* C_INITA_VAL = "0" *) - (* C_INITB_VAL = "0" *) - (* C_INIT_FILE = "COSLUT_10_16bit.mem" *) - (* C_INIT_FILE_NAME = "COSLUT_10_16bit.mif" *) - (* C_INTERFACE_TYPE = "0" *) - (* C_LOAD_INIT_FILE = "1" *) - (* C_MEM_TYPE = "4" *) - (* C_MUX_PIPELINE_STAGES = "0" *) - (* C_PRIM_TYPE = "1" *) - (* C_READ_DEPTH_A = "8192" *) - (* C_READ_DEPTH_B = "8192" *) - (* C_READ_LATENCY_A = "1" *) - (* C_READ_LATENCY_B = "1" *) - (* C_READ_WIDTH_A = "18" *) - (* C_READ_WIDTH_B = "18" *) - (* C_RSTRAM_A = "0" *) - (* C_RSTRAM_B = "0" *) - (* C_RST_PRIORITY_A = "CE" *) - (* C_RST_PRIORITY_B = "CE" *) - (* C_SIM_COLLISION_CHECK = "ALL" *) - (* C_USE_BRAM_BLOCK = "0" *) - (* C_USE_BYTE_WEA = "0" *) - (* C_USE_BYTE_WEB = "0" *) - (* C_USE_DEFAULT_DATA = "0" *) - (* C_USE_ECC = "0" *) - (* C_USE_SOFTECC = "0" *) - (* C_USE_URAM = "0" *) - (* C_WEA_WIDTH = "1" *) - (* C_WEB_WIDTH = "1" *) - (* C_WRITE_DEPTH_A = "8192" *) - (* C_WRITE_DEPTH_B = "8192" *) - (* C_WRITE_MODE_A = "WRITE_FIRST" *) - (* C_WRITE_MODE_B = "WRITE_FIRST" *) - (* C_WRITE_WIDTH_A = "18" *) - (* C_WRITE_WIDTH_B = "18" *) - (* C_XDEVICEFAMILY = "kintex7" *) - (* downgradeipidentifiedwarnings = "yes" *) - COSLUT_10_16bit_blk_mem_gen_v8_4_3 U0 - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .dbiterr(NLW_U0_dbiterr_UNCONNECTED), - .deepsleep(1'b0), - .dina({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .douta(douta), - .doutb(doutb), - .eccpipece(1'b0), - .ena(1'b0), - .enb(1'b0), - .injectdbiterr(1'b0), - .injectsbiterr(1'b0), - .rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[12:0]), - .regcea(1'b0), - .regceb(1'b0), - .rsta(1'b0), - .rsta_busy(NLW_U0_rsta_busy_UNCONNECTED), - .rstb(1'b0), - .rstb_busy(NLW_U0_rstb_busy_UNCONNECTED), - .s_aclk(1'b0), - .s_aresetn(1'b0), - .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_arburst({1'b0,1'b0}), - .s_axi_arid({1'b0,1'b0,1'b0,1'b0}), - .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED), - .s_axi_arsize({1'b0,1'b0,1'b0}), - .s_axi_arvalid(1'b0), - .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_awburst({1'b0,1'b0}), - .s_axi_awid({1'b0,1'b0,1'b0,1'b0}), - .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED), - .s_axi_awsize({1'b0,1'b0,1'b0}), - .s_axi_awvalid(1'b0), - .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]), - .s_axi_bready(1'b0), - .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]), - .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED), - .s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED), - .s_axi_injectdbiterr(1'b0), - .s_axi_injectsbiterr(1'b0), - .s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[12:0]), - .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[17:0]), - .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]), - .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED), - .s_axi_rready(1'b0), - .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]), - .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED), - .s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED), - .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_wlast(1'b0), - .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED), - .s_axi_wstrb(1'b0), - .s_axi_wvalid(1'b0), - .sbiterr(NLW_U0_sbiterr_UNCONNECTED), - .shutdown(1'b0), - .sleep(1'b0), - .wea(1'b0), - .web(1'b0)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) -module COSLUT_10_16bit_blk_mem_gen_generic_cstr - (douta, - doutb, - clka, - clkb, - addra, - addrb); - output [17:0]douta; - output [17:0]doutb; - input clka; - input clkb; - input [12:0]addra; - input [12:0]addrb; - - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [17:0]douta; - wire [35:0]douta_array; - wire [17:0]doutb; - wire [35:0]doutb_array; - wire [0:0]ena_array; - wire [0:0]enb_array; - - COSLUT_10_16bit_blk_mem_gen_mux \has_mux_a.A - (.addra(addra[12]), - .clka(clka), - .douta(douta), - .douta_array(douta_array)); - COSLUT_10_16bit_blk_mem_gen_mux__parameterized0 \has_mux_b.B - (.addrb(addrb[12]), - .clkb(clkb), - .doutb(doutb), - .doutb_array(doutb_array)); - COSLUT_10_16bit_blk_mem_gen_prim_width \ramloop[0].ram.r - (.addra(addra[11:0]), - .addrb(addrb[11:0]), - .clka(clka), - .clkb(clkb), - .douta_array(douta_array[8:0]), - .doutb_array(doutb_array[8:0]), - .ena_array(ena_array), - .enb_array(enb_array)); - COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .douta_array(douta_array[26:18]), - .doutb_array(doutb_array[26:18])); - COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .douta_array(douta_array[17:9]), - .doutb_array(doutb_array[17:9]), - .ena_array(ena_array), - .enb_array(enb_array)); - COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .douta_array(douta_array[35:27]), - .doutb_array(doutb_array[35:27])); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_mux" *) -module COSLUT_10_16bit_blk_mem_gen_mux - (douta, - addra, - clka, - douta_array); - output [17:0]douta; - input [0:0]addra; - input clka; - input [35:0]douta_array; - - wire [0:0]addra; - wire clka; - wire [17:0]dout_pipe; - wire [17:0]douta; - wire [35:0]douta_array; - wire sel_pipe; - wire sel_pipe_d1; - - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[0]_i_1 - (.I0(douta_array[18]), - .I1(sel_pipe_d1), - .I2(douta_array[0]), - .O(dout_pipe[0])); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[10]_i_1 - (.I0(douta_array[28]), - .I1(sel_pipe_d1), - .I2(douta_array[10]), - .O(dout_pipe[10])); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[11]_i_1 - (.I0(douta_array[29]), - .I1(sel_pipe_d1), - .I2(douta_array[11]), - .O(dout_pipe[11])); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[12]_i_1 - (.I0(douta_array[30]), - .I1(sel_pipe_d1), - .I2(douta_array[12]), - .O(dout_pipe[12])); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[13]_i_1 - (.I0(douta_array[31]), - .I1(sel_pipe_d1), - .I2(douta_array[13]), - .O(dout_pipe[13])); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[14]_i_1 - (.I0(douta_array[32]), - .I1(sel_pipe_d1), - .I2(douta_array[14]), - .O(dout_pipe[14])); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[15]_i_1 - (.I0(douta_array[33]), - .I1(sel_pipe_d1), - .I2(douta_array[15]), - .O(dout_pipe[15])); - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[16]_i_1 - (.I0(douta_array[34]), - .I1(sel_pipe_d1), - .I2(douta_array[16]), - .O(dout_pipe[16])); - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[17]_i_1 - (.I0(douta_array[35]), - .I1(sel_pipe_d1), - .I2(douta_array[17]), - .O(dout_pipe[17])); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[1]_i_1 - (.I0(douta_array[19]), - .I1(sel_pipe_d1), - .I2(douta_array[1]), - .O(dout_pipe[1])); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[2]_i_1 - (.I0(douta_array[20]), - .I1(sel_pipe_d1), - .I2(douta_array[2]), - .O(dout_pipe[2])); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[3]_i_1 - (.I0(douta_array[21]), - .I1(sel_pipe_d1), - .I2(douta_array[3]), - .O(dout_pipe[3])); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[4]_i_1 - (.I0(douta_array[22]), - .I1(sel_pipe_d1), - .I2(douta_array[4]), - .O(dout_pipe[4])); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[5]_i_1 - (.I0(douta_array[23]), - .I1(sel_pipe_d1), - .I2(douta_array[5]), - .O(dout_pipe[5])); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[6]_i_1 - (.I0(douta_array[24]), - .I1(sel_pipe_d1), - .I2(douta_array[6]), - .O(dout_pipe[6])); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[7]_i_1 - (.I0(douta_array[25]), - .I1(sel_pipe_d1), - .I2(douta_array[7]), - .O(dout_pipe[7])); - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[8]_i_1 - (.I0(douta_array[26]), - .I1(sel_pipe_d1), - .I2(douta_array[8]), - .O(dout_pipe[8])); - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[9]_i_1 - (.I0(douta_array[27]), - .I1(sel_pipe_d1), - .I2(douta_array[9]), - .O(dout_pipe[9])); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[0] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[0]), - .Q(douta[0]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[10] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[10]), - .Q(douta[10]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[11] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[11]), - .Q(douta[11]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[12] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[12]), - .Q(douta[12]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[13] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[13]), - .Q(douta[13]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[14] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[14]), - .Q(douta[14]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[15] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[15]), - .Q(douta[15]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[16] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[16]), - .Q(douta[16]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[17] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[17]), - .Q(douta[17]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[1] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[1]), - .Q(douta[1]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[2] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[2]), - .Q(douta[2]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[3] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[3]), - .Q(douta[3]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[4] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[4]), - .Q(douta[4]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[5] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[5]), - .Q(douta[5]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[6] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[6]), - .Q(douta[6]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[7] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[7]), - .Q(douta[7]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[8] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[8]), - .Q(douta[8]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[9] - (.C(clka), - .CE(1'b1), - .D(dout_pipe[9]), - .Q(douta[9]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0] - (.C(clka), - .CE(1'b1), - .D(sel_pipe), - .Q(sel_pipe_d1), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] - (.C(clka), - .CE(1'b1), - .D(addra), - .Q(sel_pipe), - .R(1'b0)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_mux" *) -module COSLUT_10_16bit_blk_mem_gen_mux__parameterized0 - (doutb, - addrb, - clkb, - doutb_array); - output [17:0]doutb; - input [0:0]addrb; - input clkb; - input [35:0]doutb_array; - - wire [0:0]addrb; - wire clkb; - wire [17:0]doutb; - wire [35:0]doutb_array; - wire \no_softecc_gmuxr.ce_pri.dout_i[0]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[10]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[11]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[12]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[13]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[14]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[15]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[16]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[17]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[1]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[2]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[3]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[4]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[5]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[6]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[7]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[8]_i_1_n_0 ; - wire \no_softecc_gmuxr.ce_pri.dout_i[9]_i_1_n_0 ; - wire \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ; - wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0] ; - - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[0]_i_1 - (.I0(doutb_array[18]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[0]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[10]_i_1 - (.I0(doutb_array[28]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[10]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[10]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[11]_i_1 - (.I0(doutb_array[29]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[11]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[11]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[12]_i_1 - (.I0(doutb_array[30]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[12]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[12]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[13]_i_1 - (.I0(doutb_array[31]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[13]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[13]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair16" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[14]_i_1 - (.I0(doutb_array[32]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[14]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[14]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair16" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[15]_i_1 - (.I0(doutb_array[33]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[15]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[15]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair17" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[16]_i_1 - (.I0(doutb_array[34]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[16]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[16]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair17" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[17]_i_1 - (.I0(doutb_array[35]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[17]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[17]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[1]_i_1 - (.I0(doutb_array[19]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[1]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[1]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[2]_i_1 - (.I0(doutb_array[20]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[2]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[2]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[3]_i_1 - (.I0(doutb_array[21]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[3]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[3]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair11" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[4]_i_1 - (.I0(doutb_array[22]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[4]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[4]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair11" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[5]_i_1 - (.I0(doutb_array[23]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[5]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[5]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[6]_i_1 - (.I0(doutb_array[24]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[6]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[6]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[7]_i_1 - (.I0(doutb_array[25]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[7]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[7]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[8]_i_1 - (.I0(doutb_array[26]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[8]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[8]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT3 #( - .INIT(8'hB8)) - \no_softecc_gmuxr.ce_pri.dout_i[9]_i_1 - (.I0(doutb_array[27]), - .I1(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .I2(doutb_array[9]), - .O(\no_softecc_gmuxr.ce_pri.dout_i[9]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[0] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[0]_i_1_n_0 ), - .Q(doutb[0]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[10] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[10]_i_1_n_0 ), - .Q(doutb[10]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[11] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[11]_i_1_n_0 ), - .Q(doutb[11]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[12] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[12]_i_1_n_0 ), - .Q(doutb[12]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[13] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[13]_i_1_n_0 ), - .Q(doutb[13]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[14] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[14]_i_1_n_0 ), - .Q(doutb[14]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[15] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[15]_i_1_n_0 ), - .Q(doutb[15]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[16] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[16]_i_1_n_0 ), - .Q(doutb[16]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[17] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[17]_i_1_n_0 ), - .Q(doutb[17]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[1] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[1]_i_1_n_0 ), - .Q(doutb[1]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[2] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[2]_i_1_n_0 ), - .Q(doutb[2]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[3] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[3]_i_1_n_0 ), - .Q(doutb[3]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[4] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[4]_i_1_n_0 ), - .Q(doutb[4]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[5] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[5]_i_1_n_0 ), - .Q(doutb[5]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[6] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[6]_i_1_n_0 ), - .Q(doutb[6]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[7] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[7]_i_1_n_0 ), - .Q(doutb[7]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[8] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[8]_i_1_n_0 ), - .Q(doutb[8]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_gmuxr.ce_pri.dout_i_reg[9] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_gmuxr.ce_pri.dout_i[9]_i_1_n_0 ), - .Q(doutb[9]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0] - (.C(clkb), - .CE(1'b1), - .D(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0] ), - .Q(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] - (.C(clkb), - .CE(1'b1), - .D(addrb), - .Q(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0] ), - .R(1'b0)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) -module COSLUT_10_16bit_blk_mem_gen_prim_width - (douta_array, - doutb_array, - clka, - clkb, - ena_array, - enb_array, - addra, - addrb); - output [8:0]douta_array; - output [8:0]doutb_array; - input clka; - input clkb; - input [0:0]ena_array; - input [0:0]enb_array; - input [11:0]addra; - input [11:0]addrb; - - wire [11:0]addra; - wire [11:0]addrb; - wire clka; - wire clkb; - wire [8:0]douta_array; - wire [8:0]doutb_array; - wire [0:0]ena_array; - wire [0:0]enb_array; - - COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init \prim_init.ram - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .douta_array(douta_array), - .doutb_array(doutb_array), - .ena_array(ena_array), - .enb_array(enb_array)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) -module COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized0 - (douta_array, - doutb_array, - clka, - clkb, - addra, - addrb); - output [8:0]douta_array; - output [8:0]doutb_array; - input clka; - input clkb; - input [12:0]addra; - input [12:0]addrb; - - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [8:0]douta_array; - wire [8:0]doutb_array; - - COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized0 \prim_init.ram - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .douta_array(douta_array), - .doutb_array(doutb_array)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) -module COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized1 - (douta_array, - doutb_array, - ena_array, - enb_array, - clka, - clkb, - addra, - addrb); - output [8:0]douta_array; - output [8:0]doutb_array; - output [0:0]ena_array; - output [0:0]enb_array; - input clka; - input clkb; - input [12:0]addra; - input [12:0]addrb; - - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [8:0]douta_array; - wire [8:0]doutb_array; - wire [0:0]ena_array; - wire [0:0]enb_array; - - COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized1 \prim_init.ram - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .douta_array(douta_array), - .doutb_array(doutb_array), - .ena_array(ena_array), - .enb_array(enb_array)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) -module COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized2 - (douta_array, - doutb_array, - clka, - clkb, - addra, - addrb); - output [8:0]douta_array; - output [8:0]doutb_array; - input clka; - input clkb; - input [12:0]addra; - input [12:0]addrb; - - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [8:0]douta_array; - wire [8:0]doutb_array; - - COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized2 \prim_init.ram - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .douta_array(douta_array), - .doutb_array(doutb_array)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) -module COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init - (douta_array, - doutb_array, - clka, - clkb, - ena_array, - enb_array, - addra, - addrb); - output [8:0]douta_array; - output [8:0]doutb_array; - input clka; - input clkb; - input [0:0]ena_array; - input [0:0]enb_array; - input [11:0]addra; - input [11:0]addrb; - - wire [11:0]addra; - wire [11:0]addrb; - wire clka; - wire clkb; - wire [8:0]douta_array; - wire [8:0]doutb_array; - wire [0:0]ena_array; - wire [0:0]enb_array; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; - wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; - wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; - wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; - wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; - wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; - - (* box_type = "PRIMITIVE" *) - RAMB36E1 #( - .DOA_REG(1), - .DOB_REG(1), - .EN_ECC_READ("FALSE"), - .EN_ECC_WRITE("FALSE"), - .INITP_00(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INITP_01(256'hFFFFFFFFFFFFE0000000000000000000000000000000003FFFFFFFFFFFFFFFFF), - .INITP_02(256'h0000000003FFFFFFFFFFFFFFFFFFE0000000000000000000001FFFFFFFFFFFFF), - .INITP_03(256'h00000000000FFFFFFFFFFFFFF800000000000000FFFFFFFFFFFFFFFF80000000), - .INITP_04(256'h0003FFFFFFFFFF800000000003FFFFFFFFFFF0000000000007FFFFFFFFFFFE00), - .INITP_05(256'h8000000007FFFFFFFF8000000001FFFFFFFFF8000000000FFFFFFFFFF8000000), - .INITP_06(256'h0000000FFFFFFFE00000001FFFFFFFE00000001FFFFFFFF800000001FFFFFFFF), - .INITP_07(256'hFFFFFFC0000007FFFFFF0000000FFFFFFF80000007FFFFFFC0000000FFFFFFFC), - .INITP_08(256'h0FFFFFF000000FFFFFF0000007FFFFFC000001FFFFFF8000001FFFFFF8000001), - .INITP_09(256'hFFC00001FFFFF800000FFFFFC00000FFFFFE000003FFFFF800000FFFFFF00000), - .INITP_0A(256'hFFFF800007FFFF800007FFFF800003FFFFE00001FFFFF000007FFFFE00000FFF), - .INITP_0B(256'hF80000FFFFC00007FFFE00003FFFF80000FFFFE00001FFFFC00007FFFF800007), - .INITP_0C(256'hFFF80003FFFE00007FFFC0000FFFF80001FFFF80001FFFF00001FFFF80001FFF), - .INITP_0D(256'hE0000FFFF0000FFFF00007FFF80007FFFC0001FFFE0000FFFF80003FFFE0000F), - .INITP_0E(256'hFFC0007FFF0001FFFE0003FFFC0007FFF8000FFFF0000FFFF0000FFFE0001FFF), - .INITP_0F(256'h0003FFF0001FFF8000FFFE0007FFF0001FFFC000FFFE0003FFF8000FFFE0003F), - .INIT_00(256'hFDFDFDFDFDFDFDFEFEFEFEFEFEFEFEFEFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_01(256'hF5F6F6F6F7F7F7F7F8F8F8F8F9F9F9F9FAFAFAFAFBFBFBFBFBFCFCFCFCFCFCFD), - .INIT_02(256'hE9EAEAEBEBEBECECEDEDEEEEEEEFEFF0F0F0F1F1F1F2F2F3F3F3F4F4F4F5F5F5), - .INIT_03(256'hD8D9D9DADBDBDCDCDDDDDEDFDFE0E0E1E1E2E2E3E3E4E4E5E5E6E6E7E7E8E8E9), - .INIT_04(256'hC2C3C4C4C5C6C7C7C8C9C9CACBCCCCCDCECECFD0D0D1D2D2D3D4D4D5D6D6D7D8), - .INIT_05(256'hA7A8A9AAABACADADAEAFB0B1B2B3B3B4B5B6B7B8B9B9BABBBCBDBDBEBFC0C1C1), - .INIT_06(256'h8788898A8B8C8E8F909192939495969798999A9B9C9D9E9FA0A1A1A2A3A4A5A6), - .INIT_07(256'h6264656667686A6B6C6D6E7071727374757778797A7B7C7D7E80818283848586), - .INIT_08(256'h393A3B3D3E3F414243454647494A4B4D4E4F515253555657585A5B5C5D5F6061), - .INIT_09(256'h0A0B0D0E101113141617191A1C1D1F202223252628292A2C2D2F303233343637), - .INIT_0A(256'hD6D8DADBDDDFE0E2E4E5E7E8EAECEDEFF1F2F4F5F7F9FAFCFDFF010204050708), - .INIT_0B(256'h9E9FA1A3A5A7A9AAACAEB0B2B3B5B7B9BBBCBEC0C2C3C5C7C9CACCCECFD1D3D4), - .INIT_0C(256'h60626466686A6C6E70727476787A7C7E7F81838587898B8D8F91929496989A9C), - .INIT_0D(256'h1E20222426282B2D2F31333537393B3D40424446484A4C4E50525456585A5C5E), - .INIT_0E(256'hD6D9DBDDE0E2E4E6E9EBEDEFF2F4F6F8FBFDFF010406080A0C0F11131517191C), - .INIT_0F(256'h8A8D8F929496999B9EA0A3A5A7AAACAFB1B3B6B8BABDBFC1C4C6C8CBCDCFD2D4), - .INIT_10(256'h393C3E414346494B4E505355585B5D606265676A6C6F717476797B7E80838588), - .INIT_11(256'hE3E6E8EBEEF1F3F6F9FCFE010407090C0F111417191C1F212427292C2F313436), - .INIT_12(256'h888B8E919497999C9FA2A5A8ABAEB0B3B6B9BCBFC1C4C7CACDCFD2D5D8DBDDE0), - .INIT_13(256'h282B2E3134373A3E4144474A4D505356595C5F6265686B6E707376797C7F8285), - .INIT_14(256'hC3C7CACDD0D3D7DADDE0E3E7EAEDF0F3F6F9FD000306090C0F1216191C1F2225), - .INIT_15(256'h5A5D6064676B6E7175787B7F8285898C8F9296999CA0A3A6A9ADB0B3B6BABDC0), - .INIT_16(256'hEBEFF2F6F9FD0004070B0E1215191C2023262A2D3134383B3F4245494C505356), - .INIT_17(256'h787B7F83868A8E9195999CA0A4A7ABAEB2B6B9BDC0C4C8CBCFD2D6D9DDE1E4E8), - .INIT_18(256'hFF03070B0F12161A1E2225292D3135383C4044474B4F53565A5E6265696D7074), - .INIT_19(256'h82868A8E92969A9EA2A6AAAEB2B6BABDC1C5C9CDD1D5D9DDE1E4E8ECF0F4F8FC), - .INIT_1A(256'h0004080C1115191D2125292D31363A3E42464A4E52565A5E62666A6E72767A7E), - .INIT_1B(256'h797D82868A8F93979BA0A4A8ACB1B5B9BDC1C6CACED2D6DBDFE3E7EBEFF4F8FC), - .INIT_1C(256'hEDF2F6FBFF04080C11151A1E22272B2F34383D41454A4E52575B5F64686C7175), - .INIT_1D(256'h5D61666A6F74787D81868A8F93989DA1A6AAAFB3B8BCC1C5CACED3D7DCE0E4E9), - .INIT_1E(256'hC7CCD1D5DADFE4E8EDF2F6FB0004090E13171C21252A2E33383C41464A4F5358), - .INIT_1F(256'h2D32373B40454A4F54595E62676C71767B7F84898E93979CA1A6ABAFB4B9BEC2), - .INIT_20(256'h8E93989DA2A7ACB1B6BBC0C5CACFD4D9DEE3E8EDF2F7FC01050A0F14191E2328), - .INIT_21(256'hEAEFF4F9FE03090E13181D22282D32373C41464C51565B60656A6F74797E8389), - .INIT_22(256'h41464B51565B61666B71767B81868B90969BA0A6ABB0B5BBC0C5CACFD5DADFE4), - .INIT_23(256'h93989EA3A9AEB4B9BFC4CACFD5DAE0E5EAF0F5FB00060B10161B20262B31363B), - .INIT_24(256'hE0E6ECF1F7FD02080E13191E242A2F353A40454B51565C61676C72777D82888D), - .INIT_25(256'h292F353B40464C52575D63696E747A80858B91979CA2A8ADB3B9BEC4CACFD5DB), - .INIT_26(256'h6D73797F858B91979DA2A8AEB4BAC0C6CCD2D7DDE3E9EFF5FB00060C12181E23), - .INIT_27(256'hACB2B8BEC4CBD1D7DDE3E9EFF5FB01070D13191F252B31373D43494F555B6167), - .INIT_28(256'hE6EDF3F9FF060C12181F252B31373D444A50565C63696F757B81878E949AA0A6), - .INIT_29(256'h1C22292F353C42494F555C62686F757B82888E959BA1A8AEB4BBC1C7CDD4DAE0), - .INIT_2A(256'h4D535A60676D747A81878E949BA1A8AEB5BBC2C8CFD5DCE2E9EFF5FC02090F16), - .INIT_2B(256'h797F868D939AA1A7AEB5BBC2C9CFD6DDE3EAF0F7FE040B12181F252C32394046), - .INIT_2C(256'hA0A7AEB4BBC2C9D0D7DDE4EBF2F9FF060D141A21282F353C434A50575E656B72), - .INIT_2D(256'hC2C9D0D7DEE5ECF3FA01080F161D242B323940464D545B626970777E848B9299), - .INIT_2E(256'hE0E7EEF5FD040B121920272E353D444B525960676E757C838A91989FA6ADB4BB), - .INIT_2F(256'hF900080F161D252C333B424950575F666D747C838A9198A0A7AEB5BCC3CBD2D9), - .INIT_30(256'h0D151C242B323A414950575F666E757C848B939AA1A9B0B7BFC6CDD5DCE3EAF2), - .INIT_31(256'h1D242C343B434A5259616970787F878E969DA5ACB4BBC3CAD2D9E1E8F0F7FE06), - .INIT_32(256'h282F373F474E565E656D757D848C949BA3ABB2BAC2C9D1D8E0E8EFF7FE060E15), - .INIT_33(256'h2E363E464D555D656D757C848C949CA4ABB3BBC3CBD2DAE2EAF1F90109111820), - .INIT_34(256'h2F373F474F575F676F777F878F979FA7AFB7BFC7CFD7DFE7EFF7FF060E161E26), - .INIT_35(256'h2C343C454D555D656D767E868E969EA6AEB6BFC7CFD7DFE7EFF7FF070F171F27), - .INIT_36(256'h242D353D464E565E676F7780889098A1A9B1B9C2CAD2DAE2EBF3FB030B141C24), - .INIT_37(256'h182029313A424A535B646C757D858E969FA7AFB8C0C8D1D9E2EAF2FB030B141C), - .INIT_38(256'h070F182029323A434B545C656E767F879098A1A9B2BAC3CBD4DCE5EDF6FE070F), - .INIT_39(256'hF1F9020B141C252E373F485159626B747C858E969FA8B0B9C2CAD3DBE4EDF5FE), - .INIT_3A(256'hD6DFE8F1FA030C141D262F38414A525B646D767F879099A2ABB3BCC5CED6DFE8), - .INIT_3B(256'hB7C0C9D2DBE4EDF6FF08111A232C353E475059626B747D868F98A1AAB3BCC4CD), - .INIT_3C(256'h949DA6AFB8C1CBD4DDE6EFF8010B141D262F38414A535D666F78818A939CA5AE), - .INIT_3D(256'h6B757E87919AA3ACB6BFC8D2DBE4EDF70009131C252E37414A535C666F78818A), - .INIT_3E(256'h3E48515B646E77818A949DA6B0B9C3CCD5DFE8F2FB040E17212A333D464F5962), - .INIT_3F(256'h0D17202A333D47505A636D77808A939DA6B0B9C3CCD6DFE9F3FC060F19222B35), - .INIT_40(256'hD7E1EBF4FE08121B252F38424C565F69737C869099A3ADB6C0CAD3DDE7F0FA03), - .INIT_41(256'h9DA6B0BAC4CED8E2ECF5FF09131D27313A444E58626B757F89939CA6B0BAC4CD), - .INIT_42(256'h5D67727C86909AA4AEB8C2CCD6E0EAF4FE08111B252F39434D57616B757F8993), - .INIT_43(256'h1A242E38434D57616B757F8A949EA8B2BCC6D0DBE5EFF9030D17212B353F4953), - .INIT_44(256'hD2DCE6F1FB05101A242E39434D58626C76818B959FAAB4BEC8D2DDE7F1FB0510), - .INIT_45(256'h85909AA5AFB9C4CED9E3EEF8020D17222C36414B56606A757F89949EA8B3BDC7), - .INIT_46(256'h343F49545E69747E89939EA8B3BEC8D3DDE8F2FD07121C27313C46515B66707B), - .INIT_47(256'hDFE9F4FF09141F2A343F4A545F6A747F8A959FAAB5BFCAD4DFEAF4FF0A141F29), - .INIT_48(256'h848F9AA5B0BBC6D1DBE6F1FC07121C27323D48525D68737E88939EA9B3BEC9D4), - .INIT_49(256'h26313C47525D68737E89949FAAB5C0CBD6E1ECF7020C17222D38434E59646F7A), - .INIT_4A(256'hC3CED9E5F0FB06111C27323E49545F6A75808B96A1ACB8C3CED9E4EFFA05101B), - .INIT_4B(256'h5C67727E89949FABB6C1CDD8E3EEFA05101B26323D48535E6A75808B96A2ADB8), - .INIT_4C(256'hF0FB07121E2935404B57626E7984909BA6B2BDC9D4DFEBF6010D18232F3A4550), - .INIT_4D(256'h808B97A3AEBAC5D1DCE8F3FF0A16212D38444F5B66727D8994A0ABB7C2CED9E5), - .INIT_4E(256'h0B17232E3A46525D6975808C98A3AFBBC6D2DDE9F5000C18232F3A46525D6974), - .INIT_4F(256'h929EAAB6C2CED9E5F1FD0914202C38444F5B67737F8A96A2AEB9C5D1DCE8F400), - .INIT_50(256'h15212D3945515D6975818D99A5B1BDC8D4E0ECF804101C28343F4B57636F7B87), - .INIT_51(256'h94A0ACB8C4D0DCE8F4010D1925313D4955616D7985919DA9B5C1CDD9E5F1FD09), - .INIT_52(256'h0E1A26323F4B5763707C8894A0ADB9C5D1DDEAF6020E1A26333F4B57636F7B88), - .INIT_53(256'h83909CA9B5C1CEDAE6F3FF0B1824303D4955626E7A87939FACB8C4D0DDE9F501), - .INIT_54(256'hF5020E1B2734404D5965727E8B97A4B0BDC9D6E2EFFB0714202D3946525E6B77), - .INIT_55(256'h626F7B8895A1AEBBC7D4E1EDFA0613202C3945525E6B7884919DAAB6C3CFDCE8), - .INIT_56(256'hCBD8E5F1FE0B1825313E4B5864717E8A97A4B1BDCAD7E3F0FD0A1623303C4956), - .INIT_57(256'h303D4A5763707D8A97A4B1BECBD7E4F1FE0B1825313E4B5865727E8B98A5B2BE), - .INIT_58(256'h909DAAB7C4D1DFECF90613202D3A4754616E7B8894A1AEBBC8D5E2EFFC091623), - .INIT_59(256'hEDFA0714212E3C495663707D8A98A5B2BFCCD9E6F3000E1B2835424F5C697683), - .INIT_5A(256'h45525F6C7A8794A2AFBCCAD7E4F1FF0C192634414E5B687683909DABB8C5D2DF), - .INIT_5B(256'h98A6B3C1CEDCE9F604111F2C394754626F7C8A97A4B2BFCDDAE7F5020F1D2A37), - .INIT_5C(256'hE8F603111E2C39475562707D8B98A6B3C1CEDCE9F704121F2D3A485563707E8B), - .INIT_5D(256'h34414F5D6A788693A1AFBCCAD8E5F3010E1C2A374553606E7B8997A4B2BFCDDB), - .INIT_5E(256'h7B8997A4B2C0CEDCEAF70513212F3C4A586673818F9DAAB8C6D4E1EFFD0A1826), - .INIT_5F(256'hBECCDAE8F60412202E3C4A586673818F9DABB9C7D5E3F0FE0C1A283644515F6D), - .INIT_60(256'hFD0C1A28364452606E7C8A98A6B4C2D0DEECFA08162432404E5C6A788694A2B0), - .INIT_61(256'h3947556371808E9CAAB8C6D5E3F1FF0D1B2A38465462707E8D9BA9B7C5D3E1EF), - .INIT_62(256'h707E8C9BA9B7C6D4E2F0FF0D1B2A38465563717F8E9CAAB8C7D5E3F1000E1C2A), - .INIT_63(256'hA2B1BFCEDCEBF90816253341505E6D7B8A98A6B5C3D1E0EEFD0B192836445361), - .INIT_64(256'hD1E0EFFD0C1A293746556372808F9DACBAC9D7E6F50312202F3D4C5A69778694), - .INIT_65(256'hFC0B1A283746556372818F9EADBBCAD9E7F6051322313F4E5C6B7A8897A6B4C3), - .INIT_66(256'h233241505F6D7C8B9AA9B7C6D5E4F301101F2E3D4B5A69788695A4B3C1D0DFEE), - .INIT_67(256'h465564738291A0AFBECDDCEBF90817263544536271808F9DACBBCAD9E8F70514), - .INIT_68(256'h65748392A1B0C0CFDEEDFC0B1A2938475665748392A1B0BFCEDDECFB0A192837), - .INIT_69(256'h808F9EAEBDCCDBEAFA09182736465564738291A0B0BFCEDDECFB0A1A29384756), - .INIT_6A(256'h97A6B6C5D4E4F302122130404F5E6E7D8C9BABBAC9D8E8F70615253443526271), - .INIT_6B(256'hAABAC9D9E8F807162635455464738292A1B1C0CFDFEEFE0D1C2C3B4A5A697888), - .INIT_6C(256'hBAC9D9E8F807172736465565748493A3B2C2D1E1F0000F1F2E3E4D5D6C7C8B9B), - .INIT_6D(256'hC5D5E4F404132333425262718191A0B0C0CFDFEFFE0E1E2D3D4C5C6C7B8B9AAA), - .INIT_6E(256'hCDDCECFC0C1C2B3B4B5B6B7A8A9AAAB9C9D9E9F808182837475767768696A6B5), - .INIT_6F(256'hD0E0F0001020304050606F7F8F9FAFBFCFDFEFFE0E1E2E3E4E5E6D7D8D9DADBD), - .INIT_70(256'hD0E0F000102030405061718191A1B1C1D1E1F101112131415161708090A0B0C0), - .INIT_71(256'hCCDCEDFD0D1D2D3D4E5E6E7E8E9EAEBFCFDFEFFF0F1F2F3F4F60708090A0B0C0), - .INIT_72(256'hC5D5E5F506162637475767788898A8B9C9D9E9FA0A1A2A3A4B5B6B7B8B9CACBC), - .INIT_73(256'hB9CADAEAFB0B1C2C3C4D5D6D7E8E9FAFBFD0E0F001112132425263738394A4B4), - .INIT_74(256'hAABACBDCECFD0D1E2E3F4F60708191A2B2C2D3E3F404152536465767778898A9), - .INIT_75(256'h97A8B8C9DAEAFB0B1C2D3D4E5F6F8090A1B2C2D3E3F404152636475768788999), - .INIT_76(256'h8091A2B3C3D4E5F606172839495A6B7B8C9DAEBECFE0F0011222334454657686), - .INIT_77(256'h66778899AABBCBDCEDFE0F2030415263748595A6B7C8D9E9FA0B1C2D3D4E5F70), - .INIT_78(256'h48596A7B8C9DAEBFD0E1F2031425364758697A8A9BACBDCEDFF0011223344455), - .INIT_79(256'h2738495A6B7C8D9EAFC0D2E3F405162738495A6B7C8D9EAFC0D1E2F304152637), - .INIT_7A(256'h021324354658697A8B9CAEBFD0E1F20315263748596A7B8D9EAFC0D1E2F30416), - .INIT_7B(256'hD9EAFB0D1E2F415263758697A8BACBDCEEFF10213344556678899AABBDCEDFF0), - .INIT_7C(256'hACBECFE1F204152638495B6C7D8FA0B2C3D4E6F7091A2B3D4E5F718293A5B6C7), - .INIT_7D(256'h7C8EA0B1C3D4E6F7091A2C3D4F60728395A6B8C9DBECFE0F213244556778899B), - .INIT_7E(256'h495B6C7E90A1B3C5D6E8F90B1D2E405263758698AABBCDDEF00213253648596B), - .INIT_7F(256'h12243647596B7D8EA0B2C4D5E7F90B1C2E405163758798AABCCDDFF102142637), - .INIT_A(36'h000000000), - .INIT_B(36'h000000000), - .INIT_FILE("NONE"), - .IS_CLKARDCLK_INVERTED(1'b0), - .IS_CLKBWRCLK_INVERTED(1'b0), - .IS_ENARDEN_INVERTED(1'b0), - .IS_ENBWREN_INVERTED(1'b0), - .IS_RSTRAMARSTRAM_INVERTED(1'b0), - .IS_RSTRAMB_INVERTED(1'b0), - .IS_RSTREGARSTREG_INVERTED(1'b0), - .IS_RSTREGB_INVERTED(1'b0), - .RAM_EXTENSION_A("NONE"), - .RAM_EXTENSION_B("NONE"), - .RAM_MODE("TDP"), - .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), - .READ_WIDTH_A(9), - .READ_WIDTH_B(9), - .RSTREG_PRIORITY_A("REGCE"), - .RSTREG_PRIORITY_B("REGCE"), - .SIM_COLLISION_CHECK("ALL"), - .SIM_DEVICE("7SERIES"), - .SRVAL_A(36'h000000000), - .SRVAL_B(36'h000000000), - .WRITE_MODE_A("WRITE_FIRST"), - .WRITE_MODE_B("WRITE_FIRST"), - .WRITE_WIDTH_A(9), - .WRITE_WIDTH_B(9)) - \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram - (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}), - .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}), - .CASCADEINA(1'b0), - .CASCADEINB(1'b0), - .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), - .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), - .CLKARDCLK(clka), - .CLKBWRCLK(clkb), - .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), - .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIPADIP({1'b0,1'b0,1'b0,1'b0}), - .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), - .DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],douta_array[7:0]}), - .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}), - .DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],douta_array[8]}), - .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}), - .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), - .ENARDEN(ena_array), - .ENBWREN(enb_array), - .INJECTDBITERR(1'b0), - .INJECTSBITERR(1'b0), - .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), - .REGCEAREGCE(1'b1), - .REGCEB(1'b1), - .RSTRAMARSTRAM(1'b0), - .RSTRAMB(1'b0), - .RSTREGARSTREG(1'b0), - .RSTREGB(1'b0), - .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), - .WEA({1'b0,1'b0,1'b0,1'b0}), - .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) -module COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized0 - (douta_array, - doutb_array, - clka, - clkb, - addra, - addrb); - output [8:0]douta_array; - output [8:0]doutb_array; - input clka; - input clkb; - input [12:0]addra; - input [12:0]addrb; - - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [8:0]douta_array; - wire [8:0]doutb_array; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; - wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; - wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; - wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; - wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; - wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; - - (* box_type = "PRIMITIVE" *) - RAMB36E1 #( - .DOA_REG(1), - .DOB_REG(1), - .EN_ECC_READ("FALSE"), - .EN_ECC_WRITE("FALSE"), - .INITP_00(256'hC000FFFC000FFFC001FFF8001FFF8001FFF8000FFFC000FFFC000FFFE0007FFE), - .INITP_01(256'h1FFF0007FFC000FFF8003FFF0007FFC000FFF8001FFF0003FFF0007FFE0007FF), - .INITP_02(256'hFFF8003FFC001FFF0007FF8003FFE000FFF8003FFE000FFF8003FFE000FFF800), - .INITP_03(256'h01FFE001FFF000FFF0007FF8003FFC003FFE001FFF000FFF8003FFC001FFE000), - .INITP_04(256'hFF8007FF8007FF8007FF8007FF8007FF8007FF8007FF8003FFC003FFC003FFE0), - .INITP_05(256'hFF001FFE003FFC003FF8007FF800FFF000FFE001FFE001FFC003FFC003FFC003), - .INITP_06(256'h7FF800FFE003FFC007FF000FFE001FFC007FF800FFF001FFE003FFC007FF800F), - .INITP_07(256'h800FFE003FF800FFE003FF8007FF001FFC007FF001FFE003FF800FFE001FFC00), - .INITP_08(256'h03FF801FFC007FF001FFC007FF003FF800FFE003FF800FFE003FF800FFE003FF), - .INITP_09(256'h0FFE003FF001FFC00FFE003FF001FFC007FE003FF800FFC007FF001FF800FFE0), - .INITP_0A(256'h01FF800FFC007FE003FF001FF800FFC007FF003FF801FFC007FE003FF001FFC0), - .INITP_0B(256'hC00FFC007FE003FF003FF801FFC00FFC007FE003FF001FF800FFC007FE003FF0), - .INITP_0C(256'hFF800FFC00FFE007FE003FF003FF801FF800FFC00FFE007FE003FF003FF801FF), - .INITP_0D(256'h007FE007FE003FF003FF001FF801FF800FFC00FFE007FE007FF003FF001FF801), - .INITP_0E(256'hFF800FFC00FFC00FFE007FE007FE003FF003FF001FF801FF801FFC00FFC00FFE), - .INITP_0F(256'h001FF801FF801FFC00FFC00FFC007FE007FE007FE003FF003FF003FF801FF801), - .INIT_00(256'hD8EAFB0D1F31435567788A9CAEC0D2E3F507192B3D4E60728496A7B9CBDDEF00), - .INIT_01(256'h9AACBED0E2F406182A3B4D5F718395A7B9CBDDEF01132537485A6C7E90A2B4C6), - .INIT_02(256'h586A7D8FA1B3C5D7E9FB0D1F31435567798C9EB0C2D4E6F80A1C2E4052647688), - .INIT_03(256'h1426384A5C6F8193A5B7C9DCEE00122436495B6D7F91A3B5C7DAECFE10223446), - .INIT_04(256'hCBDEF0021527394B5E708295A7B9CBDEF0021427394B5D708294A6B9CBDDEF01), - .INIT_05(256'h8092A5B7C9DCEE011325384A5D6F8194A6B8CBDDEF021426394B5D708294A7B9), - .INIT_06(256'h314356687B8DA0B2C5D7EAFC0F213446596B7E90A3B5C8DAECFF112436495B6D), - .INIT_07(256'hDFF10416293C4E61748699ABBED0E3F6081B2D405265788A9DAFC2D4E7F90C1E), - .INIT_08(256'h899CAEC1D4E7F90C1F3144576A7C8FA2B4C7DAECFF1224374A5C6F8194A7B9CC), - .INIT_09(256'h304356697B8EA1B4C7DAECFF1225374A5D708395A8BBCEE0F306192B3E516476), - .INIT_0A(256'hD4E7FA0D203346586B7E91A4B7CADDF00315283B4E61748799ACBFD2E5F80B1D), - .INIT_0B(256'h75889BAEC1D4E7FA0D203346596C7F92A5B8CBDEF104172A3C4F6275889BAEC1), - .INIT_0C(256'h1225384B5F728598ABBED1E4F70A1E3144576A7D90A3B6C9DCEF0215283C4F62), - .INIT_0D(256'hACBFD3E6F90C203346596C8093A6B9CCE0F306192C3F5366798C9FB2C5D9ECFF), - .INIT_0E(256'h43576A7D91A4B7CADEF104182B3E5265788B9FB2C5D8ECFF1226394C5F728699), - .INIT_0F(256'hD7EAFE1125384C5F728699ADC0D3E7FA0E2134485B6E8295A8BCCFE3F6091D30), - .INIT_10(256'h687B8FA2B6C9DDF004172B3E5265798CA0B3C7DAEE0115283C4F6276899DB0C4), - .INIT_11(256'hF5091D3044576B7F92A6B9CDE1F4081B2F43566A7D91A4B8CBDFF3061A2D4154), - .INIT_12(256'h8094A7BBCFE2F60A1E3145596C8094A7BBCFE2F60A1D3145586C8093A7BBCEE2), - .INIT_13(256'h071B2F43576A7E92A6BACDE1F5091C3044586C7F93A7BBCEE2F60A1D3145586C), - .INIT_14(256'h8CA0B4C8DBEF03172B3F53677B8EA2B6CADEF206192D4155697D90A4B8CCE0F4), - .INIT_15(256'h0D2135495D718599ADC1D5E9FD1125394D6175899DB1C5D9EC0014283C506478), - .INIT_16(256'h8CA0B4C8DCF004182C4054697D91A5B9CDE1F5091D3145596D8195A9BDD1E5F9), - .INIT_17(256'h071B2F44586C8094A9BDD1E5F90D21364A5E72869AAEC3D7EBFF13273B4F6378), - .INIT_18(256'h8094A8BCD1E5F90E22364A5F73879BAFC4D8EC0015293D51667A8EA2B6CBDFF3), - .INIT_19(256'hF50A1E32475B6F8498ACC1D5E9FE12263B4F63788CA0B5C9DDF2061A2E43576B), - .INIT_1A(256'h687C91A5BACEE3F70C2034495D72869BAFC3D8EC0115293E52677B8FA4B8CCE1), - .INIT_1B(256'hD8EC01152A3E53687C91A5BACEE3F70C2035495E72879BB0C4D9ED02162B3F53), - .INIT_1C(256'h45596E8397ACC1D5EAFE13283C51657A8FA3B8CCE1F60A1F33485C71869AAFC3), - .INIT_1D(256'hAFC4D8ED02172B4055697E93A7BCD1E6FA0F24384D62768BA0B4C9DEF2071C30), - .INIT_1E(256'h162B40556A7E93A8BDD2E6FB1025394E63788DA1B6CBE0F4091E33475C71869A), - .INIT_1F(256'h7B90A5BACFE3F80D22374C61768A9FB4C9DEF3081C31465B708599AEC3D8ED02), - .INIT_20(256'hDDF2071C31465B70859AAFC4D8ED02172C41566B8095AABFD4E9FE12273C5166), - .INIT_21(256'h3C51667B90A5BACFE4FA0F24394E63788DA2B7CCE1F60B20354A5F74899EB3C8), - .INIT_22(256'h98AEC3D8ED02172C42576C8196ABC0D5EB00152A3F54697E93A8BED3E8FD1227), - .INIT_23(256'hF2081D32475C72879CB1C7DCF1061B31465B70859AB0C5DAEF041A2F44596E83), - .INIT_24(256'h495F74899FB4C9DFF4091F34495E74899EB3C9DEF3091E33485E73889DB3C8DD), - .INIT_25(256'h9EB3C9DEF4091E34495F74899FB4C9DFF4091F34495F748A9FB4CADFF40A1F34), - .INIT_26(256'hF0051B30465B71869CB1C7DCF2071C32475D72889DB2C8DDF3081E33485E7389), - .INIT_27(256'h3F556A8096ABC1D6EC01172C42576D8298AEC3D9EE04192F445A6F859AB0C5DA), - .INIT_28(256'h8CA2B7CDE3F80E24394F647A90A5BBD1E6FC11273C52687D93A8BED4E9FF142A), - .INIT_29(256'hD7EC02182D43596F849AB0C5DBF1061C32475D73889EB4C9DFF50A20364B6177), - .INIT_2A(256'h1E344A60768BA1B7CDE2F80E243A4F657B91A6BCD2E8FD13293F546A8095ABC1), - .INIT_2B(256'h647A90A5BBD1E7FD13293E546A8096ACC1D7ED03192F445A70869CB1C7DDF309), - .INIT_2C(256'hA7BDD3E9FF142A40566C8298AEC4DAF0061C31475D73899FB5CBE1F60C22384E), - .INIT_2D(256'hE7FD13293F556B8197ADC3D9EF051B31475D73899FB5CBE1F70D23394F657B91), - .INIT_2E(256'h263C52687E94AAC0D6EC02182F455B71879DB3C9DFF50B21374D63798FA5BBD1), - .INIT_2F(256'h61788EA4BAD0E6FC13293F556B8197AEC4DAF0061C32485F758BA1B7CDE3F90F), - .INIT_30(256'h9BB1C7DEF40A20364D63798FA6BCD2E8FE152B41576D849AB0C6DCF3091F354B), - .INIT_31(256'hD2E8FF152B42586E849BB1C7DEF40A20374D637A90A6BCD3E9FF152C42586E85), - .INIT_32(256'h071D344A61778DA4BAD0E7FD132A40566D839AB0C6DDF30920364C62798FA5BC), - .INIT_33(256'h3A50677D93AAC0D7ED041A31475D748AA1B7CDE4FA11273D546A8197ADC4DAF1), - .INIT_34(256'h6A8197AEC4DBF1081E354B62788FA5BCD2E9FF162C435970869CB3C9E0F60D23), - .INIT_35(256'h98AFC6DCF30920364D647A91A7BED4EB02182F455C72899FB6CCE3FA10273D54), - .INIT_36(256'hC5DBF2081F364C637A90A7BED4EB01182F455C7389A0B6CDE4FA11273E556B82), - .INIT_37(256'hEE051C334960778DA4BBD2E8FF162C435A70879EB4CBE2F90F263D536A8197AE), - .INIT_38(256'h162D445B71889FB6CDE3FA11283E556C8399B0C7DEF40B22394F667D94AAC1D8), - .INIT_39(256'h3C536A8197AEC5DCF30A21374E657C93A9C0D7EE051C324960778EA4BBD2E900), - .INIT_3A(256'h60778EA5BBD2E900172E455C738AA0B7CEE5FC132A41576E859CB3CAE1F80E25), - .INIT_3B(256'h8198AFC6DDF40B223950677E95ACC3DAF1081F364D647B91A8BFD6ED041B3249), - .INIT_3C(256'hA1B8CFE6FD142B425970879FB6CDE4FB122940576E859CB3CAE1F80F263D546B), - .INIT_3D(256'hBFD6ED041B324961788FA6BDD4EB021930475E758DA4BBD2E900172E455C738A), - .INIT_3E(256'hDBF20920374E667D94ABC2D9F0081F364D647B92AAC1D8EF061D344B627A91A8), - .INIT_3F(256'hF50C233A51698097AEC5DDF40B223951687F96ADC5DCF30A213850677E95ACC3), - .INIT_40(256'h0C243B526A8198AFC7DEF50C243B52698198AFC6DEF50C233B52698098AFC6DD), - .INIT_41(256'h233A51698097AFC6DDF50C233A52698098AFC6DEF50C243B52698198AFC7DEF5), - .INIT_42(256'h374E667D94ACC3DBF20921384F677E96ADC4DCF30A223950687F97AEC5DDF40B), - .INIT_43(256'h49617890A7BFD6ED051C344B637A91A9C0D8EF071E354D647C93AAC2D9F1081F), - .INIT_44(256'h5A7189A0B8CFE7FE162D455C748BA3BAD2E9011830475F768EA5BDD4EB031A32), - .INIT_45(256'h698098B0C7DFF60E253D546C849BB3CAE2F9112840576F869EB5CDE4FC132B42), - .INIT_46(256'h768EA5BDD5EC041B334B627A91A9C1D8F0071F364E667D95ACC4DCF30B223A51), - .INIT_47(256'h8299B1C9E0F810273F576E869EB5CDE4FC142B435B728AA2B9D1E800182F475F), - .INIT_48(256'h8CA3BBD3EA021A3249617990A8C0D7EF071E364E667D95ADC4DCF40B233B526A), - .INIT_49(256'h94ACC3DBF30B223A526A8199B1C9E0F810283F576F879EB6CEE5FD152D445C74), - .INIT_4A(256'h9AB2CAE2FA112941597188A0B8D0E8FF172F475F768EA6BED6ED051D354C647C), - .INIT_4B(256'h9FB7CFE7FF172F465E768EA6BED6ED051D354D657C94ACC4DCF40B233B536B83), - .INIT_4C(256'hA3BBD3EB031A324A627A92AAC2DAF209213951698199B1C9E0F8102840587088), - .INIT_4D(256'hA5BDD5ED051D354D657C94ACC4DCF40C243C546C849CB4CCE4FB132B435B738B), - .INIT_4E(256'hA5BDD5ED051D354D657D95ADC5DDF50D253D556D859DB5CDE5FD152D455D758D), - .INIT_4F(256'hA4BCD5ED051D354D657D95ADC5DDF50D253D556D859DB5CDE5FD152D455D758D), - .INIT_50(256'hA2BAD2EA021A334B637B93ABC3DBF30B233B546C849CB4CCE4FC142C445C748C), - .INIT_51(256'h9EB6CEE7FF172F475F7790A8C0D8F008203851698199B1C9E1F9112A425A728A), - .INIT_52(256'h99B1C9E2FA122A425A738BA3BBD3EB041C344C647C95ADC5DDF50D253E566E86), - .INIT_53(256'h92ABC3DBF30C243C546C859DB5CDE5FE162E465F778FA7BFD7F0082038506981), - .INIT_54(256'h8BA3BBD3EC041C344D657D95AEC6DEF60F273F577088A0B8D1E90119324A627A), - .INIT_55(256'h819AB2CAE3FB132C445C748DA5BDD6EE061E374F678098B0C8E1F9112A425A72), - .INIT_56(256'h778FA8C0D8F109213A526A839BB3CCE4FC152D455E768EA7BFD7F00820395169), - .INIT_57(256'h6B849CB5CDE5FE162E475F7890A8C1D9F10A223B536B849CB4CDE5FD162E465F), - .INIT_58(256'h5F778FA8C0D9F10A223A536B849CB4CDE5FE162E475F7890A8C1D9F20A223B53), - .INIT_59(256'h5169829AB2CBE3FC142D455E768EA7BFD8F009213A526A839BB4CCE5FD152E46), - .INIT_5A(256'h425A728BA3BCD4ED051E364F678098B1C9E2FA132B445C758DA5BED6EF072038), - .INIT_5B(256'h314A627B93ACC4DDF50E263F577089A1BAD2EB031C344D657E96AFC7E0F81129), - .INIT_5C(256'h2038516A829BB3CCE4FD152E475F7890A9C1DAF20B233C556D869EB7CFE80019), - .INIT_5D(256'h0E263F577089A1BAD2EB031C354D667E97AFC8E1F9122A435B748DA5BED6EF07), - .INIT_5E(256'hFA132B445D758EA6BFD8F009223A536B849DB5CEE6FF183049617A93ABC4DCF5), - .INIT_5F(256'hE6FE173048617A92ABC4DCF50E263F577089A1BAD3EB041D354E667F98B0C9E2), - .INIT_60(256'hD0E9021A334C647D96AFC7E0F9112A435B748DA5BED7EF082139526A839CB4CD), - .INIT_61(256'hBAD3EC041D364E678098B1CAE3FB142D455E778FA8C1DAF20B243C556E869FB8), - .INIT_62(256'hA3BCD4ED061F375069829AB3CCE4FD162F47607992AAC3DCF40D263F577089A1), - .INIT_63(256'h8BA4BCD5EE071F38516A829BB4CDE5FE173048617A93ABC4DDF60E274059718A), - .INIT_64(256'h728BA4BCD5EE071F38516A839BB4CDE6FF173049627A93ACC5DDF60F28415972), - .INIT_65(256'h58718AA3BBD4ED061F385069829BB4CCE5FE173048617A93ACC4DDF60F284059), - .INIT_66(256'h3E576F88A1BAD3EC041D364F688199B2CBE4FD162E47607992AAC3DCF50E273F), - .INIT_67(256'h223B546D869FB8D0E9021B344D667E97B0C9E2FB142C455E7790A9C1DAF30C25), - .INIT_68(256'h061F38516A839CB5CEE6FF18314A637C95ADC6DFF8112A435C748DA6BFD8F10A), - .INIT_69(256'hEA031C344D667F98B1CAE3FC152E465F7891AAC3DCF50E263F58718AA3BCD5EE), - .INIT_6A(256'hCCE5FE173049627B94ADC6DFF81029425B748DA6BFD8F10A223B546D869FB8D1), - .INIT_6B(256'hAEC7E0F9122B445D768FA8C1DAF30C253E566F88A1BAD3EC051E375069829BB3), - .INIT_6C(256'h90A9C2DBF40D263F587189A2BBD4ED061F38516A839CB5CEE70019324B647D95), - .INIT_6D(256'h718AA3BCD5EE072039526A839CB5CEE70019324B647D96AFC8E1FA132C455E77), - .INIT_6E(256'h516A839CB5CEE70019324B647D96AFC8E1FA132C455E7790A9C2DBF40D263F58), - .INIT_6F(256'h314A637C95AEC7E0F9122B445D768FA8C1DAF30C253E577089A2BBD4ED061F38), - .INIT_70(256'h1029425B748DA6BFD8F10A233C556E87A0B9D3EC051E375069829BB4CDE6FF18), - .INIT_71(256'hEF08213A536C859EB7D0E9021B344D678099B2CBE4FD162F48617A93ACC5DEF7), - .INIT_72(256'hCDE6FF18324B647D96AFC8E1FA132C455E7790A9C2DBF40E274059728BA4BDD6), - .INIT_73(256'hABC4DDF71029425B748DA6BFD8F10A233C556F88A1BAD3EC051E375069829BB4), - .INIT_74(256'h89A2BBD4ED061F39526B849DB6CFE8011A334C657F98B1CAE3FC152E47607992), - .INIT_75(256'h667F99B2CBE4FD162F48617A93ACC6DFF8112A435C758EA7C0D9F30C253E5770), - .INIT_76(256'h435C768FA8C1DAF30C253E57718AA3BCD5EE072039526B859EB7D0E9021B344D), - .INIT_77(256'h2039526B859EB7D0E9021B344D668099B2CBE4FD162F48617B94ADC6DFF8112A), - .INIT_78(256'hFD162F48617A93ACC6DFF8112A435C758EA8C1DAF30C253E577089A3BCD5EE07), - .INIT_79(256'hD9F20B243D577089A2BBD4ED061F39526B849DB6CFE8021B344D667F98B1CAE4), - .INIT_7A(256'hB5CEE7001A334C657E97B0C9E3FC152E47607992ACC5DEF71029425B748EA7C0), - .INIT_7B(256'h91AAC3DCF60F28415A738CA5BFD8F10A233C556E88A1BAD3EC051E37516A839C), - .INIT_7C(256'h6D869FB8D1EB041D364F68819AB4CDE6FF18314A637D96AFC8E1FA132D465F78), - .INIT_7D(256'h49627B94ADC6DFF9122B445D768FA9C2DBF40D263F58728BA4BDD6EF08213B54), - .INIT_7E(256'h243D577089A2BBD4ED072039526B849DB6D0E9021B344D668099B2CBE4FD1630), - .INIT_7F(256'h0019324B657E97B0C9E2FB142E47607992ABC4DEF71029425B748EA7C0D9F20B), - .INIT_A(36'h000000000), - .INIT_B(36'h000000000), - .INIT_FILE("NONE"), - .IS_CLKARDCLK_INVERTED(1'b0), - .IS_CLKBWRCLK_INVERTED(1'b0), - .IS_ENARDEN_INVERTED(1'b0), - .IS_ENBWREN_INVERTED(1'b0), - .IS_RSTRAMARSTRAM_INVERTED(1'b0), - .IS_RSTRAMB_INVERTED(1'b0), - .IS_RSTREGARSTREG_INVERTED(1'b0), - .IS_RSTREGB_INVERTED(1'b0), - .RAM_EXTENSION_A("NONE"), - .RAM_EXTENSION_B("NONE"), - .RAM_MODE("TDP"), - .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), - .READ_WIDTH_A(9), - .READ_WIDTH_B(9), - .RSTREG_PRIORITY_A("REGCE"), - .RSTREG_PRIORITY_B("REGCE"), - .SIM_COLLISION_CHECK("ALL"), - .SIM_DEVICE("7SERIES"), - .SRVAL_A(36'h000000000), - .SRVAL_B(36'h000000000), - .WRITE_MODE_A("WRITE_FIRST"), - .WRITE_MODE_B("WRITE_FIRST"), - .WRITE_WIDTH_A(9), - .WRITE_WIDTH_B(9)) - \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram - (.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}), - .ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}), - .CASCADEINA(1'b0), - .CASCADEINB(1'b0), - .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), - .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), - .CLKARDCLK(clka), - .CLKBWRCLK(clkb), - .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), - .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIPADIP({1'b0,1'b0,1'b0,1'b0}), - .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), - .DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],douta_array[7:0]}), - .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}), - .DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],douta_array[8]}), - .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}), - .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), - .ENARDEN(addra[12]), - .ENBWREN(addrb[12]), - .INJECTDBITERR(1'b0), - .INJECTSBITERR(1'b0), - .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), - .REGCEAREGCE(1'b1), - .REGCEB(1'b1), - .RSTRAMARSTRAM(1'b0), - .RSTRAMB(1'b0), - .RSTREGARSTREG(1'b0), - .RSTREGB(1'b0), - .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), - .WEA({1'b0,1'b0,1'b0,1'b0}), - .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) -module COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized1 - (douta_array, - doutb_array, - ena_array, - enb_array, - clka, - clkb, - addra, - addrb); - output [8:0]douta_array; - output [8:0]doutb_array; - output [0:0]ena_array; - output [0:0]enb_array; - input clka; - input clkb; - input [12:0]addra; - input [12:0]addrb; - - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [8:0]douta_array; - wire [8:0]doutb_array; - wire [0:0]ena_array; - wire [0:0]enb_array; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; - wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; - wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; - wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; - wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; - wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; - - (* box_type = "PRIMITIVE" *) - RAMB36E1 #( - .DOA_REG(1), - .DOB_REG(1), - .EN_ECC_READ("FALSE"), - .EN_ECC_WRITE("FALSE"), - .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_00(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_01(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_02(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_04(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_06(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_07(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_08(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_09(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_0E(256'hFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFFFFFFFFFFFFFFFFFFFFFFFFFF), - .INIT_0F(256'hFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE), - .INIT_10(256'hFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE), - .INIT_11(256'hFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE), - .INIT_12(256'hFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE), - .INIT_13(256'hFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE), - .INIT_14(256'hFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFEFEFEFEFEFEFEFEFEFEFEFEFE), - .INIT_15(256'hFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFD), - .INIT_16(256'hFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFD), - .INIT_17(256'hFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFD), - .INIT_18(256'hFCFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFD), - .INIT_19(256'hFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFC), - .INIT_1A(256'hFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFC), - .INIT_1B(256'hFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFC), - .INIT_1C(256'hFBFBFBFBFBFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFC), - .INIT_1D(256'hFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFB), - .INIT_1E(256'hFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFB), - .INIT_1F(256'hFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFB), - .INIT_20(256'hFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFBFBFBFBFBFBFBFBFB), - .INIT_21(256'hFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFA), - .INIT_22(256'hFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFA), - .INIT_23(256'hF9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9FAFAFAFAFAFAFAFAFAFAFAFA), - .INIT_24(256'hF9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9), - .INIT_25(256'hF9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9), - .INIT_26(256'hF8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F9F9F9F9F9F9F9), - .INIT_27(256'hF8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8), - .INIT_28(256'hF7F7F7F7F7F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8), - .INIT_29(256'hF7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7), - .INIT_2A(256'hF7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7), - .INIT_2B(256'hF6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F7F7F7F7F7F7F7F7F7F7F7), - .INIT_2C(256'hF6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6), - .INIT_2D(256'hF5F5F5F5F5F5F5F5F5F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6), - .INIT_2E(256'hF5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5), - .INIT_2F(256'hF4F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5), - .INIT_30(256'hF4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4), - .INIT_31(256'hF4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4), - .INIT_32(256'hF3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F4F4F4), - .INIT_33(256'hF3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3), - .INIT_34(256'hF2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F3F3F3F3F3), - .INIT_35(256'hF2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2), - .INIT_36(256'hF1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F2F2F2F2F2), - .INIT_37(256'hF1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1), - .INIT_38(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F1F1), - .INIT_39(256'hEFEFF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0), - .INIT_3A(256'hEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEF), - .INIT_3B(256'hEEEEEEEEEEEEEEEEEEEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEF), - .INIT_3C(256'hEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE), - .INIT_3D(256'hEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE), - .INIT_3E(256'hEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDED), - .INIT_3F(256'hECECECECECECECECECECECECECECECECECECECECECECECECECECEDEDEDEDEDED), - .INIT_40(256'hEBEBEBEBEBECECECECECECECECECECECECECECECECECECECECECECECECECECEC), - .INIT_41(256'hEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEB), - .INIT_42(256'hEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEBEBEBEBEBEBEBEBEBEBEBEBEBEBEB), - .INIT_43(256'hEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEA), - .INIT_44(256'hE9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EAEA), - .INIT_45(256'hE8E8E8E8E8E8E8E8E8E8E8E8E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9), - .INIT_46(256'hE8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8), - .INIT_47(256'hE7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E8E8E8E8), - .INIT_48(256'hE6E6E6E6E6E6E6E6E6E6E6E6E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7), - .INIT_49(256'hE6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6), - .INIT_4A(256'hE5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E6E6E6), - .INIT_4B(256'hE4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5), - .INIT_4C(256'hE3E3E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4), - .INIT_4D(256'hE3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3), - .INIT_4E(256'hE2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E3E3E3E3E3E3E3E3E3E3E3), - .INIT_4F(256'hE1E1E1E1E1E1E1E1E1E1E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2), - .INIT_50(256'hE1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1), - .INIT_51(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E1), - .INIT_52(256'hDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFE0E0E0E0E0E0E0E0E0E0E0E0), - .INIT_53(256'hDEDEDEDEDEDEDEDEDEDEDEDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDF), - .INIT_54(256'hDDDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDE), - .INIT_55(256'hDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD), - .INIT_56(256'hDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDDDDDDDDDDDDDD), - .INIT_57(256'hDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDCDCDCDCDCDCDCDCDCDCDCDCDCDCDC), - .INIT_58(256'hDADADADADADADADADADBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDB), - .INIT_59(256'hD9D9DADADADADADADADADADADADADADADADADADADADADADADADADADADADADADA), - .INIT_5A(256'hD9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9), - .INIT_5B(256'hD8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D9D9D9D9D9), - .INIT_5C(256'hD7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D8D8D8D8D8D8D8D8D8D8D8), - .INIT_5D(256'hD6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7), - .INIT_5E(256'hD5D5D5D5D5D5D5D5D5D5D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6), - .INIT_5F(256'hD4D4D4D4D4D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5), - .INIT_60(256'hD3D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4), - .INIT_61(256'hD3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3), - .INIT_62(256'hD2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D3D3D3D3), - .INIT_63(256'hD1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D2D2D2D2D2D2D2), - .INIT_64(256'hD0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D1D1D1D1D1D1D1D1D1D1D1), - .INIT_65(256'hCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFD0D0D0D0D0D0D0D0D0D0D0D0D0D0), - .INIT_66(256'hCECECECECECECECECECECECECECECECFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCF), - .INIT_67(256'hCDCDCDCDCDCDCDCDCDCDCDCDCDCECECECECECECECECECECECECECECECECECECE), - .INIT_68(256'hCCCCCCCCCCCCCCCCCCCCCCCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCD), - .INIT_69(256'hCBCBCBCBCBCBCBCBCBCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC), - .INIT_6A(256'hCACACACACACACACBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCB), - .INIT_6B(256'hC9C9C9C9C9C9CACACACACACACACACACACACACACACACACACACACACACACACACACA), - .INIT_6C(256'hC8C8C8C8C8C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9), - .INIT_6D(256'hC7C7C7C7C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8), - .INIT_6E(256'hC6C6C6C6C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7), - .INIT_6F(256'hC5C5C5C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6), - .INIT_70(256'hC4C4C4C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5), - .INIT_71(256'hC3C3C3C3C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4), - .INIT_72(256'hC2C2C2C2C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3), - .INIT_73(256'hC1C1C1C1C1C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2), - .INIT_74(256'hC0C0C0C0C0C0C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1), - .INIT_75(256'hBFBFBFBFBFBFBFC0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0), - .INIT_76(256'hBEBEBEBEBEBEBEBEBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBF), - .INIT_77(256'hBDBDBDBDBDBDBDBDBDBDBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBE), - .INIT_78(256'hBCBCBCBCBCBCBCBCBCBCBCBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBD), - .INIT_79(256'hBBBBBBBBBBBBBBBBBBBBBBBBBBBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBC), - .INIT_7A(256'hBABABABABABABABABABABABABABABABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB), - .INIT_7B(256'hB9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9BABABABABABABABABABABABABABA), - .INIT_7C(256'hB8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B9B9B9B9B9B9B9B9B9B9B9B9), - .INIT_7D(256'hB7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B8B8B8B8B8B8B8B8B8), - .INIT_7E(256'hB6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B7B7B7B7B7B7B7), - .INIT_7F(256'hB5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B6B6B6B6), - .INIT_A(36'h000000000), - .INIT_B(36'h000000000), - .INIT_FILE("NONE"), - .IS_CLKARDCLK_INVERTED(1'b0), - .IS_CLKBWRCLK_INVERTED(1'b0), - .IS_ENARDEN_INVERTED(1'b0), - .IS_ENBWREN_INVERTED(1'b0), - .IS_RSTRAMARSTRAM_INVERTED(1'b0), - .IS_RSTRAMB_INVERTED(1'b0), - .IS_RSTREGARSTREG_INVERTED(1'b0), - .IS_RSTREGB_INVERTED(1'b0), - .RAM_EXTENSION_A("NONE"), - .RAM_EXTENSION_B("NONE"), - .RAM_MODE("TDP"), - .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), - .READ_WIDTH_A(9), - .READ_WIDTH_B(9), - .RSTREG_PRIORITY_A("REGCE"), - .RSTREG_PRIORITY_B("REGCE"), - .SIM_COLLISION_CHECK("ALL"), - .SIM_DEVICE("7SERIES"), - .SRVAL_A(36'h000000000), - .SRVAL_B(36'h000000000), - .WRITE_MODE_A("WRITE_FIRST"), - .WRITE_MODE_B("WRITE_FIRST"), - .WRITE_WIDTH_A(9), - .WRITE_WIDTH_B(9)) - \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram - (.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}), - .ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}), - .CASCADEINA(1'b0), - .CASCADEINB(1'b0), - .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), - .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), - .CLKARDCLK(clka), - .CLKBWRCLK(clkb), - .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), - .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIPADIP({1'b0,1'b0,1'b0,1'b0}), - .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), - .DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],douta_array[7:0]}), - .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}), - .DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],douta_array[8]}), - .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}), - .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), - .ENARDEN(ena_array), - .ENBWREN(enb_array), - .INJECTDBITERR(1'b0), - .INJECTSBITERR(1'b0), - .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), - .REGCEAREGCE(1'b1), - .REGCEB(1'b1), - .RSTRAMARSTRAM(1'b0), - .RSTRAMB(1'b0), - .RSTREGARSTREG(1'b0), - .RSTREGB(1'b0), - .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), - .WEA({1'b0,1'b0,1'b0,1'b0}), - .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); - LUT1 #( - .INIT(2'h1)) - \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1 - (.I0(addra[12]), - .O(ena_array)); - LUT1 #( - .INIT(2'h1)) - \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2 - (.I0(addrb[12]), - .O(enb_array)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) -module COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized2 - (douta_array, - doutb_array, - clka, - clkb, - addra, - addrb); - output [8:0]douta_array; - output [8:0]doutb_array; - input clka; - input clkb; - input [12:0]addra; - input [12:0]addrb; - - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [8:0]douta_array; - wire [8:0]doutb_array; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; - wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; - wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; - wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; - wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; - wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; - - (* box_type = "PRIMITIVE" *) - RAMB36E1 #( - .DOA_REG(1), - .DOB_REG(1), - .EN_ECC_READ("FALSE"), - .EN_ECC_WRITE("FALSE"), - .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_00(256'hB3B3B3B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B5), - .INIT_01(256'hB2B2B2B2B2B2B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3), - .INIT_02(256'hB1B1B1B1B1B1B1B1B1B1B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2), - .INIT_03(256'hB0B0B0B0B0B0B0B0B0B0B0B0B0B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1), - .INIT_04(256'hAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFB0B0B0B0B0B0B0B0B0B0B0B0B0B0B0), - .INIT_05(256'hAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAFAFAFAFAFAFAFAFAFAFAF), - .INIT_06(256'hADADADADADADADADADADADADADADADADADADADADADADADADADADAEAEAEAEAEAE), - .INIT_07(256'hABABACACACACACACACACACACACACACACACACACACACACACACACACACACACACADAD), - .INIT_08(256'hAAAAAAAAAAAAAAABABABABABABABABABABABABABABABABABABABABABABABABAB), - .INIT_09(256'hA9A9A9A9A9A9A9A9A9A9A9A9AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA), - .INIT_0A(256'hA8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9), - .INIT_0B(256'hA7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A8A8A8A8A8A8A8A8A8A8A8), - .INIT_0C(256'hA6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A7A7A7A7A7A7), - .INIT_0D(256'hA4A4A4A4A4A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5), - .INIT_0E(256'hA3A3A3A3A3A3A3A3A3A3A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4), - .INIT_0F(256'hA2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3), - .INIT_10(256'hA1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A2A2A2A2A2A2A2A2A2A2A2), - .INIT_11(256'h9FA0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A1A1A1A1A1), - .INIT_12(256'h9E9E9E9E9E9E9E9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F), - .INIT_13(256'h9D9D9D9D9D9D9D9D9D9D9D9D9D9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E), - .INIT_14(256'h9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9D9D9D9D9D9D9D9D9D9D9D9D9D), - .INIT_15(256'h9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9C9C9C9C9C9C9C), - .INIT_16(256'h9999999999999A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A), - .INIT_17(256'h9898989898989898989898989899999999999999999999999999999999999999), - .INIT_18(256'h9797979797979797979797979797979797979798989898989898989898989898), - .INIT_19(256'h9596969696969696969696969696969696969696969696969696979797979797), - .INIT_1A(256'h9494949494949494959595959595959595959595959595959595959595959595), - .INIT_1B(256'h9393939393939393939393939393939494949494949494949494949494949494), - .INIT_1C(256'h9292929292929292929292929292929292929292929293939393939393939393), - .INIT_1D(256'h9090909091919191919191919191919191919191919191919191919191929292), - .INIT_1E(256'h8F8F8F8F8F8F8F8F8F8F8F8F9090909090909090909090909090909090909090), - .INIT_1F(256'h8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8F8F8F8F8F8F8F8F8F8F8F8F8F), - .INIT_20(256'h8C8C8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8E8E8E8E8E), - .INIT_21(256'h8B8B8B8B8B8B8B8B8B8B8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C), - .INIT_22(256'h8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B), - .INIT_23(256'h888989898989898989898989898989898989898989898989898A8A8A8A8A8A8A), - .INIT_24(256'h8787878787878787878888888888888888888888888888888888888888888888), - .INIT_25(256'h8686868686868686868686868686868686878787878787878787878787878787), - .INIT_26(256'h8485858585858585858585858585858585858585858585858586868686868686), - .INIT_27(256'h8383838383838383838484848484848484848484848484848484848484848484), - .INIT_28(256'h8282828282828282828282828282828282828383838383838383838383838383), - .INIT_29(256'h8080818181818181818181818181818181818181818181818181828282828282), - .INIT_2A(256'h7F7F7F7F7F7F7F7F7F7F7F808080808080808080808080808080808080808080), - .INIT_2B(256'h7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7F7F7F7F7F7F7F7F7F7F7F7F7F), - .INIT_2C(256'h7C7C7C7C7C7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7E7E7E7E), - .INIT_2D(256'h7B7B7B7B7B7B7B7B7B7B7B7B7B7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C), - .INIT_2E(256'h7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7B7B7B7B7B7B7B7B7B7B), - .INIT_2F(256'h787878787878787879797979797979797979797979797979797979797979797A), - .INIT_30(256'h7777777777777777777777777777777777787878787878787878787878787878), - .INIT_31(256'h7575757676767676767676767676767676767676767676767676777777777777), - .INIT_32(256'h7474747474747474747474747575757575757575757575757575757575757575), - .INIT_33(256'h7373737373737373737373737373737373737373737474747474747474747474), - .INIT_34(256'h7171717171717172727272727272727272727272727272727272727272727373), - .INIT_35(256'h7070707070707070707070707070707071717171717171717171717171717171), - .INIT_36(256'h6E6E6E6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F707070707070), - .INIT_37(256'h6D6D6D6D6D6D6D6D6D6D6D6D6D6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E), - .INIT_38(256'h6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6D6D6D6D6D6D6D6D6D6D), - .INIT_39(256'h6A6A6A6A6A6A6A6A6A6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6C), - .INIT_3A(256'h696969696969696969696969696969696969696A6A6A6A6A6A6A6A6A6A6A6A6A), - .INIT_3B(256'h6767676767676868686868686868686868686868686868686868686869696969), - .INIT_3C(256'h6666666666666666666666666666666667676767676767676767676767676767), - .INIT_3D(256'h6464646565656565656565656565656565656565656565656566666666666666), - .INIT_3E(256'h6363636363636363636363636364646464646464646464646464646464646464), - .INIT_3F(256'h6162626262626262626262626262626262626262626262636363636363636363), - .INIT_40(256'h6060606060606060606060616161616161616161616161616161616161616161), - .INIT_41(256'h5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F6060606060606060606060), - .INIT_42(256'h5D5D5D5D5D5D5D5D5D5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5F), - .INIT_43(256'h5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5D5D5D5D5D5D5D5D5D5D5D5D5D), - .INIT_44(256'h5A5A5A5A5A5A5A5A5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5C5C5C), - .INIT_45(256'h5959595959595959595959595959595959595A5A5A5A5A5A5A5A5A5A5A5A5A5A), - .INIT_46(256'h5757575757575858585858585858585858585858585858585858585859595959), - .INIT_47(256'h5656565656565656565656565656565656575757575757575757575757575757), - .INIT_48(256'h5454545454555555555555555555555555555555555555555555555656565656), - .INIT_49(256'h5353535353535353535353535353535354545454545454545454545454545454), - .INIT_4A(256'h5151515151525252525252525252525252525252525252525252535353535353), - .INIT_4B(256'h5050505050505050505050505050505151515151515151515151515151515151), - .INIT_4C(256'h4E4E4E4E4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F505050505050), - .INIT_4D(256'h4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E), - .INIT_4E(256'h4B4B4B4B4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4D4D4D4D4D4D), - .INIT_4F(256'h4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B), - .INIT_50(256'h48484848494949494949494949494949494949494949494949494A4A4A4A4A4A), - .INIT_51(256'h4747474747474747474747474747474848484848484848484848484848484848), - .INIT_52(256'h4545454545464646464646464646464646464646464646464646474747474747), - .INIT_53(256'h4444444444444444444444444444444445454545454545454545454545454545), - .INIT_54(256'h4242424242434343434343434343434343434343434343434343444444444444), - .INIT_55(256'h4141414141414141414141414141414142424242424242424242424242424242), - .INIT_56(256'h3F3F3F3F3F3F4040404040404040404040404040404040404040404141414141), - .INIT_57(256'h3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F), - .INIT_58(256'h3C3C3C3C3C3C3C3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3E3E3E3E), - .INIT_59(256'h3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3C3C3C3C3C3C3C3C3C3C3C3C3C3C), - .INIT_5A(256'h39393939393939393A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3B3B3B), - .INIT_5B(256'h3838383838383838383838383838383838383839393939393939393939393939), - .INIT_5C(256'h3636363636363636363637373737373737373737373737373737373737373838), - .INIT_5D(256'h3535353535353535353535353535353535353535353636363636363636363636), - .INIT_5E(256'h3333333333333333333333343434343434343434343434343434343434343434), - .INIT_5F(256'h3131323232323232323232323232323232323232323233333333333333333333), - .INIT_60(256'h3030303030303030303030303031313131313131313131313131313131313131), - .INIT_61(256'h2E2E2E2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F3030303030303030), - .INIT_62(256'h2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E), - .INIT_63(256'h2B2B2B2B2B2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2D2D2D2D2D2D), - .INIT_64(256'h2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B), - .INIT_65(256'h282828282828282929292929292929292929292929292929292929292A2A2A2A), - .INIT_66(256'h2727272727272727272727272727272727272728282828282828282828282828), - .INIT_67(256'h2525252525252525252626262626262626262626262626262626262626262727), - .INIT_68(256'h2424242424242424242424242424242424242424242525252525252525252525), - .INIT_69(256'h2222222222222222222222222323232323232323232323232323232323232323), - .INIT_6A(256'h2020202121212121212121212121212121212121212121222222222222222222), - .INIT_6B(256'h1F1F1F1F1F1F1F1F1F1F1F1F1F1F202020202020202020202020202020202020), - .INIT_6C(256'h1D1D1D1D1D1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1F1F1F1F1F1F1F), - .INIT_6D(256'h1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D), - .INIT_6E(256'h1A1A1A1A1A1A1A1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1C1C1C1C), - .INIT_6F(256'h191919191919191919191919191919191919191A1A1A1A1A1A1A1A1A1A1A1A1A), - .INIT_70(256'h1717171717171717171718181818181818181818181818181818181818181819), - .INIT_71(256'h1516161616161616161616161616161616161616161617171717171717171717), - .INIT_72(256'h1414141414141414141414141415151515151515151515151515151515151515), - .INIT_73(256'h1212121213131313131313131313131313131313131313131414141414141414), - .INIT_74(256'h1111111111111111111111111111111212121212121212121212121212121212), - .INIT_75(256'h0F0F0F0F0F0F0F10101010101010101010101010101010101010101111111111), - .INIT_76(256'h0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0F0F0F0F0F0F0F0F0F0F0F0F0F0F), - .INIT_77(256'h0C0C0C0C0C0C0C0C0C0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0E0E), - .INIT_78(256'h0A0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0C0C0C0C0C0C0C0C0C0C0C), - .INIT_79(256'h0909090909090909090909090A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A), - .INIT_7A(256'h0707070808080808080808080808080808080808080808080909090909090909), - .INIT_7B(256'h0606060606060606060606060606060707070707070707070707070707070707), - .INIT_7C(256'h0404040404040505050505050505050505050505050505050505050606060606), - .INIT_7D(256'h0303030303030303030303030303030303030404040404040404040404040404), - .INIT_7E(256'h0101010101010101010202020202020202020202020202020202020202020303), - .INIT_7F(256'h0000000000000000000000000000000000000000000101010101010101010101), - .INIT_A(36'h000000000), - .INIT_B(36'h000000000), - .INIT_FILE("NONE"), - .IS_CLKARDCLK_INVERTED(1'b0), - .IS_CLKBWRCLK_INVERTED(1'b0), - .IS_ENARDEN_INVERTED(1'b0), - .IS_ENBWREN_INVERTED(1'b0), - .IS_RSTRAMARSTRAM_INVERTED(1'b0), - .IS_RSTRAMB_INVERTED(1'b0), - .IS_RSTREGARSTREG_INVERTED(1'b0), - .IS_RSTREGB_INVERTED(1'b0), - .RAM_EXTENSION_A("NONE"), - .RAM_EXTENSION_B("NONE"), - .RAM_MODE("TDP"), - .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), - .READ_WIDTH_A(9), - .READ_WIDTH_B(9), - .RSTREG_PRIORITY_A("REGCE"), - .RSTREG_PRIORITY_B("REGCE"), - .SIM_COLLISION_CHECK("ALL"), - .SIM_DEVICE("7SERIES"), - .SRVAL_A(36'h000000000), - .SRVAL_B(36'h000000000), - .WRITE_MODE_A("WRITE_FIRST"), - .WRITE_MODE_B("WRITE_FIRST"), - .WRITE_WIDTH_A(9), - .WRITE_WIDTH_B(9)) - \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram - (.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}), - .ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}), - .CASCADEINA(1'b0), - .CASCADEINB(1'b0), - .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), - .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), - .CLKARDCLK(clka), - .CLKBWRCLK(clkb), - .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), - .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIPADIP({1'b0,1'b0,1'b0,1'b0}), - .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), - .DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],douta_array[7:0]}), - .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}), - .DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],douta_array[8]}), - .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}), - .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), - .ENARDEN(addra[12]), - .ENBWREN(addrb[12]), - .INJECTDBITERR(1'b0), - .INJECTSBITERR(1'b0), - .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), - .REGCEAREGCE(1'b1), - .REGCEB(1'b1), - .RSTRAMARSTRAM(1'b0), - .RSTRAMB(1'b0), - .RSTREGARSTREG(1'b0), - .RSTREGB(1'b0), - .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), - .WEA({1'b0,1'b0,1'b0,1'b0}), - .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_top" *) -module COSLUT_10_16bit_blk_mem_gen_top - (douta, - doutb, - clka, - clkb, - addra, - addrb); - output [17:0]douta; - output [17:0]doutb; - input clka; - input clkb; - input [12:0]addra; - input [12:0]addrb; - - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [17:0]douta; - wire [17:0]doutb; - - COSLUT_10_16bit_blk_mem_gen_generic_cstr \valid.cstr - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .douta(douta), - .doutb(doutb)); -endmodule - -(* C_ADDRA_WIDTH = "13" *) (* C_ADDRB_WIDTH = "13" *) (* C_ALGORITHM = "1" *) -(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *) -(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "0" *) -(* C_COUNT_36K_BRAM = "4" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *) -(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *) -(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *) -(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *) -(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 9.414399 mW" *) -(* C_FAMILY = "kintex7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *) -(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *) -(* C_HAS_MEM_OUTPUT_REGS_B = "1" *) (* C_HAS_MUX_OUTPUT_REGS_A = "1" *) (* C_HAS_MUX_OUTPUT_REGS_B = "1" *) -(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *) -(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) -(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "COSLUT_10_16bit.mem" *) -(* C_INIT_FILE_NAME = "COSLUT_10_16bit.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *) -(* C_MEM_TYPE = "4" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *) -(* C_READ_DEPTH_A = "8192" *) (* C_READ_DEPTH_B = "8192" *) (* C_READ_LATENCY_A = "1" *) -(* C_READ_LATENCY_B = "1" *) (* C_READ_WIDTH_A = "18" *) (* C_READ_WIDTH_B = "18" *) -(* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *) -(* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *) -(* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *) -(* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *) -(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "8192" *) -(* C_WRITE_DEPTH_B = "8192" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) -(* C_WRITE_WIDTH_A = "18" *) (* C_WRITE_WIDTH_B = "18" *) (* C_XDEVICEFAMILY = "kintex7" *) -(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3" *) (* downgradeipidentifiedwarnings = "yes" *) -module COSLUT_10_16bit_blk_mem_gen_v8_4_3 - (clka, - rsta, - ena, - regcea, - wea, - addra, - dina, - douta, - clkb, - rstb, - enb, - regceb, - web, - addrb, - dinb, - doutb, - injectsbiterr, - injectdbiterr, - eccpipece, - sbiterr, - dbiterr, - rdaddrecc, - sleep, - deepsleep, - shutdown, - rsta_busy, - rstb_busy, - s_aclk, - s_aresetn, - s_axi_awid, - s_axi_awaddr, - s_axi_awlen, - s_axi_awsize, - s_axi_awburst, - s_axi_awvalid, - s_axi_awready, - s_axi_wdata, - s_axi_wstrb, - s_axi_wlast, - s_axi_wvalid, - s_axi_wready, - s_axi_bid, - s_axi_bresp, - s_axi_bvalid, - s_axi_bready, - s_axi_arid, - s_axi_araddr, - s_axi_arlen, - s_axi_arsize, - s_axi_arburst, - s_axi_arvalid, - s_axi_arready, - s_axi_rid, - s_axi_rdata, - s_axi_rresp, - s_axi_rlast, - s_axi_rvalid, - s_axi_rready, - s_axi_injectsbiterr, - s_axi_injectdbiterr, - s_axi_sbiterr, - s_axi_dbiterr, - s_axi_rdaddrecc); - input clka; - input rsta; - input ena; - input regcea; - input [0:0]wea; - input [12:0]addra; - input [17:0]dina; - output [17:0]douta; - input clkb; - input rstb; - input enb; - input regceb; - input [0:0]web; - input [12:0]addrb; - input [17:0]dinb; - output [17:0]doutb; - input injectsbiterr; - input injectdbiterr; - input eccpipece; - output sbiterr; - output dbiterr; - output [12:0]rdaddrecc; - input sleep; - input deepsleep; - input shutdown; - output rsta_busy; - output rstb_busy; - input s_aclk; - input s_aresetn; - input [3:0]s_axi_awid; - input [31:0]s_axi_awaddr; - input [7:0]s_axi_awlen; - input [2:0]s_axi_awsize; - input [1:0]s_axi_awburst; - input s_axi_awvalid; - output s_axi_awready; - input [17:0]s_axi_wdata; - input [0:0]s_axi_wstrb; - input s_axi_wlast; - input s_axi_wvalid; - output s_axi_wready; - output [3:0]s_axi_bid; - output [1:0]s_axi_bresp; - output s_axi_bvalid; - input s_axi_bready; - input [3:0]s_axi_arid; - input [31:0]s_axi_araddr; - input [7:0]s_axi_arlen; - input [2:0]s_axi_arsize; - input [1:0]s_axi_arburst; - input s_axi_arvalid; - output s_axi_arready; - output [3:0]s_axi_rid; - output [17:0]s_axi_rdata; - output [1:0]s_axi_rresp; - output s_axi_rlast; - output s_axi_rvalid; - input s_axi_rready; - input s_axi_injectsbiterr; - input s_axi_injectdbiterr; - output s_axi_sbiterr; - output s_axi_dbiterr; - output [12:0]s_axi_rdaddrecc; - - wire \ ; - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [17:0]douta; - wire [17:0]doutb; - - assign dbiterr = \ ; - assign rdaddrecc[12] = \ ; - assign rdaddrecc[11] = \ ; - assign rdaddrecc[10] = \ ; - assign rdaddrecc[9] = \ ; - assign rdaddrecc[8] = \ ; - assign rdaddrecc[7] = \ ; - assign rdaddrecc[6] = \ ; - assign rdaddrecc[5] = \ ; - assign rdaddrecc[4] = \ ; - assign rdaddrecc[3] = \ ; - assign rdaddrecc[2] = \ ; - assign rdaddrecc[1] = \ ; - assign rdaddrecc[0] = \ ; - assign rsta_busy = \ ; - assign rstb_busy = \ ; - assign s_axi_arready = \ ; - assign s_axi_awready = \ ; - assign s_axi_bid[3] = \ ; - assign s_axi_bid[2] = \ ; - assign s_axi_bid[1] = \ ; - assign s_axi_bid[0] = \ ; - assign s_axi_bresp[1] = \ ; - assign s_axi_bresp[0] = \ ; - assign s_axi_bvalid = \ ; - assign s_axi_dbiterr = \ ; - assign s_axi_rdaddrecc[12] = \ ; - assign s_axi_rdaddrecc[11] = \ ; - assign s_axi_rdaddrecc[10] = \ ; - assign s_axi_rdaddrecc[9] = \ ; - assign s_axi_rdaddrecc[8] = \ ; - assign s_axi_rdaddrecc[7] = \ ; - assign s_axi_rdaddrecc[6] = \ ; - assign s_axi_rdaddrecc[5] = \ ; - assign s_axi_rdaddrecc[4] = \ ; - assign s_axi_rdaddrecc[3] = \ ; - assign s_axi_rdaddrecc[2] = \ ; - assign s_axi_rdaddrecc[1] = \ ; - assign s_axi_rdaddrecc[0] = \ ; - assign s_axi_rdata[17] = \ ; - assign s_axi_rdata[16] = \ ; - assign s_axi_rdata[15] = \ ; - assign s_axi_rdata[14] = \ ; - assign s_axi_rdata[13] = \ ; - assign s_axi_rdata[12] = \ ; - assign s_axi_rdata[11] = \ ; - assign s_axi_rdata[10] = \ ; - assign s_axi_rdata[9] = \ ; - assign s_axi_rdata[8] = \ ; - assign s_axi_rdata[7] = \ ; - assign s_axi_rdata[6] = \ ; - assign s_axi_rdata[5] = \ ; - assign s_axi_rdata[4] = \ ; - assign s_axi_rdata[3] = \ ; - assign s_axi_rdata[2] = \ ; - assign s_axi_rdata[1] = \ ; - assign s_axi_rdata[0] = \ ; - assign s_axi_rid[3] = \ ; - assign s_axi_rid[2] = \ ; - assign s_axi_rid[1] = \ ; - assign s_axi_rid[0] = \ ; - assign s_axi_rlast = \ ; - assign s_axi_rresp[1] = \ ; - assign s_axi_rresp[0] = \ ; - assign s_axi_rvalid = \ ; - assign s_axi_sbiterr = \ ; - assign s_axi_wready = \ ; - assign sbiterr = \ ; - GND GND - (.G(\ )); - COSLUT_10_16bit_blk_mem_gen_v8_4_3_synth inst_blk_mem_gen - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .douta(douta), - .doutb(doutb)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3_synth" *) -module COSLUT_10_16bit_blk_mem_gen_v8_4_3_synth - (douta, - doutb, - clka, - clkb, - addra, - addrb); - output [17:0]douta; - output [17:0]doutb; - input clka; - input clkb; - input [12:0]addra; - input [12:0]addrb; - - wire [12:0]addra; - wire [12:0]addrb; - wire clka; - wire clkb; - wire [17:0]douta; - wire [17:0]doutb; - - COSLUT_10_16bit_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen - (.addra(addra), - .addrb(addrb), - .clka(clka), - .clkb(clkb), - .douta(douta), - .doutb(doutb)); -endmodule -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_sim_netlist.vhdl deleted file mode 100644 index 117bed13..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_sim_netlist.vhdl +++ /dev/null @@ -1,2784 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:34:22 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_sim_netlist.vhdl --- Design : COSLUT_10_16bit --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity COSLUT_10_16bit_blk_mem_gen_mux is - port ( - douta : out STD_LOGIC_VECTOR ( 17 downto 0 ); - addra : in STD_LOGIC_VECTOR ( 0 to 0 ); - clka : in STD_LOGIC; - douta_array : in STD_LOGIC_VECTOR ( 35 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of COSLUT_10_16bit_blk_mem_gen_mux : entity is "blk_mem_gen_mux"; -end COSLUT_10_16bit_blk_mem_gen_mux; - -architecture STRUCTURE of COSLUT_10_16bit_blk_mem_gen_mux is - signal dout_pipe : STD_LOGIC_VECTOR ( 17 downto 0 ); - signal sel_pipe : STD_LOGIC; - signal sel_pipe_d1 : STD_LOGIC; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[0]_i_1\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[10]_i_1\ : label is "soft_lutpair5"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[11]_i_1\ : label is "soft_lutpair5"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[12]_i_1\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[13]_i_1\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[14]_i_1\ : label is "soft_lutpair7"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[15]_i_1\ : label is "soft_lutpair7"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[16]_i_1\ : label is "soft_lutpair8"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[17]_i_1\ : label is "soft_lutpair8"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[1]_i_1\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[2]_i_1\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[3]_i_1\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[4]_i_1\ : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[5]_i_1\ : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[6]_i_1\ : label is "soft_lutpair3"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[7]_i_1\ : label is "soft_lutpair3"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[8]_i_1\ : label is "soft_lutpair4"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[9]_i_1\ : label is "soft_lutpair4"; -begin -\no_softecc_gmuxr.ce_pri.dout_i[0]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(18), - I1 => sel_pipe_d1, - I2 => douta_array(0), - O => dout_pipe(0) - ); -\no_softecc_gmuxr.ce_pri.dout_i[10]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(28), - I1 => sel_pipe_d1, - I2 => douta_array(10), - O => dout_pipe(10) - ); -\no_softecc_gmuxr.ce_pri.dout_i[11]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(29), - I1 => sel_pipe_d1, - I2 => douta_array(11), - O => dout_pipe(11) - ); -\no_softecc_gmuxr.ce_pri.dout_i[12]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(30), - I1 => sel_pipe_d1, - I2 => douta_array(12), - O => dout_pipe(12) - ); -\no_softecc_gmuxr.ce_pri.dout_i[13]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(31), - I1 => sel_pipe_d1, - I2 => douta_array(13), - O => dout_pipe(13) - ); -\no_softecc_gmuxr.ce_pri.dout_i[14]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(32), - I1 => sel_pipe_d1, - I2 => douta_array(14), - O => dout_pipe(14) - ); -\no_softecc_gmuxr.ce_pri.dout_i[15]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(33), - I1 => sel_pipe_d1, - I2 => douta_array(15), - O => dout_pipe(15) - ); -\no_softecc_gmuxr.ce_pri.dout_i[16]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(34), - I1 => sel_pipe_d1, - I2 => douta_array(16), - O => dout_pipe(16) - ); -\no_softecc_gmuxr.ce_pri.dout_i[17]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(35), - I1 => sel_pipe_d1, - I2 => douta_array(17), - O => dout_pipe(17) - ); -\no_softecc_gmuxr.ce_pri.dout_i[1]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(19), - I1 => sel_pipe_d1, - I2 => douta_array(1), - O => dout_pipe(1) - ); -\no_softecc_gmuxr.ce_pri.dout_i[2]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(20), - I1 => sel_pipe_d1, - I2 => douta_array(2), - O => dout_pipe(2) - ); -\no_softecc_gmuxr.ce_pri.dout_i[3]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(21), - I1 => sel_pipe_d1, - I2 => douta_array(3), - O => dout_pipe(3) - ); -\no_softecc_gmuxr.ce_pri.dout_i[4]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(22), - I1 => sel_pipe_d1, - I2 => douta_array(4), - O => dout_pipe(4) - ); -\no_softecc_gmuxr.ce_pri.dout_i[5]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(23), - I1 => sel_pipe_d1, - I2 => douta_array(5), - O => dout_pipe(5) - ); -\no_softecc_gmuxr.ce_pri.dout_i[6]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(24), - I1 => sel_pipe_d1, - I2 => douta_array(6), - O => dout_pipe(6) - ); -\no_softecc_gmuxr.ce_pri.dout_i[7]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(25), - I1 => sel_pipe_d1, - I2 => douta_array(7), - O => dout_pipe(7) - ); -\no_softecc_gmuxr.ce_pri.dout_i[8]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(26), - I1 => sel_pipe_d1, - I2 => douta_array(8), - O => dout_pipe(8) - ); -\no_softecc_gmuxr.ce_pri.dout_i[9]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => douta_array(27), - I1 => sel_pipe_d1, - I2 => douta_array(9), - O => dout_pipe(9) - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(0), - Q => douta(0), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[10]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(10), - Q => douta(10), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[11]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(11), - Q => douta(11), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[12]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(12), - Q => douta(12), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[13]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(13), - Q => douta(13), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[14]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(14), - Q => douta(14), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[15]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(15), - Q => douta(15), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[16]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(16), - Q => douta(16), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[17]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(17), - Q => douta(17), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(1), - Q => douta(1), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(2), - Q => douta(2), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(3), - Q => douta(3), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(4), - Q => douta(4), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(5), - Q => douta(5), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(6), - Q => douta(6), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(7), - Q => douta(7), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(8), - Q => douta(8), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[9]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => dout_pipe(9), - Q => douta(9), - R => '0' - ); -\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => sel_pipe, - Q => sel_pipe_d1, - R => '0' - ); -\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => '1', - D => addra(0), - Q => sel_pipe, - R => '0' - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \COSLUT_10_16bit_blk_mem_gen_mux__parameterized0\ is - port ( - doutb : out STD_LOGIC_VECTOR ( 17 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 0 to 0 ); - clkb : in STD_LOGIC; - doutb_array : in STD_LOGIC_VECTOR ( 35 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \COSLUT_10_16bit_blk_mem_gen_mux__parameterized0\ : entity is "blk_mem_gen_mux"; -end \COSLUT_10_16bit_blk_mem_gen_mux__parameterized0\; - -architecture STRUCTURE of \COSLUT_10_16bit_blk_mem_gen_mux__parameterized0\ is - signal \no_softecc_gmuxr.ce_pri.dout_i[0]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[10]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[11]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[12]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[13]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[14]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[15]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[16]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[17]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[1]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[2]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[3]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[4]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[5]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[6]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[7]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[8]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_gmuxr.ce_pri.dout_i[9]_i_1_n_0\ : STD_LOGIC; - signal \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\ : STD_LOGIC; - signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\ : STD_LOGIC; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[0]_i_1\ : label is "soft_lutpair9"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[10]_i_1\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[11]_i_1\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[12]_i_1\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[13]_i_1\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[14]_i_1\ : label is "soft_lutpair16"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[15]_i_1\ : label is "soft_lutpair16"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[16]_i_1\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[17]_i_1\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[1]_i_1\ : label is "soft_lutpair9"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[2]_i_1\ : label is "soft_lutpair10"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[3]_i_1\ : label is "soft_lutpair10"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[4]_i_1\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[5]_i_1\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[6]_i_1\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[7]_i_1\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[8]_i_1\ : label is "soft_lutpair13"; - attribute SOFT_HLUTNM of \no_softecc_gmuxr.ce_pri.dout_i[9]_i_1\ : label is "soft_lutpair13"; -begin -\no_softecc_gmuxr.ce_pri.dout_i[0]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(18), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(0), - O => \no_softecc_gmuxr.ce_pri.dout_i[0]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[10]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(28), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(10), - O => \no_softecc_gmuxr.ce_pri.dout_i[10]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[11]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(29), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(11), - O => \no_softecc_gmuxr.ce_pri.dout_i[11]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[12]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(30), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(12), - O => \no_softecc_gmuxr.ce_pri.dout_i[12]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[13]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(31), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(13), - O => \no_softecc_gmuxr.ce_pri.dout_i[13]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[14]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(32), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(14), - O => \no_softecc_gmuxr.ce_pri.dout_i[14]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[15]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(33), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(15), - O => \no_softecc_gmuxr.ce_pri.dout_i[15]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[16]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(34), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(16), - O => \no_softecc_gmuxr.ce_pri.dout_i[16]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[17]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(35), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(17), - O => \no_softecc_gmuxr.ce_pri.dout_i[17]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[1]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(19), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(1), - O => \no_softecc_gmuxr.ce_pri.dout_i[1]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[2]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(20), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(2), - O => \no_softecc_gmuxr.ce_pri.dout_i[2]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[3]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(21), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(3), - O => \no_softecc_gmuxr.ce_pri.dout_i[3]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[4]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(22), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(4), - O => \no_softecc_gmuxr.ce_pri.dout_i[4]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[5]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(23), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(5), - O => \no_softecc_gmuxr.ce_pri.dout_i[5]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[6]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(24), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(6), - O => \no_softecc_gmuxr.ce_pri.dout_i[6]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[7]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(25), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(7), - O => \no_softecc_gmuxr.ce_pri.dout_i[7]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[8]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(26), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(8), - O => \no_softecc_gmuxr.ce_pri.dout_i[8]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i[9]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => doutb_array(27), - I1 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - I2 => doutb_array(9), - O => \no_softecc_gmuxr.ce_pri.dout_i[9]_i_1_n_0\ - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[0]_i_1_n_0\, - Q => doutb(0), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[10]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[10]_i_1_n_0\, - Q => doutb(10), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[11]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[11]_i_1_n_0\, - Q => doutb(11), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[12]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[12]_i_1_n_0\, - Q => doutb(12), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[13]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[13]_i_1_n_0\, - Q => doutb(13), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[14]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[14]_i_1_n_0\, - Q => doutb(14), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[15]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[15]_i_1_n_0\, - Q => doutb(15), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[16]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[16]_i_1_n_0\, - Q => doutb(16), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[17]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[17]_i_1_n_0\, - Q => doutb(17), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[1]_i_1_n_0\, - Q => doutb(1), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[2]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[2]_i_1_n_0\, - Q => doutb(2), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[3]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[3]_i_1_n_0\, - Q => doutb(3), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[4]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[4]_i_1_n_0\, - Q => doutb(4), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[5]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[5]_i_1_n_0\, - Q => doutb(5), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[6]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[6]_i_1_n_0\, - Q => doutb(6), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[7]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[7]_i_1_n_0\, - Q => doutb(7), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[8]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[8]_i_1_n_0\, - Q => doutb(8), - R => '0' - ); -\no_softecc_gmuxr.ce_pri.dout_i_reg[9]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_gmuxr.ce_pri.dout_i[9]_i_1_n_0\, - Q => doutb(9), - R => '0' - ); -\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\, - Q => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\, - R => '0' - ); -\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clkb, - CE => '1', - D => addrb(0), - Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\, - R => '0' - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init is - port ( - douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - doutb_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena_array : in STD_LOGIC_VECTOR ( 0 to 0 ); - enb_array : in STD_LOGIC_VECTOR ( 0 to 0 ); - addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 11 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; -end COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init; - -architecture STRUCTURE of COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init is - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); - attribute box_type : string; - attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; -begin -\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 - generic map( - DOA_REG => 1, - DOB_REG => 1, - EN_ECC_READ => false, - EN_ECC_WRITE => false, - INITP_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INITP_01 => X"FFFFFFFFFFFFE0000000000000000000000000000000003FFFFFFFFFFFFFFFFF", - INITP_02 => X"0000000003FFFFFFFFFFFFFFFFFFE0000000000000000000001FFFFFFFFFFFFF", - INITP_03 => X"00000000000FFFFFFFFFFFFFF800000000000000FFFFFFFFFFFFFFFF80000000", - INITP_04 => X"0003FFFFFFFFFF800000000003FFFFFFFFFFF0000000000007FFFFFFFFFFFE00", - INITP_05 => X"8000000007FFFFFFFF8000000001FFFFFFFFF8000000000FFFFFFFFFF8000000", - INITP_06 => X"0000000FFFFFFFE00000001FFFFFFFE00000001FFFFFFFF800000001FFFFFFFF", - INITP_07 => X"FFFFFFC0000007FFFFFF0000000FFFFFFF80000007FFFFFFC0000000FFFFFFFC", - INITP_08 => X"0FFFFFF000000FFFFFF0000007FFFFFC000001FFFFFF8000001FFFFFF8000001", - INITP_09 => X"FFC00001FFFFF800000FFFFFC00000FFFFFE000003FFFFF800000FFFFFF00000", - INITP_0A => X"FFFF800007FFFF800007FFFF800003FFFFE00001FFFFF000007FFFFE00000FFF", - INITP_0B => X"F80000FFFFC00007FFFE00003FFFF80000FFFFE00001FFFFC00007FFFF800007", - INITP_0C => X"FFF80003FFFE00007FFFC0000FFFF80001FFFF80001FFFF00001FFFF80001FFF", - INITP_0D => X"E0000FFFF0000FFFF00007FFF80007FFFC0001FFFE0000FFFF80003FFFE0000F", - INITP_0E => X"FFC0007FFF0001FFFE0003FFFC0007FFF8000FFFF0000FFFF0000FFFE0001FFF", - INITP_0F => X"0003FFF0001FFF8000FFFE0007FFF0001FFFC000FFFE0003FFF8000FFFE0003F", - INIT_00 => X"FDFDFDFDFDFDFDFEFEFEFEFEFEFEFEFEFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_01 => X"F5F6F6F6F7F7F7F7F8F8F8F8F9F9F9F9FAFAFAFAFBFBFBFBFBFCFCFCFCFCFCFD", - INIT_02 => X"E9EAEAEBEBEBECECEDEDEEEEEEEFEFF0F0F0F1F1F1F2F2F3F3F3F4F4F4F5F5F5", - INIT_03 => X"D8D9D9DADBDBDCDCDDDDDEDFDFE0E0E1E1E2E2E3E3E4E4E5E5E6E6E7E7E8E8E9", - INIT_04 => X"C2C3C4C4C5C6C7C7C8C9C9CACBCCCCCDCECECFD0D0D1D2D2D3D4D4D5D6D6D7D8", - INIT_05 => X"A7A8A9AAABACADADAEAFB0B1B2B3B3B4B5B6B7B8B9B9BABBBCBDBDBEBFC0C1C1", - INIT_06 => X"8788898A8B8C8E8F909192939495969798999A9B9C9D9E9FA0A1A1A2A3A4A5A6", - INIT_07 => X"6264656667686A6B6C6D6E7071727374757778797A7B7C7D7E80818283848586", - INIT_08 => X"393A3B3D3E3F414243454647494A4B4D4E4F515253555657585A5B5C5D5F6061", - INIT_09 => X"0A0B0D0E101113141617191A1C1D1F202223252628292A2C2D2F303233343637", - INIT_0A => X"D6D8DADBDDDFE0E2E4E5E7E8EAECEDEFF1F2F4F5F7F9FAFCFDFF010204050708", - INIT_0B => X"9E9FA1A3A5A7A9AAACAEB0B2B3B5B7B9BBBCBEC0C2C3C5C7C9CACCCECFD1D3D4", - INIT_0C => X"60626466686A6C6E70727476787A7C7E7F81838587898B8D8F91929496989A9C", - INIT_0D => X"1E20222426282B2D2F31333537393B3D40424446484A4C4E50525456585A5C5E", - INIT_0E => X"D6D9DBDDE0E2E4E6E9EBEDEFF2F4F6F8FBFDFF010406080A0C0F11131517191C", - INIT_0F => X"8A8D8F929496999B9EA0A3A5A7AAACAFB1B3B6B8BABDBFC1C4C6C8CBCDCFD2D4", - INIT_10 => X"393C3E414346494B4E505355585B5D606265676A6C6F717476797B7E80838588", - INIT_11 => X"E3E6E8EBEEF1F3F6F9FCFE010407090C0F111417191C1F212427292C2F313436", - INIT_12 => X"888B8E919497999C9FA2A5A8ABAEB0B3B6B9BCBFC1C4C7CACDCFD2D5D8DBDDE0", - INIT_13 => X"282B2E3134373A3E4144474A4D505356595C5F6265686B6E707376797C7F8285", - INIT_14 => X"C3C7CACDD0D3D7DADDE0E3E7EAEDF0F3F6F9FD000306090C0F1216191C1F2225", - INIT_15 => X"5A5D6064676B6E7175787B7F8285898C8F9296999CA0A3A6A9ADB0B3B6BABDC0", - INIT_16 => X"EBEFF2F6F9FD0004070B0E1215191C2023262A2D3134383B3F4245494C505356", - INIT_17 => X"787B7F83868A8E9195999CA0A4A7ABAEB2B6B9BDC0C4C8CBCFD2D6D9DDE1E4E8", - INIT_18 => X"FF03070B0F12161A1E2225292D3135383C4044474B4F53565A5E6265696D7074", - INIT_19 => X"82868A8E92969A9EA2A6AAAEB2B6BABDC1C5C9CDD1D5D9DDE1E4E8ECF0F4F8FC", - INIT_1A => X"0004080C1115191D2125292D31363A3E42464A4E52565A5E62666A6E72767A7E", - INIT_1B => X"797D82868A8F93979BA0A4A8ACB1B5B9BDC1C6CACED2D6DBDFE3E7EBEFF4F8FC", - INIT_1C => X"EDF2F6FBFF04080C11151A1E22272B2F34383D41454A4E52575B5F64686C7175", - INIT_1D => X"5D61666A6F74787D81868A8F93989DA1A6AAAFB3B8BCC1C5CACED3D7DCE0E4E9", - INIT_1E => X"C7CCD1D5DADFE4E8EDF2F6FB0004090E13171C21252A2E33383C41464A4F5358", - INIT_1F => X"2D32373B40454A4F54595E62676C71767B7F84898E93979CA1A6ABAFB4B9BEC2", - INIT_20 => X"8E93989DA2A7ACB1B6BBC0C5CACFD4D9DEE3E8EDF2F7FC01050A0F14191E2328", - INIT_21 => X"EAEFF4F9FE03090E13181D22282D32373C41464C51565B60656A6F74797E8389", - INIT_22 => X"41464B51565B61666B71767B81868B90969BA0A6ABB0B5BBC0C5CACFD5DADFE4", - INIT_23 => X"93989EA3A9AEB4B9BFC4CACFD5DAE0E5EAF0F5FB00060B10161B20262B31363B", - INIT_24 => X"E0E6ECF1F7FD02080E13191E242A2F353A40454B51565C61676C72777D82888D", - INIT_25 => X"292F353B40464C52575D63696E747A80858B91979CA2A8ADB3B9BEC4CACFD5DB", - INIT_26 => X"6D73797F858B91979DA2A8AEB4BAC0C6CCD2D7DDE3E9EFF5FB00060C12181E23", - INIT_27 => X"ACB2B8BEC4CBD1D7DDE3E9EFF5FB01070D13191F252B31373D43494F555B6167", - INIT_28 => X"E6EDF3F9FF060C12181F252B31373D444A50565C63696F757B81878E949AA0A6", - INIT_29 => X"1C22292F353C42494F555C62686F757B82888E959BA1A8AEB4BBC1C7CDD4DAE0", - INIT_2A => X"4D535A60676D747A81878E949BA1A8AEB5BBC2C8CFD5DCE2E9EFF5FC02090F16", - INIT_2B => X"797F868D939AA1A7AEB5BBC2C9CFD6DDE3EAF0F7FE040B12181F252C32394046", - INIT_2C => X"A0A7AEB4BBC2C9D0D7DDE4EBF2F9FF060D141A21282F353C434A50575E656B72", - INIT_2D => X"C2C9D0D7DEE5ECF3FA01080F161D242B323940464D545B626970777E848B9299", - INIT_2E => X"E0E7EEF5FD040B121920272E353D444B525960676E757C838A91989FA6ADB4BB", - INIT_2F => X"F900080F161D252C333B424950575F666D747C838A9198A0A7AEB5BCC3CBD2D9", - INIT_30 => X"0D151C242B323A414950575F666E757C848B939AA1A9B0B7BFC6CDD5DCE3EAF2", - INIT_31 => X"1D242C343B434A5259616970787F878E969DA5ACB4BBC3CAD2D9E1E8F0F7FE06", - INIT_32 => X"282F373F474E565E656D757D848C949BA3ABB2BAC2C9D1D8E0E8EFF7FE060E15", - INIT_33 => X"2E363E464D555D656D757C848C949CA4ABB3BBC3CBD2DAE2EAF1F90109111820", - INIT_34 => X"2F373F474F575F676F777F878F979FA7AFB7BFC7CFD7DFE7EFF7FF060E161E26", - INIT_35 => X"2C343C454D555D656D767E868E969EA6AEB6BFC7CFD7DFE7EFF7FF070F171F27", - INIT_36 => X"242D353D464E565E676F7780889098A1A9B1B9C2CAD2DAE2EBF3FB030B141C24", - INIT_37 => X"182029313A424A535B646C757D858E969FA7AFB8C0C8D1D9E2EAF2FB030B141C", - INIT_38 => X"070F182029323A434B545C656E767F879098A1A9B2BAC3CBD4DCE5EDF6FE070F", - INIT_39 => X"F1F9020B141C252E373F485159626B747C858E969FA8B0B9C2CAD3DBE4EDF5FE", - INIT_3A => X"D6DFE8F1FA030C141D262F38414A525B646D767F879099A2ABB3BCC5CED6DFE8", - INIT_3B => X"B7C0C9D2DBE4EDF6FF08111A232C353E475059626B747D868F98A1AAB3BCC4CD", - INIT_3C => X"949DA6AFB8C1CBD4DDE6EFF8010B141D262F38414A535D666F78818A939CA5AE", - INIT_3D => X"6B757E87919AA3ACB6BFC8D2DBE4EDF70009131C252E37414A535C666F78818A", - INIT_3E => X"3E48515B646E77818A949DA6B0B9C3CCD5DFE8F2FB040E17212A333D464F5962", - INIT_3F => X"0D17202A333D47505A636D77808A939DA6B0B9C3CCD6DFE9F3FC060F19222B35", - INIT_40 => X"D7E1EBF4FE08121B252F38424C565F69737C869099A3ADB6C0CAD3DDE7F0FA03", - INIT_41 => X"9DA6B0BAC4CED8E2ECF5FF09131D27313A444E58626B757F89939CA6B0BAC4CD", - INIT_42 => X"5D67727C86909AA4AEB8C2CCD6E0EAF4FE08111B252F39434D57616B757F8993", - INIT_43 => X"1A242E38434D57616B757F8A949EA8B2BCC6D0DBE5EFF9030D17212B353F4953", - INIT_44 => X"D2DCE6F1FB05101A242E39434D58626C76818B959FAAB4BEC8D2DDE7F1FB0510", - INIT_45 => X"85909AA5AFB9C4CED9E3EEF8020D17222C36414B56606A757F89949EA8B3BDC7", - INIT_46 => X"343F49545E69747E89939EA8B3BEC8D3DDE8F2FD07121C27313C46515B66707B", - INIT_47 => X"DFE9F4FF09141F2A343F4A545F6A747F8A959FAAB5BFCAD4DFEAF4FF0A141F29", - INIT_48 => X"848F9AA5B0BBC6D1DBE6F1FC07121C27323D48525D68737E88939EA9B3BEC9D4", - INIT_49 => X"26313C47525D68737E89949FAAB5C0CBD6E1ECF7020C17222D38434E59646F7A", - INIT_4A => X"C3CED9E5F0FB06111C27323E49545F6A75808B96A1ACB8C3CED9E4EFFA05101B", - INIT_4B => X"5C67727E89949FABB6C1CDD8E3EEFA05101B26323D48535E6A75808B96A2ADB8", - INIT_4C => X"F0FB07121E2935404B57626E7984909BA6B2BDC9D4DFEBF6010D18232F3A4550", - INIT_4D => X"808B97A3AEBAC5D1DCE8F3FF0A16212D38444F5B66727D8994A0ABB7C2CED9E5", - INIT_4E => X"0B17232E3A46525D6975808C98A3AFBBC6D2DDE9F5000C18232F3A46525D6974", - INIT_4F => X"929EAAB6C2CED9E5F1FD0914202C38444F5B67737F8A96A2AEB9C5D1DCE8F400", - INIT_50 => X"15212D3945515D6975818D99A5B1BDC8D4E0ECF804101C28343F4B57636F7B87", - INIT_51 => X"94A0ACB8C4D0DCE8F4010D1925313D4955616D7985919DA9B5C1CDD9E5F1FD09", - INIT_52 => X"0E1A26323F4B5763707C8894A0ADB9C5D1DDEAF6020E1A26333F4B57636F7B88", - INIT_53 => X"83909CA9B5C1CEDAE6F3FF0B1824303D4955626E7A87939FACB8C4D0DDE9F501", - INIT_54 => X"F5020E1B2734404D5965727E8B97A4B0BDC9D6E2EFFB0714202D3946525E6B77", - INIT_55 => X"626F7B8895A1AEBBC7D4E1EDFA0613202C3945525E6B7884919DAAB6C3CFDCE8", - INIT_56 => X"CBD8E5F1FE0B1825313E4B5864717E8A97A4B1BDCAD7E3F0FD0A1623303C4956", - INIT_57 => X"303D4A5763707D8A97A4B1BECBD7E4F1FE0B1825313E4B5865727E8B98A5B2BE", - INIT_58 => X"909DAAB7C4D1DFECF90613202D3A4754616E7B8894A1AEBBC8D5E2EFFC091623", - INIT_59 => X"EDFA0714212E3C495663707D8A98A5B2BFCCD9E6F3000E1B2835424F5C697683", - INIT_5A => X"45525F6C7A8794A2AFBCCAD7E4F1FF0C192634414E5B687683909DABB8C5D2DF", - INIT_5B => X"98A6B3C1CEDCE9F604111F2C394754626F7C8A97A4B2BFCDDAE7F5020F1D2A37", - INIT_5C => X"E8F603111E2C39475562707D8B98A6B3C1CEDCE9F704121F2D3A485563707E8B", - INIT_5D => X"34414F5D6A788693A1AFBCCAD8E5F3010E1C2A374553606E7B8997A4B2BFCDDB", - INIT_5E => X"7B8997A4B2C0CEDCEAF70513212F3C4A586673818F9DAAB8C6D4E1EFFD0A1826", - INIT_5F => X"BECCDAE8F60412202E3C4A586673818F9DABB9C7D5E3F0FE0C1A283644515F6D", - INIT_60 => X"FD0C1A28364452606E7C8A98A6B4C2D0DEECFA08162432404E5C6A788694A2B0", - INIT_61 => X"3947556371808E9CAAB8C6D5E3F1FF0D1B2A38465462707E8D9BA9B7C5D3E1EF", - INIT_62 => X"707E8C9BA9B7C6D4E2F0FF0D1B2A38465563717F8E9CAAB8C7D5E3F1000E1C2A", - INIT_63 => X"A2B1BFCEDCEBF90816253341505E6D7B8A98A6B5C3D1E0EEFD0B192836445361", - INIT_64 => X"D1E0EFFD0C1A293746556372808F9DACBAC9D7E6F50312202F3D4C5A69778694", - INIT_65 => X"FC0B1A283746556372818F9EADBBCAD9E7F6051322313F4E5C6B7A8897A6B4C3", - INIT_66 => X"233241505F6D7C8B9AA9B7C6D5E4F301101F2E3D4B5A69788695A4B3C1D0DFEE", - INIT_67 => X"465564738291A0AFBECDDCEBF90817263544536271808F9DACBBCAD9E8F70514", - INIT_68 => X"65748392A1B0C0CFDEEDFC0B1A2938475665748392A1B0BFCEDDECFB0A192837", - INIT_69 => X"808F9EAEBDCCDBEAFA09182736465564738291A0B0BFCEDDECFB0A1A29384756", - INIT_6A => X"97A6B6C5D4E4F302122130404F5E6E7D8C9BABBAC9D8E8F70615253443526271", - INIT_6B => X"AABAC9D9E8F807162635455464738292A1B1C0CFDFEEFE0D1C2C3B4A5A697888", - INIT_6C => X"BAC9D9E8F807172736465565748493A3B2C2D1E1F0000F1F2E3E4D5D6C7C8B9B", - INIT_6D => X"C5D5E4F404132333425262718191A0B0C0CFDFEFFE0E1E2D3D4C5C6C7B8B9AAA", - INIT_6E => X"CDDCECFC0C1C2B3B4B5B6B7A8A9AAAB9C9D9E9F808182837475767768696A6B5", - INIT_6F => X"D0E0F0001020304050606F7F8F9FAFBFCFDFEFFE0E1E2E3E4E5E6D7D8D9DADBD", - INIT_70 => X"D0E0F000102030405061718191A1B1C1D1E1F101112131415161708090A0B0C0", - INIT_71 => X"CCDCEDFD0D1D2D3D4E5E6E7E8E9EAEBFCFDFEFFF0F1F2F3F4F60708090A0B0C0", - INIT_72 => X"C5D5E5F506162637475767788898A8B9C9D9E9FA0A1A2A3A4B5B6B7B8B9CACBC", - INIT_73 => X"B9CADAEAFB0B1C2C3C4D5D6D7E8E9FAFBFD0E0F001112132425263738394A4B4", - INIT_74 => X"AABACBDCECFD0D1E2E3F4F60708191A2B2C2D3E3F404152536465767778898A9", - INIT_75 => X"97A8B8C9DAEAFB0B1C2D3D4E5F6F8090A1B2C2D3E3F404152636475768788999", - INIT_76 => X"8091A2B3C3D4E5F606172839495A6B7B8C9DAEBECFE0F0011222334454657686", - INIT_77 => X"66778899AABBCBDCEDFE0F2030415263748595A6B7C8D9E9FA0B1C2D3D4E5F70", - INIT_78 => X"48596A7B8C9DAEBFD0E1F2031425364758697A8A9BACBDCEDFF0011223344455", - INIT_79 => X"2738495A6B7C8D9EAFC0D2E3F405162738495A6B7C8D9EAFC0D1E2F304152637", - INIT_7A => X"021324354658697A8B9CAEBFD0E1F20315263748596A7B8D9EAFC0D1E2F30416", - INIT_7B => X"D9EAFB0D1E2F415263758697A8BACBDCEEFF10213344556678899AABBDCEDFF0", - INIT_7C => X"ACBECFE1F204152638495B6C7D8FA0B2C3D4E6F7091A2B3D4E5F718293A5B6C7", - INIT_7D => X"7C8EA0B1C3D4E6F7091A2C3D4F60728395A6B8C9DBECFE0F213244556778899B", - INIT_7E => X"495B6C7E90A1B3C5D6E8F90B1D2E405263758698AABBCDDEF00213253648596B", - INIT_7F => X"12243647596B7D8EA0B2C4D5E7F90B1C2E405163758798AABCCDDFF102142637", - INIT_A => X"000000000", - INIT_B => X"000000000", - INIT_FILE => "NONE", - IS_CLKARDCLK_INVERTED => '0', - IS_CLKBWRCLK_INVERTED => '0', - IS_ENARDEN_INVERTED => '0', - IS_ENBWREN_INVERTED => '0', - IS_RSTRAMARSTRAM_INVERTED => '0', - IS_RSTRAMB_INVERTED => '0', - IS_RSTREGARSTREG_INVERTED => '0', - IS_RSTREGB_INVERTED => '0', - RAM_EXTENSION_A => "NONE", - RAM_EXTENSION_B => "NONE", - RAM_MODE => "TDP", - RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", - READ_WIDTH_A => 9, - READ_WIDTH_B => 9, - RSTREG_PRIORITY_A => "REGCE", - RSTREG_PRIORITY_B => "REGCE", - SIM_COLLISION_CHECK => "ALL", - SIM_DEVICE => "7SERIES", - SRVAL_A => X"000000000", - SRVAL_B => X"000000000", - WRITE_MODE_A => "WRITE_FIRST", - WRITE_MODE_B => "WRITE_FIRST", - WRITE_WIDTH_A => 9, - WRITE_WIDTH_B => 9 - ) - port map ( - ADDRARDADDR(15) => '1', - ADDRARDADDR(14 downto 3) => addra(11 downto 0), - ADDRARDADDR(2 downto 0) => B"111", - ADDRBWRADDR(15) => '1', - ADDRBWRADDR(14 downto 3) => addrb(11 downto 0), - ADDRBWRADDR(2 downto 0) => B"111", - CASCADEINA => '0', - CASCADEINB => '0', - CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, - CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, - CLKARDCLK => clka, - CLKBWRCLK => clkb, - DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, - DIADI(31 downto 0) => B"00000000000000000000000000000000", - DIBDI(31 downto 0) => B"00000000000000000000000000000000", - DIPADIP(3 downto 0) => B"0000", - DIPBDIP(3 downto 0) => B"0000", - DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8), - DOADO(7 downto 0) => douta_array(7 downto 0), - DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8), - DOBDO(7 downto 0) => doutb_array(7 downto 0), - DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1), - DOPADOP(0) => douta_array(8), - DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1), - DOPBDOP(0) => doutb_array(8), - ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), - ENARDEN => ena_array(0), - ENBWREN => enb_array(0), - INJECTDBITERR => '0', - INJECTSBITERR => '0', - RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), - REGCEAREGCE => '1', - REGCEB => '1', - RSTRAMARSTRAM => '0', - RSTRAMB => '0', - RSTREGARSTREG => '0', - RSTREGB => '0', - SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, - WEA(3 downto 0) => B"0000", - WEBWE(7 downto 0) => B"00000000" - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized0\ is - port ( - douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - doutb_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init"; -end \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized0\; - -architecture STRUCTURE of \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized0\ is - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); - attribute box_type : string; - attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; -begin -\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 - generic map( - DOA_REG => 1, - DOB_REG => 1, - EN_ECC_READ => false, - EN_ECC_WRITE => false, - INITP_00 => X"C000FFFC000FFFC001FFF8001FFF8001FFF8000FFFC000FFFC000FFFE0007FFE", - INITP_01 => X"1FFF0007FFC000FFF8003FFF0007FFC000FFF8001FFF0003FFF0007FFE0007FF", - INITP_02 => X"FFF8003FFC001FFF0007FF8003FFE000FFF8003FFE000FFF8003FFE000FFF800", - INITP_03 => X"01FFE001FFF000FFF0007FF8003FFC003FFE001FFF000FFF8003FFC001FFE000", - INITP_04 => X"FF8007FF8007FF8007FF8007FF8007FF8007FF8007FF8003FFC003FFC003FFE0", - INITP_05 => X"FF001FFE003FFC003FF8007FF800FFF000FFE001FFE001FFC003FFC003FFC003", - INITP_06 => X"7FF800FFE003FFC007FF000FFE001FFC007FF800FFF001FFE003FFC007FF800F", - INITP_07 => X"800FFE003FF800FFE003FF8007FF001FFC007FF001FFE003FF800FFE001FFC00", - INITP_08 => X"03FF801FFC007FF001FFC007FF003FF800FFE003FF800FFE003FF800FFE003FF", - INITP_09 => X"0FFE003FF001FFC00FFE003FF001FFC007FE003FF800FFC007FF001FF800FFE0", - INITP_0A => X"01FF800FFC007FE003FF001FF800FFC007FF003FF801FFC007FE003FF001FFC0", - INITP_0B => X"C00FFC007FE003FF003FF801FFC00FFC007FE003FF001FF800FFC007FE003FF0", - INITP_0C => X"FF800FFC00FFE007FE003FF003FF801FF800FFC00FFE007FE003FF003FF801FF", - INITP_0D => X"007FE007FE003FF003FF001FF801FF800FFC00FFE007FE007FF003FF001FF801", - INITP_0E => X"FF800FFC00FFC00FFE007FE007FE003FF003FF001FF801FF801FFC00FFC00FFE", - INITP_0F => X"001FF801FF801FFC00FFC00FFC007FE007FE007FE003FF003FF003FF801FF801", - INIT_00 => X"D8EAFB0D1F31435567788A9CAEC0D2E3F507192B3D4E60728496A7B9CBDDEF00", - INIT_01 => X"9AACBED0E2F406182A3B4D5F718395A7B9CBDDEF01132537485A6C7E90A2B4C6", - INIT_02 => X"586A7D8FA1B3C5D7E9FB0D1F31435567798C9EB0C2D4E6F80A1C2E4052647688", - INIT_03 => X"1426384A5C6F8193A5B7C9DCEE00122436495B6D7F91A3B5C7DAECFE10223446", - INIT_04 => X"CBDEF0021527394B5E708295A7B9CBDEF0021427394B5D708294A6B9CBDDEF01", - INIT_05 => X"8092A5B7C9DCEE011325384A5D6F8194A6B8CBDDEF021426394B5D708294A7B9", - INIT_06 => X"314356687B8DA0B2C5D7EAFC0F213446596B7E90A3B5C8DAECFF112436495B6D", - INIT_07 => X"DFF10416293C4E61748699ABBED0E3F6081B2D405265788A9DAFC2D4E7F90C1E", - INIT_08 => X"899CAEC1D4E7F90C1F3144576A7C8FA2B4C7DAECFF1224374A5C6F8194A7B9CC", - INIT_09 => X"304356697B8EA1B4C7DAECFF1225374A5D708395A8BBCEE0F306192B3E516476", - INIT_0A => X"D4E7FA0D203346586B7E91A4B7CADDF00315283B4E61748799ACBFD2E5F80B1D", - INIT_0B => X"75889BAEC1D4E7FA0D203346596C7F92A5B8CBDEF104172A3C4F6275889BAEC1", - INIT_0C => X"1225384B5F728598ABBED1E4F70A1E3144576A7D90A3B6C9DCEF0215283C4F62", - INIT_0D => X"ACBFD3E6F90C203346596C8093A6B9CCE0F306192C3F5366798C9FB2C5D9ECFF", - INIT_0E => X"43576A7D91A4B7CADEF104182B3E5265788B9FB2C5D8ECFF1226394C5F728699", - INIT_0F => X"D7EAFE1125384C5F728699ADC0D3E7FA0E2134485B6E8295A8BCCFE3F6091D30", - INIT_10 => X"687B8FA2B6C9DDF004172B3E5265798CA0B3C7DAEE0115283C4F6276899DB0C4", - INIT_11 => X"F5091D3044576B7F92A6B9CDE1F4081B2F43566A7D91A4B8CBDFF3061A2D4154", - INIT_12 => X"8094A7BBCFE2F60A1E3145596C8094A7BBCFE2F60A1D3145586C8093A7BBCEE2", - INIT_13 => X"071B2F43576A7E92A6BACDE1F5091C3044586C7F93A7BBCEE2F60A1D3145586C", - INIT_14 => X"8CA0B4C8DBEF03172B3F53677B8EA2B6CADEF206192D4155697D90A4B8CCE0F4", - INIT_15 => X"0D2135495D718599ADC1D5E9FD1125394D6175899DB1C5D9EC0014283C506478", - INIT_16 => X"8CA0B4C8DCF004182C4054697D91A5B9CDE1F5091D3145596D8195A9BDD1E5F9", - INIT_17 => X"071B2F44586C8094A9BDD1E5F90D21364A5E72869AAEC3D7EBFF13273B4F6378", - INIT_18 => X"8094A8BCD1E5F90E22364A5F73879BAFC4D8EC0015293D51667A8EA2B6CBDFF3", - INIT_19 => X"F50A1E32475B6F8498ACC1D5E9FE12263B4F63788CA0B5C9DDF2061A2E43576B", - INIT_1A => X"687C91A5BACEE3F70C2034495D72869BAFC3D8EC0115293E52677B8FA4B8CCE1", - INIT_1B => X"D8EC01152A3E53687C91A5BACEE3F70C2035495E72879BB0C4D9ED02162B3F53", - INIT_1C => X"45596E8397ACC1D5EAFE13283C51657A8FA3B8CCE1F60A1F33485C71869AAFC3", - INIT_1D => X"AFC4D8ED02172B4055697E93A7BCD1E6FA0F24384D62768BA0B4C9DEF2071C30", - INIT_1E => X"162B40556A7E93A8BDD2E6FB1025394E63788DA1B6CBE0F4091E33475C71869A", - INIT_1F => X"7B90A5BACFE3F80D22374C61768A9FB4C9DEF3081C31465B708599AEC3D8ED02", - INIT_20 => X"DDF2071C31465B70859AAFC4D8ED02172C41566B8095AABFD4E9FE12273C5166", - INIT_21 => X"3C51667B90A5BACFE4FA0F24394E63788DA2B7CCE1F60B20354A5F74899EB3C8", - INIT_22 => X"98AEC3D8ED02172C42576C8196ABC0D5EB00152A3F54697E93A8BED3E8FD1227", - INIT_23 => X"F2081D32475C72879CB1C7DCF1061B31465B70859AB0C5DAEF041A2F44596E83", - INIT_24 => X"495F74899FB4C9DFF4091F34495E74899EB3C9DEF3091E33485E73889DB3C8DD", - INIT_25 => X"9EB3C9DEF4091E34495F74899FB4C9DFF4091F34495F748A9FB4CADFF40A1F34", - INIT_26 => X"F0051B30465B71869CB1C7DCF2071C32475D72889DB2C8DDF3081E33485E7389", - INIT_27 => X"3F556A8096ABC1D6EC01172C42576D8298AEC3D9EE04192F445A6F859AB0C5DA", - INIT_28 => X"8CA2B7CDE3F80E24394F647A90A5BBD1E6FC11273C52687D93A8BED4E9FF142A", - INIT_29 => X"D7EC02182D43596F849AB0C5DBF1061C32475D73889EB4C9DFF50A20364B6177", - INIT_2A => X"1E344A60768BA1B7CDE2F80E243A4F657B91A6BCD2E8FD13293F546A8095ABC1", - INIT_2B => X"647A90A5BBD1E7FD13293E546A8096ACC1D7ED03192F445A70869CB1C7DDF309", - INIT_2C => X"A7BDD3E9FF142A40566C8298AEC4DAF0061C31475D73899FB5CBE1F60C22384E", - INIT_2D => X"E7FD13293F556B8197ADC3D9EF051B31475D73899FB5CBE1F70D23394F657B91", - INIT_2E => X"263C52687E94AAC0D6EC02182F455B71879DB3C9DFF50B21374D63798FA5BBD1", - INIT_2F => X"61788EA4BAD0E6FC13293F556B8197AEC4DAF0061C32485F758BA1B7CDE3F90F", - INIT_30 => X"9BB1C7DEF40A20364D63798FA6BCD2E8FE152B41576D849AB0C6DCF3091F354B", - INIT_31 => X"D2E8FF152B42586E849BB1C7DEF40A20374D637A90A6BCD3E9FF152C42586E85", - INIT_32 => X"071D344A61778DA4BAD0E7FD132A40566D839AB0C6DDF30920364C62798FA5BC", - INIT_33 => X"3A50677D93AAC0D7ED041A31475D748AA1B7CDE4FA11273D546A8197ADC4DAF1", - INIT_34 => X"6A8197AEC4DBF1081E354B62788FA5BCD2E9FF162C435970869CB3C9E0F60D23", - INIT_35 => X"98AFC6DCF30920364D647A91A7BED4EB02182F455C72899FB6CCE3FA10273D54", - INIT_36 => X"C5DBF2081F364C637A90A7BED4EB01182F455C7389A0B6CDE4FA11273E556B82", - INIT_37 => X"EE051C334960778DA4BBD2E8FF162C435A70879EB4CBE2F90F263D536A8197AE", - INIT_38 => X"162D445B71889FB6CDE3FA11283E556C8399B0C7DEF40B22394F667D94AAC1D8", - INIT_39 => X"3C536A8197AEC5DCF30A21374E657C93A9C0D7EE051C324960778EA4BBD2E900", - INIT_3A => X"60778EA5BBD2E900172E455C738AA0B7CEE5FC132A41576E859CB3CAE1F80E25", - INIT_3B => X"8198AFC6DDF40B223950677E95ACC3DAF1081F364D647B91A8BFD6ED041B3249", - INIT_3C => X"A1B8CFE6FD142B425970879FB6CDE4FB122940576E859CB3CAE1F80F263D546B", - INIT_3D => X"BFD6ED041B324961788FA6BDD4EB021930475E758DA4BBD2E900172E455C738A", - INIT_3E => X"DBF20920374E667D94ABC2D9F0081F364D647B92AAC1D8EF061D344B627A91A8", - INIT_3F => X"F50C233A51698097AEC5DDF40B223951687F96ADC5DCF30A213850677E95ACC3", - INIT_40 => X"0C243B526A8198AFC7DEF50C243B52698198AFC6DEF50C233B52698098AFC6DD", - INIT_41 => X"233A51698097AFC6DDF50C233A52698098AFC6DEF50C243B52698198AFC7DEF5", - INIT_42 => X"374E667D94ACC3DBF20921384F677E96ADC4DCF30A223950687F97AEC5DDF40B", - INIT_43 => X"49617890A7BFD6ED051C344B637A91A9C0D8EF071E354D647C93AAC2D9F1081F", - INIT_44 => X"5A7189A0B8CFE7FE162D455C748BA3BAD2E9011830475F768EA5BDD4EB031A32", - INIT_45 => X"698098B0C7DFF60E253D546C849BB3CAE2F9112840576F869EB5CDE4FC132B42", - INIT_46 => X"768EA5BDD5EC041B334B627A91A9C1D8F0071F364E667D95ACC4DCF30B223A51", - INIT_47 => X"8299B1C9E0F810273F576E869EB5CDE4FC142B435B728AA2B9D1E800182F475F", - INIT_48 => X"8CA3BBD3EA021A3249617990A8C0D7EF071E364E667D95ADC4DCF40B233B526A", - INIT_49 => X"94ACC3DBF30B223A526A8199B1C9E0F810283F576F879EB6CEE5FD152D445C74", - INIT_4A => X"9AB2CAE2FA112941597188A0B8D0E8FF172F475F768EA6BED6ED051D354C647C", - INIT_4B => X"9FB7CFE7FF172F465E768EA6BED6ED051D354D657C94ACC4DCF40B233B536B83", - INIT_4C => X"A3BBD3EB031A324A627A92AAC2DAF209213951698199B1C9E0F8102840587088", - INIT_4D => X"A5BDD5ED051D354D657C94ACC4DCF40C243C546C849CB4CCE4FB132B435B738B", - INIT_4E => X"A5BDD5ED051D354D657D95ADC5DDF50D253D556D859DB5CDE5FD152D455D758D", - INIT_4F => X"A4BCD5ED051D354D657D95ADC5DDF50D253D556D859DB5CDE5FD152D455D758D", - INIT_50 => X"A2BAD2EA021A334B637B93ABC3DBF30B233B546C849CB4CCE4FC142C445C748C", - INIT_51 => X"9EB6CEE7FF172F475F7790A8C0D8F008203851698199B1C9E1F9112A425A728A", - INIT_52 => X"99B1C9E2FA122A425A738BA3BBD3EB041C344C647C95ADC5DDF50D253E566E86", - INIT_53 => X"92ABC3DBF30C243C546C859DB5CDE5FE162E465F778FA7BFD7F0082038506981", - INIT_54 => X"8BA3BBD3EC041C344D657D95AEC6DEF60F273F577088A0B8D1E90119324A627A", - INIT_55 => X"819AB2CAE3FB132C445C748DA5BDD6EE061E374F678098B0C8E1F9112A425A72", - INIT_56 => X"778FA8C0D8F109213A526A839BB3CCE4FC152D455E768EA7BFD7F00820395169", - INIT_57 => X"6B849CB5CDE5FE162E475F7890A8C1D9F10A223B536B849CB4CDE5FD162E465F", - INIT_58 => X"5F778FA8C0D9F10A223A536B849CB4CDE5FE162E475F7890A8C1D9F20A223B53", - INIT_59 => X"5169829AB2CBE3FC142D455E768EA7BFD8F009213A526A839BB4CCE5FD152E46", - INIT_5A => X"425A728BA3BCD4ED051E364F678098B1C9E2FA132B445C758DA5BED6EF072038", - INIT_5B => X"314A627B93ACC4DDF50E263F577089A1BAD2EB031C344D657E96AFC7E0F81129", - INIT_5C => X"2038516A829BB3CCE4FD152E475F7890A9C1DAF20B233C556D869EB7CFE80019", - INIT_5D => X"0E263F577089A1BAD2EB031C354D667E97AFC8E1F9122A435B748DA5BED6EF07", - INIT_5E => X"FA132B445D758EA6BFD8F009223A536B849DB5CEE6FF183049617A93ABC4DCF5", - INIT_5F => X"E6FE173048617A92ABC4DCF50E263F577089A1BAD3EB041D354E667F98B0C9E2", - INIT_60 => X"D0E9021A334C647D96AFC7E0F9112A435B748DA5BED7EF082139526A839CB4CD", - INIT_61 => X"BAD3EC041D364E678098B1CAE3FB142D455E778FA8C1DAF20B243C556E869FB8", - INIT_62 => X"A3BCD4ED061F375069829AB3CCE4FD162F47607992AAC3DCF40D263F577089A1", - INIT_63 => X"8BA4BCD5EE071F38516A829BB4CDE5FE173048617A93ABC4DDF60E274059718A", - INIT_64 => X"728BA4BCD5EE071F38516A839BB4CDE6FF173049627A93ACC5DDF60F28415972", - INIT_65 => X"58718AA3BBD4ED061F385069829BB4CCE5FE173048617A93ACC4DDF60F284059", - INIT_66 => X"3E576F88A1BAD3EC041D364F688199B2CBE4FD162E47607992AAC3DCF50E273F", - INIT_67 => X"223B546D869FB8D0E9021B344D667E97B0C9E2FB142C455E7790A9C1DAF30C25", - INIT_68 => X"061F38516A839CB5CEE6FF18314A637C95ADC6DFF8112A435C748DA6BFD8F10A", - INIT_69 => X"EA031C344D667F98B1CAE3FC152E465F7891AAC3DCF50E263F58718AA3BCD5EE", - INIT_6A => X"CCE5FE173049627B94ADC6DFF81029425B748DA6BFD8F10A223B546D869FB8D1", - INIT_6B => X"AEC7E0F9122B445D768FA8C1DAF30C253E566F88A1BAD3EC051E375069829BB3", - INIT_6C => X"90A9C2DBF40D263F587189A2BBD4ED061F38516A839CB5CEE70019324B647D95", - INIT_6D => X"718AA3BCD5EE072039526A839CB5CEE70019324B647D96AFC8E1FA132C455E77", - INIT_6E => X"516A839CB5CEE70019324B647D96AFC8E1FA132C455E7790A9C2DBF40D263F58", - INIT_6F => X"314A637C95AEC7E0F9122B445D768FA8C1DAF30C253E577089A2BBD4ED061F38", - INIT_70 => X"1029425B748DA6BFD8F10A233C556E87A0B9D3EC051E375069829BB4CDE6FF18", - INIT_71 => X"EF08213A536C859EB7D0E9021B344D678099B2CBE4FD162F48617A93ACC5DEF7", - INIT_72 => X"CDE6FF18324B647D96AFC8E1FA132C455E7790A9C2DBF40E274059728BA4BDD6", - INIT_73 => X"ABC4DDF71029425B748DA6BFD8F10A233C556F88A1BAD3EC051E375069829BB4", - INIT_74 => X"89A2BBD4ED061F39526B849DB6CFE8011A334C657F98B1CAE3FC152E47607992", - INIT_75 => X"667F99B2CBE4FD162F48617A93ACC6DFF8112A435C758EA7C0D9F30C253E5770", - INIT_76 => X"435C768FA8C1DAF30C253E57718AA3BCD5EE072039526B859EB7D0E9021B344D", - INIT_77 => X"2039526B859EB7D0E9021B344D668099B2CBE4FD162F48617B94ADC6DFF8112A", - INIT_78 => X"FD162F48617A93ACC6DFF8112A435C758EA8C1DAF30C253E577089A3BCD5EE07", - INIT_79 => X"D9F20B243D577089A2BBD4ED061F39526B849DB6CFE8021B344D667F98B1CAE4", - INIT_7A => X"B5CEE7001A334C657E97B0C9E3FC152E47607992ACC5DEF71029425B748EA7C0", - INIT_7B => X"91AAC3DCF60F28415A738CA5BFD8F10A233C556E88A1BAD3EC051E37516A839C", - INIT_7C => X"6D869FB8D1EB041D364F68819AB4CDE6FF18314A637D96AFC8E1FA132D465F78", - INIT_7D => X"49627B94ADC6DFF9122B445D768FA9C2DBF40D263F58728BA4BDD6EF08213B54", - INIT_7E => X"243D577089A2BBD4ED072039526B849DB6D0E9021B344D668099B2CBE4FD1630", - INIT_7F => X"0019324B657E97B0C9E2FB142E47607992ABC4DEF71029425B748EA7C0D9F20B", - INIT_A => X"000000000", - INIT_B => X"000000000", - INIT_FILE => "NONE", - IS_CLKARDCLK_INVERTED => '0', - IS_CLKBWRCLK_INVERTED => '0', - IS_ENARDEN_INVERTED => '0', - IS_ENBWREN_INVERTED => '0', - IS_RSTRAMARSTRAM_INVERTED => '0', - IS_RSTRAMB_INVERTED => '0', - IS_RSTREGARSTREG_INVERTED => '0', - IS_RSTREGB_INVERTED => '0', - RAM_EXTENSION_A => "NONE", - RAM_EXTENSION_B => "NONE", - RAM_MODE => "TDP", - RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", - READ_WIDTH_A => 9, - READ_WIDTH_B => 9, - RSTREG_PRIORITY_A => "REGCE", - RSTREG_PRIORITY_B => "REGCE", - SIM_COLLISION_CHECK => "ALL", - SIM_DEVICE => "7SERIES", - SRVAL_A => X"000000000", - SRVAL_B => X"000000000", - WRITE_MODE_A => "WRITE_FIRST", - WRITE_MODE_B => "WRITE_FIRST", - WRITE_WIDTH_A => 9, - WRITE_WIDTH_B => 9 - ) - port map ( - ADDRARDADDR(15) => '1', - ADDRARDADDR(14 downto 3) => addra(11 downto 0), - ADDRARDADDR(2 downto 0) => B"111", - ADDRBWRADDR(15) => '1', - ADDRBWRADDR(14 downto 3) => addrb(11 downto 0), - ADDRBWRADDR(2 downto 0) => B"111", - CASCADEINA => '0', - CASCADEINB => '0', - CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, - CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, - CLKARDCLK => clka, - CLKBWRCLK => clkb, - DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, - DIADI(31 downto 0) => B"00000000000000000000000000000000", - DIBDI(31 downto 0) => B"00000000000000000000000000000000", - DIPADIP(3 downto 0) => B"0000", - DIPBDIP(3 downto 0) => B"0000", - DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8), - DOADO(7 downto 0) => douta_array(7 downto 0), - DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8), - DOBDO(7 downto 0) => doutb_array(7 downto 0), - DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1), - DOPADOP(0) => douta_array(8), - DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1), - DOPBDOP(0) => doutb_array(8), - ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), - ENARDEN => addra(12), - ENBWREN => addrb(12), - INJECTDBITERR => '0', - INJECTSBITERR => '0', - RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), - REGCEAREGCE => '1', - REGCEB => '1', - RSTRAMARSTRAM => '0', - RSTRAMB => '0', - RSTREGARSTREG => '0', - RSTREGB => '0', - SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, - WEA(3 downto 0) => B"0000", - WEBWE(7 downto 0) => B"00000000" - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized1\ is - port ( - douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - doutb_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - ena_array : out STD_LOGIC_VECTOR ( 0 to 0 ); - enb_array : out STD_LOGIC_VECTOR ( 0 to 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init"; -end \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized1\; - -architecture STRUCTURE of \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized1\ is - signal \^ena_array\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \^enb_array\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); - attribute box_type : string; - attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; -begin - ena_array(0) <= \^ena_array\(0); - enb_array(0) <= \^enb_array\(0); -\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 - generic map( - DOA_REG => 1, - DOB_REG => 1, - EN_ECC_READ => false, - EN_ECC_WRITE => false, - INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_0E => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_0F => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", - INIT_10 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", - INIT_11 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", - INIT_12 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", - INIT_13 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", - INIT_14 => X"FDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFEFEFEFEFEFEFEFEFEFEFEFEFE", - INIT_15 => X"FDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFD", - INIT_16 => X"FDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFD", - INIT_17 => X"FDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFD", - INIT_18 => X"FCFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFD", - INIT_19 => X"FCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFC", - INIT_1A => X"FCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFC", - INIT_1B => X"FCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFC", - INIT_1C => X"FBFBFBFBFBFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFC", - INIT_1D => X"FBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFB", - INIT_1E => X"FBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFB", - INIT_1F => X"FBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFB", - INIT_20 => X"FAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFBFBFBFBFBFBFBFBFB", - INIT_21 => X"FAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFA", - INIT_22 => X"FAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFA", - INIT_23 => X"F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9FAFAFAFAFAFAFAFAFAFAFAFA", - INIT_24 => X"F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9", - INIT_25 => X"F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9", - INIT_26 => X"F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F9F9F9F9F9F9F9", - INIT_27 => X"F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8", - INIT_28 => X"F7F7F7F7F7F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8", - INIT_29 => X"F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7", - INIT_2A => X"F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7", - INIT_2B => X"F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F7F7F7F7F7F7F7F7F7F7F7", - INIT_2C => X"F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6", - INIT_2D => X"F5F5F5F5F5F5F5F5F5F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6", - INIT_2E => X"F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5", - INIT_2F => X"F4F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5", - INIT_30 => X"F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4", - INIT_31 => X"F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4", - INIT_32 => X"F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F4F4F4", - INIT_33 => X"F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3", - INIT_34 => X"F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F3F3F3F3F3", - INIT_35 => X"F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2", - INIT_36 => X"F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F2F2F2F2F2", - INIT_37 => X"F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1", - INIT_38 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F1F1", - INIT_39 => X"EFEFF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0", - INIT_3A => X"EFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEF", - INIT_3B => X"EEEEEEEEEEEEEEEEEEEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEF", - INIT_3C => X"EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE", - INIT_3D => X"EDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE", - INIT_3E => X"EDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDED", - INIT_3F => X"ECECECECECECECECECECECECECECECECECECECECECECECECECECEDEDEDEDEDED", - INIT_40 => X"EBEBEBEBEBECECECECECECECECECECECECECECECECECECECECECECECECECECEC", - INIT_41 => X"EBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEB", - INIT_42 => X"EAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEBEBEBEBEBEBEBEBEBEBEBEBEBEBEB", - INIT_43 => X"EAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEA", - INIT_44 => X"E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EAEA", - INIT_45 => X"E8E8E8E8E8E8E8E8E8E8E8E8E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9", - INIT_46 => X"E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8", - INIT_47 => X"E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E8E8E8E8", - INIT_48 => X"E6E6E6E6E6E6E6E6E6E6E6E6E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7", - INIT_49 => X"E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6", - INIT_4A => X"E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E6E6E6", - INIT_4B => X"E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5", - INIT_4C => X"E3E3E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4", - INIT_4D => X"E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3", - INIT_4E => X"E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E3E3E3E3E3E3E3E3E3E3E3", - INIT_4F => X"E1E1E1E1E1E1E1E1E1E1E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2", - INIT_50 => X"E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1", - INIT_51 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E1", - INIT_52 => X"DFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFE0E0E0E0E0E0E0E0E0E0E0E0", - INIT_53 => X"DEDEDEDEDEDEDEDEDEDEDEDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDF", - INIT_54 => X"DDDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDEDE", - INIT_55 => X"DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD", - INIT_56 => X"DCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDDDDDDDDDDDDDD", - INIT_57 => X"DBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDCDCDCDCDCDCDCDCDCDCDCDCDCDCDC", - INIT_58 => X"DADADADADADADADADADBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDB", - INIT_59 => X"D9D9DADADADADADADADADADADADADADADADADADADADADADADADADADADADADADA", - INIT_5A => X"D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9", - INIT_5B => X"D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D9D9D9D9D9", - INIT_5C => X"D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D8D8D8D8D8D8D8D8D8D8D8", - INIT_5D => X"D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7", - INIT_5E => X"D5D5D5D5D5D5D5D5D5D5D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6", - INIT_5F => X"D4D4D4D4D4D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5", - INIT_60 => X"D3D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4", - INIT_61 => X"D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3", - INIT_62 => X"D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D3D3D3D3", - INIT_63 => X"D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D2D2D2D2D2D2D2", - INIT_64 => X"D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D1D1D1D1D1D1D1D1D1D1D1", - INIT_65 => X"CFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFD0D0D0D0D0D0D0D0D0D0D0D0D0D0", - INIT_66 => X"CECECECECECECECECECECECECECECECFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCFCF", - INIT_67 => X"CDCDCDCDCDCDCDCDCDCDCDCDCDCECECECECECECECECECECECECECECECECECECE", - INIT_68 => X"CCCCCCCCCCCCCCCCCCCCCCCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDCD", - INIT_69 => X"CBCBCBCBCBCBCBCBCBCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC", - INIT_6A => X"CACACACACACACACBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCB", - INIT_6B => X"C9C9C9C9C9C9CACACACACACACACACACACACACACACACACACACACACACACACACACA", - INIT_6C => X"C8C8C8C8C8C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9", - INIT_6D => X"C7C7C7C7C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8", - INIT_6E => X"C6C6C6C6C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7", - INIT_6F => X"C5C5C5C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6", - INIT_70 => X"C4C4C4C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5", - INIT_71 => X"C3C3C3C3C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4", - INIT_72 => X"C2C2C2C2C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3", - INIT_73 => X"C1C1C1C1C1C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2", - INIT_74 => X"C0C0C0C0C0C0C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1", - INIT_75 => X"BFBFBFBFBFBFBFC0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0", - INIT_76 => X"BEBEBEBEBEBEBEBEBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBF", - INIT_77 => X"BDBDBDBDBDBDBDBDBDBDBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBE", - INIT_78 => X"BCBCBCBCBCBCBCBCBCBCBCBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBD", - INIT_79 => X"BBBBBBBBBBBBBBBBBBBBBBBBBBBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBC", - INIT_7A => X"BABABABABABABABABABABABABABABABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB", - INIT_7B => X"B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9BABABABABABABABABABABABABABA", - INIT_7C => X"B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B9B9B9B9B9B9B9B9B9B9B9B9", - INIT_7D => X"B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B8B8B8B8B8B8B8B8B8", - INIT_7E => X"B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B7B7B7B7B7B7B7", - INIT_7F => X"B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B6B6B6B6", - INIT_A => X"000000000", - INIT_B => X"000000000", - INIT_FILE => "NONE", - IS_CLKARDCLK_INVERTED => '0', - IS_CLKBWRCLK_INVERTED => '0', - IS_ENARDEN_INVERTED => '0', - IS_ENBWREN_INVERTED => '0', - IS_RSTRAMARSTRAM_INVERTED => '0', - IS_RSTRAMB_INVERTED => '0', - IS_RSTREGARSTREG_INVERTED => '0', - IS_RSTREGB_INVERTED => '0', - RAM_EXTENSION_A => "NONE", - RAM_EXTENSION_B => "NONE", - RAM_MODE => "TDP", - RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", - READ_WIDTH_A => 9, - READ_WIDTH_B => 9, - RSTREG_PRIORITY_A => "REGCE", - RSTREG_PRIORITY_B => "REGCE", - SIM_COLLISION_CHECK => "ALL", - SIM_DEVICE => "7SERIES", - SRVAL_A => X"000000000", - SRVAL_B => X"000000000", - WRITE_MODE_A => "WRITE_FIRST", - WRITE_MODE_B => "WRITE_FIRST", - WRITE_WIDTH_A => 9, - WRITE_WIDTH_B => 9 - ) - port map ( - ADDRARDADDR(15) => '1', - ADDRARDADDR(14 downto 3) => addra(11 downto 0), - ADDRARDADDR(2 downto 0) => B"111", - ADDRBWRADDR(15) => '1', - ADDRBWRADDR(14 downto 3) => addrb(11 downto 0), - ADDRBWRADDR(2 downto 0) => B"111", - CASCADEINA => '0', - CASCADEINB => '0', - CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, - CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, - CLKARDCLK => clka, - CLKBWRCLK => clkb, - DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, - DIADI(31 downto 0) => B"00000000000000000000000000000000", - DIBDI(31 downto 0) => B"00000000000000000000000000000000", - DIPADIP(3 downto 0) => B"0000", - DIPBDIP(3 downto 0) => B"0000", - DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8), - DOADO(7 downto 0) => douta_array(7 downto 0), - DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8), - DOBDO(7 downto 0) => doutb_array(7 downto 0), - DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1), - DOPADOP(0) => douta_array(8), - DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1), - DOPBDOP(0) => doutb_array(8), - ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), - ENARDEN => \^ena_array\(0), - ENBWREN => \^enb_array\(0), - INJECTDBITERR => '0', - INJECTSBITERR => '0', - RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), - REGCEAREGCE => '1', - REGCEB => '1', - RSTRAMARSTRAM => '0', - RSTRAMB => '0', - RSTREGARSTREG => '0', - RSTREGB => '0', - SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, - WEA(3 downto 0) => B"0000", - WEBWE(7 downto 0) => B"00000000" - ); -\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => addra(12), - O => \^ena_array\(0) - ); -\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => addrb(12), - O => \^enb_array\(0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized2\ is - port ( - douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - doutb_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init"; -end \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized2\; - -architecture STRUCTURE of \COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized2\ is - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); - attribute box_type : string; - attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; -begin -\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 - generic map( - DOA_REG => 1, - DOB_REG => 1, - EN_ECC_READ => false, - EN_ECC_WRITE => false, - INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_00 => X"B3B3B3B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B5", - INIT_01 => X"B2B2B2B2B2B2B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3", - INIT_02 => X"B1B1B1B1B1B1B1B1B1B1B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2", - INIT_03 => X"B0B0B0B0B0B0B0B0B0B0B0B0B0B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1", - INIT_04 => X"AFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFB0B0B0B0B0B0B0B0B0B0B0B0B0B0B0", - INIT_05 => X"AEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAFAFAFAFAFAFAFAFAFAFAF", - INIT_06 => X"ADADADADADADADADADADADADADADADADADADADADADADADADADADAEAEAEAEAEAE", - INIT_07 => X"ABABACACACACACACACACACACACACACACACACACACACACACACACACACACACACADAD", - INIT_08 => X"AAAAAAAAAAAAAAABABABABABABABABABABABABABABABABABABABABABABABABAB", - INIT_09 => X"A9A9A9A9A9A9A9A9A9A9A9A9AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", - INIT_0A => X"A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9", - INIT_0B => X"A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A8A8A8A8A8A8A8A8A8A8A8", - INIT_0C => X"A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A7A7A7A7A7A7", - INIT_0D => X"A4A4A4A4A4A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5", - INIT_0E => X"A3A3A3A3A3A3A3A3A3A3A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4", - INIT_0F => X"A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3", - INIT_10 => X"A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A2A2A2A2A2A2A2A2A2A2A2", - INIT_11 => X"9FA0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A1A1A1A1A1", - INIT_12 => X"9E9E9E9E9E9E9E9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F", - INIT_13 => X"9D9D9D9D9D9D9D9D9D9D9D9D9D9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E", - INIT_14 => X"9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9D9D9D9D9D9D9D9D9D9D9D9D9D", - INIT_15 => X"9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9C9C9C9C9C9C9C", - INIT_16 => X"9999999999999A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A", - INIT_17 => X"9898989898989898989898989899999999999999999999999999999999999999", - INIT_18 => X"9797979797979797979797979797979797979798989898989898989898989898", - INIT_19 => X"9596969696969696969696969696969696969696969696969696979797979797", - INIT_1A => X"9494949494949494959595959595959595959595959595959595959595959595", - INIT_1B => X"9393939393939393939393939393939494949494949494949494949494949494", - INIT_1C => X"9292929292929292929292929292929292929292929293939393939393939393", - INIT_1D => X"9090909091919191919191919191919191919191919191919191919191929292", - INIT_1E => X"8F8F8F8F8F8F8F8F8F8F8F8F9090909090909090909090909090909090909090", - INIT_1F => X"8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8F8F8F8F8F8F8F8F8F8F8F8F8F", - INIT_20 => X"8C8C8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8E8E8E8E8E", - INIT_21 => X"8B8B8B8B8B8B8B8B8B8B8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C", - INIT_22 => X"8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B", - INIT_23 => X"888989898989898989898989898989898989898989898989898A8A8A8A8A8A8A", - INIT_24 => X"8787878787878787878888888888888888888888888888888888888888888888", - INIT_25 => X"8686868686868686868686868686868686878787878787878787878787878787", - INIT_26 => X"8485858585858585858585858585858585858585858585858586868686868686", - INIT_27 => X"8383838383838383838484848484848484848484848484848484848484848484", - INIT_28 => X"8282828282828282828282828282828282828383838383838383838383838383", - INIT_29 => X"8080818181818181818181818181818181818181818181818181828282828282", - INIT_2A => X"7F7F7F7F7F7F7F7F7F7F7F808080808080808080808080808080808080808080", - INIT_2B => X"7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7F7F7F7F7F7F7F7F7F7F7F7F7F", - INIT_2C => X"7C7C7C7C7C7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7E7E7E7E", - INIT_2D => X"7B7B7B7B7B7B7B7B7B7B7B7B7B7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C", - INIT_2E => X"7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7B7B7B7B7B7B7B7B7B7B", - INIT_2F => X"787878787878787879797979797979797979797979797979797979797979797A", - INIT_30 => X"7777777777777777777777777777777777787878787878787878787878787878", - INIT_31 => X"7575757676767676767676767676767676767676767676767676777777777777", - INIT_32 => X"7474747474747474747474747575757575757575757575757575757575757575", - INIT_33 => X"7373737373737373737373737373737373737373737474747474747474747474", - INIT_34 => X"7171717171717172727272727272727272727272727272727272727272727373", - INIT_35 => X"7070707070707070707070707070707071717171717171717171717171717171", - INIT_36 => X"6E6E6E6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F707070707070", - INIT_37 => X"6D6D6D6D6D6D6D6D6D6D6D6D6D6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E", - INIT_38 => X"6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6D6D6D6D6D6D6D6D6D6D", - INIT_39 => X"6A6A6A6A6A6A6A6A6A6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6C", - INIT_3A => X"696969696969696969696969696969696969696A6A6A6A6A6A6A6A6A6A6A6A6A", - INIT_3B => X"6767676767676868686868686868686868686868686868686868686869696969", - INIT_3C => X"6666666666666666666666666666666667676767676767676767676767676767", - INIT_3D => X"6464646565656565656565656565656565656565656565656566666666666666", - INIT_3E => X"6363636363636363636363636364646464646464646464646464646464646464", - INIT_3F => X"6162626262626262626262626262626262626262626262636363636363636363", - INIT_40 => X"6060606060606060606060616161616161616161616161616161616161616161", - INIT_41 => X"5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F6060606060606060606060", - INIT_42 => X"5D5D5D5D5D5D5D5D5D5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5F", - INIT_43 => X"5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5D5D5D5D5D5D5D5D5D5D5D5D5D", - INIT_44 => X"5A5A5A5A5A5A5A5A5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5C5C5C", - INIT_45 => X"5959595959595959595959595959595959595A5A5A5A5A5A5A5A5A5A5A5A5A5A", - INIT_46 => X"5757575757575858585858585858585858585858585858585858585859595959", - INIT_47 => X"5656565656565656565656565656565656575757575757575757575757575757", - INIT_48 => X"5454545454555555555555555555555555555555555555555555555656565656", - INIT_49 => X"5353535353535353535353535353535354545454545454545454545454545454", - INIT_4A => X"5151515151525252525252525252525252525252525252525252535353535353", - INIT_4B => X"5050505050505050505050505050505151515151515151515151515151515151", - INIT_4C => X"4E4E4E4E4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F505050505050", - INIT_4D => X"4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E", - INIT_4E => X"4B4B4B4B4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4D4D4D4D4D4D", - INIT_4F => X"4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B", - INIT_50 => X"48484848494949494949494949494949494949494949494949494A4A4A4A4A4A", - INIT_51 => X"4747474747474747474747474747474848484848484848484848484848484848", - INIT_52 => X"4545454545464646464646464646464646464646464646464646474747474747", - INIT_53 => X"4444444444444444444444444444444445454545454545454545454545454545", - INIT_54 => X"4242424242434343434343434343434343434343434343434343444444444444", - INIT_55 => X"4141414141414141414141414141414142424242424242424242424242424242", - INIT_56 => X"3F3F3F3F3F3F4040404040404040404040404040404040404040404141414141", - INIT_57 => X"3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3E3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F", - INIT_58 => X"3C3C3C3C3C3C3C3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3D3E3E3E3E", - INIT_59 => X"3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3C3C3C3C3C3C3C3C3C3C3C3C3C3C", - INIT_5A => X"39393939393939393A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3B3B3B", - INIT_5B => X"3838383838383838383838383838383838383839393939393939393939393939", - INIT_5C => X"3636363636363636363637373737373737373737373737373737373737373838", - INIT_5D => X"3535353535353535353535353535353535353535353636363636363636363636", - INIT_5E => X"3333333333333333333333343434343434343434343434343434343434343434", - INIT_5F => X"3131323232323232323232323232323232323232323233333333333333333333", - INIT_60 => X"3030303030303030303030303031313131313131313131313131313131313131", - INIT_61 => X"2E2E2E2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F2F3030303030303030", - INIT_62 => X"2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E2E", - INIT_63 => X"2B2B2B2B2B2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2D2D2D2D2D2D", - INIT_64 => X"2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B", - INIT_65 => X"282828282828282929292929292929292929292929292929292929292A2A2A2A", - INIT_66 => X"2727272727272727272727272727272727272728282828282828282828282828", - INIT_67 => X"2525252525252525252626262626262626262626262626262626262626262727", - INIT_68 => X"2424242424242424242424242424242424242424242525252525252525252525", - INIT_69 => X"2222222222222222222222222323232323232323232323232323232323232323", - INIT_6A => X"2020202121212121212121212121212121212121212121222222222222222222", - INIT_6B => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F202020202020202020202020202020202020", - INIT_6C => X"1D1D1D1D1D1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1F1F1F1F1F1F1F", - INIT_6D => X"1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D", - INIT_6E => X"1A1A1A1A1A1A1A1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1C1C1C1C", - INIT_6F => X"191919191919191919191919191919191919191A1A1A1A1A1A1A1A1A1A1A1A1A", - INIT_70 => X"1717171717171717171718181818181818181818181818181818181818181819", - INIT_71 => X"1516161616161616161616161616161616161616161617171717171717171717", - INIT_72 => X"1414141414141414141414141415151515151515151515151515151515151515", - INIT_73 => X"1212121213131313131313131313131313131313131313131414141414141414", - INIT_74 => X"1111111111111111111111111111111212121212121212121212121212121212", - INIT_75 => X"0F0F0F0F0F0F0F10101010101010101010101010101010101010101111111111", - INIT_76 => X"0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0F0F0F0F0F0F0F0F0F0F0F0F0F0F", - INIT_77 => X"0C0C0C0C0C0C0C0C0C0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0E0E", - INIT_78 => X"0A0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0C0C0C0C0C0C0C0C0C0C0C", - INIT_79 => X"0909090909090909090909090A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A", - INIT_7A => X"0707070808080808080808080808080808080808080808080909090909090909", - INIT_7B => X"0606060606060606060606060606060707070707070707070707070707070707", - INIT_7C => X"0404040404040505050505050505050505050505050505050505050606060606", - INIT_7D => X"0303030303030303030303030303030303030404040404040404040404040404", - INIT_7E => X"0101010101010101010202020202020202020202020202020202020202020303", - INIT_7F => X"0000000000000000000000000000000000000000000101010101010101010101", - INIT_A => X"000000000", - INIT_B => X"000000000", - INIT_FILE => "NONE", - IS_CLKARDCLK_INVERTED => '0', - IS_CLKBWRCLK_INVERTED => '0', - IS_ENARDEN_INVERTED => '0', - IS_ENBWREN_INVERTED => '0', - IS_RSTRAMARSTRAM_INVERTED => '0', - IS_RSTRAMB_INVERTED => '0', - IS_RSTREGARSTREG_INVERTED => '0', - IS_RSTREGB_INVERTED => '0', - RAM_EXTENSION_A => "NONE", - RAM_EXTENSION_B => "NONE", - RAM_MODE => "TDP", - RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", - READ_WIDTH_A => 9, - READ_WIDTH_B => 9, - RSTREG_PRIORITY_A => "REGCE", - RSTREG_PRIORITY_B => "REGCE", - SIM_COLLISION_CHECK => "ALL", - SIM_DEVICE => "7SERIES", - SRVAL_A => X"000000000", - SRVAL_B => X"000000000", - WRITE_MODE_A => "WRITE_FIRST", - WRITE_MODE_B => "WRITE_FIRST", - WRITE_WIDTH_A => 9, - WRITE_WIDTH_B => 9 - ) - port map ( - ADDRARDADDR(15) => '1', - ADDRARDADDR(14 downto 3) => addra(11 downto 0), - ADDRARDADDR(2 downto 0) => B"111", - ADDRBWRADDR(15) => '1', - ADDRBWRADDR(14 downto 3) => addrb(11 downto 0), - ADDRBWRADDR(2 downto 0) => B"111", - CASCADEINA => '0', - CASCADEINB => '0', - CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, - CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, - CLKARDCLK => clka, - CLKBWRCLK => clkb, - DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, - DIADI(31 downto 0) => B"00000000000000000000000000000000", - DIBDI(31 downto 0) => B"00000000000000000000000000000000", - DIPADIP(3 downto 0) => B"0000", - DIPBDIP(3 downto 0) => B"0000", - DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8), - DOADO(7 downto 0) => douta_array(7 downto 0), - DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8), - DOBDO(7 downto 0) => doutb_array(7 downto 0), - DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1), - DOPADOP(0) => douta_array(8), - DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1), - DOPBDOP(0) => doutb_array(8), - ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), - ENARDEN => addra(12), - ENBWREN => addrb(12), - INJECTDBITERR => '0', - INJECTSBITERR => '0', - RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), - REGCEAREGCE => '1', - REGCEB => '1', - RSTRAMARSTRAM => '0', - RSTRAMB => '0', - RSTREGARSTREG => '0', - RSTREGB => '0', - SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, - WEA(3 downto 0) => B"0000", - WEBWE(7 downto 0) => B"00000000" - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity COSLUT_10_16bit_blk_mem_gen_prim_width is - port ( - douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - doutb_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - ena_array : in STD_LOGIC_VECTOR ( 0 to 0 ); - enb_array : in STD_LOGIC_VECTOR ( 0 to 0 ); - addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 11 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of COSLUT_10_16bit_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; -end COSLUT_10_16bit_blk_mem_gen_prim_width; - -architecture STRUCTURE of COSLUT_10_16bit_blk_mem_gen_prim_width is -begin -\prim_init.ram\: entity work.COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init - port map ( - addra(11 downto 0) => addra(11 downto 0), - addrb(11 downto 0) => addrb(11 downto 0), - clka => clka, - clkb => clkb, - douta_array(8 downto 0) => douta_array(8 downto 0), - doutb_array(8 downto 0) => doutb_array(8 downto 0), - ena_array(0) => ena_array(0), - enb_array(0) => enb_array(0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized0\ is - port ( - douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - doutb_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width"; -end \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized0\; - -architecture STRUCTURE of \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized0\ is -begin -\prim_init.ram\: entity work.\COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized0\ - port map ( - addra(12 downto 0) => addra(12 downto 0), - addrb(12 downto 0) => addrb(12 downto 0), - clka => clka, - clkb => clkb, - douta_array(8 downto 0) => douta_array(8 downto 0), - doutb_array(8 downto 0) => doutb_array(8 downto 0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized1\ is - port ( - douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - doutb_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - ena_array : out STD_LOGIC_VECTOR ( 0 to 0 ); - enb_array : out STD_LOGIC_VECTOR ( 0 to 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width"; -end \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized1\; - -architecture STRUCTURE of \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized1\ is -begin -\prim_init.ram\: entity work.\COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized1\ - port map ( - addra(12 downto 0) => addra(12 downto 0), - addrb(12 downto 0) => addrb(12 downto 0), - clka => clka, - clkb => clkb, - douta_array(8 downto 0) => douta_array(8 downto 0), - doutb_array(8 downto 0) => doutb_array(8 downto 0), - ena_array(0) => ena_array(0), - enb_array(0) => enb_array(0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized2\ is - port ( - douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - doutb_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width"; -end \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized2\; - -architecture STRUCTURE of \COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized2\ is -begin -\prim_init.ram\: entity work.\COSLUT_10_16bit_blk_mem_gen_prim_wrapper_init__parameterized2\ - port map ( - addra(12 downto 0) => addra(12 downto 0), - addrb(12 downto 0) => addrb(12 downto 0), - clka => clka, - clkb => clkb, - douta_array(8 downto 0) => douta_array(8 downto 0), - doutb_array(8 downto 0) => doutb_array(8 downto 0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity COSLUT_10_16bit_blk_mem_gen_generic_cstr is - port ( - douta : out STD_LOGIC_VECTOR ( 17 downto 0 ); - doutb : out STD_LOGIC_VECTOR ( 17 downto 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of COSLUT_10_16bit_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; -end COSLUT_10_16bit_blk_mem_gen_generic_cstr; - -architecture STRUCTURE of COSLUT_10_16bit_blk_mem_gen_generic_cstr is - signal douta_array : STD_LOGIC_VECTOR ( 35 downto 0 ); - signal doutb_array : STD_LOGIC_VECTOR ( 35 downto 0 ); - signal ena_array : STD_LOGIC_VECTOR ( 0 to 0 ); - signal enb_array : STD_LOGIC_VECTOR ( 0 to 0 ); -begin -\has_mux_a.A\: entity work.COSLUT_10_16bit_blk_mem_gen_mux - port map ( - addra(0) => addra(12), - clka => clka, - douta(17 downto 0) => douta(17 downto 0), - douta_array(35 downto 0) => douta_array(35 downto 0) - ); -\has_mux_b.B\: entity work.\COSLUT_10_16bit_blk_mem_gen_mux__parameterized0\ - port map ( - addrb(0) => addrb(12), - clkb => clkb, - doutb(17 downto 0) => doutb(17 downto 0), - doutb_array(35 downto 0) => doutb_array(35 downto 0) - ); -\ramloop[0].ram.r\: entity work.COSLUT_10_16bit_blk_mem_gen_prim_width - port map ( - addra(11 downto 0) => addra(11 downto 0), - addrb(11 downto 0) => addrb(11 downto 0), - clka => clka, - clkb => clkb, - douta_array(8 downto 0) => douta_array(8 downto 0), - doutb_array(8 downto 0) => doutb_array(8 downto 0), - ena_array(0) => ena_array(0), - enb_array(0) => enb_array(0) - ); -\ramloop[1].ram.r\: entity work.\COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized0\ - port map ( - addra(12 downto 0) => addra(12 downto 0), - addrb(12 downto 0) => addrb(12 downto 0), - clka => clka, - clkb => clkb, - douta_array(8 downto 0) => douta_array(26 downto 18), - doutb_array(8 downto 0) => doutb_array(26 downto 18) - ); -\ramloop[2].ram.r\: entity work.\COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized1\ - port map ( - addra(12 downto 0) => addra(12 downto 0), - addrb(12 downto 0) => addrb(12 downto 0), - clka => clka, - clkb => clkb, - douta_array(8 downto 0) => douta_array(17 downto 9), - doutb_array(8 downto 0) => doutb_array(17 downto 9), - ena_array(0) => ena_array(0), - enb_array(0) => enb_array(0) - ); -\ramloop[3].ram.r\: entity work.\COSLUT_10_16bit_blk_mem_gen_prim_width__parameterized2\ - port map ( - addra(12 downto 0) => addra(12 downto 0), - addrb(12 downto 0) => addrb(12 downto 0), - clka => clka, - clkb => clkb, - douta_array(8 downto 0) => douta_array(35 downto 27), - doutb_array(8 downto 0) => doutb_array(35 downto 27) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity COSLUT_10_16bit_blk_mem_gen_top is - port ( - douta : out STD_LOGIC_VECTOR ( 17 downto 0 ); - doutb : out STD_LOGIC_VECTOR ( 17 downto 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of COSLUT_10_16bit_blk_mem_gen_top : entity is "blk_mem_gen_top"; -end COSLUT_10_16bit_blk_mem_gen_top; - -architecture STRUCTURE of COSLUT_10_16bit_blk_mem_gen_top is -begin -\valid.cstr\: entity work.COSLUT_10_16bit_blk_mem_gen_generic_cstr - port map ( - addra(12 downto 0) => addra(12 downto 0), - addrb(12 downto 0) => addrb(12 downto 0), - clka => clka, - clkb => clkb, - douta(17 downto 0) => douta(17 downto 0), - doutb(17 downto 0) => doutb(17 downto 0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity COSLUT_10_16bit_blk_mem_gen_v8_4_3_synth is - port ( - douta : out STD_LOGIC_VECTOR ( 17 downto 0 ); - doutb : out STD_LOGIC_VECTOR ( 17 downto 0 ); - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of COSLUT_10_16bit_blk_mem_gen_v8_4_3_synth : entity is "blk_mem_gen_v8_4_3_synth"; -end COSLUT_10_16bit_blk_mem_gen_v8_4_3_synth; - -architecture STRUCTURE of COSLUT_10_16bit_blk_mem_gen_v8_4_3_synth is -begin -\gnbram.gnativebmg.native_blk_mem_gen\: entity work.COSLUT_10_16bit_blk_mem_gen_top - port map ( - addra(12 downto 0) => addra(12 downto 0), - addrb(12 downto 0) => addrb(12 downto 0), - clka => clka, - clkb => clkb, - douta(17 downto 0) => douta(17 downto 0), - doutb(17 downto 0) => doutb(17 downto 0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity COSLUT_10_16bit_blk_mem_gen_v8_4_3 is - port ( - clka : in STD_LOGIC; - rsta : in STD_LOGIC; - ena : in STD_LOGIC; - regcea : in STD_LOGIC; - wea : in STD_LOGIC_VECTOR ( 0 to 0 ); - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - dina : in STD_LOGIC_VECTOR ( 17 downto 0 ); - douta : out STD_LOGIC_VECTOR ( 17 downto 0 ); - clkb : in STD_LOGIC; - rstb : in STD_LOGIC; - enb : in STD_LOGIC; - regceb : in STD_LOGIC; - web : in STD_LOGIC_VECTOR ( 0 to 0 ); - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ); - dinb : in STD_LOGIC_VECTOR ( 17 downto 0 ); - doutb : out STD_LOGIC_VECTOR ( 17 downto 0 ); - injectsbiterr : in STD_LOGIC; - injectdbiterr : in STD_LOGIC; - eccpipece : in STD_LOGIC; - sbiterr : out STD_LOGIC; - dbiterr : out STD_LOGIC; - rdaddrecc : out STD_LOGIC_VECTOR ( 12 downto 0 ); - sleep : in STD_LOGIC; - deepsleep : in STD_LOGIC; - shutdown : in STD_LOGIC; - rsta_busy : out STD_LOGIC; - rstb_busy : out STD_LOGIC; - s_aclk : in STD_LOGIC; - s_aresetn : in STD_LOGIC; - s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_awvalid : in STD_LOGIC; - s_axi_awready : out STD_LOGIC; - s_axi_wdata : in STD_LOGIC_VECTOR ( 17 downto 0 ); - s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_wlast : in STD_LOGIC; - s_axi_wvalid : in STD_LOGIC; - s_axi_wready : out STD_LOGIC; - s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_bvalid : out STD_LOGIC; - s_axi_bready : in STD_LOGIC; - s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_arvalid : in STD_LOGIC; - s_axi_arready : out STD_LOGIC; - s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_rdata : out STD_LOGIC_VECTOR ( 17 downto 0 ); - s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_rlast : out STD_LOGIC; - s_axi_rvalid : out STD_LOGIC; - s_axi_rready : in STD_LOGIC; - s_axi_injectsbiterr : in STD_LOGIC; - s_axi_injectdbiterr : in STD_LOGIC; - s_axi_sbiterr : out STD_LOGIC; - s_axi_dbiterr : out STD_LOGIC; - s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 12 downto 0 ) - ); - attribute C_ADDRA_WIDTH : integer; - attribute C_ADDRA_WIDTH of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 13; - attribute C_ADDRB_WIDTH : integer; - attribute C_ADDRB_WIDTH of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 13; - attribute C_ALGORITHM : integer; - attribute C_ALGORITHM of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_AXI_ID_WIDTH : integer; - attribute C_AXI_ID_WIDTH of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 4; - attribute C_AXI_SLAVE_TYPE : integer; - attribute C_AXI_SLAVE_TYPE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_AXI_TYPE : integer; - attribute C_AXI_TYPE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_BYTE_SIZE : integer; - attribute C_BYTE_SIZE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 9; - attribute C_COMMON_CLK : integer; - attribute C_COMMON_CLK of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_COUNT_18K_BRAM : string; - attribute C_COUNT_18K_BRAM of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "0"; - attribute C_COUNT_36K_BRAM : string; - attribute C_COUNT_36K_BRAM of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "4"; - attribute C_CTRL_ECC_ALGO : string; - attribute C_CTRL_ECC_ALGO of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "NONE"; - attribute C_DEFAULT_DATA : string; - attribute C_DEFAULT_DATA of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "0"; - attribute C_DISABLE_WARN_BHV_COLL : integer; - attribute C_DISABLE_WARN_BHV_COLL of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_DISABLE_WARN_BHV_RANGE : integer; - attribute C_DISABLE_WARN_BHV_RANGE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_ELABORATION_DIR : string; - attribute C_ELABORATION_DIR of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "./"; - attribute C_ENABLE_32BIT_ADDRESS : integer; - attribute C_ENABLE_32BIT_ADDRESS of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_DEEPSLEEP_PIN : integer; - attribute C_EN_DEEPSLEEP_PIN of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_ECC_PIPE : integer; - attribute C_EN_ECC_PIPE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_RDADDRA_CHG : integer; - attribute C_EN_RDADDRA_CHG of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_RDADDRB_CHG : integer; - attribute C_EN_RDADDRB_CHG of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_SAFETY_CKT : integer; - attribute C_EN_SAFETY_CKT of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_SHUTDOWN_PIN : integer; - attribute C_EN_SHUTDOWN_PIN of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_SLEEP_PIN : integer; - attribute C_EN_SLEEP_PIN of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EST_POWER_SUMMARY : string; - attribute C_EST_POWER_SUMMARY of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "Estimated Power for IP : 9.414399 mW"; - attribute C_FAMILY : string; - attribute C_FAMILY of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "kintex7"; - attribute C_HAS_AXI_ID : integer; - attribute C_HAS_AXI_ID of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_ENA : integer; - attribute C_HAS_ENA of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_ENB : integer; - attribute C_HAS_ENB of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_INJECTERR : integer; - attribute C_HAS_INJECTERR of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_MEM_OUTPUT_REGS_A : integer; - attribute C_HAS_MEM_OUTPUT_REGS_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_HAS_MEM_OUTPUT_REGS_B : integer; - attribute C_HAS_MEM_OUTPUT_REGS_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_HAS_MUX_OUTPUT_REGS_A : integer; - attribute C_HAS_MUX_OUTPUT_REGS_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_HAS_MUX_OUTPUT_REGS_B : integer; - attribute C_HAS_MUX_OUTPUT_REGS_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_HAS_REGCEA : integer; - attribute C_HAS_REGCEA of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_REGCEB : integer; - attribute C_HAS_REGCEB of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_RSTA : integer; - attribute C_HAS_RSTA of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_RSTB : integer; - attribute C_HAS_RSTB of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; - attribute C_HAS_SOFTECC_INPUT_REGS_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; - attribute C_HAS_SOFTECC_OUTPUT_REGS_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_INITA_VAL : string; - attribute C_INITA_VAL of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "0"; - attribute C_INITB_VAL : string; - attribute C_INITB_VAL of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "0"; - attribute C_INIT_FILE : string; - attribute C_INIT_FILE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "COSLUT_10_16bit.mem"; - attribute C_INIT_FILE_NAME : string; - attribute C_INIT_FILE_NAME of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "COSLUT_10_16bit.mif"; - attribute C_INTERFACE_TYPE : integer; - attribute C_INTERFACE_TYPE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_LOAD_INIT_FILE : integer; - attribute C_LOAD_INIT_FILE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_MEM_TYPE : integer; - attribute C_MEM_TYPE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 4; - attribute C_MUX_PIPELINE_STAGES : integer; - attribute C_MUX_PIPELINE_STAGES of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_PRIM_TYPE : integer; - attribute C_PRIM_TYPE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_READ_DEPTH_A : integer; - attribute C_READ_DEPTH_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 8192; - attribute C_READ_DEPTH_B : integer; - attribute C_READ_DEPTH_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 8192; - attribute C_READ_LATENCY_A : integer; - attribute C_READ_LATENCY_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_READ_LATENCY_B : integer; - attribute C_READ_LATENCY_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_READ_WIDTH_A : integer; - attribute C_READ_WIDTH_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 18; - attribute C_READ_WIDTH_B : integer; - attribute C_READ_WIDTH_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 18; - attribute C_RSTRAM_A : integer; - attribute C_RSTRAM_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_RSTRAM_B : integer; - attribute C_RSTRAM_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_RST_PRIORITY_A : string; - attribute C_RST_PRIORITY_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "CE"; - attribute C_RST_PRIORITY_B : string; - attribute C_RST_PRIORITY_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "CE"; - attribute C_SIM_COLLISION_CHECK : string; - attribute C_SIM_COLLISION_CHECK of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "ALL"; - attribute C_USE_BRAM_BLOCK : integer; - attribute C_USE_BRAM_BLOCK of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_BYTE_WEA : integer; - attribute C_USE_BYTE_WEA of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_BYTE_WEB : integer; - attribute C_USE_BYTE_WEB of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_DEFAULT_DATA : integer; - attribute C_USE_DEFAULT_DATA of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_ECC : integer; - attribute C_USE_ECC of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_SOFTECC : integer; - attribute C_USE_SOFTECC of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_URAM : integer; - attribute C_USE_URAM of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_WEA_WIDTH : integer; - attribute C_WEA_WIDTH of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_WEB_WIDTH : integer; - attribute C_WEB_WIDTH of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_WRITE_DEPTH_A : integer; - attribute C_WRITE_DEPTH_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 8192; - attribute C_WRITE_DEPTH_B : integer; - attribute C_WRITE_DEPTH_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 8192; - attribute C_WRITE_MODE_A : string; - attribute C_WRITE_MODE_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "WRITE_FIRST"; - attribute C_WRITE_MODE_B : string; - attribute C_WRITE_MODE_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "WRITE_FIRST"; - attribute C_WRITE_WIDTH_A : integer; - attribute C_WRITE_WIDTH_A of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 18; - attribute C_WRITE_WIDTH_B : integer; - attribute C_WRITE_WIDTH_B of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is 18; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "kintex7"; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "blk_mem_gen_v8_4_3"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of COSLUT_10_16bit_blk_mem_gen_v8_4_3 : entity is "yes"; -end COSLUT_10_16bit_blk_mem_gen_v8_4_3; - -architecture STRUCTURE of COSLUT_10_16bit_blk_mem_gen_v8_4_3 is - signal \\ : STD_LOGIC; -begin - dbiterr <= \\; - rdaddrecc(12) <= \\; - rdaddrecc(11) <= \\; - rdaddrecc(10) <= \\; - rdaddrecc(9) <= \\; - rdaddrecc(8) <= \\; - rdaddrecc(7) <= \\; - rdaddrecc(6) <= \\; - rdaddrecc(5) <= \\; - rdaddrecc(4) <= \\; - rdaddrecc(3) <= \\; - rdaddrecc(2) <= \\; - rdaddrecc(1) <= \\; - rdaddrecc(0) <= \\; - rsta_busy <= \\; - rstb_busy <= \\; - s_axi_arready <= \\; - s_axi_awready <= \\; - s_axi_bid(3) <= \\; - s_axi_bid(2) <= \\; - s_axi_bid(1) <= \\; - s_axi_bid(0) <= \\; - s_axi_bresp(1) <= \\; - s_axi_bresp(0) <= \\; - s_axi_bvalid <= \\; - s_axi_dbiterr <= \\; - s_axi_rdaddrecc(12) <= \\; - s_axi_rdaddrecc(11) <= \\; - s_axi_rdaddrecc(10) <= \\; - s_axi_rdaddrecc(9) <= \\; - s_axi_rdaddrecc(8) <= \\; - s_axi_rdaddrecc(7) <= \\; - s_axi_rdaddrecc(6) <= \\; - s_axi_rdaddrecc(5) <= \\; - s_axi_rdaddrecc(4) <= \\; - s_axi_rdaddrecc(3) <= \\; - s_axi_rdaddrecc(2) <= \\; - s_axi_rdaddrecc(1) <= \\; - s_axi_rdaddrecc(0) <= \\; - s_axi_rdata(17) <= \\; - s_axi_rdata(16) <= \\; - s_axi_rdata(15) <= \\; - s_axi_rdata(14) <= \\; - s_axi_rdata(13) <= \\; - s_axi_rdata(12) <= \\; - s_axi_rdata(11) <= \\; - s_axi_rdata(10) <= \\; - s_axi_rdata(9) <= \\; - s_axi_rdata(8) <= \\; - s_axi_rdata(7) <= \\; - s_axi_rdata(6) <= \\; - s_axi_rdata(5) <= \\; - s_axi_rdata(4) <= \\; - s_axi_rdata(3) <= \\; - s_axi_rdata(2) <= \\; - s_axi_rdata(1) <= \\; - s_axi_rdata(0) <= \\; - s_axi_rid(3) <= \\; - s_axi_rid(2) <= \\; - s_axi_rid(1) <= \\; - s_axi_rid(0) <= \\; - s_axi_rlast <= \\; - s_axi_rresp(1) <= \\; - s_axi_rresp(0) <= \\; - s_axi_rvalid <= \\; - s_axi_sbiterr <= \\; - s_axi_wready <= \\; - sbiterr <= \\; -GND: unisim.vcomponents.GND - port map ( - G => \\ - ); -inst_blk_mem_gen: entity work.COSLUT_10_16bit_blk_mem_gen_v8_4_3_synth - port map ( - addra(12 downto 0) => addra(12 downto 0), - addrb(12 downto 0) => addrb(12 downto 0), - clka => clka, - clkb => clkb, - douta(17 downto 0) => douta(17 downto 0), - doutb(17 downto 0) => doutb(17 downto 0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity COSLUT_10_16bit is - port ( - clka : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - douta : out STD_LOGIC_VECTOR ( 17 downto 0 ); - clkb : in STD_LOGIC; - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ); - doutb : out STD_LOGIC_VECTOR ( 17 downto 0 ) - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of COSLUT_10_16bit : entity is true; - attribute CHECK_LICENSE_TYPE : string; - attribute CHECK_LICENSE_TYPE of COSLUT_10_16bit : entity is "COSLUT_10_16bit,blk_mem_gen_v8_4_3,{}"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of COSLUT_10_16bit : entity is "yes"; - attribute x_core_info : string; - attribute x_core_info of COSLUT_10_16bit : entity is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; -end COSLUT_10_16bit; - -architecture STRUCTURE of COSLUT_10_16bit is - signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; - signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 ); - signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 ); - signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 ); - signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - attribute C_ADDRA_WIDTH : integer; - attribute C_ADDRA_WIDTH of U0 : label is 13; - attribute C_ADDRB_WIDTH : integer; - attribute C_ADDRB_WIDTH of U0 : label is 13; - attribute C_ALGORITHM : integer; - attribute C_ALGORITHM of U0 : label is 1; - attribute C_AXI_ID_WIDTH : integer; - attribute C_AXI_ID_WIDTH of U0 : label is 4; - attribute C_AXI_SLAVE_TYPE : integer; - attribute C_AXI_SLAVE_TYPE of U0 : label is 0; - attribute C_AXI_TYPE : integer; - attribute C_AXI_TYPE of U0 : label is 1; - attribute C_BYTE_SIZE : integer; - attribute C_BYTE_SIZE of U0 : label is 9; - attribute C_COMMON_CLK : integer; - attribute C_COMMON_CLK of U0 : label is 0; - attribute C_COUNT_18K_BRAM : string; - attribute C_COUNT_18K_BRAM of U0 : label is "0"; - attribute C_COUNT_36K_BRAM : string; - attribute C_COUNT_36K_BRAM of U0 : label is "4"; - attribute C_CTRL_ECC_ALGO : string; - attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; - attribute C_DEFAULT_DATA : string; - attribute C_DEFAULT_DATA of U0 : label is "0"; - attribute C_DISABLE_WARN_BHV_COLL : integer; - attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; - attribute C_DISABLE_WARN_BHV_RANGE : integer; - attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; - attribute C_ELABORATION_DIR : string; - attribute C_ELABORATION_DIR of U0 : label is "./"; - attribute C_ENABLE_32BIT_ADDRESS : integer; - attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; - attribute C_EN_DEEPSLEEP_PIN : integer; - attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; - attribute C_EN_ECC_PIPE : integer; - attribute C_EN_ECC_PIPE of U0 : label is 0; - attribute C_EN_RDADDRA_CHG : integer; - attribute C_EN_RDADDRA_CHG of U0 : label is 0; - attribute C_EN_RDADDRB_CHG : integer; - attribute C_EN_RDADDRB_CHG of U0 : label is 0; - attribute C_EN_SAFETY_CKT : integer; - attribute C_EN_SAFETY_CKT of U0 : label is 0; - attribute C_EN_SHUTDOWN_PIN : integer; - attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; - attribute C_EN_SLEEP_PIN : integer; - attribute C_EN_SLEEP_PIN of U0 : label is 0; - attribute C_EST_POWER_SUMMARY : string; - attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 9.414399 mW"; - attribute C_FAMILY : string; - attribute C_FAMILY of U0 : label is "kintex7"; - attribute C_HAS_AXI_ID : integer; - attribute C_HAS_AXI_ID of U0 : label is 0; - attribute C_HAS_ENA : integer; - attribute C_HAS_ENA of U0 : label is 0; - attribute C_HAS_ENB : integer; - attribute C_HAS_ENB of U0 : label is 0; - attribute C_HAS_INJECTERR : integer; - attribute C_HAS_INJECTERR of U0 : label is 0; - attribute C_HAS_MEM_OUTPUT_REGS_A : integer; - attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1; - attribute C_HAS_MEM_OUTPUT_REGS_B : integer; - attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 1; - attribute C_HAS_MUX_OUTPUT_REGS_A : integer; - attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 1; - attribute C_HAS_MUX_OUTPUT_REGS_B : integer; - attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 1; - attribute C_HAS_REGCEA : integer; - attribute C_HAS_REGCEA of U0 : label is 0; - attribute C_HAS_REGCEB : integer; - attribute C_HAS_REGCEB of U0 : label is 0; - attribute C_HAS_RSTA : integer; - attribute C_HAS_RSTA of U0 : label is 0; - attribute C_HAS_RSTB : integer; - attribute C_HAS_RSTB of U0 : label is 0; - attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; - attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; - attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; - attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; - attribute C_INITA_VAL : string; - attribute C_INITA_VAL of U0 : label is "0"; - attribute C_INITB_VAL : string; - attribute C_INITB_VAL of U0 : label is "0"; - attribute C_INIT_FILE : string; - attribute C_INIT_FILE of U0 : label is "COSLUT_10_16bit.mem"; - attribute C_INIT_FILE_NAME : string; - attribute C_INIT_FILE_NAME of U0 : label is "COSLUT_10_16bit.mif"; - attribute C_INTERFACE_TYPE : integer; - attribute C_INTERFACE_TYPE of U0 : label is 0; - attribute C_LOAD_INIT_FILE : integer; - attribute C_LOAD_INIT_FILE of U0 : label is 1; - attribute C_MEM_TYPE : integer; - attribute C_MEM_TYPE of U0 : label is 4; - attribute C_MUX_PIPELINE_STAGES : integer; - attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; - attribute C_PRIM_TYPE : integer; - attribute C_PRIM_TYPE of U0 : label is 1; - attribute C_READ_DEPTH_A : integer; - attribute C_READ_DEPTH_A of U0 : label is 8192; - attribute C_READ_DEPTH_B : integer; - attribute C_READ_DEPTH_B of U0 : label is 8192; - attribute C_READ_LATENCY_A : integer; - attribute C_READ_LATENCY_A of U0 : label is 1; - attribute C_READ_LATENCY_B : integer; - attribute C_READ_LATENCY_B of U0 : label is 1; - attribute C_READ_WIDTH_A : integer; - attribute C_READ_WIDTH_A of U0 : label is 18; - attribute C_READ_WIDTH_B : integer; - attribute C_READ_WIDTH_B of U0 : label is 18; - attribute C_RSTRAM_A : integer; - attribute C_RSTRAM_A of U0 : label is 0; - attribute C_RSTRAM_B : integer; - attribute C_RSTRAM_B of U0 : label is 0; - attribute C_RST_PRIORITY_A : string; - attribute C_RST_PRIORITY_A of U0 : label is "CE"; - attribute C_RST_PRIORITY_B : string; - attribute C_RST_PRIORITY_B of U0 : label is "CE"; - attribute C_SIM_COLLISION_CHECK : string; - attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; - attribute C_USE_BRAM_BLOCK : integer; - attribute C_USE_BRAM_BLOCK of U0 : label is 0; - attribute C_USE_BYTE_WEA : integer; - attribute C_USE_BYTE_WEA of U0 : label is 0; - attribute C_USE_BYTE_WEB : integer; - attribute C_USE_BYTE_WEB of U0 : label is 0; - attribute C_USE_DEFAULT_DATA : integer; - attribute C_USE_DEFAULT_DATA of U0 : label is 0; - attribute C_USE_ECC : integer; - attribute C_USE_ECC of U0 : label is 0; - attribute C_USE_SOFTECC : integer; - attribute C_USE_SOFTECC of U0 : label is 0; - attribute C_USE_URAM : integer; - attribute C_USE_URAM of U0 : label is 0; - attribute C_WEA_WIDTH : integer; - attribute C_WEA_WIDTH of U0 : label is 1; - attribute C_WEB_WIDTH : integer; - attribute C_WEB_WIDTH of U0 : label is 1; - attribute C_WRITE_DEPTH_A : integer; - attribute C_WRITE_DEPTH_A of U0 : label is 8192; - attribute C_WRITE_DEPTH_B : integer; - attribute C_WRITE_DEPTH_B of U0 : label is 8192; - attribute C_WRITE_MODE_A : string; - attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST"; - attribute C_WRITE_MODE_B : string; - attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; - attribute C_WRITE_WIDTH_A : integer; - attribute C_WRITE_WIDTH_A of U0 : label is 18; - attribute C_WRITE_WIDTH_B : integer; - attribute C_WRITE_WIDTH_B of U0 : label is 18; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of U0 : label is "kintex7"; - attribute downgradeipidentifiedwarnings of U0 : label is "yes"; - attribute x_interface_info : string; - attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; - attribute x_interface_parameter : string; - attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1"; - attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK"; - attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1"; - attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; - attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR"; - attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; - attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT"; -begin -U0: entity work.COSLUT_10_16bit_blk_mem_gen_v8_4_3 - port map ( - addra(12 downto 0) => addra(12 downto 0), - addrb(12 downto 0) => addrb(12 downto 0), - clka => clka, - clkb => clkb, - dbiterr => NLW_U0_dbiterr_UNCONNECTED, - deepsleep => '0', - dina(17 downto 0) => B"000000000000000000", - dinb(17 downto 0) => B"000000000000000000", - douta(17 downto 0) => douta(17 downto 0), - doutb(17 downto 0) => doutb(17 downto 0), - eccpipece => '0', - ena => '0', - enb => '0', - injectdbiterr => '0', - injectsbiterr => '0', - rdaddrecc(12 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(12 downto 0), - regcea => '0', - regceb => '0', - rsta => '0', - rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, - rstb => '0', - rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, - s_aclk => '0', - s_aresetn => '0', - s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", - s_axi_arburst(1 downto 0) => B"00", - s_axi_arid(3 downto 0) => B"0000", - s_axi_arlen(7 downto 0) => B"00000000", - s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, - s_axi_arsize(2 downto 0) => B"000", - s_axi_arvalid => '0', - s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", - s_axi_awburst(1 downto 0) => B"00", - s_axi_awid(3 downto 0) => B"0000", - s_axi_awlen(7 downto 0) => B"00000000", - s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, - s_axi_awsize(2 downto 0) => B"000", - s_axi_awvalid => '0', - s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), - s_axi_bready => '0', - s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), - s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, - s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, - s_axi_injectdbiterr => '0', - s_axi_injectsbiterr => '0', - s_axi_rdaddrecc(12 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(12 downto 0), - s_axi_rdata(17 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(17 downto 0), - s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), - s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, - s_axi_rready => '0', - s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), - s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, - s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, - s_axi_wdata(17 downto 0) => B"000000000000000000", - s_axi_wlast => '0', - s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, - s_axi_wstrb(0) => '0', - s_axi_wvalid => '0', - sbiterr => NLW_U0_sbiterr_UNCONNECTED, - shutdown => '0', - sleep => '0', - wea(0) => '0', - web(0) => '0' - ); -end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.v deleted file mode 100644 index c3abbc51..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.v +++ /dev/null @@ -1,25 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:34:22 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.v -// Design : COSLUT_10_16bit -// Purpose : Stub declaration of top-level module interface -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) -module COSLUT_10_16bit(clka, addra, douta, clkb, addrb, doutb) -/* synthesis syn_black_box black_box_pad_pin="clka,addra[12:0],douta[17:0],clkb,addrb[12:0],doutb[17:0]" */; - input clka; - input [12:0]addra; - output [17:0]douta; - input clkb; - input [12:0]addrb; - output [17:0]doutb; -endmodule diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.vhdl deleted file mode 100644 index 6c6002c4..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.vhdl +++ /dev/null @@ -1,35 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:34:22 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.vhdl --- Design : COSLUT_10_16bit --- Purpose : Stub declaration of top-level module interface --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity COSLUT_10_16bit is - Port ( - clka : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); - douta : out STD_LOGIC_VECTOR ( 17 downto 0 ); - clkb : in STD_LOGIC; - addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ); - doutb : out STD_LOGIC_VECTOR ( 17 downto 0 ) - ); - -end COSLUT_10_16bit; - -architecture stub of COSLUT_10_16bit is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clka,addra[12:0],douta[17:0],clkb,addrb[12:0],doutb[17:0]"; -attribute x_core_info : string; -attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; -begin -end; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_utilization_synth.pb b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_utilization_synth.pb deleted file mode 100644 index 531fe3da..00000000 Binary files a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_utilization_synth.pb and /dev/null differ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_utilization_synth.rpt b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_utilization_synth.rpt deleted file mode 100644 index b120c1f4..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_utilization_synth.rpt +++ /dev/null @@ -1,177 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -| Date : Sat Mar 18 23:34:22 2023 -| Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -| Command : report_utilization -file COSLUT_10_16bit_utilization_synth.rpt -pb COSLUT_10_16bit_utilization_synth.pb -| Design : COSLUT_10_16bit -| Device : 7k410tffg900-2 -| Design State : Synthesized -------------------------------------------------------------------------------------------------------------------------- - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 20 | 0 | 254200 | <0.01 | -| LUT as Logic | 20 | 0 | 254200 | <0.01 | -| LUT as Memory | 0 | 0 | 90600 | 0.00 | -| Slice Registers | 40 | 0 | 508400 | <0.01 | -| Register as Flip Flop | 40 | 0 | 508400 | <0.01 | -| Register as Latch | 0 | 0 | 508400 | 0.00 | -| F7 Muxes | 0 | 0 | 127100 | 0.00 | -| F8 Muxes | 0 | 0 | 63550 | 0.00 | -+-------------------------+------+-------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 40 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Memory ---------- - -+-------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------+------+-------+-----------+-------+ -| Block RAM Tile | 4 | 0 | 795 | 0.50 | -| RAMB36/FIFO* | 4 | 0 | 795 | 0.50 | -| RAMB36E1 only | 4 | | | | -| RAMB18 | 0 | 0 | 1590 | 0.00 | -+-------------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -3. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 1540 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -4. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 0 | 0 | 500 | 0.00 | -| Bonded IPADs | 0 | 0 | 50 | 0.00 | -| Bonded OPADs | 0 | 0 | 32 | 0.00 | -| PHY_CONTROL | 0 | 0 | 10 | 0.00 | -| PHASER_REF | 0 | 0 | 10 | 0.00 | -| OUT_FIFO | 0 | 0 | 40 | 0.00 | -| IN_FIFO | 0 | 0 | 40 | 0.00 | -| IDELAYCTRL | 0 | 0 | 10 | 0.00 | -| IBUFDS | 0 | 0 | 480 | 0.00 | -| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | -| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 | -| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | -| ILOGIC | 0 | 0 | 500 | 0.00 | -| OLOGIC | 0 | 0 | 500 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -5. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 0 | 0 | 32 | 0.00 | -| BUFIO | 0 | 0 | 40 | 0.00 | -| MMCME2_ADV | 0 | 0 | 10 | 0.00 | -| PLLE2_ADV | 0 | 0 | 10 | 0.00 | -| BUFMRCE | 0 | 0 | 20 | 0.00 | -| BUFHCE | 0 | 0 | 168 | 0.00 | -| BUFR | 0 | 0 | 40 | 0.00 | -+------------+------+-------+-----------+-------+ - - -6. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -7. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| FDRE | 40 | Flop & Latch | -| LUT3 | 36 | LUT | -| RAMB36E1 | 4 | Block Memory | -| LUT1 | 2 | LUT | -+----------+------+---------------------+ - - -8. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -9. Instantiated Netlists ------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/ISEWrap.js b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/ISEWrap.js deleted file mode 100644 index 97a2ecbc..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/ISEWrap.js +++ /dev/null @@ -1,270 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/ISEWrap.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/ISEWrap.sh deleted file mode 100644 index f679f2e8..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/__synthesis_is_complete__ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/dont_touch.xdc b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/dont_touch.xdc deleted file mode 100644 index a6aa04d2..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/dont_touch.xdc +++ /dev/null @@ -1,16 +0,0 @@ -# This file is automatically generated. -# It contains project source information necessary for synthesis and implementation. - -# IP: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit.xci -# IP: The module: 'COSLUT_10_16bit' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'COSLUT_10_16bit'. Do not add the DONT_TOUCH constraint. -set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet - -# IP: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit.xci -# IP: The module: 'COSLUT_10_16bit' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'COSLUT_10_16bit'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/gen_run.xml deleted file mode 100644 index fffbc896..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/gen_run.xml +++ /dev/null @@ -1,59 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/htr.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/htr.txt deleted file mode 100644 index 01e86dc5..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log COSLUT_10_16bit.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source COSLUT_10_16bit.tcl diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/project.wdf b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/project.wdf deleted file mode 100644 index 9507bcd5..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/project.wdf +++ /dev/null @@ -1,59 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:38:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3238:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3661346264366134396337643466636438383330333461376438356536303661:506172656e742050412070726f6a656374204944:00 -eof:3863841633 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/rundef.js b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/rundef.js deleted file mode 100644 index 4a846d4f..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/rundef.js +++ /dev/null @@ -1,36 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log COSLUT_10_16bit.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source COSLUT_10_16bit.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/runme.bat b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/runme.bat deleted file mode 100644 index 1760626b..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/runme.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/runme.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/runme.sh deleted file mode 100644 index 63449383..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/runme.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin -else - PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log COSLUT_10_16bit.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source COSLUT_10_16bit.tcl diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/vivado.pb b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/vivado.pb deleted file mode 100644 index e98395ea..00000000 Binary files a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/vivado.pb and /dev/null differ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/.Vivado_Synthesis.queue.rst b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/.Vivado_Synthesis.queue.rst deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/.vivado.begin.rst b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/.vivado.begin.rst deleted file mode 100644 index 5632771a..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/.vivado.end.rst b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/.vivado.end.rst deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m.dcp b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m.dcp deleted file mode 100644 index 81d170a6..00000000 Binary files a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m.dcp and /dev/null differ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m.tcl b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m.tcl deleted file mode 100644 index 6eee1758..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m.tcl +++ /dev/null @@ -1,157 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param general.maxThreads 20 -set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64 -set_param project.vivado.isBlockSynthRun true -set_msg_config -msgmgr_mode ooc_run -create_project -in_memory -part xc7k410tffg900-2 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] -set_property parent.project_path D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.xpr [current_project] -set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language Verilog [current_project] -set_property ip_output_repo d:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/GaussFir_12m.xci -set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/constraints/fir_compiler_v7_2.xdc] -set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/GaussFir_12m_ooc.xdc] - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -read_xdc dont_touch.xdc -set_property used_in_implementation false [get_files dont_touch.xdc] -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1 -new_name GaussFir_12m -ip [get_ips GaussFir_12m]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top GaussFir_12m -part xc7k410tffg900-2 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix GaussFir_12m_ GaussFir_12m.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ GaussFir_12m_stub.v - lappend ipCachedFiles GaussFir_12m_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ GaussFir_12m_stub.vhdl - lappend ipCachedFiles GaussFir_12m_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ GaussFir_12m_sim_netlist.v - lappend ipCachedFiles GaussFir_12m_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ GaussFir_12m_sim_netlist.vhdl - lappend ipCachedFiles GaussFir_12m_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp GaussFir_12m.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips GaussFir_12m] -} - -rename_ref -prefix_all GaussFir_12m_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef GaussFir_12m.dcp -create_report "GaussFir_12m_synth_1_synth_report_utilization_0" "report_utilization -file GaussFir_12m_utilization_synth.rpt -pb GaussFir_12m_utilization_synth.pb" - -if { [catch { - write_verilog -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -}; # end if cached_ip - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/GaussFir_12m.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/GaussFir_12m.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_sim_netlist.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/GaussFir_12m.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/GaussFir_12m.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m.dcp -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/GaussFir_12m.xci] - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/GaussFir_12m]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_sim_netlist.v D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/GaussFir_12m - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/GaussFir_12m]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_sim_netlist.vhdl D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/GaussFir_12m - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/GaussFir_12m]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.v D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/GaussFir_12m - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/GaussFir_12m]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.vhdl D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/GaussFir_12m - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m.vds b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m.vds deleted file mode 100644 index 732d52a9..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m.vds +++ /dev/null @@ -1,468 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Sat Mar 18 23:32:57 2023 -# Process ID: 29360 -# Current directory: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1 -# Command line: vivado.exe -log GaussFir_12m.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source GaussFir_12m.tcl -# Log file: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m.vds -# Journal file: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1\vivado.jou -#----------------------------------------------------------- -Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl' -source GaussFir_12m.tcl -notrace -Command: synth_design -top GaussFir_12m -part xc7k410tffg900-2 -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' -INFO: [Device 21-403] Loading part xc7k410tffg900-2 -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 33600 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 884.863 ; gain = 176.656 ---------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'GaussFir_12m' [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/synth/GaussFir_12m.vhd:70] - Parameter C_XDEVICEFAMILY bound to: kintex7 - type: string - Parameter C_ELABORATION_DIR bound to: ./ - type: string - Parameter C_COMPONENT_NAME bound to: GaussFir_12m - type: string - Parameter C_COEF_FILE bound to: GaussFir_12m.mif - type: string - Parameter C_COEF_FILE_LINES bound to: 20 - type: integer - Parameter C_FILTER_TYPE bound to: 2 - type: integer - Parameter C_INTERP_RATE bound to: 4 - type: integer - Parameter C_DECIM_RATE bound to: 1 - type: integer - Parameter C_ZERO_PACKING_FACTOR bound to: 1 - type: integer - Parameter C_SYMMETRY bound to: 0 - type: integer - Parameter C_NUM_FILTS bound to: 1 - type: integer - Parameter C_NUM_TAPS bound to: 17 - type: integer - Parameter C_NUM_CHANNELS bound to: 1 - type: integer - Parameter C_CHANNEL_PATTERN bound to: fixed - type: string - Parameter C_ROUND_MODE bound to: 0 - type: integer - Parameter C_COEF_RELOAD bound to: 0 - type: integer - Parameter C_NUM_RELOAD_SLOTS bound to: 1 - type: integer - Parameter C_COL_MODE bound to: 1 - type: integer - Parameter C_COL_PIPE_LEN bound to: 4 - type: integer - Parameter C_COL_CONFIG bound to: 5 - type: string - Parameter C_OPTIMIZATION bound to: 0 - type: integer - Parameter C_DATA_PATH_WIDTHS bound to: 2 - type: string - Parameter C_DATA_IP_PATH_WIDTHS bound to: 2 - type: string - Parameter C_DATA_PX_PATH_WIDTHS bound to: 2 - type: string - Parameter C_DATA_WIDTH bound to: 2 - type: integer - Parameter C_COEF_PATH_WIDTHS bound to: 14 - type: string - Parameter C_COEF_WIDTH bound to: 14 - type: integer - Parameter C_DATA_PATH_SRC bound to: 0 - type: string - Parameter C_COEF_PATH_SRC bound to: 0 - type: string - Parameter C_PX_PATH_SRC bound to: 0 - type: string - Parameter C_DATA_PATH_SIGN bound to: 0 - type: string - Parameter C_COEF_PATH_SIGN bound to: 1 - type: string - Parameter C_ACCUM_PATH_WIDTHS bound to: 15 - type: string - Parameter C_OUTPUT_WIDTH bound to: 15 - type: integer - Parameter C_OUTPUT_PATH_WIDTHS bound to: 15 - type: string - Parameter C_ACCUM_OP_PATH_WIDTHS bound to: 15 - type: string - Parameter C_EXT_MULT_CNFG bound to: none - type: string - Parameter C_DATA_PATH_PSAMP_SRC bound to: 0 - type: string - Parameter C_OP_PATH_PSAMP_SRC bound to: 0 - type: string - Parameter C_NUM_MADDS bound to: 5 - type: integer - Parameter C_OPT_MADDS bound to: none - type: string - Parameter C_OVERSAMPLING_RATE bound to: 1 - type: integer - Parameter C_INPUT_RATE bound to: 4 - type: integer - Parameter C_OUTPUT_RATE bound to: 1 - type: integer - Parameter C_DATA_MEMTYPE bound to: 0 - type: integer - Parameter C_COEF_MEMTYPE bound to: 2 - type: integer - Parameter C_IPBUFF_MEMTYPE bound to: 0 - type: integer - Parameter C_OPBUFF_MEMTYPE bound to: 0 - type: integer - Parameter C_DATAPATH_MEMTYPE bound to: 0 - type: integer - Parameter C_MEM_ARRANGEMENT bound to: 2 - type: integer - Parameter C_DATA_MEM_PACKING bound to: 0 - type: integer - Parameter C_COEF_MEM_PACKING bound to: 0 - type: integer - Parameter C_FILTS_PACKED bound to: 0 - type: integer - Parameter C_LATENCY bound to: 11 - type: integer - Parameter C_HAS_ARESETn bound to: 0 - type: integer - Parameter C_HAS_ACLKEN bound to: 0 - type: integer - Parameter C_DATA_HAS_TLAST bound to: 0 - type: integer - Parameter C_S_DATA_HAS_FIFO bound to: 0 - type: integer - Parameter C_S_DATA_HAS_TUSER bound to: 0 - type: integer - Parameter C_S_DATA_TDATA_WIDTH bound to: 8 - type: integer - Parameter C_S_DATA_TUSER_WIDTH bound to: 1 - type: integer - Parameter C_M_DATA_HAS_TREADY bound to: 0 - type: integer - Parameter C_M_DATA_HAS_TUSER bound to: 0 - type: integer - Parameter C_M_DATA_TDATA_WIDTH bound to: 16 - type: integer - Parameter C_M_DATA_TUSER_WIDTH bound to: 1 - type: integer - Parameter C_HAS_CONFIG_CHANNEL bound to: 0 - type: integer - Parameter C_CONFIG_SYNC_MODE bound to: 0 - type: integer - Parameter C_CONFIG_PACKET_SIZE bound to: 0 - type: integer - Parameter C_CONFIG_TDATA_WIDTH bound to: 1 - type: integer - Parameter C_RELOAD_TDATA_WIDTH bound to: 1 - type: integer -INFO: [Synth 8-3491] module 'fir_compiler_v7_2_12' declared at 'd:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/hdl/fir_compiler_v7_2_vh_rfs.vhd:61264' bound to instance 'U0' of component 'fir_compiler_v7_2_12' [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/synth/GaussFir_12m.vhd:198] -WARNING: [Synth 8-5858] RAM p_casc_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers -WARNING: [Synth 8-5858] RAM p_path_out_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers -INFO: [Synth 8-256] done synthesizing module 'GaussFir_12m' (11#1) [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/synth/GaussFir_12m.vhd:70] -WARNING: [Synth 8-3331] design delay__parameterized3 has unconnected port SCLR -WARNING: [Synth 8-3331] design delay__parameterized3 has unconnected port SCLR_ALT -WARNING: [Synth 8-3331] design buff has unconnected port RE -WARNING: [Synth 8-3331] design buff has unconnected port SCLR -WARNING: [Synth 8-3331] design delay__parameterized6 has unconnected port WE -WARNING: [Synth 8-3331] design delay__parameterized6 has unconnected port CE -WARNING: [Synth 8-3331] design delay__parameterized6 has unconnected port SCLR -WARNING: [Synth 8-3331] design delay__parameterized6 has unconnected port SCLR_ALT -WARNING: [Synth 8-3331] design delay__parameterized6 has unconnected port CLK -WARNING: [Synth 8-3331] design delay__parameterized5 has unconnected port WE -WARNING: [Synth 8-3331] design delay__parameterized5 has unconnected port CE -WARNING: [Synth 8-3331] design delay__parameterized5 has unconnected port SCLR -WARNING: [Synth 8-3331] design delay__parameterized5 has unconnected port SCLR_ALT -WARNING: [Synth 8-3331] design delay__parameterized5 has unconnected port CLK -WARNING: [Synth 8-3331] design calc has unconnected port PRE_ADDSUB -WARNING: [Synth 8-3331] design calc has unconnected port PRE_ADD_BYPASS -WARNING: [Synth 8-3331] design calc has unconnected port CED -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[fab][57] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[fab][56] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[fab][55] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[fab][54] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[fab][53] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[fab][52] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[fab][51] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[fab][50] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[fab][49] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[fab][48] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][62] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][61] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][60] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][59] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][58] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][57] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][56] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][55] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][54] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][53] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][52] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][51] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][50] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][49] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][48] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port P_EN -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port OPCODE[9] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port OPCODE[8] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port OPCODE[7] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port OPCODE[6] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port OPCODE[5] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port OPCODE[4] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port OPCODE[3] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port OPCODE[2] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port OPCODE[1] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port OPCODE[0] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][57] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][56] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][55] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][54] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][53] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][52] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][51] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][50] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][49] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][48] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][47] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][46] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][45] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][44] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][43] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][42] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][41] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][40] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][39] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][38] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][37] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][36] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][35] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][34] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][33] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][32] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][31] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][30] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][29] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][28] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][27] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][26] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][25] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][24] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][23] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][22] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][21] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][20] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][19] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][18] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][17] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][16] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][15] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][14] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][13] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][12] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][11] -INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1013.176 ; gain = 304.969 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1013.176 ; gain = 304.969 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1013.176 ; gain = 304.969 ---------------------------------------------------------------------------------- -INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization - -Processing XDC Constraints -Initializing timing engine -Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/GaussFir_12m_ooc.xdc] for cell 'U0' -Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/GaussFir_12m_ooc.xdc] for cell 'U0' -Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/constraints/fir_compiler_v7_2.xdc] for cell 'U0' -Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/constraints/fir_compiler_v7_2.xdc] for cell 'U0' -Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/dont_touch.xdc] -Finished Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/dont_touch.xdc] -Completed Processing XDC Constraints - -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1032.570 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1035.895 ; gain = 3.324 ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1035.895 ; gain = 327.688 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7k410tffg900-2 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1035.895 ; gain = 327.688 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying 'set_property' XDC Constraints ---------------------------------------------------------------------------------- -Applied set_property DONT_TOUCH = true for U0. (constraint file D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/dont_touch.xdc, line 9). ---------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1035.895 ; gain = 327.688 ---------------------------------------------------------------------------------- -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1035.895 ; gain = 327.688 ---------------------------------------------------------------------------------- -INFO: [Synth 8-223] decloning instance 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.i_cntrl_buff_sclr' (delay__parameterized2) to 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.i_cntrl_sym_buff_sclr' - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 1540 (col length:140) -BRAMs: 1590 (col length: RAMB18 140 RAMB36 70) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5587] ROM size for "p_0_out" is below threshold of ROM address width. It will be mapped to LUTs -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_paths[0].g_mem_array[0].i_mem/g_individual.i_mem_a /\gen_dram.gen_rom.d_out_reg[4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_paths[0].g_mem_array[0].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[6] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_paths[0].g_mem_array[1].i_mem/g_individual.i_mem_a /\gen_dram.gen_rom.d_out_reg[8] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_paths[0].g_mem_array[1].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[7] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_paths[0].g_mem_array[2].i_mem/g_individual.i_mem_a /\gen_dram.gen_rom.d_out_reg[1] ) -INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[14]' (FDRE) to 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[15]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tlast_int_reg ) ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1035.895 ; gain = 327.688 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Applying XDC Timing Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:34 . Memory (MB): peak = 1089.375 ; gain = 381.168 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:34 . Memory (MB): peak = 1089.969 ; gain = 381.762 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:27 ; elapsed = 00:00:35 . Memory (MB): peak = 1099.809 ; gain = 391.602 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:28 ; elapsed = 00:00:36 . Memory (MB): peak = 1115.559 ; gain = 407.352 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:28 ; elapsed = 00:00:36 . Memory (MB): peak = 1115.559 ; gain = 407.352 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:28 ; elapsed = 00:00:36 . Memory (MB): peak = 1115.559 ; gain = 407.352 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:28 ; elapsed = 00:00:36 . Memory (MB): peak = 1115.559 ; gain = 407.352 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:28 ; elapsed = 00:00:36 . Memory (MB): peak = 1115.559 ; gain = 407.352 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:28 ; elapsed = 00:00:36 . Memory (MB): peak = 1115.559 ; gain = 407.352 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+--------+------+ -| |Cell |Count | -+------+--------+------+ -|1 |DSP48E1 | 5| -|2 |LUT1 | 3| -|3 |LUT2 | 21| -|4 |LUT3 | 2| -|5 |LUT4 | 6| -|6 |LUT6 | 1| -|7 |SRL16E | 11| -|8 |FDRE | 78| -+------+--------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:28 ; elapsed = 00:00:36 . Memory (MB): peak = 1115.559 ; gain = 407.352 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 97 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:33 . Memory (MB): peak = 1115.559 ; gain = 384.633 -Synthesis Optimization Complete : Time (s): cpu = 00:00:28 ; elapsed = 00:00:37 . Memory (MB): peak = 1115.559 ; gain = 407.352 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1115.559 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -40 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:34 ; elapsed = 00:00:45 . Memory (MB): peak = 1115.559 ; gain = 729.984 -INFO: [Common 17-600] The following parameters have non-default value. -general.maxThreads -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1115.559 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m.dcp' has been generated. -WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP GaussFir_12m, cache-ID = e0ac66ca073c3edd -INFO: [Coretcl 2-1174] Renamed 32 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1115.559 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file GaussFir_12m_utilization_synth.rpt -pb GaussFir_12m_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sat Mar 18 23:33:49 2023... diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_sim_netlist.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_sim_netlist.v deleted file mode 100644 index 733517dd..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_sim_netlist.v +++ /dev/null @@ -1,2400 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:33:48 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_sim_netlist.v -// Design : GaussFir_12m -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* CHECK_LICENSE_TYPE = "GaussFir_12m,fir_compiler_v7_2_12,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *) -(* NotValidForBitStream *) -module GaussFir_12m - (aclk, - s_axis_data_tvalid, - s_axis_data_tready, - s_axis_data_tdata, - m_axis_data_tvalid, - m_axis_data_tdata); - (* x_interface_info = "xilinx.com:signal:clock:1.0 aclk_intf CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *) input aclk; - (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) input s_axis_data_tvalid; - (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY" *) output s_axis_data_tready; - (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA" *) input [7:0]s_axis_data_tdata; - (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) output m_axis_data_tvalid; - (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA" *) output [15:0]m_axis_data_tdata; - - wire aclk; - wire [15:0]m_axis_data_tdata; - wire m_axis_data_tvalid; - wire [7:0]s_axis_data_tdata; - wire s_axis_data_tready; - wire s_axis_data_tvalid; - wire NLW_U0_event_s_config_tlast_missing_UNCONNECTED; - wire NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED; - wire NLW_U0_event_s_data_chanid_incorrect_UNCONNECTED; - wire NLW_U0_event_s_data_tlast_missing_UNCONNECTED; - wire NLW_U0_event_s_data_tlast_unexpected_UNCONNECTED; - wire NLW_U0_event_s_reload_tlast_missing_UNCONNECTED; - wire NLW_U0_event_s_reload_tlast_unexpected_UNCONNECTED; - wire NLW_U0_m_axis_data_tlast_UNCONNECTED; - wire NLW_U0_s_axis_config_tready_UNCONNECTED; - wire NLW_U0_s_axis_reload_tready_UNCONNECTED; - wire [0:0]NLW_U0_m_axis_data_tuser_UNCONNECTED; - - (* C_ACCUM_OP_PATH_WIDTHS = "15" *) - (* C_ACCUM_PATH_WIDTHS = "15" *) - (* C_CHANNEL_PATTERN = "fixed" *) - (* C_COEF_FILE = "GaussFir_12m.mif" *) - (* C_COEF_FILE_LINES = "20" *) - (* C_COEF_MEMTYPE = "2" *) - (* C_COEF_MEM_PACKING = "0" *) - (* C_COEF_PATH_SIGN = "1" *) - (* C_COEF_PATH_SRC = "0" *) - (* C_COEF_PATH_WIDTHS = "14" *) - (* C_COEF_RELOAD = "0" *) - (* C_COEF_WIDTH = "14" *) - (* C_COL_CONFIG = "5" *) - (* C_COL_MODE = "1" *) - (* C_COL_PIPE_LEN = "4" *) - (* C_COMPONENT_NAME = "GaussFir_12m" *) - (* C_CONFIG_PACKET_SIZE = "0" *) - (* C_CONFIG_SYNC_MODE = "0" *) - (* C_CONFIG_TDATA_WIDTH = "1" *) - (* C_DATAPATH_MEMTYPE = "0" *) - (* C_DATA_HAS_TLAST = "0" *) - (* C_DATA_IP_PATH_WIDTHS = "2" *) - (* C_DATA_MEMTYPE = "0" *) - (* C_DATA_MEM_PACKING = "0" *) - (* C_DATA_PATH_PSAMP_SRC = "0" *) - (* C_DATA_PATH_SIGN = "0" *) - (* C_DATA_PATH_SRC = "0" *) - (* C_DATA_PATH_WIDTHS = "2" *) - (* C_DATA_PX_PATH_WIDTHS = "2" *) - (* C_DATA_WIDTH = "2" *) - (* C_DECIM_RATE = "1" *) - (* C_ELABORATION_DIR = "./" *) - (* C_EXT_MULT_CNFG = "none" *) - (* C_FILTER_TYPE = "2" *) - (* C_FILTS_PACKED = "0" *) - (* C_HAS_ACLKEN = "0" *) - (* C_HAS_ARESETn = "0" *) - (* C_HAS_CONFIG_CHANNEL = "0" *) - (* C_INPUT_RATE = "4" *) - (* C_INTERP_RATE = "4" *) - (* C_IPBUFF_MEMTYPE = "0" *) - (* C_LATENCY = "11" *) - (* C_MEM_ARRANGEMENT = "2" *) - (* C_M_DATA_HAS_TREADY = "0" *) - (* C_M_DATA_HAS_TUSER = "0" *) - (* C_M_DATA_TDATA_WIDTH = "16" *) - (* C_M_DATA_TUSER_WIDTH = "1" *) - (* C_NUM_CHANNELS = "1" *) - (* C_NUM_FILTS = "1" *) - (* C_NUM_MADDS = "5" *) - (* C_NUM_RELOAD_SLOTS = "1" *) - (* C_NUM_TAPS = "17" *) - (* C_OPBUFF_MEMTYPE = "0" *) - (* C_OPTIMIZATION = "0" *) - (* C_OPT_MADDS = "none" *) - (* C_OP_PATH_PSAMP_SRC = "0" *) - (* C_OUTPUT_PATH_WIDTHS = "15" *) - (* C_OUTPUT_RATE = "1" *) - (* C_OUTPUT_WIDTH = "15" *) - (* C_OVERSAMPLING_RATE = "1" *) - (* C_PX_PATH_SRC = "0" *) - (* C_RELOAD_TDATA_WIDTH = "1" *) - (* C_ROUND_MODE = "0" *) - (* C_SYMMETRY = "0" *) - (* C_S_DATA_HAS_FIFO = "0" *) - (* C_S_DATA_HAS_TUSER = "0" *) - (* C_S_DATA_TDATA_WIDTH = "8" *) - (* C_S_DATA_TUSER_WIDTH = "1" *) - (* C_XDEVICEFAMILY = "kintex7" *) - (* C_ZERO_PACKING_FACTOR = "1" *) - (* downgradeipidentifiedwarnings = "yes" *) - GaussFir_12m_fir_compiler_v7_2_12 U0 - (.aclk(aclk), - .aclken(1'b1), - .aresetn(1'b1), - .event_s_config_tlast_missing(NLW_U0_event_s_config_tlast_missing_UNCONNECTED), - .event_s_config_tlast_unexpected(NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED), - .event_s_data_chanid_incorrect(NLW_U0_event_s_data_chanid_incorrect_UNCONNECTED), - .event_s_data_tlast_missing(NLW_U0_event_s_data_tlast_missing_UNCONNECTED), - .event_s_data_tlast_unexpected(NLW_U0_event_s_data_tlast_unexpected_UNCONNECTED), - .event_s_reload_tlast_missing(NLW_U0_event_s_reload_tlast_missing_UNCONNECTED), - .event_s_reload_tlast_unexpected(NLW_U0_event_s_reload_tlast_unexpected_UNCONNECTED), - .m_axis_data_tdata(m_axis_data_tdata), - .m_axis_data_tlast(NLW_U0_m_axis_data_tlast_UNCONNECTED), - .m_axis_data_tready(1'b1), - .m_axis_data_tuser(NLW_U0_m_axis_data_tuser_UNCONNECTED[0]), - .m_axis_data_tvalid(m_axis_data_tvalid), - .s_axis_config_tdata(1'b0), - .s_axis_config_tlast(1'b0), - .s_axis_config_tready(NLW_U0_s_axis_config_tready_UNCONNECTED), - .s_axis_config_tvalid(1'b0), - .s_axis_data_tdata(s_axis_data_tdata), - .s_axis_data_tlast(1'b0), - .s_axis_data_tready(s_axis_data_tready), - .s_axis_data_tuser(1'b0), - .s_axis_data_tvalid(s_axis_data_tvalid), - .s_axis_reload_tdata(1'b0), - .s_axis_reload_tlast(1'b0), - .s_axis_reload_tready(NLW_U0_s_axis_reload_tready_UNCONNECTED), - .s_axis_reload_tvalid(1'b0)); -endmodule - -(* C_ACCUM_OP_PATH_WIDTHS = "15" *) (* C_ACCUM_PATH_WIDTHS = "15" *) (* C_CHANNEL_PATTERN = "fixed" *) -(* C_COEF_FILE = "GaussFir_12m.mif" *) (* C_COEF_FILE_LINES = "20" *) (* C_COEF_MEMTYPE = "2" *) -(* C_COEF_MEM_PACKING = "0" *) (* C_COEF_PATH_SIGN = "1" *) (* C_COEF_PATH_SRC = "0" *) -(* C_COEF_PATH_WIDTHS = "14" *) (* C_COEF_RELOAD = "0" *) (* C_COEF_WIDTH = "14" *) -(* C_COL_CONFIG = "5" *) (* C_COL_MODE = "1" *) (* C_COL_PIPE_LEN = "4" *) -(* C_COMPONENT_NAME = "GaussFir_12m" *) (* C_CONFIG_PACKET_SIZE = "0" *) (* C_CONFIG_SYNC_MODE = "0" *) -(* C_CONFIG_TDATA_WIDTH = "1" *) (* C_DATAPATH_MEMTYPE = "0" *) (* C_DATA_HAS_TLAST = "0" *) -(* C_DATA_IP_PATH_WIDTHS = "2" *) (* C_DATA_MEMTYPE = "0" *) (* C_DATA_MEM_PACKING = "0" *) -(* C_DATA_PATH_PSAMP_SRC = "0" *) (* C_DATA_PATH_SIGN = "0" *) (* C_DATA_PATH_SRC = "0" *) -(* C_DATA_PATH_WIDTHS = "2" *) (* C_DATA_PX_PATH_WIDTHS = "2" *) (* C_DATA_WIDTH = "2" *) -(* C_DECIM_RATE = "1" *) (* C_ELABORATION_DIR = "./" *) (* C_EXT_MULT_CNFG = "none" *) -(* C_FILTER_TYPE = "2" *) (* C_FILTS_PACKED = "0" *) (* C_HAS_ACLKEN = "0" *) -(* C_HAS_ARESETn = "0" *) (* C_HAS_CONFIG_CHANNEL = "0" *) (* C_INPUT_RATE = "4" *) -(* C_INTERP_RATE = "4" *) (* C_IPBUFF_MEMTYPE = "0" *) (* C_LATENCY = "11" *) -(* C_MEM_ARRANGEMENT = "2" *) (* C_M_DATA_HAS_TREADY = "0" *) (* C_M_DATA_HAS_TUSER = "0" *) -(* C_M_DATA_TDATA_WIDTH = "16" *) (* C_M_DATA_TUSER_WIDTH = "1" *) (* C_NUM_CHANNELS = "1" *) -(* C_NUM_FILTS = "1" *) (* C_NUM_MADDS = "5" *) (* C_NUM_RELOAD_SLOTS = "1" *) -(* C_NUM_TAPS = "17" *) (* C_OPBUFF_MEMTYPE = "0" *) (* C_OPTIMIZATION = "0" *) -(* C_OPT_MADDS = "none" *) (* C_OP_PATH_PSAMP_SRC = "0" *) (* C_OUTPUT_PATH_WIDTHS = "15" *) -(* C_OUTPUT_RATE = "1" *) (* C_OUTPUT_WIDTH = "15" *) (* C_OVERSAMPLING_RATE = "1" *) -(* C_PX_PATH_SRC = "0" *) (* C_RELOAD_TDATA_WIDTH = "1" *) (* C_ROUND_MODE = "0" *) -(* C_SYMMETRY = "0" *) (* C_S_DATA_HAS_FIFO = "0" *) (* C_S_DATA_HAS_TUSER = "0" *) -(* C_S_DATA_TDATA_WIDTH = "8" *) (* C_S_DATA_TUSER_WIDTH = "1" *) (* C_XDEVICEFAMILY = "kintex7" *) -(* C_ZERO_PACKING_FACTOR = "1" *) (* ORIG_REF_NAME = "fir_compiler_v7_2_12" *) (* downgradeipidentifiedwarnings = "yes" *) -module GaussFir_12m_fir_compiler_v7_2_12 - (aresetn, - aclk, - aclken, - s_axis_data_tvalid, - s_axis_data_tready, - s_axis_data_tlast, - s_axis_data_tuser, - s_axis_data_tdata, - s_axis_config_tvalid, - s_axis_config_tready, - s_axis_config_tlast, - s_axis_config_tdata, - s_axis_reload_tvalid, - s_axis_reload_tready, - s_axis_reload_tlast, - s_axis_reload_tdata, - m_axis_data_tvalid, - m_axis_data_tready, - m_axis_data_tlast, - m_axis_data_tuser, - m_axis_data_tdata, - event_s_data_tlast_missing, - event_s_data_tlast_unexpected, - event_s_data_chanid_incorrect, - event_s_config_tlast_missing, - event_s_config_tlast_unexpected, - event_s_reload_tlast_missing, - event_s_reload_tlast_unexpected); - input aresetn; - input aclk; - input aclken; - input s_axis_data_tvalid; - output s_axis_data_tready; - input s_axis_data_tlast; - input [0:0]s_axis_data_tuser; - input [7:0]s_axis_data_tdata; - input s_axis_config_tvalid; - output s_axis_config_tready; - input s_axis_config_tlast; - input [0:0]s_axis_config_tdata; - input s_axis_reload_tvalid; - output s_axis_reload_tready; - input s_axis_reload_tlast; - input [0:0]s_axis_reload_tdata; - output m_axis_data_tvalid; - input m_axis_data_tready; - output m_axis_data_tlast; - output [0:0]m_axis_data_tuser; - output [15:0]m_axis_data_tdata; - output event_s_data_tlast_missing; - output event_s_data_tlast_unexpected; - output event_s_data_chanid_incorrect; - output event_s_config_tlast_missing; - output event_s_config_tlast_unexpected; - output event_s_reload_tlast_missing; - output event_s_reload_tlast_unexpected; - - wire \ ; - wire aclk; - wire [14:0]\^m_axis_data_tdata ; - wire m_axis_data_tvalid; - wire [7:0]s_axis_data_tdata; - wire s_axis_data_tready; - wire s_axis_data_tvalid; - wire NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED; - wire NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED; - wire NLW_i_synth_event_s_data_chanid_incorrect_UNCONNECTED; - wire NLW_i_synth_event_s_data_tlast_missing_UNCONNECTED; - wire NLW_i_synth_event_s_data_tlast_unexpected_UNCONNECTED; - wire NLW_i_synth_event_s_reload_tlast_missing_UNCONNECTED; - wire NLW_i_synth_event_s_reload_tlast_unexpected_UNCONNECTED; - wire NLW_i_synth_m_axis_data_tlast_UNCONNECTED; - wire NLW_i_synth_s_axis_config_tready_UNCONNECTED; - wire NLW_i_synth_s_axis_reload_tready_UNCONNECTED; - wire [14:14]NLW_i_synth_m_axis_data_tdata_UNCONNECTED; - wire [0:0]NLW_i_synth_m_axis_data_tuser_UNCONNECTED; - - assign event_s_config_tlast_missing = \ ; - assign event_s_config_tlast_unexpected = \ ; - assign event_s_data_chanid_incorrect = \ ; - assign event_s_data_tlast_missing = \ ; - assign event_s_data_tlast_unexpected = \ ; - assign event_s_reload_tlast_missing = \ ; - assign event_s_reload_tlast_unexpected = \ ; - assign m_axis_data_tdata[15] = \^m_axis_data_tdata [14]; - assign m_axis_data_tdata[14:0] = \^m_axis_data_tdata [14:0]; - assign m_axis_data_tlast = \ ; - assign m_axis_data_tuser[0] = \ ; - assign s_axis_config_tready = \ ; - assign s_axis_reload_tready = \ ; - GND GND - (.G(\ )); - (* C_ACCUM_OP_PATH_WIDTHS = "15" *) - (* C_ACCUM_PATH_WIDTHS = "15" *) - (* C_CHANNEL_PATTERN = "fixed" *) - (* C_COEF_FILE = "GaussFir_12m.mif" *) - (* C_COEF_FILE_LINES = "20" *) - (* C_COEF_MEMTYPE = "2" *) - (* C_COEF_MEM_PACKING = "0" *) - (* C_COEF_PATH_SIGN = "1" *) - (* C_COEF_PATH_SRC = "0" *) - (* C_COEF_PATH_WIDTHS = "14" *) - (* C_COEF_RELOAD = "0" *) - (* C_COEF_WIDTH = "14" *) - (* C_COL_CONFIG = "5" *) - (* C_COL_MODE = "1" *) - (* C_COL_PIPE_LEN = "4" *) - (* C_COMPONENT_NAME = "GaussFir_12m" *) - (* C_CONFIG_PACKET_SIZE = "0" *) - (* C_CONFIG_SYNC_MODE = "0" *) - (* C_CONFIG_TDATA_WIDTH = "1" *) - (* C_DATAPATH_MEMTYPE = "0" *) - (* C_DATA_HAS_TLAST = "0" *) - (* C_DATA_IP_PATH_WIDTHS = "2" *) - (* C_DATA_MEMTYPE = "0" *) - (* C_DATA_MEM_PACKING = "0" *) - (* C_DATA_PATH_PSAMP_SRC = "0" *) - (* C_DATA_PATH_SIGN = "0" *) - (* C_DATA_PATH_SRC = "0" *) - (* C_DATA_PATH_WIDTHS = "2" *) - (* C_DATA_PX_PATH_WIDTHS = "2" *) - (* C_DATA_WIDTH = "2" *) - (* C_DECIM_RATE = "1" *) - (* C_ELABORATION_DIR = "./" *) - (* C_EXT_MULT_CNFG = "none" *) - (* C_FILTER_TYPE = "2" *) - (* C_FILTS_PACKED = "0" *) - (* C_HAS_ACLKEN = "0" *) - (* C_HAS_ARESETn = "0" *) - (* C_HAS_CONFIG_CHANNEL = "0" *) - (* C_INPUT_RATE = "4" *) - (* C_INTERP_RATE = "4" *) - (* C_IPBUFF_MEMTYPE = "0" *) - (* C_LATENCY = "11" *) - (* C_MEM_ARRANGEMENT = "2" *) - (* C_M_DATA_HAS_TREADY = "0" *) - (* C_M_DATA_HAS_TUSER = "0" *) - (* C_M_DATA_TDATA_WIDTH = "16" *) - (* C_M_DATA_TUSER_WIDTH = "1" *) - (* C_NUM_CHANNELS = "1" *) - (* C_NUM_FILTS = "1" *) - (* C_NUM_MADDS = "5" *) - (* C_NUM_RELOAD_SLOTS = "1" *) - (* C_NUM_TAPS = "17" *) - (* C_OPBUFF_MEMTYPE = "0" *) - (* C_OPTIMIZATION = "0" *) - (* C_OPT_MADDS = "none" *) - (* C_OP_PATH_PSAMP_SRC = "0" *) - (* C_OUTPUT_PATH_WIDTHS = "15" *) - (* C_OUTPUT_RATE = "1" *) - (* C_OUTPUT_WIDTH = "15" *) - (* C_OVERSAMPLING_RATE = "1" *) - (* C_PX_PATH_SRC = "0" *) - (* C_RELOAD_TDATA_WIDTH = "1" *) - (* C_ROUND_MODE = "0" *) - (* C_SYMMETRY = "0" *) - (* C_S_DATA_HAS_FIFO = "0" *) - (* C_S_DATA_HAS_TUSER = "0" *) - (* C_S_DATA_TDATA_WIDTH = "8" *) - (* C_S_DATA_TUSER_WIDTH = "1" *) - (* C_XDEVICEFAMILY = "kintex7" *) - (* C_ZERO_PACKING_FACTOR = "1" *) - (* downgradeipidentifiedwarnings = "yes" *) - GaussFir_12m_fir_compiler_v7_2_12_viv i_synth - (.aclk(aclk), - .aclken(1'b0), - .aresetn(1'b0), - .event_s_config_tlast_missing(NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED), - .event_s_config_tlast_unexpected(NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED), - .event_s_data_chanid_incorrect(NLW_i_synth_event_s_data_chanid_incorrect_UNCONNECTED), - .event_s_data_tlast_missing(NLW_i_synth_event_s_data_tlast_missing_UNCONNECTED), - .event_s_data_tlast_unexpected(NLW_i_synth_event_s_data_tlast_unexpected_UNCONNECTED), - .event_s_reload_tlast_missing(NLW_i_synth_event_s_reload_tlast_missing_UNCONNECTED), - .event_s_reload_tlast_unexpected(NLW_i_synth_event_s_reload_tlast_unexpected_UNCONNECTED), - .m_axis_data_tdata({\^m_axis_data_tdata [14],NLW_i_synth_m_axis_data_tdata_UNCONNECTED[14],\^m_axis_data_tdata [13:0]}), - .m_axis_data_tlast(NLW_i_synth_m_axis_data_tlast_UNCONNECTED), - .m_axis_data_tready(1'b0), - .m_axis_data_tuser(NLW_i_synth_m_axis_data_tuser_UNCONNECTED[0]), - .m_axis_data_tvalid(m_axis_data_tvalid), - .s_axis_config_tdata(1'b0), - .s_axis_config_tlast(1'b0), - .s_axis_config_tready(NLW_i_synth_s_axis_config_tready_UNCONNECTED), - .s_axis_config_tvalid(1'b0), - .s_axis_data_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,s_axis_data_tdata[1:0]}), - .s_axis_data_tlast(1'b0), - .s_axis_data_tready(s_axis_data_tready), - .s_axis_data_tuser(1'b0), - .s_axis_data_tvalid(s_axis_data_tvalid), - .s_axis_reload_tdata(1'b0), - .s_axis_reload_tlast(1'b0), - .s_axis_reload_tready(NLW_i_synth_s_axis_reload_tready_UNCONNECTED), - .s_axis_reload_tvalid(1'b0)); -endmodule -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "XILINX" -`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" -`pragma protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=64) -`pragma protect key_block -I5jBxSA30qMppesbkWzApATD001KfSyiO/EXeiSfqG/mDp7bWT98b6O2aLKwO2KBiQHns7D4kNzR -1vJ+KztHDg== - -`pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128) -`pragma protect key_block -WMu7kFTLnidedbfVrZuh/7ca7CUttjqfOqFAqALtw+gkp4fPh7ZCC2c3FriF2MGJNdt0inCBZQ1w -ERGO+2E2lzKAF62aWczdna33VjhJbQEhVD66TE3XkcNa3kH5qqUhb+EgT0e6ErzcmqjyjnkFxoKK -XKvbLV/yC8Myvjbgd1A= - -`pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`pragma protect key_block -xD5n0VbWIE6P1VxF0RmDDu2TYD4jh2LNu0PcTQhqBRKitH0v3xG4GrD/vuHfz6qhNoYV25YBOEWi -7kVjcZSXNFtC5ITuwneS2ZMRryiXpM8fFiU2j9L4eELr2/mHrJrVvacPISdaWzzVZMaXZGjjLF31 -zK98DBrt3GchBNvrcOgQmuPVAvjrSEZ+P+LhtLFVfq/zmFgYzV3AELJD6jr7elUkLyTjsJWEFYcf -b43n7Hb0i+cIbRt6Dd+v0kyLoVGDXUE7IXud31zG1Rotvh/eF07hFqqllLHHu2UWUNW8RAWEy1Fo -3/0kdpsYoC+scwVlEiw6L4xm3ZvOMO3xLhlx9Q== - -`pragma protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa" 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Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`pragma protect key_block -gk4RqgvNIG8lEex3wtMa4M3v30L0l+y0oWcBfGNO5VPXpnehoIdIjw5AFsooYYK6yx/cu/p6GCeN -aMSJiQoAoQ7xMUrXydqyR/RwSiYJHx/ZSBG82BCdeguAEPkxJnSclcsGWIYwQ8hpp/KnJy76rcpT -/3DVh5izq0/GcLIfdvX/ICJATZonr/j6x6E3AhtcpNRnKsqS+e8VZYW/Qd8bW0uvSKj+oAE8tmnx -NYvINJVoxLBqNLglkjbSy+NvK9JD3Ey5ZeWlF2xgvhokwRZ1acR1EoFLQVfOv+XHhyxPGH6UGk2v -Jk5q6LM/RtcmcQaf3o/R/7IclGghBlOvx8I8sg== - -`pragma protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`pragma protect key_block -azfW/uH4+7na1c5MypPVAw0isPaeiRpvqTu5gnZ/xgQsRJZ3DoWAuFksom0Klkh1Y9xYdS6eGCBy -YPYA6c4SxFj9MPGHrd3C1FwUglmDt+OItxatr6U32tyuuNE5GIAG7733XZZ+lfsJbMIWg2MH4Qzh -mLAZucnBEQQKs2ZuIYHLD32RNzFSKPNiimhR9pHIAnDw6ft5ZHdrqylxMLB2r1cB4H3NJOpveE5k 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-------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_sim_netlist.vhdl deleted file mode 100644 index 59601778..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_sim_netlist.vhdl +++ /dev/null @@ -1,3344 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:33:48 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_sim_netlist.vhdl --- Design : GaussFir_12m --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -`protect begin_protected -`protect version = 1 -`protect encrypt_agent = "XILINX" -`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" -`protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=64) -`protect key_block -I5jBxSA30qMppesbkWzApATD001KfSyiO/EXeiSfqG/mDp7bWT98b6O2aLKwO2KBiQHns7D4kNzR -1vJ+KztHDg== - -`protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=128) -`protect key_block -WMu7kFTLnidedbfVrZuh/7ca7CUttjqfOqFAqALtw+gkp4fPh7ZCC2c3FriF2MGJNdt0inCBZQ1w -ERGO+2E2lzKAF62aWczdna33VjhJbQEhVD66TE3XkcNa3kH5qqUhb+EgT0e6ErzcmqjyjnkFxoKK -XKvbLV/yC8Myvjbgd1A= - -`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`protect key_block -xD5n0VbWIE6P1VxF0RmDDu2TYD4jh2LNu0PcTQhqBRKitH0v3xG4GrD/vuHfz6qhNoYV25YBOEWi -7kVjcZSXNFtC5ITuwneS2ZMRryiXpM8fFiU2j9L4eELr2/mHrJrVvacPISdaWzzVZMaXZGjjLF31 -zK98DBrt3GchBNvrcOgQmuPVAvjrSEZ+P+LhtLFVfq/zmFgYzV3AELJD6jr7elUkLyTjsJWEFYcf -b43n7Hb0i+cIbRt6Dd+v0kyLoVGDXUE7IXud31zG1Rotvh/eF07hFqqllLHHu2UWUNW8RAWEy1Fo -3/0kdpsYoC+scwVlEiw6L4xm3ZvOMO3xLhlx9Q== - -`protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`protect key_block -fQrDOnMjpZojQhY1c1rw1hwuEu2Y2M8ofkmIyKutN5o3WWgs402wk38nunx4Rn3nJ4alOoXDi3N8 -wCK4FFFUnB/83xpx5yiE801fH9CrSpiGk2CFUTGUPQ2AKib6X7q/ypXzIE3Xi/Fp8v68pOYfzYgB -DWCJiGAer9WgqVkNoAOLB2B99+hjhpjUr+bqeFKCONh+smCJvnzi5NuFbGTw6NRi9XF/fOBJpA7N -7mSHNKQA9TZaG877TLVUYWhpu8Tllt4YOnNvOy5csoZO6jBxXCjuxWmM9dl9WSOXp2HX/onR6rpz -sNUbO2lQftIr2WNh0Jv073YUwDxDBpl586IEWg== - -`protect key_keyowner="Xilinx", key_keyname="xilinxt_2019_02", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`protect key_block -Yt/xtD+YwHpwIG7cpV+YFKRLELTuOpDyL++EbS2PSHkTTnkY+SDEglVSGBUkgEMCy4FK2fL2wt2N -qjVnO38YwcIpkFA3hdVylOufwvfkyXzLnO4I/oXAmiPI3b+yEyPArGvVOGpDgyd07VUs/V9x8yNF -fJU+AQwpZcLwvczmvjIU4/eR8fdXCMBV/C6JW2N+CHrwTU69ne3XstJaVfOIPupKIpZjLVLIrAYs -UQMdOWUz5FDENYd645Oho01vEbgtbLb+GrcpRedjCAIY2LgO42kQ9rDb7oVFFsUuoIPnWF4fLEjb -Pq5mb00fUdX1TzSueiRRmMIn69wkk/QkSb8jag== - -`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=128) -`protect key_block -S5Ng9U2ICFR2ATladKVkI9g1B4mI1wuXRMAnMNgbxvoijFO8db10A3+6fvjuey2Yzxp1Hf4dZcYN -c/lBn1GB/WXkp/IAC1a0hNWcvyknzHaPnT0XXAr2t5Xncs67wJ8pN5Gp2D1qrZQQzDnNoYG2S/bd -YiWvkcmY78GRhm+UXVk= - -`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa" -`protect 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key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`protect key_block -c5C/t9DTEa5Jg9aiR4h8FvIAQU7KYufvKNXB0pBrGYBxk9wwEjz3uQJ4DrJy11F695oS8rO7IpYA -x+mKRKDoYvj5sSPdzhp8kXERhmzsRXlm63AWVk5EsZN7IW1+wd2SzYPe3rhyi/YJys6smwRbCEUz -l7ek0ZYa/b4i5jZ3j6WbNudzyvh8qzbit2/OGYiD3Gt1e85mR62T8XltQDnOsU+sQ2TYBGMSLC1t -JmBOARarj+ScUAZCIhY7SPB4OyfIXNptg7TFAaRoqLRmRQ42YrtwjOE4/iHiFywI/BV4ljEb6HK7 -4wwbrm04SQXYL4ECQCZ1ocxesbOPclth8NgfIA== - -`protect data_method = "AES128-CBC" -`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 154432) -`protect data_block -esa3DMaYPU+R/pNANap7uh4b4Gp8mXvPeDrr0g2xo34kcmobL3JYnKzlf9QS5c/C2/N+5ShteGG1 -q9KyIgsWlB802f1r6ENVQAzSBQTECYE0rp1Cs1Syl43DmfLXEzuxz2EsPTH47MMFZ10sfRcQblFD -7+3/YQBotHeMACNxTZan3RYMrvMfnXr6ZFZqk+hU2K9X8XSAYOLLQ5JyPnGnStizcS0Dl6tYZesd -nObf95qTE8gM0859UbTx5KiDeVqr2aJnbQ9489xbsy2TzLM/fJAX4SEW7Lmzk6vu0adHRQ5O0VbB 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-Kxyi0LEtuV0h0vM81pxIVbOtAQRH/hOKl6IpPersVuS2NT5n/6pf1pQg8KuofsYP+SDAi16ZgI0e -IY1WUWxgY+fX0D7qI9AJzx6J+SZyWVnQGILuq7/2b9GUboApWWIUZMCxBL6Nu7svBpKXYkZdI/f/ -a4zINogHhqo05q9sxch9BR0B3Eb6N/5PsZ2UE94Xth7+NndxbxT1kgfVXMiF540o1RhaaGThs6D5 -Po2cNEfJ0MF2AZnM/rv7q0xMeOqMeF8upotBhjTndSpC97ntsrlgTykbPFRCrn7eNS3KocQj9f4e -kJ8YhLmzTrc5OAb84Ld6VT0DLH9o6JdjeXP0APa3qX2+wwpIWQ9SjGa6Cny+IsiV4XZkGWNX/2Jj -0PafHhOoL/GwWIg13MLReQiLcQ== -`protect end_protected -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity GaussFir_12m_fir_compiler_v7_2_12 is - port ( - aresetn : in STD_LOGIC; - aclk : in STD_LOGIC; - aclken : in STD_LOGIC; - s_axis_data_tvalid : in STD_LOGIC; - s_axis_data_tready : out STD_LOGIC; - s_axis_data_tlast : in STD_LOGIC; - s_axis_data_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axis_config_tvalid : in STD_LOGIC; - s_axis_config_tready : out STD_LOGIC; - s_axis_config_tlast : in STD_LOGIC; - s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axis_reload_tvalid : in STD_LOGIC; - s_axis_reload_tready : out STD_LOGIC; - s_axis_reload_tlast : in STD_LOGIC; - s_axis_reload_tdata : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_data_tvalid : out STD_LOGIC; - m_axis_data_tready : in STD_LOGIC; - m_axis_data_tlast : out STD_LOGIC; - m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); - event_s_data_tlast_missing : out STD_LOGIC; - event_s_data_tlast_unexpected : out STD_LOGIC; - event_s_data_chanid_incorrect : out STD_LOGIC; - event_s_config_tlast_missing : out STD_LOGIC; - event_s_config_tlast_unexpected : out STD_LOGIC; - event_s_reload_tlast_missing : out STD_LOGIC; - event_s_reload_tlast_unexpected : out STD_LOGIC - ); - attribute C_ACCUM_OP_PATH_WIDTHS : string; - attribute C_ACCUM_OP_PATH_WIDTHS of GaussFir_12m_fir_compiler_v7_2_12 : entity is "15"; - attribute C_ACCUM_PATH_WIDTHS : string; - attribute C_ACCUM_PATH_WIDTHS of GaussFir_12m_fir_compiler_v7_2_12 : entity is "15"; - attribute C_CHANNEL_PATTERN : string; - attribute C_CHANNEL_PATTERN of GaussFir_12m_fir_compiler_v7_2_12 : entity is "fixed"; - attribute C_COEF_FILE : string; - attribute C_COEF_FILE of GaussFir_12m_fir_compiler_v7_2_12 : entity is "GaussFir_12m.mif"; - attribute C_COEF_FILE_LINES : integer; - attribute C_COEF_FILE_LINES of GaussFir_12m_fir_compiler_v7_2_12 : entity is 20; - attribute C_COEF_MEMTYPE : integer; - attribute C_COEF_MEMTYPE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 2; - attribute C_COEF_MEM_PACKING : integer; - attribute C_COEF_MEM_PACKING of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_COEF_PATH_SIGN : string; - attribute C_COEF_PATH_SIGN of GaussFir_12m_fir_compiler_v7_2_12 : entity is "1"; - attribute C_COEF_PATH_SRC : string; - attribute C_COEF_PATH_SRC of GaussFir_12m_fir_compiler_v7_2_12 : entity is "0"; - attribute C_COEF_PATH_WIDTHS : string; - attribute C_COEF_PATH_WIDTHS of GaussFir_12m_fir_compiler_v7_2_12 : entity is "14"; - attribute C_COEF_RELOAD : integer; - attribute C_COEF_RELOAD of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_COEF_WIDTH : integer; - attribute C_COEF_WIDTH of GaussFir_12m_fir_compiler_v7_2_12 : entity is 14; - attribute C_COL_CONFIG : string; - attribute C_COL_CONFIG of GaussFir_12m_fir_compiler_v7_2_12 : entity is "5"; - attribute C_COL_MODE : integer; - attribute C_COL_MODE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_COL_PIPE_LEN : integer; - attribute C_COL_PIPE_LEN of GaussFir_12m_fir_compiler_v7_2_12 : entity is 4; - attribute C_COMPONENT_NAME : string; - attribute C_COMPONENT_NAME of GaussFir_12m_fir_compiler_v7_2_12 : entity is "GaussFir_12m"; - attribute C_CONFIG_PACKET_SIZE : integer; - attribute C_CONFIG_PACKET_SIZE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_CONFIG_SYNC_MODE : integer; - attribute C_CONFIG_SYNC_MODE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_CONFIG_TDATA_WIDTH : integer; - attribute C_CONFIG_TDATA_WIDTH of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_DATAPATH_MEMTYPE : integer; - attribute C_DATAPATH_MEMTYPE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_DATA_HAS_TLAST : integer; - attribute C_DATA_HAS_TLAST of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_DATA_IP_PATH_WIDTHS : string; - attribute C_DATA_IP_PATH_WIDTHS of GaussFir_12m_fir_compiler_v7_2_12 : entity is "2"; - attribute C_DATA_MEMTYPE : integer; - attribute C_DATA_MEMTYPE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_DATA_MEM_PACKING : integer; - attribute C_DATA_MEM_PACKING of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_DATA_PATH_PSAMP_SRC : string; - attribute C_DATA_PATH_PSAMP_SRC of GaussFir_12m_fir_compiler_v7_2_12 : entity is "0"; - attribute C_DATA_PATH_SIGN : string; - attribute C_DATA_PATH_SIGN of GaussFir_12m_fir_compiler_v7_2_12 : entity is "0"; - attribute C_DATA_PATH_SRC : string; - attribute C_DATA_PATH_SRC of GaussFir_12m_fir_compiler_v7_2_12 : entity is "0"; - attribute C_DATA_PATH_WIDTHS : string; - attribute C_DATA_PATH_WIDTHS of GaussFir_12m_fir_compiler_v7_2_12 : entity is "2"; - attribute C_DATA_PX_PATH_WIDTHS : string; - attribute C_DATA_PX_PATH_WIDTHS of GaussFir_12m_fir_compiler_v7_2_12 : entity is "2"; - attribute C_DATA_WIDTH : integer; - attribute C_DATA_WIDTH of GaussFir_12m_fir_compiler_v7_2_12 : entity is 2; - attribute C_DECIM_RATE : integer; - attribute C_DECIM_RATE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_ELABORATION_DIR : string; - attribute C_ELABORATION_DIR of GaussFir_12m_fir_compiler_v7_2_12 : entity is "./"; - attribute C_EXT_MULT_CNFG : string; - attribute C_EXT_MULT_CNFG of GaussFir_12m_fir_compiler_v7_2_12 : entity is "none"; - attribute C_FILTER_TYPE : integer; - attribute C_FILTER_TYPE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 2; - attribute C_FILTS_PACKED : integer; - attribute C_FILTS_PACKED of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_HAS_ACLKEN : integer; - attribute C_HAS_ACLKEN of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_HAS_ARESETn : integer; - attribute C_HAS_ARESETn of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_HAS_CONFIG_CHANNEL : integer; - attribute C_HAS_CONFIG_CHANNEL of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_INPUT_RATE : integer; - attribute C_INPUT_RATE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 4; - attribute C_INTERP_RATE : integer; - attribute C_INTERP_RATE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 4; - attribute C_IPBUFF_MEMTYPE : integer; - attribute C_IPBUFF_MEMTYPE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_LATENCY : integer; - attribute C_LATENCY of GaussFir_12m_fir_compiler_v7_2_12 : entity is 11; - attribute C_MEM_ARRANGEMENT : integer; - attribute C_MEM_ARRANGEMENT of GaussFir_12m_fir_compiler_v7_2_12 : entity is 2; - attribute C_M_DATA_HAS_TREADY : integer; - attribute C_M_DATA_HAS_TREADY of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_M_DATA_HAS_TUSER : integer; - attribute C_M_DATA_HAS_TUSER of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_M_DATA_TDATA_WIDTH : integer; - attribute C_M_DATA_TDATA_WIDTH of GaussFir_12m_fir_compiler_v7_2_12 : entity is 16; - attribute C_M_DATA_TUSER_WIDTH : integer; - attribute C_M_DATA_TUSER_WIDTH of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_NUM_CHANNELS : integer; - attribute C_NUM_CHANNELS of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_NUM_FILTS : integer; - attribute C_NUM_FILTS of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_NUM_MADDS : integer; - attribute C_NUM_MADDS of GaussFir_12m_fir_compiler_v7_2_12 : entity is 5; - attribute C_NUM_RELOAD_SLOTS : integer; - attribute C_NUM_RELOAD_SLOTS of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_NUM_TAPS : integer; - attribute C_NUM_TAPS of GaussFir_12m_fir_compiler_v7_2_12 : entity is 17; - attribute C_OPBUFF_MEMTYPE : integer; - attribute C_OPBUFF_MEMTYPE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_OPTIMIZATION : integer; - attribute C_OPTIMIZATION of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_OPT_MADDS : string; - attribute C_OPT_MADDS of GaussFir_12m_fir_compiler_v7_2_12 : entity is "none"; - attribute C_OP_PATH_PSAMP_SRC : string; - attribute C_OP_PATH_PSAMP_SRC of GaussFir_12m_fir_compiler_v7_2_12 : entity is "0"; - attribute C_OUTPUT_PATH_WIDTHS : string; - attribute C_OUTPUT_PATH_WIDTHS of GaussFir_12m_fir_compiler_v7_2_12 : entity is "15"; - attribute C_OUTPUT_RATE : integer; - attribute C_OUTPUT_RATE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_OUTPUT_WIDTH : integer; - attribute C_OUTPUT_WIDTH of GaussFir_12m_fir_compiler_v7_2_12 : entity is 15; - attribute C_OVERSAMPLING_RATE : integer; - attribute C_OVERSAMPLING_RATE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_PX_PATH_SRC : string; - attribute C_PX_PATH_SRC of GaussFir_12m_fir_compiler_v7_2_12 : entity is "0"; - attribute C_RELOAD_TDATA_WIDTH : integer; - attribute C_RELOAD_TDATA_WIDTH of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_ROUND_MODE : integer; - attribute C_ROUND_MODE of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_SYMMETRY : integer; - attribute C_SYMMETRY of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_S_DATA_HAS_FIFO : integer; - attribute C_S_DATA_HAS_FIFO of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_S_DATA_HAS_TUSER : integer; - attribute C_S_DATA_HAS_TUSER of GaussFir_12m_fir_compiler_v7_2_12 : entity is 0; - attribute C_S_DATA_TDATA_WIDTH : integer; - attribute C_S_DATA_TDATA_WIDTH of GaussFir_12m_fir_compiler_v7_2_12 : entity is 8; - attribute C_S_DATA_TUSER_WIDTH : integer; - attribute C_S_DATA_TUSER_WIDTH of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of GaussFir_12m_fir_compiler_v7_2_12 : entity is "kintex7"; - attribute C_ZERO_PACKING_FACTOR : integer; - attribute C_ZERO_PACKING_FACTOR of GaussFir_12m_fir_compiler_v7_2_12 : entity is 1; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of GaussFir_12m_fir_compiler_v7_2_12 : entity is "fir_compiler_v7_2_12"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of GaussFir_12m_fir_compiler_v7_2_12 : entity is "yes"; -end GaussFir_12m_fir_compiler_v7_2_12; - -architecture STRUCTURE of GaussFir_12m_fir_compiler_v7_2_12 is - signal \\ : STD_LOGIC; - signal \^m_axis_data_tdata\ : STD_LOGIC_VECTOR ( 14 downto 0 ); - signal NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_data_chanid_incorrect_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_data_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_data_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_reload_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_reload_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_m_axis_data_tlast_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_s_axis_config_tready_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_s_axis_reload_tready_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_m_axis_data_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 14 to 14 ); - signal NLW_i_synth_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - attribute C_ACCUM_OP_PATH_WIDTHS of i_synth : label is "15"; - attribute C_ACCUM_PATH_WIDTHS of i_synth : label is "15"; - attribute C_CHANNEL_PATTERN of i_synth : label is "fixed"; - attribute C_COEF_FILE of i_synth : label is "GaussFir_12m.mif"; - attribute C_COEF_FILE_LINES of i_synth : label is 20; - attribute C_COEF_MEMTYPE of i_synth : label is 2; - attribute C_COEF_MEM_PACKING of i_synth : label is 0; - attribute C_COEF_PATH_SIGN of i_synth : label is "1"; - attribute C_COEF_PATH_SRC of i_synth : label is "0"; - attribute C_COEF_PATH_WIDTHS of i_synth : label is "14"; - attribute C_COEF_RELOAD of i_synth : label is 0; - attribute C_COEF_WIDTH of i_synth : label is 14; - attribute C_COL_CONFIG of i_synth : label is "5"; - attribute C_COL_MODE of i_synth : label is 1; - attribute C_COL_PIPE_LEN of i_synth : label is 4; - attribute C_COMPONENT_NAME of i_synth : label is "GaussFir_12m"; - attribute C_CONFIG_PACKET_SIZE of i_synth : label is 0; - attribute C_CONFIG_SYNC_MODE of i_synth : label is 0; - attribute C_CONFIG_TDATA_WIDTH of i_synth : label is 1; - attribute C_DATAPATH_MEMTYPE of i_synth : label is 0; - attribute C_DATA_HAS_TLAST of i_synth : label is 0; - attribute C_DATA_IP_PATH_WIDTHS of i_synth : label is "2"; - attribute C_DATA_MEMTYPE of i_synth : label is 0; - attribute C_DATA_MEM_PACKING of i_synth : label is 0; - attribute C_DATA_PATH_PSAMP_SRC of i_synth : label is "0"; - attribute C_DATA_PATH_SIGN of i_synth : label is "0"; - attribute C_DATA_PATH_SRC of i_synth : label is "0"; - attribute C_DATA_PATH_WIDTHS of i_synth : label is "2"; - attribute C_DATA_PX_PATH_WIDTHS of i_synth : label is "2"; - attribute C_DATA_WIDTH of i_synth : label is 2; - attribute C_DECIM_RATE of i_synth : label is 1; - attribute C_ELABORATION_DIR of i_synth : label is "./"; - attribute C_EXT_MULT_CNFG of i_synth : label is "none"; - attribute C_FILTER_TYPE of i_synth : label is 2; - attribute C_FILTS_PACKED of i_synth : label is 0; - attribute C_HAS_ACLKEN of i_synth : label is 0; - attribute C_HAS_ARESETn of i_synth : label is 0; - attribute C_HAS_CONFIG_CHANNEL of i_synth : label is 0; - attribute C_INPUT_RATE of i_synth : label is 4; - attribute C_INTERP_RATE of i_synth : label is 4; - attribute C_IPBUFF_MEMTYPE of i_synth : label is 0; - attribute C_LATENCY of i_synth : label is 11; - attribute C_MEM_ARRANGEMENT of i_synth : label is 2; - attribute C_M_DATA_HAS_TREADY of i_synth : label is 0; - attribute C_M_DATA_HAS_TUSER of i_synth : label is 0; - attribute C_M_DATA_TDATA_WIDTH of i_synth : label is 16; - attribute C_M_DATA_TUSER_WIDTH of i_synth : label is 1; - attribute C_NUM_CHANNELS of i_synth : label is 1; - attribute C_NUM_FILTS of i_synth : label is 1; - attribute C_NUM_MADDS of i_synth : label is 5; - attribute C_NUM_RELOAD_SLOTS of i_synth : label is 1; - attribute C_NUM_TAPS of i_synth : label is 17; - attribute C_OPBUFF_MEMTYPE of i_synth : label is 0; - attribute C_OPTIMIZATION of i_synth : label is 0; - attribute C_OPT_MADDS of i_synth : label is "none"; - attribute C_OP_PATH_PSAMP_SRC of i_synth : label is "0"; - attribute C_OUTPUT_PATH_WIDTHS of i_synth : label is "15"; - attribute C_OUTPUT_RATE of i_synth : label is 1; - attribute C_OUTPUT_WIDTH of i_synth : label is 15; - attribute C_OVERSAMPLING_RATE of i_synth : label is 1; - attribute C_PX_PATH_SRC of i_synth : label is "0"; - attribute C_RELOAD_TDATA_WIDTH of i_synth : label is 1; - attribute C_ROUND_MODE of i_synth : label is 0; - attribute C_SYMMETRY of i_synth : label is 0; - attribute C_S_DATA_HAS_FIFO of i_synth : label is 0; - attribute C_S_DATA_HAS_TUSER of i_synth : label is 0; - attribute C_S_DATA_TDATA_WIDTH of i_synth : label is 8; - attribute C_S_DATA_TUSER_WIDTH of i_synth : label is 1; - attribute C_XDEVICEFAMILY of i_synth : label is "kintex7"; - attribute C_ZERO_PACKING_FACTOR of i_synth : label is 1; - attribute downgradeipidentifiedwarnings of i_synth : label is "yes"; -begin - event_s_config_tlast_missing <= \\; - event_s_config_tlast_unexpected <= \\; - event_s_data_chanid_incorrect <= \\; - event_s_data_tlast_missing <= \\; - event_s_data_tlast_unexpected <= \\; - event_s_reload_tlast_missing <= \\; - event_s_reload_tlast_unexpected <= \\; - m_axis_data_tdata(15) <= \^m_axis_data_tdata\(14); - m_axis_data_tdata(14 downto 0) <= \^m_axis_data_tdata\(14 downto 0); - m_axis_data_tlast <= \\; - m_axis_data_tuser(0) <= \\; - s_axis_config_tready <= \\; - s_axis_reload_tready <= \\; -GND: unisim.vcomponents.GND - port map ( - G => \\ - ); -i_synth: entity work.GaussFir_12m_fir_compiler_v7_2_12_viv - port map ( - aclk => aclk, - aclken => '0', - aresetn => '0', - event_s_config_tlast_missing => NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED, - event_s_config_tlast_unexpected => NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED, - event_s_data_chanid_incorrect => NLW_i_synth_event_s_data_chanid_incorrect_UNCONNECTED, - event_s_data_tlast_missing => NLW_i_synth_event_s_data_tlast_missing_UNCONNECTED, - event_s_data_tlast_unexpected => NLW_i_synth_event_s_data_tlast_unexpected_UNCONNECTED, - event_s_reload_tlast_missing => NLW_i_synth_event_s_reload_tlast_missing_UNCONNECTED, - event_s_reload_tlast_unexpected => NLW_i_synth_event_s_reload_tlast_unexpected_UNCONNECTED, - m_axis_data_tdata(15) => \^m_axis_data_tdata\(14), - m_axis_data_tdata(14) => NLW_i_synth_m_axis_data_tdata_UNCONNECTED(14), - m_axis_data_tdata(13 downto 0) => \^m_axis_data_tdata\(13 downto 0), - m_axis_data_tlast => NLW_i_synth_m_axis_data_tlast_UNCONNECTED, - m_axis_data_tready => '0', - m_axis_data_tuser(0) => NLW_i_synth_m_axis_data_tuser_UNCONNECTED(0), - m_axis_data_tvalid => m_axis_data_tvalid, - s_axis_config_tdata(0) => '0', - s_axis_config_tlast => '0', - s_axis_config_tready => NLW_i_synth_s_axis_config_tready_UNCONNECTED, - s_axis_config_tvalid => '0', - s_axis_data_tdata(7 downto 2) => B"000000", - s_axis_data_tdata(1 downto 0) => s_axis_data_tdata(1 downto 0), - s_axis_data_tlast => '0', - s_axis_data_tready => s_axis_data_tready, - s_axis_data_tuser(0) => '0', - s_axis_data_tvalid => s_axis_data_tvalid, - s_axis_reload_tdata(0) => '0', - s_axis_reload_tlast => '0', - s_axis_reload_tready => NLW_i_synth_s_axis_reload_tready_UNCONNECTED, - s_axis_reload_tvalid => '0' - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity GaussFir_12m is - port ( - aclk : in STD_LOGIC; - s_axis_data_tvalid : in STD_LOGIC; - s_axis_data_tready : out STD_LOGIC; - s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); - m_axis_data_tvalid : out STD_LOGIC; - m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ) - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of GaussFir_12m : entity is true; - attribute CHECK_LICENSE_TYPE : string; - attribute CHECK_LICENSE_TYPE of GaussFir_12m : entity is "GaussFir_12m,fir_compiler_v7_2_12,{}"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of GaussFir_12m : entity is "yes"; - attribute x_core_info : string; - attribute x_core_info of GaussFir_12m : entity is "fir_compiler_v7_2_12,Vivado 2019.1.3"; -end GaussFir_12m; - -architecture STRUCTURE of GaussFir_12m is - signal NLW_U0_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_data_chanid_incorrect_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_data_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_data_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_reload_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_reload_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_U0_m_axis_data_tlast_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axis_config_tready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axis_reload_tready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - attribute C_ACCUM_OP_PATH_WIDTHS : string; - attribute C_ACCUM_OP_PATH_WIDTHS of U0 : label is "15"; - attribute C_ACCUM_PATH_WIDTHS : string; - attribute C_ACCUM_PATH_WIDTHS of U0 : label is "15"; - attribute C_CHANNEL_PATTERN : string; - attribute C_CHANNEL_PATTERN of U0 : label is "fixed"; - attribute C_COEF_FILE : string; - attribute C_COEF_FILE of U0 : label is "GaussFir_12m.mif"; - attribute C_COEF_FILE_LINES : integer; - attribute C_COEF_FILE_LINES of U0 : label is 20; - attribute C_COEF_MEMTYPE : integer; - attribute C_COEF_MEMTYPE of U0 : label is 2; - attribute C_COEF_MEM_PACKING : integer; - attribute C_COEF_MEM_PACKING of U0 : label is 0; - attribute C_COEF_PATH_SIGN : string; - attribute C_COEF_PATH_SIGN of U0 : label is "1"; - attribute C_COEF_PATH_SRC : string; - attribute C_COEF_PATH_SRC of U0 : label is "0"; - attribute C_COEF_PATH_WIDTHS : string; - attribute C_COEF_PATH_WIDTHS of U0 : label is "14"; - attribute C_COEF_RELOAD : integer; - attribute C_COEF_RELOAD of U0 : label is 0; - attribute C_COEF_WIDTH : integer; - attribute C_COEF_WIDTH of U0 : label is 14; - attribute C_COL_CONFIG : string; - attribute C_COL_CONFIG of U0 : label is "5"; - attribute C_COL_MODE : integer; - attribute C_COL_MODE of U0 : label is 1; - attribute C_COL_PIPE_LEN : integer; - attribute C_COL_PIPE_LEN of U0 : label is 4; - attribute C_COMPONENT_NAME : string; - attribute C_COMPONENT_NAME of U0 : label is "GaussFir_12m"; - attribute C_CONFIG_PACKET_SIZE : integer; - attribute C_CONFIG_PACKET_SIZE of U0 : label is 0; - attribute C_CONFIG_SYNC_MODE : integer; - attribute C_CONFIG_SYNC_MODE of U0 : label is 0; - attribute C_CONFIG_TDATA_WIDTH : integer; - attribute C_CONFIG_TDATA_WIDTH of U0 : label is 1; - attribute C_DATAPATH_MEMTYPE : integer; - attribute C_DATAPATH_MEMTYPE of U0 : label is 0; - attribute C_DATA_HAS_TLAST : integer; - attribute C_DATA_HAS_TLAST of U0 : label is 0; - attribute C_DATA_IP_PATH_WIDTHS : string; - attribute C_DATA_IP_PATH_WIDTHS of U0 : label is "2"; - attribute C_DATA_MEMTYPE : integer; - attribute C_DATA_MEMTYPE of U0 : label is 0; - attribute C_DATA_MEM_PACKING : integer; - attribute C_DATA_MEM_PACKING of U0 : label is 0; - attribute C_DATA_PATH_PSAMP_SRC : string; - attribute C_DATA_PATH_PSAMP_SRC of U0 : label is "0"; - attribute C_DATA_PATH_SIGN : string; - attribute C_DATA_PATH_SIGN of U0 : label is "0"; - attribute C_DATA_PATH_SRC : string; - attribute C_DATA_PATH_SRC of U0 : label is "0"; - attribute C_DATA_PATH_WIDTHS : string; - attribute C_DATA_PATH_WIDTHS of U0 : label is "2"; - attribute C_DATA_PX_PATH_WIDTHS : string; - attribute C_DATA_PX_PATH_WIDTHS of U0 : label is "2"; - attribute C_DATA_WIDTH : integer; - attribute C_DATA_WIDTH of U0 : label is 2; - attribute C_DECIM_RATE : integer; - attribute C_DECIM_RATE of U0 : label is 1; - attribute C_ELABORATION_DIR : string; - attribute C_ELABORATION_DIR of U0 : label is "./"; - attribute C_EXT_MULT_CNFG : string; - attribute C_EXT_MULT_CNFG of U0 : label is "none"; - attribute C_FILTER_TYPE : integer; - attribute C_FILTER_TYPE of U0 : label is 2; - attribute C_FILTS_PACKED : integer; - attribute C_FILTS_PACKED of U0 : label is 0; - attribute C_HAS_ACLKEN : integer; - attribute C_HAS_ACLKEN of U0 : label is 0; - attribute C_HAS_ARESETn : integer; - attribute C_HAS_ARESETn of U0 : label is 0; - attribute C_HAS_CONFIG_CHANNEL : integer; - attribute C_HAS_CONFIG_CHANNEL of U0 : label is 0; - attribute C_INPUT_RATE : integer; - attribute C_INPUT_RATE of U0 : label is 4; - attribute C_INTERP_RATE : integer; - attribute C_INTERP_RATE of U0 : label is 4; - attribute C_IPBUFF_MEMTYPE : integer; - attribute C_IPBUFF_MEMTYPE of U0 : label is 0; - attribute C_LATENCY : integer; - attribute C_LATENCY of U0 : label is 11; - attribute C_MEM_ARRANGEMENT : integer; - attribute C_MEM_ARRANGEMENT of U0 : label is 2; - attribute C_M_DATA_HAS_TREADY : integer; - attribute C_M_DATA_HAS_TREADY of U0 : label is 0; - attribute C_M_DATA_HAS_TUSER : integer; - attribute C_M_DATA_HAS_TUSER of U0 : label is 0; - attribute C_M_DATA_TDATA_WIDTH : integer; - attribute C_M_DATA_TDATA_WIDTH of U0 : label is 16; - attribute C_M_DATA_TUSER_WIDTH : integer; - attribute C_M_DATA_TUSER_WIDTH of U0 : label is 1; - attribute C_NUM_CHANNELS : integer; - attribute C_NUM_CHANNELS of U0 : label is 1; - attribute C_NUM_FILTS : integer; - attribute C_NUM_FILTS of U0 : label is 1; - attribute C_NUM_MADDS : integer; - attribute C_NUM_MADDS of U0 : label is 5; - attribute C_NUM_RELOAD_SLOTS : integer; - attribute C_NUM_RELOAD_SLOTS of U0 : label is 1; - attribute C_NUM_TAPS : integer; - attribute C_NUM_TAPS of U0 : label is 17; - attribute C_OPBUFF_MEMTYPE : integer; - attribute C_OPBUFF_MEMTYPE of U0 : label is 0; - attribute C_OPTIMIZATION : integer; - attribute C_OPTIMIZATION of U0 : label is 0; - attribute C_OPT_MADDS : string; - attribute C_OPT_MADDS of U0 : label is "none"; - attribute C_OP_PATH_PSAMP_SRC : string; - attribute C_OP_PATH_PSAMP_SRC of U0 : label is "0"; - attribute C_OUTPUT_PATH_WIDTHS : string; - attribute C_OUTPUT_PATH_WIDTHS of U0 : label is "15"; - attribute C_OUTPUT_RATE : integer; - attribute C_OUTPUT_RATE of U0 : label is 1; - attribute C_OUTPUT_WIDTH : integer; - attribute C_OUTPUT_WIDTH of U0 : label is 15; - attribute C_OVERSAMPLING_RATE : integer; - attribute C_OVERSAMPLING_RATE of U0 : label is 1; - attribute C_PX_PATH_SRC : string; - attribute C_PX_PATH_SRC of U0 : label is "0"; - attribute C_RELOAD_TDATA_WIDTH : integer; - attribute C_RELOAD_TDATA_WIDTH of U0 : label is 1; - attribute C_ROUND_MODE : integer; - attribute C_ROUND_MODE of U0 : label is 0; - attribute C_SYMMETRY : integer; - attribute C_SYMMETRY of U0 : label is 0; - attribute C_S_DATA_HAS_FIFO : integer; - attribute C_S_DATA_HAS_FIFO of U0 : label is 0; - attribute C_S_DATA_HAS_TUSER : integer; - attribute C_S_DATA_HAS_TUSER of U0 : label is 0; - attribute C_S_DATA_TDATA_WIDTH : integer; - attribute C_S_DATA_TDATA_WIDTH of U0 : label is 8; - attribute C_S_DATA_TUSER_WIDTH : integer; - attribute C_S_DATA_TUSER_WIDTH of U0 : label is 1; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of U0 : label is "kintex7"; - attribute C_ZERO_PACKING_FACTOR : integer; - attribute C_ZERO_PACKING_FACTOR of U0 : label is 1; - attribute downgradeipidentifiedwarnings of U0 : label is "yes"; - attribute x_interface_info : string; - attribute x_interface_info of aclk : signal is "xilinx.com:signal:clock:1.0 aclk_intf CLK"; - attribute x_interface_parameter : string; - attribute x_interface_parameter of aclk : signal is "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0"; - attribute x_interface_info of m_axis_data_tvalid : signal is "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID"; - attribute x_interface_parameter of m_axis_data_tvalid : signal is "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; - attribute x_interface_info of s_axis_data_tready : signal is "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY"; - attribute x_interface_info of s_axis_data_tvalid : signal is "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID"; - attribute x_interface_parameter of s_axis_data_tvalid : signal is "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; - attribute x_interface_info of m_axis_data_tdata : signal is "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA"; - attribute x_interface_info of s_axis_data_tdata : signal is "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA"; -begin -U0: entity work.GaussFir_12m_fir_compiler_v7_2_12 - port map ( - aclk => aclk, - aclken => '1', - aresetn => '1', - event_s_config_tlast_missing => NLW_U0_event_s_config_tlast_missing_UNCONNECTED, - event_s_config_tlast_unexpected => NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED, - event_s_data_chanid_incorrect => NLW_U0_event_s_data_chanid_incorrect_UNCONNECTED, - event_s_data_tlast_missing => NLW_U0_event_s_data_tlast_missing_UNCONNECTED, - event_s_data_tlast_unexpected => NLW_U0_event_s_data_tlast_unexpected_UNCONNECTED, - event_s_reload_tlast_missing => NLW_U0_event_s_reload_tlast_missing_UNCONNECTED, - event_s_reload_tlast_unexpected => NLW_U0_event_s_reload_tlast_unexpected_UNCONNECTED, - m_axis_data_tdata(15 downto 0) => m_axis_data_tdata(15 downto 0), - m_axis_data_tlast => NLW_U0_m_axis_data_tlast_UNCONNECTED, - m_axis_data_tready => '1', - m_axis_data_tuser(0) => NLW_U0_m_axis_data_tuser_UNCONNECTED(0), - m_axis_data_tvalid => m_axis_data_tvalid, - s_axis_config_tdata(0) => '0', - s_axis_config_tlast => '0', - s_axis_config_tready => NLW_U0_s_axis_config_tready_UNCONNECTED, - s_axis_config_tvalid => '0', - s_axis_data_tdata(7 downto 0) => s_axis_data_tdata(7 downto 0), - s_axis_data_tlast => '0', - s_axis_data_tready => s_axis_data_tready, - s_axis_data_tuser(0) => '0', - s_axis_data_tvalid => s_axis_data_tvalid, - s_axis_reload_tdata(0) => '0', - s_axis_reload_tlast => '0', - s_axis_reload_tready => NLW_U0_s_axis_reload_tready_UNCONNECTED, - s_axis_reload_tvalid => '0' - ); -end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.v deleted file mode 100644 index 8d0a664c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.v +++ /dev/null @@ -1,26 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:33:48 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.v -// Design : GaussFir_12m -// Purpose : Stub declaration of top-level module interface -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *) -module GaussFir_12m(aclk, s_axis_data_tvalid, s_axis_data_tready, - s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata) -/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */; - input aclk; - input s_axis_data_tvalid; - output s_axis_data_tready; - input [7:0]s_axis_data_tdata; - output m_axis_data_tvalid; - output [15:0]m_axis_data_tdata; -endmodule diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.vhdl deleted file mode 100644 index 9caf0438..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.vhdl +++ /dev/null @@ -1,35 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:33:48 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.vhdl --- Design : GaussFir_12m --- Purpose : Stub declaration of top-level module interface --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity GaussFir_12m is - Port ( - aclk : in STD_LOGIC; - s_axis_data_tvalid : in STD_LOGIC; - s_axis_data_tready : out STD_LOGIC; - s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); - m_axis_data_tvalid : out STD_LOGIC; - m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ) - ); - -end GaussFir_12m; - -architecture stub of GaussFir_12m is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]"; -attribute x_core_info : string; -attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3"; -begin -end; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_utilization_synth.pb b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_utilization_synth.pb deleted file mode 100644 index 79ccc330..00000000 Binary files a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_utilization_synth.pb and /dev/null differ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_utilization_synth.rpt b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_utilization_synth.rpt deleted file mode 100644 index 885024f1..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_utilization_synth.rpt +++ /dev/null @@ -1,183 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -| Date : Sat Mar 18 23:33:48 2023 -| Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -| Command : report_utilization -file GaussFir_12m_utilization_synth.rpt -pb GaussFir_12m_utilization_synth.pb -| Design : GaussFir_12m -| Device : 7k410tffg900-2 -| Design State : Synthesized -------------------------------------------------------------------------------------------------------------------- - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists - -1. Slice Logic --------------- - -+----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 31 | 0 | 254200 | 0.01 | -| LUT as Logic | 20 | 0 | 254200 | <0.01 | -| LUT as Memory | 11 | 0 | 90600 | 0.01 | -| LUT as Distributed RAM | 0 | 0 | | | -| LUT as Shift Register | 11 | 0 | | | -| Slice Registers | 78 | 0 | 508400 | 0.02 | -| Register as Flip Flop | 78 | 0 | 508400 | 0.02 | -| Register as Latch | 0 | 0 | 508400 | 0.00 | -| F7 Muxes | 0 | 0 | 127100 | 0.00 | -| F8 Muxes | 0 | 0 | 63550 | 0.00 | -+----------------------------+------+-------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 78 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Memory ---------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 795 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 795 | 0.00 | -| RAMB18 | 0 | 0 | 1590 | 0.00 | -+----------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -3. DSP ------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| DSPs | 5 | 0 | 1540 | 0.32 | -| DSP48E1 only | 5 | | | | -+----------------+------+-------+-----------+-------+ - - -4. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 0 | 0 | 500 | 0.00 | -| Bonded IPADs | 0 | 0 | 50 | 0.00 | -| Bonded OPADs | 0 | 0 | 32 | 0.00 | -| PHY_CONTROL | 0 | 0 | 10 | 0.00 | -| PHASER_REF | 0 | 0 | 10 | 0.00 | -| OUT_FIFO | 0 | 0 | 40 | 0.00 | -| IN_FIFO | 0 | 0 | 40 | 0.00 | -| IDELAYCTRL | 0 | 0 | 10 | 0.00 | -| IBUFDS | 0 | 0 | 480 | 0.00 | -| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | -| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 | -| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | -| ILOGIC | 0 | 0 | 500 | 0.00 | -| OLOGIC | 0 | 0 | 500 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -5. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 0 | 0 | 32 | 0.00 | -| BUFIO | 0 | 0 | 40 | 0.00 | -| MMCME2_ADV | 0 | 0 | 10 | 0.00 | -| PLLE2_ADV | 0 | 0 | 10 | 0.00 | -| BUFMRCE | 0 | 0 | 20 | 0.00 | -| BUFHCE | 0 | 0 | 168 | 0.00 | -| BUFR | 0 | 0 | 40 | 0.00 | -+------------+------+-------+-----------+-------+ - - -6. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -7. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| FDRE | 78 | Flop & Latch | -| LUT2 | 21 | LUT | -| SRL16E | 11 | Distributed Memory | -| LUT4 | 6 | LUT | -| DSP48E1 | 5 | Block Arithmetic | -| LUT1 | 3 | LUT | -| LUT3 | 2 | LUT | -| LUT6 | 1 | LUT | -+----------+------+---------------------+ - - -8. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -9. Instantiated Netlists ------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/ISEWrap.js b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/ISEWrap.js deleted file mode 100644 index 97a2ecbc..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/ISEWrap.js +++ /dev/null @@ -1,270 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/ISEWrap.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/ISEWrap.sh deleted file mode 100644 index f679f2e8..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/__synthesis_is_complete__ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/dont_touch.xdc b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/dont_touch.xdc deleted file mode 100644 index 834f01aa..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/dont_touch.xdc +++ /dev/null @@ -1,24 +0,0 @@ -# This file is automatically generated. -# It contains project source information necessary for synthesis and implementation. - -# IP: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/GaussFir_12m.xci -# IP: The module: 'GaussFir_12m' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/constraints/fir_compiler_v7_2.xdc -# XDC: The top module name and the constraint reference have the same name: 'GaussFir_12m'. Do not add the DONT_TOUCH constraint. -set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet - -# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/GaussFir_12m_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'GaussFir_12m'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet - -# IP: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/GaussFir_12m.xci -# IP: The module: 'GaussFir_12m' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/constraints/fir_compiler_v7_2.xdc -# XDC: The top module name and the constraint reference have the same name: 'GaussFir_12m'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet - -# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_12m/GaussFir_12m_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'GaussFir_12m'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/gen_run.xml deleted file mode 100644 index f1a8d638..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/gen_run.xml +++ /dev/null @@ -1,59 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/htr.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/htr.txt deleted file mode 100644 index 0092665c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log GaussFir_12m.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source GaussFir_12m.tcl diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/project.wdf b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/project.wdf deleted file mode 100644 index 9507bcd5..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/project.wdf +++ /dev/null @@ -1,59 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:38:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/rundef.js b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/rundef.js deleted file mode 100644 index 2559312c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/rundef.js +++ /dev/null @@ -1,36 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log GaussFir_12m.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source GaussFir_12m.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/runme.bat b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/runme.bat deleted file mode 100644 index 1760626b..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/runme.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/runme.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/runme.sh deleted file mode 100644 index 736aa09b..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/runme.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin -else - PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log GaussFir_12m.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source GaussFir_12m.tcl diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/vivado.pb b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/vivado.pb deleted file mode 100644 index 1b466ff0..00000000 Binary files a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/vivado.pb and /dev/null differ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/.Vivado_Synthesis.queue.rst b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/.Vivado_Synthesis.queue.rst deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/.vivado.begin.rst b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/.vivado.begin.rst deleted file mode 100644 index 7fabac8f..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/.vivado.end.rst b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/.vivado.end.rst deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5.dcp b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5.dcp deleted file mode 100644 index 2f124ea9..00000000 Binary files a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5.dcp and /dev/null differ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5.tcl b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5.tcl deleted file mode 100644 index 6fb36693..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5.tcl +++ /dev/null @@ -1,157 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param general.maxThreads 20 -set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64 -set_param project.vivado.isBlockSynthRun true -set_msg_config -msgmgr_mode ooc_run -create_project -in_memory -part xc7k410tffg900-2 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] -set_property parent.project_path D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.xpr [current_project] -set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language Verilog [current_project] -set_property ip_output_repo d:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/GaussFir_1mp5.xci -set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/constraints/fir_compiler_v7_2.xdc] -set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/GaussFir_1mp5_ooc.xdc] - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -read_xdc dont_touch.xdc -set_property used_in_implementation false [get_files dont_touch.xdc] -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1 -new_name GaussFir_1mp5 -ip [get_ips GaussFir_1mp5]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top GaussFir_1mp5 -part xc7k410tffg900-2 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix GaussFir_1mp5_ GaussFir_1mp5.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ GaussFir_1mp5_stub.v - lappend ipCachedFiles GaussFir_1mp5_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ GaussFir_1mp5_stub.vhdl - lappend ipCachedFiles GaussFir_1mp5_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ GaussFir_1mp5_sim_netlist.v - lappend ipCachedFiles GaussFir_1mp5_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ GaussFir_1mp5_sim_netlist.vhdl - lappend ipCachedFiles GaussFir_1mp5_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp GaussFir_1mp5.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips GaussFir_1mp5] -} - -rename_ref -prefix_all GaussFir_1mp5_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef GaussFir_1mp5.dcp -create_report "GaussFir_1mp5_synth_1_synth_report_utilization_0" "report_utilization -file GaussFir_1mp5_utilization_synth.rpt -pb GaussFir_1mp5_utilization_synth.pb" - -if { [catch { - write_verilog -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -}; # end if cached_ip - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/GaussFir_1mp5.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/GaussFir_1mp5.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_sim_netlist.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/GaussFir_1mp5.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/GaussFir_1mp5.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5.dcp -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/GaussFir_1mp5.xci] - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/GaussFir_1mp5]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_sim_netlist.v D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/GaussFir_1mp5 - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/GaussFir_1mp5]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_sim_netlist.vhdl D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/GaussFir_1mp5 - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/GaussFir_1mp5]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.v D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/GaussFir_1mp5 - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/GaussFir_1mp5]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.vhdl D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/GaussFir_1mp5 - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5.vds b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5.vds deleted file mode 100644 index 5601c43e..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5.vds +++ /dev/null @@ -1,466 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Sat Mar 18 23:32:54 2023 -# Process ID: 11736 -# Current directory: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1 -# Command line: vivado.exe -log GaussFir_1mp5.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source GaussFir_1mp5.tcl -# Log file: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5.vds -# Journal file: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1\vivado.jou -#----------------------------------------------------------- -Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl' -source GaussFir_1mp5.tcl -notrace -Command: synth_design -top GaussFir_1mp5 -part xc7k410tffg900-2 -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' -INFO: [Device 21-403] Loading part xc7k410tffg900-2 -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 30180 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 884.438 ; gain = 178.086 ---------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'GaussFir_1mp5' [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/synth/GaussFir_1mp5.vhd:70] - Parameter C_XDEVICEFAMILY bound to: kintex7 - type: string - Parameter C_ELABORATION_DIR bound to: ./ - type: string - Parameter C_COMPONENT_NAME bound to: GaussFir_1mp5 - type: string - Parameter C_COEF_FILE bound to: GaussFir_1mp5.mif - type: string - Parameter C_COEF_FILE_LINES bound to: 160 - type: integer - Parameter C_FILTER_TYPE bound to: 2 - type: integer - Parameter C_INTERP_RATE bound to: 32 - type: integer - Parameter C_DECIM_RATE bound to: 1 - type: integer - Parameter C_ZERO_PACKING_FACTOR bound to: 1 - type: integer - Parameter C_SYMMETRY bound to: 0 - type: integer - Parameter C_NUM_FILTS bound to: 1 - type: integer - Parameter C_NUM_TAPS bound to: 129 - type: integer - Parameter C_NUM_CHANNELS bound to: 1 - type: integer - Parameter C_CHANNEL_PATTERN bound to: fixed - type: string - Parameter C_ROUND_MODE bound to: 0 - type: integer - Parameter C_COEF_RELOAD bound to: 0 - type: integer - Parameter C_NUM_RELOAD_SLOTS bound to: 1 - type: integer - Parameter C_COL_MODE bound to: 1 - type: integer - Parameter C_COL_PIPE_LEN bound to: 4 - type: integer - Parameter C_COL_CONFIG bound to: 5 - type: string - Parameter C_OPTIMIZATION bound to: 0 - type: integer - Parameter C_DATA_PATH_WIDTHS bound to: 2 - type: string - Parameter C_DATA_IP_PATH_WIDTHS bound to: 2 - type: string - Parameter C_DATA_PX_PATH_WIDTHS bound to: 2 - type: string - Parameter C_DATA_WIDTH bound to: 2 - type: integer - Parameter C_COEF_PATH_WIDTHS bound to: 14 - type: string - Parameter C_COEF_WIDTH bound to: 14 - type: integer - Parameter C_DATA_PATH_SRC bound to: 0 - type: string - Parameter C_COEF_PATH_SRC bound to: 0 - type: string - Parameter C_PX_PATH_SRC bound to: 0 - type: string - Parameter C_DATA_PATH_SIGN bound to: 0 - type: string - Parameter C_COEF_PATH_SIGN bound to: 1 - type: string - Parameter C_ACCUM_PATH_WIDTHS bound to: 13 - type: string - Parameter C_OUTPUT_WIDTH bound to: 13 - type: integer - Parameter C_OUTPUT_PATH_WIDTHS bound to: 13 - type: string - Parameter C_ACCUM_OP_PATH_WIDTHS bound to: 13 - type: string - Parameter C_EXT_MULT_CNFG bound to: none - type: string - Parameter C_DATA_PATH_PSAMP_SRC bound to: 0 - type: string - Parameter C_OP_PATH_PSAMP_SRC bound to: 0 - type: string - Parameter C_NUM_MADDS bound to: 5 - type: integer - Parameter C_OPT_MADDS bound to: none - type: string - Parameter C_OVERSAMPLING_RATE bound to: 1 - type: integer - Parameter C_INPUT_RATE bound to: 32 - type: integer - Parameter C_OUTPUT_RATE bound to: 1 - type: integer - Parameter C_DATA_MEMTYPE bound to: 0 - type: integer - Parameter C_COEF_MEMTYPE bound to: 2 - type: integer - Parameter C_IPBUFF_MEMTYPE bound to: 0 - type: integer - Parameter C_OPBUFF_MEMTYPE bound to: 0 - type: integer - Parameter C_DATAPATH_MEMTYPE bound to: 0 - type: integer - Parameter C_MEM_ARRANGEMENT bound to: 2 - type: integer - Parameter C_DATA_MEM_PACKING bound to: 0 - type: integer - Parameter C_COEF_MEM_PACKING bound to: 0 - type: integer - Parameter C_FILTS_PACKED bound to: 0 - type: integer - Parameter C_LATENCY bound to: 11 - type: integer - Parameter C_HAS_ARESETn bound to: 0 - type: integer - Parameter C_HAS_ACLKEN bound to: 0 - type: integer - Parameter C_DATA_HAS_TLAST bound to: 0 - type: integer - Parameter C_S_DATA_HAS_FIFO bound to: 0 - type: integer - Parameter C_S_DATA_HAS_TUSER bound to: 0 - type: integer - Parameter C_S_DATA_TDATA_WIDTH bound to: 8 - type: integer - Parameter C_S_DATA_TUSER_WIDTH bound to: 1 - type: integer - Parameter C_M_DATA_HAS_TREADY bound to: 0 - type: integer - Parameter C_M_DATA_HAS_TUSER bound to: 0 - type: integer - Parameter C_M_DATA_TDATA_WIDTH bound to: 16 - type: integer - Parameter C_M_DATA_TUSER_WIDTH bound to: 1 - type: integer - Parameter C_HAS_CONFIG_CHANNEL bound to: 0 - type: integer - Parameter C_CONFIG_SYNC_MODE bound to: 0 - type: integer - Parameter C_CONFIG_PACKET_SIZE bound to: 0 - type: integer - Parameter C_CONFIG_TDATA_WIDTH bound to: 1 - type: integer - Parameter C_RELOAD_TDATA_WIDTH bound to: 1 - type: integer -INFO: [Synth 8-3491] module 'fir_compiler_v7_2_12' declared at 'd:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/hdl/fir_compiler_v7_2_vh_rfs.vhd:61264' bound to instance 'U0' of component 'fir_compiler_v7_2_12' [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/synth/GaussFir_1mp5.vhd:198] -WARNING: [Synth 8-5858] RAM p_casc_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers -WARNING: [Synth 8-5858] RAM p_path_out_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers -INFO: [Synth 8-256] done synthesizing module 'GaussFir_1mp5' (11#1) [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/synth/GaussFir_1mp5.vhd:70] -WARNING: [Synth 8-3331] design delay__parameterized3 has unconnected port SCLR -WARNING: [Synth 8-3331] design delay__parameterized3 has unconnected port SCLR_ALT -WARNING: [Synth 8-3331] design buff has unconnected port RE -WARNING: [Synth 8-3331] design buff has unconnected port SCLR -WARNING: [Synth 8-3331] design delay__parameterized6 has unconnected port WE -WARNING: [Synth 8-3331] design delay__parameterized6 has unconnected port CE -WARNING: [Synth 8-3331] design delay__parameterized6 has unconnected port SCLR -WARNING: [Synth 8-3331] design delay__parameterized6 has unconnected port SCLR_ALT -WARNING: [Synth 8-3331] design delay__parameterized6 has unconnected port CLK -WARNING: [Synth 8-3331] design delay__parameterized5 has unconnected port WE -WARNING: [Synth 8-3331] design delay__parameterized5 has unconnected port CE -WARNING: [Synth 8-3331] design delay__parameterized5 has unconnected port SCLR -WARNING: [Synth 8-3331] design delay__parameterized5 has unconnected port SCLR_ALT -WARNING: [Synth 8-3331] design delay__parameterized5 has unconnected port CLK -WARNING: [Synth 8-3331] design calc has unconnected port PRE_ADDSUB -WARNING: [Synth 8-3331] design calc has unconnected port PRE_ADD_BYPASS -WARNING: [Synth 8-3331] design calc has unconnected port CED -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[fab][57] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[fab][56] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[fab][55] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[fab][54] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[fab][53] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[fab][52] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[fab][51] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[fab][50] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[fab][49] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[fab][48] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][62] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][61] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][60] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][59] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][58] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][57] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][56] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][55] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][54] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][53] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][52] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][51] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][50] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][49] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port POUT[casc][48] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port P_EN -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port OPCODE[9] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port OPCODE[8] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port OPCODE[7] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port OPCODE[6] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port OPCODE[5] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port OPCODE[4] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port OPCODE[3] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port OPCODE[2] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port OPCODE[1] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port OPCODE[0] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][57] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][56] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][55] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][54] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][53] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][52] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][51] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][50] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][49] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][48] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][47] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][46] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][45] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][44] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][43] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][42] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][41] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][40] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][39] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][38] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][37] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][36] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][35] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][34] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][33] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][32] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][31] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][30] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][29] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][28] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][27] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][26] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][25] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][24] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][23] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][22] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][21] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][20] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][19] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][18] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][17] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][16] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][15] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][14] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][13] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][12] -WARNING: [Synth 8-3331] design addsub_mult_add__parameterized0 has unconnected port PIN[fab][11] -INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1013.465 ; gain = 307.113 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1013.465 ; gain = 307.113 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1013.465 ; gain = 307.113 ---------------------------------------------------------------------------------- -INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization - -Processing XDC Constraints -Initializing timing engine -Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/GaussFir_1mp5_ooc.xdc] for cell 'U0' -Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/GaussFir_1mp5_ooc.xdc] for cell 'U0' -Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/constraints/fir_compiler_v7_2.xdc] for cell 'U0' -Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/constraints/fir_compiler_v7_2.xdc] for cell 'U0' -Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/dont_touch.xdc] -Finished Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/dont_touch.xdc] -Completed Processing XDC Constraints - -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1035.562 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1038.590 ; gain = 3.027 ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1038.590 ; gain = 332.238 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7k410tffg900-2 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1038.590 ; gain = 332.238 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying 'set_property' XDC Constraints ---------------------------------------------------------------------------------- -Applied set_property DONT_TOUCH = true for U0. (constraint file D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/dont_touch.xdc, line 9). ---------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1038.590 ; gain = 332.238 ---------------------------------------------------------------------------------- -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1038.590 ; gain = 332.238 ---------------------------------------------------------------------------------- -INFO: [Synth 8-223] decloning instance 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.i_cntrl_buff_sclr' (delay__parameterized2) to 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.i_cntrl_sym_buff_sclr' - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 1540 (col length:140) -BRAMs: 1590 (col length: RAMB18 140 RAMB36 70) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_paths[0].g_mem_array[0].i_mem/g_individual.i_mem_a /\gen_dram.gen_rom.d_out_reg[7] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_paths[0].g_mem_array[0].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[10] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_paths[0].g_mem_array[1].i_mem/g_individual.i_mem_a /\gen_dram.gen_rom.d_out_reg[10] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_paths[0].g_mem_array[1].i_mem/g_individual.g_mem_b.i_mem_b /\gen_dram.gen_rom.d_out_reg[8] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_paths[0].g_mem_array[2].i_mem/g_individual.i_mem_a /\gen_dram.gen_rom.d_out_reg[0] ) -INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[12]' (FDRE) to 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[13]' (FDRE) to 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[14]' (FDRE) to 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[15]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tlast_int_reg ) ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1038.590 ; gain = 332.238 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Applying XDC Timing Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 1093.180 ; gain = 386.828 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 1093.848 ; gain = 387.496 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 1103.957 ; gain = 397.605 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 1119.719 ; gain = 413.367 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 1119.719 ; gain = 413.367 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 1119.719 ; gain = 413.367 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 1119.719 ; gain = 413.367 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 1119.719 ; gain = 413.367 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:30 ; elapsed = 00:00:37 . Memory (MB): peak = 1119.719 ; gain = 413.367 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+--------+------+ -| |Cell |Count | -+------+--------+------+ -|1 |DSP48E1 | 5| -|2 |LUT1 | 1| -|3 |LUT2 | 3| -|4 |LUT3 | 3| -|5 |LUT4 | 10| -|6 |LUT5 | 32| -|7 |LUT6 | 3| -|8 |SRL16E | 11| -|9 |FDRE | 97| -+------+--------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:30 ; elapsed = 00:00:37 . Memory (MB): peak = 1119.719 ; gain = 413.367 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 97 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:33 . Memory (MB): peak = 1119.719 ; gain = 388.242 -Synthesis Optimization Complete : Time (s): cpu = 00:00:30 ; elapsed = 00:00:37 . Memory (MB): peak = 1119.719 ; gain = 413.367 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1119.719 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -37 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:45 . Memory (MB): peak = 1119.719 ; gain = 732.074 -INFO: [Common 17-600] The following parameters have non-default value. -general.maxThreads -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1119.719 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5.dcp' has been generated. -WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP GaussFir_1mp5, cache-ID = 3ca8fc11c8cf2c6f -INFO: [Coretcl 2-1174] Renamed 30 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1119.719 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file GaussFir_1mp5_utilization_synth.rpt -pb GaussFir_1mp5_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sat Mar 18 23:33:48 2023... diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_sim_netlist.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_sim_netlist.v deleted file mode 100644 index e0b32bda..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_sim_netlist.v +++ /dev/null @@ -1,2607 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:33:47 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_sim_netlist.v -// Design : GaussFir_1mp5 -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* CHECK_LICENSE_TYPE = "GaussFir_1mp5,fir_compiler_v7_2_12,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *) -(* NotValidForBitStream *) -module GaussFir_1mp5 - (aclk, - s_axis_data_tvalid, - s_axis_data_tready, - s_axis_data_tdata, - m_axis_data_tvalid, - m_axis_data_tdata); - (* x_interface_info = "xilinx.com:signal:clock:1.0 aclk_intf CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *) input aclk; - (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) input s_axis_data_tvalid; - (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY" *) output s_axis_data_tready; - (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA" *) input [7:0]s_axis_data_tdata; - (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) output m_axis_data_tvalid; - (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA" *) output [15:0]m_axis_data_tdata; - - wire aclk; - wire [15:0]m_axis_data_tdata; - wire m_axis_data_tvalid; - wire [7:0]s_axis_data_tdata; - wire s_axis_data_tready; - wire s_axis_data_tvalid; - wire NLW_U0_event_s_config_tlast_missing_UNCONNECTED; - wire NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED; - wire NLW_U0_event_s_data_chanid_incorrect_UNCONNECTED; - wire NLW_U0_event_s_data_tlast_missing_UNCONNECTED; - wire NLW_U0_event_s_data_tlast_unexpected_UNCONNECTED; - wire NLW_U0_event_s_reload_tlast_missing_UNCONNECTED; - wire NLW_U0_event_s_reload_tlast_unexpected_UNCONNECTED; - wire NLW_U0_m_axis_data_tlast_UNCONNECTED; - wire NLW_U0_s_axis_config_tready_UNCONNECTED; - wire NLW_U0_s_axis_reload_tready_UNCONNECTED; - wire [0:0]NLW_U0_m_axis_data_tuser_UNCONNECTED; - - (* C_ACCUM_OP_PATH_WIDTHS = "13" *) - (* C_ACCUM_PATH_WIDTHS = "13" *) - (* C_CHANNEL_PATTERN = "fixed" *) - (* C_COEF_FILE = "GaussFir_1mp5.mif" *) - (* C_COEF_FILE_LINES = "160" *) - (* C_COEF_MEMTYPE = "2" *) - (* C_COEF_MEM_PACKING = "0" *) - (* C_COEF_PATH_SIGN = "1" *) - (* C_COEF_PATH_SRC = "0" *) - (* C_COEF_PATH_WIDTHS = "14" *) - (* C_COEF_RELOAD = "0" *) - (* C_COEF_WIDTH = "14" *) - (* C_COL_CONFIG = "5" *) - (* C_COL_MODE = "1" *) - (* C_COL_PIPE_LEN = "4" *) - (* C_COMPONENT_NAME = "GaussFir_1mp5" *) - (* C_CONFIG_PACKET_SIZE = "0" *) - (* C_CONFIG_SYNC_MODE = "0" *) - (* C_CONFIG_TDATA_WIDTH = "1" *) - (* C_DATAPATH_MEMTYPE = "0" *) - (* C_DATA_HAS_TLAST = "0" *) - (* C_DATA_IP_PATH_WIDTHS = "2" *) - (* C_DATA_MEMTYPE = "0" *) - (* C_DATA_MEM_PACKING = "0" *) - (* C_DATA_PATH_PSAMP_SRC = "0" *) - (* C_DATA_PATH_SIGN = "0" *) - (* C_DATA_PATH_SRC = "0" *) - (* C_DATA_PATH_WIDTHS = "2" *) - (* C_DATA_PX_PATH_WIDTHS = "2" *) - (* C_DATA_WIDTH = "2" *) - (* C_DECIM_RATE = "1" *) - (* C_ELABORATION_DIR = "./" *) - (* C_EXT_MULT_CNFG = "none" *) - (* C_FILTER_TYPE = "2" *) - (* C_FILTS_PACKED = "0" *) - (* C_HAS_ACLKEN = "0" *) - (* C_HAS_ARESETn = "0" *) - (* C_HAS_CONFIG_CHANNEL = "0" *) - (* C_INPUT_RATE = "32" *) - (* C_INTERP_RATE = "32" *) - (* C_IPBUFF_MEMTYPE = "0" *) - (* C_LATENCY = "11" *) - (* C_MEM_ARRANGEMENT = "2" *) - (* C_M_DATA_HAS_TREADY = "0" *) - (* C_M_DATA_HAS_TUSER = "0" *) - (* C_M_DATA_TDATA_WIDTH = "16" *) - (* C_M_DATA_TUSER_WIDTH = "1" *) - (* C_NUM_CHANNELS = "1" *) - (* C_NUM_FILTS = "1" *) - (* C_NUM_MADDS = "5" *) - (* C_NUM_RELOAD_SLOTS = "1" *) - (* C_NUM_TAPS = "129" *) - (* C_OPBUFF_MEMTYPE = "0" *) - (* C_OPTIMIZATION = "0" *) - (* C_OPT_MADDS = "none" *) - (* C_OP_PATH_PSAMP_SRC = "0" *) - (* C_OUTPUT_PATH_WIDTHS = "13" *) - (* C_OUTPUT_RATE = "1" *) - (* C_OUTPUT_WIDTH = "13" *) - (* C_OVERSAMPLING_RATE = "1" *) - (* C_PX_PATH_SRC = "0" *) - (* C_RELOAD_TDATA_WIDTH = "1" *) - (* C_ROUND_MODE = "0" *) - (* C_SYMMETRY = "0" *) - (* C_S_DATA_HAS_FIFO = "0" *) - (* C_S_DATA_HAS_TUSER = "0" *) - (* C_S_DATA_TDATA_WIDTH = "8" *) - (* C_S_DATA_TUSER_WIDTH = "1" *) - (* C_XDEVICEFAMILY = "kintex7" *) - (* C_ZERO_PACKING_FACTOR = "1" *) - (* downgradeipidentifiedwarnings = "yes" *) - GaussFir_1mp5_fir_compiler_v7_2_12 U0 - (.aclk(aclk), - .aclken(1'b1), - .aresetn(1'b1), - .event_s_config_tlast_missing(NLW_U0_event_s_config_tlast_missing_UNCONNECTED), - .event_s_config_tlast_unexpected(NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED), - .event_s_data_chanid_incorrect(NLW_U0_event_s_data_chanid_incorrect_UNCONNECTED), - .event_s_data_tlast_missing(NLW_U0_event_s_data_tlast_missing_UNCONNECTED), - .event_s_data_tlast_unexpected(NLW_U0_event_s_data_tlast_unexpected_UNCONNECTED), - .event_s_reload_tlast_missing(NLW_U0_event_s_reload_tlast_missing_UNCONNECTED), - .event_s_reload_tlast_unexpected(NLW_U0_event_s_reload_tlast_unexpected_UNCONNECTED), - .m_axis_data_tdata(m_axis_data_tdata), - .m_axis_data_tlast(NLW_U0_m_axis_data_tlast_UNCONNECTED), - .m_axis_data_tready(1'b1), - .m_axis_data_tuser(NLW_U0_m_axis_data_tuser_UNCONNECTED[0]), - .m_axis_data_tvalid(m_axis_data_tvalid), - .s_axis_config_tdata(1'b0), - .s_axis_config_tlast(1'b0), - .s_axis_config_tready(NLW_U0_s_axis_config_tready_UNCONNECTED), - .s_axis_config_tvalid(1'b0), - .s_axis_data_tdata(s_axis_data_tdata), - .s_axis_data_tlast(1'b0), - .s_axis_data_tready(s_axis_data_tready), - .s_axis_data_tuser(1'b0), - .s_axis_data_tvalid(s_axis_data_tvalid), - .s_axis_reload_tdata(1'b0), - .s_axis_reload_tlast(1'b0), - .s_axis_reload_tready(NLW_U0_s_axis_reload_tready_UNCONNECTED), - .s_axis_reload_tvalid(1'b0)); -endmodule - -(* C_ACCUM_OP_PATH_WIDTHS = "13" *) (* C_ACCUM_PATH_WIDTHS = "13" *) (* C_CHANNEL_PATTERN = "fixed" *) -(* C_COEF_FILE = "GaussFir_1mp5.mif" *) (* C_COEF_FILE_LINES = "160" *) (* C_COEF_MEMTYPE = "2" *) -(* C_COEF_MEM_PACKING = "0" *) (* C_COEF_PATH_SIGN = "1" *) (* C_COEF_PATH_SRC = "0" *) -(* C_COEF_PATH_WIDTHS = "14" *) (* C_COEF_RELOAD = "0" *) (* C_COEF_WIDTH = "14" *) -(* C_COL_CONFIG = "5" *) (* C_COL_MODE = "1" *) (* C_COL_PIPE_LEN = "4" *) -(* C_COMPONENT_NAME = "GaussFir_1mp5" *) (* C_CONFIG_PACKET_SIZE = "0" *) (* C_CONFIG_SYNC_MODE = "0" *) -(* C_CONFIG_TDATA_WIDTH = "1" *) (* C_DATAPATH_MEMTYPE = "0" *) (* C_DATA_HAS_TLAST = "0" *) -(* C_DATA_IP_PATH_WIDTHS = "2" *) (* C_DATA_MEMTYPE = "0" *) (* C_DATA_MEM_PACKING = "0" *) -(* C_DATA_PATH_PSAMP_SRC = "0" *) (* C_DATA_PATH_SIGN = "0" *) (* C_DATA_PATH_SRC = "0" *) -(* C_DATA_PATH_WIDTHS = "2" *) (* C_DATA_PX_PATH_WIDTHS = "2" *) (* C_DATA_WIDTH = "2" *) -(* C_DECIM_RATE = "1" *) (* C_ELABORATION_DIR = "./" *) (* C_EXT_MULT_CNFG = "none" *) -(* C_FILTER_TYPE = "2" *) (* C_FILTS_PACKED = "0" *) (* C_HAS_ACLKEN = "0" *) -(* C_HAS_ARESETn = "0" *) (* C_HAS_CONFIG_CHANNEL = "0" *) (* C_INPUT_RATE = "32" *) -(* C_INTERP_RATE = "32" *) (* C_IPBUFF_MEMTYPE = "0" *) (* C_LATENCY = "11" *) -(* C_MEM_ARRANGEMENT = "2" *) (* C_M_DATA_HAS_TREADY = "0" *) (* C_M_DATA_HAS_TUSER = "0" *) -(* C_M_DATA_TDATA_WIDTH = "16" *) (* C_M_DATA_TUSER_WIDTH = "1" *) (* C_NUM_CHANNELS = "1" *) -(* C_NUM_FILTS = "1" *) (* C_NUM_MADDS = "5" *) (* C_NUM_RELOAD_SLOTS = "1" *) -(* C_NUM_TAPS = "129" *) (* C_OPBUFF_MEMTYPE = "0" *) (* C_OPTIMIZATION = "0" *) -(* C_OPT_MADDS = "none" *) (* C_OP_PATH_PSAMP_SRC = "0" *) (* C_OUTPUT_PATH_WIDTHS = "13" *) -(* C_OUTPUT_RATE = "1" *) (* C_OUTPUT_WIDTH = "13" *) (* C_OVERSAMPLING_RATE = "1" *) -(* C_PX_PATH_SRC = "0" *) (* C_RELOAD_TDATA_WIDTH = "1" *) (* C_ROUND_MODE = "0" *) -(* C_SYMMETRY = "0" *) (* C_S_DATA_HAS_FIFO = "0" *) (* C_S_DATA_HAS_TUSER = "0" *) -(* C_S_DATA_TDATA_WIDTH = "8" *) (* C_S_DATA_TUSER_WIDTH = "1" *) (* C_XDEVICEFAMILY = "kintex7" *) -(* C_ZERO_PACKING_FACTOR = "1" *) (* ORIG_REF_NAME = "fir_compiler_v7_2_12" *) (* downgradeipidentifiedwarnings = "yes" *) -module GaussFir_1mp5_fir_compiler_v7_2_12 - (aresetn, - aclk, - aclken, - s_axis_data_tvalid, - s_axis_data_tready, - s_axis_data_tlast, - s_axis_data_tuser, - s_axis_data_tdata, - s_axis_config_tvalid, - s_axis_config_tready, - s_axis_config_tlast, - s_axis_config_tdata, - s_axis_reload_tvalid, - s_axis_reload_tready, - s_axis_reload_tlast, - s_axis_reload_tdata, - m_axis_data_tvalid, - m_axis_data_tready, - m_axis_data_tlast, - m_axis_data_tuser, - m_axis_data_tdata, - event_s_data_tlast_missing, - event_s_data_tlast_unexpected, - event_s_data_chanid_incorrect, - event_s_config_tlast_missing, - event_s_config_tlast_unexpected, - event_s_reload_tlast_missing, - event_s_reload_tlast_unexpected); - input aresetn; - input aclk; - input aclken; - input s_axis_data_tvalid; - output s_axis_data_tready; - input s_axis_data_tlast; - input [0:0]s_axis_data_tuser; - input [7:0]s_axis_data_tdata; - input s_axis_config_tvalid; - output s_axis_config_tready; - input s_axis_config_tlast; - input [0:0]s_axis_config_tdata; - input s_axis_reload_tvalid; - output s_axis_reload_tready; - input s_axis_reload_tlast; - input [0:0]s_axis_reload_tdata; - output m_axis_data_tvalid; - input m_axis_data_tready; - output m_axis_data_tlast; - output [0:0]m_axis_data_tuser; - output [15:0]m_axis_data_tdata; - output event_s_data_tlast_missing; - output event_s_data_tlast_unexpected; - output event_s_data_chanid_incorrect; - output event_s_config_tlast_missing; - output event_s_config_tlast_unexpected; - output event_s_reload_tlast_missing; - output event_s_reload_tlast_unexpected; - - wire \ ; - wire aclk; - wire [12:0]\^m_axis_data_tdata ; - wire m_axis_data_tvalid; - wire [7:0]s_axis_data_tdata; - wire s_axis_data_tready; - wire s_axis_data_tvalid; - wire NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED; - wire NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED; - wire NLW_i_synth_event_s_data_chanid_incorrect_UNCONNECTED; - wire NLW_i_synth_event_s_data_tlast_missing_UNCONNECTED; - wire NLW_i_synth_event_s_data_tlast_unexpected_UNCONNECTED; - wire NLW_i_synth_event_s_reload_tlast_missing_UNCONNECTED; - wire NLW_i_synth_event_s_reload_tlast_unexpected_UNCONNECTED; - wire NLW_i_synth_m_axis_data_tlast_UNCONNECTED; - wire NLW_i_synth_s_axis_config_tready_UNCONNECTED; - wire NLW_i_synth_s_axis_reload_tready_UNCONNECTED; - wire [14:12]NLW_i_synth_m_axis_data_tdata_UNCONNECTED; - wire [0:0]NLW_i_synth_m_axis_data_tuser_UNCONNECTED; - - assign event_s_config_tlast_missing = \ ; - assign event_s_config_tlast_unexpected = \ ; - assign event_s_data_chanid_incorrect = \ ; - assign event_s_data_tlast_missing = \ ; - assign event_s_data_tlast_unexpected = \ ; - assign event_s_reload_tlast_missing = \ ; - assign event_s_reload_tlast_unexpected = \ ; - assign m_axis_data_tdata[15] = \^m_axis_data_tdata [12]; - assign m_axis_data_tdata[14] = \^m_axis_data_tdata [12]; - assign m_axis_data_tdata[13] = \^m_axis_data_tdata [12]; - assign m_axis_data_tdata[12:0] = \^m_axis_data_tdata [12:0]; - assign m_axis_data_tlast = \ ; - assign m_axis_data_tuser[0] = \ ; - assign s_axis_config_tready = \ ; - assign s_axis_reload_tready = \ ; - GND GND - (.G(\ )); - (* C_ACCUM_OP_PATH_WIDTHS = "13" *) - (* C_ACCUM_PATH_WIDTHS = "13" *) - (* C_CHANNEL_PATTERN = "fixed" *) - (* C_COEF_FILE = "GaussFir_1mp5.mif" *) - (* C_COEF_FILE_LINES = "160" *) - (* C_COEF_MEMTYPE = "2" *) - (* C_COEF_MEM_PACKING = "0" *) - (* C_COEF_PATH_SIGN = "1" *) - (* C_COEF_PATH_SRC = "0" *) - (* C_COEF_PATH_WIDTHS = "14" *) - (* C_COEF_RELOAD = "0" *) - (* C_COEF_WIDTH = "14" *) - (* C_COL_CONFIG = "5" *) - (* C_COL_MODE = "1" *) - (* C_COL_PIPE_LEN = "4" *) - (* C_COMPONENT_NAME = "GaussFir_1mp5" *) - (* C_CONFIG_PACKET_SIZE = "0" *) - (* C_CONFIG_SYNC_MODE = "0" *) - (* C_CONFIG_TDATA_WIDTH = "1" *) - (* C_DATAPATH_MEMTYPE = "0" *) - (* C_DATA_HAS_TLAST = "0" *) - (* C_DATA_IP_PATH_WIDTHS = "2" *) - (* C_DATA_MEMTYPE = "0" *) - (* C_DATA_MEM_PACKING = "0" *) - (* C_DATA_PATH_PSAMP_SRC = "0" *) - (* C_DATA_PATH_SIGN = "0" *) - (* C_DATA_PATH_SRC = "0" *) - (* C_DATA_PATH_WIDTHS = "2" *) - (* C_DATA_PX_PATH_WIDTHS = "2" *) - (* C_DATA_WIDTH = "2" *) - (* C_DECIM_RATE = "1" *) - (* C_ELABORATION_DIR = "./" *) - (* C_EXT_MULT_CNFG = "none" *) - (* C_FILTER_TYPE = "2" *) - (* C_FILTS_PACKED = "0" *) - (* C_HAS_ACLKEN = "0" *) - (* C_HAS_ARESETn = "0" *) - (* C_HAS_CONFIG_CHANNEL = "0" *) - (* C_INPUT_RATE = "32" *) - (* C_INTERP_RATE = "32" *) - (* C_IPBUFF_MEMTYPE = "0" *) - (* C_LATENCY = "11" *) - (* C_MEM_ARRANGEMENT = "2" *) - (* C_M_DATA_HAS_TREADY = "0" *) - (* C_M_DATA_HAS_TUSER = "0" *) - (* C_M_DATA_TDATA_WIDTH = "16" *) - (* C_M_DATA_TUSER_WIDTH = "1" *) - (* C_NUM_CHANNELS = "1" *) - (* C_NUM_FILTS = "1" *) - (* C_NUM_MADDS = "5" *) - (* C_NUM_RELOAD_SLOTS = "1" *) - (* C_NUM_TAPS = "129" *) - (* C_OPBUFF_MEMTYPE = "0" *) - (* C_OPTIMIZATION = "0" *) - (* C_OPT_MADDS = "none" *) - (* C_OP_PATH_PSAMP_SRC = "0" *) - (* C_OUTPUT_PATH_WIDTHS = "13" *) - (* C_OUTPUT_RATE = "1" *) - (* C_OUTPUT_WIDTH = "13" *) - (* C_OVERSAMPLING_RATE = "1" *) - (* C_PX_PATH_SRC = "0" *) - (* C_RELOAD_TDATA_WIDTH = "1" *) - (* C_ROUND_MODE = "0" *) - (* C_SYMMETRY = "0" *) - (* C_S_DATA_HAS_FIFO = "0" *) - (* C_S_DATA_HAS_TUSER = "0" *) - (* C_S_DATA_TDATA_WIDTH = "8" *) - (* C_S_DATA_TUSER_WIDTH = "1" *) - (* C_XDEVICEFAMILY = "kintex7" *) - (* C_ZERO_PACKING_FACTOR = "1" *) - (* downgradeipidentifiedwarnings = "yes" *) - GaussFir_1mp5_fir_compiler_v7_2_12_viv i_synth - (.aclk(aclk), - .aclken(1'b0), - .aresetn(1'b0), - .event_s_config_tlast_missing(NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED), - .event_s_config_tlast_unexpected(NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED), - .event_s_data_chanid_incorrect(NLW_i_synth_event_s_data_chanid_incorrect_UNCONNECTED), - .event_s_data_tlast_missing(NLW_i_synth_event_s_data_tlast_missing_UNCONNECTED), - .event_s_data_tlast_unexpected(NLW_i_synth_event_s_data_tlast_unexpected_UNCONNECTED), - .event_s_reload_tlast_missing(NLW_i_synth_event_s_reload_tlast_missing_UNCONNECTED), - .event_s_reload_tlast_unexpected(NLW_i_synth_event_s_reload_tlast_unexpected_UNCONNECTED), - .m_axis_data_tdata({\^m_axis_data_tdata [12],NLW_i_synth_m_axis_data_tdata_UNCONNECTED[14:12],\^m_axis_data_tdata [11:0]}), - .m_axis_data_tlast(NLW_i_synth_m_axis_data_tlast_UNCONNECTED), - .m_axis_data_tready(1'b0), - .m_axis_data_tuser(NLW_i_synth_m_axis_data_tuser_UNCONNECTED[0]), - .m_axis_data_tvalid(m_axis_data_tvalid), - .s_axis_config_tdata(1'b0), - .s_axis_config_tlast(1'b0), - .s_axis_config_tready(NLW_i_synth_s_axis_config_tready_UNCONNECTED), - .s_axis_config_tvalid(1'b0), - .s_axis_data_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,s_axis_data_tdata[1:0]}), - .s_axis_data_tlast(1'b0), - .s_axis_data_tready(s_axis_data_tready), - .s_axis_data_tuser(1'b0), - .s_axis_data_tvalid(s_axis_data_tvalid), - .s_axis_reload_tdata(1'b0), - .s_axis_reload_tlast(1'b0), - .s_axis_reload_tready(NLW_i_synth_s_axis_reload_tready_UNCONNECTED), - .s_axis_reload_tvalid(1'b0)); -endmodule -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "XILINX" -`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" -`pragma protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=64) -`pragma protect key_block -I5jBxSA30qMppesbkWzApATD001KfSyiO/EXeiSfqG/mDp7bWT98b6O2aLKwO2KBiQHns7D4kNzR -1vJ+KztHDg== - -`pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128) -`pragma protect key_block -WMu7kFTLnidedbfVrZuh/7ca7CUttjqfOqFAqALtw+gkp4fPh7ZCC2c3FriF2MGJNdt0inCBZQ1w -ERGO+2E2lzKAF62aWczdna33VjhJbQEhVD66TE3XkcNa3kH5qqUhb+EgT0e6ErzcmqjyjnkFxoKK -XKvbLV/yC8Myvjbgd1A= - -`pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`pragma protect key_block -xD5n0VbWIE6P1VxF0RmDDu2TYD4jh2LNu0PcTQhqBRKitH0v3xG4GrD/vuHfz6qhNoYV25YBOEWi -7kVjcZSXNFtC5ITuwneS2ZMRryiXpM8fFiU2j9L4eELr2/mHrJrVvacPISdaWzzVZMaXZGjjLF31 -zK98DBrt3GchBNvrcOgQmuPVAvjrSEZ+P+LhtLFVfq/zmFgYzV3AELJD6jr7elUkLyTjsJWEFYcf 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-qjVnO38YwcIpkFA3hdVylOufwvfkyXzLnO4I/oXAmiPI3b+yEyPArGvVOGpDgyd07VUs/V9x8yNF -fJU+AQwpZcLwvczmvjIU4/eR8fdXCMBV/C6JW2N+CHrwTU69ne3XstJaVfOIPupKIpZjLVLIrAYs -UQMdOWUz5FDENYd645Oho01vEbgtbLb+GrcpRedjCAIY2LgO42kQ9rDb7oVFFsUuoIPnWF4fLEjb -Pq5mb00fUdX1TzSueiRRmMIn69wkk/QkSb8jag== - -`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128) -`pragma protect key_block -S5Ng9U2ICFR2ATladKVkI9g1B4mI1wuXRMAnMNgbxvoijFO8db10A3+6fvjuey2Yzxp1Hf4dZcYN -c/lBn1GB/WXkp/IAC1a0hNWcvyknzHaPnT0XXAr2t5Xncs67wJ8pN5Gp2D1qrZQQzDnNoYG2S/bd -YiWvkcmY78GRhm+UXVk= - -`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`pragma protect key_block -HAhvjf08asX78hSz5fysjZpqt6weT/hM0aPw+9OZ6ZFgT2U7lNg0+xRLXb9nzh4EewIjMgSyWdbq -Irle9J+zY0NjMxQhF0AU4uZR3mjfrD6Ci+uFgn2FssxWd9BHXv/cqiRhCZU2ybiUWpzjYSU0dR0h -2hg5PlS+G3dlVbHVWfTO0k/13GXvSnwpugvkHI9jnHi2x1XT0gcm6G9Zhe1EI5PttaiCD/hIEpFy -dE9D4GBdwkisk7PYdWIuZlsBFWDWcbGou0FPnNgoQxkmsqJf2be0EcDmDksiH0SWYeS3S/ePy+eL -24oKZ31y2jK7rq17ZMr87dpRzRIdMsvbgjgGWg== - -`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`pragma protect key_block -btcBLREoCU/igGR/QFOar7vvya26XxuB61KkppFlAnzkpounYMRvjpm5+k2yevW8k8PzuO2wEhwB -YUCAVsZC61Nq+VX4UqTu37l4HqpxIovFYOO6bcEdNknZKXV6s+/Ett+dHIX8nSkTikn2kxLbKoX4 -CTbNAt73HqotRTGnfjZSAzuwDXVyogmGh3OssJmjM8W2P0I4QfLI45P34Z4m20KM7RzIRcRrtOao -BLSuYEPx0SbzpaYwG/0uEpvZnziP8WhXxmMzxW5IYyb2yYEfjL9oRdxLoaxPnctV7ZcepoPkDekr -8Crn30yBHu2Xj5jUQK2eK0SHGKr+nud/oi89YA== - -`pragma protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa" -`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`pragma protect key_block -QOyk7aC5metmmMN1Vds1Mf8Gz+7qVWxdcITqDim4CJPbeb/KjUKbN5plGxhlhv59TDcnTdt4wfam -QoEwD3hDc2wJTpS8vZv3SMRV8v/AbWcYz85tb/vssNSXy4k3diA+TAZG8nVQ6Y5EcnkSfSdFKDzQ -PkXuJpCLIgSPNJqL78AUSX96EHqoTiXcPjQKTqDluBSaJNs5LhPF20Dzb3LDZQXom1uxRZMQUGVQ -Rwu0Ul5aLPr3qfstPotWvL/SQTM9B1HbrZcwaZL+bQUXj3gonkYIzgxLnXqDiXLG2TqjFg95Fbsi -rltgs35eCawt2CnDzCg1AD929foPsSymYxWJOQ== - -`pragma protect data_method = "AES128-CBC" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 118832) -`pragma protect data_block -xRkbFHYjHBL92y0nttsod96JEIQQo7pWjDqCbvr8+o9UvyWU41a5jrY6E23iS9MJ7Ux1XFnCAkUQ -UxL+vamJwWtefz4WDIXKlmXs5ifACqpKjTzi8P0lo9389LqogNJLifFafAGu/qGxXn90yHbeAUSA -AQ+7PVIwVRJjLiTRnGWFEwP358PmJBi98ZNpy8D0gby34pEHMmA3LlrS/wyFTQbtt/kExZ9wf1T6 -GOGIZt/akc3Tf0u9m8f+oJCQAf+hZEjRvKvo+X1TBobyH8LGa6Xb1B1qq76g9iChT633Yr0vfrwl -TkmCjO/qJNu5pZy2Fb+Tgrd993enk3nA8dkESNMqlNXi858GxqXkOvrrnIm25PRloITTgeT778ff -1HOgrV+rx2iPD6egb6AYhzx7RCulI0vm38TWtlaU+rt0Ch1qN8ndUGZXytQh9mZ/rpIextgTrSHn -6BvYNQ/Q66jjPBURGAwvMjwNFR0zSyS8e0Mw8VgTNyp8UiJLNVhtWHi+8Z6cE0ytLTBklYt/GkTM -kT/uzobbyyjOApzCp/We8rMOV/U4tY6GoDy8U5s+yGsAz1+olMfg/GFCXDsHP6qfpox5w+BRpGmh -DKc4RHqyIYQE+MJzWLCooch7u6Fuai838bTX2jeyfrAJNtOGF4eyBBsmyXMLTvj+EI91JC+gpsX0 -Ev6o/+qn9PXhdyqiWcTWslfjL6gWO8C3lcPG7R3hca12IBOjEw2dKMrOUm/auRY1cO4NidCHSdTs -x9ybyx3KhATzMev0t2VCVjh3veKA1bOCgclL9rQqcZ/l8ZyZATB/XK5YvCrjJp5OPb5+RdvZvU2v -JxIkHBNW/wCDag4YwQcBawL63pgkXf1Qu4E5n7pQBL6j5bDOmmuLGj9BxXdCuIdNsYxl7z34Re4B -L0uUMPJRcdmK34WnQq5h2bvApaRB2cbIPphg0RdAqZ3MXHYX6ejwxtEeV8lZ1eXcF9NXpKHb2AMy -vWbre6+OHUujqClwwLjiVRpLdPYJm63loqtbavmSmdmgyAwRDIquAtiDNarvW/b/dftjTmyc3LcA -o5u4DW2q4oOgPoo1WL+yoaZwFBXgUQq5Iuhwm/ExaaDycPnesE8ECvIBHL20JY6/bYOIAAlVROro -E+Od2zEh8FPOD8bq5IDBZY76nHb3/AK1k/pyR4o32LGK0a5p3gusO6ALxoILxJLL5/Pt2a6cz9O9 -1mXJOf6sFXwh8AEGB55iVooYexGBGHyHw60vxoFRdmh/10ZwBqgrBVBX0+5rWcVS3Ujca0NC5xRt -p1/Z4g38F/vcw9+lzsjQzecb6LJ6LaQgpvKUBcyvGo0gz6gaRAckFXNVU07GeJ1J1RB4EnRZZxMr -ZrvohEg5IHs+hBgGQDBvJwabQpLIO3v29BhIZBvE57EBuDMv9u0A/UdMducWOLg9ZTwDC+riSnEV -aCvQhN3zTA5/biMRVfQr+FjAHX8ivM4XNEBX94A6AOs/2pGdh9nYsQJr37T/jHsArLH80qwXy12T -xcgtFDHcxCluOBI80KA2XrxVG9t7WuBeOtod8crhcvKU6KglwZaHTxlkHraXH9IVOooGm2Xbp5vF -/SmKo/f9s746ftXnJxKDtsiRJgMxqOE1PTLNrc/acPlxkRnFCHT0NmclP4eSm9KjqOoVlJn/559c -9LHA6Jjy5FSlR3kfonN5AIh+Mf1W2D8b1oLfUG93bDeXvFwxtHeK2i2kx/5xn2bTQPdjwVshzS/D -f/2gsemN6llREi39nlCg4ZiiwJtbh9kt+lxqYekHNMq2IysdYKGXYqhgdavYtkNU3RIG5Fik7Wuq -Cm/kcR1fcBNn5/xO2y2NEq7DWnoAChtIppYE1z4lIB28vqS4X3TNKsm2aeVbEmjQMcI9fhRKzTBS -4YQKeI4rluf0rXs2Qkg9fI075rRkMw8yzzp52EJk5WEzVu8KbFOru3c9Lzp868/+vGb/R7iC0tPj -QpaAFhmq5Ir9nZrm6gQ5HhWuodyMmX4NwZlGP2SdHlSjgCB5lT6nXA5/544dliQ+1AdCOzuOdCTk -/pzBgc259SUIaQ9ea68yYSriddRcgLRfgajVZLGaXQOaBqASHpvsBoyVaR5W33LEBJXfVKRpOYVP -DKOXHsfrLT67BB/CW/YLPAQCEfxPc4FJalzqS1dg23n1lIqiQd1JxHu6O4+tbNHwLcz78oxzpRa+ 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-55niUjUH7aVk9dmlJ6LGEN5pCPCh1QOpDaIAEnbvwbD5DFIpJSiu1r7HLRKUimI5l5L5KcEEUSf3 -eNVU/IqkIEGFQceffezhFIhiV9BxCDglLtn97W21MRqsKwH5n/lW1Cn79+XbRwfZk+DouhocGwrX -1F2qMcdpVywPz9MiQIYadEyaiBD0/MNFBl8hedkw1QnJ5mu2vXrZ7km5RlHaKYwkMyPelFWzM5ZQ -fZj0YGLukXV9NzTqyc4C27b96cMO9Ry6J0e/4iEZINor+u1U9zQGo2+YBN8= -`pragma protect end_protected -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_sim_netlist.vhdl deleted file mode 100644 index 61e717d9..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_sim_netlist.vhdl +++ /dev/null @@ -1,3562 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:33:47 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_sim_netlist.vhdl --- Design : GaussFir_1mp5 --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -`protect begin_protected -`protect version = 1 -`protect encrypt_agent = "XILINX" -`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" -`protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=64) -`protect key_block -I5jBxSA30qMppesbkWzApATD001KfSyiO/EXeiSfqG/mDp7bWT98b6O2aLKwO2KBiQHns7D4kNzR -1vJ+KztHDg== - -`protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=128) -`protect key_block -WMu7kFTLnidedbfVrZuh/7ca7CUttjqfOqFAqALtw+gkp4fPh7ZCC2c3FriF2MGJNdt0inCBZQ1w -ERGO+2E2lzKAF62aWczdna33VjhJbQEhVD66TE3XkcNa3kH5qqUhb+EgT0e6ErzcmqjyjnkFxoKK -XKvbLV/yC8Myvjbgd1A= - -`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`protect key_block -xD5n0VbWIE6P1VxF0RmDDu2TYD4jh2LNu0PcTQhqBRKitH0v3xG4GrD/vuHfz6qhNoYV25YBOEWi -7kVjcZSXNFtC5ITuwneS2ZMRryiXpM8fFiU2j9L4eELr2/mHrJrVvacPISdaWzzVZMaXZGjjLF31 -zK98DBrt3GchBNvrcOgQmuPVAvjrSEZ+P+LhtLFVfq/zmFgYzV3AELJD6jr7elUkLyTjsJWEFYcf -b43n7Hb0i+cIbRt6Dd+v0kyLoVGDXUE7IXud31zG1Rotvh/eF07hFqqllLHHu2UWUNW8RAWEy1Fo -3/0kdpsYoC+scwVlEiw6L4xm3ZvOMO3xLhlx9Q== - -`protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`protect key_block -fQrDOnMjpZojQhY1c1rw1hwuEu2Y2M8ofkmIyKutN5o3WWgs402wk38nunx4Rn3nJ4alOoXDi3N8 -wCK4FFFUnB/83xpx5yiE801fH9CrSpiGk2CFUTGUPQ2AKib6X7q/ypXzIE3Xi/Fp8v68pOYfzYgB -DWCJiGAer9WgqVkNoAOLB2B99+hjhpjUr+bqeFKCONh+smCJvnzi5NuFbGTw6NRi9XF/fOBJpA7N -7mSHNKQA9TZaG877TLVUYWhpu8Tllt4YOnNvOy5csoZO6jBxXCjuxWmM9dl9WSOXp2HX/onR6rpz -sNUbO2lQftIr2WNh0Jv073YUwDxDBpl586IEWg== - -`protect key_keyowner="Xilinx", key_keyname="xilinxt_2019_02", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`protect key_block -Yt/xtD+YwHpwIG7cpV+YFKRLELTuOpDyL++EbS2PSHkTTnkY+SDEglVSGBUkgEMCy4FK2fL2wt2N -qjVnO38YwcIpkFA3hdVylOufwvfkyXzLnO4I/oXAmiPI3b+yEyPArGvVOGpDgyd07VUs/V9x8yNF -fJU+AQwpZcLwvczmvjIU4/eR8fdXCMBV/C6JW2N+CHrwTU69ne3XstJaVfOIPupKIpZjLVLIrAYs -UQMdOWUz5FDENYd645Oho01vEbgtbLb+GrcpRedjCAIY2LgO42kQ9rDb7oVFFsUuoIPnWF4fLEjb -Pq5mb00fUdX1TzSueiRRmMIn69wkk/QkSb8jag== - -`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=128) -`protect key_block -S5Ng9U2ICFR2ATladKVkI9g1B4mI1wuXRMAnMNgbxvoijFO8db10A3+6fvjuey2Yzxp1Hf4dZcYN -c/lBn1GB/WXkp/IAC1a0hNWcvyknzHaPnT0XXAr2t5Xncs67wJ8pN5Gp2D1qrZQQzDnNoYG2S/bd -YiWvkcmY78GRhm+UXVk= - -`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa" -`protect 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key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa" -`protect encoding = (enctype="BASE64", line_length=76, bytes=256) -`protect key_block -3QkFB6pXKTzGzaqSXrV21Qo1VVeMZGyJDfKUAW0Gn/tLHF9wYMPIMyMsrg2CkuXEziMZfWf6brJ6 -1EhiPbi01ICAsikmkpI4l1U2LIXxzauoM3c5hw4hO+1HT4d+V235So/JfFc/gKvRdqFFIj3fghxO -W80Q9C2GqBBFjTs9skUZRrkDsi83EnML3jYAu4e/BN5O/Pss4b/RejqxYKqZlxl/bXKj1X7raVDc -cU/SFogloK+NYEmP+110ai081Mx/N+kmljZYe8JncRGR6Ljx2fJ6ECu23P3xVYP6NlIH6tOuKRba -DeY/TDtirLc5z86PUFgtRZ2RHw99Y9knKjZxQg== - -`protect data_method = "AES128-CBC" -`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 166752) -`protect data_block -xseTrOLIKfNEvJ4C1VfejwEJyeVkvCv6R0F79vqizmRwC+ZpIAIfcPaT3Cj2s/FDUcFkymiTN4sK -Cydd8vYeLrq/c3sx00VyrGfslrRw5125f4GYudhklLbfD/xqaNLDJI2IXRC1Ca6eQFifwr3JyTZ9 -kzxVMTPSuzg2rV5K9xYWaCf6B3qLJWoNeY5ESyPpM5GhCEbZiy1t3A8YOXVjpzyP1VXKICjEbYgD -HphaJvzaQy9EfS+vp7NCHhAuLyuDrt4iuKPuYsTU7E7MLYxw3IYj7E35uCA4eH50BCDll1zUe2bk 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STD_LOGIC; - s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axis_reload_tvalid : in STD_LOGIC; - s_axis_reload_tready : out STD_LOGIC; - s_axis_reload_tlast : in STD_LOGIC; - s_axis_reload_tdata : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_data_tvalid : out STD_LOGIC; - m_axis_data_tready : in STD_LOGIC; - m_axis_data_tlast : out STD_LOGIC; - m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); - event_s_data_tlast_missing : out STD_LOGIC; - event_s_data_tlast_unexpected : out STD_LOGIC; - event_s_data_chanid_incorrect : out STD_LOGIC; - event_s_config_tlast_missing : out STD_LOGIC; - event_s_config_tlast_unexpected : out STD_LOGIC; - event_s_reload_tlast_missing : out STD_LOGIC; - event_s_reload_tlast_unexpected : out STD_LOGIC - ); - attribute C_ACCUM_OP_PATH_WIDTHS : string; - attribute C_ACCUM_OP_PATH_WIDTHS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "13"; - attribute C_ACCUM_PATH_WIDTHS : string; - attribute C_ACCUM_PATH_WIDTHS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "13"; - attribute C_CHANNEL_PATTERN : string; - attribute C_CHANNEL_PATTERN of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "fixed"; - attribute C_COEF_FILE : string; - attribute C_COEF_FILE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "GaussFir_1mp5.mif"; - attribute C_COEF_FILE_LINES : integer; - attribute C_COEF_FILE_LINES of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 160; - attribute C_COEF_MEMTYPE : integer; - attribute C_COEF_MEMTYPE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 2; - attribute C_COEF_MEM_PACKING : integer; - attribute C_COEF_MEM_PACKING of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_COEF_PATH_SIGN : string; - attribute C_COEF_PATH_SIGN of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "1"; - attribute C_COEF_PATH_SRC : string; - attribute C_COEF_PATH_SRC of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "0"; - attribute C_COEF_PATH_WIDTHS : string; - attribute C_COEF_PATH_WIDTHS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "14"; - attribute C_COEF_RELOAD : integer; - attribute C_COEF_RELOAD of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_COEF_WIDTH : integer; - attribute C_COEF_WIDTH of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 14; - attribute C_COL_CONFIG : string; - attribute C_COL_CONFIG of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "5"; - attribute C_COL_MODE : integer; - attribute C_COL_MODE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_COL_PIPE_LEN : integer; - attribute C_COL_PIPE_LEN of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 4; - attribute C_COMPONENT_NAME : string; - attribute C_COMPONENT_NAME of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "GaussFir_1mp5"; - attribute C_CONFIG_PACKET_SIZE : integer; - attribute C_CONFIG_PACKET_SIZE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_CONFIG_SYNC_MODE : integer; - attribute C_CONFIG_SYNC_MODE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_CONFIG_TDATA_WIDTH : integer; - attribute C_CONFIG_TDATA_WIDTH of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_DATAPATH_MEMTYPE : integer; - attribute C_DATAPATH_MEMTYPE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_DATA_HAS_TLAST : integer; - attribute C_DATA_HAS_TLAST of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_DATA_IP_PATH_WIDTHS : string; - attribute C_DATA_IP_PATH_WIDTHS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "2"; - attribute C_DATA_MEMTYPE : integer; - attribute C_DATA_MEMTYPE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_DATA_MEM_PACKING : integer; - attribute C_DATA_MEM_PACKING of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_DATA_PATH_PSAMP_SRC : string; - attribute C_DATA_PATH_PSAMP_SRC of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "0"; - attribute C_DATA_PATH_SIGN : string; - attribute C_DATA_PATH_SIGN of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "0"; - attribute C_DATA_PATH_SRC : string; - attribute C_DATA_PATH_SRC of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "0"; - attribute C_DATA_PATH_WIDTHS : string; - attribute C_DATA_PATH_WIDTHS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "2"; - attribute C_DATA_PX_PATH_WIDTHS : string; - attribute C_DATA_PX_PATH_WIDTHS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "2"; - attribute C_DATA_WIDTH : integer; - attribute C_DATA_WIDTH of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 2; - attribute C_DECIM_RATE : integer; - attribute C_DECIM_RATE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_ELABORATION_DIR : string; - attribute C_ELABORATION_DIR of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "./"; - attribute C_EXT_MULT_CNFG : string; - attribute C_EXT_MULT_CNFG of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "none"; - attribute C_FILTER_TYPE : integer; - attribute C_FILTER_TYPE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 2; - attribute C_FILTS_PACKED : integer; - attribute C_FILTS_PACKED of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_HAS_ACLKEN : integer; - attribute C_HAS_ACLKEN of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_HAS_ARESETn : integer; - attribute C_HAS_ARESETn of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_HAS_CONFIG_CHANNEL : integer; - attribute C_HAS_CONFIG_CHANNEL of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_INPUT_RATE : integer; - attribute C_INPUT_RATE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 32; - attribute C_INTERP_RATE : integer; - attribute C_INTERP_RATE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 32; - attribute C_IPBUFF_MEMTYPE : integer; - attribute C_IPBUFF_MEMTYPE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_LATENCY : integer; - attribute C_LATENCY of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 11; - attribute C_MEM_ARRANGEMENT : integer; - attribute C_MEM_ARRANGEMENT of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 2; - attribute C_M_DATA_HAS_TREADY : integer; - attribute C_M_DATA_HAS_TREADY of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_M_DATA_HAS_TUSER : integer; - attribute C_M_DATA_HAS_TUSER of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_M_DATA_TDATA_WIDTH : integer; - attribute C_M_DATA_TDATA_WIDTH of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 16; - attribute C_M_DATA_TUSER_WIDTH : integer; - attribute C_M_DATA_TUSER_WIDTH of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_NUM_CHANNELS : integer; - attribute C_NUM_CHANNELS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_NUM_FILTS : integer; - attribute C_NUM_FILTS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_NUM_MADDS : integer; - attribute C_NUM_MADDS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 5; - attribute C_NUM_RELOAD_SLOTS : integer; - attribute C_NUM_RELOAD_SLOTS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_NUM_TAPS : integer; - attribute C_NUM_TAPS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 129; - attribute C_OPBUFF_MEMTYPE : integer; - attribute C_OPBUFF_MEMTYPE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_OPTIMIZATION : integer; - attribute C_OPTIMIZATION of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_OPT_MADDS : string; - attribute C_OPT_MADDS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "none"; - attribute C_OP_PATH_PSAMP_SRC : string; - attribute C_OP_PATH_PSAMP_SRC of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "0"; - attribute C_OUTPUT_PATH_WIDTHS : string; - attribute C_OUTPUT_PATH_WIDTHS of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "13"; - attribute C_OUTPUT_RATE : integer; - attribute C_OUTPUT_RATE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_OUTPUT_WIDTH : integer; - attribute C_OUTPUT_WIDTH of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 13; - attribute C_OVERSAMPLING_RATE : integer; - attribute C_OVERSAMPLING_RATE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_PX_PATH_SRC : string; - attribute C_PX_PATH_SRC of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "0"; - attribute C_RELOAD_TDATA_WIDTH : integer; - attribute C_RELOAD_TDATA_WIDTH of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_ROUND_MODE : integer; - attribute C_ROUND_MODE of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_SYMMETRY : integer; - attribute C_SYMMETRY of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_S_DATA_HAS_FIFO : integer; - attribute C_S_DATA_HAS_FIFO of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_S_DATA_HAS_TUSER : integer; - attribute C_S_DATA_HAS_TUSER of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 0; - attribute C_S_DATA_TDATA_WIDTH : integer; - attribute C_S_DATA_TDATA_WIDTH of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 8; - attribute C_S_DATA_TUSER_WIDTH : integer; - attribute C_S_DATA_TUSER_WIDTH of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "kintex7"; - attribute C_ZERO_PACKING_FACTOR : integer; - attribute C_ZERO_PACKING_FACTOR of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is 1; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "fir_compiler_v7_2_12"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of GaussFir_1mp5_fir_compiler_v7_2_12 : entity is "yes"; -end GaussFir_1mp5_fir_compiler_v7_2_12; - -architecture STRUCTURE of GaussFir_1mp5_fir_compiler_v7_2_12 is - signal \\ : STD_LOGIC; - signal \^m_axis_data_tdata\ : STD_LOGIC_VECTOR ( 12 downto 0 ); - signal NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_data_chanid_incorrect_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_data_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_data_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_reload_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_event_s_reload_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_m_axis_data_tlast_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_s_axis_config_tready_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_s_axis_reload_tready_UNCONNECTED : STD_LOGIC; - signal NLW_i_synth_m_axis_data_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 12 ); - signal NLW_i_synth_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - attribute C_ACCUM_OP_PATH_WIDTHS of i_synth : label is "13"; - attribute C_ACCUM_PATH_WIDTHS of i_synth : label is "13"; - attribute C_CHANNEL_PATTERN of i_synth : label is "fixed"; - attribute C_COEF_FILE of i_synth : label is "GaussFir_1mp5.mif"; - attribute C_COEF_FILE_LINES of i_synth : label is 160; - attribute C_COEF_MEMTYPE of i_synth : label is 2; - attribute C_COEF_MEM_PACKING of i_synth : label is 0; - attribute C_COEF_PATH_SIGN of i_synth : label is "1"; - attribute C_COEF_PATH_SRC of i_synth : label is "0"; - attribute C_COEF_PATH_WIDTHS of i_synth : label is "14"; - attribute C_COEF_RELOAD of i_synth : label is 0; - attribute C_COEF_WIDTH of i_synth : label is 14; - attribute C_COL_CONFIG of i_synth : label is "5"; - attribute C_COL_MODE of i_synth : label is 1; - attribute C_COL_PIPE_LEN of i_synth : label is 4; - attribute C_COMPONENT_NAME of i_synth : label is "GaussFir_1mp5"; - attribute C_CONFIG_PACKET_SIZE of i_synth : label is 0; - attribute C_CONFIG_SYNC_MODE of i_synth : label is 0; - attribute C_CONFIG_TDATA_WIDTH of i_synth : label is 1; - attribute C_DATAPATH_MEMTYPE of i_synth : label is 0; - attribute C_DATA_HAS_TLAST of i_synth : label is 0; - attribute C_DATA_IP_PATH_WIDTHS of i_synth : label is "2"; - attribute C_DATA_MEMTYPE of i_synth : label is 0; - attribute C_DATA_MEM_PACKING of i_synth : label is 0; - attribute C_DATA_PATH_PSAMP_SRC of i_synth : label is "0"; - attribute C_DATA_PATH_SIGN of i_synth : label is "0"; - attribute C_DATA_PATH_SRC of i_synth : label is "0"; - attribute C_DATA_PATH_WIDTHS of i_synth : label is "2"; - attribute C_DATA_PX_PATH_WIDTHS of i_synth : label is "2"; - attribute C_DATA_WIDTH of i_synth : label is 2; - attribute C_DECIM_RATE of i_synth : label is 1; - attribute C_ELABORATION_DIR of i_synth : label is "./"; - attribute C_EXT_MULT_CNFG of i_synth : label is "none"; - attribute C_FILTER_TYPE of i_synth : label is 2; - attribute C_FILTS_PACKED of i_synth : label is 0; - attribute C_HAS_ACLKEN of i_synth : label is 0; - attribute C_HAS_ARESETn of i_synth : label is 0; - attribute C_HAS_CONFIG_CHANNEL of i_synth : label is 0; - attribute C_INPUT_RATE of i_synth : label is 32; - attribute C_INTERP_RATE of i_synth : label is 32; - attribute C_IPBUFF_MEMTYPE of i_synth : label is 0; - attribute C_LATENCY of i_synth : label is 11; - attribute C_MEM_ARRANGEMENT of i_synth : label is 2; - attribute C_M_DATA_HAS_TREADY of i_synth : label is 0; - attribute C_M_DATA_HAS_TUSER of i_synth : label is 0; - attribute C_M_DATA_TDATA_WIDTH of i_synth : label is 16; - attribute C_M_DATA_TUSER_WIDTH of i_synth : label is 1; - attribute C_NUM_CHANNELS of i_synth : label is 1; - attribute C_NUM_FILTS of i_synth : label is 1; - attribute C_NUM_MADDS of i_synth : label is 5; - attribute C_NUM_RELOAD_SLOTS of i_synth : label is 1; - attribute C_NUM_TAPS of i_synth : label is 129; - attribute C_OPBUFF_MEMTYPE of i_synth : label is 0; - attribute C_OPTIMIZATION of i_synth : label is 0; - attribute C_OPT_MADDS of i_synth : label is "none"; - attribute C_OP_PATH_PSAMP_SRC of i_synth : label is "0"; - attribute C_OUTPUT_PATH_WIDTHS of i_synth : label is "13"; - attribute C_OUTPUT_RATE of i_synth : label is 1; - attribute C_OUTPUT_WIDTH of i_synth : label is 13; - attribute C_OVERSAMPLING_RATE of i_synth : label is 1; - attribute C_PX_PATH_SRC of i_synth : label is "0"; - attribute C_RELOAD_TDATA_WIDTH of i_synth : label is 1; - attribute C_ROUND_MODE of i_synth : label is 0; - attribute C_SYMMETRY of i_synth : label is 0; - attribute C_S_DATA_HAS_FIFO of i_synth : label is 0; - attribute C_S_DATA_HAS_TUSER of i_synth : label is 0; - attribute C_S_DATA_TDATA_WIDTH of i_synth : label is 8; - attribute C_S_DATA_TUSER_WIDTH of i_synth : label is 1; - attribute C_XDEVICEFAMILY of i_synth : label is "kintex7"; - attribute C_ZERO_PACKING_FACTOR of i_synth : label is 1; - attribute downgradeipidentifiedwarnings of i_synth : label is "yes"; -begin - event_s_config_tlast_missing <= \\; - event_s_config_tlast_unexpected <= \\; - event_s_data_chanid_incorrect <= \\; - event_s_data_tlast_missing <= \\; - event_s_data_tlast_unexpected <= \\; - event_s_reload_tlast_missing <= \\; - event_s_reload_tlast_unexpected <= \\; - m_axis_data_tdata(15) <= \^m_axis_data_tdata\(12); - m_axis_data_tdata(14) <= \^m_axis_data_tdata\(12); - m_axis_data_tdata(13) <= \^m_axis_data_tdata\(12); - m_axis_data_tdata(12 downto 0) <= \^m_axis_data_tdata\(12 downto 0); - m_axis_data_tlast <= \\; - m_axis_data_tuser(0) <= \\; - s_axis_config_tready <= \\; - s_axis_reload_tready <= \\; -GND: unisim.vcomponents.GND - port map ( - G => \\ - ); -i_synth: entity work.GaussFir_1mp5_fir_compiler_v7_2_12_viv - port map ( - aclk => aclk, - aclken => '0', - aresetn => '0', - event_s_config_tlast_missing => NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED, - event_s_config_tlast_unexpected => NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED, - event_s_data_chanid_incorrect => NLW_i_synth_event_s_data_chanid_incorrect_UNCONNECTED, - event_s_data_tlast_missing => NLW_i_synth_event_s_data_tlast_missing_UNCONNECTED, - event_s_data_tlast_unexpected => NLW_i_synth_event_s_data_tlast_unexpected_UNCONNECTED, - event_s_reload_tlast_missing => NLW_i_synth_event_s_reload_tlast_missing_UNCONNECTED, - event_s_reload_tlast_unexpected => NLW_i_synth_event_s_reload_tlast_unexpected_UNCONNECTED, - m_axis_data_tdata(15) => \^m_axis_data_tdata\(12), - m_axis_data_tdata(14 downto 12) => NLW_i_synth_m_axis_data_tdata_UNCONNECTED(14 downto 12), - m_axis_data_tdata(11 downto 0) => \^m_axis_data_tdata\(11 downto 0), - m_axis_data_tlast => NLW_i_synth_m_axis_data_tlast_UNCONNECTED, - m_axis_data_tready => '0', - m_axis_data_tuser(0) => NLW_i_synth_m_axis_data_tuser_UNCONNECTED(0), - m_axis_data_tvalid => m_axis_data_tvalid, - s_axis_config_tdata(0) => '0', - s_axis_config_tlast => '0', - s_axis_config_tready => NLW_i_synth_s_axis_config_tready_UNCONNECTED, - s_axis_config_tvalid => '0', - s_axis_data_tdata(7 downto 2) => B"000000", - s_axis_data_tdata(1 downto 0) => s_axis_data_tdata(1 downto 0), - s_axis_data_tlast => '0', - s_axis_data_tready => s_axis_data_tready, - s_axis_data_tuser(0) => '0', - s_axis_data_tvalid => s_axis_data_tvalid, - s_axis_reload_tdata(0) => '0', - s_axis_reload_tlast => '0', - s_axis_reload_tready => NLW_i_synth_s_axis_reload_tready_UNCONNECTED, - s_axis_reload_tvalid => '0' - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity GaussFir_1mp5 is - port ( - aclk : in STD_LOGIC; - s_axis_data_tvalid : in STD_LOGIC; - s_axis_data_tready : out STD_LOGIC; - s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); - m_axis_data_tvalid : out STD_LOGIC; - m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ) - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of GaussFir_1mp5 : entity is true; - attribute CHECK_LICENSE_TYPE : string; - attribute CHECK_LICENSE_TYPE of GaussFir_1mp5 : entity is "GaussFir_1mp5,fir_compiler_v7_2_12,{}"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of GaussFir_1mp5 : entity is "yes"; - attribute x_core_info : string; - attribute x_core_info of GaussFir_1mp5 : entity is "fir_compiler_v7_2_12,Vivado 2019.1.3"; -end GaussFir_1mp5; - -architecture STRUCTURE of GaussFir_1mp5 is - signal NLW_U0_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_data_chanid_incorrect_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_data_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_data_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_reload_tlast_missing_UNCONNECTED : STD_LOGIC; - signal NLW_U0_event_s_reload_tlast_unexpected_UNCONNECTED : STD_LOGIC; - signal NLW_U0_m_axis_data_tlast_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axis_config_tready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axis_reload_tready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - attribute C_ACCUM_OP_PATH_WIDTHS : string; - attribute C_ACCUM_OP_PATH_WIDTHS of U0 : label is "13"; - attribute C_ACCUM_PATH_WIDTHS : string; - attribute C_ACCUM_PATH_WIDTHS of U0 : label is "13"; - attribute C_CHANNEL_PATTERN : string; - attribute C_CHANNEL_PATTERN of U0 : label is "fixed"; - attribute C_COEF_FILE : string; - attribute C_COEF_FILE of U0 : label is "GaussFir_1mp5.mif"; - attribute C_COEF_FILE_LINES : integer; - attribute C_COEF_FILE_LINES of U0 : label is 160; - attribute C_COEF_MEMTYPE : integer; - attribute C_COEF_MEMTYPE of U0 : label is 2; - attribute C_COEF_MEM_PACKING : integer; - attribute C_COEF_MEM_PACKING of U0 : label is 0; - attribute C_COEF_PATH_SIGN : string; - attribute C_COEF_PATH_SIGN of U0 : label is "1"; - attribute C_COEF_PATH_SRC : string; - attribute C_COEF_PATH_SRC of U0 : label is "0"; - attribute C_COEF_PATH_WIDTHS : string; - attribute C_COEF_PATH_WIDTHS of U0 : label is "14"; - attribute C_COEF_RELOAD : integer; - attribute C_COEF_RELOAD of U0 : label is 0; - attribute C_COEF_WIDTH : integer; - attribute C_COEF_WIDTH of U0 : label is 14; - attribute C_COL_CONFIG : string; - attribute C_COL_CONFIG of U0 : label is "5"; - attribute C_COL_MODE : integer; - attribute C_COL_MODE of U0 : label is 1; - attribute C_COL_PIPE_LEN : integer; - attribute C_COL_PIPE_LEN of U0 : label is 4; - attribute C_COMPONENT_NAME : string; - attribute C_COMPONENT_NAME of U0 : label is "GaussFir_1mp5"; - attribute C_CONFIG_PACKET_SIZE : integer; - attribute C_CONFIG_PACKET_SIZE of U0 : label is 0; - attribute C_CONFIG_SYNC_MODE : integer; - attribute C_CONFIG_SYNC_MODE of U0 : label is 0; - attribute C_CONFIG_TDATA_WIDTH : integer; - attribute C_CONFIG_TDATA_WIDTH of U0 : label is 1; - attribute C_DATAPATH_MEMTYPE : integer; - attribute C_DATAPATH_MEMTYPE of U0 : label is 0; - attribute C_DATA_HAS_TLAST : integer; - attribute C_DATA_HAS_TLAST of U0 : label is 0; - attribute C_DATA_IP_PATH_WIDTHS : string; - attribute C_DATA_IP_PATH_WIDTHS of U0 : label is "2"; - attribute C_DATA_MEMTYPE : integer; - attribute C_DATA_MEMTYPE of U0 : label is 0; - attribute C_DATA_MEM_PACKING : integer; - attribute C_DATA_MEM_PACKING of U0 : label is 0; - attribute C_DATA_PATH_PSAMP_SRC : string; - attribute C_DATA_PATH_PSAMP_SRC of U0 : label is "0"; - attribute C_DATA_PATH_SIGN : string; - attribute C_DATA_PATH_SIGN of U0 : label is "0"; - attribute C_DATA_PATH_SRC : string; - attribute C_DATA_PATH_SRC of U0 : label is "0"; - attribute C_DATA_PATH_WIDTHS : string; - attribute C_DATA_PATH_WIDTHS of U0 : label is "2"; - attribute C_DATA_PX_PATH_WIDTHS : string; - attribute C_DATA_PX_PATH_WIDTHS of U0 : label is "2"; - attribute C_DATA_WIDTH : integer; - attribute C_DATA_WIDTH of U0 : label is 2; - attribute C_DECIM_RATE : integer; - attribute C_DECIM_RATE of U0 : label is 1; - attribute C_ELABORATION_DIR : string; - attribute C_ELABORATION_DIR of U0 : label is "./"; - attribute C_EXT_MULT_CNFG : string; - attribute C_EXT_MULT_CNFG of U0 : label is "none"; - attribute C_FILTER_TYPE : integer; - attribute C_FILTER_TYPE of U0 : label is 2; - attribute C_FILTS_PACKED : integer; - attribute C_FILTS_PACKED of U0 : label is 0; - attribute C_HAS_ACLKEN : integer; - attribute C_HAS_ACLKEN of U0 : label is 0; - attribute C_HAS_ARESETn : integer; - attribute C_HAS_ARESETn of U0 : label is 0; - attribute C_HAS_CONFIG_CHANNEL : integer; - attribute C_HAS_CONFIG_CHANNEL of U0 : label is 0; - attribute C_INPUT_RATE : integer; - attribute C_INPUT_RATE of U0 : label is 32; - attribute C_INTERP_RATE : integer; - attribute C_INTERP_RATE of U0 : label is 32; - attribute C_IPBUFF_MEMTYPE : integer; - attribute C_IPBUFF_MEMTYPE of U0 : label is 0; - attribute C_LATENCY : integer; - attribute C_LATENCY of U0 : label is 11; - attribute C_MEM_ARRANGEMENT : integer; - attribute C_MEM_ARRANGEMENT of U0 : label is 2; - attribute C_M_DATA_HAS_TREADY : integer; - attribute C_M_DATA_HAS_TREADY of U0 : label is 0; - attribute C_M_DATA_HAS_TUSER : integer; - attribute C_M_DATA_HAS_TUSER of U0 : label is 0; - attribute C_M_DATA_TDATA_WIDTH : integer; - attribute C_M_DATA_TDATA_WIDTH of U0 : label is 16; - attribute C_M_DATA_TUSER_WIDTH : integer; - attribute C_M_DATA_TUSER_WIDTH of U0 : label is 1; - attribute C_NUM_CHANNELS : integer; - attribute C_NUM_CHANNELS of U0 : label is 1; - attribute C_NUM_FILTS : integer; - attribute C_NUM_FILTS of U0 : label is 1; - attribute C_NUM_MADDS : integer; - attribute C_NUM_MADDS of U0 : label is 5; - attribute C_NUM_RELOAD_SLOTS : integer; - attribute C_NUM_RELOAD_SLOTS of U0 : label is 1; - attribute C_NUM_TAPS : integer; - attribute C_NUM_TAPS of U0 : label is 129; - attribute C_OPBUFF_MEMTYPE : integer; - attribute C_OPBUFF_MEMTYPE of U0 : label is 0; - attribute C_OPTIMIZATION : integer; - attribute C_OPTIMIZATION of U0 : label is 0; - attribute C_OPT_MADDS : string; - attribute C_OPT_MADDS of U0 : label is "none"; - attribute C_OP_PATH_PSAMP_SRC : string; - attribute C_OP_PATH_PSAMP_SRC of U0 : label is "0"; - attribute C_OUTPUT_PATH_WIDTHS : string; - attribute C_OUTPUT_PATH_WIDTHS of U0 : label is "13"; - attribute C_OUTPUT_RATE : integer; - attribute C_OUTPUT_RATE of U0 : label is 1; - attribute C_OUTPUT_WIDTH : integer; - attribute C_OUTPUT_WIDTH of U0 : label is 13; - attribute C_OVERSAMPLING_RATE : integer; - attribute C_OVERSAMPLING_RATE of U0 : label is 1; - attribute C_PX_PATH_SRC : string; - attribute C_PX_PATH_SRC of U0 : label is "0"; - attribute C_RELOAD_TDATA_WIDTH : integer; - attribute C_RELOAD_TDATA_WIDTH of U0 : label is 1; - attribute C_ROUND_MODE : integer; - attribute C_ROUND_MODE of U0 : label is 0; - attribute C_SYMMETRY : integer; - attribute C_SYMMETRY of U0 : label is 0; - attribute C_S_DATA_HAS_FIFO : integer; - attribute C_S_DATA_HAS_FIFO of U0 : label is 0; - attribute C_S_DATA_HAS_TUSER : integer; - attribute C_S_DATA_HAS_TUSER of U0 : label is 0; - attribute C_S_DATA_TDATA_WIDTH : integer; - attribute C_S_DATA_TDATA_WIDTH of U0 : label is 8; - attribute C_S_DATA_TUSER_WIDTH : integer; - attribute C_S_DATA_TUSER_WIDTH of U0 : label is 1; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of U0 : label is "kintex7"; - attribute C_ZERO_PACKING_FACTOR : integer; - attribute C_ZERO_PACKING_FACTOR of U0 : label is 1; - attribute downgradeipidentifiedwarnings of U0 : label is "yes"; - attribute x_interface_info : string; - attribute x_interface_info of aclk : signal is "xilinx.com:signal:clock:1.0 aclk_intf CLK"; - attribute x_interface_parameter : string; - attribute x_interface_parameter of aclk : signal is "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0"; - attribute x_interface_info of m_axis_data_tvalid : signal is "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID"; - attribute x_interface_parameter of m_axis_data_tvalid : signal is "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; - attribute x_interface_info of s_axis_data_tready : signal is "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY"; - attribute x_interface_info of s_axis_data_tvalid : signal is "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID"; - attribute x_interface_parameter of s_axis_data_tvalid : signal is "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; - attribute x_interface_info of m_axis_data_tdata : signal is "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA"; - attribute x_interface_info of s_axis_data_tdata : signal is "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA"; -begin -U0: entity work.GaussFir_1mp5_fir_compiler_v7_2_12 - port map ( - aclk => aclk, - aclken => '1', - aresetn => '1', - event_s_config_tlast_missing => NLW_U0_event_s_config_tlast_missing_UNCONNECTED, - event_s_config_tlast_unexpected => NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED, - event_s_data_chanid_incorrect => NLW_U0_event_s_data_chanid_incorrect_UNCONNECTED, - event_s_data_tlast_missing => NLW_U0_event_s_data_tlast_missing_UNCONNECTED, - event_s_data_tlast_unexpected => NLW_U0_event_s_data_tlast_unexpected_UNCONNECTED, - event_s_reload_tlast_missing => NLW_U0_event_s_reload_tlast_missing_UNCONNECTED, - event_s_reload_tlast_unexpected => NLW_U0_event_s_reload_tlast_unexpected_UNCONNECTED, - m_axis_data_tdata(15 downto 0) => m_axis_data_tdata(15 downto 0), - m_axis_data_tlast => NLW_U0_m_axis_data_tlast_UNCONNECTED, - m_axis_data_tready => '1', - m_axis_data_tuser(0) => NLW_U0_m_axis_data_tuser_UNCONNECTED(0), - m_axis_data_tvalid => m_axis_data_tvalid, - s_axis_config_tdata(0) => '0', - s_axis_config_tlast => '0', - s_axis_config_tready => NLW_U0_s_axis_config_tready_UNCONNECTED, - s_axis_config_tvalid => '0', - s_axis_data_tdata(7 downto 0) => s_axis_data_tdata(7 downto 0), - s_axis_data_tlast => '0', - s_axis_data_tready => s_axis_data_tready, - s_axis_data_tuser(0) => '0', - s_axis_data_tvalid => s_axis_data_tvalid, - s_axis_reload_tdata(0) => '0', - s_axis_reload_tlast => '0', - s_axis_reload_tready => NLW_U0_s_axis_reload_tready_UNCONNECTED, - s_axis_reload_tvalid => '0' - ); -end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.v deleted file mode 100644 index aea6fdf9..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.v +++ /dev/null @@ -1,26 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:33:47 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.v -// Design : GaussFir_1mp5 -// Purpose : Stub declaration of top-level module interface -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *) -module GaussFir_1mp5(aclk, s_axis_data_tvalid, s_axis_data_tready, - s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata) -/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */; - input aclk; - input s_axis_data_tvalid; - output s_axis_data_tready; - input [7:0]s_axis_data_tdata; - output m_axis_data_tvalid; - output [15:0]m_axis_data_tdata; -endmodule diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.vhdl deleted file mode 100644 index 0b7b836d..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.vhdl +++ /dev/null @@ -1,35 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:33:47 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.vhdl --- Design : GaussFir_1mp5 --- Purpose : Stub declaration of top-level module interface --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity GaussFir_1mp5 is - Port ( - aclk : in STD_LOGIC; - s_axis_data_tvalid : in STD_LOGIC; - s_axis_data_tready : out STD_LOGIC; - s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); - m_axis_data_tvalid : out STD_LOGIC; - m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ) - ); - -end GaussFir_1mp5; - -architecture stub of GaussFir_1mp5 is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]"; -attribute x_core_info : string; -attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3"; -begin -end; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_utilization_synth.pb b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_utilization_synth.pb deleted file mode 100644 index 0385569f..00000000 Binary files a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_utilization_synth.pb and /dev/null differ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_utilization_synth.rpt b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_utilization_synth.rpt deleted file mode 100644 index cd179f82..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_utilization_synth.rpt +++ /dev/null @@ -1,184 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -| Date : Sat Mar 18 23:33:47 2023 -| Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -| Command : report_utilization -file GaussFir_1mp5_utilization_synth.rpt -pb GaussFir_1mp5_utilization_synth.pb -| Design : GaussFir_1mp5 -| Device : 7k410tffg900-2 -| Design State : Synthesized ---------------------------------------------------------------------------------------------------------------------- - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists - -1. Slice Logic --------------- - -+----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 41 | 0 | 254200 | 0.02 | -| LUT as Logic | 30 | 0 | 254200 | 0.01 | -| LUT as Memory | 11 | 0 | 90600 | 0.01 | -| LUT as Distributed RAM | 0 | 0 | | | -| LUT as Shift Register | 11 | 0 | | | -| Slice Registers | 97 | 0 | 508400 | 0.02 | -| Register as Flip Flop | 97 | 0 | 508400 | 0.02 | -| Register as Latch | 0 | 0 | 508400 | 0.00 | -| F7 Muxes | 0 | 0 | 127100 | 0.00 | -| F8 Muxes | 0 | 0 | 63550 | 0.00 | -+----------------------------+------+-------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 97 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Memory ---------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 795 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 795 | 0.00 | -| RAMB18 | 0 | 0 | 1590 | 0.00 | -+----------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -3. DSP ------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| DSPs | 5 | 0 | 1540 | 0.32 | -| DSP48E1 only | 5 | | | | -+----------------+------+-------+-----------+-------+ - - -4. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 0 | 0 | 500 | 0.00 | -| Bonded IPADs | 0 | 0 | 50 | 0.00 | -| Bonded OPADs | 0 | 0 | 32 | 0.00 | -| PHY_CONTROL | 0 | 0 | 10 | 0.00 | -| PHASER_REF | 0 | 0 | 10 | 0.00 | -| OUT_FIFO | 0 | 0 | 40 | 0.00 | -| IN_FIFO | 0 | 0 | 40 | 0.00 | -| IDELAYCTRL | 0 | 0 | 10 | 0.00 | -| IBUFDS | 0 | 0 | 480 | 0.00 | -| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | -| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 | -| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | -| ILOGIC | 0 | 0 | 500 | 0.00 | -| OLOGIC | 0 | 0 | 500 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -5. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 0 | 0 | 32 | 0.00 | -| BUFIO | 0 | 0 | 40 | 0.00 | -| MMCME2_ADV | 0 | 0 | 10 | 0.00 | -| PLLE2_ADV | 0 | 0 | 10 | 0.00 | -| BUFMRCE | 0 | 0 | 20 | 0.00 | -| BUFHCE | 0 | 0 | 168 | 0.00 | -| BUFR | 0 | 0 | 40 | 0.00 | -+------------+------+-------+-----------+-------+ - - -6. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -7. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| FDRE | 97 | Flop & Latch | -| LUT5 | 32 | LUT | -| SRL16E | 11 | Distributed Memory | -| LUT4 | 10 | LUT | -| DSP48E1 | 5 | Block Arithmetic | -| LUT6 | 3 | LUT | -| LUT3 | 3 | LUT | -| LUT2 | 3 | LUT | -| LUT1 | 1 | LUT | -+----------+------+---------------------+ - - -8. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -9. Instantiated Netlists ------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/ISEWrap.js b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/ISEWrap.js deleted file mode 100644 index 97a2ecbc..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/ISEWrap.js +++ /dev/null @@ -1,270 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/ISEWrap.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/ISEWrap.sh deleted file mode 100644 index f679f2e8..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/__synthesis_is_complete__ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/dont_touch.xdc b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/dont_touch.xdc deleted file mode 100644 index 46bdc5e7..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/dont_touch.xdc +++ /dev/null @@ -1,24 +0,0 @@ -# This file is automatically generated. -# It contains project source information necessary for synthesis and implementation. - -# IP: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/GaussFir_1mp5.xci -# IP: The module: 'GaussFir_1mp5' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/constraints/fir_compiler_v7_2.xdc -# XDC: The top module name and the constraint reference have the same name: 'GaussFir_1mp5'. Do not add the DONT_TOUCH constraint. -set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet - -# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/GaussFir_1mp5_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'GaussFir_1mp5'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet - -# IP: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/GaussFir_1mp5.xci -# IP: The module: 'GaussFir_1mp5' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/constraints/fir_compiler_v7_2.xdc -# XDC: The top module name and the constraint reference have the same name: 'GaussFir_1mp5'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet - -# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/GaussFir_1mp5/GaussFir_1mp5_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'GaussFir_1mp5'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/gen_run.xml deleted file mode 100644 index 6cb0e7c8..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/gen_run.xml +++ /dev/null @@ -1,59 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/htr.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/htr.txt deleted file mode 100644 index 70ad0282..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log GaussFir_1mp5.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source GaussFir_1mp5.tcl diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/project.wdf b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/project.wdf deleted file mode 100644 index 9507bcd5..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/project.wdf +++ /dev/null @@ -1,59 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:38:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/rundef.js b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/rundef.js deleted file mode 100644 index f73da1ca..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/rundef.js +++ /dev/null @@ -1,36 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log GaussFir_1mp5.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source GaussFir_1mp5.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/runme.bat b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/runme.bat deleted file mode 100644 index 1760626b..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/runme.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/runme.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/runme.sh deleted file mode 100644 index 4741c57c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/runme.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin -else - PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log GaussFir_1mp5.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source GaussFir_1mp5.tcl diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/vivado.pb b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/vivado.pb deleted file mode 100644 index ad1462f1..00000000 Binary files a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/vivado.pb and /dev/null differ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/.Vivado_Synthesis.queue.rst b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/.Vivado_Synthesis.queue.rst deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/.vivado.begin.rst b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/.vivado.begin.rst deleted file mode 100644 index 76583712..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/.vivado.end.rst b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/.vivado.end.rst deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/ISEWrap.js b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/ISEWrap.js deleted file mode 100644 index 97a2ecbc..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/ISEWrap.js +++ /dev/null @@ -1,270 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/ISEWrap.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/ISEWrap.sh deleted file mode 100644 index f679f2e8..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/__synthesis_is_complete__ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m.dcp b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m.dcp deleted file mode 100644 index 3d15d674..00000000 Binary files a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m.dcp and /dev/null differ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m.tcl b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m.tcl deleted file mode 100644 index 1ee9a65c..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m.tcl +++ /dev/null @@ -1,156 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param general.maxThreads 20 -set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64 -set_param project.vivado.isBlockSynthRun true -set_msg_config -msgmgr_mode ooc_run -create_project -in_memory -part xc7k410tffg900-2 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] -set_property parent.project_path D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.xpr [current_project] -set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language Verilog [current_project] -set_property ip_output_repo d:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/data_1p5m/data_1p5m.xci -set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/data_1p5m/data_1p5m_ooc.xdc] - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -read_xdc dont_touch.xdc -set_property used_in_implementation false [get_files dont_touch.xdc] -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1 -new_name data_1p5m -ip [get_ips data_1p5m]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top data_1p5m -part xc7k410tffg900-2 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix data_1p5m_ data_1p5m.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ data_1p5m_stub.v - lappend ipCachedFiles data_1p5m_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ data_1p5m_stub.vhdl - lappend ipCachedFiles data_1p5m_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ data_1p5m_sim_netlist.v - lappend ipCachedFiles data_1p5m_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ data_1p5m_sim_netlist.vhdl - lappend ipCachedFiles data_1p5m_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp data_1p5m.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips data_1p5m] -} - -rename_ref -prefix_all data_1p5m_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef data_1p5m.dcp -create_report "data_1p5m_synth_1_synth_report_utilization_0" "report_utilization -file data_1p5m_utilization_synth.rpt -pb data_1p5m_utilization_synth.pb" - -if { [catch { - write_verilog -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -}; # end if cached_ip - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_stub.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/data_1p5m/data_1p5m.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_stub.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/data_1p5m/data_1p5m.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_sim_netlist.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/data_1p5m/data_1p5m.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/data_1p5m/data_1p5m.xci] - -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m.dcp -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/data_1p5m/data_1p5m.xci] - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/data_1p5m]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_sim_netlist.v D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/data_1p5m - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/data_1p5m]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_sim_netlist.vhdl D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/data_1p5m - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/data_1p5m]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_stub.v D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/data_1p5m - } -} - -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/data_1p5m]} { - catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_stub.vhdl D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/data_1p5m - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m.vds b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m.vds deleted file mode 100644 index 46343525..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m.vds +++ /dev/null @@ -1,461 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Sat Mar 18 23:32:54 2023 -# Process ID: 29504 -# Current directory: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1 -# Command line: vivado.exe -log data_1p5m.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source data_1p5m.tcl -# Log file: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m.vds -# Journal file: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1\vivado.jou -#----------------------------------------------------------- -Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl' -source data_1p5m.tcl -notrace -Command: synth_design -top data_1p5m -part xc7k410tffg900-2 -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' -INFO: [Device 21-403] Loading part xc7k410tffg900-2 -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 30372 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 883.863 ; gain = 177.320 ---------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'data_1p5m' [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/data_1p5m/synth/data_1p5m.vhd:68] - Parameter C_FAMILY bound to: kintex7 - type: string - Parameter C_XDEVICEFAMILY bound to: kintex7 - type: string - Parameter C_ELABORATION_DIR bound to: ./ - type: string - Parameter C_INTERFACE_TYPE bound to: 0 - type: integer - Parameter C_AXI_TYPE bound to: 1 - type: integer - Parameter C_AXI_SLAVE_TYPE bound to: 0 - type: integer - Parameter C_USE_BRAM_BLOCK bound to: 0 - type: integer - Parameter C_ENABLE_32BIT_ADDRESS bound to: 0 - type: integer - Parameter C_CTRL_ECC_ALGO bound to: NONE - type: string - Parameter C_HAS_AXI_ID bound to: 0 - type: integer - Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer - Parameter C_MEM_TYPE bound to: 3 - type: integer - Parameter C_BYTE_SIZE bound to: 9 - type: integer - Parameter C_ALGORITHM bound to: 1 - type: integer - Parameter C_PRIM_TYPE bound to: 1 - type: integer - Parameter C_LOAD_INIT_FILE bound to: 1 - type: integer - Parameter C_INIT_FILE_NAME bound to: data_1p5m.mif - type: string - Parameter C_INIT_FILE bound to: data_1p5m.mem - type: string - Parameter C_USE_DEFAULT_DATA bound to: 0 - type: integer - Parameter C_DEFAULT_DATA bound to: 0 - type: string - Parameter C_HAS_RSTA bound to: 0 - type: integer - Parameter C_RST_PRIORITY_A bound to: CE - type: string - Parameter C_RSTRAM_A bound to: 0 - type: integer - Parameter C_INITA_VAL bound to: 0 - type: string - Parameter C_HAS_ENA bound to: 1 - type: integer - Parameter C_HAS_REGCEA bound to: 0 - type: integer - Parameter C_USE_BYTE_WEA bound to: 0 - type: integer - Parameter C_WEA_WIDTH bound to: 1 - type: integer - Parameter C_WRITE_MODE_A bound to: WRITE_FIRST - type: string - Parameter C_WRITE_WIDTH_A bound to: 1 - type: integer - Parameter C_READ_WIDTH_A bound to: 1 - type: integer - Parameter C_WRITE_DEPTH_A bound to: 2048 - type: integer - Parameter C_READ_DEPTH_A bound to: 2048 - type: integer - Parameter C_ADDRA_WIDTH bound to: 11 - type: integer - Parameter C_HAS_RSTB bound to: 0 - type: integer - Parameter C_RST_PRIORITY_B bound to: CE - type: string - Parameter C_RSTRAM_B bound to: 0 - type: integer - Parameter C_INITB_VAL bound to: 0 - type: string - Parameter C_HAS_ENB bound to: 0 - type: integer - Parameter C_HAS_REGCEB bound to: 0 - type: integer - Parameter C_USE_BYTE_WEB bound to: 0 - type: integer - Parameter C_WEB_WIDTH bound to: 1 - type: integer - Parameter C_WRITE_MODE_B bound to: WRITE_FIRST - type: string - Parameter C_WRITE_WIDTH_B bound to: 1 - type: integer - Parameter C_READ_WIDTH_B bound to: 1 - type: integer - Parameter C_WRITE_DEPTH_B bound to: 2048 - type: integer - Parameter C_READ_DEPTH_B bound to: 2048 - type: integer - Parameter C_ADDRB_WIDTH bound to: 11 - type: integer - Parameter C_HAS_MEM_OUTPUT_REGS_A bound to: 1 - type: integer - Parameter C_HAS_MEM_OUTPUT_REGS_B bound to: 0 - type: integer - Parameter C_HAS_MUX_OUTPUT_REGS_A bound to: 1 - type: integer - Parameter C_HAS_MUX_OUTPUT_REGS_B bound to: 0 - type: integer - Parameter C_MUX_PIPELINE_STAGES bound to: 0 - type: integer - Parameter C_HAS_SOFTECC_INPUT_REGS_A bound to: 0 - type: integer - Parameter C_HAS_SOFTECC_OUTPUT_REGS_B bound to: 0 - type: integer - Parameter C_USE_SOFTECC bound to: 0 - type: integer - Parameter C_USE_ECC bound to: 0 - type: integer - Parameter C_EN_ECC_PIPE bound to: 0 - type: integer - Parameter C_READ_LATENCY_A bound to: 1 - type: integer - Parameter C_READ_LATENCY_B bound to: 1 - type: integer - Parameter C_HAS_INJECTERR bound to: 0 - type: integer - Parameter C_SIM_COLLISION_CHECK bound to: ALL - type: string - Parameter C_COMMON_CLK bound to: 0 - type: integer - Parameter C_DISABLE_WARN_BHV_COLL bound to: 0 - type: integer - Parameter C_EN_SLEEP_PIN bound to: 0 - type: integer - Parameter C_USE_URAM bound to: 0 - type: integer - Parameter C_EN_RDADDRA_CHG bound to: 0 - type: integer - Parameter C_EN_RDADDRB_CHG bound to: 0 - type: integer - Parameter C_EN_DEEPSLEEP_PIN bound to: 0 - type: integer - Parameter C_EN_SHUTDOWN_PIN bound to: 0 - type: integer - Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer - Parameter C_DISABLE_WARN_BHV_RANGE bound to: 0 - type: integer - Parameter C_COUNT_36K_BRAM bound to: 0 - type: string - Parameter C_COUNT_18K_BRAM bound to: 1 - type: string - Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP : 0.990811 mW - type: string -INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_3' declared at 'd:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/data_1p5m/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195321' bound to instance 'U0' of component 'blk_mem_gen_v8_4_3' [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/data_1p5m/synth/data_1p5m.vhd:232] -INFO: [Synth 8-256] done synthesizing module 'data_1p5m' (9#1) [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/data_1p5m/synth/data_1p5m.vhd:68] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRA -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port CLKB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ENB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port REGCEB -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port WEB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[10] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[9] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[8] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[7] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[6] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[5] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[4] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[3] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[2] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[1] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[8] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[7] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[6] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[5] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[4] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[3] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[2] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[1] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SLEEP -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port INJECTSBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port INJECTDBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ECCPIPECE -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ram_rstram_b -WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ram_rstreg_b -WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port RSTA[1] -WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port RSTA[0] -WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port REGCEB[0] -WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port INJECTSBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port INJECTDBITERR -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port CLKB -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[0] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port SBITERR_I -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DBITERR_I -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[10] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[9] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[8] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[7] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[6] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[5] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[4] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[3] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[2] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[1] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[0] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port RSTA -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port REGCEA -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port WEA[0] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[0] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port CLKB -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port RSTB -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port ENB -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port REGCEB -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port WEB[0] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port ADDRB[10] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port ADDRB[9] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port ADDRB[8] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port ADDRB[7] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port ADDRB[6] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port ADDRB[5] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port ADDRB[4] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port ADDRB[3] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port ADDRB[2] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port ADDRB[1] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port ADDRB[0] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINB[0] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port INJECTDBITERR -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port INJECTSBITERR -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AClk -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_ARESETN -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWID[3] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWID[2] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWID[1] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWID[0] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWADDR[31] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWADDR[30] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWADDR[29] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWADDR[28] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWADDR[27] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWADDR[26] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWADDR[25] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWADDR[24] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWADDR[23] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWADDR[22] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWADDR[21] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWADDR[20] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWADDR[19] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWADDR[18] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWADDR[17] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWADDR[16] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWADDR[15] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWADDR[14] -WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_synth has unconnected port S_AXI_AWADDR[13] -INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 1164.984 ; gain = 458.441 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 1164.984 ; gain = 458.441 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 1164.984 ; gain = 458.441 ---------------------------------------------------------------------------------- -INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization - -Processing XDC Constraints -Initializing timing engine -Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/data_1p5m/data_1p5m_ooc.xdc] for cell 'U0' -Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/data_1p5m/data_1p5m_ooc.xdc] for cell 'U0' -Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/dont_touch.xdc] -Finished Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/dont_touch.xdc] -Completed Processing XDC Constraints - -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1164.984 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1164.984 ; gain = 0.000 ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:45 ; elapsed = 00:00:59 . Memory (MB): peak = 1164.984 ; gain = 458.441 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7k410tffg900-2 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:45 ; elapsed = 00:00:59 . Memory (MB): peak = 1164.984 ; gain = 458.441 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying 'set_property' XDC Constraints ---------------------------------------------------------------------------------- -Applied set_property DONT_TOUCH = true for U0. (constraint file D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/dont_touch.xdc, line 9). ---------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:45 ; elapsed = 00:00:59 . Memory (MB): peak = 1164.984 ; gain = 458.441 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:45 ; elapsed = 00:00:59 . Memory (MB): peak = 1164.984 ; gain = 458.441 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- -Hierarchical RTL Component report -Module blk_mem_gen_generic_cstr -Detailed RTL Component Info : -+---Registers : - 1 Bit Registers := 1 ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 1540 (col length:140) -BRAMs: 1590 (col length: RAMB18 140 RAMB36 70) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:46 ; elapsed = 00:01:00 . Memory (MB): peak = 1164.984 ; gain = 458.441 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Applying XDC Timing Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:51 ; elapsed = 00:01:06 . Memory (MB): peak = 1164.984 ; gain = 458.441 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:51 ; elapsed = 00:01:06 . Memory (MB): peak = 1164.984 ; gain = 458.441 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:51 ; elapsed = 00:01:06 . Memory (MB): peak = 1164.984 ; gain = 458.441 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:52 ; elapsed = 00:01:08 . Memory (MB): peak = 1164.984 ; gain = 458.441 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:52 ; elapsed = 00:01:08 . Memory (MB): peak = 1164.984 ; gain = 458.441 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:52 ; elapsed = 00:01:08 . Memory (MB): peak = 1164.984 ; gain = 458.441 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:52 ; elapsed = 00:01:08 . Memory (MB): peak = 1164.984 ; gain = 458.441 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:52 ; elapsed = 00:01:08 . Memory (MB): peak = 1164.984 ; gain = 458.441 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:52 ; elapsed = 00:01:08 . Memory (MB): peak = 1164.984 ; gain = 458.441 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+---------+------+ -| |Cell |Count | -+------+---------+------+ -|1 |RAMB18E1 | 1| -|2 |FDRE | 1| -+------+---------+------+ - -Report Instance Areas: -+------+---------------------------------------------+------------------------------+------+ -| |Instance |Module |Cells | -+------+---------------------------------------------+------------------------------+------+ -|1 |top | | 2| -|2 | U0 |blk_mem_gen_v8_4_3 | 2| -|3 | inst_blk_mem_gen |blk_mem_gen_v8_4_3_synth | 2| -|4 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_top | 2| -|5 | \valid.cstr |blk_mem_gen_generic_cstr | 2| -|6 | \ramloop[0].ram.r |blk_mem_gen_prim_width | 1| -|7 | \prim_init.ram |blk_mem_gen_prim_wrapper_init | 1| -+------+---------------------------------------------+------------------------------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:52 ; elapsed = 00:01:08 . Memory (MB): peak = 1164.984 ; gain = 458.441 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 136 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:01:05 . Memory (MB): peak = 1164.984 ; gain = 458.441 -Synthesis Optimization Complete : Time (s): cpu = 00:00:52 ; elapsed = 00:01:08 . Memory (MB): peak = 1164.984 ; gain = 458.441 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1164.984 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -17 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:16 . Memory (MB): peak = 1164.984 ; gain = 778.656 -INFO: [Common 17-600] The following parameters have non-default value. -general.maxThreads -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1164.984 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m.dcp' has been generated. -WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP data_1p5m, cache-ID = a7e4491a454f9323 -INFO: [Coretcl 2-1174] Renamed 6 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1164.984 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file data_1p5m_utilization_synth.rpt -pb data_1p5m_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sat Mar 18 23:34:17 2023... diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_sim_netlist.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_sim_netlist.v deleted file mode 100644 index fb64abdb..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_sim_netlist.v +++ /dev/null @@ -1,734 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:34:17 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_sim_netlist.v -// Design : data_1p5m -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* CHECK_LICENSE_TYPE = "data_1p5m,blk_mem_gen_v8_4_3,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) -(* NotValidForBitStream *) -module data_1p5m - (clka, - ena, - addra, - douta); - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) input clka; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [10:0]addra; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [0:0]douta; - - wire [10:0]addra; - wire clka; - wire [0:0]douta; - wire ena; - wire NLW_U0_dbiterr_UNCONNECTED; - wire NLW_U0_rsta_busy_UNCONNECTED; - wire NLW_U0_rstb_busy_UNCONNECTED; - wire NLW_U0_s_axi_arready_UNCONNECTED; - wire NLW_U0_s_axi_awready_UNCONNECTED; - wire NLW_U0_s_axi_bvalid_UNCONNECTED; - wire NLW_U0_s_axi_dbiterr_UNCONNECTED; - wire NLW_U0_s_axi_rlast_UNCONNECTED; - wire NLW_U0_s_axi_rvalid_UNCONNECTED; - wire NLW_U0_s_axi_sbiterr_UNCONNECTED; - wire NLW_U0_s_axi_wready_UNCONNECTED; - wire NLW_U0_sbiterr_UNCONNECTED; - wire [0:0]NLW_U0_doutb_UNCONNECTED; - wire [10:0]NLW_U0_rdaddrecc_UNCONNECTED; - wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED; - wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; - wire [10:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED; - wire [0:0]NLW_U0_s_axi_rdata_UNCONNECTED; - wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED; - wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; - - (* C_ADDRA_WIDTH = "11" *) - (* C_ADDRB_WIDTH = "11" *) - (* C_ALGORITHM = "1" *) - (* C_AXI_ID_WIDTH = "4" *) - (* C_AXI_SLAVE_TYPE = "0" *) - (* C_AXI_TYPE = "1" *) - (* C_BYTE_SIZE = "9" *) - (* C_COMMON_CLK = "0" *) - (* C_COUNT_18K_BRAM = "1" *) - (* C_COUNT_36K_BRAM = "0" *) - (* C_CTRL_ECC_ALGO = "NONE" *) - (* C_DEFAULT_DATA = "0" *) - (* C_DISABLE_WARN_BHV_COLL = "0" *) - (* C_DISABLE_WARN_BHV_RANGE = "0" *) - (* C_ELABORATION_DIR = "./" *) - (* C_ENABLE_32BIT_ADDRESS = "0" *) - (* C_EN_DEEPSLEEP_PIN = "0" *) - (* C_EN_ECC_PIPE = "0" *) - (* C_EN_RDADDRA_CHG = "0" *) - (* C_EN_RDADDRB_CHG = "0" *) - (* C_EN_SAFETY_CKT = "0" *) - (* C_EN_SHUTDOWN_PIN = "0" *) - (* C_EN_SLEEP_PIN = "0" *) - (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 0.990811 mW" *) - (* C_FAMILY = "kintex7" *) - (* C_HAS_AXI_ID = "0" *) - (* C_HAS_ENA = "1" *) - (* C_HAS_ENB = "0" *) - (* C_HAS_INJECTERR = "0" *) - (* C_HAS_MEM_OUTPUT_REGS_A = "1" *) - (* C_HAS_MEM_OUTPUT_REGS_B = "0" *) - (* C_HAS_MUX_OUTPUT_REGS_A = "1" *) - (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) - (* C_HAS_REGCEA = "0" *) - (* C_HAS_REGCEB = "0" *) - (* C_HAS_RSTA = "0" *) - (* C_HAS_RSTB = "0" *) - (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) - (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) - (* C_INITA_VAL = "0" *) - (* C_INITB_VAL = "0" *) - (* C_INIT_FILE = "data_1p5m.mem" *) - (* C_INIT_FILE_NAME = "data_1p5m.mif" *) - (* C_INTERFACE_TYPE = "0" *) - (* C_LOAD_INIT_FILE = "1" *) - (* C_MEM_TYPE = "3" *) - (* C_MUX_PIPELINE_STAGES = "0" *) - (* C_PRIM_TYPE = "1" *) - (* C_READ_DEPTH_A = "2048" *) - (* C_READ_DEPTH_B = "2048" *) - (* C_READ_LATENCY_A = "1" *) - (* C_READ_LATENCY_B = "1" *) - (* C_READ_WIDTH_A = "1" *) - (* C_READ_WIDTH_B = "1" *) - (* C_RSTRAM_A = "0" *) - (* C_RSTRAM_B = "0" *) - (* C_RST_PRIORITY_A = "CE" *) - (* C_RST_PRIORITY_B = "CE" *) - (* C_SIM_COLLISION_CHECK = "ALL" *) - (* C_USE_BRAM_BLOCK = "0" *) - (* C_USE_BYTE_WEA = "0" *) - (* C_USE_BYTE_WEB = "0" *) - (* C_USE_DEFAULT_DATA = "0" *) - (* C_USE_ECC = "0" *) - (* C_USE_SOFTECC = "0" *) - (* C_USE_URAM = "0" *) - (* C_WEA_WIDTH = "1" *) - (* C_WEB_WIDTH = "1" *) - (* C_WRITE_DEPTH_A = "2048" *) - (* C_WRITE_DEPTH_B = "2048" *) - (* C_WRITE_MODE_A = "WRITE_FIRST" *) - (* C_WRITE_MODE_B = "WRITE_FIRST" *) - (* C_WRITE_WIDTH_A = "1" *) - (* C_WRITE_WIDTH_B = "1" *) - (* C_XDEVICEFAMILY = "kintex7" *) - (* downgradeipidentifiedwarnings = "yes" *) - data_1p5m_blk_mem_gen_v8_4_3 U0 - (.addra(addra), - .addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .clka(clka), - .clkb(1'b0), - .dbiterr(NLW_U0_dbiterr_UNCONNECTED), - .deepsleep(1'b0), - .dina(1'b0), - .dinb(1'b0), - .douta(douta), - .doutb(NLW_U0_doutb_UNCONNECTED[0]), - .eccpipece(1'b0), - .ena(ena), - .enb(1'b0), - .injectdbiterr(1'b0), - .injectsbiterr(1'b0), - .rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[10:0]), - .regcea(1'b0), - .regceb(1'b0), - .rsta(1'b0), - .rsta_busy(NLW_U0_rsta_busy_UNCONNECTED), - .rstb(1'b0), - .rstb_busy(NLW_U0_rstb_busy_UNCONNECTED), - .s_aclk(1'b0), - .s_aresetn(1'b0), - .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_arburst({1'b0,1'b0}), - .s_axi_arid({1'b0,1'b0,1'b0,1'b0}), - .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED), - .s_axi_arsize({1'b0,1'b0,1'b0}), - .s_axi_arvalid(1'b0), - .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_awburst({1'b0,1'b0}), - .s_axi_awid({1'b0,1'b0,1'b0,1'b0}), - .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED), - .s_axi_awsize({1'b0,1'b0,1'b0}), - .s_axi_awvalid(1'b0), - .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]), - .s_axi_bready(1'b0), - .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]), - .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED), - .s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED), - .s_axi_injectdbiterr(1'b0), - .s_axi_injectsbiterr(1'b0), - .s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[10:0]), - .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[0]), - .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]), - .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED), - .s_axi_rready(1'b0), - .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]), - .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED), - .s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED), - .s_axi_wdata(1'b0), - .s_axi_wlast(1'b0), - .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED), - .s_axi_wstrb(1'b0), - .s_axi_wvalid(1'b0), - .sbiterr(NLW_U0_sbiterr_UNCONNECTED), - .shutdown(1'b0), - .sleep(1'b0), - .wea(1'b0), - .web(1'b0)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) -module data_1p5m_blk_mem_gen_generic_cstr - (douta, - clka, - ena, - addra); - output [0:0]douta; - input clka; - input ena; - input [10:0]addra; - - wire [10:0]addra; - wire clka; - wire [0:0]douta; - wire ena; - wire ram_douta; - - FDRE #( - .INIT(1'b0)) - \mux_a_wire.mux_reg.ce_pri.douta_i_reg[0] - (.C(clka), - .CE(ena), - .D(ram_douta), - .Q(douta), - .R(1'b0)); - data_1p5m_blk_mem_gen_prim_width \ramloop[0].ram.r - (.DOADO(ram_douta), - .addra(addra), - .clka(clka), - .ena(ena)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) -module data_1p5m_blk_mem_gen_prim_width - (DOADO, - clka, - ena, - addra); - output [0:0]DOADO; - input clka; - input ena; - input [10:0]addra; - - wire [0:0]DOADO; - wire [10:0]addra; - wire clka; - wire ena; - - data_1p5m_blk_mem_gen_prim_wrapper_init \prim_init.ram - (.DOADO(DOADO), - .addra(addra), - .clka(clka), - .ena(ena)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) -module data_1p5m_blk_mem_gen_prim_wrapper_init - (DOADO, - clka, - ena, - addra); - output [0:0]DOADO; - input clka; - input ena; - input [10:0]addra; - - wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_10 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_11 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_12 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_13 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_14 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_8 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_9 ; - wire [0:0]DOADO; - wire [10:0]addra; - wire clka; - wire ena; - wire [15:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ; - wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ; - wire [1:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ; - wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ; - - (* box_type = "PRIMITIVE" *) - RAMB18E1 #( - .DOA_REG(1), - .DOB_REG(0), - .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_00(256'h0101000001010101000101000001010100010100010101000101000100010001), - .INIT_01(256'h0000010001000000010100000100010100000100010101000100000100000101), - .INIT_02(256'h0001000000010001010000010101000100010100000000010100000001010001), - .INIT_03(256'h0100000101000100010000010000000101010000000001000000000101000001), - .INIT_04(256'h0001010101010000000001000100010100000001010000010001000101010000), - .INIT_05(256'h0101010100010000000101000101010101000100010000010001010000000101), - .INIT_06(256'h0101010100010100010001010001010000000001000001010100000000010101), - .INIT_07(256'h0000010100010000000101010001000000000100010000000100010001000001), - .INIT_08(256'h0101000101010101010000000000000001000000010001000001000100000100), - .INIT_09(256'h0000010000000101000100010001000000000101000001010001010100010001), - .INIT_0A(256'h0000000101000100000001000001000100000100000101010100010100000101), - .INIT_0B(256'h0100010001000000010101000101010001010000010101010101000001010100), - .INIT_0C(256'h0100010101010001000101010101000000010100010100000000000101010100), - .INIT_0D(256'h0001010001010000000000010000010100000000010100010001000001010101), - .INIT_0E(256'h0000010000010001000000000001000100000000010000000101000100000100), - .INIT_0F(256'h0000010101010100000000000000010101010001000001000100010101010101), - .INIT_10(256'h0101000100010001010100010101000101010000010101010000000001000000), - .INIT_11(256'h0101010100000000000001000000010000000100000001000001000001000001), - .INIT_12(256'h0000000101010101000001000100010100010000010000010100010101000101), - .INIT_13(256'h0100000000000000000100000100010000010000000101010101000101000100), - .INIT_14(256'h0101010101010100010001000100010001010100000100000101010101010001), - .INIT_15(256'h0100010000010101000000010001000001000100000001010001010000010000), - .INIT_16(256'h0100000001000101000101010100000100000101000101000101010000010001), - .INIT_17(256'h0100010001000100000101000000010000000000000000010000010001010000), - .INIT_18(256'h0000010100000100000101010101000000000101010101010001010100010100), - .INIT_19(256'h0100000100010001000100010000010000000100000000010001010001010100), - .INIT_1A(256'h0001010100010001000100000100000000010100010001010100010100010001), - .INIT_1B(256'h0100010000000101010000010101010100000000010001000000010000000001), - .INIT_1C(256'h0101000000010100000000010100010100000001000000000100000100010100), - .INIT_1D(256'h0101010101000101000100000100000000000001010001000101010100000001), - .INIT_1E(256'h0101010100010001010000010101000100000100000100000000000101000000), - .INIT_1F(256'h0101010000000100000001010001010001010001000001000001000001000101), - .INIT_20(256'h0101000100010000010001000101010100010000010001010101000100010001), - .INIT_21(256'h0001000001000100010000010101000001000100010101010100010100000101), - .INIT_22(256'h0101000100010101010101010001000100000100000001000000010101000100), - .INIT_23(256'h0000000000010101010100010001010100010101010001000001010100000000), - .INIT_24(256'h0100000000010000000100000100000101000100000100010001010000000001), - .INIT_25(256'h0001010100000001010000010000000001010000000100000100000101010100), - .INIT_26(256'h0001010101010000010101000001000000010001010101000000010000010100), - .INIT_27(256'h0001000000010100010101010001000100000000000000000001010000010101), - .INIT_28(256'h0101010101010001010101010100000100000100000000000001000100000000), - .INIT_29(256'h0100000100010101000001000101010001000001000000010001010001000100), - .INIT_2A(256'h0001000000010000010001000101000101000101010000000100000000000101), - .INIT_2B(256'h0100010101000000000101000101000001000101010101010100000001000101), - .INIT_2C(256'h0101010000000001000001000100010100000000000100010001000101010001), - .INIT_2D(256'h0001010000000101000100000101000000000001000100000100000000010001), - .INIT_2E(256'h0001010101010000010101010000010000000000010001000100000000000001), - .INIT_2F(256'h0000010101000100010000010000000000010101010100000001000001000000), - .INIT_30(256'h0101000100000100010000000000000101010001000100000100000101000101), - .INIT_31(256'h0000000000000001010001000100010001000000010101010001000100000001), - .INIT_32(256'h0101000100010001010101010101000100000101010100000101000101000101), - .INIT_33(256'h0000010101000101000101010001010001010101010000010101010001010101), - .INIT_34(256'h0101000000010001010100010000010100000001000000000101000001010100), - .INIT_35(256'h0001000001000100000101000001000101010001000100010101010100000000), - .INIT_36(256'h0000010100010000010101010001010101000001010101000001000001000101), - .INIT_37(256'h0001000101000101000000010101000101010100000100010101000000010001), - .INIT_38(256'h0000000001010101000000000100000101000001010001000100010100010001), - .INIT_39(256'h0000010101000001000000010000000100010001010100010001010101000101), - .INIT_3A(256'h0101010100000100000000000001000000010100010000010001000101010001), - .INIT_3B(256'h0001010100010101010100000001010101010101010000010001000100010001), - .INIT_3C(256'h0000000001010000000100000101000101000101010100000000010100010101), - .INIT_3D(256'h0001000101000000010000000100010100010101010001000000000000010001), - .INIT_3E(256'h0000000101000100000000010000010000010100010001000000010100000100), - .INIT_3F(256'h0100000000010001000100010100000101000000010100000101010100010000), - .INIT_A(18'h00000), - .INIT_B(18'h00000), - .INIT_FILE("NONE"), - .IS_CLKARDCLK_INVERTED(1'b0), - .IS_CLKBWRCLK_INVERTED(1'b0), - .IS_ENARDEN_INVERTED(1'b0), - .IS_ENBWREN_INVERTED(1'b0), - .IS_RSTRAMARSTRAM_INVERTED(1'b0), - .IS_RSTRAMB_INVERTED(1'b0), - .IS_RSTREGARSTREG_INVERTED(1'b0), - .IS_RSTREGB_INVERTED(1'b0), - .RAM_MODE("TDP"), - .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), - .READ_WIDTH_A(9), - .READ_WIDTH_B(9), - .RSTREG_PRIORITY_A("REGCE"), - .RSTREG_PRIORITY_B("REGCE"), - .SIM_COLLISION_CHECK("ALL"), - .SIM_DEVICE("7SERIES"), - .SRVAL_A(18'h00000), - .SRVAL_B(18'h00000), - .WRITE_MODE_A("WRITE_FIRST"), - .WRITE_MODE_B("WRITE_FIRST"), - .WRITE_WIDTH_A(9), - .WRITE_WIDTH_B(9)) - \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram - (.ADDRARDADDR({addra,1'b0,1'b0,1'b0}), - .ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .CLKARDCLK(clka), - .CLKBWRCLK(clka), - .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIPADIP({1'b0,1'b0}), - .DIPBDIP({1'b0,1'b0}), - .DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:8],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_8 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_9 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_10 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_11 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_12 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_13 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_14 ,DOADO}), - .DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]), - .DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33 }), - .DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]), - .ENARDEN(ena), - .ENBWREN(1'b0), - .REGCEAREGCE(ena), - .REGCEB(1'b0), - .RSTRAMARSTRAM(1'b0), - .RSTRAMB(1'b0), - .RSTREGARSTREG(1'b0), - .RSTREGB(1'b0), - .WEA({1'b0,1'b0}), - .WEBWE({1'b0,1'b0,1'b0,1'b0})); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_top" *) -module data_1p5m_blk_mem_gen_top - (douta, - clka, - ena, - addra); - output [0:0]douta; - input clka; - input ena; - input [10:0]addra; - - wire [10:0]addra; - wire clka; - wire [0:0]douta; - wire ena; - - data_1p5m_blk_mem_gen_generic_cstr \valid.cstr - (.addra(addra), - .clka(clka), - .douta(douta), - .ena(ena)); -endmodule - -(* C_ADDRA_WIDTH = "11" *) (* C_ADDRB_WIDTH = "11" *) (* C_ALGORITHM = "1" *) -(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *) -(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *) -(* C_COUNT_36K_BRAM = "0" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *) -(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *) -(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *) -(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *) -(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 0.990811 mW" *) -(* C_FAMILY = "kintex7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *) -(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *) -(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "1" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) -(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *) -(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) -(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "data_1p5m.mem" *) -(* C_INIT_FILE_NAME = "data_1p5m.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *) -(* C_MEM_TYPE = "3" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *) -(* C_READ_DEPTH_A = "2048" *) (* C_READ_DEPTH_B = "2048" *) (* C_READ_LATENCY_A = "1" *) -(* C_READ_LATENCY_B = "1" *) (* C_READ_WIDTH_A = "1" *) (* C_READ_WIDTH_B = "1" *) -(* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *) -(* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *) -(* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *) -(* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *) -(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "2048" *) -(* C_WRITE_DEPTH_B = "2048" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) -(* C_WRITE_WIDTH_A = "1" *) (* C_WRITE_WIDTH_B = "1" *) (* C_XDEVICEFAMILY = "kintex7" *) -(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3" *) (* downgradeipidentifiedwarnings = "yes" *) -module data_1p5m_blk_mem_gen_v8_4_3 - (clka, - rsta, - ena, - regcea, - wea, - addra, - dina, - douta, - clkb, - rstb, - enb, - regceb, - web, - addrb, - dinb, - doutb, - injectsbiterr, - injectdbiterr, - eccpipece, - sbiterr, - dbiterr, - rdaddrecc, - sleep, - deepsleep, - shutdown, - rsta_busy, - rstb_busy, - s_aclk, - s_aresetn, - s_axi_awid, - s_axi_awaddr, - s_axi_awlen, - s_axi_awsize, - s_axi_awburst, - s_axi_awvalid, - s_axi_awready, - s_axi_wdata, - s_axi_wstrb, - s_axi_wlast, - s_axi_wvalid, - s_axi_wready, - s_axi_bid, - s_axi_bresp, - s_axi_bvalid, - s_axi_bready, - s_axi_arid, - s_axi_araddr, - s_axi_arlen, - s_axi_arsize, - s_axi_arburst, - s_axi_arvalid, - s_axi_arready, - s_axi_rid, - s_axi_rdata, - s_axi_rresp, - s_axi_rlast, - s_axi_rvalid, - s_axi_rready, - s_axi_injectsbiterr, - s_axi_injectdbiterr, - s_axi_sbiterr, - s_axi_dbiterr, - s_axi_rdaddrecc); - input clka; - input rsta; - input ena; - input regcea; - input [0:0]wea; - input [10:0]addra; - input [0:0]dina; - output [0:0]douta; - input clkb; - input rstb; - input enb; - input regceb; - input [0:0]web; - input [10:0]addrb; - input [0:0]dinb; - output [0:0]doutb; - input injectsbiterr; - input injectdbiterr; - input eccpipece; - output sbiterr; - output dbiterr; - output [10:0]rdaddrecc; - input sleep; - input deepsleep; - input shutdown; - output rsta_busy; - output rstb_busy; - input s_aclk; - input s_aresetn; - input [3:0]s_axi_awid; - input [31:0]s_axi_awaddr; - input [7:0]s_axi_awlen; - input [2:0]s_axi_awsize; - input [1:0]s_axi_awburst; - input s_axi_awvalid; - output s_axi_awready; - input [0:0]s_axi_wdata; - input [0:0]s_axi_wstrb; - input s_axi_wlast; - input s_axi_wvalid; - output s_axi_wready; - output [3:0]s_axi_bid; - output [1:0]s_axi_bresp; - output s_axi_bvalid; - input s_axi_bready; - input [3:0]s_axi_arid; - input [31:0]s_axi_araddr; - input [7:0]s_axi_arlen; - input [2:0]s_axi_arsize; - input [1:0]s_axi_arburst; - input s_axi_arvalid; - output s_axi_arready; - output [3:0]s_axi_rid; - output [0:0]s_axi_rdata; - output [1:0]s_axi_rresp; - output s_axi_rlast; - output s_axi_rvalid; - input s_axi_rready; - input s_axi_injectsbiterr; - input s_axi_injectdbiterr; - output s_axi_sbiterr; - output s_axi_dbiterr; - output [10:0]s_axi_rdaddrecc; - - wire \ ; - wire [10:0]addra; - wire clka; - wire [0:0]douta; - wire ena; - - assign dbiterr = \ ; - assign doutb[0] = \ ; - assign rdaddrecc[10] = \ ; - assign rdaddrecc[9] = \ ; - assign rdaddrecc[8] = \ ; - assign rdaddrecc[7] = \ ; - assign rdaddrecc[6] = \ ; - assign rdaddrecc[5] = \ ; - assign rdaddrecc[4] = \ ; - assign rdaddrecc[3] = \ ; - assign rdaddrecc[2] = \ ; - assign rdaddrecc[1] = \ ; - assign rdaddrecc[0] = \ ; - assign rsta_busy = \ ; - assign rstb_busy = \ ; - assign s_axi_arready = \ ; - assign s_axi_awready = \ ; - assign s_axi_bid[3] = \ ; - assign s_axi_bid[2] = \ ; - assign s_axi_bid[1] = \ ; - assign s_axi_bid[0] = \ ; - assign s_axi_bresp[1] = \ ; - assign s_axi_bresp[0] = \ ; - assign s_axi_bvalid = \ ; - assign s_axi_dbiterr = \ ; - assign s_axi_rdaddrecc[10] = \ ; - assign s_axi_rdaddrecc[9] = \ ; - assign s_axi_rdaddrecc[8] = \ ; - assign s_axi_rdaddrecc[7] = \ ; - assign s_axi_rdaddrecc[6] = \ ; - assign s_axi_rdaddrecc[5] = \ ; - assign s_axi_rdaddrecc[4] = \ ; - assign s_axi_rdaddrecc[3] = \ ; - assign s_axi_rdaddrecc[2] = \ ; - assign s_axi_rdaddrecc[1] = \ ; - assign s_axi_rdaddrecc[0] = \ ; - assign s_axi_rdata[0] = \ ; - assign s_axi_rid[3] = \ ; - assign s_axi_rid[2] = \ ; - assign s_axi_rid[1] = \ ; - assign s_axi_rid[0] = \ ; - assign s_axi_rlast = \ ; - assign s_axi_rresp[1] = \ ; - assign s_axi_rresp[0] = \ ; - assign s_axi_rvalid = \ ; - assign s_axi_sbiterr = \ ; - assign s_axi_wready = \ ; - assign sbiterr = \ ; - GND GND - (.G(\ )); - data_1p5m_blk_mem_gen_v8_4_3_synth inst_blk_mem_gen - (.addra(addra), - .clka(clka), - .douta(douta), - .ena(ena)); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3_synth" *) -module data_1p5m_blk_mem_gen_v8_4_3_synth - (douta, - clka, - ena, - addra); - output [0:0]douta; - input clka; - input ena; - input [10:0]addra; - - wire [10:0]addra; - wire clka; - wire [0:0]douta; - wire ena; - - data_1p5m_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen - (.addra(addra), - .clka(clka), - .douta(douta), - .ena(ena)); -endmodule -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_sim_netlist.vhdl deleted file mode 100644 index bcd24484..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_sim_netlist.vhdl +++ /dev/null @@ -1,849 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:34:17 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_sim_netlist.vhdl --- Design : data_1p5m --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity data_1p5m_blk_mem_gen_prim_wrapper_init is - port ( - DOADO : out STD_LOGIC_VECTOR ( 0 to 0 ); - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of data_1p5m_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; -end data_1p5m_blk_mem_gen_prim_wrapper_init; - -architecture STRUCTURE of data_1p5m_blk_mem_gen_prim_wrapper_init is - signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_10\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_11\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_12\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_13\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_14\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_8\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_9\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); - attribute box_type : string; - attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE"; -begin -\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1 - generic map( - DOA_REG => 1, - DOB_REG => 0, - INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_00 => X"0101000001010101000101000001010100010100010101000101000100010001", - INIT_01 => X"0000010001000000010100000100010100000100010101000100000100000101", - INIT_02 => X"0001000000010001010000010101000100010100000000010100000001010001", - INIT_03 => X"0100000101000100010000010000000101010000000001000000000101000001", - INIT_04 => X"0001010101010000000001000100010100000001010000010001000101010000", - INIT_05 => X"0101010100010000000101000101010101000100010000010001010000000101", - INIT_06 => X"0101010100010100010001010001010000000001000001010100000000010101", - INIT_07 => X"0000010100010000000101010001000000000100010000000100010001000001", - INIT_08 => X"0101000101010101010000000000000001000000010001000001000100000100", - INIT_09 => X"0000010000000101000100010001000000000101000001010001010100010001", - INIT_0A => X"0000000101000100000001000001000100000100000101010100010100000101", - INIT_0B => X"0100010001000000010101000101010001010000010101010101000001010100", - INIT_0C => X"0100010101010001000101010101000000010100010100000000000101010100", - INIT_0D => X"0001010001010000000000010000010100000000010100010001000001010101", - INIT_0E => X"0000010000010001000000000001000100000000010000000101000100000100", - INIT_0F => X"0000010101010100000000000000010101010001000001000100010101010101", - INIT_10 => X"0101000100010001010100010101000101010000010101010000000001000000", - INIT_11 => X"0101010100000000000001000000010000000100000001000001000001000001", - INIT_12 => X"0000000101010101000001000100010100010000010000010100010101000101", - INIT_13 => X"0100000000000000000100000100010000010000000101010101000101000100", - INIT_14 => X"0101010101010100010001000100010001010100000100000101010101010001", - INIT_15 => X"0100010000010101000000010001000001000100000001010001010000010000", - INIT_16 => X"0100000001000101000101010100000100000101000101000101010000010001", - INIT_17 => X"0100010001000100000101000000010000000000000000010000010001010000", - INIT_18 => X"0000010100000100000101010101000000000101010101010001010100010100", - INIT_19 => X"0100000100010001000100010000010000000100000000010001010001010100", - INIT_1A => X"0001010100010001000100000100000000010100010001010100010100010001", - INIT_1B => X"0100010000000101010000010101010100000000010001000000010000000001", - INIT_1C => X"0101000000010100000000010100010100000001000000000100000100010100", - INIT_1D => X"0101010101000101000100000100000000000001010001000101010100000001", - INIT_1E => X"0101010100010001010000010101000100000100000100000000000101000000", - INIT_1F => X"0101010000000100000001010001010001010001000001000001000001000101", - INIT_20 => X"0101000100010000010001000101010100010000010001010101000100010001", - INIT_21 => X"0001000001000100010000010101000001000100010101010100010100000101", - INIT_22 => X"0101000100010101010101010001000100000100000001000000010101000100", - INIT_23 => X"0000000000010101010100010001010100010101010001000001010100000000", - INIT_24 => X"0100000000010000000100000100000101000100000100010001010000000001", - INIT_25 => X"0001010100000001010000010000000001010000000100000100000101010100", - INIT_26 => X"0001010101010000010101000001000000010001010101000000010000010100", - INIT_27 => X"0001000000010100010101010001000100000000000000000001010000010101", - INIT_28 => X"0101010101010001010101010100000100000100000000000001000100000000", - INIT_29 => X"0100000100010101000001000101010001000001000000010001010001000100", - INIT_2A => X"0001000000010000010001000101000101000101010000000100000000000101", - INIT_2B => X"0100010101000000000101000101000001000101010101010100000001000101", - INIT_2C => X"0101010000000001000001000100010100000000000100010001000101010001", - INIT_2D => X"0001010000000101000100000101000000000001000100000100000000010001", - INIT_2E => X"0001010101010000010101010000010000000000010001000100000000000001", - INIT_2F => X"0000010101000100010000010000000000010101010100000001000001000000", - INIT_30 => X"0101000100000100010000000000000101010001000100000100000101000101", - INIT_31 => X"0000000000000001010001000100010001000000010101010001000100000001", - INIT_32 => X"0101000100010001010101010101000100000101010100000101000101000101", - INIT_33 => X"0000010101000101000101010001010001010101010000010101010001010101", - INIT_34 => X"0101000000010001010100010000010100000001000000000101000001010100", - INIT_35 => X"0001000001000100000101000001000101010001000100010101010100000000", - INIT_36 => X"0000010100010000010101010001010101000001010101000001000001000101", - INIT_37 => X"0001000101000101000000010101000101010100000100010101000000010001", - INIT_38 => X"0000000001010101000000000100000101000001010001000100010100010001", - INIT_39 => X"0000010101000001000000010000000100010001010100010001010101000101", - INIT_3A => X"0101010100000100000000000001000000010100010000010001000101010001", - INIT_3B => X"0001010100010101010100000001010101010101010000010001000100010001", - INIT_3C => X"0000000001010000000100000101000101000101010100000000010100010101", - INIT_3D => X"0001000101000000010000000100010100010101010001000000000000010001", - INIT_3E => X"0000000101000100000000010000010000010100010001000000010100000100", - INIT_3F => X"0100000000010001000100010100000101000000010100000101010100010000", - INIT_A => X"00000", - INIT_B => X"00000", - INIT_FILE => "NONE", - IS_CLKARDCLK_INVERTED => '0', - IS_CLKBWRCLK_INVERTED => '0', - IS_ENARDEN_INVERTED => '0', - IS_ENBWREN_INVERTED => '0', - IS_RSTRAMARSTRAM_INVERTED => '0', - IS_RSTRAMB_INVERTED => '0', - IS_RSTREGARSTREG_INVERTED => '0', - IS_RSTREGB_INVERTED => '0', - RAM_MODE => "TDP", - RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", - READ_WIDTH_A => 9, - READ_WIDTH_B => 9, - RSTREG_PRIORITY_A => "REGCE", - RSTREG_PRIORITY_B => "REGCE", - SIM_COLLISION_CHECK => "ALL", - SIM_DEVICE => "7SERIES", - SRVAL_A => X"00000", - SRVAL_B => X"00000", - WRITE_MODE_A => "WRITE_FIRST", - WRITE_MODE_B => "WRITE_FIRST", - WRITE_WIDTH_A => 9, - WRITE_WIDTH_B => 9 - ) - port map ( - ADDRARDADDR(13 downto 3) => addra(10 downto 0), - ADDRARDADDR(2 downto 0) => B"000", - ADDRBWRADDR(13 downto 0) => B"00000000000000", - CLKARDCLK => clka, - CLKBWRCLK => clka, - DIADI(15 downto 0) => B"0000000000000000", - DIBDI(15 downto 0) => B"0000000000000000", - DIPADIP(1 downto 0) => B"00", - DIPBDIP(1 downto 0) => B"00", - DOADO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 8), - DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_8\, - DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_9\, - DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_10\, - DOADO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_11\, - DOADO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_12\, - DOADO(2) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_13\, - DOADO(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_14\, - DOADO(0) => DOADO(0), - DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0), - DOPADOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1), - DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33\, - DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0), - ENARDEN => ena, - ENBWREN => '0', - REGCEAREGCE => ena, - REGCEB => '0', - RSTRAMARSTRAM => '0', - RSTRAMB => '0', - RSTREGARSTREG => '0', - RSTREGB => '0', - WEA(1 downto 0) => B"00", - WEBWE(3 downto 0) => B"0000" - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity data_1p5m_blk_mem_gen_prim_width is - port ( - DOADO : out STD_LOGIC_VECTOR ( 0 to 0 ); - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of data_1p5m_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; -end data_1p5m_blk_mem_gen_prim_width; - -architecture STRUCTURE of data_1p5m_blk_mem_gen_prim_width is -begin -\prim_init.ram\: entity work.data_1p5m_blk_mem_gen_prim_wrapper_init - port map ( - DOADO(0) => DOADO(0), - addra(10 downto 0) => addra(10 downto 0), - clka => clka, - ena => ena - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity data_1p5m_blk_mem_gen_generic_cstr is - port ( - douta : out STD_LOGIC_VECTOR ( 0 to 0 ); - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of data_1p5m_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; -end data_1p5m_blk_mem_gen_generic_cstr; - -architecture STRUCTURE of data_1p5m_blk_mem_gen_generic_cstr is - signal ram_douta : STD_LOGIC; -begin -\mux_a_wire.mux_reg.ce_pri.douta_i_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => clka, - CE => ena, - D => ram_douta, - Q => douta(0), - R => '0' - ); -\ramloop[0].ram.r\: entity work.data_1p5m_blk_mem_gen_prim_width - port map ( - DOADO(0) => ram_douta, - addra(10 downto 0) => addra(10 downto 0), - clka => clka, - ena => ena - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity data_1p5m_blk_mem_gen_top is - port ( - douta : out STD_LOGIC_VECTOR ( 0 to 0 ); - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of data_1p5m_blk_mem_gen_top : entity is "blk_mem_gen_top"; -end data_1p5m_blk_mem_gen_top; - -architecture STRUCTURE of data_1p5m_blk_mem_gen_top is -begin -\valid.cstr\: entity work.data_1p5m_blk_mem_gen_generic_cstr - port map ( - addra(10 downto 0) => addra(10 downto 0), - clka => clka, - douta(0) => douta(0), - ena => ena - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity data_1p5m_blk_mem_gen_v8_4_3_synth is - port ( - douta : out STD_LOGIC_VECTOR ( 0 to 0 ); - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of data_1p5m_blk_mem_gen_v8_4_3_synth : entity is "blk_mem_gen_v8_4_3_synth"; -end data_1p5m_blk_mem_gen_v8_4_3_synth; - -architecture STRUCTURE of data_1p5m_blk_mem_gen_v8_4_3_synth is -begin -\gnbram.gnativebmg.native_blk_mem_gen\: entity work.data_1p5m_blk_mem_gen_top - port map ( - addra(10 downto 0) => addra(10 downto 0), - clka => clka, - douta(0) => douta(0), - ena => ena - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity data_1p5m_blk_mem_gen_v8_4_3 is - port ( - clka : in STD_LOGIC; - rsta : in STD_LOGIC; - ena : in STD_LOGIC; - regcea : in STD_LOGIC; - wea : in STD_LOGIC_VECTOR ( 0 to 0 ); - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); - dina : in STD_LOGIC_VECTOR ( 0 to 0 ); - douta : out STD_LOGIC_VECTOR ( 0 to 0 ); - clkb : in STD_LOGIC; - rstb : in STD_LOGIC; - enb : in STD_LOGIC; - regceb : in STD_LOGIC; - web : in STD_LOGIC_VECTOR ( 0 to 0 ); - addrb : in STD_LOGIC_VECTOR ( 10 downto 0 ); - dinb : in STD_LOGIC_VECTOR ( 0 to 0 ); - doutb : out STD_LOGIC_VECTOR ( 0 to 0 ); - injectsbiterr : in STD_LOGIC; - injectdbiterr : in STD_LOGIC; - eccpipece : in STD_LOGIC; - sbiterr : out STD_LOGIC; - dbiterr : out STD_LOGIC; - rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 ); - sleep : in STD_LOGIC; - deepsleep : in STD_LOGIC; - shutdown : in STD_LOGIC; - rsta_busy : out STD_LOGIC; - rstb_busy : out STD_LOGIC; - s_aclk : in STD_LOGIC; - s_aresetn : in STD_LOGIC; - s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_awvalid : in STD_LOGIC; - s_axi_awready : out STD_LOGIC; - s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_wlast : in STD_LOGIC; - s_axi_wvalid : in STD_LOGIC; - s_axi_wready : out STD_LOGIC; - s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_bvalid : out STD_LOGIC; - s_axi_bready : in STD_LOGIC; - s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_arvalid : in STD_LOGIC; - s_axi_arready : out STD_LOGIC; - s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_rdata : out STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_rlast : out STD_LOGIC; - s_axi_rvalid : out STD_LOGIC; - s_axi_rready : in STD_LOGIC; - s_axi_injectsbiterr : in STD_LOGIC; - s_axi_injectdbiterr : in STD_LOGIC; - s_axi_sbiterr : out STD_LOGIC; - s_axi_dbiterr : out STD_LOGIC; - s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 ) - ); - attribute C_ADDRA_WIDTH : integer; - attribute C_ADDRA_WIDTH of data_1p5m_blk_mem_gen_v8_4_3 : entity is 11; - attribute C_ADDRB_WIDTH : integer; - attribute C_ADDRB_WIDTH of data_1p5m_blk_mem_gen_v8_4_3 : entity is 11; - attribute C_ALGORITHM : integer; - attribute C_ALGORITHM of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_AXI_ID_WIDTH : integer; - attribute C_AXI_ID_WIDTH of data_1p5m_blk_mem_gen_v8_4_3 : entity is 4; - attribute C_AXI_SLAVE_TYPE : integer; - attribute C_AXI_SLAVE_TYPE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_AXI_TYPE : integer; - attribute C_AXI_TYPE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_BYTE_SIZE : integer; - attribute C_BYTE_SIZE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 9; - attribute C_COMMON_CLK : integer; - attribute C_COMMON_CLK of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_COUNT_18K_BRAM : string; - attribute C_COUNT_18K_BRAM of data_1p5m_blk_mem_gen_v8_4_3 : entity is "1"; - attribute C_COUNT_36K_BRAM : string; - attribute C_COUNT_36K_BRAM of data_1p5m_blk_mem_gen_v8_4_3 : entity is "0"; - attribute C_CTRL_ECC_ALGO : string; - attribute C_CTRL_ECC_ALGO of data_1p5m_blk_mem_gen_v8_4_3 : entity is "NONE"; - attribute C_DEFAULT_DATA : string; - attribute C_DEFAULT_DATA of data_1p5m_blk_mem_gen_v8_4_3 : entity is "0"; - attribute C_DISABLE_WARN_BHV_COLL : integer; - attribute C_DISABLE_WARN_BHV_COLL of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_DISABLE_WARN_BHV_RANGE : integer; - attribute C_DISABLE_WARN_BHV_RANGE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_ELABORATION_DIR : string; - attribute C_ELABORATION_DIR of data_1p5m_blk_mem_gen_v8_4_3 : entity is "./"; - attribute C_ENABLE_32BIT_ADDRESS : integer; - attribute C_ENABLE_32BIT_ADDRESS of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_DEEPSLEEP_PIN : integer; - attribute C_EN_DEEPSLEEP_PIN of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_ECC_PIPE : integer; - attribute C_EN_ECC_PIPE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_RDADDRA_CHG : integer; - attribute C_EN_RDADDRA_CHG of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_RDADDRB_CHG : integer; - attribute C_EN_RDADDRB_CHG of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_SAFETY_CKT : integer; - attribute C_EN_SAFETY_CKT of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_SHUTDOWN_PIN : integer; - attribute C_EN_SHUTDOWN_PIN of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EN_SLEEP_PIN : integer; - attribute C_EN_SLEEP_PIN of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_EST_POWER_SUMMARY : string; - attribute C_EST_POWER_SUMMARY of data_1p5m_blk_mem_gen_v8_4_3 : entity is "Estimated Power for IP : 0.990811 mW"; - attribute C_FAMILY : string; - attribute C_FAMILY of data_1p5m_blk_mem_gen_v8_4_3 : entity is "kintex7"; - attribute C_HAS_AXI_ID : integer; - attribute C_HAS_AXI_ID of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_ENA : integer; - attribute C_HAS_ENA of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_HAS_ENB : integer; - attribute C_HAS_ENB of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_INJECTERR : integer; - attribute C_HAS_INJECTERR of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_MEM_OUTPUT_REGS_A : integer; - attribute C_HAS_MEM_OUTPUT_REGS_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_HAS_MEM_OUTPUT_REGS_B : integer; - attribute C_HAS_MEM_OUTPUT_REGS_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_MUX_OUTPUT_REGS_A : integer; - attribute C_HAS_MUX_OUTPUT_REGS_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_HAS_MUX_OUTPUT_REGS_B : integer; - attribute C_HAS_MUX_OUTPUT_REGS_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_REGCEA : integer; - attribute C_HAS_REGCEA of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_REGCEB : integer; - attribute C_HAS_REGCEB of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_RSTA : integer; - attribute C_HAS_RSTA of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_RSTB : integer; - attribute C_HAS_RSTB of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; - attribute C_HAS_SOFTECC_INPUT_REGS_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; - attribute C_HAS_SOFTECC_OUTPUT_REGS_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_INITA_VAL : string; - attribute C_INITA_VAL of data_1p5m_blk_mem_gen_v8_4_3 : entity is "0"; - attribute C_INITB_VAL : string; - attribute C_INITB_VAL of data_1p5m_blk_mem_gen_v8_4_3 : entity is "0"; - attribute C_INIT_FILE : string; - attribute C_INIT_FILE of data_1p5m_blk_mem_gen_v8_4_3 : entity is "data_1p5m.mem"; - attribute C_INIT_FILE_NAME : string; - attribute C_INIT_FILE_NAME of data_1p5m_blk_mem_gen_v8_4_3 : entity is "data_1p5m.mif"; - attribute C_INTERFACE_TYPE : integer; - attribute C_INTERFACE_TYPE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_LOAD_INIT_FILE : integer; - attribute C_LOAD_INIT_FILE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_MEM_TYPE : integer; - attribute C_MEM_TYPE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 3; - attribute C_MUX_PIPELINE_STAGES : integer; - attribute C_MUX_PIPELINE_STAGES of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_PRIM_TYPE : integer; - attribute C_PRIM_TYPE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_READ_DEPTH_A : integer; - attribute C_READ_DEPTH_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 2048; - attribute C_READ_DEPTH_B : integer; - attribute C_READ_DEPTH_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 2048; - attribute C_READ_LATENCY_A : integer; - attribute C_READ_LATENCY_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_READ_LATENCY_B : integer; - attribute C_READ_LATENCY_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_READ_WIDTH_A : integer; - attribute C_READ_WIDTH_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_READ_WIDTH_B : integer; - attribute C_READ_WIDTH_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_RSTRAM_A : integer; - attribute C_RSTRAM_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_RSTRAM_B : integer; - attribute C_RSTRAM_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_RST_PRIORITY_A : string; - attribute C_RST_PRIORITY_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is "CE"; - attribute C_RST_PRIORITY_B : string; - attribute C_RST_PRIORITY_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is "CE"; - attribute C_SIM_COLLISION_CHECK : string; - attribute C_SIM_COLLISION_CHECK of data_1p5m_blk_mem_gen_v8_4_3 : entity is "ALL"; - attribute C_USE_BRAM_BLOCK : integer; - attribute C_USE_BRAM_BLOCK of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_BYTE_WEA : integer; - attribute C_USE_BYTE_WEA of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_BYTE_WEB : integer; - attribute C_USE_BYTE_WEB of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_DEFAULT_DATA : integer; - attribute C_USE_DEFAULT_DATA of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_ECC : integer; - attribute C_USE_ECC of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_SOFTECC : integer; - attribute C_USE_SOFTECC of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_USE_URAM : integer; - attribute C_USE_URAM of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0; - attribute C_WEA_WIDTH : integer; - attribute C_WEA_WIDTH of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_WEB_WIDTH : integer; - attribute C_WEB_WIDTH of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_WRITE_DEPTH_A : integer; - attribute C_WRITE_DEPTH_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 2048; - attribute C_WRITE_DEPTH_B : integer; - attribute C_WRITE_DEPTH_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 2048; - attribute C_WRITE_MODE_A : string; - attribute C_WRITE_MODE_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is "WRITE_FIRST"; - attribute C_WRITE_MODE_B : string; - attribute C_WRITE_MODE_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is "WRITE_FIRST"; - attribute C_WRITE_WIDTH_A : integer; - attribute C_WRITE_WIDTH_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_WRITE_WIDTH_B : integer; - attribute C_WRITE_WIDTH_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of data_1p5m_blk_mem_gen_v8_4_3 : entity is "kintex7"; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of data_1p5m_blk_mem_gen_v8_4_3 : entity is "blk_mem_gen_v8_4_3"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of data_1p5m_blk_mem_gen_v8_4_3 : entity is "yes"; -end data_1p5m_blk_mem_gen_v8_4_3; - -architecture STRUCTURE of data_1p5m_blk_mem_gen_v8_4_3 is - signal \\ : STD_LOGIC; -begin - dbiterr <= \\; - doutb(0) <= \\; - rdaddrecc(10) <= \\; - rdaddrecc(9) <= \\; - rdaddrecc(8) <= \\; - rdaddrecc(7) <= \\; - rdaddrecc(6) <= \\; - rdaddrecc(5) <= \\; - rdaddrecc(4) <= \\; - rdaddrecc(3) <= \\; - rdaddrecc(2) <= \\; - rdaddrecc(1) <= \\; - rdaddrecc(0) <= \\; - rsta_busy <= \\; - rstb_busy <= \\; - s_axi_arready <= \\; - s_axi_awready <= \\; - s_axi_bid(3) <= \\; - s_axi_bid(2) <= \\; - s_axi_bid(1) <= \\; - s_axi_bid(0) <= \\; - s_axi_bresp(1) <= \\; - s_axi_bresp(0) <= \\; - s_axi_bvalid <= \\; - s_axi_dbiterr <= \\; - s_axi_rdaddrecc(10) <= \\; - s_axi_rdaddrecc(9) <= \\; - s_axi_rdaddrecc(8) <= \\; - s_axi_rdaddrecc(7) <= \\; - s_axi_rdaddrecc(6) <= \\; - s_axi_rdaddrecc(5) <= \\; - s_axi_rdaddrecc(4) <= \\; - s_axi_rdaddrecc(3) <= \\; - s_axi_rdaddrecc(2) <= \\; - s_axi_rdaddrecc(1) <= \\; - s_axi_rdaddrecc(0) <= \\; - s_axi_rdata(0) <= \\; - s_axi_rid(3) <= \\; - s_axi_rid(2) <= \\; - s_axi_rid(1) <= \\; - s_axi_rid(0) <= \\; - s_axi_rlast <= \\; - s_axi_rresp(1) <= \\; - s_axi_rresp(0) <= \\; - s_axi_rvalid <= \\; - s_axi_sbiterr <= \\; - s_axi_wready <= \\; - sbiterr <= \\; -GND: unisim.vcomponents.GND - port map ( - G => \\ - ); -inst_blk_mem_gen: entity work.data_1p5m_blk_mem_gen_v8_4_3_synth - port map ( - addra(10 downto 0) => addra(10 downto 0), - clka => clka, - douta(0) => douta(0), - ena => ena - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity data_1p5m is - port ( - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); - douta : out STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of data_1p5m : entity is true; - attribute CHECK_LICENSE_TYPE : string; - attribute CHECK_LICENSE_TYPE of data_1p5m : entity is "data_1p5m,blk_mem_gen_v8_4_3,{}"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of data_1p5m : entity is "yes"; - attribute x_core_info : string; - attribute x_core_info of data_1p5m : entity is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; -end data_1p5m; - -architecture STRUCTURE of data_1p5m is - signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; - signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; - signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); - signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); - signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - attribute C_ADDRA_WIDTH : integer; - attribute C_ADDRA_WIDTH of U0 : label is 11; - attribute C_ADDRB_WIDTH : integer; - attribute C_ADDRB_WIDTH of U0 : label is 11; - attribute C_ALGORITHM : integer; - attribute C_ALGORITHM of U0 : label is 1; - attribute C_AXI_ID_WIDTH : integer; - attribute C_AXI_ID_WIDTH of U0 : label is 4; - attribute C_AXI_SLAVE_TYPE : integer; - attribute C_AXI_SLAVE_TYPE of U0 : label is 0; - attribute C_AXI_TYPE : integer; - attribute C_AXI_TYPE of U0 : label is 1; - attribute C_BYTE_SIZE : integer; - attribute C_BYTE_SIZE of U0 : label is 9; - attribute C_COMMON_CLK : integer; - attribute C_COMMON_CLK of U0 : label is 0; - attribute C_COUNT_18K_BRAM : string; - attribute C_COUNT_18K_BRAM of U0 : label is "1"; - attribute C_COUNT_36K_BRAM : string; - attribute C_COUNT_36K_BRAM of U0 : label is "0"; - attribute C_CTRL_ECC_ALGO : string; - attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; - attribute C_DEFAULT_DATA : string; - attribute C_DEFAULT_DATA of U0 : label is "0"; - attribute C_DISABLE_WARN_BHV_COLL : integer; - attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; - attribute C_DISABLE_WARN_BHV_RANGE : integer; - attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; - attribute C_ELABORATION_DIR : string; - attribute C_ELABORATION_DIR of U0 : label is "./"; - attribute C_ENABLE_32BIT_ADDRESS : integer; - attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; - attribute C_EN_DEEPSLEEP_PIN : integer; - attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; - attribute C_EN_ECC_PIPE : integer; - attribute C_EN_ECC_PIPE of U0 : label is 0; - attribute C_EN_RDADDRA_CHG : integer; - attribute C_EN_RDADDRA_CHG of U0 : label is 0; - attribute C_EN_RDADDRB_CHG : integer; - attribute C_EN_RDADDRB_CHG of U0 : label is 0; - attribute C_EN_SAFETY_CKT : integer; - attribute C_EN_SAFETY_CKT of U0 : label is 0; - attribute C_EN_SHUTDOWN_PIN : integer; - attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; - attribute C_EN_SLEEP_PIN : integer; - attribute C_EN_SLEEP_PIN of U0 : label is 0; - attribute C_EST_POWER_SUMMARY : string; - attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 0.990811 mW"; - attribute C_FAMILY : string; - attribute C_FAMILY of U0 : label is "kintex7"; - attribute C_HAS_AXI_ID : integer; - attribute C_HAS_AXI_ID of U0 : label is 0; - attribute C_HAS_ENA : integer; - attribute C_HAS_ENA of U0 : label is 1; - attribute C_HAS_ENB : integer; - attribute C_HAS_ENB of U0 : label is 0; - attribute C_HAS_INJECTERR : integer; - attribute C_HAS_INJECTERR of U0 : label is 0; - attribute C_HAS_MEM_OUTPUT_REGS_A : integer; - attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1; - attribute C_HAS_MEM_OUTPUT_REGS_B : integer; - attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; - attribute C_HAS_MUX_OUTPUT_REGS_A : integer; - attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 1; - attribute C_HAS_MUX_OUTPUT_REGS_B : integer; - attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; - attribute C_HAS_REGCEA : integer; - attribute C_HAS_REGCEA of U0 : label is 0; - attribute C_HAS_REGCEB : integer; - attribute C_HAS_REGCEB of U0 : label is 0; - attribute C_HAS_RSTA : integer; - attribute C_HAS_RSTA of U0 : label is 0; - attribute C_HAS_RSTB : integer; - attribute C_HAS_RSTB of U0 : label is 0; - attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; - attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; - attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; - attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; - attribute C_INITA_VAL : string; - attribute C_INITA_VAL of U0 : label is "0"; - attribute C_INITB_VAL : string; - attribute C_INITB_VAL of U0 : label is "0"; - attribute C_INIT_FILE : string; - attribute C_INIT_FILE of U0 : label is "data_1p5m.mem"; - attribute C_INIT_FILE_NAME : string; - attribute C_INIT_FILE_NAME of U0 : label is "data_1p5m.mif"; - attribute C_INTERFACE_TYPE : integer; - attribute C_INTERFACE_TYPE of U0 : label is 0; - attribute C_LOAD_INIT_FILE : integer; - attribute C_LOAD_INIT_FILE of U0 : label is 1; - attribute C_MEM_TYPE : integer; - attribute C_MEM_TYPE of U0 : label is 3; - attribute C_MUX_PIPELINE_STAGES : integer; - attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; - attribute C_PRIM_TYPE : integer; - attribute C_PRIM_TYPE of U0 : label is 1; - attribute C_READ_DEPTH_A : integer; - attribute C_READ_DEPTH_A of U0 : label is 2048; - attribute C_READ_DEPTH_B : integer; - attribute C_READ_DEPTH_B of U0 : label is 2048; - attribute C_READ_LATENCY_A : integer; - attribute C_READ_LATENCY_A of U0 : label is 1; - attribute C_READ_LATENCY_B : integer; - attribute C_READ_LATENCY_B of U0 : label is 1; - attribute C_READ_WIDTH_A : integer; - attribute C_READ_WIDTH_A of U0 : label is 1; - attribute C_READ_WIDTH_B : integer; - attribute C_READ_WIDTH_B of U0 : label is 1; - attribute C_RSTRAM_A : integer; - attribute C_RSTRAM_A of U0 : label is 0; - attribute C_RSTRAM_B : integer; - attribute C_RSTRAM_B of U0 : label is 0; - attribute C_RST_PRIORITY_A : string; - attribute C_RST_PRIORITY_A of U0 : label is "CE"; - attribute C_RST_PRIORITY_B : string; - attribute C_RST_PRIORITY_B of U0 : label is "CE"; - attribute C_SIM_COLLISION_CHECK : string; - attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; - attribute C_USE_BRAM_BLOCK : integer; - attribute C_USE_BRAM_BLOCK of U0 : label is 0; - attribute C_USE_BYTE_WEA : integer; - attribute C_USE_BYTE_WEA of U0 : label is 0; - attribute C_USE_BYTE_WEB : integer; - attribute C_USE_BYTE_WEB of U0 : label is 0; - attribute C_USE_DEFAULT_DATA : integer; - attribute C_USE_DEFAULT_DATA of U0 : label is 0; - attribute C_USE_ECC : integer; - attribute C_USE_ECC of U0 : label is 0; - attribute C_USE_SOFTECC : integer; - attribute C_USE_SOFTECC of U0 : label is 0; - attribute C_USE_URAM : integer; - attribute C_USE_URAM of U0 : label is 0; - attribute C_WEA_WIDTH : integer; - attribute C_WEA_WIDTH of U0 : label is 1; - attribute C_WEB_WIDTH : integer; - attribute C_WEB_WIDTH of U0 : label is 1; - attribute C_WRITE_DEPTH_A : integer; - attribute C_WRITE_DEPTH_A of U0 : label is 2048; - attribute C_WRITE_DEPTH_B : integer; - attribute C_WRITE_DEPTH_B of U0 : label is 2048; - attribute C_WRITE_MODE_A : string; - attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST"; - attribute C_WRITE_MODE_B : string; - attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; - attribute C_WRITE_WIDTH_A : integer; - attribute C_WRITE_WIDTH_A of U0 : label is 1; - attribute C_WRITE_WIDTH_B : integer; - attribute C_WRITE_WIDTH_B of U0 : label is 1; - attribute C_XDEVICEFAMILY : string; - attribute C_XDEVICEFAMILY of U0 : label is "kintex7"; - attribute downgradeipidentifiedwarnings of U0 : label is "yes"; - attribute x_interface_info : string; - attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; - attribute x_interface_parameter : string; - attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1"; - attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN"; - attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; - attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; -begin -U0: entity work.data_1p5m_blk_mem_gen_v8_4_3 - port map ( - addra(10 downto 0) => addra(10 downto 0), - addrb(10 downto 0) => B"00000000000", - clka => clka, - clkb => '0', - dbiterr => NLW_U0_dbiterr_UNCONNECTED, - deepsleep => '0', - dina(0) => '0', - dinb(0) => '0', - douta(0) => douta(0), - doutb(0) => NLW_U0_doutb_UNCONNECTED(0), - eccpipece => '0', - ena => ena, - enb => '0', - injectdbiterr => '0', - injectsbiterr => '0', - rdaddrecc(10 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(10 downto 0), - regcea => '0', - regceb => '0', - rsta => '0', - rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, - rstb => '0', - rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, - s_aclk => '0', - s_aresetn => '0', - s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", - s_axi_arburst(1 downto 0) => B"00", - s_axi_arid(3 downto 0) => B"0000", - s_axi_arlen(7 downto 0) => B"00000000", - s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, - s_axi_arsize(2 downto 0) => B"000", - s_axi_arvalid => '0', - s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", - s_axi_awburst(1 downto 0) => B"00", - s_axi_awid(3 downto 0) => B"0000", - s_axi_awlen(7 downto 0) => B"00000000", - s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, - s_axi_awsize(2 downto 0) => B"000", - s_axi_awvalid => '0', - s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), - s_axi_bready => '0', - s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), - s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, - s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, - s_axi_injectdbiterr => '0', - s_axi_injectsbiterr => '0', - s_axi_rdaddrecc(10 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(10 downto 0), - s_axi_rdata(0) => NLW_U0_s_axi_rdata_UNCONNECTED(0), - s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), - s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, - s_axi_rready => '0', - s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), - s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, - s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, - s_axi_wdata(0) => '0', - s_axi_wlast => '0', - s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, - s_axi_wstrb(0) => '0', - s_axi_wvalid => '0', - sbiterr => NLW_U0_sbiterr_UNCONNECTED, - shutdown => '0', - sleep => '0', - wea(0) => '0', - web(0) => '0' - ); -end STRUCTURE; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_stub.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_stub.v deleted file mode 100644 index 7ece828a..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_stub.v +++ /dev/null @@ -1,23 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:34:17 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_stub.v -// Design : data_1p5m -// Purpose : Stub declaration of top-level module interface -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) -module data_1p5m(clka, ena, addra, douta) -/* synthesis syn_black_box black_box_pad_pin="clka,ena,addra[10:0],douta[0:0]" */; - input clka; - input ena; - input [10:0]addra; - output [0:0]douta; -endmodule diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_stub.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_stub.vhdl deleted file mode 100644 index 434c04bd..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_stub.vhdl +++ /dev/null @@ -1,33 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:34:17 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_stub.vhdl --- Design : data_1p5m --- Purpose : Stub declaration of top-level module interface --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity data_1p5m is - Port ( - clka : in STD_LOGIC; - ena : in STD_LOGIC; - addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); - douta : out STD_LOGIC_VECTOR ( 0 to 0 ) - ); - -end data_1p5m; - -architecture stub of data_1p5m is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clka,ena,addra[10:0],douta[0:0]"; -attribute x_core_info : string; -attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; -begin -end; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_utilization_synth.pb b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_utilization_synth.pb deleted file mode 100644 index c7e83a09..00000000 Binary files a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_utilization_synth.pb and /dev/null differ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_utilization_synth.rpt b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_utilization_synth.rpt deleted file mode 100644 index f739a7e3..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_utilization_synth.rpt +++ /dev/null @@ -1,175 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -| Date : Sat Mar 18 23:34:17 2023 -| Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -| Command : report_utilization -file data_1p5m_utilization_synth.rpt -pb data_1p5m_utilization_synth.pb -| Design : data_1p5m -| Device : 7k410tffg900-2 -| Design State : Synthesized -------------------------------------------------------------------------------------------------------------- - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 0 | 0 | 254200 | 0.00 | -| LUT as Logic | 0 | 0 | 254200 | 0.00 | -| LUT as Memory | 0 | 0 | 90600 | 0.00 | -| Slice Registers | 1 | 0 | 508400 | <0.01 | -| Register as Flip Flop | 1 | 0 | 508400 | <0.01 | -| Register as Latch | 0 | 0 | 508400 | 0.00 | -| F7 Muxes | 0 | 0 | 127100 | 0.00 | -| F8 Muxes | 0 | 0 | 63550 | 0.00 | -+-------------------------+------+-------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 1 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Memory ---------- - -+-------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------+------+-------+-----------+-------+ -| Block RAM Tile | 0.5 | 0 | 795 | 0.06 | -| RAMB36/FIFO* | 0 | 0 | 795 | 0.00 | -| RAMB18 | 1 | 0 | 1590 | 0.06 | -| RAMB18E1 only | 1 | | | | -+-------------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -3. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 1540 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -4. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 0 | 0 | 500 | 0.00 | -| Bonded IPADs | 0 | 0 | 50 | 0.00 | -| Bonded OPADs | 0 | 0 | 32 | 0.00 | -| PHY_CONTROL | 0 | 0 | 10 | 0.00 | -| PHASER_REF | 0 | 0 | 10 | 0.00 | -| OUT_FIFO | 0 | 0 | 40 | 0.00 | -| IN_FIFO | 0 | 0 | 40 | 0.00 | -| IDELAYCTRL | 0 | 0 | 10 | 0.00 | -| IBUFDS | 0 | 0 | 480 | 0.00 | -| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | -| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 | -| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | -| ILOGIC | 0 | 0 | 500 | 0.00 | -| OLOGIC | 0 | 0 | 500 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -5. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 0 | 0 | 32 | 0.00 | -| BUFIO | 0 | 0 | 40 | 0.00 | -| MMCME2_ADV | 0 | 0 | 10 | 0.00 | -| PLLE2_ADV | 0 | 0 | 10 | 0.00 | -| BUFMRCE | 0 | 0 | 20 | 0.00 | -| BUFHCE | 0 | 0 | 168 | 0.00 | -| BUFR | 0 | 0 | 40 | 0.00 | -+------------+------+-------+-----------+-------+ - - -6. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -7. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| RAMB18E1 | 1 | Block Memory | -| FDRE | 1 | Flop & Latch | -+----------+------+---------------------+ - - -8. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -9. Instantiated Netlists ------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/dont_touch.xdc b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/dont_touch.xdc deleted file mode 100644 index 0dbfc3f4..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/dont_touch.xdc +++ /dev/null @@ -1,16 +0,0 @@ -# This file is automatically generated. -# It contains project source information necessary for synthesis and implementation. - -# IP: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/data_1p5m/data_1p5m.xci -# IP: The module: 'data_1p5m' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/data_1p5m/data_1p5m_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'data_1p5m'. Do not add the DONT_TOUCH constraint. -set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet - -# IP: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/data_1p5m/data_1p5m.xci -# IP: The module: 'data_1p5m' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/transmitter/data_1p5m/data_1p5m_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'data_1p5m'. Do not add the DONT_TOUCH constraint. -#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/gen_run.xml deleted file mode 100644 index f43dfc70..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/gen_run.xml +++ /dev/null @@ -1,59 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/htr.txt b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/htr.txt deleted file mode 100644 index c426ed7d..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log data_1p5m.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source data_1p5m.tcl diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/project.wdf b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/project.wdf deleted file mode 100644 index 9507bcd5..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/project.wdf +++ /dev/null @@ -1,59 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:38:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3238:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3661346264366134396337643466636438383330333461376438356536303661:506172656e742050412070726f6a656374204944:00 -eof:3863841633 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/rundef.js b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/rundef.js deleted file mode 100644 index ac55b300..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/rundef.js +++ /dev/null @@ -1,36 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log data_1p5m.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source data_1p5m.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/runme.bat b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/runme.bat deleted file mode 100644 index 1760626b..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/runme.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/runme.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/runme.sh deleted file mode 100644 index 731744ec..00000000 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/runme.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin -else - PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log data_1p5m.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source data_1p5m.tcl diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/vivado.pb b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/vivado.pb deleted file mode 100644 index 39754597..00000000 Binary files a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/vivado.pb and /dev/null differ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_AntCtrl_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_AntCtrl_synth_1/gen_run.xml index a99e1f76..151b6491 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_AntCtrl_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_AntCtrl_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_rfcontrl_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_rfcontrl_synth_1/gen_run.xml index bf5a5aa2..77a26f3d 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_rfcontrl_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_rfcontrl_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_rx_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_rx_synth_1/gen_run.xml index 327c52d1..e9613bc7 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_rx_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_rx_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_tx_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_tx_synth_1/gen_run.xml index ab0940b0..fe3e7f99 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_tx_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_tx_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.begin.rst b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.begin.rst index ae50c0ea..ccc3efd7 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.begin.rst +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml index 5cc301ee..58579f7e 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml @@ -1,11 +1,14 @@ - + + + + @@ -53,7 +56,9 @@ - + + Vivado Synthesis Defaults + diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/project.wdf b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/project.wdf index 9507bcd5..69f40645 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/project.wdf +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/project.wdf @@ -1,13 +1,13 @@ version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:38:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:36:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3239:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3239:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3330:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3330:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 @@ -30,7 +30,9 @@ version:1 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f416e744374726c:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f63616c:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f7266636f6e74726c:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f7278:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f72785f707265:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f7478:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f74785f7278:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c72616d5f686f705f64617461:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c636f726469635f76365f305f31355c726f746174655f313662:636f72655f636f6e7461696e6572:74727565:00:00 @@ -48,12 +50,12 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3238:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3638:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3638:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3638:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3638:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3638:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3638:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3638:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3661346264366134396337643466636438383330333461376438356536303661:506172656e742050412070726f6a656374204944:00 -eof:3863841633 +eof:899866123 diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.sh b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.sh index 73fbfa82..46f2137d 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.sh +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1' +HD_PWD='D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp index 14694b31..016c5cb5 100644 Binary files a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp and b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp differ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.tcl b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.tcl index 204d0c3c..f556ca5a 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.tcl +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.tcl @@ -17,7 +17,6 @@ proc create_report { reportName command } { send_msg_id runtcl-5 warning "$msg" } } -set_param general.maxThreads 20 set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64 set_param project.vivado.isBlockSynthRun true set_msg_config -msgmgr_mode ooc_run @@ -27,16 +26,16 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] -set_property parent.project_path D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property webtalk.parent_dir D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr [current_project] set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language Verilog [current_project] -set_property ip_output_repo d:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_output_repo d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet D:/vivado-git/projects/datalink_814/dl814_cmos/ip/vio_manual_ctrl/vio_manual_ctrl.xci -set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_cmos/ip/vio_manual_ctrl/vio_manual_ctrl.xdc] -set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_cmos/ip/vio_manual_ctrl/vio_manual_ctrl_ooc.xdc] +read_ip -quiet D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_manual_ctrl/vio_manual_ctrl.xci +set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_manual_ctrl/vio_manual_ctrl.xdc] +set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_manual_ctrl/vio_manual_ctrl_ooc.xdc] # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -48,7 +47,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1 -new_name vio_manual_ctrl -ip [get_ips vio_manual_ctrl]] +set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1 -new_name vio_manual_ctrl -ip [get_ips vio_manual_ctrl]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -89,25 +88,25 @@ write_checkpoint -force -noxdef vio_manual_ctrl.dcp create_report "vio_manual_ctrl_synth_1_synth_report_utilization_0" "report_utilization -file vio_manual_ctrl_utilization_synth.rpt -pb vio_manual_ctrl_utilization_synth.pb" if { [catch { - write_verilog -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v + write_verilog -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl + write_vhdl -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v + write_verilog -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl + write_vhdl -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -118,37 +117,37 @@ if { [catch { }; # end if cached_ip -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/vio_manual_ctrl/vio_manual_ctrl.xci] +add_files D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_manual_ctrl/vio_manual_ctrl.xci] -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/vio_manual_ctrl/vio_manual_ctrl.xci] +add_files D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_manual_ctrl/vio_manual_ctrl.xci] -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/vio_manual_ctrl/vio_manual_ctrl.xci] +add_files D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_manual_ctrl/vio_manual_ctrl.xci] -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/vio_manual_ctrl/vio_manual_ctrl.xci] +add_files D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_manual_ctrl/vio_manual_ctrl.xci] -add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/vio_manual_ctrl/vio_manual_ctrl.xci] +add_files D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_manual_ctrl/vio_manual_ctrl.xci] -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/vio_manual_ctrl]} { +if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl]} { catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/vio_manual_ctrl + file copy -force D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl } } -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/vio_manual_ctrl]} { +if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl]} { catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/vio_manual_ctrl + file copy -force D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl } } -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/vio_manual_ctrl]} { +if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl]} { catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/vio_manual_ctrl + file copy -force D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl } } -if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/vio_manual_ctrl]} { +if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl]} { catch { - file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/vio_manual_ctrl + file copy -force D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl } } file delete __synthesis_is_running__ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds index 23369d4d..c0074a3e 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds @@ -2,12 +2,12 @@ # Vivado v2019.1.3 (64-bit) # SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Sat Mar 18 23:33:50 2023 -# Process ID: 33312 -# Current directory: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1 +# Start of session at: Tue Mar 21 22:54:17 2023 +# Process ID: 31280 +# Current directory: D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1 # Command line: vivado.exe -log vio_manual_ctrl.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_manual_ctrl.tcl -# Log file: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds -# Journal file: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1\vivado.jou +# Log file: D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds +# Journal file: D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1\vivado.jou #----------------------------------------------------------- Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl' source vio_manual_ctrl.tcl -notrace @@ -17,13 +17,13 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Device 21-403] Loading part xc7k410tffg900-2 INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 33576 +INFO: Helper process launched with PID 11916 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 889.008 ; gain = 178.320 +Starting RTL Elaboration : Time (s): cpu = 00:00:00 ; elapsed = 00:00:04 . Memory (MB): peak = 889.141 ; gain = 176.203 --------------------------------------------------------------------------------- -INFO: [Synth 8-6157] synthesizing module 'vio_manual_ctrl' [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/vio_manual_ctrl/synth/vio_manual_ctrl.v:59] -WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_manual_ctrl does not have driver. [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/vio_manual_ctrl/synth/vio_manual_ctrl.v:79] -INFO: [Synth 8-6155] done synthesizing module 'vio_manual_ctrl' (7#1) [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/vio_manual_ctrl/synth/vio_manual_ctrl.v:59] +INFO: [Synth 8-6157] synthesizing module 'vio_manual_ctrl' [d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_manual_ctrl/synth/vio_manual_ctrl.v:59] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_manual_ctrl does not have driver. [d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_manual_ctrl/synth/vio_manual_ctrl.v:79] +INFO: [Synth 8-6155] done synthesizing module 'vio_manual_ctrl' (7#1) [d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_manual_ctrl/synth/vio_manual_ctrl.v:59] WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Read WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[15] @@ -90,6 +90,7 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bu WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[5] WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[4] WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[3] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[2] WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in0[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in1[0] @@ -123,10 +124,9 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in28[0 WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in29[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in30[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in31[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in32[0] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 961.367 ; gain = 250.680 +Finished RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 961.434 ; gain = 248.496 --------------------------------------------------------------------------------- Report Check Netlist: @@ -139,44 +139,44 @@ Report Check Netlist: Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 961.367 ; gain = 250.680 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 961.434 ; gain = 248.496 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 961.367 ; gain = 250.680 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 961.434 ; gain = 248.496 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine -Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/vio_manual_ctrl/vio_manual_ctrl_ooc.xdc] -Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/vio_manual_ctrl/vio_manual_ctrl_ooc.xdc] -Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/vio_manual_ctrl/vio_manual_ctrl.xdc] -Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/vio_manual_ctrl/vio_manual_ctrl.xdc] +Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_manual_ctrl/vio_manual_ctrl_ooc.xdc] +Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_manual_ctrl/vio_manual_ctrl_ooc.xdc] +Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_manual_ctrl/vio_manual_ctrl.xdc] +Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_manual_ctrl/vio_manual_ctrl.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1080.723 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1079.141 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1093.344 ; gain = 12.621 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1090.871 ; gain = 11.730 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1093.344 ; gain = 382.656 +Finished Constraint Validation : Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 1090.871 ; gain = 377.934 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k410tffg900-2 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1093.344 ; gain = 382.656 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 1090.871 ; gain = 377.934 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1093.344 ; gain = 382.656 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 1090.871 ; gain = 377.934 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1093.344 ; gain = 382.656 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 1090.871 ; gain = 377.934 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -198,8 +198,8 @@ Detailed RTL Component Info : 7 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 1 - 3 Bit Registers := 4 - 2 Bit Registers := 3 + 3 Bit Registers := 3 + 2 Bit Registers := 4 1 Bit Registers := 18 +---Muxes : 2 Input 16 Bit Muxes := 3 @@ -216,7 +216,7 @@ Module vio_v3_0_20_probe_out_one Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 - 3 Bit Registers := 1 + 2 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module vio_v3_0_20_probe_out_one__parameterized0 @@ -310,6 +310,7 @@ Warning: Parallel synthesis criteria is not met INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' @@ -368,7 +369,7 @@ INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] ) --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1093.344 ; gain = 382.656 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:02 ; elapsed = 00:00:10 . Memory (MB): peak = 1090.871 ; gain = 377.934 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -380,13 +381,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1093.344 ; gain = 382.656 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:03 ; elapsed = 00:00:14 . Memory (MB): peak = 1090.871 ; gain = 377.934 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1093.344 ; gain = 382.656 +Finished Timing Optimization : Time (s): cpu = 00:00:03 ; elapsed = 00:00:14 . Memory (MB): peak = 1090.871 ; gain = 377.934 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -398,7 +399,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1093.344 ; gain = 382.656 +Finished Technology Mapping : Time (s): cpu = 00:00:03 ; elapsed = 00:00:15 . Memory (MB): peak = 1090.871 ; gain = 377.934 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -459,7 +460,7 @@ WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1093.344 ; gain = 382.656 +Finished IO Insertion : Time (s): cpu = 00:00:04 ; elapsed = 00:00:16 . Memory (MB): peak = 1090.871 ; gain = 377.934 --------------------------------------------------------------------------------- Report Check Netlist: @@ -472,7 +473,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1093.344 ; gain = 382.656 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:04 ; elapsed = 00:00:16 . Memory (MB): peak = 1090.871 ; gain = 377.934 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -484,25 +485,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1093.344 ; gain = 382.656 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:04 ; elapsed = 00:00:16 . Memory (MB): peak = 1090.871 ; gain = 377.934 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1093.344 ; gain = 382.656 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:04 ; elapsed = 00:00:16 . Memory (MB): peak = 1090.871 ; gain = 377.934 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1093.344 ; gain = 382.656 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:16 . Memory (MB): peak = 1090.871 ; gain = 377.934 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1093.344 ; gain = 382.656 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:04 ; elapsed = 00:00:16 . Memory (MB): peak = 1090.871 ; gain = 377.934 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -519,24 +520,24 @@ Report Cell Usage: | |Cell |Count | +------+-----+------+ |1 |LUT2 | 7| -|2 |LUT3 | 59| +|2 |LUT3 | 58| |3 |LUT4 | 10| -|4 |LUT5 | 25| -|5 |LUT6 | 82| -|6 |FDRE | 352| -|7 |FDSE | 4| +|4 |LUT5 | 26| +|5 |LUT6 | 81| +|6 |FDRE | 348| +|7 |FDSE | 6| +------+-----+------+ Report Instance Areas: +------+---------------------------------------+------------------------------------------+------+ | |Instance |Module |Cells | +------+---------------------------------------+------------------------------------------+------+ -|1 |top | | 539| -|2 | inst |vio_v3_0_20_vio | 539| +|1 |top | | 536| +|2 | inst |vio_v3_0_20_vio | 536| |3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| |4 | DECODER_INST |vio_v3_0_20_decoder | 82| -|5 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 183| -|6 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 9| +|5 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 180| +|6 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 6| |7 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 3| |8 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 104| |9 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2 | 6| @@ -544,34 +545,32 @@ Report Instance Areas: |11 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 10| +------+---------------------------------------+------------------------------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1093.344 ; gain = 382.656 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:04 ; elapsed = 00:00:16 . Memory (MB): peak = 1090.871 ; gain = 377.934 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 293 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 1093.344 ; gain = 250.680 -Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1093.344 ; gain = 382.656 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:03 ; elapsed = 00:00:14 . Memory (MB): peak = 1090.871 ; gain = 248.496 +Synthesis Optimization Complete : Time (s): cpu = 00:00:04 ; elapsed = 00:00:16 . Memory (MB): peak = 1090.871 ; gain = 377.934 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1117.988 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1112.855 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis -72 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. +73 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:32 . Memory (MB): peak = 1117.988 ; gain = 727.395 -INFO: [Common 17-600] The following parameters have non-default value. -general.maxThreads -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1117.988 ; gain = 0.000 +synth_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:21 . Memory (MB): peak = 1112.855 ; gain = 721.418 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1112.855 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp' has been generated. +INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_manual_ctrl, cache-ID = d67f719ca10fc992 +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_manual_ctrl, cache-ID = b5d522090233ffcd INFO: [Coretcl 2-1174] Renamed 10 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1117.988 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1112.855 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp' has been generated. +INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file vio_manual_ctrl_utilization_synth.rpt -pb vio_manual_ctrl_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sat Mar 18 23:34:28 2023... +INFO: [Common 17-206] Exiting Vivado at Tue Mar 21 22:54:43 2023... diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v index 466415a6..d76c3fc0 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:34:28 2023 +// Date : Tue Mar 21 22:54:43 2023 // Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) // Command : write_verilog -force -mode funcsim -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v +// D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v // Design : vio_manual_ctrl // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -22,14 +22,14 @@ module vio_manual_ctrl probe_out3, probe_out4); input clk; - output [2:0]probe_out0; + output [1:0]probe_out0; output [0:0]probe_out1; output [31:0]probe_out2; output [1:0]probe_out3; output [3:0]probe_out4; wire clk; - wire [2:0]probe_out0; + wire [1:0]probe_out0; wire [0:0]probe_out1; wire [31:0]probe_out2; wire [1:0]probe_out3; @@ -563,8 +563,8 @@ module vio_manual_ctrl (* C_PROBE_IN98_WIDTH = "1" *) (* C_PROBE_IN99_WIDTH = "1" *) (* C_PROBE_IN9_WIDTH = "1" *) - (* C_PROBE_OUT0_INIT_VAL = "3'b000" *) - (* C_PROBE_OUT0_WIDTH = "3" *) + (* C_PROBE_OUT0_INIT_VAL = "2'b10" *) + (* C_PROBE_OUT0_WIDTH = "2" *) (* C_PROBE_OUT100_INIT_VAL = "1'b0" *) (* C_PROBE_OUT100_WIDTH = "1" *) (* C_PROBE_OUT101_INIT_VAL = "1'b0" *) @@ -1081,525 +1081,525 @@ module vio_manual_ctrl (* C_XSDB_SLAVE_TYPE = "33" *) (* DONT_TOUCH *) (* DowngradeIPIdentifiedWarnings = "yes" *) - (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000101111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000010001001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000010001010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000010001011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000010001100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000010001101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000010001110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000010001111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000010010000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000010010001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000010010010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000110000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000010010011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000010010100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000010010101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000010010110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000010010111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000010011000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000010011001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000010011010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000010011011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000010011100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000110001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000010011101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000010011110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000010011111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000010100000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000010100001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000010100010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000010100011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000010100100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010100101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010100110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000110010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010100111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010101000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010101001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010101010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010101011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010101100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010101101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010101110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010101111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010110000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000110011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010110001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010110010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010110011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010110100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010110101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010110110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010110111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010111000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010111001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010111010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000110100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010111011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010111100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010111101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010111110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010111111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000011000000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000011000001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000011000010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000011000011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000011000100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000110101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000011000101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000011000110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000011000111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000011001000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000011001001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000011001010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000011001011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000011001100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000011001101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000011001110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000110110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000011001111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000011010000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000011010001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000011010010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000011010011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000011010100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000011010101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000011010110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000011010111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000011011000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000110111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000011011001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000011011010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000011011011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000011011100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000011011101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000011011110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000011011111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000011100000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000011100001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000011100010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000111000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000011100011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000011100100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011100101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011100110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011100111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011101000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011101001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011101010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011101011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011101100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000100011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000111001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011101101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011101110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011101111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011110000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011110001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011110010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011110011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011110100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011110101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011110110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000111010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011110111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011111000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011111001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011111010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011111011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011111100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011111101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011111110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011111111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000100000000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000111011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000100000001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000100000010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000100000011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000100000100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000100000101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000100000110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000100000111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000100001000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000100001001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000100001010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000111100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000100001011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000100001100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000100001101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000100001110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000100001111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000100010000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000100010001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000100010010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000100010011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000100010100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000111101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000100010101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000100010110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000100010111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000100011000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000100011001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000100011010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000100011011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000100011100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000100011101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000100011110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000111110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000100011111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000100100000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000100100001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000100100010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000100100011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000100100100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000111111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000001000000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000001000001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000001000010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000100101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000001000011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000001000100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000001000101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000001000110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000001000111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000001001000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000001001001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000001001010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000001001011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000001001100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000101001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000001001101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000001001110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000001001111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000001010000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000001010001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000001010010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000001010011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000001010100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000001010101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000001010110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000101010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000001010111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000001011000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000001011001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000001011010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000001011011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000001011100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000001011101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000001011110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000001011111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000001100000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000101011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000001100001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000001100010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000001100011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000001100100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001100101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001100110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001100111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001101000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001101001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001101010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000101100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001101011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001101100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001101101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001101110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001101111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001110000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001110001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001110010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001110011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001110100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000101101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001110101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001110110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001110111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001111000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001111001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001111010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001111011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001111100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001111101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001111110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000101110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001111111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000010000000" *) - (* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000010000001" *) - (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000010000010" *) - (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000010000011" *) - (* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000010000100" *) - (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000010000101" *) - (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000010000110" *) - (* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000010000111" *) - (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000010001000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000101110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000010001000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000010001001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000010001010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000010001011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000010001100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000010001101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000010001110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000010001111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000010010000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000010010001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000101111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000010010010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000010010011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000010010100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000010010101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000010010110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000010010111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000010011000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000010011001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000010011010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000010011011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000110000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000010011100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000010011101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000010011110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000010011111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000010100000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000010100001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000010100010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000010100011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010100100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010100101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000110001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010100110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010100111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010101000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010101001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010101010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010101011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010101100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010101101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010101110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010101111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000110010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010110000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010110001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010110010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010110011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010110100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010110101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010110110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010110111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010111000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010111001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000110011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010111010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010111011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010111100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010111101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010111110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010111111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000011000000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000011000001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000011000010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000011000011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000110100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000011000100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000011000101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000011000110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000011000111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000011001000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000011001001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000011001010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000011001011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000011001100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000011001101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000110101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000011001110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000011001111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000011010000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000011010001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000011010010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000011010011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000011010100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000011010101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000011010110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000011010111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000110110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000011011000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000011011001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000011011010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000011011011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000011011100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000011011101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000011011110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000011011111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000011100000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000011100001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000110111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000011100010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000011100011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011100100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011100101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011100110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011100111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011101000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011101001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011101010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011101011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000100010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000111000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011101100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011101101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011101110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011101111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011110000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011110001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011110010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011110011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011110100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011110101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000111001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011110110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011110111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011111000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011111001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011111010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011111011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011111100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011111101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011111110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011111111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000111010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000100000000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000100000001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000100000010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000100000011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000100000100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000100000101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000100000110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000100000111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000100001000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000100001001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000111011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000100001010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000100001011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000100001100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000100001101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000100001110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000100001111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000100010000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000100010001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000100010010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000100010011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000111100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000100010100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000100010101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000100010110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000100010111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000100011000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000100011001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000100011010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000100011011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000100011100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000100011101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000111101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000100011110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000100011111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000100100000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000100100001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000100100010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000100100011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000111110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000111111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000001000000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000001000001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000100100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000001000010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000001000011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000001000100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000001000101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000001000110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000001000111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000001001000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000001001001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000001001010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000001001011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000101000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000001001100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000001001101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000001001110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000001001111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000001010000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000001010001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000001010010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000001010011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000001010100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000001010101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000101001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000001010110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000001010111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000001011000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000001011001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000001011010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000001011011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000001011100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000001011101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000001011110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000001011111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000101010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000001100000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000001100001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000001100010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000001100011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001100100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001100101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001100110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001100111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001101000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001101001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000101011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001101010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001101011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001101100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001101101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001101110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001101111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001110000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001110001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001110010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001110011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000101100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001110100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001110101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001110110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001110111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001111000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001111001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001111010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001111011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001111100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001111101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000101101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001111110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001111111" *) + (* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000010000000" *) + (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000010000001" *) + (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000010000010" *) + (* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000010000011" *) + (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000010000100" *) + (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000010000101" *) + (* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000010000110" *) + (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000010000111" *) (* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *) - (* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000011" *) - (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000101111" *) - (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000010001001" *) - (* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000010001010" *) - (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000010001011" *) - (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000010001100" *) - (* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000010001101" *) - (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000010001110" *) - (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000010001111" *) - (* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000010010000" *) - (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000010010001" *) - (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000010010010" *) - (* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000110000" *) - (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000010010011" *) - (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000010010100" *) - (* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000010010101" *) - (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000010010110" *) - (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000010010111" *) - (* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000010011000" *) - (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000010011001" *) - (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000010011010" *) - (* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000010011011" *) - (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000010011100" *) - (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000110001" *) - (* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000010011101" *) - (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000010011110" *) - (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000010011111" *) - (* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000010100000" *) - (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000010100001" *) - (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000010100010" *) - (* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000010100011" *) - (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000010100100" *) - (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010100101" *) - (* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010100110" *) - (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000110010" *) - (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010100111" *) - (* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010101000" *) - (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010101001" *) - (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010101010" *) - (* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010101011" *) - (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010101100" *) - (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010101101" *) - (* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010101110" *) - (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010101111" *) - (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010110000" *) - (* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000110011" *) - (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010110001" *) - (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010110010" *) - (* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010110011" *) - (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010110100" *) - (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010110101" *) - (* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010110110" *) - (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010110111" *) - (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010111000" *) - (* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010111001" *) - (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010111010" *) - (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000110100" *) - (* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010111011" *) - (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010111100" *) - (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010111101" *) - (* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010111110" *) - (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010111111" *) - (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000011000000" *) - (* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000011000001" *) - (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000011000010" *) - (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000011000011" *) - (* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000011000100" *) - (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000110101" *) - (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000011000101" *) - (* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000011000110" *) - (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000011000111" *) - (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000011001000" *) - (* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000011001001" *) - (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000011001010" *) - (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000011001011" *) - (* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000011001100" *) - (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000011001101" *) - (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000011001110" *) - (* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000110110" *) - (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000011001111" *) - (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000011010000" *) - (* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000011010001" *) - (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000011010010" *) - (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000011010011" *) - (* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000011010100" *) - (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000011010101" *) - (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000011010110" *) - (* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000011010111" *) - (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000011011000" *) - (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000110111" *) - (* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000011011001" *) - (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000011011010" *) - (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000011011011" *) - (* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000011011100" *) - (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000011011101" *) - (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000011011110" *) - (* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000011011111" *) - (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000011100000" *) - (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000011100001" *) - (* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000011100010" *) - (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000111000" *) - (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000011100011" *) - (* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000011100100" *) - (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011100101" *) - (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011100110" *) - (* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011100111" *) - (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011101000" *) - (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011101001" *) - (* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011101010" *) - (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011101011" *) - (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011101100" *) - (* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000100" *) - (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000111001" *) - (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011101101" *) - (* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011101110" *) - (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011101111" *) - (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011110000" *) - (* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011110001" *) - (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011110010" *) - (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011110011" *) - (* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011110100" *) - (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011110101" *) - (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011110110" *) - (* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000111010" *) - (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011110111" *) - (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011111000" *) - (* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011111001" *) - (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011111010" *) - (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011111011" *) - (* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011111100" *) - (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011111101" *) - (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011111110" *) - (* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011111111" *) - (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000100000000" *) - (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000111011" *) - (* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000100000001" *) - (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000100000010" *) - (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000100000011" *) - (* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000100000100" *) - (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000100000101" *) - (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000100000110" *) - (* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000100000111" *) - (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000100001000" *) - (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000100001001" *) - (* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000100001010" *) - (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000111100" *) - (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000100001011" *) - (* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000100001100" *) - (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000100001101" *) - (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000100001110" *) - (* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000100001111" *) - (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000100010000" *) - (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000100010001" *) - (* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000100010010" *) - (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000100010011" *) - (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000100010100" *) - (* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000111101" *) - (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000100010101" *) - (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000100010110" *) - (* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000100010111" *) - (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000100011000" *) - (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000100011001" *) - (* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000100011010" *) - (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000100011011" *) - (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000100011100" *) - (* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000100011101" *) - (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000100011110" *) - (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000111110" *) - (* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000100011111" *) - (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000100100000" *) - (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000100100001" *) - (* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000100100010" *) - (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000100100011" *) - (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000100100100" *) - (* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000111111" *) - (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000001000000" *) - (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000001000001" *) - (* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000001000010" *) - (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000100100" *) - (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000001000011" *) - (* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000001000100" *) - (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000001000101" *) - (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000001000110" *) - (* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000001000111" *) - (* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000001001000" *) - (* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000001001001" *) - (* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000001001010" *) - (* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000001001011" *) - (* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000001001100" *) - (* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000100110" *) - (* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000001001101" *) - (* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000001001110" *) - (* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000001001111" *) - (* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000001010000" *) - (* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000001010001" *) - (* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000001010010" *) - (* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000001010011" *) - (* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000001010100" *) - (* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000001010101" *) - (* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000001010110" *) - (* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000101010" *) - (* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000001010111" *) - (* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000001011000" *) - (* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000001011001" *) - (* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000001011010" *) - (* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000001011011" *) - (* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000001011100" *) - (* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000001011101" *) - (* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000001011110" *) - (* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000001011111" *) - (* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000001100000" *) - (* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000101011" *) - (* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000001100001" *) - (* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000001100010" *) - (* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000001100011" *) - (* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000001100100" *) - (* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001100101" *) - (* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001100110" *) - (* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001100111" *) - (* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001101000" *) - (* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001101001" *) - (* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001101010" *) - (* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000101100" *) - (* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001101011" *) - (* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001101100" *) - (* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001101101" *) - (* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001101110" *) - (* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001101111" *) - (* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001110000" *) - (* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001110001" *) - (* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001110010" *) - (* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001110011" *) - (* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001110100" *) - (* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000101101" *) - (* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001110101" *) - (* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001110110" *) - (* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001110111" *) - (* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001111000" *) - (* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001111001" *) - (* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001111010" *) - (* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001111011" *) - (* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001111100" *) - (* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001111101" *) - (* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001111110" *) - (* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000101110" *) - (* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001111111" *) - (* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000010000000" *) - (* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000010000001" *) - (* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000010000010" *) - (* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000010000011" *) - (* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000010000100" *) - (* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000010000101" *) - (* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000010000110" *) - (* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000010000111" *) - (* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000010001000" *) + (* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000010" *) + (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000101110" *) + (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000010001000" *) + (* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000010001001" *) + (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000010001010" *) + (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000010001011" *) + (* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000010001100" *) + (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000010001101" *) + (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000010001110" *) + (* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000010001111" *) + (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000010010000" *) + (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000010010001" *) + (* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000101111" *) + (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000010010010" *) + (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000010010011" *) + (* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000010010100" *) + (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000010010101" *) + (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000010010110" *) + (* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000010010111" *) + (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000010011000" *) + (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000010011001" *) + (* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000010011010" *) + (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000010011011" *) + (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000110000" *) + (* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000010011100" *) + (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000010011101" *) + (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000010011110" *) + (* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000010011111" *) + (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000010100000" *) + (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000010100001" *) + (* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000010100010" *) + (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000010100011" *) + (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010100100" *) + (* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010100101" *) + (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000110001" *) + (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010100110" *) + (* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010100111" *) + (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010101000" *) + (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010101001" *) + (* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010101010" *) + (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010101011" *) + (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010101100" *) + (* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010101101" *) + (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010101110" *) + (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010101111" *) + (* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000110010" *) + (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010110000" *) + (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010110001" *) + (* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010110010" *) + (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010110011" *) + (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010110100" *) + (* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010110101" *) + (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010110110" *) + (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010110111" *) + (* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010111000" *) + (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010111001" *) + (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000110011" *) + (* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010111010" *) + (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010111011" *) + (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010111100" *) + (* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010111101" *) + (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010111110" *) + (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010111111" *) + (* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000011000000" *) + (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000011000001" *) + (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000011000010" *) + (* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000011000011" *) + (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000110100" *) + (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000011000100" *) + (* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000011000101" *) + (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000011000110" *) + (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000011000111" *) + (* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000011001000" *) + (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000011001001" *) + (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000011001010" *) + (* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000011001011" *) + (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000011001100" *) + (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000011001101" *) + (* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000110101" *) + (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000011001110" *) + (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000011001111" *) + (* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000011010000" *) + (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000011010001" *) + (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000011010010" *) + (* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000011010011" *) + (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000011010100" *) + (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000011010101" *) + (* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000011010110" *) + (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000011010111" *) + (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000110110" *) + (* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000011011000" *) + (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000011011001" *) + (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000011011010" *) + (* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000011011011" *) + (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000011011100" *) + (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000011011101" *) + (* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000011011110" *) + (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000011011111" *) + (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000011100000" *) + (* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000011100001" *) + (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000110111" *) + (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000011100010" *) + (* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000011100011" *) + (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011100100" *) + (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011100101" *) + (* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011100110" *) + (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011100111" *) + (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011101000" *) + (* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011101001" *) + (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011101010" *) + (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011101011" *) + (* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000011" *) + (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000111000" *) + (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011101100" *) + (* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011101101" *) + (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011101110" *) + (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011101111" *) + (* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011110000" *) + (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011110001" *) + (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011110010" *) + (* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011110011" *) + (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011110100" *) + (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011110101" *) + (* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000111001" *) + (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011110110" *) + (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011110111" *) + (* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011111000" *) + (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011111001" *) + (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011111010" *) + (* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011111011" *) + (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011111100" *) + (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011111101" *) + (* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011111110" *) + (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011111111" *) + (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000111010" *) + (* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000100000000" *) + (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000100000001" *) + (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000100000010" *) + (* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000100000011" *) + (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000100000100" *) + (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000100000101" *) + (* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000100000110" *) + (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000100000111" *) + (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000100001000" *) + (* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000100001001" *) + (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000111011" *) + (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000100001010" *) + (* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000100001011" *) + (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000100001100" *) + (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000100001101" *) + (* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000100001110" *) + (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000100001111" *) + (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000100010000" *) + (* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000100010001" *) + (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000100010010" *) + (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000100010011" *) + (* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000111100" *) + (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000100010100" *) + (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000100010101" *) + (* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000100010110" *) + (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000100010111" *) + (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000100011000" *) + (* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000100011001" *) + (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000100011010" *) + (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000100011011" *) + (* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000100011100" *) + (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000100011101" *) + (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000111101" *) + (* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000100011110" *) + (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000100011111" *) + (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000100100000" *) + (* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000100100001" *) + (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000100100010" *) + (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000100100011" *) + (* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000111110" *) + (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000111111" *) + (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000001000000" *) + (* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000001000001" *) + (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000100011" *) + (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000001000010" *) + (* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000001000011" *) + (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000001000100" *) + (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000001000101" *) + (* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000001000110" *) + (* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000001000111" *) + (* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000001001000" *) + (* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000001001001" *) + (* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000001001010" *) + (* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000001001011" *) + (* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000100101" *) + (* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000001001100" *) + (* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000001001101" *) + (* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000001001110" *) + (* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000001001111" *) + (* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000001010000" *) + (* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000001010001" *) + (* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000001010010" *) + (* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000001010011" *) + (* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000001010100" *) + (* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000001010101" *) + (* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000101001" *) + (* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000001010110" *) + (* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000001010111" *) + (* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000001011000" *) + (* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000001011001" *) + (* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000001011010" *) + (* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000001011011" *) + (* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000001011100" *) + (* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000001011101" *) + (* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000001011110" *) + (* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000001011111" *) + (* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000101010" *) + (* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000001100000" *) + (* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000001100001" *) + (* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000001100010" *) + (* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000001100011" *) + (* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001100100" *) + (* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001100101" *) + (* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001100110" *) + (* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001100111" *) + (* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001101000" *) + (* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001101001" *) + (* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000101011" *) + (* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001101010" *) + (* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001101011" *) + (* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001101100" *) + (* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001101101" *) + (* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001101110" *) + (* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001101111" *) + (* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001110000" *) + (* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001110001" *) + (* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001110010" *) + (* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001110011" *) + (* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000101100" *) + (* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001110100" *) + (* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001110101" *) + (* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001110110" *) + (* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001110111" *) + (* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001111000" *) + (* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001111001" *) + (* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001111010" *) + (* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001111011" *) + (* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001111100" *) + (* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001111101" *) + (* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000101101" *) + (* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001111110" *) + (* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001111111" *) + (* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000010000000" *) + (* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000010000001" *) + (* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000010000010" *) + (* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000010000011" *) + (* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000010000100" *) + (* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000010000101" *) + (* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000010000110" *) + (* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000010000111" *) (* LC_PROBE_IN_WIDTH_STRING = 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*) + (* LC_PROBE_OUT_HIGH_BIT_POS_STRING = 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*) + (* LC_PROBE_OUT_INIT_VAL_STRING = "292'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000010" *) + (* LC_PROBE_OUT_LOW_BIT_POS_STRING = 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*) + (* LC_PROBE_OUT_WIDTH_STRING = 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*) (* LC_TOTAL_PROBE_IN_WIDTH = "0" *) - (* LC_TOTAL_PROBE_OUT_WIDTH = "42" *) + (* LC_TOTAL_PROBE_OUT_WIDTH = "41" *) (* syn_noprune = "1" *) vio_manual_ctrl_vio_v3_0_20_vio inst (.clk(clk), @@ -2895,7 +2895,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all \G_PROBE_OUT[0].wr_probe_out_reg[0]_2 , Q, internal_cnt_rst); - output [2:0]probe_out0; + output [1:0]probe_out0; output [0:0]probe_out1; output [31:0]probe_out2; output [1:0]probe_out3; @@ -2931,9 +2931,8 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all wire [15:0]Bus_Data_out_int; (* async_reg = "true" *) wire Committ_1; (* async_reg = "true" *) wire Committ_2; + wire \G_PROBE_OUT[0].PROBE_OUT0_INST_n_2 ; wire \G_PROBE_OUT[0].PROBE_OUT0_INST_n_3 ; - wire \G_PROBE_OUT[0].PROBE_OUT0_INST_n_4 ; - wire \G_PROBE_OUT[0].PROBE_OUT0_INST_n_5 ; wire \G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0 ; wire \G_PROBE_OUT[0].wr_probe_out[0]_i_2_n_0 ; wire \G_PROBE_OUT[0].wr_probe_out[0]_i_6_n_0 ; @@ -2989,7 +2988,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all wire in0; wire internal_cnt_rst; wire out; - wire [2:0]probe_out0; + wire [1:0]probe_out0; wire [0:0]probe_out1; wire [31:0]probe_out2; wire [1:0]probe_out3; @@ -3017,9 +3016,9 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .Q(Committ_2), .R(1'b0)); vio_manual_ctrl_vio_v3_0_20_probe_out_one \G_PROBE_OUT[0].PROBE_OUT0_INST - (.D({\G_PROBE_OUT[0].PROBE_OUT0_INST_n_3 ,\G_PROBE_OUT[0].PROBE_OUT0_INST_n_4 ,\G_PROBE_OUT[0].PROBE_OUT0_INST_n_5 }), + (.D({\G_PROBE_OUT[0].PROBE_OUT0_INST_n_2 ,\G_PROBE_OUT[0].PROBE_OUT0_INST_n_3 }), .E(Committ_2), - .Q(Q[2:0]), + .Q(Q[1:0]), .SR(SR), .clk(clk), .out(out), @@ -3177,7 +3176,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .D(\G_PROBE_OUT[4].wr_probe_out[4]_i_1_n_0 ), .Q(wr_probe_out[4]), .R(\G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair24" *) + (* SOFT_HLUTNM = "soft_lutpair23" *) LUT3 #( .INIT(8'hB8)) \Probe_out_reg_int[0]_i_1 @@ -3193,9 +3192,9 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I2(\addr_p1_reg[2]_0 [1]), .I3(\G_PROBE_OUT[1].PROBE_OUT0_INST_n_1 ), .I4(\addr_p1_reg[2]_0 [0]), - .I5(\G_PROBE_OUT[0].PROBE_OUT0_INST_n_5 ), + .I5(\G_PROBE_OUT[0].PROBE_OUT0_INST_n_3 ), .O(\Probe_out_reg_int[0]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair28" *) + (* SOFT_HLUTNM = "soft_lutpair27" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[10]_i_1 @@ -3203,7 +3202,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[10]), .O(\Probe_out_reg_int[10]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair27" *) + (* SOFT_HLUTNM = "soft_lutpair26" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[11]_i_1 @@ -3211,7 +3210,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[11]), .O(\Probe_out_reg_int[11]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair25" *) + (* SOFT_HLUTNM = "soft_lutpair24" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[12]_i_1 @@ -3219,7 +3218,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[12]), .O(\Probe_out_reg_int[12]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair26" *) + (* SOFT_HLUTNM = "soft_lutpair25" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[13]_i_1 @@ -3227,7 +3226,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[13]), .O(\Probe_out_reg_int[13]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair26" *) + (* SOFT_HLUTNM = "soft_lutpair25" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[14]_i_1 @@ -3235,7 +3234,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[14]), .O(\Probe_out_reg_int[14]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair25" *) + (* SOFT_HLUTNM = "soft_lutpair24" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[15]_i_1 @@ -3243,7 +3242,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[15]), .O(\Probe_out_reg_int[15]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair24" *) + (* SOFT_HLUTNM = "soft_lutpair23" *) LUT3 #( .INIT(8'hB8)) \Probe_out_reg_int[1]_i_1 @@ -3257,18 +3256,17 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all (.I0(\G_PROBE_OUT[3].PROBE_OUT0_INST_n_2 ), .I1(Bus_Data_out_int[1]), .I2(\addr_p1_reg[2]_0 [1]), - .I3(\G_PROBE_OUT[0].PROBE_OUT0_INST_n_4 ), + .I3(\G_PROBE_OUT[0].PROBE_OUT0_INST_n_2 ), .I4(\addr_p1_reg[2]_0 [0]), .O(\Probe_out_reg_int[1]_i_2_n_0 )); - LUT6 #( - .INIT(64'h88888888B8BBB888)) + LUT5 #( + .INIT(32'h88B88888)) \Probe_out_reg_int[2]_i_1 (.I0(\G_PROBE_OUT[4].PROBE_OUT0_INST_n_5 ), .I1(\addr_p1_reg[2]_0 [2]), - .I2(Bus_Data_out_int[2]), - .I3(\addr_p1_reg[2]_0 [1]), - .I4(\G_PROBE_OUT[0].PROBE_OUT0_INST_n_3 ), - .I5(\addr_p1_reg[2]_0 [0]), + .I2(\addr_p1_reg[2]_0 [1]), + .I3(\addr_p1_reg[2]_0 [0]), + .I4(Bus_Data_out_int[2]), .O(probe_out_mem[2])); LUT5 #( .INIT(32'h88B88888)) @@ -3279,7 +3277,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I3(\addr_p1_reg[2]_0 [0]), .I4(Bus_Data_out_int[3]), .O(probe_out_mem[3])); - (* SOFT_HLUTNM = "soft_lutpair30" *) + (* SOFT_HLUTNM = "soft_lutpair29" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[4]_i_1 @@ -3287,7 +3285,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[4]), .O(\Probe_out_reg_int[4]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair30" *) + (* SOFT_HLUTNM = "soft_lutpair29" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[5]_i_1 @@ -3295,7 +3293,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[5]), .O(\Probe_out_reg_int[5]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair29" *) + (* SOFT_HLUTNM = "soft_lutpair28" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[6]_i_1 @@ -3303,7 +3301,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[6]), .O(\Probe_out_reg_int[6]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair29" *) + (* SOFT_HLUTNM = "soft_lutpair28" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[7]_i_1 @@ -3311,7 +3309,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[7]), .O(\Probe_out_reg_int[7]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair28" *) + (* SOFT_HLUTNM = "soft_lutpair27" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[8]_i_1 @@ -3319,7 +3317,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_all .I1(\addr_p1_reg[2]_0 [0]), .I2(Bus_Data_out_int[8]), .O(\Probe_out_reg_int[8]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair27" *) + (* SOFT_HLUTNM = "soft_lutpair26" *) LUT3 #( .INIT(8'h20)) \Probe_out_reg_int[9]_i_1 @@ -3453,25 +3451,24 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one out, E, clk); - output [2:0]probe_out0; - output [2:0]D; + output [1:0]probe_out0; + output [1:0]D; input [0:0]SR; - input [2:0]Q; + input [1:0]Q; input [0:0]wr_probe_out; input out; input [0:0]E; input clk; - wire [2:0]D; + wire [1:0]D; wire [0:0]E; - wire [2:0]Q; + wire [1:0]Q; (* DIRECT_RESET *) wire [0:0]SR; wire clk; wire \data_int[0]_i_1_n_0 ; wire \data_int[1]_i_1_n_0 ; - wire \data_int[2]_i_1_n_0 ; wire out; - (* DONT_TOUCH *) wire [2:0]probe_out0; + (* DONT_TOUCH *) wire [1:0]probe_out0; wire [0:0]wr_probe_out; (* DONT_TOUCH *) @@ -3484,20 +3481,12 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one .R(SR)); (* DONT_TOUCH *) (* KEEP = "yes" *) - FDRE \Probe_out_reg[1] + FDSE \Probe_out_reg[1] (.C(clk), .CE(E), .D(D[1]), .Q(probe_out0[1]), - .R(SR)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - FDRE \Probe_out_reg[2] - (.C(clk), - .CE(E), - .D(D[2]), - .Q(probe_out0[2]), - .R(SR)); + .S(SR)); LUT3 #( .INIT(8'hB8)) \data_int[0]_i_1 @@ -3505,7 +3494,6 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one .I1(wr_probe_out), .I2(D[0]), .O(\data_int[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair14" *) LUT3 #( .INIT(8'hB8)) \data_int[1]_i_1 @@ -3513,32 +3501,18 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one .I1(wr_probe_out), .I2(D[1]), .O(\data_int[1]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT3 #( - .INIT(8'hB8)) - \data_int[2]_i_1 - (.I0(Q[2]), - .I1(wr_probe_out), - .I2(D[2]), - .O(\data_int[2]_i_1_n_0 )); FDRE \data_int_reg[0] (.C(out), .CE(1'b1), .D(\data_int[0]_i_1_n_0 ), .Q(D[0]), .R(SR)); - FDRE \data_int_reg[1] + FDSE \data_int_reg[1] (.C(out), .CE(1'b1), .D(\data_int[1]_i_1_n_0 ), .Q(D[1]), - .R(SR)); - FDRE \data_int_reg[2] - (.C(out), - .CE(1'b1), - .D(\data_int[2]_i_1_n_0 ), - .Q(D[2]), - .R(SR)); + .S(SR)); endmodule (* ORIG_REF_NAME = "vio_v3_0_20_probe_out_one" *) @@ -3659,7 +3633,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 wire s_den_o; wire s_dwe_o; - (* SOFT_HLUTNM = "soft_lutpair22" *) + (* SOFT_HLUTNM = "soft_lutpair21" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[0]_i_1 @@ -3667,7 +3641,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [0]), .O(\Bus_Data_out_int[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair17" *) + (* SOFT_HLUTNM = "soft_lutpair16" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[10]_i_1 @@ -3675,7 +3649,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [10]), .O(\Bus_Data_out_int[10]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair17" *) + (* SOFT_HLUTNM = "soft_lutpair16" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[11]_i_1 @@ -3683,7 +3657,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [11]), .O(\Bus_Data_out_int[11]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair16" *) + (* SOFT_HLUTNM = "soft_lutpair15" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[12]_i_1 @@ -3691,7 +3665,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [12]), .O(\Bus_Data_out_int[12]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair16" *) + (* SOFT_HLUTNM = "soft_lutpair15" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[13]_i_1 @@ -3699,7 +3673,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [13]), .O(\Bus_Data_out_int[13]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair15" *) + (* SOFT_HLUTNM = "soft_lutpair14" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[14]_i_1 @@ -3707,7 +3681,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [14]), .O(\Bus_Data_out_int[14]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair15" *) + (* SOFT_HLUTNM = "soft_lutpair14" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[15]_i_1 @@ -3715,7 +3689,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [15]), .O(\Bus_Data_out_int[15]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair22" *) + (* SOFT_HLUTNM = "soft_lutpair21" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[1]_i_1 @@ -3723,7 +3697,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [1]), .O(\Bus_Data_out_int[1]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair21" *) + (* SOFT_HLUTNM = "soft_lutpair20" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[2]_i_1 @@ -3731,7 +3705,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [2]), .O(\Bus_Data_out_int[2]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair21" *) + (* SOFT_HLUTNM = "soft_lutpair20" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[3]_i_1 @@ -3739,7 +3713,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [3]), .O(\Bus_Data_out_int[3]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair20" *) + (* SOFT_HLUTNM = "soft_lutpair19" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[4]_i_1 @@ -3747,7 +3721,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [4]), .O(\Bus_Data_out_int[4]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair20" *) + (* SOFT_HLUTNM = "soft_lutpair19" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[5]_i_1 @@ -3755,7 +3729,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [5]), .O(\Bus_Data_out_int[5]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair19" *) + (* SOFT_HLUTNM = "soft_lutpair18" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[6]_i_1 @@ -3763,7 +3737,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [6]), .O(\Bus_Data_out_int[6]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair19" *) + (* SOFT_HLUTNM = "soft_lutpair18" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[7]_i_1 @@ -3771,7 +3745,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [7]), .O(\Bus_Data_out_int[7]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair18" *) + (* SOFT_HLUTNM = "soft_lutpair17" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[8]_i_1 @@ -3779,7 +3753,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1 .I1(addr_count[0]), .I2(\mem_probe_out[0] [8]), .O(\Bus_Data_out_int[8]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair18" *) + (* SOFT_HLUTNM = "soft_lutpair17" *) LUT3 #( .INIT(8'hB8)) \Bus_Data_out_int[9]_i_1 @@ -4448,7 +4422,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized2 .D(D[1]), .Q(probe_out3[1]), .S(SR)); - (* SOFT_HLUTNM = "soft_lutpair23" *) + (* SOFT_HLUTNM = "soft_lutpair22" *) LUT3 #( .INIT(8'hB8)) \data_int[0]_i_1 @@ -4456,7 +4430,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized2 .I1(wr_probe_out), .I2(D[0]), .O(\data_int[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair23" *) + (* SOFT_HLUTNM = "soft_lutpair22" *) LUT3 #( .INIT(8'hB8)) \data_int[1]_i_1 @@ -4587,7 +4561,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_width wire rd_probe_out_width; wire s_rst_o; - (* SOFT_HLUTNM = "soft_lutpair31" *) + (* SOFT_HLUTNM = "soft_lutpair30" *) LUT5 #( .INIT(32'h0000001A)) \addr_count[0]_i_1 @@ -4597,7 +4571,7 @@ module vio_manual_ctrl_vio_v3_0_20_probe_width .I3(s_rst_o), .I4(internal_cnt_rst), .O(\addr_count[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair31" *) + (* SOFT_HLUTNM = "soft_lutpair30" *) LUT5 #( .INIT(32'h0000002C)) \addr_count[1]_i_1 @@ -4619,20 +4593,20 @@ module vio_manual_ctrl_vio_v3_0_20_probe_width .D(\addr_count[1]_i_1_n_0 ), .Q(addr_count[1]), .R(1'b0)); - LUT2 #( - .INIT(4'h6)) - \probe_width_int[0]_i_1 - (.I0(addr_count[0]), - .I1(addr_count[1]), - .O(probe_width_mem[0])); - (* SOFT_HLUTNM = "soft_lutpair32" *) LUT2 #( .INIT(4'h7)) - \probe_width_int[1]_i_1 + \probe_width_int[0]_i_1 (.I0(addr_count[1]), .I1(addr_count[0]), + .O(probe_width_mem[0])); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT2 #( + .INIT(4'h6)) + \probe_width_int[1]_i_1 + (.I0(addr_count[0]), + .I1(addr_count[1]), .O(probe_width_mem[1])); - (* SOFT_HLUTNM = "soft_lutpair32" *) + (* SOFT_HLUTNM = "soft_lutpair31" *) LUT2 #( .INIT(4'h2)) \probe_width_int[8]_i_1 @@ -4751,7 +4725,7 @@ endmodule (* C_PROBE_IN92_WIDTH = "1" *) (* C_PROBE_IN93_WIDTH = "1" *) (* C_PROBE_IN94_WIDTH = "1" *) (* C_PROBE_IN95_WIDTH = "1" *) (* C_PROBE_IN96_WIDTH = "1" *) (* C_PROBE_IN97_WIDTH = "1" *) (* C_PROBE_IN98_WIDTH = "1" *) (* C_PROBE_IN99_WIDTH = "1" *) (* C_PROBE_IN9_WIDTH = "1" *) -(* C_PROBE_OUT0_INIT_VAL = "3'b000" *) (* C_PROBE_OUT0_WIDTH = "3" *) (* C_PROBE_OUT100_INIT_VAL = "1'b0" *) +(* C_PROBE_OUT0_INIT_VAL = "2'b10" *) (* C_PROBE_OUT0_WIDTH = "2" *) (* C_PROBE_OUT100_INIT_VAL = "1'b0" *) (* C_PROBE_OUT100_WIDTH = "1" *) (* C_PROBE_OUT101_INIT_VAL = "1'b0" *) (* C_PROBE_OUT101_WIDTH = "1" *) (* C_PROBE_OUT102_INIT_VAL = "1'b0" *) (* C_PROBE_OUT102_WIDTH = "1" *) (* C_PROBE_OUT103_INIT_VAL = "1'b0" *) (* C_PROBE_OUT103_WIDTH = "1" *) (* C_PROBE_OUT104_INIT_VAL = "1'b0" *) (* C_PROBE_OUT104_WIDTH = "1" *) @@ -4923,180 +4897,180 @@ endmodule (* C_PROBE_OUT98_WIDTH = "1" *) (* C_PROBE_OUT99_INIT_VAL = "1'b0" *) (* C_PROBE_OUT99_WIDTH = "1" *) (* C_PROBE_OUT9_INIT_VAL = "1'b0" *) (* C_PROBE_OUT9_WIDTH = "1" *) (* C_USE_TEST_REG = "1" *) (* C_XDEVICEFAMILY = "kintex7" *) (* C_XLNX_HW_PROBE_INFO = "DEFAULT" *) (* C_XSDB_SLAVE_TYPE = "33" *) -(* DowngradeIPIdentifiedWarnings = "yes" *) (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000010001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000010001010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000010001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000010001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000010001101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000010001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000010001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000010010000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000010010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000010010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000110000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000010010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000010010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000010010101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000010010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000010010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000010011000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000010011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000010011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000010011011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000010011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000010011101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000010011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000010011111" *) (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000010100000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000010100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000010100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000010100011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000010100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010100110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010101000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010101011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010101110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000110011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010110011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010110110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010111001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010111011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010111110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000011000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000011000001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000011000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000011000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000011000100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000011000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000011000110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000011000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000011001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000011001001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000011001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000011001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000011001100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000011001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000011001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000110110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000011001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000011010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000011010001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000011010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000011010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000011010100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000011010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000011010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000011010111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000011011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000011011001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000011011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000011011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000011011100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000011011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000011011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000011011111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000011100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000011100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000011100010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000011100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000011100100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011100111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011101010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000100011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011101110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011110001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011110100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000111010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011111001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011111100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011111111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000100000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000100000001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000100000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000100000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000100000100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000100000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000100000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000100000111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000100001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000100001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000100001010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000100001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000100001100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000100001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000100001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000100001111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000100010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000100010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000100010010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000100010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000100010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000111101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000100010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000100010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000100010111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000100011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000100011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000100011010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000100011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000100011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000100011101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000100011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000100011111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000100100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000100100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000100100010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000100100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000100100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000111111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000001000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000001000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000001000010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000001000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000001000100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000001000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000001000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000001000111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000001001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000001001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000001001010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000001001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000001001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000101001" *) -(* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000001001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000001001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000001001111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000001010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000001010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000001010010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000001010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000001010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000001010101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000001010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000001010111" *) -(* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000001011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000001011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000001011010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000001011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000001011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000001011101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000001011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000001011111" *) (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000001100000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000001100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000001100010" *) -(* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000001100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000001100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001100101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001101000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000101100" *) -(* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001101101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001110000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001110011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001110101" *) -(* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001111000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001111011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001111110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000010000000" *) -(* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000010000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000010000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000010000011" *) -(* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000010000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000010000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000010000110" *) -(* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000010000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000010001000" *) (* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *) -(* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000011" *) (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000101111" *) (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000010001001" *) -(* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000010001010" *) (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000010001011" *) (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000010001100" *) -(* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000010001101" *) (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000010001110" *) (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000010001111" *) -(* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000010010000" *) (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000010010001" *) (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000010010010" *) -(* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000110000" *) (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000010010011" *) (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000010010100" *) -(* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000010010101" *) (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000010010110" *) (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000010010111" *) -(* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000010011000" *) (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000010011001" *) (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000010011010" *) -(* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000010011011" *) (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000010011100" *) (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000110001" *) -(* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000010011101" *) (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000010011110" *) (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000010011111" *) -(* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000010100000" *) (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000010100001" *) (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000010100010" *) -(* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000010100011" *) (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000010100100" *) (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010100101" *) -(* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010100110" *) (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000110010" *) (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010100111" *) -(* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010101000" *) (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010101001" *) (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010101010" *) -(* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010101011" *) (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010101100" *) (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010101101" *) -(* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010101110" *) (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010101111" *) (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010110000" *) -(* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000110011" *) (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010110001" *) (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010110010" *) -(* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010110011" *) (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010110100" *) (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010110101" *) -(* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010110110" *) (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010110111" *) (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010111000" *) -(* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010111001" *) (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010111010" *) (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000110100" *) -(* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010111011" *) (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010111100" *) (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010111101" *) -(* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010111110" *) (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010111111" *) (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000011000000" *) -(* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000011000001" *) (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000011000010" *) (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000011000011" *) -(* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000011000100" *) (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000110101" *) (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000011000101" *) -(* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000011000110" *) (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000011000111" *) (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000011001000" *) -(* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000011001001" *) (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000011001010" *) (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000011001011" *) -(* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000011001100" *) (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000011001101" *) (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000011001110" *) -(* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000110110" *) (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000011001111" *) (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000011010000" *) -(* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000011010001" *) (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000011010010" *) (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000011010011" *) -(* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000011010100" *) (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000011010101" *) (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000011010110" *) -(* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000011010111" *) (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000011011000" *) (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000110111" *) -(* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000011011001" *) (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000011011010" *) (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000011011011" *) -(* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000011011100" *) (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000011011101" *) (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000011011110" *) -(* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000011011111" *) (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000011100000" *) (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000011100001" *) -(* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000011100010" *) (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000111000" *) (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000011100011" *) -(* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000011100100" *) (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011100101" *) (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011100110" *) -(* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011100111" *) (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011101000" *) (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011101001" *) -(* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011101010" *) (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011101011" *) (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011101100" *) -(* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000100" *) (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000111001" *) (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011101101" *) -(* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011101110" *) (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011101111" *) (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011110000" *) -(* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011110001" *) (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011110010" *) (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011110011" *) -(* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011110100" *) (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011110101" *) (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011110110" *) -(* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000111010" *) (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011110111" *) (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011111000" *) -(* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011111001" *) (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011111010" *) (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011111011" *) -(* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011111100" *) (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011111101" *) (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011111110" *) -(* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011111111" *) (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000100000000" *) (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000111011" *) -(* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000100000001" *) (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000100000010" *) (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000100000011" *) -(* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000100000100" *) (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000100000101" *) (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000100000110" *) -(* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000100000111" *) (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000100001000" *) (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000100001001" *) -(* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000100001010" *) (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000111100" *) (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000100001011" *) -(* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000100001100" *) (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000100001101" *) (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000100001110" *) -(* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000100001111" *) (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000100010000" *) (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000100010001" *) -(* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000100010010" *) (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000100010011" *) (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000100010100" *) -(* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000111101" *) (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000100010101" *) (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000100010110" *) -(* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000100010111" *) (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000100011000" *) (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000100011001" *) -(* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000100011010" *) (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000100011011" *) (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000100011100" *) -(* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000100011101" *) (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000100011110" *) (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000111110" *) -(* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000100011111" *) (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000100100000" *) (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000100100001" *) -(* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000100100010" *) (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000100100011" *) (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000100100100" *) -(* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000111111" *) (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000001000000" *) (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000001000001" *) -(* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000001000010" *) (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000100100" *) (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000001000011" *) -(* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000001000100" *) (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000001000101" *) (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000001000110" *) -(* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000001000111" *) (* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000001001000" *) (* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000001001001" *) -(* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000001001010" *) (* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000001001011" *) (* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000001001100" *) -(* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000100110" *) (* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000001001101" *) (* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000001001110" *) -(* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000001001111" *) (* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000001010000" *) (* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000001010001" *) -(* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000001010010" *) (* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000001010011" *) (* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000001010100" *) -(* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000001010101" *) (* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000001010110" *) (* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000101010" *) -(* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000001010111" *) (* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000001011000" *) (* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000001011001" *) -(* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000001011010" *) (* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000001011011" *) (* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000001011100" *) -(* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000001011101" *) (* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000001011110" *) (* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000001011111" *) -(* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000001100000" *) (* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000101011" *) (* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000001100001" *) -(* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000001100010" *) (* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000001100011" *) (* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000001100100" *) -(* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001100101" *) (* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001100110" *) (* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001100111" *) -(* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001101000" *) (* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001101001" *) (* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001101010" *) -(* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000101100" *) (* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001101011" *) (* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001101100" *) -(* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001101101" *) (* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001101110" *) (* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001101111" *) -(* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001110000" *) (* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001110001" *) (* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001110010" *) -(* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001110011" *) (* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001110100" *) (* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000101101" *) -(* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001110101" *) (* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001110110" *) (* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001110111" *) -(* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001111000" *) (* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001111001" *) (* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001111010" *) -(* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001111011" *) (* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001111100" *) (* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001111101" *) -(* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001111110" *) (* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000101110" *) (* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001111111" *) -(* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000010000000" *) (* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000010000001" *) (* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000010000010" *) -(* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000010000011" *) (* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000010000100" *) (* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000010000101" *) -(* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000010000110" *) (* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000010000111" *) (* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000010001000" *) -(* LC_PROBE_IN_WIDTH_STRING = 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*) (* LC_PROBE_OUT_HIGH_BIT_POS_STRING = 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*) (* LC_PROBE_OUT_WIDTH_STRING = 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*) (* LC_TOTAL_PROBE_IN_WIDTH = "0" *) -(* LC_TOTAL_PROBE_OUT_WIDTH = "42" *) (* ORIG_REF_NAME = "vio_v3_0_20_vio" *) (* dont_touch = "true" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000010001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000010001001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000010001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000010001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000010001100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000010001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000010001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000010001111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000010010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000010010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000101111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000010010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000010010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000010010100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000010010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000010010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000010010111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000010011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000010011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000010011010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000010011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000010011100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000010011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000010011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000010011111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000010100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000010100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000010100010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000010100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010100101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010100111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010101010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010101101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000110010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010110010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010110101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010111000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010111010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010111101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000011000000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000011000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000011000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000011000011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000011000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000011000101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000011000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000011000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000011001000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000011001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000011001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000011001011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000011001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000011001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000110101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000011001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000011001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000011010000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000011010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000011010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000011010011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000011010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000011010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000011010110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000011010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000011011000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000011011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000011011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000011011011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000011011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000011011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000011011110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000011011111" *) (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000011100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000011100001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000011100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000011100011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011100110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011101001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000100010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011101101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011110000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011110011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000111001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011111000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011111011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011111110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000100000000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000100000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000100000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000100000011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000100000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000100000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000100000110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000100000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000100001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000100001001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000100001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000100001011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000100001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000100001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000100001110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000100001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000100010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000100010001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000100010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000100010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000111100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000100010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000100010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000100010110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000100010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000100011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000100011001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000100011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000100011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000100011100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000100011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000100011110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000100011111" *) (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000100100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000100100001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000100100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000100100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000111110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000001000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000001000001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000001000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000001000011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000001000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000001000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000001000110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000001000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000001001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000001001001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000001001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000001001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000101000" *) +(* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000001001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000001001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000001001110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000001001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000001010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000001010001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000001010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000001010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000001010100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000001010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000001010110" *) +(* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000001010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000001011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000001011001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000001011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000001011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000001011100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000001011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000001011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000001011111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000001100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000001100001" *) +(* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000001100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000001100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001100100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001100111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000101011" *) +(* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001101100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001101111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001110010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001110100" *) +(* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001110111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001111010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001111101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001111111" *) +(* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000010000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000010000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000010000010" *) +(* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000010000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000010000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000010000101" *) +(* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000010000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000010000111" *) (* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *) +(* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000010" *) (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000101110" *) (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000010001000" *) +(* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000010001001" *) (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000010001010" *) (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000010001011" *) +(* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000010001100" *) (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000010001101" *) (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000010001110" *) +(* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000010001111" *) (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000010010000" *) (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000010010001" *) +(* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000101111" *) (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000010010010" *) (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000010010011" *) +(* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000010010100" *) (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000010010101" *) (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000010010110" *) +(* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000010010111" *) (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000010011000" *) (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000010011001" *) +(* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000010011010" *) (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000010011011" *) (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000110000" *) +(* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000010011100" *) (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000010011101" *) (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000010011110" *) +(* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000010011111" *) (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000010100000" *) (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000010100001" *) +(* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000010100010" *) (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000010100011" *) (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010100100" *) +(* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010100101" *) (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000110001" *) (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010100110" *) +(* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010100111" *) (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010101000" *) (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010101001" *) +(* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010101010" *) (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010101011" *) (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010101100" *) +(* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010101101" *) (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010101110" *) (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010101111" *) +(* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000110010" *) (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010110000" *) (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010110001" *) +(* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010110010" *) (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010110011" *) (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010110100" *) +(* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010110101" *) (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010110110" *) (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010110111" *) +(* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010111000" *) (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010111001" *) (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000110011" *) +(* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010111010" *) (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010111011" *) (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010111100" *) +(* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010111101" *) (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010111110" *) (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010111111" *) +(* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000011000000" *) (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000011000001" *) (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000011000010" *) +(* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000011000011" *) (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000110100" *) (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000011000100" *) +(* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000011000101" *) (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000011000110" *) (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000011000111" *) +(* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000011001000" *) (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000011001001" *) (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000011001010" *) +(* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000011001011" *) (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000011001100" *) (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000011001101" *) +(* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000110101" *) (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000011001110" *) (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000011001111" *) +(* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000011010000" *) (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000011010001" *) (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000011010010" *) +(* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000011010011" *) (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000011010100" *) (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000011010101" *) +(* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000011010110" *) (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000011010111" *) (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000110110" *) +(* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000011011000" *) (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000011011001" *) (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000011011010" *) +(* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000011011011" *) (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000011011100" *) (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000011011101" *) +(* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000011011110" *) (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000011011111" *) (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000011100000" *) +(* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000011100001" *) (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000110111" *) (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000011100010" *) +(* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000011100011" *) (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011100100" *) (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011100101" *) +(* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011100110" *) (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011100111" *) (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011101000" *) +(* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011101001" *) (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011101010" *) (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011101011" *) +(* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000011" *) (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000111000" *) (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011101100" *) +(* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011101101" *) (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011101110" *) (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011101111" *) +(* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011110000" *) (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011110001" *) (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011110010" *) +(* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011110011" *) (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011110100" *) (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011110101" *) +(* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000111001" *) (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011110110" *) (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011110111" *) +(* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011111000" *) (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011111001" *) (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011111010" *) +(* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011111011" *) (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011111100" *) (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011111101" *) +(* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011111110" *) (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011111111" *) (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000111010" *) +(* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000100000000" *) (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000100000001" *) (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000100000010" *) +(* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000100000011" *) (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000100000100" *) (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000100000101" *) +(* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000100000110" *) (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000100000111" *) (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000100001000" *) +(* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000100001001" *) (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000111011" *) (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000100001010" *) +(* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000100001011" *) (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000100001100" *) (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000100001101" *) +(* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000100001110" *) (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000100001111" *) (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000100010000" *) +(* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000100010001" *) (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000100010010" *) (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000100010011" *) +(* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000111100" *) (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000100010100" *) (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000100010101" *) +(* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000100010110" *) (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000100010111" *) (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000100011000" *) +(* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000100011001" *) (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000100011010" *) (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000100011011" *) +(* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000100011100" *) (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000100011101" *) (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000111101" *) +(* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000100011110" *) (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000100011111" *) (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000100100000" *) +(* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000100100001" *) (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000100100010" *) (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000100100011" *) +(* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000111110" *) (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000111111" *) (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000001000000" *) +(* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000001000001" *) (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000100011" *) (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000001000010" *) +(* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000001000011" *) (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000001000100" *) (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000001000101" *) +(* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000001000110" *) (* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000001000111" *) (* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000001001000" *) +(* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000001001001" *) (* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000001001010" *) (* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000001001011" *) +(* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000100101" *) (* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000001001100" *) (* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000001001101" *) +(* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000001001110" *) (* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000001001111" *) (* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000001010000" *) +(* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000001010001" *) (* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000001010010" *) (* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000001010011" *) +(* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000001010100" *) (* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000001010101" *) (* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000101001" *) +(* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000001010110" *) (* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000001010111" *) (* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000001011000" *) +(* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000001011001" *) (* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000001011010" *) (* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000001011011" *) +(* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000001011100" *) (* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000001011101" *) (* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000001011110" *) +(* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000001011111" *) (* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000101010" *) (* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000001100000" *) +(* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000001100001" *) (* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000001100010" *) (* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000001100011" *) +(* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001100100" *) (* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001100101" *) (* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001100110" *) +(* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001100111" *) (* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001101000" *) (* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001101001" *) +(* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000101011" *) (* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001101010" *) (* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001101011" *) +(* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001101100" *) (* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001101101" *) (* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001101110" *) +(* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001101111" *) (* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001110000" *) (* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001110001" *) +(* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001110010" *) (* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001110011" *) (* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000101100" *) +(* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001110100" *) (* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001110101" *) (* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001110110" *) +(* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001110111" *) (* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001111000" *) (* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001111001" *) +(* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001111010" *) (* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001111011" *) (* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001111100" *) +(* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001111101" *) (* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000101101" *) (* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001111110" *) +(* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001111111" *) (* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000010000000" *) (* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000010000001" *) +(* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000010000010" *) (* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000010000011" *) (* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000010000100" *) +(* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000010000101" *) (* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000010000110" *) (* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000010000111" *) +(* LC_PROBE_IN_WIDTH_STRING = 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*) (* LC_PROBE_OUT_HIGH_BIT_POS_STRING = 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*) (* LC_PROBE_OUT_INIT_VAL_STRING = "292'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000010" *) +(* LC_PROBE_OUT_LOW_BIT_POS_STRING = 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*) (* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000001000111110000000000000001" *) (* LC_TOTAL_PROBE_IN_WIDTH = "0" *) +(* LC_TOTAL_PROBE_OUT_WIDTH = "41" *) (* ORIG_REF_NAME = "vio_v3_0_20_vio" *) (* dont_touch = "true" *) module vio_manual_ctrl_vio_v3_0_20_vio (clk, probe_in0, @@ -5872,7 +5846,7 @@ module vio_manual_ctrl_vio_v3_0_20_vio input [0:0]probe_in255; (* dont_touch = "true" *) input [36:0]sl_iport0; (* dont_touch = "true" *) output [16:0]sl_oport0; - output [2:0]probe_out0; + output [1:0]probe_out0; output [0:0]probe_out1; output [31:0]probe_out2; output [1:0]probe_out3; @@ -6133,7 +6107,8 @@ module vio_manual_ctrl_vio_v3_0_20_vio wire DECODER_INST_n_5; wire DECODER_INST_n_6; wire DECODER_INST_n_7; - wire PROBE_OUT_ALL_INST_n_42; + wire PROBE_OUT_ALL_INST_n_41; + wire PROBE_OUT_ALL_INST_n_45; wire PROBE_OUT_ALL_INST_n_46; wire PROBE_OUT_ALL_INST_n_47; wire PROBE_OUT_ALL_INST_n_48; @@ -6149,7 +6124,6 @@ module vio_manual_ctrl_vio_v3_0_20_vio wire PROBE_OUT_ALL_INST_n_58; wire PROBE_OUT_ALL_INST_n_59; wire PROBE_OUT_ALL_INST_n_60; - wire PROBE_OUT_ALL_INST_n_61; wire [16:0]bus_addr; (* DONT_TOUCH *) wire bus_clk; wire \bus_data_int_reg_n_0_[0] ; @@ -6178,7 +6152,7 @@ module vio_manual_ctrl_vio_v3_0_20_vio wire committ; wire internal_cnt_rst; wire p_0_in; - wire [2:0]probe_out0; + wire [1:0]probe_out0; wire [0:0]probe_out1; wire [31:0]probe_out2; wire [1:0]probe_out3; @@ -6441,29 +6415,29 @@ module vio_manual_ctrl_vio_v3_0_20_vio assign probe_out98[0] = \ ; assign probe_out99[0] = \ ; vio_manual_ctrl_vio_v3_0_20_decoder DECODER_INST - (.\Bus_data_out_reg[10]_0 (PROBE_OUT_ALL_INST_n_55), - .\Bus_data_out_reg[11]_0 (PROBE_OUT_ALL_INST_n_54), - .\Bus_data_out_reg[12]_0 (PROBE_OUT_ALL_INST_n_53), - .\Bus_data_out_reg[13]_0 (PROBE_OUT_ALL_INST_n_52), - .\Bus_data_out_reg[14]_0 (PROBE_OUT_ALL_INST_n_51), + (.\Bus_data_out_reg[10]_0 (PROBE_OUT_ALL_INST_n_54), + .\Bus_data_out_reg[11]_0 (PROBE_OUT_ALL_INST_n_53), + .\Bus_data_out_reg[12]_0 (PROBE_OUT_ALL_INST_n_52), + .\Bus_data_out_reg[13]_0 (PROBE_OUT_ALL_INST_n_51), + .\Bus_data_out_reg[14]_0 (PROBE_OUT_ALL_INST_n_50), .\Bus_data_out_reg[15]_0 (bus_do), - .\Bus_data_out_reg[15]_1 (PROBE_OUT_ALL_INST_n_50), + .\Bus_data_out_reg[15]_1 (PROBE_OUT_ALL_INST_n_49), .\Bus_data_out_reg[3]_0 ({probe_width_int[8],probe_width_int[1:0]}), - .\Bus_data_out_reg[4]_0 (PROBE_OUT_ALL_INST_n_61), - .\Bus_data_out_reg[5]_0 (PROBE_OUT_ALL_INST_n_60), - .\Bus_data_out_reg[6]_0 (PROBE_OUT_ALL_INST_n_59), - .\Bus_data_out_reg[7]_0 (PROBE_OUT_ALL_INST_n_58), - .\Bus_data_out_reg[8]_0 (PROBE_OUT_ALL_INST_n_57), - .\Bus_data_out_reg[9]_0 (PROBE_OUT_ALL_INST_n_56), + .\Bus_data_out_reg[4]_0 (PROBE_OUT_ALL_INST_n_60), + .\Bus_data_out_reg[5]_0 (PROBE_OUT_ALL_INST_n_59), + .\Bus_data_out_reg[6]_0 (PROBE_OUT_ALL_INST_n_58), + .\Bus_data_out_reg[7]_0 (PROBE_OUT_ALL_INST_n_57), + .\Bus_data_out_reg[8]_0 (PROBE_OUT_ALL_INST_n_56), + .\Bus_data_out_reg[9]_0 (PROBE_OUT_ALL_INST_n_55), .\G_PROBE_OUT[0].wr_probe_out[0]_i_3_0 (DECODER_INST_n_7), .\G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 (DECODER_INST_n_5), - .Q({PROBE_OUT_ALL_INST_n_46,PROBE_OUT_ALL_INST_n_47,PROBE_OUT_ALL_INST_n_48,PROBE_OUT_ALL_INST_n_49}), + .Q({PROBE_OUT_ALL_INST_n_45,PROBE_OUT_ALL_INST_n_46,PROBE_OUT_ALL_INST_n_47,PROBE_OUT_ALL_INST_n_48}), .SR(clear), .in0(committ), .internal_cnt_rst(internal_cnt_rst), .out(bus_clk), .\probe_out_modified_reg[15]_0 ({\bus_data_int_reg_n_0_[15] ,\bus_data_int_reg_n_0_[14] ,\bus_data_int_reg_n_0_[13] ,\bus_data_int_reg_n_0_[12] ,\bus_data_int_reg_n_0_[11] ,\bus_data_int_reg_n_0_[10] ,\bus_data_int_reg_n_0_[9] ,\bus_data_int_reg_n_0_[8] ,\bus_data_int_reg_n_0_[7] ,\bus_data_int_reg_n_0_[6] ,\bus_data_int_reg_n_0_[5] ,\bus_data_int_reg_n_0_[4] ,\bus_data_int_reg_n_0_[3] ,\bus_data_int_reg_n_0_[2] ,p_0_in,\bus_data_int_reg_n_0_[0] }), - .\rd_en_reg[6]_0 (PROBE_OUT_ALL_INST_n_42), + .\rd_en_reg[6]_0 (PROBE_OUT_ALL_INST_n_41), .rd_probe_out_width(rd_probe_out_width), .s_daddr_o(bus_addr), .s_den_o(bus_den), @@ -6478,22 +6452,22 @@ module vio_manual_ctrl_vio_v3_0_20_vio (.\G_PROBE_OUT[0].wr_probe_out_reg[0]_0 (DECODER_INST_n_7), .\G_PROBE_OUT[0].wr_probe_out_reg[0]_1 (DECODER_INST_n_5), .\G_PROBE_OUT[0].wr_probe_out_reg[0]_2 (DECODER_INST_n_6), - .\Probe_out_reg_int_reg[10]_0 (PROBE_OUT_ALL_INST_n_55), - .\Probe_out_reg_int_reg[11]_0 (PROBE_OUT_ALL_INST_n_54), - .\Probe_out_reg_int_reg[12]_0 (PROBE_OUT_ALL_INST_n_53), - .\Probe_out_reg_int_reg[13]_0 (PROBE_OUT_ALL_INST_n_52), - .\Probe_out_reg_int_reg[14]_0 (PROBE_OUT_ALL_INST_n_51), - .\Probe_out_reg_int_reg[15]_0 (PROBE_OUT_ALL_INST_n_50), - .\Probe_out_reg_int_reg[3]_0 ({PROBE_OUT_ALL_INST_n_46,PROBE_OUT_ALL_INST_n_47,PROBE_OUT_ALL_INST_n_48,PROBE_OUT_ALL_INST_n_49}), - .\Probe_out_reg_int_reg[4]_0 (PROBE_OUT_ALL_INST_n_61), - .\Probe_out_reg_int_reg[5]_0 (PROBE_OUT_ALL_INST_n_60), - .\Probe_out_reg_int_reg[6]_0 (PROBE_OUT_ALL_INST_n_59), - .\Probe_out_reg_int_reg[7]_0 (PROBE_OUT_ALL_INST_n_58), - .\Probe_out_reg_int_reg[8]_0 (PROBE_OUT_ALL_INST_n_57), - .\Probe_out_reg_int_reg[9]_0 (PROBE_OUT_ALL_INST_n_56), + .\Probe_out_reg_int_reg[10]_0 (PROBE_OUT_ALL_INST_n_54), + .\Probe_out_reg_int_reg[11]_0 (PROBE_OUT_ALL_INST_n_53), + .\Probe_out_reg_int_reg[12]_0 (PROBE_OUT_ALL_INST_n_52), + .\Probe_out_reg_int_reg[13]_0 (PROBE_OUT_ALL_INST_n_51), + .\Probe_out_reg_int_reg[14]_0 (PROBE_OUT_ALL_INST_n_50), + .\Probe_out_reg_int_reg[15]_0 (PROBE_OUT_ALL_INST_n_49), + .\Probe_out_reg_int_reg[3]_0 ({PROBE_OUT_ALL_INST_n_45,PROBE_OUT_ALL_INST_n_46,PROBE_OUT_ALL_INST_n_47,PROBE_OUT_ALL_INST_n_48}), + .\Probe_out_reg_int_reg[4]_0 (PROBE_OUT_ALL_INST_n_60), + .\Probe_out_reg_int_reg[5]_0 (PROBE_OUT_ALL_INST_n_59), + .\Probe_out_reg_int_reg[6]_0 (PROBE_OUT_ALL_INST_n_58), + .\Probe_out_reg_int_reg[7]_0 (PROBE_OUT_ALL_INST_n_57), + .\Probe_out_reg_int_reg[8]_0 (PROBE_OUT_ALL_INST_n_56), + .\Probe_out_reg_int_reg[9]_0 (PROBE_OUT_ALL_INST_n_55), .Q({\bus_data_int_reg_n_0_[15] ,\bus_data_int_reg_n_0_[14] ,\bus_data_int_reg_n_0_[13] ,\bus_data_int_reg_n_0_[12] ,\bus_data_int_reg_n_0_[11] ,\bus_data_int_reg_n_0_[10] ,\bus_data_int_reg_n_0_[9] ,\bus_data_int_reg_n_0_[8] ,\bus_data_int_reg_n_0_[7] ,\bus_data_int_reg_n_0_[6] ,\bus_data_int_reg_n_0_[5] ,\bus_data_int_reg_n_0_[4] ,\bus_data_int_reg_n_0_[3] ,\bus_data_int_reg_n_0_[2] ,p_0_in,\bus_data_int_reg_n_0_[0] }), .SR(clear), - .\addr_count[1]_i_5 (PROBE_OUT_ALL_INST_n_42), + .\addr_count[1]_i_5 (PROBE_OUT_ALL_INST_n_41), .\addr_p1_reg[2]_0 (xsdb_addr_2_0_p1), .clk(clk), .in0(committ), diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl index 8626d906..bfccd60b 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:34:28 2023 +-- Date : Tue Mar 21 22:54:43 2023 -- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl +-- D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl -- Design : vio_manual_ctrl -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -917,10 +917,10 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity vio_manual_ctrl_vio_v3_0_20_probe_out_one is port ( - probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); - D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + D : out STD_LOGIC_VECTOR ( 1 downto 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); wr_probe_out : in STD_LOGIC_VECTOR ( 0 to 0 ); \out\ : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); @@ -931,23 +931,17 @@ entity vio_manual_ctrl_vio_v3_0_20_probe_out_one is end vio_manual_ctrl_vio_v3_0_20_probe_out_one; architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_probe_out_one is - signal \^d\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^d\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \data_int[0]_i_1_n_0\ : STD_LOGIC; signal \data_int[1]_i_1_n_0\ : STD_LOGIC; - signal \data_int[2]_i_1_n_0\ : STD_LOGIC; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of \Probe_out_reg[0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \Probe_out_reg[0]\ : label is "yes"; attribute DONT_TOUCH of \Probe_out_reg[1]\ : label is std.standard.true; attribute KEEP of \Probe_out_reg[1]\ : label is "yes"; - attribute DONT_TOUCH of \Probe_out_reg[2]\ : label is std.standard.true; - attribute KEEP of \Probe_out_reg[2]\ : label is "yes"; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \data_int[1]_i_1\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \data_int[2]_i_1\ : label is "soft_lutpair14"; begin - D(2 downto 0) <= \^d\(2 downto 0); + D(1 downto 0) <= \^d\(1 downto 0); \Probe_out_reg[0]\: unisim.vcomponents.FDRE port map ( C => clk, @@ -956,21 +950,13 @@ begin Q => probe_out0(0), R => SR(0) ); -\Probe_out_reg[1]\: unisim.vcomponents.FDRE +\Probe_out_reg[1]\: unisim.vcomponents.FDSE port map ( C => clk, CE => E(0), D => \^d\(1), Q => probe_out0(1), - R => SR(0) - ); -\Probe_out_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => clk, - CE => E(0), - D => \^d\(2), - Q => probe_out0(2), - R => SR(0) + S => SR(0) ); \data_int[0]_i_1\: unisim.vcomponents.LUT3 generic map( @@ -992,16 +978,6 @@ begin I2 => \^d\(1), O => \data_int[1]_i_1_n_0\ ); -\data_int[2]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => Q(2), - I1 => wr_probe_out(0), - I2 => \^d\(2), - O => \data_int[2]_i_1_n_0\ - ); \data_int_reg[0]\: unisim.vcomponents.FDRE port map ( C => \out\, @@ -1010,21 +986,13 @@ begin Q => \^d\(0), R => SR(0) ); -\data_int_reg[1]\: unisim.vcomponents.FDRE +\data_int_reg[1]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => '1', D => \data_int[1]_i_1_n_0\, Q => \^d\(1), - R => SR(0) - ); -\data_int_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => \out\, - CE => '1', - D => \data_int[2]_i_1_n_0\, - Q => \^d\(2), - R => SR(0) + S => SR(0) ); end STRUCTURE; library IEEE; @@ -1132,22 +1100,22 @@ architecture STRUCTURE of \vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameteri signal \mem_probe_out[0]\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal rd_probe_out : STD_LOGIC_VECTOR ( 2 to 2 ); attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \Bus_Data_out_int[0]_i_1\ : label is "soft_lutpair22"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[10]_i_1\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[11]_i_1\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[12]_i_1\ : label is "soft_lutpair16"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[13]_i_1\ : label is "soft_lutpair16"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[14]_i_1\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[15]_i_1\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[1]_i_1\ : label is "soft_lutpair22"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[2]_i_1\ : label is "soft_lutpair21"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[3]_i_1\ : label is "soft_lutpair21"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[4]_i_1\ : label is "soft_lutpair20"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[5]_i_1\ : label is "soft_lutpair20"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[6]_i_1\ : label is "soft_lutpair19"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[7]_i_1\ : label is "soft_lutpair19"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[8]_i_1\ : label is "soft_lutpair18"; - attribute SOFT_HLUTNM of \Bus_Data_out_int[9]_i_1\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[0]_i_1\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[10]_i_1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[11]_i_1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[12]_i_1\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[13]_i_1\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[14]_i_1\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[15]_i_1\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[1]_i_1\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[2]_i_1\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[3]_i_1\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[4]_i_1\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[5]_i_1\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[6]_i_1\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[7]_i_1\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[8]_i_1\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \Bus_Data_out_int[9]_i_1\ : label is "soft_lutpair17"; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of \Probe_out_reg[0]\ : label is std.standard.true; attribute KEEP : string; @@ -2139,8 +2107,8 @@ architecture STRUCTURE of \vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameteri attribute DONT_TOUCH of \Probe_out_reg[1]\ : label is std.standard.true; attribute KEEP of \Probe_out_reg[1]\ : label is "yes"; attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \data_int[0]_i_1\ : label is "soft_lutpair23"; - attribute SOFT_HLUTNM of \data_int[1]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \data_int[0]_i_1\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \data_int[1]_i_1\ : label is "soft_lutpair22"; begin D(1 downto 0) <= \^d\(1 downto 0); \Probe_out_reg[0]\: unisim.vcomponents.FDSE @@ -2316,10 +2284,10 @@ architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_probe_width is signal \addr_count[1]_i_1_n_0\ : STD_LOGIC; signal probe_width_mem : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \addr_count[0]_i_1\ : label is "soft_lutpair31"; - attribute SOFT_HLUTNM of \addr_count[1]_i_1\ : label is "soft_lutpair31"; - attribute SOFT_HLUTNM of \probe_width_int[1]_i_1\ : label is "soft_lutpair32"; - attribute SOFT_HLUTNM of \probe_width_int[8]_i_1\ : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \addr_count[0]_i_1\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \addr_count[1]_i_1\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \probe_width_int[1]_i_1\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \probe_width_int[8]_i_1\ : label is "soft_lutpair31"; begin \addr_count[0]_i_1\: unisim.vcomponents.LUT5 generic map( @@ -2362,21 +2330,21 @@ begin R => '0' ); \probe_width_int[0]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => addr_count(0), - I1 => addr_count(1), - O => probe_width_mem(0) - ); -\probe_width_int[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => addr_count(1), I1 => addr_count(0), + O => probe_width_mem(0) + ); +\probe_width_int[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => addr_count(0), + I1 => addr_count(1), O => probe_width_mem(1) ); \probe_width_int[8]_i_1\: unisim.vcomponents.LUT2 @@ -5411,7 +5379,7 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity vio_manual_ctrl_vio_v3_0_20_probe_out_all is port ( - probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); @@ -5455,9 +5423,8 @@ architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_probe_out_all is attribute async_reg of Committ_1 : signal is "true"; signal Committ_2 : STD_LOGIC; attribute async_reg of Committ_2 : signal is "true"; + signal \G_PROBE_OUT[0].PROBE_OUT0_INST_n_2\ : STD_LOGIC; signal \G_PROBE_OUT[0].PROBE_OUT0_INST_n_3\ : STD_LOGIC; - signal \G_PROBE_OUT[0].PROBE_OUT0_INST_n_4\ : STD_LOGIC; - signal \G_PROBE_OUT[0].PROBE_OUT0_INST_n_5\ : STD_LOGIC; signal \G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0\ : STD_LOGIC; signal \G_PROBE_OUT[0].wr_probe_out[0]_i_2_n_0\ : STD_LOGIC; signal \G_PROBE_OUT[0].wr_probe_out[0]_i_6_n_0\ : STD_LOGIC; @@ -5500,20 +5467,20 @@ architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_probe_out_all is attribute ASYNC_REG_boolean of Committ_2_reg : label is std.standard.true; attribute KEEP of Committ_2_reg : label is "yes"; attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \Probe_out_reg_int[0]_i_1\ : label is "soft_lutpair24"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[10]_i_1\ : label is "soft_lutpair28"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[11]_i_1\ : label is "soft_lutpair27"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[12]_i_1\ : label is "soft_lutpair25"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[13]_i_1\ : label is "soft_lutpair26"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[14]_i_1\ : label is "soft_lutpair26"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[15]_i_1\ : label is "soft_lutpair25"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[1]_i_1\ : label is "soft_lutpair24"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[4]_i_1\ : label is "soft_lutpair30"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[5]_i_1\ : label is "soft_lutpair30"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[6]_i_1\ : label is "soft_lutpair29"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[7]_i_1\ : label is "soft_lutpair29"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[8]_i_1\ : label is "soft_lutpair28"; - attribute SOFT_HLUTNM of \Probe_out_reg_int[9]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[0]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[10]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[11]_i_1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[12]_i_1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[13]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[14]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[15]_i_1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[1]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[4]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[5]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[6]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[7]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[8]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \Probe_out_reg_int[9]_i_1\ : label is "soft_lutpair26"; begin \addr_count[1]_i_5\ <= \^addr_count[1]_i_5\; \addr_p1_reg[2]_0\(2 downto 0) <= \^addr_p1_reg[2]_0\(2 downto 0); @@ -5535,15 +5502,14 @@ Committ_2_reg: unisim.vcomponents.FDRE ); \G_PROBE_OUT[0].PROBE_OUT0_INST\: entity work.vio_manual_ctrl_vio_v3_0_20_probe_out_one port map ( - D(2) => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_3\, - D(1) => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_4\, - D(0) => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_5\, + D(1) => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_2\, + D(0) => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_3\, E(0) => Committ_2, - Q(2 downto 0) => Q(2 downto 0), + Q(1 downto 0) => Q(1 downto 0), SR(0) => SR(0), clk => clk, \out\ => \out\, - probe_out0(2 downto 0) => probe_out0(2 downto 0), + probe_out0(1 downto 0) => probe_out0(1 downto 0), wr_probe_out(0) => wr_probe_out(0) ); \G_PROBE_OUT[0].wr_probe_out[0]_i_1\: unisim.vcomponents.LUT4 @@ -5767,7 +5733,7 @@ Committ_2_reg: unisim.vcomponents.FDRE I2 => \^addr_p1_reg[2]_0\(1), I3 => \G_PROBE_OUT[1].PROBE_OUT0_INST_n_1\, I4 => \^addr_p1_reg[2]_0\(0), - I5 => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_5\, + I5 => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_3\, O => \Probe_out_reg_int[0]_i_2_n_0\ ); \Probe_out_reg_int[10]_i_1\: unisim.vcomponents.LUT3 @@ -5848,21 +5814,20 @@ Committ_2_reg: unisim.vcomponents.FDRE I0 => \G_PROBE_OUT[3].PROBE_OUT0_INST_n_2\, I1 => Bus_Data_out_int(1), I2 => \^addr_p1_reg[2]_0\(1), - I3 => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_4\, + I3 => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_2\, I4 => \^addr_p1_reg[2]_0\(0), O => \Probe_out_reg_int[1]_i_2_n_0\ ); -\Probe_out_reg_int[2]_i_1\: unisim.vcomponents.LUT6 +\Probe_out_reg_int[2]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"88888888B8BBB888" + INIT => X"88B88888" ) port map ( I0 => \G_PROBE_OUT[4].PROBE_OUT0_INST_n_5\, I1 => \^addr_p1_reg[2]_0\(2), - I2 => Bus_Data_out_int(2), - I3 => \^addr_p1_reg[2]_0\(1), - I4 => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_3\, - I5 => \^addr_p1_reg[2]_0\(0), + I2 => \^addr_p1_reg[2]_0\(1), + I3 => \^addr_p1_reg[2]_0\(0), + I4 => Bus_Data_out_int(2), O => probe_out_mem(2) ); \Probe_out_reg_int[3]_i_1\: unisim.vcomponents.LUT5 @@ -6355,7 +6320,7 @@ entity vio_manual_ctrl_vio_v3_0_20_vio is probe_in255 : in STD_LOGIC_VECTOR ( 0 to 0 ); sl_iport0 : in STD_LOGIC_VECTOR ( 36 downto 0 ); sl_oport0 : out STD_LOGIC_VECTOR ( 16 downto 0 ); - probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); @@ -7165,9 +7130,9 @@ entity vio_manual_ctrl_vio_v3_0_20_vio is attribute C_PROBE_IN9_WIDTH : integer; attribute C_PROBE_IN9_WIDTH of vio_manual_ctrl_vio_v3_0_20_vio : entity is 1; attribute C_PROBE_OUT0_INIT_VAL : string; - attribute C_PROBE_OUT0_INIT_VAL of vio_manual_ctrl_vio_v3_0_20_vio : entity is "3'b000"; + attribute C_PROBE_OUT0_INIT_VAL of vio_manual_ctrl_vio_v3_0_20_vio : entity is "2'b10"; attribute C_PROBE_OUT0_WIDTH : integer; - attribute C_PROBE_OUT0_WIDTH of vio_manual_ctrl_vio_v3_0_20_vio : entity is 3; + attribute C_PROBE_OUT0_WIDTH of vio_manual_ctrl_vio_v3_0_20_vio : entity is 2; attribute C_PROBE_OUT100_INIT_VAL : string; attribute C_PROBE_OUT100_INIT_VAL of vio_manual_ctrl_vio_v3_0_20_vio : entity is "1'b0"; attribute C_PROBE_OUT100_WIDTH : integer; @@ -8199,1043 +8164,1043 @@ entity vio_manual_ctrl_vio_v3_0_20_vio is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of vio_manual_ctrl_vio_v3_0_20_vio : entity is "yes"; attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT0 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT0 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000000001"; attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT1 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT1 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000000010"; attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT10 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT10 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101110"; attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT100 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT100 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001000"; attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT101 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT101 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001001"; attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT102 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT102 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001010"; attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT103 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT103 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001011"; attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT104 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT104 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001100"; attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT105 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT105 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001101"; attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT106 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT106 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001110"; attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT107 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT107 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001111"; attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT108 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT108 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010000"; attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT109 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT109 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010001"; attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT11 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT11 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101111"; attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT110 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT110 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010010"; attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT111 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT111 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010011"; attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT112 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT112 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010100"; attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT113 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT113 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010101"; attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT114 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT114 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010110"; attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT115 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT115 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010111"; attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT116 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT116 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011000"; attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT117 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT117 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011001"; attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT118 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT118 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011010"; attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT119 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT119 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011011"; attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT12 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT12 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110000"; attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT120 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT120 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011100"; attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT121 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT121 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011101"; attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT122 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT122 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011110"; attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT123 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT123 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011111"; attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT124 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT124 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100000"; attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT125 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT125 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100001"; attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT126 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT126 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100010"; attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT127 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT127 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100011"; attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT128 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT128 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100100"; attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT129 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT129 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100101"; attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT13 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT13 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110001"; attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT130 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT130 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100110"; attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT131 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT131 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100111"; attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT132 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT132 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101000"; attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT133 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT133 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101001"; attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT134 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT134 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101010"; attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT135 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT135 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101011"; attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT136 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT136 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101100"; attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT137 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT137 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101101"; attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT138 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT138 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101110"; attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT139 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT139 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101111"; attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT14 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT14 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110010"; attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT140 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT140 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110000"; attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT141 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT141 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110001"; attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT142 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT142 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110010"; attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT143 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT143 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110011"; attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT144 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT144 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110100"; attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT145 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT145 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110101"; attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT146 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT146 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110110"; attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT147 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT147 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110111"; attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT148 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT148 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111000"; attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT149 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT149 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111001"; attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT15 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT15 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110011"; attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT150 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT150 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111010"; attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT151 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT151 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111011"; attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT152 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT152 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111100"; attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT153 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT153 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111101"; attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT154 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT154 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111110"; attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT155 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT155 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111111"; attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT156 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT156 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000000"; attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT157 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT157 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000001"; attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT158 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT158 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000010"; attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT159 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT159 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000011"; attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT16 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT16 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110100"; attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT160 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT160 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000100"; attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT161 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT161 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000101"; attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT162 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT162 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000110"; attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT163 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT163 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000111"; attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT164 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT164 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001000"; attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT165 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT165 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001001"; attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT166 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT166 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001010"; attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT167 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT167 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001011"; attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT168 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT168 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001100"; attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT169 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT169 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001101"; attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT17 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT17 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110101"; attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT170 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT170 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001110"; attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT171 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT171 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001111"; attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT172 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT172 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010000"; attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT173 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT173 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010001"; attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT174 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT174 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010010"; attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT175 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT175 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010011"; attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT176 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT176 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010100"; attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT177 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT177 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010101"; attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT178 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT178 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010110"; attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT179 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT179 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010111"; attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT18 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT18 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110110"; attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT180 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT180 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011000"; attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT181 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT181 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011001"; attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT182 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT182 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011010"; attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT183 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT183 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011011"; attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT184 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT184 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011100"; attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT185 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT185 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011101"; attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT186 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT186 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011110"; attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT187 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT187 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011111"; attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT188 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT188 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100000"; attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT189 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT189 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100001"; attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT19 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT19 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110111"; attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT190 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT190 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100010"; attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT191 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT191 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100011"; attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT192 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT192 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100100"; attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT193 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT193 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100101"; attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT194 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT194 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100110"; attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT195 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT195 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100111"; attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT196 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT196 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101000"; attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT197 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT197 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101001"; attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT198 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT198 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101010"; attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT199 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT199 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101011"; attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT2 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT2 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000100010"; attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT20 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT20 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111000"; attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT200 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT200 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101100"; attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT201 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT201 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101101"; attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT202 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT202 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101110"; attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT203 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT203 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101111"; attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT204 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT204 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110000"; attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT205 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT205 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110001"; attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT206 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT206 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110010"; attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT207 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT207 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110011"; attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT208 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT208 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110100"; attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT209 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT209 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110101"; attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT21 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT21 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111001"; attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT210 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT210 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110110"; attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT211 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT211 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110111"; attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT212 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT212 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111000"; attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT213 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT213 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111001"; attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT214 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT214 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111010"; attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT215 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT215 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111011"; attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT216 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT216 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111100"; attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT217 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT217 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111101"; attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT218 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT218 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111110"; attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT219 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT219 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111111"; attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT22 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT22 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111010"; attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT220 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT220 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000000"; attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT221 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT221 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000001"; attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT222 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT222 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000010"; attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT223 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT223 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000011"; attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT224 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT224 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000100"; attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT225 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT225 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000101"; attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT226 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT226 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000110"; attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT227 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT227 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000111"; attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT228 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT228 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001000"; attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT229 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT229 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001001"; attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT23 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT23 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111011"; attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT230 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT230 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001010"; attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT231 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT231 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001011"; attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT232 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT232 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001100"; attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT233 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT233 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001101"; attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT234 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT234 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001110"; attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT235 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT235 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001111"; attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT236 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT236 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010000"; attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT237 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT237 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010001"; attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT238 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT238 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010010"; attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT239 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT239 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010011"; attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT24 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT24 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111100"; attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT240 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT240 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010100"; attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT241 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT241 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010101"; attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT242 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT242 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010110"; attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT243 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT243 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010111"; attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT244 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT244 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011000"; attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT245 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT245 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011001"; attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT246 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT246 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011010"; attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT247 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT247 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011011"; attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT248 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT248 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011100"; attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT249 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT249 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011101"; attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT25 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT25 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111101"; attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT250 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT250 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011110"; attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT251 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT251 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011111"; attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT252 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT252 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100000"; attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT253 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT253 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100001"; attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT254 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT254 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100010"; attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT255 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT255 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100011"; attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT26 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT26 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111110"; attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT27 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT27 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111111"; attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT28 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT28 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000000"; attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT29 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT29 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000001"; attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT3 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT3 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000100100"; attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT30 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT30 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000010"; attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT31 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT31 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000011"; attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT32 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT32 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000100"; attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT33 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT33 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000101"; attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT34 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT34 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000110"; attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT35 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT35 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000111"; attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT36 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT36 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001000"; attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT37 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT37 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001001"; attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT38 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT38 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001010"; attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT39 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT39 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001011"; attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT4 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT4 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101000"; attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT40 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT40 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001100"; attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT41 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT41 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001101"; attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT42 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT42 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001110"; attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT43 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT43 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001111"; attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT44 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT44 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010000"; attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT45 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT45 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010001"; attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT46 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT46 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010010"; attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT47 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT47 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010011"; attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT48 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT48 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010100"; attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT49 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT49 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010101"; attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT5 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT5 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101001"; attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT50 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT50 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010110"; attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT51 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT51 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010111"; attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT52 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT52 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011000"; attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT53 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT53 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011001"; attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT54 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT54 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011010"; attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT55 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT55 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011011"; attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT56 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT56 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011100"; attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT57 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT57 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011101"; attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT58 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT58 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011110"; attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT59 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT59 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011111"; attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT6 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT6 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101010"; attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT60 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT60 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100000"; attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT61 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT61 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100001"; attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT62 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT62 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100010"; attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT63 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT63 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100011"; attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT64 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT64 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100100"; attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT65 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT65 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100101"; attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT66 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT66 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100110"; attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT67 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT67 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100111"; attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT68 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT68 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101000"; attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT69 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT69 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101001"; attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT7 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT7 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101011"; attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT70 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT70 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101010"; attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT71 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT71 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101011"; attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT72 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT72 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101100"; attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT73 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT73 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101101"; attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT74 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT74 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101110"; attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT75 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT75 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101111"; attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT76 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT76 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110000"; attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT77 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT77 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110001"; attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT78 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT78 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110010"; attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT79 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT79 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110011"; attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT8 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT8 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101100"; attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT80 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT80 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110100"; attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT81 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT81 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110101"; attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT82 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT82 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110110"; attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT83 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT83 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110111"; attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT84 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT84 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111000"; attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT85 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT85 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111001"; attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT86 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT86 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111010"; attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT87 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT87 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111011"; attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT88 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT88 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111100"; attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT89 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT89 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111101"; attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT9 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT9 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101101"; attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT90 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT90 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111110"; attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT91 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT91 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111111"; attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT92 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT92 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000000"; attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT93 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT93 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000001"; attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT94 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT94 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000010"; attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT95 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT95 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000011"; attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT96 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT96 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000100"; attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT97 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT97 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000101"; attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT98 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT98 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000110"; attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT99 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT99 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000111"; attribute LC_LOW_BIT_POS_PROBE_OUT0 : string; attribute LC_LOW_BIT_POS_PROBE_OUT0 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000000000"; attribute LC_LOW_BIT_POS_PROBE_OUT1 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT1 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT1 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000000010"; attribute LC_LOW_BIT_POS_PROBE_OUT10 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT10 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT10 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101110"; attribute LC_LOW_BIT_POS_PROBE_OUT100 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT100 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT100 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001000"; attribute LC_LOW_BIT_POS_PROBE_OUT101 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT101 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT101 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001001"; attribute LC_LOW_BIT_POS_PROBE_OUT102 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT102 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT102 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001010"; attribute LC_LOW_BIT_POS_PROBE_OUT103 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT103 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT103 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001011"; attribute LC_LOW_BIT_POS_PROBE_OUT104 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT104 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT104 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001100"; attribute LC_LOW_BIT_POS_PROBE_OUT105 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT105 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT105 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001101"; attribute LC_LOW_BIT_POS_PROBE_OUT106 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT106 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT106 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001110"; attribute LC_LOW_BIT_POS_PROBE_OUT107 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT107 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT107 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001111"; attribute LC_LOW_BIT_POS_PROBE_OUT108 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT108 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT108 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010000"; attribute LC_LOW_BIT_POS_PROBE_OUT109 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT109 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT109 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010001"; attribute LC_LOW_BIT_POS_PROBE_OUT11 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT11 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT11 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101111"; attribute LC_LOW_BIT_POS_PROBE_OUT110 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT110 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT110 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010010"; attribute LC_LOW_BIT_POS_PROBE_OUT111 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT111 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT111 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010011"; attribute LC_LOW_BIT_POS_PROBE_OUT112 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT112 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT112 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010100"; attribute LC_LOW_BIT_POS_PROBE_OUT113 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT113 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT113 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010101"; attribute LC_LOW_BIT_POS_PROBE_OUT114 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT114 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT114 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010110"; attribute LC_LOW_BIT_POS_PROBE_OUT115 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT115 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT115 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010010111"; attribute LC_LOW_BIT_POS_PROBE_OUT116 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT116 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT116 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011000"; attribute LC_LOW_BIT_POS_PROBE_OUT117 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT117 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT117 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011001"; attribute LC_LOW_BIT_POS_PROBE_OUT118 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT118 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT118 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011010"; attribute LC_LOW_BIT_POS_PROBE_OUT119 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT119 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT119 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011011"; attribute LC_LOW_BIT_POS_PROBE_OUT12 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT12 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT12 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110000"; attribute LC_LOW_BIT_POS_PROBE_OUT120 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT120 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT120 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011100"; attribute LC_LOW_BIT_POS_PROBE_OUT121 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT121 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT121 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011101"; attribute LC_LOW_BIT_POS_PROBE_OUT122 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT122 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT122 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011110"; attribute LC_LOW_BIT_POS_PROBE_OUT123 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT123 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT123 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010011111"; attribute LC_LOW_BIT_POS_PROBE_OUT124 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT124 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT124 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100000"; attribute LC_LOW_BIT_POS_PROBE_OUT125 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT125 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT125 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100001"; attribute LC_LOW_BIT_POS_PROBE_OUT126 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT126 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT126 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100010"; attribute LC_LOW_BIT_POS_PROBE_OUT127 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT127 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT127 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100011"; attribute LC_LOW_BIT_POS_PROBE_OUT128 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT128 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100101"; + attribute LC_LOW_BIT_POS_PROBE_OUT128 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100100"; attribute LC_LOW_BIT_POS_PROBE_OUT129 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT129 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT129 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100101"; attribute LC_LOW_BIT_POS_PROBE_OUT13 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT13 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT13 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110001"; attribute LC_LOW_BIT_POS_PROBE_OUT130 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT130 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100111"; + attribute LC_LOW_BIT_POS_PROBE_OUT130 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100110"; attribute LC_LOW_BIT_POS_PROBE_OUT131 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT131 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101000"; + attribute LC_LOW_BIT_POS_PROBE_OUT131 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010100111"; attribute LC_LOW_BIT_POS_PROBE_OUT132 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT132 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101001"; + attribute LC_LOW_BIT_POS_PROBE_OUT132 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101000"; attribute LC_LOW_BIT_POS_PROBE_OUT133 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT133 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT133 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101001"; attribute LC_LOW_BIT_POS_PROBE_OUT134 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT134 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT134 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101010"; attribute LC_LOW_BIT_POS_PROBE_OUT135 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT135 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT135 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101011"; attribute LC_LOW_BIT_POS_PROBE_OUT136 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT136 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT136 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101100"; attribute LC_LOW_BIT_POS_PROBE_OUT137 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT137 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT137 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101101"; attribute LC_LOW_BIT_POS_PROBE_OUT138 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT138 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT138 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101110"; attribute LC_LOW_BIT_POS_PROBE_OUT139 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT139 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT139 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010101111"; attribute LC_LOW_BIT_POS_PROBE_OUT14 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT14 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT14 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110010"; attribute LC_LOW_BIT_POS_PROBE_OUT140 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT140 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT140 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110000"; attribute LC_LOW_BIT_POS_PROBE_OUT141 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT141 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT141 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110001"; attribute LC_LOW_BIT_POS_PROBE_OUT142 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT142 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT142 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110010"; attribute LC_LOW_BIT_POS_PROBE_OUT143 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT143 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT143 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110011"; attribute LC_LOW_BIT_POS_PROBE_OUT144 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT144 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT144 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110100"; attribute LC_LOW_BIT_POS_PROBE_OUT145 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT145 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT145 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110101"; attribute LC_LOW_BIT_POS_PROBE_OUT146 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT146 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT146 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110110"; attribute LC_LOW_BIT_POS_PROBE_OUT147 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT147 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT147 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010110111"; attribute LC_LOW_BIT_POS_PROBE_OUT148 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT148 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT148 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111000"; attribute LC_LOW_BIT_POS_PROBE_OUT149 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT149 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT149 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111001"; attribute LC_LOW_BIT_POS_PROBE_OUT15 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT15 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT15 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110011"; attribute LC_LOW_BIT_POS_PROBE_OUT150 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT150 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT150 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111010"; attribute LC_LOW_BIT_POS_PROBE_OUT151 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT151 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT151 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111011"; attribute LC_LOW_BIT_POS_PROBE_OUT152 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT152 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT152 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111100"; attribute LC_LOW_BIT_POS_PROBE_OUT153 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT153 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT153 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111101"; attribute LC_LOW_BIT_POS_PROBE_OUT154 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT154 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT154 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111110"; attribute LC_LOW_BIT_POS_PROBE_OUT155 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT155 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT155 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010111111"; attribute LC_LOW_BIT_POS_PROBE_OUT156 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT156 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT156 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000000"; attribute LC_LOW_BIT_POS_PROBE_OUT157 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT157 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT157 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000001"; attribute LC_LOW_BIT_POS_PROBE_OUT158 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT158 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT158 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000010"; attribute LC_LOW_BIT_POS_PROBE_OUT159 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT159 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT159 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000011"; attribute LC_LOW_BIT_POS_PROBE_OUT16 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT16 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT16 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110100"; attribute LC_LOW_BIT_POS_PROBE_OUT160 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT160 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT160 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000100"; attribute LC_LOW_BIT_POS_PROBE_OUT161 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT161 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT161 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000101"; attribute LC_LOW_BIT_POS_PROBE_OUT162 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT162 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT162 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000110"; attribute LC_LOW_BIT_POS_PROBE_OUT163 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT163 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT163 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011000111"; attribute LC_LOW_BIT_POS_PROBE_OUT164 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT164 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT164 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001000"; attribute LC_LOW_BIT_POS_PROBE_OUT165 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT165 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT165 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001001"; attribute LC_LOW_BIT_POS_PROBE_OUT166 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT166 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT166 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001010"; attribute LC_LOW_BIT_POS_PROBE_OUT167 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT167 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT167 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001011"; attribute LC_LOW_BIT_POS_PROBE_OUT168 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT168 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT168 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001100"; attribute LC_LOW_BIT_POS_PROBE_OUT169 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT169 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT169 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001101"; attribute LC_LOW_BIT_POS_PROBE_OUT17 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT17 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT17 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110101"; attribute LC_LOW_BIT_POS_PROBE_OUT170 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT170 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT170 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001110"; attribute LC_LOW_BIT_POS_PROBE_OUT171 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT171 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT171 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011001111"; attribute LC_LOW_BIT_POS_PROBE_OUT172 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT172 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT172 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010000"; attribute LC_LOW_BIT_POS_PROBE_OUT173 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT173 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT173 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010001"; attribute LC_LOW_BIT_POS_PROBE_OUT174 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT174 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT174 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010010"; attribute LC_LOW_BIT_POS_PROBE_OUT175 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT175 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT175 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010011"; attribute LC_LOW_BIT_POS_PROBE_OUT176 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT176 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT176 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010100"; attribute LC_LOW_BIT_POS_PROBE_OUT177 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT177 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT177 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010101"; attribute LC_LOW_BIT_POS_PROBE_OUT178 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT178 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT178 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010110"; attribute LC_LOW_BIT_POS_PROBE_OUT179 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT179 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT179 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011010111"; attribute LC_LOW_BIT_POS_PROBE_OUT18 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT18 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT18 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110110"; attribute LC_LOW_BIT_POS_PROBE_OUT180 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT180 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT180 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011000"; attribute LC_LOW_BIT_POS_PROBE_OUT181 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT181 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT181 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011001"; attribute LC_LOW_BIT_POS_PROBE_OUT182 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT182 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT182 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011010"; attribute LC_LOW_BIT_POS_PROBE_OUT183 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT183 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT183 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011011"; attribute LC_LOW_BIT_POS_PROBE_OUT184 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT184 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT184 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011100"; attribute LC_LOW_BIT_POS_PROBE_OUT185 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT185 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT185 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011101"; attribute LC_LOW_BIT_POS_PROBE_OUT186 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT186 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT186 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011110"; attribute LC_LOW_BIT_POS_PROBE_OUT187 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT187 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT187 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011011111"; attribute LC_LOW_BIT_POS_PROBE_OUT188 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT188 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT188 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100000"; attribute LC_LOW_BIT_POS_PROBE_OUT189 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT189 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT189 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100001"; attribute LC_LOW_BIT_POS_PROBE_OUT19 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT19 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT19 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000110111"; attribute LC_LOW_BIT_POS_PROBE_OUT190 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT190 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT190 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100010"; attribute LC_LOW_BIT_POS_PROBE_OUT191 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT191 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT191 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100011"; attribute LC_LOW_BIT_POS_PROBE_OUT192 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT192 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100101"; + attribute LC_LOW_BIT_POS_PROBE_OUT192 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100100"; attribute LC_LOW_BIT_POS_PROBE_OUT193 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT193 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT193 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100101"; attribute LC_LOW_BIT_POS_PROBE_OUT194 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT194 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100111"; + attribute LC_LOW_BIT_POS_PROBE_OUT194 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100110"; attribute LC_LOW_BIT_POS_PROBE_OUT195 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT195 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101000"; + attribute LC_LOW_BIT_POS_PROBE_OUT195 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011100111"; attribute LC_LOW_BIT_POS_PROBE_OUT196 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT196 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101001"; + attribute LC_LOW_BIT_POS_PROBE_OUT196 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101000"; attribute LC_LOW_BIT_POS_PROBE_OUT197 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT197 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT197 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101001"; attribute LC_LOW_BIT_POS_PROBE_OUT198 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT198 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT198 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101010"; attribute LC_LOW_BIT_POS_PROBE_OUT199 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT199 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT199 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101011"; attribute LC_LOW_BIT_POS_PROBE_OUT2 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT2 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT2 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000000011"; attribute LC_LOW_BIT_POS_PROBE_OUT20 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT20 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT20 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111000"; attribute LC_LOW_BIT_POS_PROBE_OUT200 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT200 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT200 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101100"; attribute LC_LOW_BIT_POS_PROBE_OUT201 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT201 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT201 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101101"; attribute LC_LOW_BIT_POS_PROBE_OUT202 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT202 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT202 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101110"; attribute LC_LOW_BIT_POS_PROBE_OUT203 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT203 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT203 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011101111"; attribute LC_LOW_BIT_POS_PROBE_OUT204 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT204 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT204 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110000"; attribute LC_LOW_BIT_POS_PROBE_OUT205 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT205 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT205 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110001"; attribute LC_LOW_BIT_POS_PROBE_OUT206 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT206 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT206 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110010"; attribute LC_LOW_BIT_POS_PROBE_OUT207 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT207 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT207 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110011"; attribute LC_LOW_BIT_POS_PROBE_OUT208 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT208 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT208 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110100"; attribute LC_LOW_BIT_POS_PROBE_OUT209 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT209 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT209 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110101"; attribute LC_LOW_BIT_POS_PROBE_OUT21 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT21 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT21 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111001"; attribute LC_LOW_BIT_POS_PROBE_OUT210 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT210 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT210 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110110"; attribute LC_LOW_BIT_POS_PROBE_OUT211 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT211 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT211 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011110111"; attribute LC_LOW_BIT_POS_PROBE_OUT212 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT212 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT212 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111000"; attribute LC_LOW_BIT_POS_PROBE_OUT213 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT213 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT213 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111001"; attribute LC_LOW_BIT_POS_PROBE_OUT214 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT214 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT214 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111010"; attribute LC_LOW_BIT_POS_PROBE_OUT215 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT215 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT215 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111011"; attribute LC_LOW_BIT_POS_PROBE_OUT216 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT216 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT216 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111100"; attribute LC_LOW_BIT_POS_PROBE_OUT217 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT217 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT217 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111101"; attribute LC_LOW_BIT_POS_PROBE_OUT218 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT218 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT218 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111110"; attribute LC_LOW_BIT_POS_PROBE_OUT219 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT219 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT219 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000011111111"; attribute LC_LOW_BIT_POS_PROBE_OUT22 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT22 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT22 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111010"; attribute LC_LOW_BIT_POS_PROBE_OUT220 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT220 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT220 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000000"; attribute LC_LOW_BIT_POS_PROBE_OUT221 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT221 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT221 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000001"; attribute LC_LOW_BIT_POS_PROBE_OUT222 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT222 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT222 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000010"; attribute LC_LOW_BIT_POS_PROBE_OUT223 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT223 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT223 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000011"; attribute LC_LOW_BIT_POS_PROBE_OUT224 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT224 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT224 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000100"; attribute LC_LOW_BIT_POS_PROBE_OUT225 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT225 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT225 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000101"; attribute LC_LOW_BIT_POS_PROBE_OUT226 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT226 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT226 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000110"; attribute LC_LOW_BIT_POS_PROBE_OUT227 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT227 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT227 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100000111"; attribute LC_LOW_BIT_POS_PROBE_OUT228 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT228 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT228 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001000"; attribute LC_LOW_BIT_POS_PROBE_OUT229 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT229 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT229 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001001"; attribute LC_LOW_BIT_POS_PROBE_OUT23 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT23 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT23 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111011"; attribute LC_LOW_BIT_POS_PROBE_OUT230 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT230 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT230 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001010"; attribute LC_LOW_BIT_POS_PROBE_OUT231 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT231 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT231 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001011"; attribute LC_LOW_BIT_POS_PROBE_OUT232 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT232 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT232 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001100"; attribute LC_LOW_BIT_POS_PROBE_OUT233 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT233 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT233 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001101"; attribute LC_LOW_BIT_POS_PROBE_OUT234 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT234 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT234 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001110"; attribute LC_LOW_BIT_POS_PROBE_OUT235 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT235 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT235 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100001111"; attribute LC_LOW_BIT_POS_PROBE_OUT236 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT236 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT236 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010000"; attribute LC_LOW_BIT_POS_PROBE_OUT237 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT237 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT237 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010001"; attribute LC_LOW_BIT_POS_PROBE_OUT238 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT238 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT238 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010010"; attribute LC_LOW_BIT_POS_PROBE_OUT239 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT239 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT239 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010011"; attribute LC_LOW_BIT_POS_PROBE_OUT24 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT24 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT24 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111100"; attribute LC_LOW_BIT_POS_PROBE_OUT240 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT240 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT240 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010100"; attribute LC_LOW_BIT_POS_PROBE_OUT241 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT241 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT241 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010101"; attribute LC_LOW_BIT_POS_PROBE_OUT242 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT242 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT242 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010110"; attribute LC_LOW_BIT_POS_PROBE_OUT243 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT243 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT243 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100010111"; attribute LC_LOW_BIT_POS_PROBE_OUT244 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT244 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT244 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011000"; attribute LC_LOW_BIT_POS_PROBE_OUT245 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT245 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT245 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011001"; attribute LC_LOW_BIT_POS_PROBE_OUT246 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT246 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT246 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011010"; attribute LC_LOW_BIT_POS_PROBE_OUT247 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT247 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT247 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011011"; attribute LC_LOW_BIT_POS_PROBE_OUT248 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT248 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT248 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011100"; attribute LC_LOW_BIT_POS_PROBE_OUT249 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT249 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT249 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011101"; attribute LC_LOW_BIT_POS_PROBE_OUT25 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT25 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT25 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111101"; attribute LC_LOW_BIT_POS_PROBE_OUT250 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT250 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT250 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011110"; attribute LC_LOW_BIT_POS_PROBE_OUT251 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT251 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT251 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100011111"; attribute LC_LOW_BIT_POS_PROBE_OUT252 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT252 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT252 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100000"; attribute LC_LOW_BIT_POS_PROBE_OUT253 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT253 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT253 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100001"; attribute LC_LOW_BIT_POS_PROBE_OUT254 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT254 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT254 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100010"; attribute LC_LOW_BIT_POS_PROBE_OUT255 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT255 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT255 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000100100011"; attribute LC_LOW_BIT_POS_PROBE_OUT26 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT26 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT26 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111110"; attribute LC_LOW_BIT_POS_PROBE_OUT27 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT27 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT27 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000111111"; attribute LC_LOW_BIT_POS_PROBE_OUT28 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT28 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT28 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000000"; attribute LC_LOW_BIT_POS_PROBE_OUT29 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT29 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT29 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000001"; attribute LC_LOW_BIT_POS_PROBE_OUT3 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT3 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT3 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000100011"; attribute LC_LOW_BIT_POS_PROBE_OUT30 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT30 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT30 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000010"; attribute LC_LOW_BIT_POS_PROBE_OUT31 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT31 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT31 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000011"; attribute LC_LOW_BIT_POS_PROBE_OUT32 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT32 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT32 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000100"; attribute LC_LOW_BIT_POS_PROBE_OUT33 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT33 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT33 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000101"; attribute LC_LOW_BIT_POS_PROBE_OUT34 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT34 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT34 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000110"; attribute LC_LOW_BIT_POS_PROBE_OUT35 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT35 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT35 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001000111"; attribute LC_LOW_BIT_POS_PROBE_OUT36 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT36 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT36 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001000"; attribute LC_LOW_BIT_POS_PROBE_OUT37 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT37 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT37 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001001"; attribute LC_LOW_BIT_POS_PROBE_OUT38 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT38 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT38 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001010"; attribute LC_LOW_BIT_POS_PROBE_OUT39 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT39 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT39 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001011"; attribute LC_LOW_BIT_POS_PROBE_OUT4 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT4 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT4 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000100101"; attribute LC_LOW_BIT_POS_PROBE_OUT40 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT40 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT40 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001100"; attribute LC_LOW_BIT_POS_PROBE_OUT41 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT41 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT41 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001101"; attribute LC_LOW_BIT_POS_PROBE_OUT42 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT42 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT42 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001110"; attribute LC_LOW_BIT_POS_PROBE_OUT43 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT43 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT43 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001001111"; attribute LC_LOW_BIT_POS_PROBE_OUT44 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT44 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT44 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010000"; attribute LC_LOW_BIT_POS_PROBE_OUT45 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT45 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT45 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010001"; attribute LC_LOW_BIT_POS_PROBE_OUT46 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT46 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT46 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010010"; attribute LC_LOW_BIT_POS_PROBE_OUT47 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT47 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT47 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010011"; attribute LC_LOW_BIT_POS_PROBE_OUT48 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT48 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT48 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010100"; attribute LC_LOW_BIT_POS_PROBE_OUT49 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT49 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT49 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010101"; attribute LC_LOW_BIT_POS_PROBE_OUT5 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT5 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT5 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101001"; attribute LC_LOW_BIT_POS_PROBE_OUT50 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT50 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT50 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010110"; attribute LC_LOW_BIT_POS_PROBE_OUT51 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT51 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT51 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001010111"; attribute LC_LOW_BIT_POS_PROBE_OUT52 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT52 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT52 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011000"; attribute LC_LOW_BIT_POS_PROBE_OUT53 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT53 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT53 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011001"; attribute LC_LOW_BIT_POS_PROBE_OUT54 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT54 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT54 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011010"; attribute LC_LOW_BIT_POS_PROBE_OUT55 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT55 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT55 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011011"; attribute LC_LOW_BIT_POS_PROBE_OUT56 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT56 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT56 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011100"; attribute LC_LOW_BIT_POS_PROBE_OUT57 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT57 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT57 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011101"; attribute LC_LOW_BIT_POS_PROBE_OUT58 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT58 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT58 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011110"; attribute LC_LOW_BIT_POS_PROBE_OUT59 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT59 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT59 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001011111"; attribute LC_LOW_BIT_POS_PROBE_OUT6 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT6 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT6 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101010"; attribute LC_LOW_BIT_POS_PROBE_OUT60 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT60 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT60 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100000"; attribute LC_LOW_BIT_POS_PROBE_OUT61 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT61 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT61 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100001"; attribute LC_LOW_BIT_POS_PROBE_OUT62 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT62 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT62 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100010"; attribute LC_LOW_BIT_POS_PROBE_OUT63 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT63 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT63 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100011"; attribute LC_LOW_BIT_POS_PROBE_OUT64 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT64 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100101"; + attribute LC_LOW_BIT_POS_PROBE_OUT64 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100100"; attribute LC_LOW_BIT_POS_PROBE_OUT65 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT65 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT65 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100101"; attribute LC_LOW_BIT_POS_PROBE_OUT66 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT66 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100111"; + attribute LC_LOW_BIT_POS_PROBE_OUT66 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100110"; attribute LC_LOW_BIT_POS_PROBE_OUT67 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT67 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101000"; + attribute LC_LOW_BIT_POS_PROBE_OUT67 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001100111"; attribute LC_LOW_BIT_POS_PROBE_OUT68 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT68 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101001"; + attribute LC_LOW_BIT_POS_PROBE_OUT68 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101000"; attribute LC_LOW_BIT_POS_PROBE_OUT69 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT69 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT69 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101001"; attribute LC_LOW_BIT_POS_PROBE_OUT7 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT7 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT7 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101011"; attribute LC_LOW_BIT_POS_PROBE_OUT70 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT70 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT70 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101010"; attribute LC_LOW_BIT_POS_PROBE_OUT71 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT71 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT71 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101011"; attribute LC_LOW_BIT_POS_PROBE_OUT72 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT72 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT72 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101100"; attribute LC_LOW_BIT_POS_PROBE_OUT73 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT73 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT73 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101101"; attribute LC_LOW_BIT_POS_PROBE_OUT74 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT74 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT74 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101110"; attribute LC_LOW_BIT_POS_PROBE_OUT75 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT75 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT75 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001101111"; attribute LC_LOW_BIT_POS_PROBE_OUT76 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT76 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT76 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110000"; attribute LC_LOW_BIT_POS_PROBE_OUT77 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT77 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT77 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110001"; attribute LC_LOW_BIT_POS_PROBE_OUT78 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT78 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT78 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110010"; attribute LC_LOW_BIT_POS_PROBE_OUT79 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT79 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT79 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110011"; attribute LC_LOW_BIT_POS_PROBE_OUT8 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT8 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT8 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101100"; attribute LC_LOW_BIT_POS_PROBE_OUT80 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT80 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT80 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110100"; attribute LC_LOW_BIT_POS_PROBE_OUT81 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT81 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT81 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110101"; attribute LC_LOW_BIT_POS_PROBE_OUT82 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT82 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT82 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110110"; attribute LC_LOW_BIT_POS_PROBE_OUT83 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT83 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT83 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001110111"; attribute LC_LOW_BIT_POS_PROBE_OUT84 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT84 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT84 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111000"; attribute LC_LOW_BIT_POS_PROBE_OUT85 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT85 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT85 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111001"; attribute LC_LOW_BIT_POS_PROBE_OUT86 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT86 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT86 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111010"; attribute LC_LOW_BIT_POS_PROBE_OUT87 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT87 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT87 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111011"; attribute LC_LOW_BIT_POS_PROBE_OUT88 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT88 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT88 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111100"; attribute LC_LOW_BIT_POS_PROBE_OUT89 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT89 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT89 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111101"; attribute LC_LOW_BIT_POS_PROBE_OUT9 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT9 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT9 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000000101101"; attribute LC_LOW_BIT_POS_PROBE_OUT90 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT90 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT90 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111110"; attribute LC_LOW_BIT_POS_PROBE_OUT91 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT91 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT91 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000001111111"; attribute LC_LOW_BIT_POS_PROBE_OUT92 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT92 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT92 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000000"; attribute LC_LOW_BIT_POS_PROBE_OUT93 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT93 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT93 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000001"; attribute LC_LOW_BIT_POS_PROBE_OUT94 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT94 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT94 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000010"; attribute LC_LOW_BIT_POS_PROBE_OUT95 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT95 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT95 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000011"; attribute LC_LOW_BIT_POS_PROBE_OUT96 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT96 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT96 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000100"; attribute LC_LOW_BIT_POS_PROBE_OUT97 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT97 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT97 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000101"; attribute LC_LOW_BIT_POS_PROBE_OUT98 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT98 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT98 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000110"; attribute LC_LOW_BIT_POS_PROBE_OUT99 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT99 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT99 of vio_manual_ctrl_vio_v3_0_20_vio : entity is "16'b0000000010000111"; attribute LC_PROBE_IN_WIDTH_STRING : string; attribute LC_PROBE_IN_WIDTH_STRING of vio_manual_ctrl_vio_v3_0_20_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string; - attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of vio_manual_ctrl_vio_v3_0_20_vio : entity is "4096'b0000000100100100000000010010001100000001001000100000000100100001000000010010000000000001000111110000000100011110000000010001110100000001000111000000000100011011000000010001101000000001000110010000000100011000000000010001011100000001000101100000000100010101000000010001010000000001000100110000000100010010000000010001000100000001000100000000000100001111000000010000111000000001000011010000000100001100000000010000101100000001000010100000000100001001000000010000100000000001000001110000000100000110000000010000010100000001000001000000000100000011000000010000001000000001000000010000000100000000000000001111111100000000111111100000000011111101000000001111110000000000111110110000000011111010000000001111100100000000111110000000000011110111000000001111011000000000111101010000000011110100000000001111001100000000111100100000000011110001000000001111000000000000111011110000000011101110000000001110110100000000111011000000000011101011000000001110101000000000111010010000000011101000000000001110011100000000111001100000000011100101000000001110010000000000111000110000000011100010000000001110000100000000111000000000000011011111000000001101111000000000110111010000000011011100000000001101101100000000110110100000000011011001000000001101100000000000110101110000000011010110000000001101010100000000110101000000000011010011000000001101001000000000110100010000000011010000000000001100111100000000110011100000000011001101000000001100110000000000110010110000000011001010000000001100100100000000110010000000000011000111000000001100011000000000110001010000000011000100000000001100001100000000110000100000000011000001000000001100000000000000101111110000000010111110000000001011110100000000101111000000000010111011000000001011101000000000101110010000000010111000000000001011011100000000101101100000000010110101000000001011010000000000101100110000000010110010000000001011000100000000101100000000000010101111000000001010111000000000101011010000000010101100000000001010101100000000101010100000000010101001000000001010100000000000101001110000000010100110000000001010010100000000101001000000000010100011000000001010001000000000101000010000000010100000000000001001111100000000100111100000000010011101000000001001110000000000100110110000000010011010000000001001100100000000100110000000000010010111000000001001011000000000100101010000000010010100000000001001001100000000100100100000000010010001000000001001000000000000100011110000000010001110000000001000110100000000100011000000000010001011000000001000101000000000100010010000000010001000000000001000011100000000100001100000000010000101000000001000010000000000100000110000000010000010000000001000000100000000100000000000000001111111000000000111111000000000011111010000000001111100000000000111101100000000011110100000000001111001000000000111100000000000011101110000000001110110000000000111010100000000011101000000000001110011000000000111001000000000011100010000000001110000000000000110111100000000011011100000000001101101000000000110110000000000011010110000000001101010000000000110100100000000011010000000000001100111000000000110011000000000011001010000000001100100000000000110001100000000011000100000000001100001000000000110000000000000010111110000000001011110000000000101110100000000010111000000000001011011000000000101101000000000010110010000000001011000000000000101011100000000010101100000000001010101000000000101010000000000010100110000000001010010000000000101000100000000010100000000000001001111000000000100111000000000010011010000000001001100000000000100101100000000010010100000000001001001000000000100100000000000010001110000000001000110000000000100010100000000010001000000000001000011000000000100001000000000010000010000000001000000000000000011111100000000001111100000000000111101000000000011110000000000001110110000000000111010000000000011100100000000001110000000000000110111000000000011011000000000001101010000000000110100000000000011001100000000001100100000000000110001000000000011000000000000001011110000000000101110000000000010110100000000001011000000000000101011000000000010101000000000001010010000000000100101000000000010001100000000000000110000000000000010"; + attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of vio_manual_ctrl_vio_v3_0_20_vio : entity is "4096'b0000000100100011000000010010001000000001001000010000000100100000000000010001111100000001000111100000000100011101000000010001110000000001000110110000000100011010000000010001100100000001000110000000000100010111000000010001011000000001000101010000000100010100000000010001001100000001000100100000000100010001000000010001000000000001000011110000000100001110000000010000110100000001000011000000000100001011000000010000101000000001000010010000000100001000000000010000011100000001000001100000000100000101000000010000010000000001000000110000000100000010000000010000000100000001000000000000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100100000000000010001000000000000000100000000000000001"; attribute LC_PROBE_OUT_INIT_VAL_STRING : string; - attribute LC_PROBE_OUT_INIT_VAL_STRING of vio_manual_ctrl_vio_v3_0_20_vio : entity is "293'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000"; + attribute LC_PROBE_OUT_INIT_VAL_STRING of vio_manual_ctrl_vio_v3_0_20_vio : entity is "292'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000010"; attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string; - attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of vio_manual_ctrl_vio_v3_0_20_vio : entity is "4096'b0000000100100100000000010010001100000001001000100000000100100001000000010010000000000001000111110000000100011110000000010001110100000001000111000000000100011011000000010001101000000001000110010000000100011000000000010001011100000001000101100000000100010101000000010001010000000001000100110000000100010010000000010001000100000001000100000000000100001111000000010000111000000001000011010000000100001100000000010000101100000001000010100000000100001001000000010000100000000001000001110000000100000110000000010000010100000001000001000000000100000011000000010000001000000001000000010000000100000000000000001111111100000000111111100000000011111101000000001111110000000000111110110000000011111010000000001111100100000000111110000000000011110111000000001111011000000000111101010000000011110100000000001111001100000000111100100000000011110001000000001111000000000000111011110000000011101110000000001110110100000000111011000000000011101011000000001110101000000000111010010000000011101000000000001110011100000000111001100000000011100101000000001110010000000000111000110000000011100010000000001110000100000000111000000000000011011111000000001101111000000000110111010000000011011100000000001101101100000000110110100000000011011001000000001101100000000000110101110000000011010110000000001101010100000000110101000000000011010011000000001101001000000000110100010000000011010000000000001100111100000000110011100000000011001101000000001100110000000000110010110000000011001010000000001100100100000000110010000000000011000111000000001100011000000000110001010000000011000100000000001100001100000000110000100000000011000001000000001100000000000000101111110000000010111110000000001011110100000000101111000000000010111011000000001011101000000000101110010000000010111000000000001011011100000000101101100000000010110101000000001011010000000000101100110000000010110010000000001011000100000000101100000000000010101111000000001010111000000000101011010000000010101100000000001010101100000000101010100000000010101001000000001010100000000000101001110000000010100110000000001010010100000000101001000000000010100011000000001010001000000000101000010000000010100000000000001001111100000000100111100000000010011101000000001001110000000000100110110000000010011010000000001001100100000000100110000000000010010111000000001001011000000000100101010000000010010100000000001001001100000000100100100000000010010001000000001001000000000000100011110000000010001110000000001000110100000000100011000000000010001011000000001000101000000000100010010000000010001000000000001000011100000000100001100000000010000101000000001000010000000000100000110000000010000010000000001000000100000000100000000000000001111111000000000111111000000000011111010000000001111100000000000111101100000000011110100000000001111001000000000111100000000000011101110000000001110110000000000111010100000000011101000000000001110011000000000111001000000000011100010000000001110000000000000110111100000000011011100000000001101101000000000110110000000000011010110000000001101010000000000110100100000000011010000000000001100111000000000110011000000000011001010000000001100100000000000110001100000000011000100000000001100001000000000110000000000000010111110000000001011110000000000101110100000000010111000000000001011011000000000101101000000000010110010000000001011000000000000101011100000000010101100000000001010101000000000101010000000000010100110000000001010010000000000101000100000000010100000000000001001111000000000100111000000000010011010000000001001100000000000100101100000000010010100000000001001001000000000100100000000000010001110000000001000110000000000100010100000000010001000000000001000011000000000100001000000000010000010000000001000000000000000011111100000000001111100000000000111101000000000011110000000000001110110000000000111010000000000011100100000000001110000000000000110111000000000011011000000000001101010000000000110100000000000011001100000000001100100000000000110001000000000011000000000000001011110000000000101110000000000010110100000000001011000000000000101011000000000010101000000000001001100000000000100100000000000000010000000000000000110000000000000000"; + attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of vio_manual_ctrl_vio_v3_0_20_vio : entity is "4096'b0000000100100011000000010010001000000001001000010000000100100000000000010001111100000001000111100000000100011101000000010001110000000001000110110000000100011010000000010001100100000001000110000000000100010111000000010001011000000001000101010000000100010100000000010001001100000001000100100000000100010001000000010001000000000001000011110000000100001110000000010000110100000001000011000000000100001011000000010000101000000001000010010000000100001000000000010000011100000001000001100000000100000101000000010000010000000001000000110000000100000010000000010000000100000001000000000000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001001010000000000100011000000000000001100000000000000100000000000000000"; attribute LC_PROBE_OUT_WIDTH_STRING : string; - attribute LC_PROBE_OUT_WIDTH_STRING of vio_manual_ctrl_vio_v3_0_20_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000001000111110000000000000010"; + attribute LC_PROBE_OUT_WIDTH_STRING of vio_manual_ctrl_vio_v3_0_20_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000001000111110000000000000001"; attribute LC_TOTAL_PROBE_IN_WIDTH : integer; attribute LC_TOTAL_PROBE_IN_WIDTH of vio_manual_ctrl_vio_v3_0_20_vio : entity is 0; attribute LC_TOTAL_PROBE_OUT_WIDTH : integer; - attribute LC_TOTAL_PROBE_OUT_WIDTH of vio_manual_ctrl_vio_v3_0_20_vio : entity is 42; + attribute LC_TOTAL_PROBE_OUT_WIDTH of vio_manual_ctrl_vio_v3_0_20_vio : entity is 41; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of vio_manual_ctrl_vio_v3_0_20_vio : entity is "vio_v3_0_20_vio"; attribute dont_touch : string; @@ -9247,7 +9212,8 @@ architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_vio is signal DECODER_INST_n_5 : STD_LOGIC; signal DECODER_INST_n_6 : STD_LOGIC; signal DECODER_INST_n_7 : STD_LOGIC; - signal PROBE_OUT_ALL_INST_n_42 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_41 : STD_LOGIC; + signal PROBE_OUT_ALL_INST_n_45 : STD_LOGIC; signal PROBE_OUT_ALL_INST_n_46 : STD_LOGIC; signal PROBE_OUT_ALL_INST_n_47 : STD_LOGIC; signal PROBE_OUT_ALL_INST_n_48 : STD_LOGIC; @@ -9263,7 +9229,6 @@ architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_vio is signal PROBE_OUT_ALL_INST_n_58 : STD_LOGIC; signal PROBE_OUT_ALL_INST_n_59 : STD_LOGIC; signal PROBE_OUT_ALL_INST_n_60 : STD_LOGIC; - signal PROBE_OUT_ALL_INST_n_61 : STD_LOGIC; signal bus_addr : STD_LOGIC_VECTOR ( 16 downto 0 ); signal bus_clk : STD_LOGIC; attribute DONT_TOUCH_boolean : boolean; @@ -9567,27 +9532,27 @@ begin probe_out99(0) <= \\; DECODER_INST: entity work.vio_manual_ctrl_vio_v3_0_20_decoder port map ( - \Bus_data_out_reg[10]_0\ => PROBE_OUT_ALL_INST_n_55, - \Bus_data_out_reg[11]_0\ => PROBE_OUT_ALL_INST_n_54, - \Bus_data_out_reg[12]_0\ => PROBE_OUT_ALL_INST_n_53, - \Bus_data_out_reg[13]_0\ => PROBE_OUT_ALL_INST_n_52, - \Bus_data_out_reg[14]_0\ => PROBE_OUT_ALL_INST_n_51, + \Bus_data_out_reg[10]_0\ => PROBE_OUT_ALL_INST_n_54, + \Bus_data_out_reg[11]_0\ => PROBE_OUT_ALL_INST_n_53, + \Bus_data_out_reg[12]_0\ => PROBE_OUT_ALL_INST_n_52, + \Bus_data_out_reg[13]_0\ => PROBE_OUT_ALL_INST_n_51, + \Bus_data_out_reg[14]_0\ => PROBE_OUT_ALL_INST_n_50, \Bus_data_out_reg[15]_0\(15 downto 0) => bus_do(15 downto 0), - \Bus_data_out_reg[15]_1\ => PROBE_OUT_ALL_INST_n_50, + \Bus_data_out_reg[15]_1\ => PROBE_OUT_ALL_INST_n_49, \Bus_data_out_reg[3]_0\(2) => probe_width_int(8), \Bus_data_out_reg[3]_0\(1 downto 0) => probe_width_int(1 downto 0), - \Bus_data_out_reg[4]_0\ => PROBE_OUT_ALL_INST_n_61, - \Bus_data_out_reg[5]_0\ => PROBE_OUT_ALL_INST_n_60, - \Bus_data_out_reg[6]_0\ => PROBE_OUT_ALL_INST_n_59, - \Bus_data_out_reg[7]_0\ => PROBE_OUT_ALL_INST_n_58, - \Bus_data_out_reg[8]_0\ => PROBE_OUT_ALL_INST_n_57, - \Bus_data_out_reg[9]_0\ => PROBE_OUT_ALL_INST_n_56, + \Bus_data_out_reg[4]_0\ => PROBE_OUT_ALL_INST_n_60, + \Bus_data_out_reg[5]_0\ => PROBE_OUT_ALL_INST_n_59, + \Bus_data_out_reg[6]_0\ => PROBE_OUT_ALL_INST_n_58, + \Bus_data_out_reg[7]_0\ => PROBE_OUT_ALL_INST_n_57, + \Bus_data_out_reg[8]_0\ => PROBE_OUT_ALL_INST_n_56, + \Bus_data_out_reg[9]_0\ => PROBE_OUT_ALL_INST_n_55, \G_PROBE_OUT[0].wr_probe_out[0]_i_3_0\ => DECODER_INST_n_7, \G_PROBE_OUT[0].wr_probe_out[0]_i_4_0\ => DECODER_INST_n_5, - Q(3) => PROBE_OUT_ALL_INST_n_46, - Q(2) => PROBE_OUT_ALL_INST_n_47, - Q(1) => PROBE_OUT_ALL_INST_n_48, - Q(0) => PROBE_OUT_ALL_INST_n_49, + Q(3) => PROBE_OUT_ALL_INST_n_45, + Q(2) => PROBE_OUT_ALL_INST_n_46, + Q(1) => PROBE_OUT_ALL_INST_n_47, + Q(0) => PROBE_OUT_ALL_INST_n_48, SR(0) => clear, in0 => committ, internal_cnt_rst => internal_cnt_rst, @@ -9608,7 +9573,7 @@ DECODER_INST: entity work.vio_manual_ctrl_vio_v3_0_20_decoder \probe_out_modified_reg[15]_0\(2) => \bus_data_int_reg_n_0_[2]\, \probe_out_modified_reg[15]_0\(1) => p_0_in, \probe_out_modified_reg[15]_0\(0) => \bus_data_int_reg_n_0_[0]\, - \rd_en_reg[6]_0\ => PROBE_OUT_ALL_INST_n_42, + \rd_en_reg[6]_0\ => PROBE_OUT_ALL_INST_n_41, rd_probe_out_width => rd_probe_out_width, s_daddr_o(16 downto 0) => bus_addr(16 downto 0), s_den_o => bus_den, @@ -9627,22 +9592,22 @@ PROBE_OUT_ALL_INST: entity work.vio_manual_ctrl_vio_v3_0_20_probe_out_all \G_PROBE_OUT[0].wr_probe_out_reg[0]_0\ => DECODER_INST_n_7, \G_PROBE_OUT[0].wr_probe_out_reg[0]_1\ => DECODER_INST_n_5, \G_PROBE_OUT[0].wr_probe_out_reg[0]_2\ => DECODER_INST_n_6, - \Probe_out_reg_int_reg[10]_0\ => PROBE_OUT_ALL_INST_n_55, - \Probe_out_reg_int_reg[11]_0\ => PROBE_OUT_ALL_INST_n_54, - \Probe_out_reg_int_reg[12]_0\ => PROBE_OUT_ALL_INST_n_53, - \Probe_out_reg_int_reg[13]_0\ => PROBE_OUT_ALL_INST_n_52, - \Probe_out_reg_int_reg[14]_0\ => PROBE_OUT_ALL_INST_n_51, - \Probe_out_reg_int_reg[15]_0\ => PROBE_OUT_ALL_INST_n_50, - \Probe_out_reg_int_reg[3]_0\(3) => PROBE_OUT_ALL_INST_n_46, - \Probe_out_reg_int_reg[3]_0\(2) => PROBE_OUT_ALL_INST_n_47, - \Probe_out_reg_int_reg[3]_0\(1) => PROBE_OUT_ALL_INST_n_48, - \Probe_out_reg_int_reg[3]_0\(0) => PROBE_OUT_ALL_INST_n_49, - \Probe_out_reg_int_reg[4]_0\ => PROBE_OUT_ALL_INST_n_61, - \Probe_out_reg_int_reg[5]_0\ => PROBE_OUT_ALL_INST_n_60, - \Probe_out_reg_int_reg[6]_0\ => PROBE_OUT_ALL_INST_n_59, - \Probe_out_reg_int_reg[7]_0\ => PROBE_OUT_ALL_INST_n_58, - \Probe_out_reg_int_reg[8]_0\ => PROBE_OUT_ALL_INST_n_57, - \Probe_out_reg_int_reg[9]_0\ => PROBE_OUT_ALL_INST_n_56, + \Probe_out_reg_int_reg[10]_0\ => PROBE_OUT_ALL_INST_n_54, + \Probe_out_reg_int_reg[11]_0\ => PROBE_OUT_ALL_INST_n_53, + \Probe_out_reg_int_reg[12]_0\ => PROBE_OUT_ALL_INST_n_52, + \Probe_out_reg_int_reg[13]_0\ => PROBE_OUT_ALL_INST_n_51, + \Probe_out_reg_int_reg[14]_0\ => PROBE_OUT_ALL_INST_n_50, + \Probe_out_reg_int_reg[15]_0\ => PROBE_OUT_ALL_INST_n_49, + \Probe_out_reg_int_reg[3]_0\(3) => PROBE_OUT_ALL_INST_n_45, + \Probe_out_reg_int_reg[3]_0\(2) => PROBE_OUT_ALL_INST_n_46, + \Probe_out_reg_int_reg[3]_0\(1) => PROBE_OUT_ALL_INST_n_47, + \Probe_out_reg_int_reg[3]_0\(0) => PROBE_OUT_ALL_INST_n_48, + \Probe_out_reg_int_reg[4]_0\ => PROBE_OUT_ALL_INST_n_60, + \Probe_out_reg_int_reg[5]_0\ => PROBE_OUT_ALL_INST_n_59, + \Probe_out_reg_int_reg[6]_0\ => PROBE_OUT_ALL_INST_n_58, + \Probe_out_reg_int_reg[7]_0\ => PROBE_OUT_ALL_INST_n_57, + \Probe_out_reg_int_reg[8]_0\ => PROBE_OUT_ALL_INST_n_56, + \Probe_out_reg_int_reg[9]_0\ => PROBE_OUT_ALL_INST_n_55, Q(15) => \bus_data_int_reg_n_0_[15]\, Q(14) => \bus_data_int_reg_n_0_[14]\, Q(13) => \bus_data_int_reg_n_0_[13]\, @@ -9660,13 +9625,13 @@ PROBE_OUT_ALL_INST: entity work.vio_manual_ctrl_vio_v3_0_20_probe_out_all Q(1) => p_0_in, Q(0) => \bus_data_int_reg_n_0_[0]\, SR(0) => clear, - \addr_count[1]_i_5\ => PROBE_OUT_ALL_INST_n_42, + \addr_count[1]_i_5\ => PROBE_OUT_ALL_INST_n_41, \addr_p1_reg[2]_0\(2 downto 0) => xsdb_addr_2_0_p1(2 downto 0), clk => clk, in0 => committ, internal_cnt_rst => internal_cnt_rst, \out\ => bus_clk, - probe_out0(2 downto 0) => probe_out0(2 downto 0), + probe_out0(1 downto 0) => probe_out0(1 downto 0), probe_out1(0) => probe_out1(0), probe_out2(31 downto 0) => probe_out2(31 downto 0), probe_out3(1 downto 0) => probe_out3(1 downto 0), @@ -9833,7 +9798,7 @@ use UNISIM.VCOMPONENTS.ALL; entity vio_manual_ctrl is port ( clk : in STD_LOGIC; - probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); @@ -10653,9 +10618,9 @@ architecture STRUCTURE of vio_manual_ctrl is attribute C_PROBE_IN9_WIDTH : integer; attribute C_PROBE_IN9_WIDTH of inst : label is 1; attribute C_PROBE_OUT0_INIT_VAL : string; - attribute C_PROBE_OUT0_INIT_VAL of inst : label is "3'b000"; + attribute C_PROBE_OUT0_INIT_VAL of inst : label is "2'b10"; attribute C_PROBE_OUT0_WIDTH : integer; - attribute C_PROBE_OUT0_WIDTH of inst : label is 3; + attribute C_PROBE_OUT0_WIDTH of inst : label is 2; attribute C_PROBE_OUT100_INIT_VAL : string; attribute C_PROBE_OUT100_INIT_VAL of inst : label is "1'b0"; attribute C_PROBE_OUT100_WIDTH : integer; @@ -11689,1043 +11654,1043 @@ architecture STRUCTURE of vio_manual_ctrl is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000001"; attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000010"; attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000101110"; attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000010001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000010001000"; attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000010001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000010001001"; attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000010001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000010001010"; attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000010001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000010001011"; attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000010001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000010001100"; attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000010001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000010001101"; attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000010001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000010001110"; attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000010010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000010001111"; attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000010010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000010010000"; attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000010010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000010010001"; attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000101111"; attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000010010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000010010010"; attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000010010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000010010011"; attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000010010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000010010100"; attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000010010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000010010101"; attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000010010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000010010110"; attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000010011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000010010111"; attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000010011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000010011000"; attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000010011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000010011001"; attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000010011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000010011010"; attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000010011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000010011011"; attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000110000"; attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000010011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000010011100"; attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000010011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000010011101"; attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000010011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000010011110"; attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000010100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000010011111"; attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000010100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000010100000"; attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000010100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000010100001"; attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000010100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000010100010"; attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000010100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000010100011"; attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010100100"; attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010100110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010100101"; attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000110001"; attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010100111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010100110"; attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010101000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010100111"; attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010101000"; attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010101001"; attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010101010"; attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010101011"; attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010101100"; attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010101101"; attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010101110"; attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010101111"; attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000110010"; attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010110000"; attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010110001"; attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010110010"; attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010110011"; attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010110100"; attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010110101"; attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010110110"; attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010110111"; attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010111000"; attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010111001"; attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000110011"; attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010111010"; attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010111011"; attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010111100"; attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010111101"; attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010111110"; attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000011000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010111111"; attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000011000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000011000000"; attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000011000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000011000001"; attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000011000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000011000010"; attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000011000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000011000011"; attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000110100"; attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000011000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000011000100"; attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000011000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000011000101"; attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000011000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000011000110"; attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000011001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000011000111"; attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000011001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000011001000"; attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000011001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000011001001"; attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000011001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000011001010"; attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000011001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000011001011"; attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000011001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000011001100"; attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000011001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000011001101"; attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000110101"; attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000011001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000011001110"; attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000011010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000011001111"; attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000011010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000011010000"; attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000011010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000011010001"; attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000011010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000011010010"; attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000011010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000011010011"; attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000011010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000011010100"; attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000011010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000011010101"; attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000011010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000011010110"; attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000011011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000011010111"; attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000110110"; attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000011011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000011011000"; attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000011011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000011011001"; attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000011011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000011011010"; attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000011011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000011011011"; attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000011011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000011011100"; attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000011011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000011011101"; attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000011011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000011011110"; attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000011100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000011011111"; attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000011100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000011100000"; attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000011100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000011100001"; attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000110111"; attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000011100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000011100010"; attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000011100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000011100011"; attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011100100"; attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011100110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011100101"; attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011100111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011100110"; attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011101000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011100111"; attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011101000"; attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011101001"; attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011101010"; attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011101011"; attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000100010"; attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000111000"; attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011101100"; attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011101101"; attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011101110"; attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011101111"; attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011110000"; attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011110001"; attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011110010"; attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011110011"; attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011110100"; attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011110101"; attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000111001"; attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011110110"; attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011110111"; attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011111000"; attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011111001"; attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011111010"; attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011111011"; attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011111100"; attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011111101"; attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011111110"; attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000100000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011111111"; attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000111010"; attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000100000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000100000000"; attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000100000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000100000001"; attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000100000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000100000010"; attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000100000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000100000011"; attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000100000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000100000100"; attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000100000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000100000101"; attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000100000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000100000110"; attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000100001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000100000111"; attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000100001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000100001000"; attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000100001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000100001001"; attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000111011"; attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000100001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000100001010"; attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000100001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000100001011"; attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000100001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000100001100"; attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000100001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000100001101"; attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000100001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000100001110"; attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000100010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000100001111"; attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000100010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000100010000"; attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000100010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000100010001"; attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000100010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000100010010"; attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000100010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000100010011"; attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000111100"; attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000100010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000100010100"; attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000100010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000100010101"; attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000100010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000100010110"; attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000100011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000100010111"; attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000100011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000100011000"; attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000100011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000100011001"; attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000100011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000100011010"; attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000100011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000100011011"; attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000100011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000100011100"; attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000100011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000100011101"; attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000111101"; attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000100011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000100011110"; attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000100100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000100011111"; attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000100100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000100100000"; attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000100100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000100100001"; attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000100100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000100100010"; attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000100100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000100100011"; attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000111110"; attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000001000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000111111"; attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000001000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000001000000"; attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000001000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000001000001"; attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000100100"; attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000001000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000001000010"; attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000001000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000001000011"; attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000001000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000001000100"; attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000001000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000001000101"; attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000001000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000001000110"; attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000001001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000001000111"; attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000001001001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000001001000"; attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000001001010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000001001001"; attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000001001011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000001001010"; attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000001001100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000001001011"; attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000101000"; attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000001001101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000001001100"; attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000001001110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000001001101"; attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000001001111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000001001110"; attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000001010000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000001001111"; attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000001010001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000001010000"; attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000001010010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000001010001"; attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000001010011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000001010010"; attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000001010100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000001010011"; attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000001010101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000001010100"; attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000001010110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000001010101"; attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000101001"; attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000001010111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000001010110"; attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000001011000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000001010111"; attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000001011001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000001011000"; attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000001011010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000001011001"; attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000001011011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000001011010"; attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000001011100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000001011011"; attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000001011101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000001011100"; attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000001011110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000001011101"; attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000001011111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000001011110"; attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000001100000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000001011111"; attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000101010"; attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000001100001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000001100000"; attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000001100010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000001100001"; attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000001100011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000001100010"; attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000001100100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000001100011"; attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001100101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001100100"; attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001100110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001100101"; attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001100111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001100110"; attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001101000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001100111"; attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001101001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001101000"; attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001101010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001101001"; attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000101011"; attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001101011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001101010"; attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001101100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001101011"; attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001101100"; attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001101101"; attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001101111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001101110"; attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001110000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001101111"; attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001110001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001110000"; attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001110010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001110001"; attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001110011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001110010"; attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001110100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001110011"; attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000101101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000101100"; attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001110101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001110100"; attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001110110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001110101"; attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001110111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001110110"; attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001111000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001110111"; attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001111001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001111000"; attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001111010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001111001"; attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001111011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001111010"; attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001111100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001111011"; attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001111101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001111100"; attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001111110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001111101"; attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000101110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000101101"; attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001111111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001111110"; attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000010000000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001111111"; attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000010000001"; + attribute LC_HIGH_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000010000000"; attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000010000010"; + attribute LC_HIGH_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000010000001"; attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000010000011"; + attribute LC_HIGH_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000010000010"; attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000010000100"; + attribute LC_HIGH_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000010000011"; attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000010000101"; + attribute LC_HIGH_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000010000100"; attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000010000110"; + attribute LC_HIGH_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000010000101"; attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000010000111"; + attribute LC_HIGH_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000010000110"; attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string; - attribute LC_HIGH_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000010001000"; + attribute LC_HIGH_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000010000111"; attribute LC_LOW_BIT_POS_PROBE_OUT0 : string; attribute LC_LOW_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000000"; attribute LC_LOW_BIT_POS_PROBE_OUT1 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000010"; attribute LC_LOW_BIT_POS_PROBE_OUT10 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000101110"; attribute LC_LOW_BIT_POS_PROBE_OUT100 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000010001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000010001000"; attribute LC_LOW_BIT_POS_PROBE_OUT101 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000010001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000010001001"; attribute LC_LOW_BIT_POS_PROBE_OUT102 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000010001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000010001010"; attribute LC_LOW_BIT_POS_PROBE_OUT103 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000010001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000010001011"; attribute LC_LOW_BIT_POS_PROBE_OUT104 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000010001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000010001100"; attribute LC_LOW_BIT_POS_PROBE_OUT105 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000010001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000010001101"; attribute LC_LOW_BIT_POS_PROBE_OUT106 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000010001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000010001110"; attribute LC_LOW_BIT_POS_PROBE_OUT107 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000010010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000010001111"; attribute LC_LOW_BIT_POS_PROBE_OUT108 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000010010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000010010000"; attribute LC_LOW_BIT_POS_PROBE_OUT109 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000010010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000010010001"; attribute LC_LOW_BIT_POS_PROBE_OUT11 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000101111"; attribute LC_LOW_BIT_POS_PROBE_OUT110 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000010010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000010010010"; attribute LC_LOW_BIT_POS_PROBE_OUT111 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000010010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000010010011"; attribute LC_LOW_BIT_POS_PROBE_OUT112 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000010010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000010010100"; attribute LC_LOW_BIT_POS_PROBE_OUT113 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000010010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000010010101"; attribute LC_LOW_BIT_POS_PROBE_OUT114 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000010010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000010010110"; attribute LC_LOW_BIT_POS_PROBE_OUT115 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000010011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000010010111"; attribute LC_LOW_BIT_POS_PROBE_OUT116 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000010011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000010011000"; attribute LC_LOW_BIT_POS_PROBE_OUT117 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000010011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000010011001"; attribute LC_LOW_BIT_POS_PROBE_OUT118 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000010011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000010011010"; attribute LC_LOW_BIT_POS_PROBE_OUT119 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000010011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000010011011"; attribute LC_LOW_BIT_POS_PROBE_OUT12 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000110000"; attribute LC_LOW_BIT_POS_PROBE_OUT120 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000010011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000010011100"; attribute LC_LOW_BIT_POS_PROBE_OUT121 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000010011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000010011101"; attribute LC_LOW_BIT_POS_PROBE_OUT122 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000010011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000010011110"; attribute LC_LOW_BIT_POS_PROBE_OUT123 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000010100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000010011111"; attribute LC_LOW_BIT_POS_PROBE_OUT124 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000010100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000010100000"; attribute LC_LOW_BIT_POS_PROBE_OUT125 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000010100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000010100001"; attribute LC_LOW_BIT_POS_PROBE_OUT126 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000010100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000010100010"; attribute LC_LOW_BIT_POS_PROBE_OUT127 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000010100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000010100011"; attribute LC_LOW_BIT_POS_PROBE_OUT128 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010100101"; + attribute LC_LOW_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010100100"; attribute LC_LOW_BIT_POS_PROBE_OUT129 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010100101"; attribute LC_LOW_BIT_POS_PROBE_OUT13 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000110001"; attribute LC_LOW_BIT_POS_PROBE_OUT130 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010100111"; + attribute LC_LOW_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010100110"; attribute LC_LOW_BIT_POS_PROBE_OUT131 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010101000"; + attribute LC_LOW_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010100111"; attribute LC_LOW_BIT_POS_PROBE_OUT132 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010101001"; + attribute LC_LOW_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010101000"; attribute LC_LOW_BIT_POS_PROBE_OUT133 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010101001"; attribute LC_LOW_BIT_POS_PROBE_OUT134 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010101010"; attribute LC_LOW_BIT_POS_PROBE_OUT135 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010101011"; attribute LC_LOW_BIT_POS_PROBE_OUT136 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010101100"; attribute LC_LOW_BIT_POS_PROBE_OUT137 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010101101"; attribute LC_LOW_BIT_POS_PROBE_OUT138 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010101110"; attribute LC_LOW_BIT_POS_PROBE_OUT139 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010101111"; attribute LC_LOW_BIT_POS_PROBE_OUT14 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000110010"; attribute LC_LOW_BIT_POS_PROBE_OUT140 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010110000"; attribute LC_LOW_BIT_POS_PROBE_OUT141 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010110001"; attribute LC_LOW_BIT_POS_PROBE_OUT142 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010110010"; attribute LC_LOW_BIT_POS_PROBE_OUT143 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010110011"; attribute LC_LOW_BIT_POS_PROBE_OUT144 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010110100"; attribute LC_LOW_BIT_POS_PROBE_OUT145 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010110101"; attribute LC_LOW_BIT_POS_PROBE_OUT146 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010110110"; attribute LC_LOW_BIT_POS_PROBE_OUT147 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010110111"; attribute LC_LOW_BIT_POS_PROBE_OUT148 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010111000"; attribute LC_LOW_BIT_POS_PROBE_OUT149 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010111001"; attribute LC_LOW_BIT_POS_PROBE_OUT15 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000110011"; attribute LC_LOW_BIT_POS_PROBE_OUT150 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010111010"; attribute LC_LOW_BIT_POS_PROBE_OUT151 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010111011"; attribute LC_LOW_BIT_POS_PROBE_OUT152 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010111100"; attribute LC_LOW_BIT_POS_PROBE_OUT153 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010111101"; attribute LC_LOW_BIT_POS_PROBE_OUT154 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010111110"; attribute LC_LOW_BIT_POS_PROBE_OUT155 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000011000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010111111"; attribute LC_LOW_BIT_POS_PROBE_OUT156 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000011000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000011000000"; attribute LC_LOW_BIT_POS_PROBE_OUT157 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000011000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000011000001"; attribute LC_LOW_BIT_POS_PROBE_OUT158 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000011000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000011000010"; attribute LC_LOW_BIT_POS_PROBE_OUT159 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000011000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000011000011"; attribute LC_LOW_BIT_POS_PROBE_OUT16 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000110100"; attribute LC_LOW_BIT_POS_PROBE_OUT160 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000011000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000011000100"; attribute LC_LOW_BIT_POS_PROBE_OUT161 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000011000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000011000101"; attribute LC_LOW_BIT_POS_PROBE_OUT162 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000011000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000011000110"; attribute LC_LOW_BIT_POS_PROBE_OUT163 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000011001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000011000111"; attribute LC_LOW_BIT_POS_PROBE_OUT164 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000011001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000011001000"; attribute LC_LOW_BIT_POS_PROBE_OUT165 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000011001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000011001001"; attribute LC_LOW_BIT_POS_PROBE_OUT166 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000011001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000011001010"; attribute LC_LOW_BIT_POS_PROBE_OUT167 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000011001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000011001011"; attribute LC_LOW_BIT_POS_PROBE_OUT168 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000011001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000011001100"; attribute LC_LOW_BIT_POS_PROBE_OUT169 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000011001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000011001101"; attribute LC_LOW_BIT_POS_PROBE_OUT17 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000110101"; attribute LC_LOW_BIT_POS_PROBE_OUT170 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000011001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000011001110"; attribute LC_LOW_BIT_POS_PROBE_OUT171 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000011010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000011001111"; attribute LC_LOW_BIT_POS_PROBE_OUT172 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000011010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000011010000"; attribute LC_LOW_BIT_POS_PROBE_OUT173 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000011010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000011010001"; attribute LC_LOW_BIT_POS_PROBE_OUT174 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000011010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000011010010"; attribute LC_LOW_BIT_POS_PROBE_OUT175 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000011010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000011010011"; attribute LC_LOW_BIT_POS_PROBE_OUT176 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000011010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000011010100"; attribute LC_LOW_BIT_POS_PROBE_OUT177 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000011010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000011010101"; attribute LC_LOW_BIT_POS_PROBE_OUT178 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000011010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000011010110"; attribute LC_LOW_BIT_POS_PROBE_OUT179 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000011011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000011010111"; attribute LC_LOW_BIT_POS_PROBE_OUT18 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000110110"; attribute LC_LOW_BIT_POS_PROBE_OUT180 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000011011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000011011000"; attribute LC_LOW_BIT_POS_PROBE_OUT181 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000011011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000011011001"; attribute LC_LOW_BIT_POS_PROBE_OUT182 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000011011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000011011010"; attribute LC_LOW_BIT_POS_PROBE_OUT183 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000011011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000011011011"; attribute LC_LOW_BIT_POS_PROBE_OUT184 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000011011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000011011100"; attribute LC_LOW_BIT_POS_PROBE_OUT185 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000011011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000011011101"; attribute LC_LOW_BIT_POS_PROBE_OUT186 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000011011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000011011110"; attribute LC_LOW_BIT_POS_PROBE_OUT187 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000011100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000011011111"; attribute LC_LOW_BIT_POS_PROBE_OUT188 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000011100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000011100000"; attribute LC_LOW_BIT_POS_PROBE_OUT189 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000011100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000011100001"; attribute LC_LOW_BIT_POS_PROBE_OUT19 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000110111"; attribute LC_LOW_BIT_POS_PROBE_OUT190 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000011100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000011100010"; attribute LC_LOW_BIT_POS_PROBE_OUT191 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000011100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000011100011"; attribute LC_LOW_BIT_POS_PROBE_OUT192 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011100101"; + attribute LC_LOW_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011100100"; attribute LC_LOW_BIT_POS_PROBE_OUT193 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011100101"; attribute LC_LOW_BIT_POS_PROBE_OUT194 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011100111"; + attribute LC_LOW_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011100110"; attribute LC_LOW_BIT_POS_PROBE_OUT195 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011101000"; + attribute LC_LOW_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011100111"; attribute LC_LOW_BIT_POS_PROBE_OUT196 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011101001"; + attribute LC_LOW_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011101000"; attribute LC_LOW_BIT_POS_PROBE_OUT197 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011101001"; attribute LC_LOW_BIT_POS_PROBE_OUT198 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011101010"; attribute LC_LOW_BIT_POS_PROBE_OUT199 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011101011"; attribute LC_LOW_BIT_POS_PROBE_OUT2 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000011"; attribute LC_LOW_BIT_POS_PROBE_OUT20 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000111000"; attribute LC_LOW_BIT_POS_PROBE_OUT200 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011101100"; attribute LC_LOW_BIT_POS_PROBE_OUT201 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011101101"; attribute LC_LOW_BIT_POS_PROBE_OUT202 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011101110"; attribute LC_LOW_BIT_POS_PROBE_OUT203 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011101111"; attribute LC_LOW_BIT_POS_PROBE_OUT204 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011110000"; attribute LC_LOW_BIT_POS_PROBE_OUT205 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011110001"; attribute LC_LOW_BIT_POS_PROBE_OUT206 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011110010"; attribute LC_LOW_BIT_POS_PROBE_OUT207 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011110011"; attribute LC_LOW_BIT_POS_PROBE_OUT208 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011110100"; attribute LC_LOW_BIT_POS_PROBE_OUT209 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011110101"; attribute LC_LOW_BIT_POS_PROBE_OUT21 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000111001"; attribute LC_LOW_BIT_POS_PROBE_OUT210 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011110110"; attribute LC_LOW_BIT_POS_PROBE_OUT211 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011110111"; attribute LC_LOW_BIT_POS_PROBE_OUT212 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011111000"; attribute LC_LOW_BIT_POS_PROBE_OUT213 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011111001"; attribute LC_LOW_BIT_POS_PROBE_OUT214 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011111010"; attribute LC_LOW_BIT_POS_PROBE_OUT215 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011111011"; attribute LC_LOW_BIT_POS_PROBE_OUT216 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011111100"; attribute LC_LOW_BIT_POS_PROBE_OUT217 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011111101"; attribute LC_LOW_BIT_POS_PROBE_OUT218 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011111110"; attribute LC_LOW_BIT_POS_PROBE_OUT219 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000100000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011111111"; attribute LC_LOW_BIT_POS_PROBE_OUT22 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000111010"; attribute LC_LOW_BIT_POS_PROBE_OUT220 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000100000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000100000000"; attribute LC_LOW_BIT_POS_PROBE_OUT221 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000100000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000100000001"; attribute LC_LOW_BIT_POS_PROBE_OUT222 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000100000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000100000010"; attribute LC_LOW_BIT_POS_PROBE_OUT223 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000100000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000100000011"; attribute LC_LOW_BIT_POS_PROBE_OUT224 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000100000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000100000100"; attribute LC_LOW_BIT_POS_PROBE_OUT225 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000100000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000100000101"; attribute LC_LOW_BIT_POS_PROBE_OUT226 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000100000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000100000110"; attribute LC_LOW_BIT_POS_PROBE_OUT227 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000100001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000100000111"; attribute LC_LOW_BIT_POS_PROBE_OUT228 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000100001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000100001000"; attribute LC_LOW_BIT_POS_PROBE_OUT229 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000100001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000100001001"; attribute LC_LOW_BIT_POS_PROBE_OUT23 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000111011"; attribute LC_LOW_BIT_POS_PROBE_OUT230 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000100001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000100001010"; attribute LC_LOW_BIT_POS_PROBE_OUT231 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000100001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000100001011"; attribute LC_LOW_BIT_POS_PROBE_OUT232 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000100001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000100001100"; attribute LC_LOW_BIT_POS_PROBE_OUT233 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000100001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000100001101"; attribute LC_LOW_BIT_POS_PROBE_OUT234 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000100001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000100001110"; attribute LC_LOW_BIT_POS_PROBE_OUT235 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000100010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000100001111"; attribute LC_LOW_BIT_POS_PROBE_OUT236 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000100010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000100010000"; attribute LC_LOW_BIT_POS_PROBE_OUT237 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000100010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000100010001"; attribute LC_LOW_BIT_POS_PROBE_OUT238 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000100010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000100010010"; attribute LC_LOW_BIT_POS_PROBE_OUT239 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000100010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000100010011"; attribute LC_LOW_BIT_POS_PROBE_OUT24 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000111100"; attribute LC_LOW_BIT_POS_PROBE_OUT240 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000100010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000100010100"; attribute LC_LOW_BIT_POS_PROBE_OUT241 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000100010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000100010101"; attribute LC_LOW_BIT_POS_PROBE_OUT242 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000100010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000100010110"; attribute LC_LOW_BIT_POS_PROBE_OUT243 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000100011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000100010111"; attribute LC_LOW_BIT_POS_PROBE_OUT244 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000100011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000100011000"; attribute LC_LOW_BIT_POS_PROBE_OUT245 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000100011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000100011001"; attribute LC_LOW_BIT_POS_PROBE_OUT246 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000100011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000100011010"; attribute LC_LOW_BIT_POS_PROBE_OUT247 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000100011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000100011011"; attribute LC_LOW_BIT_POS_PROBE_OUT248 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000100011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000100011100"; attribute LC_LOW_BIT_POS_PROBE_OUT249 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000100011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000100011101"; attribute LC_LOW_BIT_POS_PROBE_OUT25 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000111101"; attribute LC_LOW_BIT_POS_PROBE_OUT250 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000100011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000100011110"; attribute LC_LOW_BIT_POS_PROBE_OUT251 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000100100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000100011111"; attribute LC_LOW_BIT_POS_PROBE_OUT252 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000100100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000100100000"; attribute LC_LOW_BIT_POS_PROBE_OUT253 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000100100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000100100001"; attribute LC_LOW_BIT_POS_PROBE_OUT254 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000100100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000100100010"; attribute LC_LOW_BIT_POS_PROBE_OUT255 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000100100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000100100011"; attribute LC_LOW_BIT_POS_PROBE_OUT26 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000111110"; attribute LC_LOW_BIT_POS_PROBE_OUT27 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000001000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000111111"; attribute LC_LOW_BIT_POS_PROBE_OUT28 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000001000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000001000000"; attribute LC_LOW_BIT_POS_PROBE_OUT29 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000001000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000001000001"; attribute LC_LOW_BIT_POS_PROBE_OUT3 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000100011"; attribute LC_LOW_BIT_POS_PROBE_OUT30 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000001000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000001000010"; attribute LC_LOW_BIT_POS_PROBE_OUT31 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000001000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000001000011"; attribute LC_LOW_BIT_POS_PROBE_OUT32 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000001000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000001000100"; attribute LC_LOW_BIT_POS_PROBE_OUT33 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000001000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000001000101"; attribute LC_LOW_BIT_POS_PROBE_OUT34 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000001000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000001000110"; attribute LC_LOW_BIT_POS_PROBE_OUT35 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000001001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000001000111"; attribute LC_LOW_BIT_POS_PROBE_OUT36 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000001001001"; + attribute LC_LOW_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000001001000"; attribute LC_LOW_BIT_POS_PROBE_OUT37 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000001001010"; + attribute LC_LOW_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000001001001"; attribute LC_LOW_BIT_POS_PROBE_OUT38 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000001001011"; + attribute LC_LOW_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000001001010"; attribute LC_LOW_BIT_POS_PROBE_OUT39 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000001001100"; + attribute LC_LOW_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000001001011"; attribute LC_LOW_BIT_POS_PROBE_OUT4 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000100101"; attribute LC_LOW_BIT_POS_PROBE_OUT40 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000001001101"; + attribute LC_LOW_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000001001100"; attribute LC_LOW_BIT_POS_PROBE_OUT41 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000001001110"; + attribute LC_LOW_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000001001101"; attribute LC_LOW_BIT_POS_PROBE_OUT42 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000001001111"; + attribute LC_LOW_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000001001110"; attribute LC_LOW_BIT_POS_PROBE_OUT43 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000001010000"; + attribute LC_LOW_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000001001111"; attribute LC_LOW_BIT_POS_PROBE_OUT44 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000001010001"; + attribute LC_LOW_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000001010000"; attribute LC_LOW_BIT_POS_PROBE_OUT45 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000001010010"; + attribute LC_LOW_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000001010001"; attribute LC_LOW_BIT_POS_PROBE_OUT46 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000001010011"; + attribute LC_LOW_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000001010010"; attribute LC_LOW_BIT_POS_PROBE_OUT47 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000001010100"; + attribute LC_LOW_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000001010011"; attribute LC_LOW_BIT_POS_PROBE_OUT48 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000001010101"; + attribute LC_LOW_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000001010100"; attribute LC_LOW_BIT_POS_PROBE_OUT49 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000001010110"; + attribute LC_LOW_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000001010101"; attribute LC_LOW_BIT_POS_PROBE_OUT5 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000101001"; attribute LC_LOW_BIT_POS_PROBE_OUT50 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000001010111"; + attribute LC_LOW_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000001010110"; attribute LC_LOW_BIT_POS_PROBE_OUT51 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000001011000"; + attribute LC_LOW_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000001010111"; attribute LC_LOW_BIT_POS_PROBE_OUT52 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000001011001"; + attribute LC_LOW_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000001011000"; attribute LC_LOW_BIT_POS_PROBE_OUT53 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000001011010"; + attribute LC_LOW_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000001011001"; attribute LC_LOW_BIT_POS_PROBE_OUT54 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000001011011"; + attribute LC_LOW_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000001011010"; attribute LC_LOW_BIT_POS_PROBE_OUT55 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000001011100"; + attribute LC_LOW_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000001011011"; attribute LC_LOW_BIT_POS_PROBE_OUT56 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000001011101"; + attribute LC_LOW_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000001011100"; attribute LC_LOW_BIT_POS_PROBE_OUT57 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000001011110"; + attribute LC_LOW_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000001011101"; attribute LC_LOW_BIT_POS_PROBE_OUT58 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000001011111"; + attribute LC_LOW_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000001011110"; attribute LC_LOW_BIT_POS_PROBE_OUT59 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000001100000"; + attribute LC_LOW_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000001011111"; attribute LC_LOW_BIT_POS_PROBE_OUT6 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000101010"; attribute LC_LOW_BIT_POS_PROBE_OUT60 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000001100001"; + attribute LC_LOW_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000001100000"; attribute LC_LOW_BIT_POS_PROBE_OUT61 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000001100010"; + attribute LC_LOW_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000001100001"; attribute LC_LOW_BIT_POS_PROBE_OUT62 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000001100011"; + attribute LC_LOW_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000001100010"; attribute LC_LOW_BIT_POS_PROBE_OUT63 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000001100100"; + attribute LC_LOW_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000001100011"; attribute LC_LOW_BIT_POS_PROBE_OUT64 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001100101"; + attribute LC_LOW_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001100100"; attribute LC_LOW_BIT_POS_PROBE_OUT65 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001100110"; + attribute LC_LOW_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001100101"; attribute LC_LOW_BIT_POS_PROBE_OUT66 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001100111"; + attribute LC_LOW_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001100110"; attribute LC_LOW_BIT_POS_PROBE_OUT67 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001101000"; + attribute LC_LOW_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001100111"; attribute LC_LOW_BIT_POS_PROBE_OUT68 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001101001"; + attribute LC_LOW_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001101000"; attribute LC_LOW_BIT_POS_PROBE_OUT69 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001101010"; + attribute LC_LOW_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001101001"; attribute LC_LOW_BIT_POS_PROBE_OUT7 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000101011"; attribute LC_LOW_BIT_POS_PROBE_OUT70 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001101011"; + attribute LC_LOW_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001101010"; attribute LC_LOW_BIT_POS_PROBE_OUT71 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001101100"; + attribute LC_LOW_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001101011"; attribute LC_LOW_BIT_POS_PROBE_OUT72 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001101100"; attribute LC_LOW_BIT_POS_PROBE_OUT73 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001101101"; attribute LC_LOW_BIT_POS_PROBE_OUT74 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001101111"; + attribute LC_LOW_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001101110"; attribute LC_LOW_BIT_POS_PROBE_OUT75 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001110000"; + attribute LC_LOW_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001101111"; attribute LC_LOW_BIT_POS_PROBE_OUT76 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001110001"; + attribute LC_LOW_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001110000"; attribute LC_LOW_BIT_POS_PROBE_OUT77 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001110010"; + attribute LC_LOW_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001110001"; attribute LC_LOW_BIT_POS_PROBE_OUT78 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001110011"; + attribute LC_LOW_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001110010"; attribute LC_LOW_BIT_POS_PROBE_OUT79 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001110100"; + attribute LC_LOW_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001110011"; attribute LC_LOW_BIT_POS_PROBE_OUT8 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000101101"; + attribute LC_LOW_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000101100"; attribute LC_LOW_BIT_POS_PROBE_OUT80 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001110101"; + attribute LC_LOW_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001110100"; attribute LC_LOW_BIT_POS_PROBE_OUT81 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001110110"; + attribute LC_LOW_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001110101"; attribute LC_LOW_BIT_POS_PROBE_OUT82 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001110111"; + attribute LC_LOW_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001110110"; attribute LC_LOW_BIT_POS_PROBE_OUT83 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001111000"; + attribute LC_LOW_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001110111"; attribute LC_LOW_BIT_POS_PROBE_OUT84 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001111001"; + attribute LC_LOW_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001111000"; attribute LC_LOW_BIT_POS_PROBE_OUT85 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001111010"; + attribute LC_LOW_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001111001"; attribute LC_LOW_BIT_POS_PROBE_OUT86 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001111011"; + attribute LC_LOW_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001111010"; attribute LC_LOW_BIT_POS_PROBE_OUT87 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001111100"; + attribute LC_LOW_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001111011"; attribute LC_LOW_BIT_POS_PROBE_OUT88 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001111101"; + attribute LC_LOW_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001111100"; attribute LC_LOW_BIT_POS_PROBE_OUT89 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001111110"; + attribute LC_LOW_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001111101"; attribute LC_LOW_BIT_POS_PROBE_OUT9 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000101110"; + attribute LC_LOW_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000101101"; attribute LC_LOW_BIT_POS_PROBE_OUT90 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001111111"; + attribute LC_LOW_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001111110"; attribute LC_LOW_BIT_POS_PROBE_OUT91 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000010000000"; + attribute LC_LOW_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001111111"; attribute LC_LOW_BIT_POS_PROBE_OUT92 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000010000001"; + attribute LC_LOW_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000010000000"; attribute LC_LOW_BIT_POS_PROBE_OUT93 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000010000010"; + attribute LC_LOW_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000010000001"; attribute LC_LOW_BIT_POS_PROBE_OUT94 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000010000011"; + attribute LC_LOW_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000010000010"; attribute LC_LOW_BIT_POS_PROBE_OUT95 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000010000100"; + attribute LC_LOW_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000010000011"; attribute LC_LOW_BIT_POS_PROBE_OUT96 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000010000101"; + attribute LC_LOW_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000010000100"; attribute LC_LOW_BIT_POS_PROBE_OUT97 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000010000110"; + attribute LC_LOW_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000010000101"; attribute LC_LOW_BIT_POS_PROBE_OUT98 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000010000111"; + attribute LC_LOW_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000010000110"; attribute LC_LOW_BIT_POS_PROBE_OUT99 : string; - attribute LC_LOW_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000010001000"; + attribute LC_LOW_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000010000111"; attribute LC_PROBE_IN_WIDTH_STRING : string; attribute LC_PROBE_IN_WIDTH_STRING of inst : label is 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attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string; - attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of inst : label is "4096'b0000000100100100000000010010001100000001001000100000000100100001000000010010000000000001000111110000000100011110000000010001110100000001000111000000000100011011000000010001101000000001000110010000000100011000000000010001011100000001000101100000000100010101000000010001010000000001000100110000000100010010000000010001000100000001000100000000000100001111000000010000111000000001000011010000000100001100000000010000101100000001000010100000000100001001000000010000100000000001000001110000000100000110000000010000010100000001000001000000000100000011000000010000001000000001000000010000000100000000000000001111111100000000111111100000000011111101000000001111110000000000111110110000000011111010000000001111100100000000111110000000000011110111000000001111011000000000111101010000000011110100000000001111001100000000111100100000000011110001000000001111000000000000111011110000000011101110000000001110110100000000111011000000000011101011000000001110101000000000111010010000000011101000000000001110011100000000111001100000000011100101000000001110010000000000111000110000000011100010000000001110000100000000111000000000000011011111000000001101111000000000110111010000000011011100000000001101101100000000110110100000000011011001000000001101100000000000110101110000000011010110000000001101010100000000110101000000000011010011000000001101001000000000110100010000000011010000000000001100111100000000110011100000000011001101000000001100110000000000110010110000000011001010000000001100100100000000110010000000000011000111000000001100011000000000110001010000000011000100000000001100001100000000110000100000000011000001000000001100000000000000101111110000000010111110000000001011110100000000101111000000000010111011000000001011101000000000101110010000000010111000000000001011011100000000101101100000000010110101000000001011010000000000101100110000000010110010000000001011000100000000101100000000000010101111000000001010111000000000101011010000000010101100000000001010101100000000101010100000000010101001000000001010100000000000101001110000000010100110000000001010010100000000101001000000000010100011000000001010001000000000101000010000000010100000000000001001111100000000100111100000000010011101000000001001110000000000100110110000000010011010000000001001100100000000100110000000000010010111000000001001011000000000100101010000000010010100000000001001001100000000100100100000000010010001000000001001000000000000100011110000000010001110000000001000110100000000100011000000000010001011000000001000101000000000100010010000000010001000000000001000011100000000100001100000000010000101000000001000010000000000100000110000000010000010000000001000000100000000100000000000000001111111000000000111111000000000011111010000000001111100000000000111101100000000011110100000000001111001000000000111100000000000011101110000000001110110000000000111010100000000011101000000000001110011000000000111001000000000011100010000000001110000000000000110111100000000011011100000000001101101000000000110110000000000011010110000000001101010000000000110100100000000011010000000000001100111000000000110011000000000011001010000000001100100000000000110001100000000011000100000000001100001000000000110000000000000010111110000000001011110000000000101110100000000010111000000000001011011000000000101101000000000010110010000000001011000000000000101011100000000010101100000000001010101000000000101010000000000010100110000000001010010000000000101000100000000010100000000000001001111000000000100111000000000010011010000000001001100000000000100101100000000010010100000000001001001000000000100100000000000010001110000000001000110000000000100010100000000010001000000000001000011000000000100001000000000010000010000000001000000000000000011111100000000001111100000000000111101000000000011110000000000001110110000000000111010000000000011100100000000001110000000000000110111000000000011011000000000001101010000000000110100000000000011001100000000001100100000000000110001000000000011000000000000001011110000000000101110000000000010110100000000001011000000000000101011000000000010101000000000001010010000000000100101000000000010001100000000000000110000000000000010"; + attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of inst : label is "4096'b0000000100100011000000010010001000000001001000010000000100100000000000010001111100000001000111100000000100011101000000010001110000000001000110110000000100011010000000010001100100000001000110000000000100010111000000010001011000000001000101010000000100010100000000010001001100000001000100100000000100010001000000010001000000000001000011110000000100001110000000010000110100000001000011000000000100001011000000010000101000000001000010010000000100001000000000010000011100000001000001100000000100000101000000010000010000000001000000110000000100000010000000010000000100000001000000000000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100100000000000010001000000000000000100000000000000001"; attribute LC_PROBE_OUT_INIT_VAL_STRING : string; - attribute LC_PROBE_OUT_INIT_VAL_STRING of inst : label is "293'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000"; + attribute LC_PROBE_OUT_INIT_VAL_STRING of inst : label is "292'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000010"; attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string; - attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of inst : label is "4096'b0000000100100100000000010010001100000001001000100000000100100001000000010010000000000001000111110000000100011110000000010001110100000001000111000000000100011011000000010001101000000001000110010000000100011000000000010001011100000001000101100000000100010101000000010001010000000001000100110000000100010010000000010001000100000001000100000000000100001111000000010000111000000001000011010000000100001100000000010000101100000001000010100000000100001001000000010000100000000001000001110000000100000110000000010000010100000001000001000000000100000011000000010000001000000001000000010000000100000000000000001111111100000000111111100000000011111101000000001111110000000000111110110000000011111010000000001111100100000000111110000000000011110111000000001111011000000000111101010000000011110100000000001111001100000000111100100000000011110001000000001111000000000000111011110000000011101110000000001110110100000000111011000000000011101011000000001110101000000000111010010000000011101000000000001110011100000000111001100000000011100101000000001110010000000000111000110000000011100010000000001110000100000000111000000000000011011111000000001101111000000000110111010000000011011100000000001101101100000000110110100000000011011001000000001101100000000000110101110000000011010110000000001101010100000000110101000000000011010011000000001101001000000000110100010000000011010000000000001100111100000000110011100000000011001101000000001100110000000000110010110000000011001010000000001100100100000000110010000000000011000111000000001100011000000000110001010000000011000100000000001100001100000000110000100000000011000001000000001100000000000000101111110000000010111110000000001011110100000000101111000000000010111011000000001011101000000000101110010000000010111000000000001011011100000000101101100000000010110101000000001011010000000000101100110000000010110010000000001011000100000000101100000000000010101111000000001010111000000000101011010000000010101100000000001010101100000000101010100000000010101001000000001010100000000000101001110000000010100110000000001010010100000000101001000000000010100011000000001010001000000000101000010000000010100000000000001001111100000000100111100000000010011101000000001001110000000000100110110000000010011010000000001001100100000000100110000000000010010111000000001001011000000000100101010000000010010100000000001001001100000000100100100000000010010001000000001001000000000000100011110000000010001110000000001000110100000000100011000000000010001011000000001000101000000000100010010000000010001000000000001000011100000000100001100000000010000101000000001000010000000000100000110000000010000010000000001000000100000000100000000000000001111111000000000111111000000000011111010000000001111100000000000111101100000000011110100000000001111001000000000111100000000000011101110000000001110110000000000111010100000000011101000000000001110011000000000111001000000000011100010000000001110000000000000110111100000000011011100000000001101101000000000110110000000000011010110000000001101010000000000110100100000000011010000000000001100111000000000110011000000000011001010000000001100100000000000110001100000000011000100000000001100001000000000110000000000000010111110000000001011110000000000101110100000000010111000000000001011011000000000101101000000000010110010000000001011000000000000101011100000000010101100000000001010101000000000101010000000000010100110000000001010010000000000101000100000000010100000000000001001111000000000100111000000000010011010000000001001100000000000100101100000000010010100000000001001001000000000100100000000000010001110000000001000110000000000100010100000000010001000000000001000011000000000100001000000000010000010000000001000000000000000011111100000000001111100000000000111101000000000011110000000000001110110000000000111010000000000011100100000000001110000000000000110111000000000011011000000000001101010000000000110100000000000011001100000000001100100000000000110001000000000011000000000000001011110000000000101110000000000010110100000000001011000000000000101011000000000010101000000000001001100000000000100100000000000000010000000000000000110000000000000000"; + attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of inst : label is "4096'b0000000100100011000000010010001000000001001000010000000100100000000000010001111100000001000111100000000100011101000000010001110000000001000110110000000100011010000000010001100100000001000110000000000100010111000000010001011000000001000101010000000100010100000000010001001100000001000100100000000100010001000000010001000000000001000011110000000100001110000000010000110100000001000011000000000100001011000000010000101000000001000010010000000100001000000000010000011100000001000001100000000100000101000000010000010000000001000000110000000100000010000000010000000100000001000000000000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001001010000000000100011000000000000001100000000000000100000000000000000"; attribute LC_PROBE_OUT_WIDTH_STRING : string; - attribute LC_PROBE_OUT_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000001000111110000000000000010"; + attribute LC_PROBE_OUT_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000001000111110000000000000001"; attribute LC_TOTAL_PROBE_IN_WIDTH : integer; attribute LC_TOTAL_PROBE_IN_WIDTH of inst : label is 0; attribute LC_TOTAL_PROBE_OUT_WIDTH : integer; - attribute LC_TOTAL_PROBE_OUT_WIDTH of inst : label is 42; + attribute LC_TOTAL_PROBE_OUT_WIDTH of inst : label is 41; attribute syn_noprune : string; attribute syn_noprune of inst : label is "1"; begin @@ -12988,7 +12953,7 @@ inst: entity work.vio_manual_ctrl_vio_v3_0_20_vio probe_in97(0) => '0', probe_in98(0) => '0', probe_in99(0) => '0', - probe_out0(2 downto 0) => probe_out0(2 downto 0), + probe_out0(1 downto 0) => probe_out0(1 downto 0), probe_out1(0) => probe_out1(0), probe_out10(0) => NLW_inst_probe_out10_UNCONNECTED(0), probe_out100(0) => NLW_inst_probe_out100_UNCONNECTED(0), diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v index 89b68089..753fedff 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:34:28 2023 +// Date : Tue Mar 21 22:54:43 2023 // Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) // Command : write_verilog -force -mode synth_stub -// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v +// D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v // Design : vio_manual_ctrl // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 @@ -16,9 +16,9 @@ (* X_CORE_INFO = "vio,Vivado 2019.1.3" *) module vio_manual_ctrl(clk, probe_out0, probe_out1, probe_out2, probe_out3, probe_out4) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */; +/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */; input clk; - output [2:0]probe_out0; + output [1:0]probe_out0; output [0:0]probe_out1; output [31:0]probe_out2; output [1:0]probe_out3; diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl index 762f1d28..31ef8c8c 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:34:28 2023 +-- Date : Tue Mar 21 22:54:43 2023 -- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode synth_stub --- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl +-- D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl -- Design : vio_manual_ctrl -- Purpose : Stub declaration of top-level module interface -- Device : xc7k410tffg900-2 @@ -15,7 +15,7 @@ use IEEE.STD_LOGIC_1164.ALL; entity vio_manual_ctrl is Port ( clk : in STD_LOGIC; - probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); @@ -28,7 +28,7 @@ architecture stub of vio_manual_ctrl is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; begin diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.pb b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.pb index fb320ac4..37765f1c 100644 Binary files a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.pb and b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.pb differ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.rpt b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.rpt index 92fc3562..e4db3821 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.rpt +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -| Date : Sat Mar 18 23:34:28 2023 +| Date : Tue Mar 21 22:54:43 2023 | Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) | Command : report_utilization -file vio_manual_ctrl_utilization_synth.rpt -pb vio_manual_ctrl_utilization_synth.pb | Design : vio_manual_ctrl @@ -33,8 +33,8 @@ Table of Contents | Slice LUTs* | 150 | 0 | 254200 | 0.06 | | LUT as Logic | 150 | 0 | 254200 | 0.06 | | LUT as Memory | 0 | 0 | 90600 | 0.00 | -| Slice Registers | 356 | 0 | 508400 | 0.07 | -| Register as Flip Flop | 356 | 0 | 508400 | 0.07 | +| Slice Registers | 354 | 0 | 508400 | 0.07 | +| Register as Flip Flop | 354 | 0 | 508400 | 0.07 | | Register as Latch | 0 | 0 | 508400 | 0.00 | | F7 Muxes | 0 | 0 | 127100 | 0.00 | | F8 Muxes | 0 | 0 | 63550 | 0.00 | @@ -56,8 +56,8 @@ Table of Contents | 0 | Yes | - | - | | 0 | Yes | - | Set | | 0 | Yes | - | Reset | -| 4 | Yes | Set | - | -| 352 | Yes | Reset | - | +| 6 | Yes | Set | - | +| 348 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -151,13 +151,13 @@ Table of Contents +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| FDRE | 352 | Flop & Latch | -| LUT6 | 82 | LUT | -| LUT3 | 59 | LUT | -| LUT5 | 25 | LUT | +| FDRE | 348 | Flop & Latch | +| LUT6 | 81 | LUT | +| LUT3 | 58 | LUT | +| LUT5 | 26 | LUT | | LUT4 | 10 | LUT | | LUT2 | 7 | LUT | -| FDSE | 4 | Flop & Latch | +| FDSE | 6 | Flop & Latch | +----------+------+---------------------+ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vivado.pb b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vivado.pb index 2fe27b6a..1981b29d 100644 Binary files a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vivado.pb and b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vivado.pb differ diff --git a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr index 55bb9ce7..e0cfb10d 100644 --- a/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr +++ b/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr @@ -39,13 +39,13 @@